text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
.*/
#define SPI_MEM_USR_MOSI (BIT(27))
#define SPI_MEM_USR_MOSI_M (BIT(27))
#define SPI_MEM_USR_MOSI_V 0x1
#define SPI_MEM_USR_MOSI_S 27
/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: spi clock is disable in dummy phase when the bit is enable..*/
#define SPI_MEM_USR_DUMMY_IDLE ... | 1,055 |
.*/
#define SPI_MEM_FWRITE_QIO (BIT(15))
#define SPI_MEM_FWRITE_QIO_M (BIT(15))
#define SPI_MEM_FWRITE_QIO_V 0x1
#define SPI_MEM_FWRITE_QIO_S 15
/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: In the write operations address phase and read-data phase apply 2 signals..*/
#define SPI_MEM... | 1,055 |
.*/
#define SPI_MEM_CK_OUT_EDGE (BIT(9))
#define SPI_MEM_CK_OUT_EDGE_M (BIT(9))
#define SPI_MEM_CK_OUT_EDGE_V 0x1
#define SPI_MEM_CK_OUT_EDGE_S 9
/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable..*/
#define SPI_MEM_CS_SE... | 1,055 |
The register value shall be (cy
cle_num-1)..*/
#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F
#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F
#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0
#define SPI_MEM_USER2_REG(i) ... | 1,055 |
The register value shall be (bit_num-1)..*/
#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF
#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF
#define SPI_MEM_USR_MOSI_DBITLEN_S 0
#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI... | 1,055 |
.*/
#define SPI_MEM_STATUS 0x0000FFFF
#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
#define SPI_MEM_STATUS_V 0xFFFF
#define SPI_MEM_STATUS_S 0
#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34)
/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: spi ... | 1,055 |
.*/
#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA (BIT(6))
#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_M (BIT(6))
#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_V 0x1
#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_S 6
/* SPI_MEM_CSPI_ST_TRANS_END : R/W/SS ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to indicate... | 1,055 |
.*/
#define SPI_MEM_TRANS_END (BIT(3))
#define SPI_MEM_TRANS_END_M (BIT(3))
#define SPI_MEM_TRANS_END_V 0x1
#define SPI_MEM_TRANS_END_S 3
/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d
evice, such as flash, e... | 1,055 |
1: enable 0: disable. The bit is
the same with spi_mem_fread_qio..*/
#define SPI_MEM_FADDR_QUAD (BIT(8))
#define SPI_MEM_FADDR_QUAD_M (BIT(8))
#define SPI_MEM_FADDR_QUAD_V 0x1
#define SPI_MEM_FADDR_QUAD_S 8
/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: For SPI0 flash, dout phase ap... | 1,055 |
The bit is
the same with spi_mem_fread_dio..*/
#define SPI_MEM_FADDR_DUAL (BIT(5))
#define SPI_MEM_FADDR_DUAL_M (BIT(5))
#define SPI_MEM_FADDR_DUAL_V 0x1
#define SPI_MEM_FADDR_DUAL_S 5
/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: For SPI0 flash, dout phase apply 2 signals. 1: enab... | 1,055 |
.*/
#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2))
#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2))
#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1
#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2
/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: For SPI0, cache read flash with 4 bytes address, ... | 1,055 |
.*/
#define SPI_MEM_CSPI_LOCK_DELAY_TIME 0x0000001F
#define SPI_MEM_CSPI_LOCK_DELAY_TIME_M ((SPI_MEM_CSPI_LOCK_DELAY_TIME_V)<<(SPI_MEM_CSPI_LOCK_DELAY_TIME_S))
#define SPI_MEM_CSPI_LOCK_DELAY_TIME_V 0x1F
#define SPI_MEM_CSPI_LOCK_DELAY_TIME_S 7
/* SPI_MEM_EM_ST : RO ;bitpos:[6:4] ;default: 3'h0 ; */
/*description... | 1,055 |
.*/
#define SPI_MEM_CSPI_ST 0x0000000F
#define SPI_MEM_CSPI_ST_M ((SPI_MEM_CSPI_ST_V)<<(SPI_MEM_CSPI_ST_S))
#define SPI_MEM_CSPI_ST_V 0xF
#define SPI_MEM_CSPI_ST_S 0
#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58)
/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data bu... | 1,055 |
*/
#define SPI_MEM_BUF3 0xFFFFFFFF
#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
#define SPI_MEM_BUF3_V 0xFFFFFFFF
#define SPI_MEM_BUF3_S 0
#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68)
/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer.*/
#def... | 1,055 |
*/
#define SPI_MEM_BUF7 0xFFFFFFFF
#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
#define SPI_MEM_BUF7_V 0xFFFFFFFF
#define SPI_MEM_BUF7_S 0
#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78)
/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer.*/
#def... | 1,055 |
*/
#define SPI_MEM_BUF11 0xFFFFFFFF
#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
#define SPI_MEM_BUF11_V 0xFFFFFFFF
#define SPI_MEM_BUF11_S 0
#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88)
/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer... | 1,055 |
*/
#define SPI_MEM_BUF15 0xFFFFFFFF
#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
#define SPI_MEM_BUF15_V 0xFFFFFFFF
#define SPI_MEM_BUF15_S 0
#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98)
/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
/... | 1,055 |
*/
#define SPI_MEM_WAITI_DUMMY (BIT(1))
#define SPI_MEM_WAITI_DUMMY_M (BIT(1))
#define SPI_MEM_WAITI_DUMMY_V 0x1
#define SPI_MEM_WAITI_DUMMY_S 1
#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C)
/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
/*description: When SPI... | 1,055 |
0: Only need to check WIP is 0..*/
#define SPI_MEM_PER_END_EN (BIT(23))
#define SPI_MEM_PER_END_EN_M (BIT(23))
#define SPI_MEM_PER_END_EN_V 0x1
#define SPI_MEM_PER_END_EN_S 23
/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status b... | 1,055 |
.*/
#define SPI_MEM_FLASH_PES_EN (BIT(5))
#define SPI_MEM_FLASH_PES_EN_M (BIT(5))
#define SPI_MEM_FLASH_PES_EN_V 0x1
#define SPI_MEM_FLASH_PES_EN_S 5
/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
pplicati... | 1,055 |
0: SPI1 does not wait after program erase
resume command is sent..*/
#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2))
#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2))
#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1
#define SPI_MEM_FLASH_PER_WAIT_EN_S 2
/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
/*description: p... | 1,055 |
The command should be sent when SUS
/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash
..*/
#define SPI_MEM_WAIT_PESR_COMMAND 0x0000FFFF
#define SPI_MEM_WAIT_PESR_COMMAND_M ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
#define SPI_MEM_WAIT_PESR_COMMAND_V 0xFFFF
#defi... | 1,055 |
0: Disable it..*/
#define SPI_MEM_SPI0_LOCK_EN (BIT(7))
#define SPI_MEM_SPI0_LOCK_EN_M (BIT(7))
#define SPI_MEM_SPI0_LOCK_EN_V 0x1
#define SPI_MEM_SPI0_LOCK_EN_S 7
/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_C... | 1,055 |
0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
after DP command is sent..*/
#define SPI_MEM_FLASH_DP_DLY_128 (BIT(4))
#define SPI_MEM_FLASH_DP_DLY_128_M (BIT(4))
#define SPI_MEM_FLASH_DP_DLY_128_V 0x1
#define SPI_MEM_FLASH_DP_DLY_128_S 4
/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default:... | 1,055 |
0:
SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/
#define SPI_MEM_WAIT_PESR_CMD_2B (BIT(1))
#define SPI_MEM_WAIT_PESR_CMD_2B_M (BIT(1))
#define SPI_MEM_WAIT_PESR_CMD_2B_V 0x1
#define SPI_MEM_WAIT_PESR_CMD_2B_S 1
/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
/*des... | 1,055 |
.*/
#define SPI_MEM_TIMING_CALI (BIT(1))
#define SPI_MEM_TIMING_CALI_M (BIT(1))
#define SPI_MEM_TIMING_CALI_V 0x1
#define SPI_MEM_TIMING_CALI_S 1
/* SPI_MEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to enable timing adjust clock for all reading operations..*/
#define SPI_... | 1,055 |
*/
#define SPI_MEM_DIN2_MODE 0x00000003
#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
#define SPI_MEM_DIN2_MODE_V 0x3
#define SPI_MEM_DIN2_MODE_S 4
/* SPI_MEM_DIN1_MODE : HRO ;bitpos:[3:2] ;default: 2'h0 ; */
/*description: the input signals are delayed by system clock cycles, 0: inpu... | 1,055 |
*/
#define SPI_MEM_DIN0_MODE 0x00000003
#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
#define SPI_MEM_DIN0_MODE_V 0x3
#define SPI_MEM_DIN0_MODE_S 0
#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0xB0)
/* SPI_MEM_DIN3_NUM : HRO ;bitpos:[3] ;default: 1'h0 ; */
/*descrip... | 1,055 |
...*/
#define SPI_MEM_DIN1_NUM (BIT(1))
#define SPI_MEM_DIN1_NUM_M (BIT(1))
#define SPI_MEM_DIN1_NUM_V 0x1
#define SPI_MEM_DIN1_NUM_S 1
/* SPI_MEM_DIN0_NUM : HRO ;bitpos:[0] ;default: 1'h0 ; */
/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
delayed by 2 cycles,....*... | 1,055 |
*/
#define SPI_MEM_DOUT2_MODE (BIT(2))
#define SPI_MEM_DOUT2_MODE_M (BIT(2))
#define SPI_MEM_DOUT2_MODE_V 0x1
#define SPI_MEM_DOUT2_MODE_S 2
/* SPI_MEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */
/*description: the output signals are delayed by system clock cycles, 0: output without delayed
, 1: output with ... | 1,055 |
*/
#define SPI_MEM_DOUT0_MODE (BIT(0))
#define SPI_MEM_DOUT0_MODE_M (BIT(0))
#define SPI_MEM_DOUT0_MODE_V 0x1
#define SPI_MEM_DOUT0_MODE_S 0
#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0)
/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The enable bit for SP... | 1,055 |
.*/
#define SPI_MEM_WPE_END_INT_ENA (BIT(2))
#define SPI_MEM_WPE_END_INT_ENA_M (BIT(2))
#define SPI_MEM_WPE_END_INT_ENA_V 0x1
#define SPI_MEM_WPE_END_INT_ENA_S 2
/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
#define SPI_MEM_PES... | 1,055 |
.*/
#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4))
#define SPI_MEM_MST_ST_END_INT_CLR_M (BIT(4))
#define SPI_MEM_MST_ST_END_INT_CLR_V 0x1
#define SPI_MEM_MST_ST_END_INT_CLR_S 4
/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
#de... | 1,055 |
.*/
#define SPI_MEM_PER_END_INT_CLR (BIT(0))
#define SPI_MEM_PER_END_INT_CLR_M (BIT(0))
#define SPI_MEM_PER_END_INT_CLR_V 0x1
#define SPI_MEM_PER_END_INT_CLR_S 0
#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8)
/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
/*descript... | 1,055 |
.*/
#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4))
#define SPI_MEM_MST_ST_END_INT_RAW_M (BIT(4))
#define SPI_MEM_MST_ST_END_INT_RAW_V 0x1
#define SPI_MEM_MST_ST_END_INT_RAW_S 4
/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1:... | 1,055 |
1: Triggered when Auto Suspend com
mand (0x75) is sent and flash is suspended. 0: Others..*/
#define SPI_MEM_PES_END_INT_RAW (BIT(1))
#define SPI_MEM_PES_END_INT_RAW_M (BIT(1))
#define SPI_MEM_PES_END_INT_RAW_V 0x1
#define SPI_MEM_PES_END_INT_RAW_S 1
/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b... | 1,055 |
.*/
#define SPI_MEM_MST_ST_END_INT_ST (BIT(4))
#define SPI_MEM_MST_ST_END_INT_ST_M (BIT(4))
#define SPI_MEM_MST_ST_END_INT_ST_V 0x1
#define SPI_MEM_MST_ST_END_INT_ST_S 4
/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
#define... | 1,055 |
.*/
#define SPI_MEM_PER_END_INT_ST (BIT(0))
#define SPI_MEM_PER_END_INT_ST_M (BIT(0))
#define SPI_MEM_PER_END_INT_ST_V 0x1
#define SPI_MEM_PER_END_INT_ST_S 0
#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0xDC)
/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Register clo... | 1,055 |
1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (c
lk) 160MHz. 3: Not used..*/
#define SPI_MEM_SPI01_CLK_SEL 0x00000003
#define SPI_MEM_SPI01_CLK_SEL_M ((SPI_MEM_SPI01_CLK_SEL_V)<<(SPI_MEM_SPI01_CLK_SEL_S))
#define SPI_MEM_SPI01_CLK_SEL_V 0x3
#define SPI_MEM_SPI01_CLK_SEL_S 0
#define SPI_MEM_DATE... | 1,055 |
/*
*/
#pragma once
#define ADC1_GPIO0_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 0
#define ADC1_GPIO1_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 1
#define ADC1_GPIO2_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 2
#define ADC1_GPIO3_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 3
#define ADC1_GPIO4_CHA... | 1,057 |
/*
*/
/*
*/
#pragma once
/* COMMON CAPS */
#define SOC_ADC_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
#define SOC_BT_SUPPO... | 1,059 |
> 3)
#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
/* RTCIO CAPS */
/* No dedicated RTCIO subsystem on ESP32-C2. RTC functions are still supported
#d... | 1,059 |
5
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/* TIMER GROUP CAPS */
#define SOC_TIMER_GROUPS (1U)
#define SOC_TIMER_GROUP_T... | 1,059 |
< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_SUPPORT_PLL_F40M_CLK (1) /*!< Support APB as the clock source */
#define SOC_UART_SUPPORT_RTC_... | 1,059 |
< ESP32C2 only supports to connect an external oscillator, not a crystal */
/* WI-FI CAPS */
#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
#define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */
#define SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW (1) /*!< S... | 1,059 |
< Support For BLE Periodic Adv Enhancements */
/* PHY CAPS */
#define SOC_PHY_IMPROVE_RX_11B (1)
#define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi and BLE*/
| 1,059 |
Clear vld before set reg_ck8m_div_sel*/
uint32_t ck8m_div : 2; /*CK8M_D256_OUT divider. 00: div128*/
uint32_t enb_ck8m : 1; /*disable CK8M and CK8M_D256_OUT*/
uint32_t enb_ck8m_div : 1; /*1: CK8M_D256_OUT is actu... | 1,060 |
0: XTAL div 2*/
uint32_t ana_clk_rtc_sel : 2; /*Need add desc*/
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t reserved0 : 22; /*Reserved*/
uint32_t rtc_ana_clk_div_vld : 1; /*used to syn... | 1,060 |
8v or lower )*/
uint32_t rtculator_force_pu : 1; /*Need add desc*/
};
uint32_t val;
} rtc;
union {
struct {
uint32_t reserved0 : 21; /*Reserved*/
uint32_t rtc_pad_force_hold : 1; /*rtc pad force hol... | 1,060 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of rom_table_lock register
*/
typedef union {
struct {
/** rom_table_lock : R/W; bitpos: [0]; default: 0;
*/
uint32_t rom_table_lock:1;
uint32_t reserved_1:31;
... | 1,061 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct spi_mem_dev_s{
union {
struct {
uint32_t mst_st : 4; /*The current status of SPI1 master FSM.*/
uint32_t slv_st : 4; /*The current sta... | 1,062 |
The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_res : 1; /*This bit... | 1,062 |
Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the o... | 1,062 |
1: enable 0: disable. */
uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
uint32_t flash_wrdi : 1; /*Write flash disable. Write disa... | 1,062 |
*/
uint32_t reserved4 : 3; /*reserved*/
uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
... | 1,062 |
1: enable 0: disable. */
uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
uint32_t reserved16 : 2; /*reserved*/
uint32_t q_pol ... | 1,062 |
1: enable 0: disable. */
uint32_t fread_qio : 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
uint32_t reserved25 : 7; /*reserved*/
};
uint32_t val;
} ctrl;
union {
... | 1,062 |
*/
uint32_t cs_hold_time : 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t reserved10 : 15; /*reserved*/
uint32_t cs_hold_delay : 6; /*These bits are use... | 1,062 |
So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24 : 7; /*In the master mode it is pre-divider of spi_mem_clk. */
uint32_t clk_equ_sysclk : 1; /*Set this bit in 1-division mode.*/
};
uint32_t val;
} clock;
... | 1,062 |
*/
uint32_t fwrite_qio : 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_t reserved16 : 8; /*reserved*/
uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of... | 1,062 |
*/
uint32_t usr_addr : 1; /*This bit enable the address phase of an operation.*/
uint32_t usr_command : 1; /*This bit enable the command phase of an operation.*/
};
uint32_t val;
} user;
union {
struct {
u... | 1,062 |
The register value shall be (bit_num-1)*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_bit_len : 10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved10 : 22; /... | 1,062 |
*/
uint32_t cs1_dis : 1; /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
uint32_t reserved0 : 1; /*reserved*/
uint32_t mst_st_trans_end : ... | 1,062 |
*/
uint32_t reserved11 : 21; /*reserved*/
};
uint32_t val;
} misc;
uint32_t tx_crc;
union {
struct {
uint32_t req_en : 1; /*For SPI0, Cache access enable, 1: enable, 0:disable.*/
uint32_t usr_addr_4... | 1,062 |
1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t fdin_quad : 1; /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t fdout_quad : 1; /*For SPI0 flash... | 1,062 |
*/
uint32_t spi0_mst_st : 3; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
uint32_t cspi_lo... | 1,062 |
*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} flash_waiti_ctrl;
union {
struct {
uint32_t flash_per : 1; /*program erase resume bit, program erase suspend operation will be triggered when the bit is set... | 1,062 |
0: SPI1 does not wait after program erase suspend command is sent. */
uint32_t pes_per_en : 1; /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
uint32_t flash_pes_en : 1; ... | 1,062 |
0: Only need to check WIP is 0.*/
uint32_t pes_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
uint32_t sus_timeout_cnt : 7; /*When SPI1 checks SUS/SUS1/SUS2 bits... | 1,062 |
*/
uint32_t wait_pesr_cmd_2b : 1; /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
uint32_t flash_hpm_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY... | 1,062 |
1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
uint32_t flash_pes_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_C... | 1,062 |
*/
uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} timing_cali;
union {
struct {
uint32_t din0_mode ... | 1,062 |
..*/
uint32_t din1_num : 1; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t din2_num : 1; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delay... | 1,062 |
*/
uint32_t pes_end_en : 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t wpe_end_en : 1; /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
uint32_t slv_st_end_en : 1; /*The enable bit for SPI_MEM_... | 1,062 |
*/
uint32_t slv_st_end : 1; /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
uint32_t mst_st_end : 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
uint32_t brown_out : 1; /*The status bit for SPI_... | 1,062 |
1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
uint32_t slv_st_end : 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
... | 1,062 |
*/
uint32_t pes_end : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t wpe_end : 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
uint32_t slv_st_end : 1; /*The status bit for SPI_MEM_... | 1,062 |
1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (cl... | 1,062 |
*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} date;
} spi_mem_dev_t;
extern spi_mem_dev_t SPIMEM0;
extern spi_mem_dev_t SPIMEM1;
#ifndef __cplusplus
_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
#endif
#ifdef __cpluspl... | 1,062 |
/*
*/
#ifndef _DPORT_ACCESS_H_
#define _DPORT_ACCESS_H_
#include
#include "soc.h"
#include "uart_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
*/
voi... | 1,063 |
/*
*/
#pragma once
#include "soc.h"
/* Hardware random number generator register */
#define WDEV_RND_REG 0x600260b0
| 1,064 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct uart_dev_s {
union {
struct {
uint32_t rw_byte : 32; /*UART $n accesses FIFO via this register.*/
};
uint32_t val;
} ahb_fifo;
union {
struct ... | 1,066 |
*/
uint32_t dsr_chg : 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
uint32_t cts_chg : 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signa... | 1,066 |
*/
uint32_t glitch_det : 1; /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
uint32_t tx_brk_done : 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL ch... | 1,066 |
*/
uint32_t rs485_clash : 1; /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/
uint32_t at_cmd_char_det : 1; /*This interrupt raw bit turns to high level when receiver detects the configured... | 1,066 |
*/
uint32_t frm_err : 1; /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
uint32_t rxfifo_ovf : 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
uint32_t dsr_chg ... | 1,066 |
*/
uint32_t glitch_det : 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
uint32_t tx_brk_done : 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
uint32_t ... | 1,066 |
*/
uint32_t at_cmd_char_det : 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
uint32_t wakeup : 1; /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
uint... | 1,066 |
*/
uint32_t dsr_chg : 1; /*This is the enable bit for dsr_chg_int_st register.*/
uint32_t cts_chg : 1; /*This is the enable bit for cts_chg_int_st register.*/
uint32_t brk_det : 1; /*This is the enable bit ... | 1,066 |
*/
uint32_t tx_done : 1; /*This is the enable bit for tx_done_int_st register.*/
uint32_t rs485_parity_err : 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_frm_err : 1; /*This is the en... | 1,066 |
*/
uint32_t txfifo_empty : 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
uint32_t parity_err : 1; /*Set this bit to clear parity_err_int_raw interrupt.*/
uint32_t frm_err : 1; /*Set this bit to clear... | 1,066 |
*/
uint32_t sw_xoff : 1; /*Set this bit to clear the sw_xoff_int_raw interrupt.*/
uint32_t glitch_det : 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/
uint32_t tx_brk_done : 1; /*Set this bit to cl... | 1,066 |
*/
uint32_t wakeup : 1; /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/
uint32_t reserved20 : 12; /*Reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t div_int ... | 1,066 |
*/
uint32_t reserved10 : 3;
uint32_t dsrn : 1; /*The register represent the level value of the internal uart dsr signal.*/
uint32_t ctsn : 1; /*This register represent the level value of the internal uart... | 1,066 |
*/
};
uint32_t val;
} status;
union {
struct {
uint32_t parity : 1; /*This register is used to configure the parity check mode.*/
uint32_t parity_en : 1; /*Set this bit to enable uart parity check.*/
u... | 1,066 |
*/
uint32_t irda_dplx : 1; /*Set this bit to enable IrDA loopback mode.*/
uint32_t irda_tx_en : 1; /*This is the start enable bit for IrDA transmitter.*/
uint32_t irda_wctl : 1; /*1'h1: The IrDA transmitter's 11th... | 1,066 |
*/
uint32_t txfifo_rst : 1; /*Set this bit to reset the uart transmit-FIFO.*/
uint32_t rxd_inv : 1; /*Set this bit to inverse the level value of uart rxd signal.*/
uint32_t cts_inv : 1; /*Set this bit to inver... | 1,066 |
*/
uint32_t err_wr_mask : 1; /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.*/
uint32_t autobaud_en : 1; /*This is the enable bit for detecting baudrate.*/
... | 1,066 |
*/
uint32_t rx_flow_en : 1; /*This is the flow enable bit for UART receiver.*/
uint32_t rx_tout_en : 1; /*This is the enble bit for uart receiver's timeout function.*/
uint32_t reserved22 : 10;
};
uin... | 1,066 |
It is used in baud rate-detect process.*/
uint32_t reserved10 : 22; /*Reserved*/
};
uint32_t val;
} rxd_cnt;
union {
struct {
uint32_t sw_flow_con_en : 1; /*Set this bit to enable software flow control. It is used with re... | 1,066 |
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