text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
uint32_t reserved10 : 22; /*Reserved*/
};
uint32_t val;
} sleep_conf;
union {
struct {
uint32_t xoff_threshold : 9; /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, i... | 1,066 |
It is active when txd_brk is set to 1.*/
uint32_t reserved8 : 24;
};
uint32_t val;
} txbrk_conf;
union {
struct {
uint32_t rx_idle_thrhd : 10; /*It will produce frame end signal when receiver takes more time to receive o... | 1,066 |
*/
uint32_t rx_busy_tx_en : 1; /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. */
uint32_t rx_dly_num : 1; /*This register is used to delay the receiver's internal data signal.*/
uint32_t tx_dly_num ... | 1,066 |
*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} at_cmd_postcnt;
union {
struct {
uint32_t rx_gap_tout : 16; /*This register is used to configure the duration time between the at_cmd chars.*/
uin... | 1,066 |
The default number is 128 bytes.*/
uint32_t tx_size : 3; /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/
uint32_t rx_flow_thrhd : 9; /*This register is used to configure the maxi... | 1,066 |
*/
uint32_t reserved10 : 1; /*Reserved*/
uint32_t tx_raddr : 10; /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/
uint32_t reserved21 : 11; /*Reserved*/
};
... | 1,066 |
*/
uint32_t st_utx_out : 4; /*This is the status register of transmitter.*/
uint32_t reserved8 : 24; /*Reserved*/
};
uint32_t val;
} fsm_status;
union {
struct {
uint32_t min_cnt : ... | 1,066 |
*/
uint32_t sclk_div_a : 6; /*The numerator of the frequency divider factor.*/
uint32_t sclk_div_num : 8; /*The integral part of the frequency divider factor.*/
uint32_t sclk_sel : 2; /*UART clock source select. 1: ... | 1,066 |
*/
uint32_t high_speed : 1; /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */... | 1,066 |
/*
*/
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C2.
#ifndef _SOC_UART_CHANNEL_H
#define _SOC_UART_CHANNEL_H
//UART channels
#define UART_GPIO20_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 20
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0
#define UA... | 1,067 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Configuration Register */
/** Type of conf register
*/
typedef union {
struct {
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
*/
uint32_t systimer_clk_fo: 1;
uint32_t reserved_1: 21;
/** targe... | 1,068 |
/*
*/
#pragma once
#include "interrupt_core0_reg.h"
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG
#define INTERRUPT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
| 1,069 |
/*
*/
#pragma once
/**
*/
#define I2C_BIAS 0X6A
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS_DREG_1P1_PVT 1
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
#define I2C_BIAS_DREG_1P1_PVT_LSB 0
| 1,071 |
/*
*/
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 19
#define U0TXD_GPIO_NUM 20
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U1RXD_GP... | 1,072 |
/*
*/
#pragma once
/**
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_IR_FORCE_XPD_CK 0
#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2
#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2
#define I2C_ULP_IR_FORCE_XPD_IPH 0
#de... | 1,073 |
/**
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
*/
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [0]; default: 0;
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL... | 1,074 |
/*
*/
#ifndef _SOC_SPI_STRUCT_H_
#define _SOC_SPI_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct spi_dev_s{
union {
struct {
uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state... | 1,075 |
1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.*/
uint32_t reserved4 : 1; /*reserved*/
uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
... | 1,075 |
Can be configured in CONF state.*/
uint32_t reserved11 : 3; /*reserved*/
uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t fread_quad ... | 1,075 |
*/
uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be c... | 1,075 |
Can be configured in CONF state.*/
uint32_t clkcnt_h : 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
uint32_t clkcnt_n : 6; /*In the master mode it is the divid... | 1,075 |
1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved1 : 2; /*reserved*/
uint32_t qpi_mode : 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
... | 1,075 |
0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
uint32_t ck_out_edge : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
uint32_t reserved10 : 2; /*reserved*/
uint32_t fwrite_d... | 1,075 |
*/
uint32_t reserved16 : 1; /*reserved*/
uint32_t sio : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserve... | 1,075 |
Can be configured in CONF state.*/
uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation. Can be configured in CO... | 1,075 |
0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
uint32_t cs_setup_time : 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
uint32_t cs_hold_time ... | 1,075 |
0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
};
uint32_t val;
} u... | 1,075 |
Can be configured in CONF state.*/
uint32_t cs1_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs2_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs... | 1,075 |
Can be configured in CONF state.*/
uint32_t master_cs_pol : 6; /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
uint32_t reserved13 : 3; /*reserved*... | 1,075 |
Can be configured in CONF state.*/
uint32_t cmd_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/
uint32_t reserved20 ... | 1,075 |
*/
uint32_t quad_din_pin_swap : 1; /*1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state.*/
};
uint32_t val;
} misc;
union {
struct {
uint32_t din0_mode ... | 1,075 |
Can be configured in CONF state.*/
uint32_t din3_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
... | 1,075 |
Can be configured in CONF state.*/
uint32_t din7_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
... | 1,075 |
Can be configured in CONF state.*/
uint32_t din2_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din3_num : 2; /*the input signa... | 1,075 |
.. Can be configured in CONF state.*/
uint32_t din7_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t reserved16 : 16; /*reserved*/
... | 1,075 |
Can be configured in CONF state.*/
uint32_t dout3_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout4_mode ... | 1,075 |
*/
uint32_t dout7_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t d_dqs_mode : 1; /*The out... | 1,075 |
*/
uint32_t reserved2 : 16; /*reserved*/
uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared ... | 1,075 |
*/
uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/
uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
uint32_t buf_afifo... | 1,075 |
*/
uint32_t en_qpi : 1; /*The enable bit for SPI slave En_QPI interrupt.*/
uint32_t cmd7 : 1; /*The enable bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8 : 1; /*The enable bit for SPI slave CMD8 i... | 1,075 |
*/
uint32_t trans_done : 1; /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
uint32_t dma_seg_trans_done : 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
uint32_t seg_magic_err : 1; /*The enable bit for SP... | 1,075 |
*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_ena;
union {
struct {
uint32_t infifo_full_err : 1; /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
uint32_t outfifo_empty_err ... | 1,075 |
*/
uint32_t rd_dma_done : 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
uint32_t wr_dma_done : 1; /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
uint32_t rd_buf_done : 1; /*The clear bit for SPI... | 1,075 |
*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
uint32_t mst_tx_afifo_rempty_err : 1; /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
uint32_t app2 : 1; /*The cl... | 1,075 |
1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
uint32_t en_qpi : 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
uint32_t cmd7 : 1; /*The raw bit for SPI slave CMD... | 1,075 |
0: Others.*/
uint32_t wr_dma_done : 1; /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
uint32_t rd_buf_done : 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode R... | 1,075 |
*/
uint32_t seg_magic_err : 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
uint32_t buf_addr_err : 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The a... | 1,075 |
0: Others.*/
uint32_t app2 : 1; /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/
uint32_t app1 : 1; /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/
ui... | 1,075 |
*/
uint32_t cmd8 : 1; /*The status bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9 : 1; /*The status bit for SPI slave CMD9 interrupt.*/
uint32_t cmda : 1; /*The status bit for SPI slave CMDA int... | 1,075 |
*/
uint32_t seg_magic_err : 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
uint32_t buf_addr_err : 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err : 1; /*The status bit for S... | 1,075 |
*/
uint32_t outfifo_empty_err_int_set : 1; /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
uint32_t ex_qpi_int_set : 1; /*The software set bit for SPI slave Ex_QPI interrupt.*/
uint32_t en_qpi_int_set : 1; /*The soft... | 1,075 |
*/
uint32_t rd_buf_done_int_set : 1; /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
uint32_t wr_buf_done_int_set : 1; /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
uint32_t trans_done_int_set : 1; /*The sof... | 1,075 |
*/
uint32_t app2_int_set : 1; /*The software set bit for SPI_APP2_INT interrupt.*/
uint32_t app1_int_set : 1; /*The software set bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
... | 1,075 |
0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first e... | 1,075 |
0: others*/
uint32_t rdbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
uint32_t wrbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-writ... | 1,075 |
0: This is not seg-trans mode.*/
uint32_t reserved29 : 3; /*reserved*/
};
uint32_t val;
} slave;
union {
struct {
uint32_t data_bitlen : 18; /*The transferred data bit length in SPI slave FD and HD mode. */
... | 1,075 |
*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} date;
} spi_dev_t;
extern spi_dev_t GPSPI2;
extern spi_dev_t GPSPI3;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SPI_STRUCT_H_ */
| 1,075 |
/**
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#ifdef __cplusplus
}
#endif
| 1,076 |
/*
*/
#ifndef _SOC_SPI_PINS_H_
#define _SOC_SPI_PINS_H_
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_HD 12
#define SPI_IOMUX_PIN_NUM_CS 14
#define SPI_IOMUX_PIN_NUM_MOSI 16
#define SPI_IOMUX_PIN_NUM_CLK 15
#define SPI_IOMUX_PIN_NUM_MISO 17
#define SPI_IOMUX_PIN_NUM_WP 13
#define SPI2_FUN... | 1,077 |
/*
*/
#pragma once
/**
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 0
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_C... | 1,078 |
/*
*/
/*
*/
#pragma once
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"
| 1,079 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** XTS_AES_PLAIN_MEM register
*/
#define XTS_AES_PLAIN_MEM (DR_REG_XTS_AES_BASE + 0x0)
#define XTS_AES_PLAIN_MEM_SIZE_BYTES 16
/** XTS_AES_LINESIZE_REG register
*/
#define XTS_AES_LINESIZE_REG (DR_REG_XTS_AES_BASE + 0x40)
/... | 1,080 |
/*
*/
#pragma once
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xC)
/* ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt.*/
#define ECC_MULT_C... | 1,081 |
*/
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x1
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
/* ECC_MULT_CALC_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*des... | 1,081 |
*/
#define ECC_MULT_CLK_EN (BIT(4))
#define ECC_MULT_CLK_EN_M (BIT(4))
#define ECC_MULT_CLK_EN_V 0x1
#define ECC_MULT_CLK_EN_S 4
/* ECC_MULT_SECURITY_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to enable slave receiver mode.*/
#define ECC_MULT_SECURITY_MODE (BIT(3))
#define ECC_MULT_... | 1,081 |
*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (BIT(0))
#define ECC_MULT_START_V 0x1
#define ECC_MULT_START_S 0
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xFC)
/* ECC_MULT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012230 ; */
/*description: ECC mult version control register.*/
#defin... | 1,081 |
*/
#define ECC_MULT_MEM_K_3 0xFFFFFFFF
#define ECC_MULT_MEM_K_3_M ((ECC_MULT_MEM_K_3_V)<<(ECC_MULT_MEM_K_3_S))
#define ECC_MULT_MEM_K_3_V 0xFFFFFFFF
#define ECC_MULT_MEM_K_3_S 0
#define ECC_MULT_K_4_REG (DR_REG_ECC_MULT_BASE + 0x010c)
/* ECC_MULT_MEM_K_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*descrip... | 1,081 |
*/
#define ECC_MULT_MEM_K_6 0xFFFFFFFF
#define ECC_MULT_MEM_K_6_M ((ECC_MULT_MEM_K_6_V)<<(ECC_MULT_MEM_K_6_S))
#define ECC_MULT_MEM_K_6_V 0xFFFFFFFF
#define ECC_MULT_MEM_K_6_S 0
#define ECC_MULT_K_7_REG (DR_REG_ECC_MULT_BASE + 0x0118)
/* ECC_MULT_MEM_K_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*descrip... | 1,081 |
*/
#define ECC_MULT_MEM_PX_1 0xFFFFFFFF
#define ECC_MULT_MEM_PX_1_M ((ECC_MULT_MEM_PX_1_V)<<(ECC_MULT_MEM_PX_1_S))
#define ECC_MULT_MEM_PX_1_V 0xFFFFFFFF
#define ECC_MULT_MEM_PX_1_S 0
#define ECC_MULT_PX_2_REG (DR_REG_ECC_MULT_BASE + 0x0124)
/* ECC_MULT_MEM_PX_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/... | 1,081 |
*/
#define ECC_MULT_MEM_PX_4 0xFFFFFFFF
#define ECC_MULT_MEM_PX_4_M ((ECC_MULT_MEM_PX_4_V)<<(ECC_MULT_MEM_PX_4_S))
#define ECC_MULT_MEM_PX_4_V 0xFFFFFFFF
#define ECC_MULT_MEM_PX_4_S 0
#define ECC_MULT_PX_5_REG (DR_REG_ECC_MULT_BASE + 0x0130)
/* ECC_MULT_MEM_PX_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/... | 1,081 |
*/
#define ECC_MULT_MEM_PX_7 0xFFFFFFFF
#define ECC_MULT_MEM_PX_7_M ((ECC_MULT_MEM_PX_7_V)<<(ECC_MULT_MEM_PX_7_S))
#define ECC_MULT_MEM_PX_7_V 0xFFFFFFFF
#define ECC_MULT_MEM_PX_7_S 0
#define ECC_MULT_PX_8_REG (DR_REG_ECC_MULT_BASE + 0x013c)
/* ECC_MULT_MEM_PX_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/... | 1,081 |
*/
#define ECC_MULT_MEM_PY_2 0xFFFFFFFF
#define ECC_MULT_MEM_PY_2_M ((ECC_MULT_MEM_PY_2_V)<<(ECC_MULT_MEM_PY_2_S))
#define ECC_MULT_MEM_PY_2_V 0xFFFFFFFF
#define ECC_MULT_MEM_PY_2_S 0
#define ECC_MULT_PY_3_REG (DR_REG_ECC_MULT_BASE + 0x0148)
/* ECC_MULT_MEM_PY_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/... | 1,081 |
*/
#define ECC_MULT_MEM_PY_5 0xFFFFFFFF
#define ECC_MULT_MEM_PY_5_M ((ECC_MULT_MEM_PY_5_V)<<(ECC_MULT_MEM_PY_5_S))
#define ECC_MULT_MEM_PY_5_V 0xFFFFFFFF
#define ECC_MULT_MEM_PY_5_S 0
#define ECC_MULT_PY_6_REG (DR_REG_ECC_MULT_BASE + 0x0154)
/* ECC_MULT_MEM_PY_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/... | 1,081 |
*/
#define ECC_MULT_MEM_PY_8 0xFFFFFFFF
#define ECC_MULT_MEM_PY_8_M ((ECC_MULT_MEM_PY_8_V)<<(ECC_MULT_MEM_PY_8_S))
#define ECC_MULT_MEM_PY_8_V 0xFFFFFFFF
#define ECC_MULT_MEM_PY_8_S 0
#ifdef __cplusplus
}
#endif
| 1,081 |
/*
*/
#pragma once
/* Some of the baseband control registers.
*/
#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
#define BB_FFT_FORCE_PU (BIT(3))
#define BB_FFT_FORCE_PU_M (BIT(3))
#define BB_FFT_FORCE_PU_V 1
#define BB_FFT_FORCE_PU_S 3
#define BB_FFT_FORCE_PD (BIT(2))
#define BB_FFT_FORCE_PD_M (BIT(2))
#define BB_FFT... | 1,082 |
/*
*/
#pragma once
#include "soc/soc.h"
/* Some of the RF frontend control registers.
*/
#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
#define FE_IQ_EST_FORCE_PU (BIT(5))
#define FE_IQ_EST_FORCE_PU_M (BIT(5))
#define FE_IQ_EST_FORCE_PU_V 1
#define FE_IQ_EST_FORCE_PU_S 5
#define FE_IQ_EST_FORCE_PD (BIT(4))
#define... | 1,083 |
/*
*/
#ifndef _SOC_RTC_CNTL_REG_H_
#define _SOC_RTC_CNTL_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG
#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG
#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0)
/* RTC_CNTL_SW_SYS_RST : ;... | 1,084 |
*/
#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28))
#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1
#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28
/* RTC_CNTL_ANALOG_FORCE_ISO : ;bitpos:[25] ;default: 1'd0 ; */
/*description: Need add desc.*/
#define RTC_CNTL_ANALOG_FORCE_ISO ... | 1,084 |
*/
#define RTC_CNTL_XTL_FORCE_PU (BIT(13))
#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13))
#define RTC_CNTL_XTL_FORCE_PU_V 0x1
#define RTC_CNTL_XTL_FORCE_PU_S 13
/* RTC_CNTL_XTL_FORCE_PD : ;bitpos:[12] ;default: 1'b0 ; */
/*description: crystall force power down.*/
#define RTC_CNTL_XTL_FORCE_PD (BIT(12))
#define RT... | 1,084 |
*/
#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9))
#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9))
#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1
#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9
/* RTC_CNTL_BBPLL_I2C_FORCE_PD : ;bitpos:[8] ;default: 1'b0 ; */
/*description: BB_PLL _I2C force power down.*/
#define RTC_CNTL_BBPLL_I... | 1,084 |
*/
#define RTC_CNTL_SW_PROCPU_RST (BIT(5))
#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5))
#define RTC_CNTL_SW_PROCPU_RST_V 0x1
#define RTC_CNTL_SW_PROCPU_RST_S 5
/* RTC_CNTL_SW_STALL_PROCPU_C0 : ;bitpos:[3:2] ;default: 2'b0 ; */
/*description: {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will s... | 1,084 |
*/
#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16))
#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16))
#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1
#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16
/* RTC_CNTL_SLP_VAL_HI : ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: RTC sleep timer high 16 bits.*/
#define RTC_CNTL_SLP_... | 1,084 |
*/
#define RTC_CNTL_TIMER_XTL_OFF (BIT(28))
#define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28))
#define RTC_CNTL_TIMER_XTL_OFF_V 0x1
#define RTC_CNTL_TIMER_XTL_OFF_S 28
/* RTC_CNTL_TIMER_SYS_STALL : ;bitpos:[27] ;default: 1'b0 ; */
/*description: Enable to record system stall time.*/
#define RTC_CNTL_TIMER_SYS_STALL (... | 1,084 |
*/
#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF
#define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S))
#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF
#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0
#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18)
/* RTC_CNTL_S... | 1,084 |
*/
#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28))
#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28))
#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1
#define RTC_CNTL_SDIO_ACTIVE_IND_S 28
/* RTC_CNTL_APB2RTC_BRIDGE_SEL : ;bitpos:[22] ;default: 1'd0 ; */
/*description: 1: APB to RTC using bridge.*/
#define RTC_CNTL_APB2RTC_BRIDGE_SE... | 1,084 |
*/
#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF
#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF
#define RTC_CNTL_PLL_BUF_WAIT_S 24
/* RTC_CNTL_XTL_BUF_WAIT : ;bitpos:[23:14] ;default: 10'd80 ; */
/*description: XTAL wait cycles in slow_clk_r... | 1,084 |
*/
#define RTC_CNTL_CPU_STALL_EN (BIT(0))
#define RTC_CNTL_CPU_STALL_EN_M (BIT(0))
#define RTC_CNTL_CPU_STALL_EN_V 0x1
#define RTC_CNTL_CPU_STALL_EN_S 0
#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20)
/* RTC_CNTL_MIN_TIME_CK8M_OFF : ;bitpos:[31:24] ;default: 8'h1 ; */
/*description: minimal cy... | 1,084 |
*/
#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF
#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF
#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16
#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x28)
/* RTC_... | 1,084 |
*/
#define RTC_CNTL_CKGEN_I2C_PU (BIT(30))
#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30))
#define RTC_CNTL_CKGEN_I2C_PU_V 0x1
#define RTC_CNTL_CKGEN_I2C_PU_S 30
/* RTC_CNTL_RFRX_PBUS_PU : ;bitpos:[28] ;default: 1'd0 ; */
/*description: 1: RFRX_PBUS power up.*/
#define RTC_CNTL_RFRX_PBUS_PU (BIT(28))
#define RTC_CN... | 1,084 |
*/
#define RTC_CNTL_SAR_I2C_PU (BIT(22))
#define RTC_CNTL_SAR_I2C_PU_M (BIT(22))
#define RTC_CNTL_SAR_I2C_PU_V 0x1
#define RTC_CNTL_SAR_I2C_PU_S 22
/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : ;bitpos:[19] ;default: 1'b0 ; */
/*description: Need add desc.*/
#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19))
#define RT... | 1,084 |
*/
#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU (BIT(19))
#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M (BIT(19))
#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V 0x1
#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S 19
/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU : ;bitpos:[13] ;default: 1'b1 ; */
/*description: PRO CPU state vector sel... | 1,084 |
*/
#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF
#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
#define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF
#define RTC_CNTL_WAKEUP_ENA_S 15
#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x38)
/* RTC_CNTL_BBPLL_CAL_INT_ENA : BIT ;bitpos:[20] ;de... | 1,084 |
*/
#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9))
#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9))
#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1
#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9
/* RTC_CNTL_WDT_INT_ENA : BIT ;bitpos:[3] ;default: 1'b0 ; */
/*description: enable RTC WDT interrupt.*/
#define RTC_CNTL_WDT_INT_ENA (BIT... | 1,084 |
*/
#define RTC_CNTL_BBPLL_CAL_INT_RAW (BIT(20))
#define RTC_CNTL_BBPLL_CAL_INT_RAW_M (BIT(20))
#define RTC_CNTL_BBPLL_CAL_INT_RAW_V 0x1
#define RTC_CNTL_BBPLL_CAL_INT_RAW_S 20
/* RTC_CNTL_SWD_INT_RAW : ;bitpos:[15] ;default: 1'b0 ; */
/*description: super watch dog interrupt raw.*/
#define RTC_CNTL_SWD_INT_RAW ... | 1,084 |
*/
#define RTC_CNTL_WDT_INT_RAW (BIT(3))
#define RTC_CNTL_WDT_INT_RAW_M (BIT(3))
#define RTC_CNTL_WDT_INT_RAW_V 0x1
#define RTC_CNTL_WDT_INT_RAW_S 3
/* RTC_CNTL_SLP_REJECT_INT_RAW : ;bitpos:[1] ;default: 1'b0 ; */
/*description: sleep reject interrupt raw.*/
#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1))
#defin... | 1,084 |
*/
#define RTC_CNTL_SWD_INT_ST (BIT(15))
#define RTC_CNTL_SWD_INT_ST_M (BIT(15))
#define RTC_CNTL_SWD_INT_ST_V 0x1
#define RTC_CNTL_SWD_INT_ST_S 15
/* RTC_CNTL_MAIN_TIMER_INT_ST : ;bitpos:[10] ;default: 1'b0 ; */
/*description: RTC main timer interrupt state.*/
#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10))
#de... | 1,084 |
*/
#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1))
#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1))
#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1
#define RTC_CNTL_SLP_REJECT_INT_ST_S 1
/* RTC_CNTL_SLP_WAKEUP_INT_ST : ;bitpos:[0] ;default: 1'b0 ; */
/*description: sleep wakeup interrupt state.*/
#define RTC_CNTL_SLP_WAKEUP_I... | 1,084 |
*/
#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10))
#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10))
#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1
#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10
/* RTC_CNTL_BROWN_OUT_INT_CLR : ;bitpos:[9] ;default: 1'b0 ; */
/*description: Clear brown out interrupt state.*/
#define RTC_CNTL_BR... | 1,084 |
*/
#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0))
#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0))
#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1
#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0
#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x48)
/* RTC_CNTL_SCRATCH0 : ;bitpos:[31:0] ;default: 0 ; */
/*description:... | 1,084 |
*/
#define RTC_CNTL_SCRATCH2 0xFFFFFFFF
#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF
#define RTC_CNTL_SCRATCH2_S 0
#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x54)
/* RTC_CNTL_SCRATCH3 : ;bitpos:[31:0] ;default: 0 ; */
/*descr... | 1,084 |
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