text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
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*/
#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(31))
#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(31))
#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1
#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 31
#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60)
/* RTC_CNTL_DEEP_SLP_REJECT_EN : ;bitpos:[31] ;default: 1... | 1,084 |
*/
#define RTC_CNTL_CPUPERIOD_SEL 0x00000003
#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
#define RTC_CNTL_CPUPERIOD_SEL_V 0x3
#define RTC_CNTL_CPUPERIOD_SEL_S 30
/* RTC_CNTL_CPUSEL_CONF : ;bitpos:[29] ;default: 1'b0 ; */
/*description: CPU sel option.*/
#define RTC_C... | 1,084 |
*/
#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28))
#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (BIT(28))
#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x1
#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28
/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : ;bitpos:[27] ;default: 1'b0 ; */
/*description: Need add desc.... | 1,084 |
*/
#define RTC_CNTL_CK8M_DFREQ 0x000000FF
#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
#define RTC_CNTL_CK8M_DFREQ_V 0xFF
#define RTC_CNTL_CK8M_DFREQ_S 17
/* RTC_CNTL_CK8M_FORCE_NOGATING : ;bitpos:[16] ;default: 1'd0 ; */
/*description: CK8M force no gating during sleep.*/
#de... | 1,084 |
*/
#define RTC_CNTL_DIG_CLK8M_EN (BIT(10))
#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10))
#define RTC_CNTL_DIG_CLK8M_EN_V 0x1
#define RTC_CNTL_DIG_CLK8M_EN_S 10
/* RTC_CNTL_DIG_CLK8M_D256_EN : ;bitpos:[9] ;default: 1'd1 ; */
/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/
#defi... | 1,084 |
*/
#define RTC_CNTL_ENB_CK8M (BIT(6))
#define RTC_CNTL_ENB_CK8M_M (BIT(6))
#define RTC_CNTL_ENB_CK8M_V 0x1
#define RTC_CNTL_ENB_CK8M_S 6
/* RTC_CNTL_CK8M_DIV : ;bitpos:[5:4] ;default: 2'b01 ; */
/*description: CK8M_D256_OUT divider. 00: div128.*/
#define RTC_CNTL_CK8M_DIV 0x00000003
#define RTC_CNTL_CK8M_DIV_... | 1,084 |
*/
#define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1))
#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1))
#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1
#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1
#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6C)
/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : ;bitpos:[31] ... | 1,084 |
*/
#define RTC_CNTL_DBG_ATTEN_ACTIVE 0x0000000F
#define RTC_CNTL_DBG_ATTEN_ACTIVE_M ((RTC_CNTL_DBG_ATTEN_ACTIVE_V)<<(RTC_CNTL_DBG_ATTEN_ACTIVE_S))
#define RTC_CNTL_DBG_ATTEN_ACTIVE_V 0xF
#define RTC_CNTL_DBG_ATTEN_ACTIVE_S 26
/* RTC_CNTL_DBG_ATTEN_MONITOR : ;bitpos:[25:22] ;default: 4'd0 ; */
/*description: DBG_... | 1,084 |
*/
#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17))
#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17))
#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1
#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17
/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : ;bitpos:[16] ;default: 1'b1 ; */
/*description: bias_sleep when rtc in sleep_state.*/
#define RTC_C... | 1,084 |
*/
#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13))
#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13))
#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1
#define RTC_CNTL_BIAS_BUF_MONITOR_S 13
/* RTC_CNTL_BIAS_BUF_DEEP_SLP : ;bitpos:[12] ;default: 1'b0 ; */
/*description: Need add desc.*/
#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(1... | 1,084 |
*/
#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN (BIT(8))
#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M (BIT(8))
#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V 0x1
#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S 8
/* RTC_CNTL_DG_VDD_DRV_B_SLP : ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: Need add desc.*/
#define RTC_CNTL_DG_VDD_DRV_B_SLP ... | 1,084 |
8v or lower ).*/
#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30))
#define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30))
#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1
#define RTC_CNTL_REGULATOR_FORCE_PD_S 30
/* RTC_CNTL_SCK_DCAP : ;bitpos:[21:14] ;default: 8'd0 ; */
/*description: SCK_DCAP.*/
#define RTC_CNTL_SCK_DCAP 0x00... | 1,084 |
*/
#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31))
#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31))
#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1
#define RTC_CNTL_DG_WRAP_PD_EN_S 31
/* RTC_CNTL_DG_WRAP_FORCE_PU : ;bitpos:[20] ;default: 1'd1 ; */
/*description: digital core force power up.*/
#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(2... | 1,084 |
*/
#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(4))
#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(4))
#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1
#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 4
/* RTC_CNTL_VDD_SPI_PD_EN : ;bitpos:[3] ;default: 1'b0 ; */
/*description: Need add desc.*/
#define RTC_CNTL_VDD_SPI_PD_EN (BIT(3))
#defi... | 1,084 |
*/
#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31))
#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31))
#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1
#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31
/* RTC_CNTL_DG_WRAP_FORCE_ISO : ;bitpos:[30] ;default: 1'd0 ; */
/*description: digital core force ISO.*/
#define RTC_CNTL_DG_WRA... | 1,084 |
*/
#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13))
#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13))
#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1
#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13
/* RTC_CNTL_DG_PAD_FORCE_NOISO : ;bitpos:[12] ;default: 1'd1 ; */
/*description: digital pad force no ISO.*/
#define RTC_CNTL_DG_PAD_FORCE_NO... | 1,084 |
*/
#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9))
#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9))
#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1
#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9
/* RTC_CNTL_DIG_ISO_FORCE_ON : ;bitpos:[8] ;default: 1'd0 ; */
/*description: Need add desc.*/
#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8))
#define... | 1,084 |
*/
#define RTC_CNTL_WDT_STG0 0x00000007
#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
#define RTC_CNTL_WDT_STG0_V 0x7
#define RTC_CNTL_WDT_STG0_S 28
/* RTC_CNTL_WDT_STG1 : ;bitpos:[27:25] ;default: 3'h0 ; */
/*description: 1: interrupt stage en.*/
#define RTC_CNTL_WDT_STG1 0x00000... | 1,084 |
*/
#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007
#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7
#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16
/* RTC_CNTL_WDT_SYS_RESET_LENGTH : ;bitpos:[15:13] ;default: 3'... | 1,084 |
*/
#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11))
#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11))
#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1
#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11
/* RTC_CNTL_WDT_PAUSE_IN_SLP : ;bitpos:[9] ;default: 1'd1 ; */
/*description: pause WDT in sleep.*/
#define RTC_CNTL_WDT_PAUSE_IN... | 1,084 |
*/
#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF
#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF
#define RTC_CNTL_WDT_STG0_HOLD_S 0
#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x8C)
/* RTC_CNTL_WDT_STG1_HOLD : ... | 1,084 |
*/
#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF
#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF
#define RTC_CNTL_WDT_STG3_HOLD_S 0
#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x98)
/* RTC_CNTL_WDT_FEED : ;bitpos:... | 1,084 |
*/
#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31))
#define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31))
#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1
#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31
/* RTC_CNTL_SWD_DISABLE : ;bitpos:[30] ;default: 1'b0 ; */
/*description: disabel SWD.*/
#define RTC_CNTL_SWD_DISABLE (BIT(30))
#define RT... | 1,084 |
*/
#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF
#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S))
#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF
#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18
/* RTC_CNTL_SWD_BYPASS_RST : ;bitpos:[17] ;default: 1'b0 ; */
/*description: Need add... | 1,084 |
*/
#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF
#define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S))
#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF
#define RTC_CNTL_SWD_WKEY_S 0
#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xA8)
/* RTC_CNTL_SW_STALL_PROCPU_C1 : ;bitpos:[31:26] ;defaul... | 1,084 |
*/
#define RTC_CNTL_SCRATCH5 0xFFFFFFFF
#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF
#define RTC_CNTL_SCRATCH5_S 0
#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xB4)
/* RTC_CNTL_SCRATCH6 : ;bitpos:[31:0] ;default: 0 ; */
/*descr... | 1,084 |
*/
#define RTC_CNTL_MAIN_STATE 0x0000000F
#define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S))
#define RTC_CNTL_MAIN_STATE_V 0xF
#define RTC_CNTL_MAIN_STATE_S 28
/* RTC_CNTL_MAIN_STATE_IN_IDLE : ;bitpos:[27] ;default: 1'b0 ; */
/*description: rtc main state machine is in idle state.*/... | 1,084 |
*/
#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24))
#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24))
#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1
#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24
/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : ;bitpos:[23] ;default: 1'b0 ; */
/*description: rtc main state machine is in wait... | 1,084 |
*/
#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20))
#define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20))
#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1
#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20
/* RTC_CNTL_RDY_FOR_WAKEUP : ;bitpos:[19] ;default: 1'b0 ; */
/*description: rtc is ready to receive wake up trigger from wake up... | 1,084 |
*/
#define RTC_CNTL_COCPU_STATE_DONE (BIT(16))
#define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16))
#define RTC_CNTL_COCPU_STATE_DONE_V 0x1
#define RTC_CNTL_COCPU_STATE_DONE_S 16
/* RTC_CNTL_COCPU_STATE_SLP : ;bitpos:[15] ;default: 1'b0 ; */
/*description: ulp/cocpu is in sleep state.*/
#define RTC_CNTL_COCPU_STATE_SLP... | 1,084 |
*/
#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12))
#define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12))
#define RTC_CNTL_TOUCH_STATE_DONE_V 0x1
#define RTC_CNTL_TOUCH_STATE_DONE_S 12
/* RTC_CNTL_TOUCH_STATE_SLP : ;bitpos:[11] ;default: 1'b0 ; */
/*description: touch is in sleep state.*/
#define RTC_CNTL_TOUCH_STATE_SLP ... | 1,084 |
*/
#define RTC_CNTL_XPD_DIG (BIT(8))
#define RTC_CNTL_XPD_DIG_M (BIT(8))
#define RTC_CNTL_XPD_DIG_V 0x1
#define RTC_CNTL_XPD_DIG_S 8
#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xC0)
/* RTC_CNTL_LOW_POWER_DIAG1 : ;bitpos:[31:0] ;default: 0 ; */
/*description: Need add desc.*/
#define RTC_CNTL_LOW... | 1,084 |
*/
#define RTC_CNTL_GPIO_PIN3_HOLD (BIT(3))
#define RTC_CNTL_GPIO_PIN3_HOLD_M (BIT(3))
#define RTC_CNTL_GPIO_PIN3_HOLD_V 0x1
#define RTC_CNTL_GPIO_PIN3_HOLD_S 3
/* RTC_CNTL_GPIO_PIN2_HOLD : ;bitpos:[2] ;default: 1'b0 ; */
/*description: Need add desc.*/
#define RTC_CNTL_GPIO_PIN2_HOLD (BIT(2))
#define RTC_CNT... | 1,084 |
*/
#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF
#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF
#define RTC_CNTL_DIG_PAD_HOLD_S 0
#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xCC)
/* RTC_CNTL_BROWN_OUT_DET : ;bitpos... | 1,084 |
*/
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28))
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28))
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28
/* RTC_CNTL_BROWN_OUT_RST_SEL : ;bitpos:[27] ;default: 1'b0 ; */
/*description: 1: 4-pos reset.*/
#define RTC_CNTL_BROWN_OUT... | 1,084 |
*/
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15))
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15))
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15
/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : ;bitpos:[14] ;default: 1'b0 ; */
/*description: enable close flash when brown out happens... | 1,084 |
*/
#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF
#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF
#define RTC_CNTL_TIMER_VALUE1_LOW_S 0
#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xD4)
/* RTC_CNTL... | 1,084 |
*/
#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF
#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
#define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF
#define RTC_CNTL_REJECT_CAUSE_S 0
#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0xE0)
/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : ;bitpo... | 1,084 |
*/
#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF
#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF
#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8
#define RTC_CNTL_INT_ENA_RTC_W1TS_REG ... | 1,084 |
*/
#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10))
#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10))
#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1
#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10
/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : ;bitpos:[9] ;default: 1'b0 ; */
/*description: enable brown out interrupt.*/... | 1,084 |
*/
#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0))
#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0))
#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1
#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0
#define RTC_CNTL_INT_ENA_RTC_W1TC_REG (DR_REG_RTCCNTL_BASE + 0xF0)
/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : ;b... | 1,084 |
*/
#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9))
#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9))
#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1
#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9
/* RTC_CNTL_WDT_INT_ENA_W1TC : ;bitpos:[3] ;default: 1'b0 ; */
/*description: enable RTC WDT interrupt.*/
#define RTC_CN... | 1,084 |
*/
#define RTC_CNTL_RETENTION_WAIT 0x0000001F
#define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S))
#define RTC_CNTL_RETENTION_WAIT_V 0x1F
#define RTC_CNTL_RETENTION_WAIT_S 27
/* RTC_CNTL_RETENTION_EN : ;bitpos:[26] ;default: 1'd0 ; */
/*description: Need add desc.*/
#defin... | 1,084 |
*/
#define RTC_CNTL_RETENTION_CLK_SEL (BIT(18))
#define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(18))
#define RTC_CNTL_RETENTION_CLK_SEL_V 0x1
#define RTC_CNTL_RETENTION_CLK_SEL_S 18
#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0xF8)
/* RTC_CNTL_FIB_SEL : ;bitpos:[2:0] ;default: 3'd7 ; */
/*description... | 1,084 |
*/
#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE (BIT(30))
#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(30))
#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V 0x1
#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S 30
/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : ;bitpos:[29] ;default: 1'b0 ; */
/*description: Need add desc.*/
#define RT... | 1,084 |
*/
#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE (BIT(26))
#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(26))
#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V 0x1
#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S 26
/* RTC_CNTL_GPIO_PIN0_INT_TYPE : ;bitpos:[25:23] ;default: 3'd0 ; */
/*description: Need add desc.*/
#define RTC_... | 1,084 |
*/
#define RTC_CNTL_GPIO_PIN3_INT_TYPE 0x00000007
#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S))
#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V 0x7
#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S 14
/* RTC_CNTL_GPIO_PIN4_INT_TYPE : ;bitpos:[13:11] ;default: 3'd0 ; */
/*desc... | 1,084 |
*/
#define RTC_CNTL_GPIO_PIN_CLK_GATE (BIT(7))
#define RTC_CNTL_GPIO_PIN_CLK_GATE_M (BIT(7))
#define RTC_CNTL_GPIO_PIN_CLK_GATE_V 0x1
#define RTC_CNTL_GPIO_PIN_CLK_GATE_S 7
/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : ;bitpos:[6] ;default: 1'b0 ; */
/*description: Need add desc.*/
#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR... | 1,084 |
*/
#define RTC_CNTL_DEBUG_SEL3 0x0000001F
#define RTC_CNTL_DEBUG_SEL3_M ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S))
#define RTC_CNTL_DEBUG_SEL3_V 0x1F
#define RTC_CNTL_DEBUG_SEL3_S 22
/* RTC_CNTL_DEBUG_SEL2 : ;bitpos:[21:17] ;default: 5'd0 ; */
/*description: Need add desc.*/
#define RTC_CNTL_DEBUG_SEL2 ... | 1,084 |
*/
#define RTC_CNTL_DEBUG_BIT_SEL 0x0000001F
#define RTC_CNTL_DEBUG_BIT_SEL_M ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S))
#define RTC_CNTL_DEBUG_BIT_SEL_V 0x1F
#define RTC_CNTL_DEBUG_BIT_SEL_S 2
/* RTC_CNTL_DEBUG_12M_NO_GATING : ;bitpos:[1] ;default: 1'b0 ; */
/*description: Need add desc.*/
#define... | 1,084 |
*/
#define RTC_CNTL_GPIO_PIN1_FUN_SEL 0x0000000F
#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S))
#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V 0xF
#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S 24
/* RTC_CNTL_GPIO_PIN2_FUN_SEL : ;bitpos:[23:20] ;default: 4'd0 ; */
/*description... | 1,084 |
*/
#define RTC_CNTL_GPIO_PIN4_FUN_SEL 0x0000000F
#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S))
#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V 0xF
#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S 12
/* RTC_CNTL_GPIO_PIN5_FUN_SEL : ;bitpos:[11:8] ;default: 4'd0 ; */
/*description:... | 1,084 |
*/
#define RTC_CNTL_GPIO_PIN2_MUX_SEL (BIT(5))
#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M (BIT(5))
#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V 0x1
#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S 5
/* RTC_CNTL_GPIO_PIN3_MUX_SEL : ;bitpos:[4] ;default: 1'b0 ; */
/*description: Need add desc.*/
#define RTC_CNTL_GPIO_PIN3_MUX_SEL (BIT(4... | 1,084 |
*/
#define RTC_CNTL_FORCE_XPD_SAR 0x00000003
#define RTC_CNTL_FORCE_XPD_SAR_M ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S))
#define RTC_CNTL_FORCE_XPD_SAR_V 0x3
#define RTC_CNTL_FORCE_XPD_SAR_S 30
/* RTC_CNTL_SAR2_PWDET_CCT : ;bitpos:[29:27] ;default: 3'd0 ; */
/*description: Need add desc.*/
#define ... | 1,084 |
*/
#define RTC_CNTL_DATE 0x0FFFFFFF
#define RTC_CNTL_DATE_M ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S))
#define RTC_CNTL_DATE_V 0xFFFFFFF
#define RTC_CNTL_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RTC_CNTL_REG_H_ */
| 1,084 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6004E840
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
#define ANA_CONFIG_REG 0x6004E844
#define A... | 1,085 |
/*
*/
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_
#define SPICLK_OUT_MUX_IDX SPICLK_OUT_IDX
#define SPIQ_IN_IDX 0
#define SPIQ_OUT_IDX 0
#define SPID_IN_IDX 1
#define SPID_OUT_IDX 1
#define SPIHD_IN_IDX 2
#... | 1,086 |
/*
*/
#ifndef _SOC_SYSCON_REG_H_
#define _SOC_SYSCON_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: reg_rst_tick_cnt.*/
#define SYSCON_RST_TICK_CNT (BIT(... | 1,088 |
*/
#define SYSCON_TICK_ENABLE (BIT(16))
#define SYSCON_TICK_ENABLE_M (BIT(16))
#define SYSCON_TICK_ENABLE_V 0x1
#define SYSCON_TICK_ENABLE_S 16
/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
/*description: reg_ck8m_tick_num.*/
#define SYSCON_CK8M_TICK_NUM 0x000000FF
#define SYSCON_CK8M_TICK_N... | 1,088 |
*/
#define SYSCON_CLK40X_BB_OEN (BIT(9))
#define SYSCON_CLK40X_BB_OEN_M (BIT(9))
#define SYSCON_CLK40X_BB_OEN_V 0x1
#define SYSCON_CLK40X_BB_OEN_S 9
/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: reg_clk_dac_cpu_oen.*/
#define SYSCON_CLK_DAC_CPU_OEN (BIT(8))
#define SYSCON_CLK_D... | 1,088 |
*/
#define SYSCON_CLK160_OEN (BIT(5))
#define SYSCON_CLK160_OEN_M (BIT(5))
#define SYSCON_CLK160_OEN_V 0x1
#define SYSCON_CLK160_OEN_S 5
/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: reg_clk80_oen.*/
#define SYSCON_CLK80_OEN (BIT(4))
#define SYSCON_CLK80_OEN_M (BIT(4))
#define SYSCO... | 1,088 |
*/
#define SYSCON_CLK20_OEN (BIT(0))
#define SYSCON_CLK20_OEN_M (BIT(0))
#define SYSCON_CLK20_OEN_V 0x1
#define SYSCON_CLK20_OEN_S 0
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xC)
/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: reg_wifi_bb_cfg.*/
#define SYSCON_... | 1,088 |
*/
#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_S 0
#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x18)
/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0... | 1,088 |
*/
#define SYSCON_PERI_IO_SWAP 0x000000FF
#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
#define SYSCON_PERI_IO_SWAP_V 0xFF
#define SYSCON_PERI_IO_SWAP_S 0
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20)
/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;defa... | 1,088 |
*/
#define SYSCON_FLASH_ACE1_ATTR 0x00000003
#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
#define SYSCON_FLASH_ACE1_ATTR_V 0x3
#define SYSCON_FLASH_ACE1_ATTR_S 0
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30)
/* SYSCON_FLASH_ACE2_ATTR : R/W ;b... | 1,088 |
*/
#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_S 0
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3C)
/* SYSCON_FLASH... | 1,088 |
*/
#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_S 0
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48)
/* SYSCON_FLASH... | 1,088 |
*/
#define SYSCON_FLASH_ACE2_SIZE 0x00001FFF
#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
#define SYSCON_FLASH_ACE2_SIZE_V 0x1FFF
#define SYSCON_FLASH_ACE2_SIZE_S 0
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54)
/* SYSCON_FLASH_ACE3_SIZE : R/W... | 1,088 |
*/
#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1))
#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1))
#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1
#define SYSCON_SPI_MEM_REJECT_CLR_S 1
/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: reg_spi_mem_reject_int.*/
#define SYSCON_SPI_MEM_REJECT_INT (... | 1,088 |
*/
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1
#define SYSCON_SDIO_WIN_ACCESS_EN_S 0
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94)
/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: re... | 1,088 |
*/
#define SYSCON_REDCY_SIG1 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_S 0
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9C)
/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: ... | 1,088 |
*/
#define SYSCON_DC_MEM_FORCE_PU (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_V 0x1
#define SYSCON_DC_MEM_FORCE_PU_S 4
/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: reg_pbus_mem_force_pd.*/
#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3))
#defin... | 1,088 |
*/
#define SYSCON_AGC_MEM_FORCE_PU (BIT(0))
#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0))
#define SYSCON_AGC_MEM_FORCE_PU_V 0x1
#define SYSCON_AGC_MEM_FORCE_PU_S 0
#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xA0)
/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*descripti... | 1,088 |
*/
#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x0000000F
#define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
#define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0xF
#define SYSCON_SRAM_CLKGATE_FORCE_ON_S 3
/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
... | 1,088 |
*/
#define SYSCON_ROM_POWER_DOWN 0x00000007
#define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
#define SYSCON_ROM_POWER_DOWN_V 0x7
#define SYSCON_ROM_POWER_DOWN_S 0
#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xAC)
/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[6:3]... | 1,088 |
*/
#define SYSCON_RND_DATA 0xFFFFFFFF
#define SYSCON_RND_DATA_M ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S))
#define SYSCON_RND_DATA_V 0xFFFFFFFF
#define SYSCON_RND_DATA_S 0
#define SYSCON_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0xB4)
/* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/... | 1,088 |
*/
#define SYSCON_PERI_BACKUP_SIZE 0x000003FF
#define SYSCON_PERI_BACKUP_SIZE_M ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S))
#define SYSCON_PERI_BACKUP_SIZE_V 0x3FF
#define SYSCON_PERI_BACKUP_SIZE_S 19
/* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
/*description: reg_per... | 1,088 |
*/
#define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000003
#define SYSCON_PERI_BACKUP_FLOW_ERR_M ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S))
#define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x3
#define SYSCON_PERI_BACKUP_FLOW_ERR_S 1
#define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0xB8)... | 1,088 |
*/
#define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V 0x1
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S 1
/* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
/*description: reg_peri_backup_done_int_raw.*/
#defin... | 1,088 |
*/
#define SYSCON_PERI_BACKUP_DONE_INT_ST (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_ST_M (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x1
#define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0
#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0xC8)
/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:... | 1,088 |
*/
#define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V 0x1
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S 1
/* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
/*description: reg_peri_backup_done_int_clr.*/
#defin... | 1,088 |
/*
*/
#pragma once
#include "sdkconfig.h"
// TODO: IDF-9197 This file is created to glob the soc_caps correctly in esp-docs
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "../../beta3/include/soc/soc_caps.h" // recursive, condition: IDF_TARGET_ESP32C5_BETA3_VERSION
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSIO... | 1,089 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interr... | 1,090 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control/Configuration Registers */
/** Type of mode register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val... | 1,091 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */... | 1,095 |
< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
G... | 1,095 |
/*
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/*CLINT MINT*/
#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0)
/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define CLINT_CPU_MINT_SIP BIT(0)
#define CLINT_CPU_MINT_SIP_M BIT(0)
#defin... | 1,096 |
*/
#define CLINT_MINT_SAMPLING_MODE 0x00000003
#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S))
#define CLINT_MINT_SAMPLING_MODE_V 0x3
#define CLINT_MINT_SAMPLING_MODE_S 4
/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define CLIN... | 1,096 |
*/
#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S))
#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_H_S 0
#ifdef __cplusplus
}
#endif
| 1,096 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RSA_M_MEM register
*/
#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
#define RSA_M_MEM_SIZE_BYTES 16
/** RSA_Z_MEM register
*/
#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
#define RSA_Z_MEM_SIZE_BYTES 16
/** RSA_Y_MEM registe... | 1,099 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V link. "
*/
#define AES_BLOCK_... | 1,101 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of tar_low register
*/
typedef union {
struct {
/** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t main_timer_tar_low0:32;
};
uint32_t val;
} lp_tim... | 1,102 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}
#endif
| 1,103 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HUK_CLK_REG register
*/
#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
*/
#define HUK_CLK_EN (BIT(0))
#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S)
#define HUK_CLK_EN_... | 1,110 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
*/
typedef union {
struct {
/** log_mode : R/W; bitpos: [3:0]; default: 0;
*/
uint32_t log_mode:4;
/** log_mem_loop_enable : R/W; bitpos: [... | 1,111 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V link.... | 1,112 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_... | 1,119 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** GPIO_STRAP_REG register
*/
#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0)
/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0;
*/
#define GPIO_STRAPPING 0x0000FFFFU
#define GPIO_STRAPPING_M (GPIO_STRAPPING_V link.
*... | 1,120 |
*/
#define GPIO_FUNC7_OUT_SEL 0x000001FFU
#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V link.
*/
#define GPIO_FUNC8_OUT_SEL 0x000001FFU
#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V link.
*/
#define GPIO_FUNC9_OUT_SEL 0x000001FFU
#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V link.
*/
#de... | 1,120 |
*/
#define GPIO_FUNC17_OUT_SEL 0x000001FFU
#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V link.
*/
#define GPIO_FUNC18_OUT_SEL 0x000001FFU
#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V link.
*/
#define GPIO_FUNC19_OUT_SEL 0x000001FFU
#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V link... | 1,120 |
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