text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
uint32_t pes_end : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t wpe_end : 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
uint32_t slv_st_end : 1; /*The status bit for SPI_MEM_... | 1,177 |
*/
uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t reserved11 : 21; /*reserved*/
};
uint32_t val;
} int_st;
uint32_t reserved_d0;
union {
struct {
uint32_t reg_... | 1,177 |
*/
uint32_t reg_fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/
uint32_t reg_fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to... | 1,177 |
*/
uint32_t reg_fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
uint32_t reg_fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
... | 1,177 |
*/
uint32_t reg_smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/
uint32_t reg_smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/
uint32_t reg_smem_ddr_cmd_dis : 1; /*the bit... | 1,177 |
It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
uint32_t reserved22 : 2; /*reserved*/
uint32_t reg_smem_clk_diff_en : 1; /*Set this bit to enable the diff... | 1,177 |
*/
uint32_t reg_smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
uint32_t reserved31 : 1; /*reserved*/
};
... | 1,177 |
The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
uint32_t reserved3 : 29; /*reserved*/
};
uint32_t val;
} spi_fmem_pms0_attr;
union {
struct {
uint32_t reg_fmem_pms1_rd_attr ... | 1,177 |
0: Not allowed.*/
uint32_t reg_fmem_pms2_wr_attr : 1; /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
uint32_t reg_fmem_pms2_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by... | 1,177 |
*/
uint32_t reserved3 : 29; /*reserved*/
};
uint32_t val;
} spi_fmem_pms3_attr;
union {
struct {
uint32_t reg_fmem_pms0_addr_s : 26; /*SPI1 flash ACE section $n start address value*/
uint32_t reserved26 ... | 1,177 |
0: Not allowed.*/
uint32_t reg_smem_pms0_wr_attr : 1; /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
uint32_t reg_smem_pms0_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE sectio... | 1,177 |
*/
uint32_t reserved3 : 29; /*reserved*/
};
uint32_t val;
} spi_smem_pms1_attr;
union {
struct {
uint32_t reg_smem_pms2_rd_attr : 1; /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
uint32_t r... | 1,177 |
0: Not allowed.*/
uint32_t reg_smem_pms3_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
uint32_t reserved3 ... | 1,177 |
It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
uint32_t pm_en : 1; /*Set this bit to enable SPI0/1 transfer permission control function.*/
uint32_t reserved27 : 1; /*reserved*/
uint32_t pms_ld ... | 1,177 |
*/
};
uint32_t val;
} pms_reject;
union {
struct {
uint32_t reserved0 : 11; /*reserved*/
uint32_t ecc_err_int_num : 6; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
u... | 1,177 |
*/
uint32_t reserved22 : 2; /*reserved*/
uint32_t ecc_continue_record_err_en : 1; /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC... | 1,177 |
It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */
uint32_t all_fifo_empty : 1; /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/
... | 1,177 |
*/
};
uint32_t val;
} axi_err_addr;
union {
struct {
uint32_t reserved0 : 17; /*reserved*/
uint32_t reg_smem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
... | 1,177 |
*/
uint32_t timing_cali : 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t dll_timing_cali ... | 1,177 |
..*/
uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delay... | 1,177 |
..*/
uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delay... | 1,177 |
*/
uint32_t reg_smem_timing_cali : 1; /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t reg_smem_extra_dummy_cyclelen : 3; /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reg_... | 1,177 |
..*/
uint32_t reg_smem_din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t reg_smem_din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delay... | 1,177 |
..*/
uint32_t reg_smem_din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t reg_smem_dins_num : 2; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: in... | 1,177 |
1: enable 0: disable. */
uint32_t reg_smem_cs_hold : 1; /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */
uint32_t reg_smem_cs_setup_time : 5; /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_... | 1,177 |
*/
uint32_t reserved17 : 8; /*reserved*/
uint32_t reg_smem_cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.... | 1,177 |
1: Enable. 0: Disable.*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} clock_gate;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uin... | 1,177 |
It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/
uint32_t reserved2 : 30; /*reserved*/
};
uint32_t val;
} xts_linesize;
union {
struct {
uint32_t reg_xts_destination : ... | 1,177 |
This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} xts_trigger;
... | 1,177 |
0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/
uint32_t reserved2 : 30; /*reserved*/
};
uint32_t val;
} xts_state;
union {
stru... | 1,177 |
*/
uint32_t reg_mmu_page_size : 2; /*0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8*/
uint32_t reserved5 : 11; /*reserved*/
uint32_t aux_ctrl : 14; /*MMU PSRAM aux control register*/
... | 1,177 |
1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
uint32_t reg_crypt_dpa_selectister : 1; /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
... | 1,177 |
*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} date;
} spi_mem_dev_t;
extern spi_mem_dev_t SPIMEM0;
extern spi_mem_dev_t SPIMEM1;
#ifndef __cplusplus
_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
#endif
#... | 1,177 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of m0_mode_ctrl register
*/
typedef union {
struct {
/** m0_mode : R/W; bitpos: [1:0]; default: 3;
*/
uint32_t m0_mode:2;
/** m0_lock : R/W; bitpos: [2]; default... | 1,178 |
/*
*/
#pragma once
#include
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
*/
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t... | 1,179 |
/*
*/
#pragma once
#include "soc.h"
#include "soc/lpperi_reg.h"
/* Hardware random number generator register */
#define WDEV_RND_REG LPPERI_RNG_DATA_REG
| 1,180 |
/*
*/
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C6.
#pragma once
// TODO: [ESP32C5] IDF-8722
//UART channels
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 16
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_D... | 1,186 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
/** Type of conf register
*/
typedef union {
struct {
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
*/
uint32_t systimer_clk_fo:1;
/** etm_en : R/W; bitpos:... | 1,187 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
*/
#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
*/
#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0)... | 1,188 |
/*
*/
#include "soc/clic_reg.h"
#include "soc/soc_caps.h"
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF)
| 1,189 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory configuration registers */
/** Type of mem_start_addr register
*/
typedef union {
struct {
/** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t mem_start_addr:32;
};
uint32_t val;... | 1,191 |
/*
*/
#pragma once
#include "soc/io_mux_reg.h"
// TODO: [ESP32C5] IDF-8722
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 12
#define U0TXD_GPIO_NUM 11
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GP... | 1,196 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
/*description: .*/
#define I2C_ANA_MST_I2C0_BUSY (BIT(25))
#define I2C_ANA_MST_I2C0_BUSY... | 1,198 |
*/
#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF
#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S))
#define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF
#define I2C_ANA_MST_I2C1_CTRL_S 0
#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31... | 1,198 |
*/
#define I2C_ANA_MST_I2C1_STATUS 0x000000FF
#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S))
#define I2C_ANA_MST_I2C1_STATUS_V 0xFF
#define I2C_ANA_MST_I2C1_STATUS_S 24
/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: .*/
#define I2C_ANA_MST_I2C1_... | 1,198 |
*/
#define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S))
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20
/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */
/*desc... | 1,198 |
*/
#define I2C_ANA_MST_ANA_STATUS0 0x000000FF
#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_STATUS0_V)<<(I2C_ANA_MST_STATUS0_S))
#define I2C_ANA_MST_ANA_STATUS0_V 0xFF
#define I2C_ANA_MST_ANA_STATUS0_S 24
/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */
/*description: .*/
#define I2C_ANA... | 1,198 |
*/
#define I2C_ANA_MST_ANA_STATUS2 0x000000FF
#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S))
#define I2C_ANA_MST_ANA_STATUS2_V 0xFF
#define I2C_ANA_MST_ANA_STATUS2_S 24
/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
/*description: .*/
#define I2C_ANA... | 1,198 |
*/
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S))
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_B... | 1,198 |
*/
#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11))
#define I2C_ANA_MST_ARBITER_DIS_V 0x1
#define I2C_ANA_MST_ARBITER_DIS_S 11
/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
/*description: .*/
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F
#... | 1,198 |
*/
#define I2C_ANA_MST_NOUSE 0xFFFFFFFF
#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S))
#define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF
#define I2C_ANA_MST_NOUSE_S 0
#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
/*descrip... | 1,198 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of mn_mode_ctrl register
*/
typedef union {
struct {
/** mn_mode : R/W; bitpos: [1:0]; default: 0;
*/
uint32_t mn_mode:2;
/** mn_lock : R/W; bitpos: [2]; default... | 1,207 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of config0 register
*/
typedef union {
struct {
/** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20;
*/
uint32_t wdt_chip_reset_width:8;
/** wdt_chip_reset_en : ... | 1,211 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
*/
uint32_t set_start:1;
uint32_t reserv... | 1,213 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** rng_ck_en : R/W; bitpos: [24]; default: 1;
*/
uint32_t rng_ck_en:1;
/** otp_dbg_ck_en... | 1,214 |
/*
*/
#pragma once
// TODO: [ESP32C5] IDF-8698 (inherit from C6)
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_CS 24
#define SPI_IOMUX_PIN_NUM_CLK 29
#define SPI_IOMUX_PIN_NUM_MOSI 30
#define SPI_IOMUX_PIN_NUM_MISO 25
#define SPI_IOMUX_PIN_NUM_WP 26
#define SPI_IOMUX_PIN_NUM_HD 28
#defin... | 1,215 |
/**
*/
#pragma once
#include "soc/lp_gpio_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef lp_gpio_dev_t rtc_io_dev_t;
#define RTCIO LP_GPIO
#ifdef __cplusplus
}
#endif
| 1,216 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control and configuration registers */
/** Type of tx_inst_cfg0 register
*/
typedef union {
struct {
/** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t tx_inst_idx:3;
/** tx_inst_pos : R/W... | 1,217 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitp... | 1,218 |
/*
*/
#pragma once
/**
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 0
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_C... | 1,219 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
*/
typedef union {
struct {
/** reg_cg_force_on : R/W; bitpos: [0]; default: 1;
*/
uint32_t reg_cg_force_on:1;
/** mem_cg_fo... | 1,221 |
/*
*/
/*
*/
#pragma once
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"
| 1,223 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** I2S_INT_RAW_REG register
*/
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define I2S_RX_DONE_INT_RAW (BIT(0))
#define I2S_RX_DONE_INT_RAW_M (I2S_R... | 1,224 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC... | 1,225 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Key Registers */
/** Type of key_n register
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_n_reg_t;
/** Group: TEXT_IN Reg... | 1,226 |
/*
*/
#pragma once
#define PMU_ICG_APB_ENA_CAN0 18
#define PMU_ICG_APB_ENA_CAN1 19
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_I2C 13
#define PMU_ICG_APB_ENA_I2S 4
#define PMU_ICG_APB_ENA_INTMTX 3
#define PMU_ICG_APB... | 1,228 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
*/
uint32_t work_mode:2;
/** ecc_curve : R/... | 1,229 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
*/
uint32_t region_filter_en:4;
uint32_t rese... | 1,234 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x600AF818
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
#define ANA_CONFIG_REG 0x600AF81C
... | 1,236 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_ANA_BOD_MODE0_CNTL_REG register
*/
#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
*/
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6... | 1,237 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C"
{
#endif
// TODO: [ESP32C5] IDF-8654 need update for MP version
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE,
ETS_WIFI_MAC_NMI_SOURCE,
ETS_WIFI_PWR_INTR_SOURCE,
... | 1,240 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of mode register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} sha_m... | 1,241 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */... | 1,245 |
< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
G... | 1,245 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RSA_M_MEM register
*/
#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
#define RSA_M_MEM_SIZE_BYTES 16
/** RSA_Z_MEM register
*/
#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
#define RSA_Z_MEM_SIZE_BYTES 16
/** RSA_Y_MEM registe... | 1,248 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KE... | 1,250 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of addr_lock register
*/
typedef union {
struct {
/** lock : R/W; bitpos: [1:0]; default: 0;
*/
uint32_t lock:2;
uint32_t reserved_2:30;
};
uint32_t val;
}... | 1,251 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of tar_low register
*/
typedef union {
struct {
/** main_timer_tar_low : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t main_timer_tar_low:32;
};
uint32_t val;
} lp_timer... | 1,252 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}
#endif
| 1,253 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
*/
#define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ... | 1,256 |
/*
*/
#pragma once
#define GPIO_EVT_CH0_RISE_EDGE 1
#define GPIO_EVT_CH1_RISE_EDGE 2
#define GPIO_EVT_CH2_RISE_EDGE 3
#define GPIO_EVT_CH3_RISE_EDGE 4
#define GPIO_EVT_CH4_RISE_EDGE 5
#define GPIO_EVT_CH5_RISE_EDGE 6
#define GPIO_EVT_CH6_RISE_EDGE 7
#define GPIO_EVT_CH7_RISE_EDGE 8
#define GPIO_EVT_CH0_FALL_EDGE 9
#d... | 1,257 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HUK_CLK_REG register
*/
#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
*/
#define HUK_CLK_EN (BIT(0))
#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S)
#define HUK_CLK_EN_... | 1,260 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
*/
typedef union {
struct {
/** log_ena : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t log_ena:3;
/** log_mode : R/W; bitpos: [6:3]; default... | 1,261 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HM... | 1,262 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of store n register
*/
typedef union {
struct {
/** lp_aon_store : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t lp_aon_store:32;
};
uint32_t val;
} lp_aon_store_reg_t;
... | 1,267 |
/*
*/
#pragma once
// TODO: [ESP32C5] IDF-8719 (inherit from C6)
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL 2 ... | 1,268 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x41000000
#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_... | 1,270 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32C5 Root Clock Source
*/
// TODO: [ESP32C5] IDF-8642 (inherit from C6)
/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!... | 1,272 |
< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
SOC_MOD_CLK_SPLL, /... | 1,272 |
< Indication of the end of the available module clock sources */
} soc_module_clk_t;
//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
/**
*/
typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6)
SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XT... | 1,272 |
< Select XTAL as the source clock */
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
*/
typedef enum {
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC... | 1,272 |
< Select XTAL as the source clock */
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_rmt_clk_src_t;
/**
*/
typedef enum { // TODO: [ESP32C5] IDF-8726 (inherit from C6)
RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
... | 1,272 |
< Select XTAL as the default choice */
} soc_periph_temperature_sensor_clk_src_t;
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**
*/
#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
*/
typedef enum {... | 1,272 |
< LP_UART source clock is XTAL_D2 */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
} soc_periph_lp_uart_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
*/
#def... | 1,272 |
< Select PLL_F160M as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
/**
*/
#define SOC_MCPWM_CA... | 1,272 |
< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_EXTERNAL = -1, ... | 1,272 |
< LP_I2C source clock is RTC_FAST */
LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */
LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */
} soc_periph_lp_i2c_clk_src_t;
/////////////////////////////... | 1,272 |
< Select XTAL clock as the source clock */
SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////... | 1,272 |
< Select XTAL as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
} soc_periph_twai_clk_src_t;
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
/**
*/
#define SOC_ADC_DIGI_CLKS {SOC... | 1,272 |
< Select XTAL as the source clock */
MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */
MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 80 MHz as... | 1,272 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.