text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
0: Not allowed.*/
uint32_t reg_smem_pms3_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
uint32_t reserved3 ... | 1,327 |
It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
uint32_t pm_en : 1; /*Set this bit to enable SPI0/1 transfer permission control function.*/
uint32_t reserved27 : 1; /*reserved*/
uint32_t pms_ld ... | 1,327 |
*/
};
uint32_t val;
} pms_reject;
union {
struct {
uint32_t reserved0 : 11; /*reserved*/
uint32_t ecc_err_int_num : 6; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
u... | 1,327 |
*/
uint32_t reserved22 : 2; /*reserved*/
uint32_t ecc_continue_record_err_en : 1; /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC... | 1,327 |
It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */
uint32_t all_fifo_empty : 1; /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/
... | 1,327 |
*/
};
uint32_t val;
} axi_err_addr;
union {
struct {
uint32_t reserved0 : 17; /*reserved*/
uint32_t reg_smem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
... | 1,327 |
*/
uint32_t timing_cali : 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t dll_timing_cali ... | 1,327 |
..*/
uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delay... | 1,327 |
..*/
uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delay... | 1,327 |
*/
uint32_t reg_smem_timing_cali : 1; /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t reg_smem_extra_dummy_cyclelen : 3; /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reg_... | 1,327 |
..*/
uint32_t reg_smem_din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t reg_smem_din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delay... | 1,327 |
..*/
uint32_t reg_smem_din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t reg_smem_dins_num : 2; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: in... | 1,327 |
1: enable 0: disable. */
uint32_t reg_smem_cs_hold : 1; /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */
uint32_t reg_smem_cs_setup_time : 5; /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_... | 1,327 |
*/
uint32_t reserved17 : 8; /*reserved*/
uint32_t reg_smem_cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.... | 1,327 |
1: Enable. 0: Disable.*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} clock_gate;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uin... | 1,327 |
It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/
uint32_t reserved2 : 30; /*reserved*/
};
uint32_t val;
} xts_linesize;
union {
struct {
uint32_t reg_xts_destination : ... | 1,327 |
This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} xts_trigger;
... | 1,327 |
0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/
uint32_t reserved2 : 30; /*reserved*/
};
uint32_t val;
} xts_state;
union {
stru... | 1,327 |
*/
uint32_t reg_mmu_page_size : 2; /*0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8*/
uint32_t reserved5 : 11; /*reserved*/
uint32_t aux_ctrl : 14; /*MMU PSRAM aux control register*/
... | 1,327 |
1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
uint32_t reg_crypt_dpa_selectister : 1; /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
... | 1,327 |
*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} date;
} spi_mem_dev_t;
extern spi_mem_dev_t SPIMEM0;
extern spi_mem_dev_t SPIMEM1;
#ifndef __cplusplus
_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
#endif
#... | 1,327 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of m0_mode_ctrl register
*/
typedef union {
struct {
/** m0_mode : R/W; bitpos: [1:0]; default: 3;
*/
uint32_t m0_mode:2;
/** m0_lock : R/W; bitpos: [2]; default... | 1,328 |
/*
*/
#pragma once
#include
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
*/
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t... | 1,329 |
/*
*/
#pragma once
#include "soc.h"
#include "soc/lpperi_reg.h"
/* Hardware random number generator register */
#define WDEV_RND_REG LPPERI_RNG_DATA_REG
| 1,330 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of sigmadeltan register
*/
typedef union {
struct {
/** sdn_in : R/W; bitpos: [7:0]; default: 0;
*/
uint32_t sdn_in:8;
/** sdn_prescale : R/W; bitpos: [15:8]; defa... | 1,333 |
/*
*/
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C5.
#pragma once
//UART channels
#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 10
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 11
#define U... | 1,336 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
/** Type of conf register
*/
typedef union {
struct {
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
*/
uint32_t systimer_clk_fo:1;
/** etm_en : R/W; bitpos:... | 1,337 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
*/
#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
*/
#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0)... | 1,339 |
/*
*/
#include "soc/clic_reg.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF)
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG ... | 1,340 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Trace memory configuration registers */
/** Type of mem_start_addr register
*/
typedef union {
struct {
/** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t mem_start_addr:32;
};
uint32_... | 1,342 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ATOMIC_ADDR_LOCK_REG register
*/
#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
*/
#define ATOMIC_LOCK 0x00000003U
#define ATOMIC_LOCK_M (ATOMIC_LOCK_V << ATO... | 1,343 |
/*
*/
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 11
#define U0TXD_GPIO_NUM 10
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U1RXD_GP... | 1,348 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
/*description: .*/
#define I2C_ANA_MST_I2C0_BUSY (BIT(25))
#define I2C_ANA_MST_I2C0_BUSY... | 1,350 |
*/
#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF
#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S))
#define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF
#define I2C_ANA_MST_I2C1_CTRL_S 0
#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31... | 1,350 |
*/
#define I2C_ANA_MST_I2C1_STATUS 0x000000FF
#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S))
#define I2C_ANA_MST_I2C1_STATUS_V 0xFF
#define I2C_ANA_MST_I2C1_STATUS_S 24
/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: .*/
#define I2C_ANA_MST_I2C1_... | 1,350 |
*/
#define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S))
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20
/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */
/*desc... | 1,350 |
*/
#define I2C_ANA_MST_ANA_STATUS0 0x000000FF
#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_STATUS0_V)<<(I2C_ANA_MST_STATUS0_S))
#define I2C_ANA_MST_ANA_STATUS0_V 0xFF
#define I2C_ANA_MST_ANA_STATUS0_S 24
/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */
/*description: .*/
#define I2C_ANA... | 1,350 |
*/
#define I2C_ANA_MST_ANA_STATUS2 0x000000FF
#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S))
#define I2C_ANA_MST_ANA_STATUS2_V 0xFF
#define I2C_ANA_MST_ANA_STATUS2_S 24
/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
/*description: .*/
#define I2C_ANA... | 1,350 |
*/
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S))
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_B... | 1,350 |
*/
#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11))
#define I2C_ANA_MST_ARBITER_DIS_V 0x1
#define I2C_ANA_MST_ARBITER_DIS_S 11
/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
/*description: .*/
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F
#... | 1,350 |
*/
#define I2C_ANA_MST_NOUSE 0xFFFFFFFF
#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S))
#define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF
#define I2C_ANA_MST_NOUSE_S 0
#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
/*descrip... | 1,350 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/regdma.h"
#ifdef __cplusplus
extern "C"
{
#endif
#if SOC_PAU_SUPPORTED // TODO: [ESP32C5] IDF-8640
/**
*/
#define INT_MTX_RETENTION_LINK_LEN 1
extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN];
/**
*... | 1,355 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of config0 register
*/
typedef union {
struct {
/** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20;
*/
uint32_t wdt_chip_reset_width:8;
/** wdt_chip_reset_en : ... | 1,363 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
*/
uint32_t set_start:1;
uint32_t reserv... | 1,366 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** rng_ck_en : R/W; bitpos: [24]; default: 1;
*/
uint32_t rng_ck_en:1;
/** otp_dbg_ck_en... | 1,367 |
/*
*/
#pragma once
// MSPI pin defined in io_mux_reg.h
// IOMUX pin for GPSPI2
#define SPI2_FUNC_NUM 2
#define SPI2_IOMUX_PIN_NUM_MISO 2
#define SPI2_IOMUX_PIN_NUM_HD 4
#define SPI2_IOMUX_PIN_NUM_WP 5
#define SPI2_IOMUX_PIN_NUM_CLK 6
#define SPI2_IOMUX_PIN_NUM_MOSI 7
#define SPI2_IOMUX_PIN_NUM_CS 1... | 1,368 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control and configuration registers */
/** Type of tx_inst_cfg0 register
*/
typedef union {
struct {
/** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t tx_inst_idx:3;
/** tx_inst_pos : R/W... | 1,369 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitp... | 1,370 |
/*
*/
#pragma once
/**
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 0
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 4
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 5
#define I2C_B... | 1,371 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitp... | 1,373 |
/*
*/
/*
*/
#pragma once
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"
| 1,375 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** I2S_INT_RAW_REG register
*/
#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define I2S_RX_DONE_INT_RAW (BIT(0))
#define I2S_RX_DONE_INT_RAW_M (I2S_RX_D... | 1,377 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC... | 1,378 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: key register */
/** Type of key_0 register
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_0_reg_t;
/** Type of key_1 regist... | 1,379 |
/*
*/
#ifndef _SOC_ICG_MAP_H_
#define _SOC_ICG_MAP_H_
#define PMU_ICG_APB_ENA_CAN0 18
#define PMU_ICG_APB_ENA_CAN1 19
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_I2C 13
#define PMU_ICG_A... | 1,381 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
*/
uint32_t work_mode:2;
/** ecc_curve : R/... | 1,382 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
// TODO: [ESP32C5] IDF-8824
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x600AF818
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
#define... | 1,387 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_ANA_BOD_MODE0_CNTL_REG register
*/
#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
*/
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6... | 1,388 |
/*
*/
#pragma once
#define EXT_ADC_START_IDX 0
#define LEDC_LS_SIG_OUT0_IDX 0
#define LEDC_LS_SIG_OUT1_IDX 1
#define LEDC_LS_SIG_OUT2_IDX 2
#define LEDC_LS_SIG_OUT3_IDX 3
#define LEDC_LS_SIG_OUT4_IDX ... | 1,390 |
/*
*/
#ifndef _SOC_MODEM_SYSCON_REG_H_
#define _SOC_MODEM_SYSCON_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "reg_base.h"
#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0)
/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define... | 1,392 |
*/
#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31))
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (BIT(31))
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x1
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31
/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BLE_TIMER_... | 1,392 |
*/
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27))
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (BIT(27))
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x1
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27
/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_S... | 1,392 |
*/
#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23))
#define MODEM_SYSCON_CLK_ZB_APB_EN_M (BIT(23))
#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x1
#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23
/* MODEM_SYSCON_CLK_ETM_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_ETM_EN (BIT(22))
#define ... | 1,392 |
*/
#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30))
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (BIT(30))
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x1
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30
/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_MODEM_SEC_... | 1,392 |
*/
#define MODEM_SYSCON_CLK_ZBMAC_FO (BIT(8))
#define MODEM_SYSCON_CLK_ZBMAC_FO_M (BIT(8))
#define MODEM_SYSCON_CLK_ZBMAC_FO_V 0x1
#define MODEM_SYSCON_CLK_ZBMAC_FO_S 8
/* MODEM_SYSCON_CLK_BT_APB_FO : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(7))
#define MOD... | 1,392 |
*/
#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(4))
#define MODEM_SYSCON_CLK_FE_APB_FO_M (BIT(4))
#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x1
#define MODEM_SYSCON_CLK_FE_APB_FO_S 4
/* MODEM_SYSCON_CLK_FE_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_FO (BIT(3))
#define MODEM_S... | 1,392 |
*/
#define MODEM_SYSCON_CLK_WIFIBB_FO (BIT(0))
#define MODEM_SYSCON_CLK_WIFIBB_FO_M (BIT(0))
#define MODEM_SYSCON_CLK_WIFIBB_FO_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_FO_S 0
#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xC)
/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W ;bitpos:[31:... | 1,392 |
*/
#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000F
#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M ((MODEM_SYSCON_CLK_WIFI_ST_MAP_V)<<(MODEM_SYSCON_CLK_WIFI_ST_MAP_S))
#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0xF
#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20
/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; *... | 1,392 |
*/
#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31))
#define MODEM_SYSCON_RST_DATA_DUMP_M (BIT(31))
#define MODEM_SYSCON_RST_DATA_DUMP_V 0x1
#define MODEM_SYSCON_RST_DATA_DUMP_S 31
/* MODEM_SYSCON_RST_BLE_TIMER : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30))
#d... | 1,392 |
*/
#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26))
#define MODEM_SYSCON_RST_MODEM_CCM_M (BIT(26))
#define MODEM_SYSCON_RST_MODEM_CCM_V 0x1
#define MODEM_SYSCON_RST_MODEM_CCM_S 26
/* MODEM_SYSCON_RST_MODEM_ECB : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25))
#d... | 1,392 |
*/
#define MODEM_SYSCON_RST_BTBB (BIT(18))
#define MODEM_SYSCON_RST_BTBB_M (BIT(18))
#define MODEM_SYSCON_RST_BTBB_V 0x1
#define MODEM_SYSCON_RST_BTBB_S 18
/* MODEM_SYSCON_RST_BTBB_APB : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_BTBB_APB (BIT(17))
#define MODEM_SYSCON_RST... | 1,392 |
*/
#define MODEM_SYSCON_RST_FE (BIT(14))
#define MODEM_SYSCON_RST_FE_M (BIT(14))
#define MODEM_SYSCON_RST_FE_V 0x1
#define MODEM_SYSCON_RST_FE_S 14
/* MODEM_SYSCON_RST_FE_AHB : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_FE_AHB (BIT(13))
#define MODEM_SYSCON_RST_FE_AHB_M (... | 1,392 |
*/
#define MODEM_SYSCON_RST_WIFIMAC (BIT(9))
#define MODEM_SYSCON_RST_WIFIMAC_M (BIT(9))
#define MODEM_SYSCON_RST_WIFIMAC_V 0x1
#define MODEM_SYSCON_RST_WIFIMAC_S 9
/* MODEM_SYSCON_RST_WIFIBB : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_WIFIBB (BIT(8))
#define MODEM_SYSCON_... | 1,392 |
*/
#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN (BIT(19))
#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M (BIT(19))
#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V 0x1
#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S 19
/* MODEM_SYSCON_CLK_BTMAC_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BT... | 1,392 |
*/
#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(15))
#define MODEM_SYSCON_CLK_FE_APB_EN_M (BIT(15))
#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x1
#define MODEM_SYSCON_CLK_FE_APB_EN_S 15
/* MODEM_SYSCON_CLK_FE_160M_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14))
... | 1,392 |
*/
#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11))
#define MODEM_SYSCON_CLK_FE_20M_EN_M (BIT(11))
#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x1
#define MODEM_SYSCON_CLK_FE_20M_EN_S 11
/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)... | 1,392 |
*/
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7))
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (BIT(7))
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7
/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFI... | 1,392 |
*/
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3))
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (BIT(3))
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3
/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIBB_44... | 1,392 |
*/
#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFF
#define MODEM_SYSCON_WIFI_BB_CFG_M ((MODEM_SYSCON_WIFI_BB_CFG_V)<<(MODEM_SYSCON_WIFI_BB_CFG_S))
#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF
#define MODEM_SYSCON_WIFI_BB_CFG_S 0
#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x1C)
/* MOD... | 1,392 |
*/
#define MODEM_SYSCON_DATE 0x0FFFFFFF
#define MODEM_SYSCON_DATE_M ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S))
#define MODEM_SYSCON_DATE_V 0xFFFFFFF
#define MODEM_SYSCON_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_MODEM_SYSCON_REG_H_ */
| 1,392 |
/*
*/
#pragma once
#define DR_REG_MODEM_SYSCON_BASE 0x600A9800
#define DR_REG_MODEM_LPCON_BASE 0x600AF000
| 1,393 |
/*
*/
#ifndef _SOC_MODEM_LPCON_REG_H_
#define _SOC_MODEM_LPCON_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "modem/reg_base.h"
#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_... | 1,394 |
*/
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2
/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_L... | 1,394 |
*/
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S))
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4
/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpo... | 1,394 |
*/
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0))
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0))
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0
#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC)
/* MODEM_LPCON_CLK... | 1,394 |
*/
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2
/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#defi... | 1,394 |
*/
#define MODEM_LPCON_CLK_I2C_MST_SEL_160M (BIT(0))
#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_M (BIT(0))
#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_V 0x1
#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_S 0
#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
/* MODEM_LPCON_CLK_MODEM_32K_SE... | 1,394 |
*/
#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2))
#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2))
#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1
#define MODEM_LPCON_CLK_I2C_MST_EN_S 2
/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_COEX_EN (BIT(1))
#define MODEM... | 1,394 |
*/
#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3))
#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3))
#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1
#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3
/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2))
#de... | 1,394 |
*/
#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S))
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28
/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default... | 1,394 |
*/
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S))
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16
#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_L... | 1,394 |
*/
#define MODEM_LPCON_RST_WIFIPWR (BIT(0))
#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0))
#define MODEM_LPCON_RST_WIFIPWR_V 0x1
#define MODEM_LPCON_RST_WIFIPWR_S 0
#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28)
/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W ;bitpos:[5:0] ;default: 6'd39 ; *... | 1,394 |
*/
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU (BIT(10))
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M (BIT(10))
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V 0x1
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S 10
/* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: .*/
#define MODEM... | 1,394 |
*/
#define MODEM_LPCON_BC_MEM_FORCE_PU (BIT(6))
#define MODEM_LPCON_BC_MEM_FORCE_PU_M (BIT(6))
#define MODEM_LPCON_BC_MEM_FORCE_PU_V 0x1
#define MODEM_LPCON_BC_MEM_FORCE_PU_S 6
/* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_PBUS_MEM_FORCE_PD (BIT(5... | 1,394 |
*/
#define MODEM_LPCON_AGC_MEM_FORCE_PU (BIT(2))
#define MODEM_LPCON_AGC_MEM_FORCE_PU_M (BIT(2))
#define MODEM_LPCON_AGC_MEM_FORCE_PU_V 0x1
#define MODEM_LPCON_AGC_MEM_FORCE_PU_S 2
/* MODEM_LPCON_DC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_DC_MEM_FORCE_PD (BIT(1... | 1,394 |
*/
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFF
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S))
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFF
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S 0
#define MODEM_LPCON_DATE_RE... | 1,394 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t clk_en : 1;
uint32_t modem_ant_force_sel_bt : 1;
uint32_t modem_ant_force_sel_wifi : 1;
uint32_t reserv... | 1,395 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interru... | 1,397 |
*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level,... | 1,397 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output *... | 1,399 |
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