text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define PCNT_CNT_H_LIM_U4 0x0000FFFF
#define PCNT_CNT_H_LIM_U4_M ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S))
#define PCNT_CNT_H_LIM_U4_V 0xFFFF
#define PCNT_CNT_H_LIM_U4_S 0
#define PCNT_U5_CONF0_REG (DR_REG_PCNT_BASE + 0x003c)
/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
/*de... | 1,588 |
2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
#define PCNT_CH1_POS_MODE_U5 0x00000003
#define PCNT_CH1_POS_MODE_U5_M ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S))
#define PCNT_CH1_POS_MODE_U5_V 0x3
#define PCNT_CH1_POS_MODE_U5_S 26
/* PCN... | 1,588 |
2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
#define PCNT_CH0_HCTRL_MODE_U5 0x00000003
#define PCNT_CH0_HCTRL_MODE_U5_M ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S))
#define PCNT_CH0_HCTRL_MODE_U5_V 0x3
#define PCNT_CH0_HCTRL_MODE_U5_S 20
/* ... | 1,588 |
*/
#define PCNT_THR_THRES1_EN_U5 (BIT(15))
#define PCNT_THR_THRES1_EN_U5_M (BIT(15))
#define PCNT_THR_THRES1_EN_U5_V 0x1
#define PCNT_THR_THRES1_EN_U5_S 15
/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: This is the enable bit for comparing unit5's count with thres0 value.*/
#define ... | 1,588 |
*/
#define PCNT_THR_ZERO_EN_U5 (BIT(11))
#define PCNT_THR_ZERO_EN_U5_M (BIT(11))
#define PCNT_THR_ZERO_EN_U5_V 0x1
#define PCNT_THR_ZERO_EN_U5_S 11
/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: This is the enable bit for filtering input signals for unit5.*/
#define PCNT_FILTER_EN_U5 (B... | 1,588 |
*/
#define PCNT_CNT_THRES1_U5 0x0000FFFF
#define PCNT_CNT_THRES1_U5_M ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S))
#define PCNT_CNT_THRES1_U5_V 0xFFFF
#define PCNT_CNT_THRES1_U5_S 16
/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
/*description: This register is used to configure thres0 value fo... | 1,588 |
*/
#define PCNT_CNT_H_LIM_U5 0x0000FFFF
#define PCNT_CNT_H_LIM_U5_M ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S))
#define PCNT_CNT_H_LIM_U5_V 0xFFFF
#define PCNT_CNT_H_LIM_U5_S 0
#define PCNT_U6_CONF0_REG (DR_REG_PCNT_BASE + 0x0048)
/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
/*de... | 1,588 |
2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
#define PCNT_CH1_POS_MODE_U6 0x00000003
#define PCNT_CH1_POS_MODE_U6_M ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S))
#define PCNT_CH1_POS_MODE_U6_V 0x3
#define PCNT_CH1_POS_MODE_U6_S 26
/* PCN... | 1,588 |
2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
#define PCNT_CH0_HCTRL_MODE_U6 0x00000003
#define PCNT_CH0_HCTRL_MODE_U6_M ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S))
#define PCNT_CH0_HCTRL_MODE_U6_V 0x3
#define PCNT_CH0_HCTRL_MODE_U6_S 20
/* ... | 1,588 |
*/
#define PCNT_THR_THRES1_EN_U6 (BIT(15))
#define PCNT_THR_THRES1_EN_U6_M (BIT(15))
#define PCNT_THR_THRES1_EN_U6_V 0x1
#define PCNT_THR_THRES1_EN_U6_S 15
/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: This is the enable bit for comparing unit6's count with thres0 value.*/
#define ... | 1,588 |
*/
#define PCNT_THR_ZERO_EN_U6 (BIT(11))
#define PCNT_THR_ZERO_EN_U6_M (BIT(11))
#define PCNT_THR_ZERO_EN_U6_V 0x1
#define PCNT_THR_ZERO_EN_U6_S 11
/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: This is the enable bit for filtering input signals for unit6.*/
#define PCNT_FILTER_EN_U6 (B... | 1,588 |
*/
#define PCNT_CNT_THRES1_U6 0x0000FFFF
#define PCNT_CNT_THRES1_U6_M ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S))
#define PCNT_CNT_THRES1_U6_V 0xFFFF
#define PCNT_CNT_THRES1_U6_S 16
/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
/*description: This register is used to configure thres0 value fo... | 1,588 |
*/
#define PCNT_CNT_H_LIM_U6 0x0000FFFF
#define PCNT_CNT_H_LIM_U6_M ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S))
#define PCNT_CNT_H_LIM_U6_V 0xFFFF
#define PCNT_CNT_H_LIM_U6_S 0
#define PCNT_U7_CONF0_REG (DR_REG_PCNT_BASE + 0x0054)
/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
/*de... | 1,588 |
2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
#define PCNT_CH1_POS_MODE_U7 0x00000003
#define PCNT_CH1_POS_MODE_U7_M ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S))
#define PCNT_CH1_POS_MODE_U7_V 0x3
#define PCNT_CH1_POS_MODE_U7_S 26
/* PCN... | 1,588 |
2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
#define PCNT_CH0_HCTRL_MODE_U7 0x00000003
#define PCNT_CH0_HCTRL_MODE_U7_M ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S))
#define PCNT_CH0_HCTRL_MODE_U7_V 0x3
#define PCNT_CH0_HCTRL_MODE_U7_S 20
/* ... | 1,588 |
*/
#define PCNT_THR_THRES1_EN_U7 (BIT(15))
#define PCNT_THR_THRES1_EN_U7_M (BIT(15))
#define PCNT_THR_THRES1_EN_U7_V 0x1
#define PCNT_THR_THRES1_EN_U7_S 15
/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: This is the enable bit for comparing unit7's count with thres0 value.*/
#define ... | 1,588 |
*/
#define PCNT_THR_ZERO_EN_U7 (BIT(11))
#define PCNT_THR_ZERO_EN_U7_M (BIT(11))
#define PCNT_THR_ZERO_EN_U7_V 0x1
#define PCNT_THR_ZERO_EN_U7_S 11
/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: This is the enable bit for filtering input signals for unit7.*/
#define PCNT_FILTER_EN_U7 (B... | 1,588 |
*/
#define PCNT_CNT_THRES1_U7 0x0000FFFF
#define PCNT_CNT_THRES1_U7_M ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S))
#define PCNT_CNT_THRES1_U7_V 0xFFFF
#define PCNT_CNT_THRES1_U7_S 16
/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
/*description: This register is used to configure thres0 value fo... | 1,588 |
*/
#define PCNT_CNT_H_LIM_U7 0x0000FFFF
#define PCNT_CNT_H_LIM_U7_M ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S))
#define PCNT_CNT_H_LIM_U7_V 0xFFFF
#define PCNT_CNT_H_LIM_U7_S 0
#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0060)
/* PCNT_PLUS_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description... | 1,588 |
*/
#define PCNT_PLUS_CNT_U2 0x0000FFFF
#define PCNT_PLUS_CNT_U2_M ((PCNT_PLUS_CNT_U2_V)<<(PCNT_PLUS_CNT_U2_S))
#define PCNT_PLUS_CNT_U2_V 0xFFFF
#define PCNT_PLUS_CNT_U2_S 0
#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x006c)
/* PCNT_PLUS_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: This... | 1,588 |
*/
#define PCNT_PLUS_CNT_U5 0x0000FFFF
#define PCNT_PLUS_CNT_U5_M ((PCNT_PLUS_CNT_U5_V)<<(PCNT_PLUS_CNT_U5_S))
#define PCNT_PLUS_CNT_U5_V 0xFFFF
#define PCNT_PLUS_CNT_U5_S 0
#define PCNT_U6_CNT_REG (DR_REG_PCNT_BASE + 0x0078)
/* PCNT_PLUS_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: This... | 1,588 |
*/
#define PCNT_CNT_THR_EVENT_U7_INT_RAW (BIT(7))
#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M (BIT(7))
#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V 0x1
#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S 7
/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: This is the interrupt raw bit for channel6 eve... | 1,588 |
*/
#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3))
#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3))
#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1
#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3
/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the interrupt raw bit for channel2 eve... | 1,588 |
*/
#define PCNT_CNT_THR_EVENT_U7_INT_ST (BIT(7))
#define PCNT_CNT_THR_EVENT_U7_INT_ST_M (BIT(7))
#define PCNT_CNT_THR_EVENT_U7_INT_ST_V 0x1
#define PCNT_CNT_THR_EVENT_U7_INT_ST_S 7
/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: This is the interrupt status bit for channel6 even... | 1,588 |
*/
#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3))
#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3))
#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1
#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3
/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the interrupt status bit for channel2 even... | 1,588 |
*/
#define PCNT_CNT_THR_EVENT_U7_INT_ENA (BIT(7))
#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M (BIT(7))
#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V 0x1
#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S 7
/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: This is the interrupt enable bit for channel... | 1,588 |
*/
#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3))
#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3))
#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1
#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3
/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the interrupt enable bit for channel... | 1,588 |
*/
#define PCNT_CNT_THR_EVENT_U7_INT_CLR (BIT(7))
#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M (BIT(7))
#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V 0x1
#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S 7
/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to clear channel6 event interrupt... | 1,588 |
*/
#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3))
#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3))
#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1
#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3
/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to clear channel2 event interrupt... | 1,588 |
*/
#define PCNT_CNT_PAUSE_U7 (BIT(15))
#define PCNT_CNT_PAUSE_U7_M (BIT(15))
#define PCNT_CNT_PAUSE_U7_V 0x1
#define PCNT_CNT_PAUSE_U7_S 15
/* PCNT_PLUS_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */
/*description: Set this bit to clear unit7's counter.*/
#define PCNT_PLUS_CNT_RST_U7 (BIT(14))
#define PCNT_PLUS... | 1,588 |
*/
#define PCNT_CNT_PAUSE_U5 (BIT(11))
#define PCNT_CNT_PAUSE_U5_M (BIT(11))
#define PCNT_CNT_PAUSE_U5_V 0x1
#define PCNT_CNT_PAUSE_U5_S 11
/* PCNT_PLUS_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: Set this bit to clear unit5's counter.*/
#define PCNT_PLUS_CNT_RST_U5 (BIT(10))
#define PCNT_PLUS... | 1,588 |
*/
#define PCNT_CNT_PAUSE_U3 (BIT(7))
#define PCNT_CNT_PAUSE_U3_M (BIT(7))
#define PCNT_CNT_PAUSE_U3_V 0x1
#define PCNT_CNT_PAUSE_U3_S 7
/* PCNT_PLUS_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: Set this bit to clear unit3's counter.*/
#define PCNT_PLUS_CNT_RST_U3 (BIT(6))
#define PCNT_PLUS_CNT_... | 1,588 |
*/
#define PCNT_CNT_PAUSE_U1 (BIT(3))
#define PCNT_CNT_PAUSE_U1_M (BIT(3))
#define PCNT_CNT_PAUSE_U1_V 0x1
#define PCNT_CNT_PAUSE_U1_S 3
/* PCNT_PLUS_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: Set this bit to clear unit1's counter.*/
#define PCNT_PLUS_CNT_RST_U1 (BIT(2))
#define PCNT_PLUS_CNT_... | 1,588 |
/*
*/
#ifndef _SOC_SDMMC_STRUCT_H_
#define _SOC_SDMMC_STRUCT_H_
#include
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct sdmmc_desc_s {
struct {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor:... | 1,589 |
} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values
#ifndef __cplusplus
_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
#endif
typedef struct sdmmc_dev_t {
volatile union {
struct {
... | 1,589 |
uint32_t ddr: 16; ///< bit N enables DDR mode for card N
};
} uhs; ///< UHS related settings
volatile union {
struct {
uint32_t cards: 2; ///< bit N resets card N, active low
uint32_t reserved: 30;
};
} rst_n;... | 1,589 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,590 |
The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uin... | 1,590 |
An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: en... | 1,590 |
1: enable 0: disable.*/
uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_rdsr: 1; /*Read ... | 1,590 |
The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
};
uint32_t val;... | 1,590 |
1: enable 0: disable.*/
uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals.... | 1,590 |
1: enable 0: disable.*/
uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals.... | 1,590 |
*/
uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/
uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/
};
uint32_t val;
} rd_status;
... | 1,590 |
*/
uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delaye... | 1,590 |
In the slave mode it must be 0.*/
uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequenc... | 1,590 |
1: enable 0: disable.*/
uint32_t cs_setup: 1; /*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/
uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_mis... | 1,590 |
*/
uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disab... | 1,590 |
*/
uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_miso_highpart: 1... | 1,590 |
*/
uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/
uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/
};
uint32_t val;
} user;
union {
struct {
u... | 1,590 |
The register value shall be (bit_num-1)*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_dbitlen:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*r... | 1,590 |
*/
uint32_t reserved9: 2; /*reserved*/
uint32_t master_ck_sel: 3; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/
uint32_t reserved14: 15; /*reserve... | 1,590 |
*/
uint32_t rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/
uint32_t wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/
uint32... | 1,590 |
*/
uint32_t trans_inten: 1; /*The interrupt enable bit for the completion of any operation in both the master mode and the slave mode.*/
uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate... | 1,590 |
*/
uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/
};
uint32_t val;
} slave;
union {
struct {
uint32_t rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of du... | 1,590 |
The register value shall be (bit_num-1).*/
uint32_t reserved16: 9; /*reserved*/
uint32_t status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/
uint32_t status_fast_en: 1; ... | 1,590 |
The register value shall be (cycle_num-1).*/
uint32_t wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/
};
uint32_t val;
} slave2;
union {
str... | 1,590 |
The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} slv_wrbuf_dlen;
union {
struct {
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for read-buffe... | 1,590 |
*/
uint32_t reserved4: 28; /*reserved*/
};
uint32_t val;
} cache_fctrl;
union {
struct {
uint32_t reserved0: 1; /*reserved*/
uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mo... | 1,590 |
*/
uint32_t sram_dummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The regi... | 1,590 |
The bit will be cleared once the operation done.*/
uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/
uint32_t rst_io: 1; /*For ... | 1,590 |
*/
};
uint32_t val;
} sram_drd_cmd;
union {
struct {
uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/
uint32_t reserved16: 12; /*reserved*/
... | 1,590 |
*/
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
union {
struct {
... | 1,590 |
*/
uint32_t reserved20: 11; /*reserved*/
uint32_t t_erase_ena: 1; /*erase flash delay enable.*/
};
uint32_t val;
} ext1;
union {
struct {
uint32_t st: 3; /*The status of spi ... | 1,590 |
*/
uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/
uint32_t ahbm_fifo_rst: 1; /*reset spi dma ahb master fifo pointer.*/
uint32_t ahbm_rst: 1; /*reset spi dma ahb master... | 1,590 |
*/
uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/
uint32_t reserved13: 1; /*reserved*/
uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/
uint32... | 1,590 |
*/
uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} dma_out_link;
union {
struct {
uint32_t addr: 20; ... | 1,590 |
*/
uint32_t tx_en: 1; /*spi dma write data status bit.*/
uint32_t reserved2: 30; /*spi dma read data from memory count.*/
};
uint32_t val;
} dma_status;
union {
struct {
uint32_t inlink_dscr_empty: ... | 1,590 |
*/
uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
}... | 1,590 |
*/
uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The raw bit for sendin... | 1,590 |
*/
uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; ... | 1,590 |
*/
uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The clear bit for completi... | 1,590 |
*/
uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/
uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer rela... | 1,590 |
*/
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserve... | 1,590 |
*/
uint32_t reserved28: 4; /*reserved*/
};
uint32_t val;
} date;
} spi_dev_t;
extern spi_dev_t SPI0; /* SPI0 IS FOR INTERNAL USE*/
extern spi_dev_t SPI1;
extern spi_dev_t SPI2;
extern spi_dev_t SPI3;
#ifdef __cplusplus
}
#endi... | 1,590 |
/**
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
/* Write disable bits */
#define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */
#define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */
#define EFUS... | 1,591 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,593 |
Set by hw on int.
#define PROPID_TABLE_LEVEL ((PROPID_GEN_BASE)+0x028)
//PID/prev int data for each int
#define PROPID_FROM_1 ((PROPID_GEN_BASE)+0x02C)
#define PROPID_FROM_2 ((PROPID_GEN_BASE)+0x030)
#define PROPID_FROM_3 ((PROPID_GEN_BASE)+0x034)
#define PROPID_FROM_4 ((PROPID_GEN_BASE)+0x038)
#def... | 1,593 |
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,594 |
Please use the Macros above
#define HSPI_FUNC_NUM 1
#define HSPI_IOMUX_PIN_NUM_MISO 12
#define HSPI_IOMUX_PIN_NUM_MOSI 13
#define HSPI_IOMUX_PIN_NUM_CLK 14
#define HSPI_IOMUX_PIN_NUM_CS 15
#define HSPI_IOMUX_PIN_NUM_WP 2
#define HSPI_IOMUX_PIN_NUM_HD 4
#define VSPI_FUNC_NUM 1
#define VSPI_I... | 1,594 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,595 |
*/
union {
struct {
uint32_t reserved0: 30;
uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/
uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/
};
uint32_t val;
} hall_sens;
uni... | 1,595 |
Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
uint32_t fun_ie: 1; /*the input enable of the pad*/
uint32_t slp_oe: 1; /*the output enable of the pad in sleep status*/
uint32_t slp_ie: 1; ... | 1,595 |
*/
uint32_t dres_xtal_32k: 2; /*32K XTAL resistor bias control.*/
uint32_t x32p_fun_ie: 1; /*the input enable of the pad*/
uint32_t x32p_slp_oe: 1; /*the output enable of the pad in sleep status*/
uint32_t x32p_slp_ie... | 1,595 |
*/
uint32_t x32p_rue: 1; /*the pull up enable of the pad*/
uint32_t x32p_rde: 1; /*the pull down enable of the pad*/
uint32_t x32p_hold: 1; /*hold the current value of the output when setting the hold to �1�*/
... | 1,595 |
Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP this setting is available*/
uint32_t drange: 2; /*touch sensor saw wave voltage range.*/
uint32_t drefl: 2; /*touch sensor saw wave bottom voltage.*/
uint32_t drefh: 2; ... | 1,595 |
*/
uint32_t tie_opt: 1; /*default touch sensor tie option. 0: tie low 1: tie high.*/
uint32_t start: 1; /*start touch sensor.*/
uint32_t dac: 3; /*touch sensor slope control. 3-bit for each touch panel default 100.*/
uint32_t re... | 1,595 |
..�17� select GPIO17*/
};
uint32_t val;
} xtl_ext_ctr;
union {
struct {
uint32_t reserved0: 23;
uint32_t debug_bit_sel: 5;
uint32_t scl_sel: 2; /*�0� using TOUCH_PAD[0] as i2c clk �1� using TOUCH_PAD[2] as i2c clk*/
ui... | 1,595 |
/*
*/
#pragma once
/**
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 4
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_C... | 1,596 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,597 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,598 |
/*
*/
#ifndef _SOC_APB_CTRL_STRUCT_H_
#define _SOC_APB_CTRL_STRUCT_H_
#warning "apb_ctrl_struct is deprecated due to duplicated with syscon_struct, please use syscon_struct instead, they are same"
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct apb_ctrl_dev_s {
union {
struct {
... | 1,600 |
*/
volatile uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
volatile uint32_t reserved27: 5;
};
volatile uint32_t val;
}saradc_ctrl;
union {
struct {
volatile uint32_t m... | 1,600 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C"
{
#endif
#include
typedef struct emac_dma_dev_s {
volatile union {
struct {
uint32_t sw_rst : 1; /*When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after ... | 1,602 |
*/
uint32_t alt_desc_size : 1; /*When set the size of the alternate descriptor increases to 32 bytes.*/
uint32_t prog_burst_len : 6; /*These bits indicate the maximum number of beats to be transferred in one DMA transaction. If the number of beats to be transferred is more than 32 then perfor... | 1,602 |
*/
uint32_t rx_dma_pbl : 6; /*This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst tran... | 1,602 |
*/
uint32_t dmaaddralibea : 1; /*When this bit is set high and the FIXED_BURST bit is 1 the AHB interface generates all bursts aligned to the start address LS bits. If the FIXED_BURST bit is 0 the first burst (accessing the start address of data buffer) is not aligned but subsequent bursts are aligned t... | 1,602 |
If that descriptor is not available (owned by the Host) the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available the transmission resumes.*/
uint32_t dmarxpolldemand; /*When these bits are written with any value the DMA reads the current descri... | 1,602 |
Therefore these LSB bits are read-only.*/
volatile union {
struct {
uint32_t trans_int : 1; /*This bit indicates that the frame transmission is complete. When transmission is complete Bit[31] (OWN) of TDES0 is reset and the specific frame status information is updated in the Descripto... | 1,602 |
When the Jabber Timeout occurs the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.*/
uint32_t recv_ovflow : 1; /*This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame ... | 1,602 |
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