text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
The Receive Process is suspended. To resume processing Receive descriptors the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the... | 1,602 |
When this bit is set the corresponding DMA engine disables all of its bus accesses.*/
uint32_t early_recv_int : 1; /*This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whiche... | 1,602 |
*/
uint32_t norm_int_summ : 1; /*Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Recei... | 1,602 |
Transferring the TX packets data from receive buffer to host memory.*/
uint32_t trans_proc_state : 3; /*This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Transmit Command issued. 3'b001: Running. Fetching Transmit Transfer Descript... | 1,602 |
3'b101: Error during Tx DMA Descriptor Write Access. 3'b110: Error during Rx DMA Descriptor Read Access. 3'b111: Error during Tx DMA Descriptor Read Access.*/
uint32_t reserved26 : 1;
uint32_t reserved27 : 1;
uint32_t pmt_int : 1; /*This bit indicates an interrupt event in the... | 1,602 |
The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared the Rx DMA operation is stopped after the transfer of the current frame.*/
uint32_t opt_second_frame : 1; /*When this bit is set it instructs the DMA to process the second frame of ... | 1,602 |
*/
uint32_t fwd_err_frame : 1; /*When this bit is reset the Rx FIFO drops frames with error status (CRC error collision error giant frame watchdog timeout or overflow).*/
uint32_t reserved8 : 1;
uint32_t reserved9 : 2;
uint32_t reserved11 : 2;
uint32_t... | 1,602 |
3'b000: 64 3'b001: 128 3'b010: 192 3'b011: 256 3'b100: 40 3'b101: 32 3'b110: 24 3'b111: 16 .*/
uint32_t reserved17 : 3;
uint32_t flush_tx_fifo : 1; /*When this bit is set the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flu... | 1,602 |
*/
uint32_t dis_drop_tcpip_err_fram : 1; /*When this bit is set the MAC does not drop the frames which only have errors detected by the Receive Checksum engine.When this bit is reset all error frames are dropped if the Fwd_Err_Frame bit is reset.*/
uint32_t reserved27 : 5;
};
u... | 1,602 |
*/
uint32_t dmain_tjte : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset the Transmit Jabber Timeout Interrupt is disabled.*/
uint32_t dmain_oie : 1; /*When this bit is set with Abnormal Interr... | 1,602 |
When this bit is reset the Receive Buffer Unavailable Interrupt is disabled.*/
uint32_t dmain_rse : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped Interrupt is disabled.*/
uint32... | 1,602 |
*/
uint32_t dmain_erie : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Early Receive Interrupt is enabled. When this bit is reset the Early Receive Interrupt is disabled.*/
uint32_t dmain_aise : 1; /*When this bit is set abnormal interrupt summary is enabled. Wh... | 1,602 |
Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt.*/
uint32_t reserved17 : 15;
};
uint32_t val;
} dmain_en;
volatile union {
struct {
uint32_t missed_fc : 16; /*This field indicates the number of frames missed by the controller because of the Host ... | 1,602 |
The counter is cleared when this register is read.*/
uint32_t overflow_bfoc : 1; /*This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows that is the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario the overflow frame counter is reset to all-z... | 1,602 |
*/
uint32_t reserved8 : 24;
};
uint32_t val;
} dmarintwdtimer;
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t reserved_34;
uint32_t reserved_38;
uint32_t reserved_3c;
uint32_t reserved_40;
uint32_t reserved_44;
uint32_t dmat... | 1,602 |
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,603 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,606 |
0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/
#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003
#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3
#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30
/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;de... | 1,608 |
00: div128 01: div256 10: div512 11: div1024.*/
#define RTC_CNTL_CK8M_DIV 0x00000003
#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
#define RTC_CNTL_CK8M_DIV_V 0x3
#define RTC_CNTL_CK8M_DIV_S 4
#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74)
/* RTC_CNTL_XPD_SDIO... | 1,608 |
Only active when reg_sdio_force = 1*/
#define RTC_CNTL_DREFM_SDIO 0x00000003
#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S))
#define RTC_CNTL_DREFM_SDIO_V 0x3
#define RTC_CNTL_DREFM_SDIO_S 27
/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */
/*description: SW option... | 1,608 |
Only active when reg_sdio_force = 0*/
#define RTC_CNTL_SDIO_PD_EN (BIT(21))
#define RTC_CNTL_SDIO_PD_EN_M (BIT(21))
#define RTC_CNTL_SDIO_PD_EN_V 0x1
#define RTC_CNTL_SDIO_PD_EN_S 21
#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78)
/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; *... | 1,608 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
/* Clear to enable APLL */
#define I2C_APLL_M (BIT(14))
/* Clear to enable BBPLL */
#define I2C_BBPLL_M (BIT(17))
| 1,609 |
/*
*/
#pragma once
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK 6
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD 11
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0 7
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1 8
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2 9
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3 10
#define SDIO_SLAVE_S... | 1,610 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,612 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interru... | 1,614 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of mode register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} sha_m... | 1,615 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */... | 1,618 |
< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
G... | 1,618 |
/*
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/*CLINT MINT*/
#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0)
/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define CLINT_CPU_MINT_SIP 0xFFFFFFFF
#define CLINT_CPU_MINT_SIP_M ((CLINT_C... | 1,619 |
*/
#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_L_S 0
#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xC)
/* CLINT_CPU_MINT_MTIME_H : RO ... | 1,619 |
*/
#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_H_S 0
/*CLINT UINT*/
#define CLINT_UINT_SIP_REG (DR_REG_CLINT_U_BASE + 0x0)
/*... | 1,619 |
*/
#define CLINT_CPU_UINT_UTIME_L 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIME_L_M ((CLINT_CPU_UINT_UTIME_L_V)<<(CLINT_CPU_UINT_UTIME_L_S))
#define CLINT_CPU_UINT_UTIME_L_V 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIME_L_S 0
#define CLINT_UINT_UTIME_H_REG (DR_REG_CLINT_U_BASE + 0xC)
/* CLINT_CPU_UINT_UTIME_H : RO ... | 1,619 |
*/
#define CLINT_CPU_UINT_UTIMECMP_H 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIMECMP_H_M ((CLINT_CPU_UINT_UTIMECMP_H_V)<<(CLINT_CPU_UINT_UTIMECMP_H_S))
#define CLINT_CPU_UINT_UTIMECMP_H_V 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIMECMP_H_S 0
#ifdef __cplusplus
}
#endif
| 1,619 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RSA_M_MEM register
*/
#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
#define RSA_M_MEM_SIZE_BYTES 16
/** RSA_Z_MEM register
*/
#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
#define RSA_Z_MEM_SIZE_BYTES 16
/** RSA_Y_MEM registe... | 1,623 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KE... | 1,625 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of addr_lock register
*/
typedef union {
struct {
/** lock : R/W; bitpos: [1:0]; default: 0;
*/
uint32_t lock:2;
uint32_t reserved_2:30;
};
uint32_t val;
}... | 1,626 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
union {
struct {
uint32_t target_lo: 32;
};
uint32_t val;
} lo;
union {
struct {
uint32_t target_hi: 16;
uint32_t reserved0: 15;
uint32_t e... | 1,627 |
/*
*/
#ifndef _SOC_BOOT_MODE_H_
#define _SOC_BOOT_MODE_H_
#include "soc.h"
/*SPI Boot*/
#define IS_1XXX(v) (((v)&0x08)==0x08)
/*Download Boot, SPI(or SDIO_V2)/UART0*/
#define IS_00XX(v) (((v)&0x0c)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
#def... | 1,628 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}
#endif
| 1,629 |
See soc/i2c_struct.h
//extern lp_i2c_dev_t LP_I2C;
#ifndef __cplusplus
_Static_assert(sizeof(lp_i2c_dev_t) == 0x184, "Invalid size of lp_i2c_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif
| 1,631 |
/*
*/
#pragma once
/**
*/
#define I2C_BOD 0x61
#define I2C_BOD_HOSTID 0
#define I2C_BOD_THRESHOLD 0x5
#define I2C_BOD_THRESHOLD_MSB 2
#define I2C_BOD_THRESHOLD_LSB 0
| 1,635 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
*/
typedef union {
struct {
/** log_ena : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t log_ena:3;
/** log_mode : R/W; bitpos: [6:3]; default... | 1,636 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HM... | 1,637 |
/*
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PLIC_MXINT_CONF_REG ( 0x200013FC )
#define PLIC_UXINT_CONF_REG ( 0x200017FC )
#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#define PLIC_UXINT_PRI_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4)
/*PLIC MX*/
#defin... | 1,639 |
*/
#define PLIC_CPU_MXINT_CLEAR 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLEAR_M ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S))
#define PLIC_CPU_MXINT_CLEAR_V 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLEAR_S 0
#define PLIC_EMIP_STATUS_REG (DR_REG_PLIC_MX_BASE + 0xC)
/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;d... | 1,639 |
*/
#define PLIC_CPU_MXINT1_PRI 0x0000000F
#define PLIC_CPU_MXINT1_PRI_M ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S))
#define PLIC_CPU_MXINT1_PRI_V 0xF
#define PLIC_CPU_MXINT1_PRI_S 0
#define PLIC_MXINT2_PRI_REG (DR_REG_PLIC_MX_BASE + 0x18)
/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,639 |
*/
#define PLIC_CPU_MXINT4_PRI 0x0000000F
#define PLIC_CPU_MXINT4_PRI_M ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S))
#define PLIC_CPU_MXINT4_PRI_V 0xF
#define PLIC_CPU_MXINT4_PRI_S 0
#define PLIC_MXINT5_PRI_REG (DR_REG_PLIC_MX_BASE + 0x24)
/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,639 |
*/
#define PLIC_CPU_MXINT7_PRI 0x0000000F
#define PLIC_CPU_MXINT7_PRI_M ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S))
#define PLIC_CPU_MXINT7_PRI_V 0xF
#define PLIC_CPU_MXINT7_PRI_S 0
#define PLIC_MXINT8_PRI_REG (DR_REG_PLIC_MX_BASE + 0x30)
/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,639 |
*/
#define PLIC_CPU_MXINT10_PRI 0x0000000F
#define PLIC_CPU_MXINT10_PRI_M ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S))
#define PLIC_CPU_MXINT10_PRI_V 0xF
#define PLIC_CPU_MXINT10_PRI_S 0
#define PLIC_MXINT11_PRI_REG (DR_REG_PLIC_MX_BASE + 0x3C)
/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_MXINT13_PRI 0x0000000F
#define PLIC_CPU_MXINT13_PRI_M ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S))
#define PLIC_CPU_MXINT13_PRI_V 0xF
#define PLIC_CPU_MXINT13_PRI_S 0
#define PLIC_MXINT14_PRI_REG (DR_REG_PLIC_MX_BASE + 0x48)
/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_MXINT16_PRI 0x0000000F
#define PLIC_CPU_MXINT16_PRI_M ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S))
#define PLIC_CPU_MXINT16_PRI_V 0xF
#define PLIC_CPU_MXINT16_PRI_S 0
#define PLIC_MXINT17_PRI_REG (DR_REG_PLIC_MX_BASE + 0x54)
/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_MXINT19_PRI 0x0000000F
#define PLIC_CPU_MXINT19_PRI_M ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S))
#define PLIC_CPU_MXINT19_PRI_V 0xF
#define PLIC_CPU_MXINT19_PRI_S 0
#define PLIC_MXINT20_PRI_REG (DR_REG_PLIC_MX_BASE + 0x60)
/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_MXINT22_PRI 0x0000000F
#define PLIC_CPU_MXINT22_PRI_M ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S))
#define PLIC_CPU_MXINT22_PRI_V 0xF
#define PLIC_CPU_MXINT22_PRI_S 0
#define PLIC_MXINT23_PRI_REG (DR_REG_PLIC_MX_BASE + 0x6C)
/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_MXINT25_PRI 0x0000000F
#define PLIC_CPU_MXINT25_PRI_M ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S))
#define PLIC_CPU_MXINT25_PRI_V 0xF
#define PLIC_CPU_MXINT25_PRI_S 0
#define PLIC_MXINT26_PRI_REG (DR_REG_PLIC_MX_BASE + 0x78)
/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_MXINT28_PRI 0x0000000F
#define PLIC_CPU_MXINT28_PRI_M ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S))
#define PLIC_CPU_MXINT28_PRI_V 0xF
#define PLIC_CPU_MXINT28_PRI_S 0
#define PLIC_MXINT29_PRI_REG (DR_REG_PLIC_MX_BASE + 0x84)
/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_MXINT31_PRI 0x0000000F
#define PLIC_CPU_MXINT31_PRI_M ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S))
#define PLIC_CPU_MXINT31_PRI_V 0xF
#define PLIC_CPU_MXINT31_PRI_S 0
#define PLIC_MXINT_THRESH_REG (DR_REG_PLIC_MX_BASE + 0x90)
/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;defa... | 1,639 |
*/
#define PLIC_CPU_UXINT_ENABLE 0xFFFFFFFF
#define PLIC_CPU_UXINT_ENABLE_M ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S))
#define PLIC_CPU_UXINT_ENABLE_V 0xFFFFFFFF
#define PLIC_CPU_UXINT_ENABLE_S 0
#define PLIC_UXINT_TYPE_REG (DR_REG_PLIC_UX_BASE + 0x4)
/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31... | 1,639 |
*/
#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_S 0
#define PLIC_UXINT0_PRI_REG (DR_REG_PLIC_UX_BASE + 0x10)
/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default... | 1,639 |
*/
#define PLIC_CPU_UXINT2_PRI 0x0000000F
#define PLIC_CPU_UXINT2_PRI_M ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S))
#define PLIC_CPU_UXINT2_PRI_V 0xF
#define PLIC_CPU_UXINT2_PRI_S 0
#define PLIC_UXINT3_PRI_REG (DR_REG_PLIC_UX_BASE + 0x1C)
/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,639 |
*/
#define PLIC_CPU_UXINT5_PRI 0x0000000F
#define PLIC_CPU_UXINT5_PRI_M ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S))
#define PLIC_CPU_UXINT5_PRI_V 0xF
#define PLIC_CPU_UXINT5_PRI_S 0
#define PLIC_UXINT6_PRI_REG (DR_REG_PLIC_UX_BASE + 0x28)
/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,639 |
*/
#define PLIC_CPU_UXINT8_PRI 0x0000000F
#define PLIC_CPU_UXINT8_PRI_M ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S))
#define PLIC_CPU_UXINT8_PRI_V 0xF
#define PLIC_CPU_UXINT8_PRI_S 0
#define PLIC_UXINT9_PRI_REG (DR_REG_PLIC_UX_BASE + 0x34)
/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,639 |
*/
#define PLIC_CPU_UXINT11_PRI 0x0000000F
#define PLIC_CPU_UXINT11_PRI_M ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S))
#define PLIC_CPU_UXINT11_PRI_V 0xF
#define PLIC_CPU_UXINT11_PRI_S 0
#define PLIC_UXINT12_PRI_REG (DR_REG_PLIC_UX_BASE + 0x40)
/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_UXINT14_PRI 0x0000000F
#define PLIC_CPU_UXINT14_PRI_M ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S))
#define PLIC_CPU_UXINT14_PRI_V 0xF
#define PLIC_CPU_UXINT14_PRI_S 0
#define PLIC_UXINT15_PRI_REG (DR_REG_PLIC_UX_BASE + 0x4C)
/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_UXINT17_PRI 0x0000000F
#define PLIC_CPU_UXINT17_PRI_M ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S))
#define PLIC_CPU_UXINT17_PRI_V 0xF
#define PLIC_CPU_UXINT17_PRI_S 0
#define PLIC_UXINT18_PRI_REG (DR_REG_PLIC_UX_BASE + 0x58)
/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_UXINT20_PRI 0x0000000F
#define PLIC_CPU_UXINT20_PRI_M ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S))
#define PLIC_CPU_UXINT20_PRI_V 0xF
#define PLIC_CPU_UXINT20_PRI_S 0
#define PLIC_UXINT21_PRI_REG (DR_REG_PLIC_UX_BASE + 0x64)
/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_UXINT23_PRI 0x0000000F
#define PLIC_CPU_UXINT23_PRI_M ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S))
#define PLIC_CPU_UXINT23_PRI_V 0xF
#define PLIC_CPU_UXINT23_PRI_S 0
#define PLIC_UXINT24_PRI_REG (DR_REG_PLIC_UX_BASE + 0x70)
/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_UXINT26_PRI 0x0000000F
#define PLIC_CPU_UXINT26_PRI_M ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S))
#define PLIC_CPU_UXINT26_PRI_V 0xF
#define PLIC_CPU_UXINT26_PRI_S 0
#define PLIC_UXINT27_PRI_REG (DR_REG_PLIC_UX_BASE + 0x7C)
/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_UXINT29_PRI 0x0000000F
#define PLIC_CPU_UXINT29_PRI_M ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S))
#define PLIC_CPU_UXINT29_PRI_V 0xF
#define PLIC_CPU_UXINT29_PRI_S 0
#define PLIC_UXINT30_PRI_REG (DR_REG_PLIC_UX_BASE + 0x88)
/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,639 |
*/
#define PLIC_CPU_UXINT_THRESH 0x000000FF
#define PLIC_CPU_UXINT_THRESH_M ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S))
#define PLIC_CPU_UXINT_THRESH_V 0xFF
#define PLIC_CPU_UXINT_THRESH_S 0
#define PLIC_UXINT_CLAIM_REG (DR_REG_PLIC_UX_BASE + 0x94)
/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ... | 1,639 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of store register
*/
typedef union {
struct {
/** store : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t store:32;
};
uint32_t val;
} lp_aon_store_reg_t;
/** Type of gpi... | 1,644 |
/*
*/
#pragma once
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GP... | 1,645 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of out_data register
*/
typedef union {
struct {
/** out_data : R/W/WTC; bitpos: [7:0]; default: 0;
*/
uint32_t out_data:8;
uint32_t reserved_8:24;
};
uint32_t ... | 1,646 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_... | 1,647 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32C6 Root Clock Source
*/
/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!, F
/**
*/
typedef enum {
// For CPU doma... | 1,649 |
< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
SOC_MOD_CLK_XTAL32K, /... | 1,649 |
< SYSTIMER source clock is XTAL */
SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
} soc_periph_systimer_clk_src_t;
//////////////////////////////////////////////////GPT... | 1,649 |
< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
} soc_periph_tg_clk_src_legacy_t;
////////////////////////////////... | 1,649 |
< RMT source clock is XTAL */
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**
*/
#define SOC_TEMP_SENSOR... | 1,649 |
< UART source clock is PLL_F80M */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F... | 1,649 |
< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
*/
#define SOC_MCPWM_CAPTURE_... | 1,649 |
< Select XTAL as the source clock */
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_carrier_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
*/
#d... | 1,649 |
< Select XTAL as the source clock */
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
} soc_periph_i2c_clk_src_t;
///////////////////////////////////... | 1,649 |
< Select PLL_80M as SPI source clock */
SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock *... | 1,649 |
< Select XTAL clock as the source clock */
GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
////////////... | 1,649 |
< Select XTAL as the source clock */
ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the ... | 1,649 |
< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
... | 1,649 |
< Select RC_FAST as the source clock */
PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the source clock */
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */
} soc_periph_parlio_clk_src_t;
/////////////////////////////////////... | 1,649 |
5MHz */
CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */
CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
#ifdef __cplusplus
}
#endif
| 1,649 |
/*
*/
#define DR_REG_PLIC_MX_BASE 0x20001000
#define DR_REG_PLIC_UX_BASE 0x20001400
#define DR_REG_CLINT_M_BASE 0x20001800
#define DR_REG_CLINT_U_BASE 0x20001C00
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_U... | 1,652 |
/*
*/
#pragma once
#ifndef __ASSEMBLER__
#include
#include "esp_assert.h"
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#define PRO_CPU_NUM (0)
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6
#define REG_UART_BASE(i) ... | 1,653 |
__ASSEMBLER__ */
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader... | 1,653 |
#define SOC_DIRAM_IRAM_LOW 0x40800000
#define SOC_DIRAM_IRAM_HIGH 0x40880000
#define SOC_DIRAM_DRAM_LOW 0x40800000
#define SOC_DIRAM_DRAM_HIGH 0x40880000
#define MAP_DRAM_TO_IRAM(addr) (addr)
#define MAP_IRAM_TO_DRAM(addr) (addr)
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
#define SO... | 1,653 |
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_MEMPROT_ERR_INUM... | 1,653 |
/**
*/
#pragma once
#include "soc/lp_io_reg.h"
| 1,655 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
*/
typedef union {
struct {
/** filter_thres : R/W; bitpos: [9:0]; default: 16;
*/
uint32_t filter_thres:10;
/** filter_en : R/W; bitpos: [10];... | 1,656 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of core0_cpu_int_enable register
*/
typedef union {
struct {
/** core0_cpu_int_enable : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t core0_cpu_int_enable:32;
};
ui... | 1,658 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of set_start register
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t ... | 1,659 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of i2c0_ctrl register
*/
typedef union {
struct {
/** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
*/
uint32_t i2c0_ctrl:25;
/** i2c0_busy : RO; bitpos: [25]; default: ... | 1,662 |
/*
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH... | 1,665 |
/*
*/
#pragma once
#include "soc/interrupts.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
/* HP peripherals */
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERI... | 1,667 |
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