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<Compatible to the old version of IDF */
#define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
#define SOC_PM_SUPPORT_RTC_FAST_MEM_PD (1)
#define SOC_PM_SUPPORT_RTC_SLOW_MEM_PD (1)
#define S... | 1,577 |
*/
#define SOC_SDMMC_USE_IOMUX 1
#define SOC_SDMMC_NUM_SLOTS 2
/* WI-FI HARDWARE CAPS */
#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */
#define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */
#define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI ME... | 1,577 |
< Support Wi-Fi, BT and BLE*/
/* EMAC */
#define SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK (1) /*!< REF RMII CLK output is looped back internally */
| 1,577 |
00: div128 01: div256 10: div512 11: div1024.*/
uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/
uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/
uint32_t dig_xtal32k_en: ... | 1,578 |
0: XTAL 1: PLL 2: CK8M 3: APLL*/
uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/
uint32_t ana_clk_rtc_sel: 2; /*slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/
};
uint32_t val;
} clk_conf;
unio... | 1,578 |
Only active when reg_sdio_force = 1*/
uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
uint32_t xpd_sdio: 1; /*SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/
};
uint32_t val;
... | 1,578 |
/*
*/
#ifndef _DPORT_ACCESS_H_
#define _DPORT_ACCESS_H_
#include
#include "soc/soc_caps.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
//Registers Operation {{
// The _DPORT_xxx register read macros access DPORT memory directly (as opposed to
// DPORT_REG_READ which applies SMP-safe protections... | 1,579 |
// Note that disable interrupt need only if the chip has two cores.
// 4) If you want to make a sequence of DPORT reads,
// use DPORT_STALL_OTHER_CPU_START() macro explicitly
// and then use _DPORT_REG_READ macro while other CPU is stalled.
// After completing read operations, use DPORT_STALL_OTHER_CPU_END... | 1,579 |
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,580 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,581 |
*/
uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/
uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity err... | 1,581 |
*/
uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_co... | 1,581 |
*/
uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/
uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/
uint32_t rs485_frm_err... | 1,581 |
*/
uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/
uint32_t rxfifo_ovf: 1; ... | 1,581 |
*/
uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
uint32_t tx_brk_done: 1; ... | 1,581 |
*/
uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rxfifo_full: 1; /*... | 1,581 |
*/
uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/
uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/
uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st re... | 1,581 |
*/
uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/
uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_... | 1,581 |
*/
uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/
uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw int... | 1,581 |
*/
uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/
uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_... | 1,581 |
*/
uint32_t reserved1: 7;
uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/
uint32_t reserved16: 16;
};
uint32_t val;
} auto_baud;
union {
... | 1,581 |
*/
uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/
uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/
uint32_t txfifo_cnt: 8; /*(tx_mem_cnt... | 1,581 |
*/
uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/
};
uint32_t val;
} status;
union {
struct {
uint32_t parity: 1; /*This register is used to configure the parity check mode.... | 1,581 |
.*/
uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/
uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/
uint32_t irda_tx_en: 1; /*This is the start ... | 1,581 |
*/
uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/
uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/
uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*... | 1,581 |
0：receiver stores the data even if the received data is wrong.*/
uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/
uint32_t reserved28: 4;
};
uint32_t val;
} conf0;
union {
struct {
uin... | 1,581 |
the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/
uint32_t rx_flow_en: 1; /*This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal*/
uint32_t rx_tout_thrhd: 7; /*This register is used to configure the ti... | 1,581 |
*/
uint32_t reserved20: 12;
};
uint32_t val;
} highpulse;
union {
struct {
uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/
uint32_t reserved10: 22;
};
... | 1,581 |
*/
uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/
uint32_t reserved6: 26;
};
uint32_t val;
} flow_conf;
union {
struct {
uint32_t active_threshold:10; /*When the input ... | 1,581 |
*/
uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/
};
uint32_t val;
} swfc_conf;
union {
struct {
uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， ... | 1,581 |
*/
uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/
uint32_t rx_busy_tx_en: 1; /*1: enab... | 1,581 |
*/
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_precnt;
union {
struct {
uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register v... | 1,581 |
*/
uint32_t reserved16: 16;
};
uint32_t val;
} at_cmd_char;
union {
struct {
uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/
uint... | 1,581 |
*/
uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/
uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/
uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/
... | 1,581 |
*/
uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/
uint32_t reserved6: 26;
};
uint32_t val;
} mem_cnt_status;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edg... | 1,581 |
/*
*/
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32.
#ifndef _SOC_UART_CHANNEL_H
#define _SOC_UART_CHANNEL_H
//UART channels
#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1
#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0
#define UART_... | 1,583 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
/* Register Layout */
/* The TWAI peripheral's registers are 8bits, however the ESP32 can only access
*/
typedef volatile struct twai_dev_s {
//Configuration and Control Registers
union {
struct {
uint32_t rm: 1; ... | 1,584 |
2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; ... | 1,584 |
0 Receive Interrupt */
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
uint32_t ei: 1; /* IR.2 Error Interrupt */
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
uint32_t reserved4: 1; /* Internal Re... | 1,584 |
2 Error Interrupt Enable */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t brp_div: 1; /* THIS IS NOT AN INTERRUPT. brp_div will prescale BRP by 2. Only available on ESP32 Revision 2 or later. Reserved otherwise */
uint32_t epie:... | 1,584 |
7 Sampling*/
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; ... | 1,584 |
3 CLKOUT enable/disable */
uint32_t reserved4: 3; /* Internal Reserved. RXINTEN and CBP not supported */
uint32_t cm: 1; /* CDR.7 Register Layout. Basic:0 Extended:1 */
uint32_t reserved6: 24; /* Internal Reserved */
};
ui... | 1,584 |
/*
*/
#pragma once
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000)
#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004)
#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008)
#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c... | 1,585 |
1:mem is in low power state.*/
#define RMT_MEM_PD (BIT(30))
#define RMT_MEM_PD_M (BIT(30))
#define RMT_MEM_PD_V 0x1
#define RMT_MEM_PD_S 30
/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */
/*description: This bit is used to configure the way carrier wave is modulated
for channel0.1'b1:transmit on... | 1,585 |
*/
#define RMT_IDLE_THRES_CH0 0x0000FFFF
#define RMT_IDLE_THRES_CH0_M ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S))
#define RMT_IDLE_THRES_CH0_V 0xFFFF
#define RMT_IDLE_THRES_CH0_S 8
/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
/*description: This register is used to configure the frequency divide... | 1,585 |
*/
#define RMT_IDLE_OUT_LV_CH0 (BIT(18))
#define RMT_IDLE_OUT_LV_CH0_M (BIT(18))
#define RMT_IDLE_OUT_LV_CH0_V 0x1
#define RMT_IDLE_OUT_LV_CH0_S 18
/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
#define RMT_REF_ALWAY... | 1,585 |
*/
#define RMT_RX_FILTER_EN_CH0 (BIT(7))
#define RMT_RX_FILTER_EN_CH0_M (BIT(7))
#define RMT_RX_FILTER_EN_CH0_V 0x1
#define RMT_RX_FILTER_EN_CH0_S 7
/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to continue sending from the first data to the
last data in channel0 again... | 1,585 |
*/
#define RMT_MEM_RD_RST_CH0 (BIT(3))
#define RMT_MEM_RD_RST_CH0_M (BIT(3))
#define RMT_MEM_RD_RST_CH0_V 0x1
#define RMT_MEM_RD_RST_CH0_S 3
/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Set this bit to reset write ram address for channel0 by receiver access.*/
#define RMT_MEM_WR_RST_CH... | 1,585 |
1'b1:transmit on low output level 1'b0:transmit on high output level.*/
#define RMT_CARRIER_OUT_LV_CH1 (BIT(29))
#define RMT_CARRIER_OUT_LV_CH1_M (BIT(29))
#define RMT_CARRIER_OUT_LV_CH1_V 0x1
#define RMT_CARRIER_OUT_LV_CH1_S 29
/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */
/*description: This is t... | 1,585 |
*/
#define RMT_IDLE_THRES_CH1 0x0000FFFF
#define RMT_IDLE_THRES_CH1_M ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S))
#define RMT_IDLE_THRES_CH1_V 0xFFFF
#define RMT_IDLE_THRES_CH1_S 8
/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
/*description: This register is used to configure the frequency divide... | 1,585 |
*/
#define RMT_IDLE_OUT_LV_CH1 (BIT(18))
#define RMT_IDLE_OUT_LV_CH1_M (BIT(18))
#define RMT_IDLE_OUT_LV_CH1_V 0x1
#define RMT_IDLE_OUT_LV_CH1_S 18
/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
#define RMT_REF_ALWAY... | 1,585 |
*/
#define RMT_RX_FILTER_EN_CH1 (BIT(7))
#define RMT_RX_FILTER_EN_CH1_M (BIT(7))
#define RMT_RX_FILTER_EN_CH1_V 0x1
#define RMT_RX_FILTER_EN_CH1_S 7
/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to continue sending from the first data to the
last data in channel1 again... | 1,585 |
*/
#define RMT_MEM_RD_RST_CH1 (BIT(3))
#define RMT_MEM_RD_RST_CH1_M (BIT(3))
#define RMT_MEM_RD_RST_CH1_V 0x1
#define RMT_MEM_RD_RST_CH1_S 3
/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Set this bit to reset write ram address for channel1 by receiver access.*/
#define RMT_MEM_WR_RST_CH... | 1,585 |
1'b1:add
on low level 1'b0:add on high level.*/
#define RMT_CARRIER_OUT_LV_CH2 (BIT(29))
#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29))
#define RMT_CARRIER_OUT_LV_CH2_V 0x1
#define RMT_CARRIER_OUT_LV_CH2_S 29
/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */
/*description: This is the carrier modulation e... | 1,585 |
*/
#define RMT_IDLE_THRES_CH2 0x0000FFFF
#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S))
#define RMT_IDLE_THRES_CH2_V 0xFFFF
#define RMT_IDLE_THRES_CH2_S 8
/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
/*description: This register is used to configure the frequency divide... | 1,585 |
*/
#define RMT_IDLE_OUT_LV_CH2 (BIT(18))
#define RMT_IDLE_OUT_LV_CH2_M (BIT(18))
#define RMT_IDLE_OUT_LV_CH2_V 0x1
#define RMT_IDLE_OUT_LV_CH2_S 18
/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
#define RMT_REF_ALWAY... | 1,585 |
*/
#define RMT_RX_FILTER_EN_CH2 (BIT(7))
#define RMT_RX_FILTER_EN_CH2_M (BIT(7))
#define RMT_RX_FILTER_EN_CH2_V 0x1
#define RMT_RX_FILTER_EN_CH2_S 7
/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to continue sending from the first data to the
last data in channel2.*/
#d... | 1,585 |
*/
#define RMT_MEM_RD_RST_CH2 (BIT(3))
#define RMT_MEM_RD_RST_CH2_M (BIT(3))
#define RMT_MEM_RD_RST_CH2_V 0x1
#define RMT_MEM_RD_RST_CH2_S 3
/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Set this bit to reset write ram address for channel2 by receiver access.*/
#define RMT_MEM_WR_RST_CH... | 1,585 |
1'b1:add
on low level 1'b0:add on high level.*/
#define RMT_CARRIER_OUT_LV_CH3 (BIT(29))
#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29))
#define RMT_CARRIER_OUT_LV_CH3_V 0x1
#define RMT_CARRIER_OUT_LV_CH3_S 29
/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */
/*description: This is the carrier modulation e... | 1,585 |
*/
#define RMT_IDLE_THRES_CH3 0x0000FFFF
#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S))
#define RMT_IDLE_THRES_CH3_V 0xFFFF
#define RMT_IDLE_THRES_CH3_S 8
/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
/*description: This register is used to configure the frequency divide... | 1,585 |
*/
#define RMT_IDLE_OUT_LV_CH3 (BIT(18))
#define RMT_IDLE_OUT_LV_CH3_M (BIT(18))
#define RMT_IDLE_OUT_LV_CH3_V 0x1
#define RMT_IDLE_OUT_LV_CH3_S 18
/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
#define RMT_REF_ALWAY... | 1,585 |
*/
#define RMT_RX_FILTER_EN_CH3 (BIT(7))
#define RMT_RX_FILTER_EN_CH3_M (BIT(7))
#define RMT_RX_FILTER_EN_CH3_V 0x1
#define RMT_RX_FILTER_EN_CH3_S 7
/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to continue sending from the first data to the
last data in channel3.*/
#d... | 1,585 |
*/
#define RMT_MEM_RD_RST_CH3 (BIT(3))
#define RMT_MEM_RD_RST_CH3_M (BIT(3))
#define RMT_MEM_RD_RST_CH3_V 0x1
#define RMT_MEM_RD_RST_CH3_S 3
/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Set this bit to reset write ram address for channel3 by receiver access.*/
#define RMT_MEM_WR_RST_CH... | 1,585 |
1'b1:add
on low level 1'b0:add on high level.*/
#define RMT_CARRIER_OUT_LV_CH4 (BIT(29))
#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29))
#define RMT_CARRIER_OUT_LV_CH4_V 0x1
#define RMT_CARRIER_OUT_LV_CH4_S 29
/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */
/*description: This is the carrier modulation e... | 1,585 |
*/
#define RMT_IDLE_THRES_CH4 0x0000FFFF
#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S))
#define RMT_IDLE_THRES_CH4_V 0xFFFF
#define RMT_IDLE_THRES_CH4_S 8
/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
/*description: This register is used to configure the frequency divide... | 1,585 |
*/
#define RMT_IDLE_OUT_LV_CH4 (BIT(18))
#define RMT_IDLE_OUT_LV_CH4_M (BIT(18))
#define RMT_IDLE_OUT_LV_CH4_V 0x1
#define RMT_IDLE_OUT_LV_CH4_S 18
/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
#define RMT_REF_ALWAY... | 1,585 |
*/
#define RMT_RX_FILTER_EN_CH4 (BIT(7))
#define RMT_RX_FILTER_EN_CH4_M (BIT(7))
#define RMT_RX_FILTER_EN_CH4_V 0x1
#define RMT_RX_FILTER_EN_CH4_S 7
/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to continue sending from the first data to the
last data in channel4.*/
#d... | 1,585 |
*/
#define RMT_MEM_RD_RST_CH4 (BIT(3))
#define RMT_MEM_RD_RST_CH4_M (BIT(3))
#define RMT_MEM_RD_RST_CH4_V 0x1
#define RMT_MEM_RD_RST_CH4_S 3
/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Set this bit to reset write ram address for channel4 by receiver access.*/
#define RMT_MEM_WR_RST_CH... | 1,585 |
1'b1:add
on low level 1'b0:add on high level.*/
#define RMT_CARRIER_OUT_LV_CH5 (BIT(29))
#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29))
#define RMT_CARRIER_OUT_LV_CH5_V 0x1
#define RMT_CARRIER_OUT_LV_CH5_S 29
/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */
/*description: This is the carrier modulation e... | 1,585 |
*/
#define RMT_IDLE_THRES_CH5 0x0000FFFF
#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S))
#define RMT_IDLE_THRES_CH5_V 0xFFFF
#define RMT_IDLE_THRES_CH5_S 8
/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
/*description: This register is used to configure the frequency divide... | 1,585 |
*/
#define RMT_IDLE_OUT_LV_CH5 (BIT(18))
#define RMT_IDLE_OUT_LV_CH5_M (BIT(18))
#define RMT_IDLE_OUT_LV_CH5_V 0x1
#define RMT_IDLE_OUT_LV_CH5_S 18
/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
#define RMT_REF_ALWAY... | 1,585 |
*/
#define RMT_RX_FILTER_EN_CH5 (BIT(7))
#define RMT_RX_FILTER_EN_CH5_M (BIT(7))
#define RMT_RX_FILTER_EN_CH5_V 0x1
#define RMT_RX_FILTER_EN_CH5_S 7
/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to continue sending from the first data to the
last data in channel5.*/
#d... | 1,585 |
*/
#define RMT_MEM_RD_RST_CH5 (BIT(3))
#define RMT_MEM_RD_RST_CH5_M (BIT(3))
#define RMT_MEM_RD_RST_CH5_V 0x1
#define RMT_MEM_RD_RST_CH5_S 3
/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Set this bit to reset write ram address for channel5 by receiver access.*/
#define RMT_MEM_WR_RST_CH... | 1,585 |
1'b1:add
on low level 1'b0:add on high level.*/
#define RMT_CARRIER_OUT_LV_CH6 (BIT(29))
#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29))
#define RMT_CARRIER_OUT_LV_CH6_V 0x1
#define RMT_CARRIER_OUT_LV_CH6_S 29
/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */
/*description: This is the carrier modulation e... | 1,585 |
*/
#define RMT_IDLE_THRES_CH6 0x0000FFFF
#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S))
#define RMT_IDLE_THRES_CH6_V 0xFFFF
#define RMT_IDLE_THRES_CH6_S 8
/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
/*description: This register is used to configure the frequency divide... | 1,585 |
*/
#define RMT_IDLE_OUT_LV_CH6 (BIT(18))
#define RMT_IDLE_OUT_LV_CH6_M (BIT(18))
#define RMT_IDLE_OUT_LV_CH6_V 0x1
#define RMT_IDLE_OUT_LV_CH6_S 18
/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
#define RMT_REF_ALWAY... | 1,585 |
*/
#define RMT_RX_FILTER_EN_CH6 (BIT(7))
#define RMT_RX_FILTER_EN_CH6_M (BIT(7))
#define RMT_RX_FILTER_EN_CH6_V 0x1
#define RMT_RX_FILTER_EN_CH6_S 7
/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to continue sending from the first data to the
last data in channel6.*/
#d... | 1,585 |
*/
#define RMT_MEM_RD_RST_CH6 (BIT(3))
#define RMT_MEM_RD_RST_CH6_M (BIT(3))
#define RMT_MEM_RD_RST_CH6_V 0x1
#define RMT_MEM_RD_RST_CH6_S 3
/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Set this bit to reset write ram address for channel6 by receiver access.*/
#define RMT_MEM_WR_RST_CH... | 1,585 |
1'b1:add
on low level 1'b0:add on high level.*/
#define RMT_CARRIER_OUT_LV_CH7 (BIT(29))
#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29))
#define RMT_CARRIER_OUT_LV_CH7_V 0x1
#define RMT_CARRIER_OUT_LV_CH7_S 29
/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */
/*description: This is the carrier modulation e... | 1,585 |
*/
#define RMT_IDLE_THRES_CH7 0x0000FFFF
#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S))
#define RMT_IDLE_THRES_CH7_V 0xFFFF
#define RMT_IDLE_THRES_CH7_S 8
/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
/*description: This register is used to configure the frequency divide... | 1,585 |
*/
#define RMT_IDLE_OUT_LV_CH7 (BIT(18))
#define RMT_IDLE_OUT_LV_CH7_M (BIT(18))
#define RMT_IDLE_OUT_LV_CH7_V 0x1
#define RMT_IDLE_OUT_LV_CH7_S 18
/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
#define RMT_REF_ALWAY... | 1,585 |
*/
#define RMT_RX_FILTER_EN_CH7 (BIT(7))
#define RMT_RX_FILTER_EN_CH7_M (BIT(7))
#define RMT_RX_FILTER_EN_CH7_V 0x1
#define RMT_RX_FILTER_EN_CH7_S 7
/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to continue sending from the first data to the
last data in channel7.*/
#d... | 1,585 |
*/
#define RMT_MEM_RD_RST_CH7 (BIT(3))
#define RMT_MEM_RD_RST_CH7_M (BIT(3))
#define RMT_MEM_RD_RST_CH7_V 0x1
#define RMT_MEM_RD_RST_CH7_S 3
/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Set this bit to reset write ram address for channel7 by receiver access.*/
#define RMT_MEM_WR_RST_CH... | 1,585 |
*/
#define RMT_APB_MEM_RD_ERR_CH0 (BIT(31))
#define RMT_APB_MEM_RD_ERR_CH0_M ((RMT_APB_MEM_RD_ERR_CH0_V)<<(RMT_APB_MEM_RD_ERR_CH0_S))
#define RMT_APB_MEM_RD_ERR_CH0_V 0x1
#define RMT_APB_MEM_RD_ERR_CH0_S 31
/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: The apb write memory status bit... | 1,585 |
*/
#define RMT_MEM_FULL_CH0 (BIT(28))
#define RMT_MEM_FULL_CH0_M ((RMT_MEM_FULL_CH0_V)<<(RMT_MEM_FULL_CH0_S))
#define RMT_MEM_FULL_CH0_V 0x1
#define RMT_MEM_FULL_CH0_S 28
/* RMT_MEM_OWNER_ERR_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: When channel0 is configured for receive mode, this bit will turn to ... | 1,585 |
*/
#define RMT_MEM_RADDR_EX_CH0 0x003ff000
#define RMT_MEM_RADDR_EX_CH0_M ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S))
#define RMT_MEM_RADDR_EX_CH0_V 0x3ff
#define RMT_MEM_RADDR_EX_CH0_S 12
/* RMT_MEM_WADDR_EX_CH0 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
/*description: The current memory read address of chann... | 1,585 |
*/
#define RMT_APB_MEM_RD_ERR_CH1 (BIT(31))
#define RMT_APB_MEM_RD_ERR_CH1_M ((RMT_APB_MEM_RD_ERR_CH1_V)<<(RMT_APB_MEM_RD_ERR_CH1_S))
#define RMT_APB_MEM_RD_ERR_CH1_V 0x1
#define RMT_APB_MEM_RD_ERR_CH1_S 31
/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: The apb write memory status bit... | 1,585 |
*/
#define RMT_MEM_FULL_CH1 (BIT(28))
#define RMT_MEM_FULL_CH1_M ((RMT_MEM_FULL_CH1_V)<<(RMT_MEM_FULL_CH1_S))
#define RMT_MEM_FULL_CH1_V 0x1
#define RMT_MEM_FULL_CH1_S 28
/* RMT_MEM_OWNER_ERR_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: When channel1 is configured for receive mode, this bit will turn to ... | 1,585 |
*/
#define RMT_MEM_RADDR_EX_CH1 0x003ff000
#define RMT_MEM_RADDR_EX_CH1_M ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S))
#define RMT_MEM_RADDR_EX_CH1_V 0x3ff
#define RMT_MEM_RADDR_EX_CH1_S 12
/* RMT_MEM_WADDR_EX_CH1 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
/*description: The current memory read address of chann... | 1,585 |
*/
#define RMT_APB_MEM_RD_ERR_CH2 (BIT(31))
#define RMT_APB_MEM_RD_ERR_CH2_M ((RMT_APB_MEM_RD_ERR_CH2_V)<<(RMT_APB_MEM_RD_ERR_CH2_S))
#define RMT_APB_MEM_RD_ERR_CH2_V 0x1
#define RMT_APB_MEM_RD_ERR_CH2_S 31
/* RMT_APB_MEM_WR_ERR_CH2 : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: The apb write memory status bit... | 1,585 |
*/
#define RMT_MEM_FULL_CH2 (BIT(28))
#define RMT_MEM_FULL_CH2_M ((RMT_MEM_FULL_CH2_V)<<(RMT_MEM_FULL_CH2_S))
#define RMT_MEM_FULL_CH2_V 0x1
#define RMT_MEM_FULL_CH2_S 28
/* RMT_MEM_OWNER_ERR_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: When channel2 is configured for receive mode, this bit will turn to ... | 1,585 |
*/
#define RMT_MEM_RADDR_EX_CH2 0x003ff000
#define RMT_MEM_RADDR_EX_CH2_M ((RMT_MEM_RADDR_EX_CH2_V)<<(RMT_MEM_RADDR_EX_CH2_S))
#define RMT_MEM_RADDR_EX_CH2_V 0x3ff
#define RMT_MEM_RADDR_EX_CH2_S 12
/* RMT_MEM_WADDR_EX_CH2 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
/*description: The current memory read address of chann... | 1,585 |
*/
#define RMT_APB_MEM_RD_ERR_CH3 (BIT(31))
#define RMT_APB_MEM_RD_ERR_CH3_M ((RMT_APB_MEM_RD_ERR_CH3_V)<<(RMT_APB_MEM_RD_ERR_CH3_S))
#define RMT_APB_MEM_RD_ERR_CH3_V 0x1
#define RMT_APB_MEM_RD_ERR_CH3_S 31
/* RMT_APB_MEM_WR_ERR_CH3 : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: The apb write memory status bit... | 1,585 |
*/
#define RMT_MEM_FULL_CH3 (BIT(28))
#define RMT_MEM_FULL_CH3_M ((RMT_MEM_FULL_CH3_V)<<(RMT_MEM_FULL_CH3_S))
#define RMT_MEM_FULL_CH3_V 0x1
#define RMT_MEM_FULL_CH3_S 28
/* RMT_MEM_OWNER_ERR_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: When channel3 is configured for receive mode, this bit will turn to ... | 1,585 |
*/
#define RMT_MEM_RADDR_EX_CH3 0x003ff000
#define RMT_MEM_RADDR_EX_CH3_M ((RMT_MEM_RADDR_EX_CH3_V)<<(RMT_MEM_RADDR_EX_CH3_S))
#define RMT_MEM_RADDR_EX_CH3_V 0x3ff
#define RMT_MEM_RADDR_EX_CH3_S 12
/* RMT_MEM_WADDR_EX_CH3 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
/*description: The current memory read address of chann... | 1,585 |
*/
#define RMT_APB_MEM_RD_ERR_CH4 (BIT(31))
#define RMT_APB_MEM_RD_ERR_CH4_M ((RMT_APB_MEM_RD_ERR_CH4_V)<<(RMT_APB_MEM_RD_ERR_CH4_S))
#define RMT_APB_MEM_RD_ERR_CH4_V 0x1
#define RMT_APB_MEM_RD_ERR_CH4_S 31
/* RMT_APB_MEM_WR_ERR_CH4 : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: The apb write memory status bit... | 1,585 |
*/
#define RMT_MEM_FULL_CH4 (BIT(28))
#define RMT_MEM_FULL_CH4_M ((RMT_MEM_FULL_CH4_V)<<(RMT_MEM_FULL_CH4_S))
#define RMT_MEM_FULL_CH4_V 0x1
#define RMT_MEM_FULL_CH4_S 28
/* RMT_MEM_OWNER_ERR_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: When channel4 is configured for receive mode, this bit will turn to ... | 1,585 |
*/
#define RMT_MEM_RADDR_EX_CH4 0x003ff000
#define RMT_MEM_RADDR_EX_CH4_M ((RMT_MEM_RADDR_EX_CH4_V)<<(RMT_MEM_RADDR_EX_CH4_S))
#define RMT_MEM_RADDR_EX_CH4_V 0x3ff
#define RMT_MEM_RADDR_EX_CH4_S 12
/* RMT_MEM_WADDR_EX_CH4 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
/*description: The current memory read address of chann... | 1,585 |
*/
#define RMT_APB_MEM_RD_ERR_CH5 (BIT(31))
#define RMT_APB_MEM_RD_ERR_CH5_M ((RMT_APB_MEM_RD_ERR_CH5_V)<<(RMT_APB_MEM_RD_ERR_CH5_S))
#define RMT_APB_MEM_RD_ERR_CH5_V 0x1
#define RMT_APB_MEM_RD_ERR_CH5_S 31
/* RMT_APB_MEM_WR_ERR_CH5 : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: The apb write memory status bit... | 1,585 |
*/
#define RMT_MEM_FULL_CH5 (BIT(28))
#define RMT_MEM_FULL_CH5_M ((RMT_MEM_FULL_CH5_V)<<(RMT_MEM_FULL_CH5_S))
#define RMT_MEM_FULL_CH5_V 0x1
#define RMT_MEM_FULL_CH5_S 28
/* RMT_MEM_OWNER_ERR_CH5 : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: When channel5 is configured for receive mode, this bit will turn to ... | 1,585 |
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