text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
.*/
#define SPI_MEM_SADDR_QUAD (BIT(16))
#define SPI_MEM_SADDR_QUAD_M (BIT(16))
#define SPI_MEM_SADDR_QUAD_V 0x1
#define SPI_MEM_SADDR_QUAD_S 16
/* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */
/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi
t is the sam... | 1,695 |
.*/
#define SPI_MEM_SADDR_DUAL (BIT(12))
#define SPI_MEM_SADDR_DUAL_M (BIT(12))
#define SPI_MEM_SADDR_DUAL_V 0x1
#define SPI_MEM_SADDR_DUAL_S 12
/* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */
/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi
t is the sam... | 1,695 |
.*/
#define SPI_MEM_SWB_MODE 0x000000FF
#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
#define SPI_MEM_SWB_MODE_V 0xFF
#define SPI_MEM_SWB_MODE_S 2
/* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */
/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI ... | 1,695 |
.*/
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0
#define SPI_MEM_SRAM_DWR... | 1,695 |
.*/
#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF
#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF
#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0
#define SPI_MEM_SRAM_CLK... | 1,695 |
.*/
#define SPI_MEM_SCLKCNT_H 0x000000FF
#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
#define SPI_MEM_SCLKCNT_H_V 0xFF
#define SPI_MEM_SCLKCNT_H_S 8
/* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */
/*description: For SPI0 external RAM interface, it must be equal to spi_m... | 1,695 |
*/
#define SPI_MEM_BUF0 0xFFFFFFFF
#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
#define SPI_MEM_BUF0_V 0xFFFFFFFF
#define SPI_MEM_BUF0_S 0
#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C)
/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer.*/
#def... | 1,695 |
*/
#define SPI_MEM_BUF4 0xFFFFFFFF
#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
#define SPI_MEM_BUF4_V 0xFFFFFFFF
#define SPI_MEM_BUF4_S 0
#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C)
/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer.*/
#def... | 1,695 |
*/
#define SPI_MEM_BUF8 0xFFFFFFFF
#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
#define SPI_MEM_BUF8_V 0xFFFFFFFF
#define SPI_MEM_BUF8_S 0
#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C)
/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer.*/
#def... | 1,695 |
*/
#define SPI_MEM_BUF12 0xFFFFFFFF
#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
#define SPI_MEM_BUF12_V 0xFFFFFFFF
#define SPI_MEM_BUF12_S 0
#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C)
/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer... | 1,695 |
.*/
#define SPI_MEM_WAITI_CMD 0x0000FFFF
#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
#define SPI_MEM_WAITI_CMD_V 0xFFFF
#define SPI_MEM_WAITI_CMD_S 16
/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
/*description: The dummy cycle length when wait flash idle... | 1,695 |
It is not active when
SPI_MEM_WAITI_ADDR_EN is cleared..*/
#define SPI_MEM_WAITI_ADDR_CYCLELEN 0x00000003
#define SPI_MEM_WAITI_ADDR_CYCLELEN_M ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S))
#define SPI_MEM_WAITI_ADDR_CYCLELEN_V 0x3
#define SPI_MEM_WAITI_ADDR_CYCLELEN_S 3
/* SPI_MEM_WAITI_ADD... | 1,695 |
0: The functions of hardware wait idle and auto
Suspend/Resume are not supported..*/
#define SPI_MEM_WAITI_EN (BIT(0))
#define SPI_MEM_WAITI_EN_M (BIT(0))
#define SPI_MEM_WAITI_EN_V 0x1
#define SPI_MEM_WAITI_EN_S 0
#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C)
/* SPI_MEM_SUS_TIMEOU... | 1,695 |
0: Only need to check WIP is 0..*/
#define SPI_MEM_PER_END_EN (BIT(23))
#define SPI_MEM_PER_END_EN_M (BIT(23))
#define SPI_MEM_PER_END_EN_V 0x1
#define SPI_MEM_PER_END_EN_S 23
/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status b... | 1,695 |
.*/
#define SPI_MEM_FLASH_PES_EN (BIT(5))
#define SPI_MEM_FLASH_PES_EN_M (BIT(5))
#define SPI_MEM_FLASH_PES_EN_V 0x1
#define SPI_MEM_FLASH_PES_EN_S 5
/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
pplicati... | 1,695 |
0: SPI1 does not wait after program erase
resume command is sent..*/
#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2))
#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2))
#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1
#define SPI_MEM_FLASH_PER_WAIT_EN_S 2
/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
/*description: p... | 1,695 |
The command should be sent when SUS
/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash
..*/
#define SPI_MEM_WAIT_PESR_COMMAND 0x0000FFFF
#define SPI_MEM_WAIT_PESR_COMMAND_M ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
#define SPI_MEM_WAIT_PESR_COMMAND_V 0xFFFF
#defi... | 1,695 |
0: The bit leng
th of Program/Erase Suspend/Resume command is 8..*/
#define SPI_MEM_FLASH_PESR_CMD_2B (BIT(15))
#define SPI_MEM_FLASH_PESR_CMD_2B_M (BIT(15))
#define SPI_MEM_FLASH_PESR_CMD_2B_V 0x1
#define SPI_MEM_FLASH_PESR_CMD_2B_S 15
/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description:... | 1,695 |
1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
#define SPI_MEM_FLASH_PER_DLY_128 (BIT(5))
#define SPI_MEM_FLASH_PER_DLY_128_M (BIT(5))
#define SPI_MEM_FLASH_PER_DLY_128_... | 1,695 |
.*/
#define SPI_MEM_FLASH_RES_DLY_128 (BIT(3))
#define SPI_MEM_FLASH_RES_DLY_128_M (BIT(3))
#define SPI_MEM_FLASH_RES_DLY_128_V 0x1
#define SPI_MEM_FLASH_RES_DLY_128_S 3
/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK c... | 1,695 |
.*/
#define SPI_MEM_FLASH_SUS (BIT(0))
#define SPI_MEM_FLASH_SUS_M (BIT(0))
#define SPI_MEM_FLASH_SUS_V 0x1
#define SPI_MEM_FLASH_SUS_S 0
#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0)
/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: The enable bit for SPI_... | 1,695 |
.*/
#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8))
#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (BIT(8))
#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x1
#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8
/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The enable bit for SPI_MEM_AXI... | 1,695 |
.*/
#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4))
#define SPI_MEM_MST_ST_END_INT_ENA_M (BIT(4))
#define SPI_MEM_MST_ST_END_INT_ENA_V 0x1
#define SPI_MEM_MST_ST_END_INT_ENA_S 4
/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
#... | 1,695 |
.*/
#define SPI_MEM_PER_END_INT_ENA (BIT(0))
#define SPI_MEM_PER_END_INT_ENA_M (BIT(0))
#define SPI_MEM_PER_END_INT_ENA_V 0x1
#define SPI_MEM_PER_END_INT_ENA_S 0
#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4)
/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
/*description: ... | 1,695 |
.*/
#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8))
#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (BIT(8))
#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x1
#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8
/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
/*description: The clear bit for SPI_MEM_AXI_R... | 1,695 |
.*/
#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4))
#define SPI_MEM_MST_ST_END_INT_CLR_M (BIT(4))
#define SPI_MEM_MST_ST_END_INT_CLR_V 0x1
#define SPI_MEM_MST_ST_END_INT_CLR_S 4
/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
#de... | 1,695 |
.*/
#define SPI_MEM_PER_END_INT_CLR (BIT(0))
#define SPI_MEM_PER_END_INT_CLR_M (BIT(0))
#define SPI_MEM_PER_END_INT_CLR_V 0x1
#define SPI_MEM_PER_END_INT_CLR_S 0
#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8)
/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
/*descrip... | 1,695 |
0: Others..*/
#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9))
#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (BIT(9))
#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x1
#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9
/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The raw bit for SPI_MEM_AXI_... | 1,695 |
1: Triggered when SPI1 access
is rejected. 0: Others..*/
#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6))
#define SPI_MEM_PMS_REJECT_INT_RAW_M (BIT(6))
#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x1
#define SPI_MEM_PMS_REJECT_INT_RAW_S 6
/* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The ra... | 1,695 |
.*/
#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5))
#define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(5))
#define SPI_MEM_ECC_ERR_INT_RAW_V 0x1
#define SPI_MEM_ECC_ERR_INT_RAW_S 5
/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered w... | 1,695 |
1: Triggered when WRSR/PP/SE/BE/C
E is sent and flash is already idle. 0: Others..*/
#define SPI_MEM_WPE_END_INT_RAW (BIT(2))
#define SPI_MEM_WPE_END_INT_RAW_M (BIT(2))
#define SPI_MEM_WPE_END_INT_RAW_V 0x1
#define SPI_MEM_WPE_END_INT_RAW_S 2
/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
... | 1,695 |
.*/
#define SPI_MEM_BROWN_OUT_INT_ST (BIT(10))
#define SPI_MEM_BROWN_OUT_INT_ST_M (BIT(10))
#define SPI_MEM_BROWN_OUT_INT_ST_V 0x1
#define SPI_MEM_BROWN_OUT_INT_ST_S 10
/* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
#... | 1,695 |
.*/
#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6))
#define SPI_MEM_PMS_REJECT_INT_ST_M (BIT(6))
#define SPI_MEM_PMS_REJECT_INT_ST_V 0x1
#define SPI_MEM_PMS_REJECT_INT_ST_S 6
/* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
#define SPI_... | 1,695 |
.*/
#define SPI_MEM_WPE_END_INT_ST (BIT(2))
#define SPI_MEM_WPE_END_INT_ST_M (BIT(2))
#define SPI_MEM_WPE_END_INT_ST_V 0x1
#define SPI_MEM_WPE_END_INT_ST_S 2
/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
#define SPI_MEM_PES_END_I... | 1,695 |
.*/
#define SPI_MEM_FMEM_HYPERBUS_CA (BIT(30))
#define SPI_MEM_FMEM_HYPERBUS_CA_M (BIT(30))
#define SPI_MEM_FMEM_HYPERBUS_CA_V 0x1
#define SPI_MEM_FMEM_HYPERBUS_CA_S 30
/* SPI_MEM_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
/*description: Set this bit to enable octa_ram address out when accesses to ... | 1,695 |
.*/
#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X (BIT(27))
#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27))
#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V 0x1
#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S 27
/* SPI_MEM_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
/*description: Set this bit to enable the input of SPI_D... | 1,695 |
It is used when there is no SPI_DQS signal or
SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
egative edge of SPI_DQS..*/
#define SPI_MEM_FMEM_DDR_DQS_LOOP (BIT(21))
#define SPI_MEM_FMEM_DDR_DQS_LOOP_M (BIT(21))
#define SPI_MEM_FMEM_DDR_DQS_LOOP_V 0x1
#define SPI_MEM_FMEM_DDR_DQS_... | 1,695 |
.*/
#define SPI_MEM_FMEM_TX_DDR_MSK_EN (BIT(12))
#define SPI_MEM_FMEM_TX_DDR_MSK_EN_M (BIT(12))
#define SPI_MEM_FMEM_TX_DDR_MSK_EN_V 0x1
#define SPI_MEM_FMEM_TX_DDR_MSK_EN_S 12
/* SPI_MEM_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
/*description: It is the minimum output data length in the panda d... | 1,695 |
.*/
#define SPI_MEM_FMEM_DDR_WDAT_SWP (BIT(3))
#define SPI_MEM_FMEM_DDR_WDAT_SWP_M (BIT(3))
#define SPI_MEM_FMEM_DDR_WDAT_SWP_V 0x1
#define SPI_MEM_FMEM_DDR_WDAT_SWP_S 3
/* SPI_MEM_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/... | 1,695 |
.*/
#define SPI_MEM_SMEM_HYPERBUS_CA (BIT(30))
#define SPI_MEM_SMEM_HYPERBUS_CA_M (BIT(30))
#define SPI_MEM_SMEM_HYPERBUS_CA_V 0x1
#define SPI_MEM_SMEM_HYPERBUS_CA_S 30
/* SPI_MEM_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
/*description: Set this bit to enable octa_ram address out when accesses to ... | 1,695 |
.*/
#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X (BIT(27))
#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27))
#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_V 0x1
#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_S 27
/* SPI_MEM_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
/*description: Set this bit to enable the input of SPI_D... | 1,695 |
It is used when there is no SPI_DQS signal or
SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
egative edge of SPI_DQS..*/
#define SPI_MEM_SMEM_DDR_DQS_LOOP (BIT(21))
#define SPI_MEM_SMEM_DDR_DQS_LOOP_M (BIT(21))
#define SPI_MEM_SMEM_DDR_DQS_LOOP_V 0x1
#define SPI_MEM_SMEM_DDR_DQS_... | 1,695 |
.*/
#define SPI_MEM_SMEM_TX_DDR_MSK_EN (BIT(12))
#define SPI_MEM_SMEM_TX_DDR_MSK_EN_M (BIT(12))
#define SPI_MEM_SMEM_TX_DDR_MSK_EN_V 0x1
#define SPI_MEM_SMEM_TX_DDR_MSK_EN_S 12
/* SPI_MEM_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
/*description: It is the minimum output data length in the DDR psr... | 1,695 |
.*/
#define SPI_MEM_SMEM_DDR_WDAT_SWP (BIT(3))
#define SPI_MEM_SMEM_DDR_WDAT_SWP_M (BIT(3))
#define SPI_MEM_SMEM_DDR_WDAT_SWP_V 0x1
#define SPI_MEM_SMEM_DDR_WDAT_SWP_S 3
/* SPI_MEM_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/... | 1,695 |
0: Disable it. The flash
ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
PMS$n_SIZE_REG..*/
#define SPI_MEM_FMEM_PMS0_ECC (BIT(2))
#define SPI_MEM_FMEM_PMS0_ECC_M (BIT(2))
#define SPI_MEM_FMEM_PMS0_ECC_V 0x1
#define SPI_MEM_FMEM_PMS0_ECC_S 2
/* SPI_MEM_FMEM_PMS0_WR_ATTR : R/W ;bi... | 1,695 |
0: Disable it. The flash
ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
PMS$n_SIZE_REG..*/
#define SPI_MEM_FMEM_PMS1_ECC (BIT(2))
#define SPI_MEM_FMEM_PMS1_ECC_M (BIT(2))
#define SPI_MEM_FMEM_PMS1_ECC_V 0x1
#define SPI_MEM_FMEM_PMS1_ECC_S 2
/* SPI_MEM_FMEM_PMS1_WR_ATTR : R/W ;bi... | 1,695 |
0: Disable it. The flash
ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
PMS$n_SIZE_REG..*/
#define SPI_MEM_FMEM_PMS2_ECC (BIT(2))
#define SPI_MEM_FMEM_PMS2_ECC_M (BIT(2))
#define SPI_MEM_FMEM_PMS2_ECC_V 0x1
#define SPI_MEM_FMEM_PMS2_ECC_S 2
/* SPI_MEM_FMEM_PMS2_WR_ATTR : R/W ;bi... | 1,695 |
0: Disable it. The flash
ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
PMS$n_SIZE_REG..*/
#define SPI_MEM_FMEM_PMS3_ECC (BIT(2))
#define SPI_MEM_FMEM_PMS3_ECC_M (BIT(2))
#define SPI_MEM_FMEM_PMS3_ECC_V 0x1
#define SPI_MEM_FMEM_PMS3_ECC_S 2
/* SPI_MEM_FMEM_PMS3_WR_ATTR : R/W ;bi... | 1,695 |
*/
#define SPI_MEM_FMEM_PMS0_ADDR_S 0x03FFFFFF
#define SPI_MEM_FMEM_PMS0_ADDR_S_M ((SPI_MEM_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_FMEM_PMS0_ADDR_S_S))
#define SPI_MEM_FMEM_PMS0_ADDR_S_V 0x3FFFFFF
#define SPI_MEM_FMEM_PMS0_ADDR_S_S 0
#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x114)
/* SPI_... | 1,695 |
*/
#define SPI_MEM_FMEM_PMS3_ADDR_S 0x03FFFFFF
#define SPI_MEM_FMEM_PMS3_ADDR_S_M ((SPI_MEM_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_FMEM_PMS3_ADDR_S_S))
#define SPI_MEM_FMEM_PMS3_ADDR_S_V 0x3FFFFFF
#define SPI_MEM_FMEM_PMS3_ADDR_S_S 0
#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120)
/* SPI_... | 1,695 |
*/
#define SPI_MEM_FMEM_PMS1_SIZE 0x00003FFF
#define SPI_MEM_FMEM_PMS1_SIZE_M ((SPI_MEM_FMEM_PMS1_SIZE_V)<<(SPI_MEM_FMEM_PMS1_SIZE_S))
#define SPI_MEM_FMEM_PMS1_SIZE_V 0x3FFF
#define SPI_MEM_FMEM_PMS1_SIZE_S 0
#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x128)
/* SPI_MEM_FMEM_PMS2_S... | 1,695 |
0: Disable it. Th
e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
and SPI_SMEM_PMS$n_SIZE_REG..*/
#define SPI_MEM_SMEM_PMS0_ECC (BIT(2))
#define SPI_MEM_SMEM_PMS0_ECC_M (BIT(2))
#define SPI_MEM_SMEM_PMS0_ECC_V 0x1
#define SPI_MEM_SMEM_PMS0_ECC_S 2
/* SPI_MEM_SMEM_PMS0_WR_ATTR : ... | 1,695 |
0: Disable it. Th
e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
and SPI_SMEM_PMS$n_SIZE_REG..*/
#define SPI_MEM_SMEM_PMS1_ECC (BIT(2))
#define SPI_MEM_SMEM_PMS1_ECC_M (BIT(2))
#define SPI_MEM_SMEM_PMS1_ECC_V 0x1
#define SPI_MEM_SMEM_PMS1_ECC_S 2
/* SPI_MEM_SMEM_PMS1_WR_ATTR : ... | 1,695 |
0: Disable it. Th
e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
and SPI_SMEM_PMS$n_SIZE_REG..*/
#define SPI_MEM_SMEM_PMS2_ECC (BIT(2))
#define SPI_MEM_SMEM_PMS2_ECC_M (BIT(2))
#define SPI_MEM_SMEM_PMS2_ECC_V 0x1
#define SPI_MEM_SMEM_PMS2_ECC_S 2
/* SPI_MEM_SMEM_PMS2_WR_ATTR : ... | 1,695 |
0: Disable it. Th
e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
and SPI_SMEM_PMS$n_SIZE_REG..*/
#define SPI_MEM_SMEM_PMS3_ECC (BIT(2))
#define SPI_MEM_SMEM_PMS3_ECC_M (BIT(2))
#define SPI_MEM_SMEM_PMS3_ECC_V 0x1
#define SPI_MEM_SMEM_PMS3_ECC_S 2
/* SPI_MEM_SMEM_PMS3_WR_ATTR : ... | 1,695 |
*/
#define SPI_MEM_SMEM_PMS0_ADDR_S 0x03FFFFFF
#define SPI_MEM_SMEM_PMS0_ADDR_S_M ((SPI_MEM_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SMEM_PMS0_ADDR_S_S))
#define SPI_MEM_SMEM_PMS0_ADDR_S_V 0x3FFFFFF
#define SPI_MEM_SMEM_PMS0_ADDR_S_S 0
#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x144)
/* SPI_... | 1,695 |
*/
#define SPI_MEM_SMEM_PMS3_ADDR_S 0x03FFFFFF
#define SPI_MEM_SMEM_PMS3_ADDR_S_M ((SPI_MEM_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SMEM_PMS3_ADDR_S_S))
#define SPI_MEM_SMEM_PMS3_ADDR_S_V 0x3FFFFFF
#define SPI_MEM_SMEM_PMS3_ADDR_S_S 0
#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x150)
/* SPI_... | 1,695 |
*/
#define SPI_MEM_SMEM_PMS1_SIZE 0x00003FFF
#define SPI_MEM_SMEM_PMS1_SIZE_M ((SPI_MEM_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SMEM_PMS1_SIZE_S))
#define SPI_MEM_SMEM_PMS1_SIZE_V 0x3FFF
#define SPI_MEM_SMEM_PMS1_SIZE_S 0
#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x158)
/* SPI_MEM_SMEM_PMS2_S... | 1,695 |
*/
#define SPI_MEM_SMEM_PMS3_SIZE 0x00003FFF
#define SPI_MEM_SMEM_PMS3_SIZE_M ((SPI_MEM_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SMEM_PMS3_SIZE_S))
#define SPI_MEM_SMEM_PMS3_SIZE_V 0x3FFF
#define SPI_MEM_SMEM_PMS3_SIZE_S 0
#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x164)
/* SPI_MEM_PMS_IVD : R/SS/WTC ... | 1,695 |
0: No read access error. It is cleared by when SPI_M
EM_PMS_REJECT_INT_CLR bit is set..*/
#define SPI_MEM_PMS_ST (BIT(29))
#define SPI_MEM_PMS_ST_M (BIT(29))
#define SPI_MEM_PMS_ST_V 0x1
#define SPI_MEM_PMS_ST_S 29
/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */
/*description: 1: SPI1 write access... | 1,695 |
.*/
#define SPI_MEM_REJECT_ADDR 0x03FFFFFF
#define SPI_MEM_REJECT_ADDR_M ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S))
#define SPI_MEM_REJECT_ADDR_V 0x3FFFFFF
#define SPI_MEM_REJECT_ADDR_S 0
#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x168)
/* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ... | 1,695 |
.*/
#define SPI_MEM_USR_ECC_ADDR_EN (BIT(21))
#define SPI_MEM_USR_ECC_ADDR_EN_M (BIT(21))
#define SPI_MEM_USR_ECC_ADDR_EN_V 0x1
#define SPI_MEM_USR_ECC_ADDR_EN_S 21
/* SPI_MEM_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI ... | 1,695 |
.*/
#define SPI_MEM_FMEM_ECC_ERR_INT_EN (BIT(17))
#define SPI_MEM_FMEM_ECC_ERR_INT_EN_M (BIT(17))
#define SPI_MEM_FMEM_ECC_ERR_INT_EN_V 0x1
#define SPI_MEM_FMEM_ECC_ERR_INT_EN_S 17
/* SPI_MEM_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */
/*description: Set the error times of MSPI ECC read to gen... | 1,695 |
It is cleared by when SPI_MEM_
ECC_ERR_INT_CLR bit is set..*/
#define SPI_MEM_ECC_ERR_ADDR 0x03FFFFFF
#define SPI_MEM_ECC_ERR_ADDR_M ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S))
#define SPI_MEM_ECC_ERR_ADDR_V 0x3FFFFFF
#define SPI_MEM_ECC_ERR_ADDR_S 0
#define SPI_MEM_AXI_ERR_ADDR_REG(i) (REG_S... | 1,695 |
0: At least one AXI write transfer is pending..*/
#define SPI_MEM_WDATA_AFIFO_REMPTY (BIT(29))
#define SPI_MEM_WDATA_AFIFO_REMPTY_M (BIT(29))
#define SPI_MEM_WDATA_AFIFO_REMPTY_V 0x1
#define SPI_MEM_WDATA_AFIFO_REMPTY_S 29
/* SPI_MEM_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */
/*description: 1: AXI_... | 1,695 |
1: All AXI transfers
and SPI0 transfers are done. 0: Others..*/
#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26))
#define SPI_MEM_ALL_FIFO_EMPTY_M (BIT(26))
#define SPI_MEM_ALL_FIFO_EMPTY_V 0x1
#define SPI_MEM_ALL_FIFO_EMPTY_S 26
/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: This ... | 1,695 |
If there is no ECC region in ex
ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/
#define SPI_MEM_SMEM_ECC_ADDR_EN (BIT(20))
#define SPI_MEM_SMEM_ECC_ADDR_EN_M (BIT(20))
#define SPI_MEM_SMEM_ECC_ADDR_EN_V 0x1
#define SPI_MEM_SMEM_ECC_ADDR_EN_S 20
/* SPI_MEM_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18... | 1,695 |
.*/
#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6))
#define SPI_MEM_TIMING_CALI_UPDATE_M (BIT(6))
#define SPI_MEM_TIMING_CALI_UPDATE_V 0x1
#define SPI_MEM_TIMING_CALI_UPDATE_S 6
/* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to enable DLL for timing calibration in DDR mod... | 1,695 |
.*/
#define SPI_MEM_TIMING_CALI (BIT(1))
#define SPI_MEM_TIMING_CALI_M (BIT(1))
#define SPI_MEM_TIMING_CALI_V 0x1
#define SPI_MEM_TIMING_CALI_S 1
/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to enable timing adjust clock for all reading operations..*/
#define SPI_... | 1,695 |
*/
#define SPI_MEM_DIN7_MODE 0x00000007
#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S))
#define SPI_MEM_DIN7_MODE_V 0x7
#define SPI_MEM_DIN7_MODE_S 21
/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
/*description: the input signals are delayed by system clock cycles, 0: i... | 1,695 |
*/
#define SPI_MEM_DIN4_MODE 0x00000007
#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S))
#define SPI_MEM_DIN4_MODE_V 0x7
#define SPI_MEM_DIN4_MODE_S 12
/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
/*description: the input signals are delayed by system clock cycles, 0: in... | 1,695 |
*/
#define SPI_MEM_DIN2_MODE 0x00000007
#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
#define SPI_MEM_DIN2_MODE_V 0x7
#define SPI_MEM_DIN2_MODE_S 6
/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
/*description: the input signals are delayed by system clock cycles, 0: inpu... | 1,695 |
*/
#define SPI_MEM_DIN0_MODE 0x00000007
#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
#define SPI_MEM_DIN0_MODE_V 0x7
#define SPI_MEM_DIN0_MODE_S 0
#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x188)
/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
/*de... | 1,695 |
...*/
#define SPI_MEM_DIN6_NUM 0x00000003
#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S))
#define SPI_MEM_DIN6_NUM_V 0x3
#define SPI_MEM_DIN6_NUM_S 12
/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
/*description: the input signals are delayed by system clock cycles, 0: delay... | 1,695 |
...*/
#define SPI_MEM_DIN3_NUM 0x00000003
#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
#define SPI_MEM_DIN3_NUM_V 0x3
#define SPI_MEM_DIN3_NUM_S 6
/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
/*description: the input signals are delayed by system clock cycles, 0: delayed ... | 1,695 |
...*/
#define SPI_MEM_DIN0_NUM 0x00000003
#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
#define SPI_MEM_DIN0_NUM_V 0x3
#define SPI_MEM_DIN0_NUM_S 0
#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x18C)
/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
/*descr... | 1,695 |
*/
#define SPI_MEM_DOUT6_MODE (BIT(6))
#define SPI_MEM_DOUT6_MODE_M (BIT(6))
#define SPI_MEM_DOUT6_MODE_V 0x1
#define SPI_MEM_DOUT6_MODE_S 6
/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
/*description: the output signals are delayed by system clock cycles, 0: output without delayed
, 1: output with ... | 1,695 |
*/
#define SPI_MEM_DOUT3_MODE (BIT(3))
#define SPI_MEM_DOUT3_MODE_M (BIT(3))
#define SPI_MEM_DOUT3_MODE_V 0x1
#define SPI_MEM_DOUT3_MODE_S 3
/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: the output signals are delayed by system clock cycles, 0: output without delayed
, 1: output with ... | 1,695 |
*/
#define SPI_MEM_DOUT1_MODE (BIT(1))
#define SPI_MEM_DOUT1_MODE_M (BIT(1))
#define SPI_MEM_DOUT1_MODE_V 0x1
#define SPI_MEM_DOUT1_MODE_S 1
/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: the output signals are delayed by system clock cycles, 0: output without delayed
, 1: output with ... | 1,695 |
.*/
#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007
#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S))
#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7
#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S 2
/* SPI_MEM_SMEM_TIMING_CALI : HRO ;bitpo... | 1,695 |
*/
#define SPI_MEM_SMEM_DINS_MODE 0x00000007
#define SPI_MEM_SMEM_DINS_MODE_M ((SPI_MEM_SMEM_DINS_MODE_V)<<(SPI_MEM_SMEM_DINS_MODE_S))
#define SPI_MEM_SMEM_DINS_MODE_V 0x7
#define SPI_MEM_SMEM_DINS_MODE_S 24
/* SPI_MEM_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */
/*description: the input signals are d... | 1,695 |
*/
#define SPI_MEM_SMEM_DIN6_MODE 0x00000007
#define SPI_MEM_SMEM_DIN6_MODE_M ((SPI_MEM_SMEM_DIN6_MODE_V)<<(SPI_MEM_SMEM_DIN6_MODE_S))
#define SPI_MEM_SMEM_DIN6_MODE_V 0x7
#define SPI_MEM_SMEM_DIN6_MODE_S 18
/* SPI_MEM_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */
/*description: the input signals are d... | 1,695 |
*/
#define SPI_MEM_SMEM_DIN4_MODE 0x00000007
#define SPI_MEM_SMEM_DIN4_MODE_M ((SPI_MEM_SMEM_DIN4_MODE_V)<<(SPI_MEM_SMEM_DIN4_MODE_S))
#define SPI_MEM_SMEM_DIN4_MODE_V 0x7
#define SPI_MEM_SMEM_DIN4_MODE_S 12
/* SPI_MEM_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */
/*description: the input signals are de... | 1,695 |
*/
#define SPI_MEM_SMEM_DIN2_MODE 0x00000007
#define SPI_MEM_SMEM_DIN2_MODE_M ((SPI_MEM_SMEM_DIN2_MODE_V)<<(SPI_MEM_SMEM_DIN2_MODE_S))
#define SPI_MEM_SMEM_DIN2_MODE_V 0x7
#define SPI_MEM_SMEM_DIN2_MODE_S 6
/* SPI_MEM_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */
/*description: the input signals are dela... | 1,695 |
*/
#define SPI_MEM_SMEM_DIN0_MODE 0x00000007
#define SPI_MEM_SMEM_DIN0_MODE_M ((SPI_MEM_SMEM_DIN0_MODE_V)<<(SPI_MEM_SMEM_DIN0_MODE_S))
#define SPI_MEM_SMEM_DIN0_MODE_V 0x7
#define SPI_MEM_SMEM_DIN0_MODE_S 0
#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x198)
/* SPI_MEM_SMEM_DINS_NUM : ... | 1,695 |
...*/
#define SPI_MEM_SMEM_DIN7_NUM 0x00000003
#define SPI_MEM_SMEM_DIN7_NUM_M ((SPI_MEM_SMEM_DIN7_NUM_V)<<(SPI_MEM_SMEM_DIN7_NUM_S))
#define SPI_MEM_SMEM_DIN7_NUM_V 0x3
#define SPI_MEM_SMEM_DIN7_NUM_S 14
/* SPI_MEM_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */
/*description: the input signals are delay... | 1,695 |
...*/
#define SPI_MEM_SMEM_DIN4_NUM 0x00000003
#define SPI_MEM_SMEM_DIN4_NUM_M ((SPI_MEM_SMEM_DIN4_NUM_V)<<(SPI_MEM_SMEM_DIN4_NUM_S))
#define SPI_MEM_SMEM_DIN4_NUM_V 0x3
#define SPI_MEM_SMEM_DIN4_NUM_S 8
/* SPI_MEM_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */
/*description: the input signals are delayed ... | 1,695 |
...*/
#define SPI_MEM_SMEM_DIN1_NUM 0x00000003
#define SPI_MEM_SMEM_DIN1_NUM_M ((SPI_MEM_SMEM_DIN1_NUM_V)<<(SPI_MEM_SMEM_DIN1_NUM_S))
#define SPI_MEM_SMEM_DIN1_NUM_V 0x3
#define SPI_MEM_SMEM_DIN1_NUM_S 2
/* SPI_MEM_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: the input signals are delayed ... | 1,695 |
*/
#define SPI_MEM_SMEM_DOUTS_MODE (BIT(8))
#define SPI_MEM_SMEM_DOUTS_MODE_M (BIT(8))
#define SPI_MEM_SMEM_DOUTS_MODE_V 0x1
#define SPI_MEM_SMEM_DOUTS_MODE_S 8
/* SPI_MEM_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */
/*description: the output signals are delayed by system clock cycles, 0: output without ... | 1,695 |
*/
#define SPI_MEM_SMEM_DOUT6_MODE (BIT(6))
#define SPI_MEM_SMEM_DOUT6_MODE_M (BIT(6))
#define SPI_MEM_SMEM_DOUT6_MODE_V 0x1
#define SPI_MEM_SMEM_DOUT6_MODE_S 6
/* SPI_MEM_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */
/*description: the output signals are delayed by system clock cycles, 0: output without ... | 1,695 |
*/
#define SPI_MEM_SMEM_DOUT4_MODE (BIT(4))
#define SPI_MEM_SMEM_DOUT4_MODE_M (BIT(4))
#define SPI_MEM_SMEM_DOUT4_MODE_V 0x1
#define SPI_MEM_SMEM_DOUT4_MODE_S 4
/* SPI_MEM_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */
/*description: the output signals are delayed by system clock cycles, 0: output without ... | 1,695 |
*/
#define SPI_MEM_SMEM_DOUT2_MODE (BIT(2))
#define SPI_MEM_SMEM_DOUT2_MODE_M (BIT(2))
#define SPI_MEM_SMEM_DOUT2_MODE_V 0x1
#define SPI_MEM_SMEM_DOUT2_MODE_S 2
/* SPI_MEM_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */
/*description: the output signals are delayed by system clock cycles, 0: output without ... | 1,695 |
*/
#define SPI_MEM_SMEM_DOUT0_MODE (BIT(0))
#define SPI_MEM_SMEM_DOUT0_MODE_M (BIT(0))
#define SPI_MEM_SMEM_DOUT0_MODE_V 0x1
#define SPI_MEM_SMEM_DOUT0_MODE_S 0
#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A0)
/* SPI_MEM_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */
/*descri... | 1,695 |
.*/
#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN (BIT(16))
#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16))
#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V 0x1
#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_S 16
/* SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */
/*description: 1: SPI0 skips page corner ... | 1,695 |
.*/
#define SPI_MEM_SMEM_CS_HOLD_TIME 0x0000001F
#define SPI_MEM_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_CS_HOLD_TIME_S))
#define SPI_MEM_SMEM_CS_HOLD_TIME_V 0x1F
#define SPI_MEM_SMEM_CS_HOLD_TIME_S 7
/* SPI_MEM_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */
/*description: Fo... | 1,695 |
1: enable 0: d
isable..*/
#define SPI_MEM_SMEM_CS_SETUP (BIT(0))
#define SPI_MEM_SMEM_CS_SETUP_M (BIT(0))
#define SPI_MEM_SMEM_CS_SETUP_V 0x1
#define SPI_MEM_SMEM_CS_SETUP_S 0
#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200)
/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*descr... | 1,695 |
*/
#define SPI_MEM_MMU_ITEM_INDEX 0xFFFFFFFF
#define SPI_MEM_MMU_ITEM_INDEX_M ((SPI_MEM_MMU_ITEM_INDEX_V)<<(SPI_MEM_MMU_ITEM_INDEX_S))
#define SPI_MEM_MMU_ITEM_INDEX_V 0xFFFFFFFF
#define SPI_MEM_MMU_ITEM_INDEX_S 0
#define SPI_MEM_MMU_POWER_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x384)
/* SPI_MEM_RDN_RESULT ... | 1,695 |
*/
#define SPI_MEM_MMU_PAGE_SIZE 0x00000003
#define SPI_MEM_MMU_PAGE_SIZE_M ((SPI_MEM_MMU_PAGE_SIZE_V)<<(SPI_MEM_MMU_PAGE_SIZE_S))
#define SPI_MEM_MMU_PAGE_SIZE_V 0x3
#define SPI_MEM_MMU_PAGE_SIZE_S 3
/* SPI_MEM_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: Set this bit to force mmu-memory... | 1,695 |
*/
#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFF
#define SPI_MEM_REGISTERRND_ECO_HIGH_M ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S))
#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFF
#define SPI_MEM_REGISTERRND_ECO_HIGH_S 0
#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i) (REG_SPI_ME... | 1,695 |
/*
*/
#include "soc/hp_system_reg.h"
// TODO: IDF-5720
#include "intpri_reg.h"
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0
| 1,696 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.