text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define I2C_ANA_MST_ANA_STATUS2 0x000000FF
#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S))
#define I2C_ANA_MST_ANA_STATUS2_V 0xFF
#define I2C_ANA_MST_ANA_STATUS2_S 24
/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
/*description: .*/
#define I2C_ANA... | 1,732 |
*/
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S))
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_B... | 1,732 |
*/
#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11))
#define I2C_ANA_MST_ARBITER_DIS_V 0x1
#define I2C_ANA_MST_ARBITER_DIS_S 11
/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
/*description: .*/
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F
#... | 1,732 |
*/
#define I2C_ANA_MST_NOUSE 0xFFFFFFFF
#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S))
#define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF
#define I2C_ANA_MST_NOUSE_S 0
#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
/*descrip... | 1,732 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/regdma.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
*/
#define INT_MTX_RETENTION_LINK_LEN 1
extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN];
/**
*/
#define HP_SYSTEM_RETENTION_LINK_LEN 1
extern co... | 1,736 |
/**
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#ifdef __cplusplus
}
#endif
| 1,742 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of config0 register
*/
typedef union {
struct {
/** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20;
*/
uint32_t wdt_chip_reset_width:8;
/** wdt_chip_reset_en : ... | 1,743 |
/*
*/
#pragma once
#include "soc/soc.h"
#include "esp32c6/rom/cache.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef union {
struct {
uint32_t cat0 : 2;
uint32_t cat1 : 2;
uint32_t cat2 : 2;
uint32_t res0 : 8;
uint32_t splitaddr : 8;
uin... | 1,746 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
*/
uint32_t set_start:1;
uint32_t reserv... | 1,747 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** rng_ck_en : R/W; bitpos: [24]; default: 1;
*/
uint32_t rng_ck_en:1;
/** otp_dbg_ck_en... | 1,748 |
/*
*/
#ifndef _SOC_SPI_PINS_H_
#define _SOC_SPI_PINS_H_
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_CS 24
#define SPI_IOMUX_PIN_NUM_CLK 29
#define SPI_IOMUX_PIN_NUM_MOSI 30
#define SPI_IOMUX_PIN_NUM_MISO 25
#define SPI_IOMUX_PIN_NUM_WP 26
#define SPI_IOMUX_PIN_NUM_HD 28
#define SPI2_FUN... | 1,749 |
/**
*/
#pragma once
#include "soc/lp_io_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef lp_io_dev_t rtc_io_dev_t;
#define RTCIO LP_IO
#ifdef __cplusplus
}
#endif
| 1,750 |
/*
*/
#pragma once
/**
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 0
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_C... | 1,751 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TRACE_MEM_START_ADDR_REG register
*/
#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
/** TRACE_MEM_STAET_ADDR : R/W; bitpos: [31:0]; default: 0;
*/
#define TRACE_MEM_STAET_ADDR 0xFFFFFFFFU
#define TRACE_MEM_... | 1,752 |
/*
*/
/*
*/
#pragma once
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"
| 1,754 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** I2S_INT_RAW_REG register
*/
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define I2S_RX_DONE_INT_RAW (BIT(0))
#define I2S_RX_DONE_INT_RAW_M (I2S_R... | 1,756 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300)
/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: This field is only used to generate include file in c case. This field is useles
s. P... | 1,757 |
0: flash(default), 1: psram(reserved). Only default value can be
used..*/
#define XTS_AES_DESTINATION (BIT(0))
#define XTS_AES_DESTINATION_M (BIT(0))
#define XTS_AES_DESTINATION_V 0x1
#define XTS_AES_DESTINATION_S 0
#define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348)
/* XTS_AES_PHYSIC... | 1,757 |
This actio
n should only be asserted when manual encryption status is 0. After this action,
manual encryption status becomes 1. After calculation is done, manual encryptio
n status becomes 2..*/
#define XTS_AES_TRIGGER (BIT(0))
#define XTS_AES_TRIGGER_M (BIT(0))
#define XTS_AES_TRIGGER_V 0x1
#define XTS_AES_TRIG... | 1,757 |
After this action, manual encryption status wi
ll become 0..*/
#define XTS_AES_DESTROY (BIT(0))
#define XTS_AES_DESTROY_M (BIT(0))
#define XTS_AES_DESTROY_V 0x1
#define XTS_AES_DESTROY_S 0
#define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358)
/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */... | 1,757 |
0: Controlled by efuse bits..*/
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER (BIT(4))
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M (BIT(4))
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V 0x1
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S 4
/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description:... | 1,757 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC... | 1,758 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: key register */
/** Type of key_0 register
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_0_reg_t;
/** Type of key_1 regist... | 1,759 |
/*
*/
#ifndef _SOC_ICG_MAP_H_
#define _SOC_ICG_MAP_H_
#define PMU_ICG_APB_ENA_CAN0 18
#define PMU_ICG_APB_ENA_CAN1 19
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_I2C 13
#define PMU_ICG_A... | 1,762 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x600AF818
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
#define ANA_CONFIG_REG 0x600AF81C
... | 1,769 |
/*
*/
#pragma once
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD 18
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK 19
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0 20
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1 21
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2 22
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3 23
#define SDIO_SLAV... | 1,772 |
/*
*/
#pragma once
#define DR_REG_MODEM_SYSCON_BASE 0x600A9800
#define DR_REG_MODEM_LPCON_BASE 0x600AF000
| 1,777 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef union {
struct {
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} modem_syscon_test_conf_reg_t;
typedef union {
struct {
uint32_t reserved_0:21;
uint32_t clk_data_dump_mux:1;
... | 1,779 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef union {
struct {
uint32_t clk_en:1;
uint32_t clk_debug_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} modem_lpcon_test_conf_reg_t;
typedef union {
struct {
uint32_t clk_lp_timer_sel_osc_sl... | 1,780 |
/*
*/
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and o... | 1,781 |
< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
G... | 1,781 |
< GPIO34, input mode only */
GPIO_NUM_35 = 35, /*!< GPIO35, input mode only */
GPIO_NUM_36 = 36, /*!< GPIO36, input mode only */
GPIO_NUM_37 = 37, /*!< GPIO37, input mode only */
GPIO_NUM_38 = 38, /*!< GPIO38, input mode only */
GPIO_NUM_39 = 39, /*!< GPIO39, input mode only */
GPIO_NU... | 1,781 |
/*
*/
/**
*/
| 1,782 |
/*
*/
#pragma once
/**
*/
/**
*/
typedef enum {
SOC_MOD_CLK_APB = 1,
} soc_module_clk_t;
/**
*/
typedef enum {
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB,
SPI_CLK_SRC_APB = SOC_MOD_CLK_APB,
} soc_periph_spi_clk_src_t;
| 1,783 |
/*
*/
/*
*/
/*
*/
#pragma once
/* GPIO CAPS */
#define SOC_GPIO_IN_RANGE_MAX (65535)
#define SOC_GPIO_OUT_RANGE_MAX (65535)
/* I2C CAPS */
#define SOC_I2C_SUPPORT_SLAVE (1)
#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
| 1,784 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_PMU_INTR_SOURCE = 0,
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_LP_RTC_... | 1,785 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of mode register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} sha_m... | 1,786 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */
... | 1,789 |
< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
G... | 1,789 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define DR_REG_CLINT_M_BASE ( 0x20001800)
#define DR_REG_CLINT_U_BASE ( 0x20001C00)
/*CLINT MINT*/
#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0)
/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define CL... | 1,790 |
*/
#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_L_S 0
#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xC)
/* CLINT_CPU_MINT_MTIME_H : RO ... | 1,790 |
*/
#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_H_S 0
/*CLINT UINT*/
#define CLINT_UINT_SIP_REG (DR_REG_CLINT_U_BASE + 0x0)
/*... | 1,790 |
*/
#define CLINT_CPU_UINT_UTIME_L 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIME_L_M ((CLINT_CPU_UINT_UTIME_L_V)<<(CLINT_CPU_UINT_UTIME_L_S))
#define CLINT_CPU_UINT_UTIME_L_V 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIME_L_S 0
#define CLINT_UINT_UTIME_H_REG (DR_REG_CLINT_U_BASE + 0xC)
/* CLINT_CPU_UINT_UTIME_H : RO ... | 1,790 |
*/
#define CLINT_CPU_UINT_UTIMECMP_H 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIMECMP_H_M ((CLINT_CPU_UINT_UTIMECMP_H_V)<<(CLINT_CPU_UINT_UTIMECMP_H_S))
#define CLINT_CPU_UINT_UTIMECMP_H_V 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIMECMP_H_S 0
#ifdef __cplusplus
}
#endif
| 1,790 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RSA_M_MEM register
*/
#define RSA_M_MEM_REG (DR_REG_RSA_BASE + 0x0)
#define RSA_M_MEM_SIZE_BYTES 16
/** RSA_Z_MEM register
*/
#define RSA_Z_MEM_REG (DR_REG_RSA_BASE + 0x200)
#define RSA_Z_MEM_SIZE_BYTES 16
/** RSA_Y_MEM... | 1,793 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KE... | 1,795 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
union {
struct {
uint32_t target_lo: 32;
};
uint32_t val;
} lo;
union {
struct {
uint32_t target_hi: 16;
uint32_t reserved0: 15;
uint32_t e... | 1,796 |
/*
*/
#ifndef _SOC_BOOT_MODE_H_
#define _SOC_BOOT_MODE_H_
#include "soc.h"
/*SPI Boot*/
#define IS_1XXX(v) (((v)&0x08)==0x08)
/*Download Boot, SPI(or SDIO_V2)/UART0*/
#define IS_00XX(v) (((v)&0x0c)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
#def... | 1,797 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#define GPIO_MATRIX_INVALID (0x3A)
#ifdef __cplusplus
}
#endif
| 1,798 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [0]; default: 0;
*/
#define ECDSA_WORK_MODE (BIT(0))
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA... | 1,800 |
/*
*/
#pragma once
#include "regi2c_pmu.h"
/**
*/
#define I2C_BOD I2C_PMU
#define I2C_BOD_HOSTID I2C_PMU_HOSTID
#define I2C_PMU_OR_DREFL_VBAT 17
#define I2C_PMU_OR_DREFL_VBAT_MSB 4
#define I2C_PMU_OR_DREFL_VBAT_LSB 2
#define I2C_PMU_OR_DREFH_VBAT 17
#define I2C_PMU_OR_DREFH_VBAT_MS... | 1,805 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
*/
typedef union {
struct {
/** log_ena : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t log_ena:3;
/** log_mode : R/W; bitpos: [6:3]; default... | 1,806 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HM... | 1,807 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define DR_REG_PLIC_MX_BASE ( 0x20001000 )
#define DR_REG_PLIC_UX_BASE ( 0x20001400 )
#define PLIC_MXINT_CONF_REG ( 0x200013FC )
#define PLIC_UXINT_CONF_REG ( 0x200017FC )
#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#... | 1,809 |
*/
#define PLIC_CPU_MXINT_CLEAR 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLEAR_M ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S))
#define PLIC_CPU_MXINT_CLEAR_V 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLEAR_S 0
#define PLIC_EMIP_STATUS_REG (DR_REG_PLIC_MX_BASE + 0xC)
/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;d... | 1,809 |
*/
#define PLIC_CPU_MXINT1_PRI 0x0000000F
#define PLIC_CPU_MXINT1_PRI_M ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S))
#define PLIC_CPU_MXINT1_PRI_V 0xF
#define PLIC_CPU_MXINT1_PRI_S 0
#define PLIC_MXINT2_PRI_REG (DR_REG_PLIC_MX_BASE + 0x18)
/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,809 |
*/
#define PLIC_CPU_MXINT4_PRI 0x0000000F
#define PLIC_CPU_MXINT4_PRI_M ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S))
#define PLIC_CPU_MXINT4_PRI_V 0xF
#define PLIC_CPU_MXINT4_PRI_S 0
#define PLIC_MXINT5_PRI_REG (DR_REG_PLIC_MX_BASE + 0x24)
/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,809 |
*/
#define PLIC_CPU_MXINT7_PRI 0x0000000F
#define PLIC_CPU_MXINT7_PRI_M ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S))
#define PLIC_CPU_MXINT7_PRI_V 0xF
#define PLIC_CPU_MXINT7_PRI_S 0
#define PLIC_MXINT8_PRI_REG (DR_REG_PLIC_MX_BASE + 0x30)
/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,809 |
*/
#define PLIC_CPU_MXINT10_PRI 0x0000000F
#define PLIC_CPU_MXINT10_PRI_M ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S))
#define PLIC_CPU_MXINT10_PRI_V 0xF
#define PLIC_CPU_MXINT10_PRI_S 0
#define PLIC_MXINT11_PRI_REG (DR_REG_PLIC_MX_BASE + 0x3C)
/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_MXINT13_PRI 0x0000000F
#define PLIC_CPU_MXINT13_PRI_M ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S))
#define PLIC_CPU_MXINT13_PRI_V 0xF
#define PLIC_CPU_MXINT13_PRI_S 0
#define PLIC_MXINT14_PRI_REG (DR_REG_PLIC_MX_BASE + 0x48)
/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_MXINT16_PRI 0x0000000F
#define PLIC_CPU_MXINT16_PRI_M ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S))
#define PLIC_CPU_MXINT16_PRI_V 0xF
#define PLIC_CPU_MXINT16_PRI_S 0
#define PLIC_MXINT17_PRI_REG (DR_REG_PLIC_MX_BASE + 0x54)
/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_MXINT19_PRI 0x0000000F
#define PLIC_CPU_MXINT19_PRI_M ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S))
#define PLIC_CPU_MXINT19_PRI_V 0xF
#define PLIC_CPU_MXINT19_PRI_S 0
#define PLIC_MXINT20_PRI_REG (DR_REG_PLIC_MX_BASE + 0x60)
/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_MXINT22_PRI 0x0000000F
#define PLIC_CPU_MXINT22_PRI_M ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S))
#define PLIC_CPU_MXINT22_PRI_V 0xF
#define PLIC_CPU_MXINT22_PRI_S 0
#define PLIC_MXINT23_PRI_REG (DR_REG_PLIC_MX_BASE + 0x6C)
/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_MXINT25_PRI 0x0000000F
#define PLIC_CPU_MXINT25_PRI_M ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S))
#define PLIC_CPU_MXINT25_PRI_V 0xF
#define PLIC_CPU_MXINT25_PRI_S 0
#define PLIC_MXINT26_PRI_REG (DR_REG_PLIC_MX_BASE + 0x78)
/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_MXINT28_PRI 0x0000000F
#define PLIC_CPU_MXINT28_PRI_M ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S))
#define PLIC_CPU_MXINT28_PRI_V 0xF
#define PLIC_CPU_MXINT28_PRI_S 0
#define PLIC_MXINT29_PRI_REG (DR_REG_PLIC_MX_BASE + 0x84)
/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_MXINT31_PRI 0x0000000F
#define PLIC_CPU_MXINT31_PRI_M ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S))
#define PLIC_CPU_MXINT31_PRI_V 0xF
#define PLIC_CPU_MXINT31_PRI_S 0
#define PLIC_MXINT_THRESH_REG (DR_REG_PLIC_MX_BASE + 0x90)
/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;defa... | 1,809 |
*/
#define PLIC_CPU_UXINT_ENABLE 0xFFFFFFFF
#define PLIC_CPU_UXINT_ENABLE_M ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S))
#define PLIC_CPU_UXINT_ENABLE_V 0xFFFFFFFF
#define PLIC_CPU_UXINT_ENABLE_S 0
#define PLIC_UXINT_TYPE_REG (DR_REG_PLIC_UX_BASE + 0x4)
/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31... | 1,809 |
*/
#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_S 0
#define PLIC_UXINT0_PRI_REG (DR_REG_PLIC_UX_BASE + 0x10)
/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default... | 1,809 |
*/
#define PLIC_CPU_UXINT2_PRI 0x0000000F
#define PLIC_CPU_UXINT2_PRI_M ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S))
#define PLIC_CPU_UXINT2_PRI_V 0xF
#define PLIC_CPU_UXINT2_PRI_S 0
#define PLIC_UXINT3_PRI_REG (DR_REG_PLIC_UX_BASE + 0x1C)
/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,809 |
*/
#define PLIC_CPU_UXINT5_PRI 0x0000000F
#define PLIC_CPU_UXINT5_PRI_M ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S))
#define PLIC_CPU_UXINT5_PRI_V 0xF
#define PLIC_CPU_UXINT5_PRI_S 0
#define PLIC_UXINT6_PRI_REG (DR_REG_PLIC_UX_BASE + 0x28)
/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,809 |
*/
#define PLIC_CPU_UXINT8_PRI 0x0000000F
#define PLIC_CPU_UXINT8_PRI_M ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S))
#define PLIC_CPU_UXINT8_PRI_V 0xF
#define PLIC_CPU_UXINT8_PRI_S 0
#define PLIC_UXINT9_PRI_REG (DR_REG_PLIC_UX_BASE + 0x34)
/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ... | 1,809 |
*/
#define PLIC_CPU_UXINT11_PRI 0x0000000F
#define PLIC_CPU_UXINT11_PRI_M ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S))
#define PLIC_CPU_UXINT11_PRI_V 0xF
#define PLIC_CPU_UXINT11_PRI_S 0
#define PLIC_UXINT12_PRI_REG (DR_REG_PLIC_UX_BASE + 0x40)
/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_UXINT14_PRI 0x0000000F
#define PLIC_CPU_UXINT14_PRI_M ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S))
#define PLIC_CPU_UXINT14_PRI_V 0xF
#define PLIC_CPU_UXINT14_PRI_S 0
#define PLIC_UXINT15_PRI_REG (DR_REG_PLIC_UX_BASE + 0x4C)
/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_UXINT17_PRI 0x0000000F
#define PLIC_CPU_UXINT17_PRI_M ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S))
#define PLIC_CPU_UXINT17_PRI_V 0xF
#define PLIC_CPU_UXINT17_PRI_S 0
#define PLIC_UXINT18_PRI_REG (DR_REG_PLIC_UX_BASE + 0x58)
/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_UXINT20_PRI 0x0000000F
#define PLIC_CPU_UXINT20_PRI_M ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S))
#define PLIC_CPU_UXINT20_PRI_V 0xF
#define PLIC_CPU_UXINT20_PRI_S 0
#define PLIC_UXINT21_PRI_REG (DR_REG_PLIC_UX_BASE + 0x64)
/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_UXINT23_PRI 0x0000000F
#define PLIC_CPU_UXINT23_PRI_M ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S))
#define PLIC_CPU_UXINT23_PRI_V 0xF
#define PLIC_CPU_UXINT23_PRI_S 0
#define PLIC_UXINT24_PRI_REG (DR_REG_PLIC_UX_BASE + 0x70)
/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_UXINT26_PRI 0x0000000F
#define PLIC_CPU_UXINT26_PRI_M ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S))
#define PLIC_CPU_UXINT26_PRI_V 0xF
#define PLIC_CPU_UXINT26_PRI_S 0
#define PLIC_UXINT27_PRI_REG (DR_REG_PLIC_UX_BASE + 0x7C)
/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_UXINT29_PRI 0x0000000F
#define PLIC_CPU_UXINT29_PRI_M ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S))
#define PLIC_CPU_UXINT29_PRI_V 0xF
#define PLIC_CPU_UXINT29_PRI_S 0
#define PLIC_UXINT30_PRI_REG (DR_REG_PLIC_UX_BASE + 0x88)
/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;defaul... | 1,809 |
*/
#define PLIC_CPU_UXINT_THRESH 0x000000FF
#define PLIC_CPU_UXINT_THRESH_M ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S))
#define PLIC_CPU_UXINT_THRESH_V 0xFF
#define PLIC_CPU_UXINT_THRESH_S 0
#define PLIC_UXINT_CLAIM_REG (DR_REG_PLIC_UX_BASE + 0x94)
/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ... | 1,809 |
/*
*/
#pragma once
/**
*/
#define I2C_PMU 0x6d
#define I2C_PMU_HOSTID 0
#define I2C_PMU_EN_I2C_RTC_DREG 8
#define I2C_PMU_EN_I2C_RTC_DREG_MSB 0
#define I2C_PMU_EN_I2C_RTC_DREG_LSB 0
#define I2C_PMU_EN_I2C_DIG_DREG 8
#define I2C_PMU_EN_I2C_DIG_DREG_MSB 1
#define I2C_PMU_EN_I2C_... | 1,810 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of store register
*/
typedef union {
struct {
/** store : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t store:32;
};
uint32_t val;
} lp_aon_store_reg_t;
/** Type of gpi... | 1,813 |
/*
*/
#pragma once
//RTC GPIO channels
#define RTCIO_GPIO7_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 7
#define RTCIO_GPIO8_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 8
#define RTCIO_GPIO9_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GP... | 1,814 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_... | 1,815 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32H2 Root Clock Source
*/
/* With the default value of CK8M_DFREQ = 860, RC_FAST clock frequency is 8.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 8500000 /*!, F
/**
*/
typedef enum {
// For CPU domai... | 1,817 |
< PLL_F64M_CLK is derived from FLASH_PLL (clock gating), it has a fixed frequency of 64MHz */
SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external ... | 1,817 |
< SYSTIMER source clock is RC_FAST */
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
} soc_periph_systimer_clk_src_t;
//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
/**
*/
#define SOC_G... | 1,817 |
< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source default choice is PLL_F48M */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
*/
#d... | 1,817 |
< Select XTAL as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
} soc_periph_temperature_sensor_clk_src_t;
//////////////////////////////... | 1,817 |
< Select PLL_F96M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
*/
#define SOC_MCPWM_CAPTURE_CL... | 1,817 |
< Select XTAL as the source clock */
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_mcpwm_carrier_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
*/
#de... | 1,817 |
< Select XTAL as the source clock */
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
} soc_periph_i2c_clk_src_t;
///////////////////////////////////... | 1,817 |
< Select XTAL clock as the source clock */
SDM_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////... | 1,817 |
< Select XTAL clock as the source clock */
GLITCH_FILTER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
////////////... | 1,817 |
< Select XTAL as the source clock */
ADC_DIGI_CLK_SRC_PLL_F96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the ... | 1,817 |
< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
... | 1,817 |
< Select PLL_F96M as the source clock */
PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the source clock */
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the... | 1,817 |
< Select PLL_F64M as the default clock choice */
MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_mspi_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum {
CLKO... | 1,817 |
/*
*/
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_UART1_BASE 0x60001000
#define DR_REG_SPI0_BASE 0x60002000
#define DR_REG_SPI1_BASE 0x60003000
#define DR_REG_I2C_EXT0_BASE 0x60004000
#define DR_REG_I2... | 1,820 |
/*
*/
#pragma once
#ifndef __ASSEMBLER__
#include
#include "esp_assert.h"
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#define PRO_CPU_NUM (0)
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1... | 1,821 |
__ASSEMBLER__ */
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 32*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ_MHZ_BTLD (64) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader... | 1,821 |
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