text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
#define SOC_DIRAM_IRAM_LOW 0x40800000
#define SOC_DIRAM_IRAM_HIGH 0x40850000
#define SOC_DIRAM_DRAM_LOW 0x40800000
#define SOC_DIRAM_DRAM_HIGH 0x40850000
#define MAP_DRAM_TO_IRAM(addr) (addr)
#define MAP_IRAM_TO_DRAM(addr) (addr)
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
#define SO... | 1,821 |
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_MEMPROT_ERR_INUM... | 1,821 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
*/
typedef union {
struct {
/** filter_thres : R/W; bitpos: [9:0]; default: 16;
*/
uint32_t filter_thres:10;
/** filter_en : R/W; bitpos: [10];... | 1,823 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of core0_cpu_int_enable register
*/
typedef union {
struct {
/** core0_cpu_int_enable : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t core0_cpu_int_enable:32;
};
ui... | 1,825 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of set_start register
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t ... | 1,826 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TIMER_TAR0_LOW_REG register
*/
#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU
#defi... | 1,827 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration register */
/** Type of bt_select register
*/
typedef union {
struct {
/** bt_sel : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t bt_sel:32;
};
uint32_t val;
} gpio_bt_select_reg_t;
/**... | 1,829 |
/*
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH... | 1,831 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of external_device_encrypt_decrypt_control register
*/
typedef union {
struct {
/** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
*/
uint32_t enable_spi_manual_... | 1,832 |
/*
*/
#pragma once
#include "soc/interrupts.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERIP... | 1,833 |
!! Don't append soc modules here !!! */
} periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_BT_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_M... | 1,833 |
/*
*/
#pragma once
#include "soc/aes_reg.h"
#include "soc/ds_reg.h"
#include "soc/hmac_reg.h"
#include "soc/rsa_reg.h"
#include "soc/sha_reg.h"
| 1,834 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DS_Y_MEM register
*/
#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
#define DS_Y_MEM_SIZE_BYTES 512
/** DS_M_MEM register
*/
#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
#define DS_M_MEM_SIZE_BYTES 512
/** DS_RB_MEM register
*/
... | 1,835 |
/*
*/
#ifndef _SOC_CACHE_REG_H_
#define _SOC_CACHE_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4)
/* CACHE_L1_CACHE_SHUT_BUS1 : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: The bit is used to disable core1 dbus access L1-Cache,... | 1,836 |
.*/
#define CACHE_L1_CACHE_WRAP (BIT(4))
#define CACHE_L1_CACHE_WRAP_M (BIT(4))
#define CACHE_L1_CACHE_WRAP_V 0x1
#define CACHE_L1_CACHE_WRAP_S 4
#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24)
/* CACHE_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
/*descripti... | 1,836 |
1: close gating,
0: open clock gating..*/
#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON (BIT(16))
#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_M (BIT(16))
#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V 0x1
#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S 16
#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + ... | 1,836 |
1: close gating,
0: open clock gating..*/
#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON (BIT(16))
#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_M (BIT(16))
#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V 0x1
#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S 16
#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2... | 1,836 |
It can be cleared by sof
tware..*/
#define CACHE_L1_CACHE_FREEZE_EN (BIT(16))
#define CACHE_L1_CACHE_FREEZE_EN_M (BIT(16))
#define CACHE_L1_CACHE_FREEZE_EN_V 0x1
#define CACHE_L1_CACHE_FREEZE_EN_S 16
#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30)
/* CACHE_L1_CACHE_DATA_MEM_WR_E... | 1,836 |
0: disable, 1
: enable..*/
#define CACHE_L1_CACHE_TAG_MEM_WR_EN (BIT(17))
#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M (BIT(17))
#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V 0x1
#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S 17
/* CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: The bit is used to ... | 1,836 |
.*/
#define CACHE_L1_CACHE_PRELOCK_SCT1_EN (BIT(1))
#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M (BIT(1))
#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V 0x1
#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S 1
/* CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: The bit is used to enable the first s... | 1,836 |
*/
#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF
#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M ((CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S))
#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF
#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S 0
#define CACHE_L1_CACHE_PRELOCK_SCT_SIZE... | 1,836 |
*/
#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFF
#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M ((CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S))
#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x3FFF
#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S 0
#define CACHE_LOCK_CTRL_REG (DR_RE... | 1,836 |
It will be cleared by hardware after l
ock operation done.*/
#define CACHE_LOCK_ENA (BIT(0))
#define CACHE_LOCK_ENA_M (BIT(0))
#define CACHE_LOCK_ENA_V 0x1
#define CACHE_LOCK_ENA_S 0
#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8C)
/* CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
/*descri... | 1,836 |
*/
#define CACHE_LOCK_SIZE 0x0000FFFF
#define CACHE_LOCK_SIZE_M ((CACHE_LOCK_SIZE_V)<<(CACHE_LOCK_SIZE_S))
#define CACHE_LOCK_SIZE_V 0xFFFF
#define CACHE_LOCK_SIZE_S 0
#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98)
/* CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */
/*description: The bit is... | 1,836 |
It will be cleared by hardware af
ter writeback operation done. Note that this bit and the other sync-bits (invali
date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is,
those bits can not be set to 1 at the same time..*/
#define CACHE_WRITEBACK_ENA (BIT(2))
#define CACHE_WRITEBACK_ENA_M (... | 1,836 |
It will be cleared by hardware a
fter invalidate operation done. Note that this bit and the other sync-bits (clea
n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
those bits can not be set to 1 at the same time..*/
#define CACHE_INVALIDATE_ENA (BIT(0))
#define CACHE_INVALIDATE_ENA_M... | 1,836 |
*/
#define CACHE_SYNC_ADDR 0xFFFFFFFF
#define CACHE_SYNC_ADDR_M ((CACHE_SYNC_ADDR_V)<<(CACHE_SYNC_ADDR_S))
#define CACHE_SYNC_ADDR_V 0xFFFFFFFF
#define CACHE_SYNC_ADDR_S 0
#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xA4)
/* CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: T... | 1,836 |
0: ascending, 1
: descending..*/
#define CACHE_L1_CACHE_PRELOAD_ORDER (BIT(2))
#define CACHE_L1_CACHE_PRELOAD_ORDER_M (BIT(2))
#define CACHE_L1_CACHE_PRELOAD_ORDER_V 0x1
#define CACHE_L1_CACHE_PRELOAD_ORDER_S 2
/* CACHE_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
/*description: The bit is used to ... | 1,836 |
*/
#define CACHE_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFF
#define CACHE_L1_CACHE_PRELOAD_ADDR_M ((CACHE_L1_CACHE_PRELOAD_ADDR_V)<<(CACHE_L1_CACHE_PRELOAD_ADDR_S))
#define CACHE_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFF
#define CACHE_L1_CACHE_PRELOAD_ADDR_S 0
#define CACHE_L1_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE +... | 1,836 |
.*/
#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9))
#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M (BIT(9))
#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x1
#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9
/* CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
/*description: The bit is used to enable t... | 1,836 |
0:
ascending. 1: descending..*/
#define CACHE_L1_CACHE_AUTOLOAD_ORDER (BIT(2))
#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M (BIT(2))
#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V 0x1
#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S 2
/* CACHE_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
/*description: The bit is use... | 1,836 |
Note that it should be used together with L1
_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF
#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M ((CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S))
#define CACHE_L1_CACHE_AUTOLOAD_S... | 1,836 |
Note that it should be used together with L
1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF
#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M ((CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S))
#define CACHE_L1_CACHE_AUTOLOAD_S... | 1,836 |
Note that it should be used together with L1
_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA..*/
#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR 0xFFFFFFFF
#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M ((CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S))
#define CACHE_L1_CACHE_AUTOLOAD_S... | 1,836 |
Note that it should be used together with L
1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA..*/
#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR 0xFFFFFFFF
#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M ((CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S))
#define CACHE_L1_CACHE_AUTOLOAD_S... | 1,836 |
.*/
#define CACHE_L1_BUS1_OVF_INT_ENA (BIT(5))
#define CACHE_L1_BUS1_OVF_INT_ENA_M (BIT(5))
#define CACHE_L1_BUS1_OVF_INT_ENA_V 0x1
#define CACHE_L1_BUS1_OVF_INT_ENA_S 5
/* CACHE_L1_BUS0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of one of counters overflo... | 1,836 |
.*/
#define CACHE_L1_BUS0_OVF_INT_CLR (BIT(4))
#define CACHE_L1_BUS0_OVF_INT_CLR_M (BIT(4))
#define CACHE_L1_BUS0_OVF_INT_CLR_V 0x1
#define CACHE_L1_BUS0_OVF_INT_CLR_S 4
#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160)
/* CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1... | 1,836 |
.*/
#define CACHE_L1_BUS1_OVF_INT_ST (BIT(5))
#define CACHE_L1_BUS1_OVF_INT_ST_M (BIT(5))
#define CACHE_L1_BUS1_OVF_INT_ST_V 0x1
#define CACHE_L1_BUS1_OVF_INT_ST_S 5
/* CACHE_L1_BUS0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit indicates the interrupt status of one of counters overflow t... | 1,836 |
.*/
#define CACHE_L1_CACHE_FAIL_INT_CLR (BIT(4))
#define CACHE_L1_CACHE_FAIL_INT_CLR_M (BIT(4))
#define CACHE_L1_CACHE_FAIL_INT_CLR_V 0x1
#define CACHE_L1_CACHE_FAIL_INT_CLR_S 4
#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x170)
/* CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ... | 1,836 |
.*/
#define CACHE_L1_BUS1_CNT_CLR (BIT(21))
#define CACHE_L1_BUS1_CNT_CLR_M (BIT(21))
#define CACHE_L1_BUS1_CNT_CLR_V 0x1
#define CACHE_L1_BUS1_CNT_CLR_S 21
/* CACHE_L1_BUS0_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
/*description: The bit is used to clear dbus0 counter in L1-DCache..*/
#define CACHE_L1_BUS0_C... | 1,836 |
.*/
#define CACHE_L1_BUS0_HIT_CNT 0xFFFFFFFF
#define CACHE_L1_BUS0_HIT_CNT_M ((CACHE_L1_BUS0_HIT_CNT_V)<<(CACHE_L1_BUS0_HIT_CNT_S))
#define CACHE_L1_BUS0_HIT_CNT_V 0xFFFFFFFF
#define CACHE_L1_BUS0_HIT_CNT_S 0
#define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1C0)
/* CACHE_L1_BUS0_MISS_CNT : ... | 1,836 |
.*/
#define CACHE_L1_BUS0_NXTLVL_CNT 0xFFFFFFFF
#define CACHE_L1_BUS0_NXTLVL_CNT_M ((CACHE_L1_BUS0_NXTLVL_CNT_V)<<(CACHE_L1_BUS0_NXTLVL_CNT_S))
#define CACHE_L1_BUS0_NXTLVL_CNT_V 0xFFFFFFFF
#define CACHE_L1_BUS0_NXTLVL_CNT_S 0
#define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1CC)
/* CACHE_L1... | 1,836 |
.*/
#define CACHE_L1_BUS1_CONFLICT_CNT 0xFFFFFFFF
#define CACHE_L1_BUS1_CONFLICT_CNT_M ((CACHE_L1_BUS1_CONFLICT_CNT_V)<<(CACHE_L1_BUS1_CONFLICT_CNT_S))
#define CACHE_L1_BUS1_CONFLICT_CNT_V 0xFFFFFFFF
#define CACHE_L1_BUS1_CONFLICT_CNT_S 0
#define CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1... | 1,836 |
.*/
#define CACHE_L1_CACHE_FAIL_ID 0x0000FFFF
#define CACHE_L1_CACHE_FAIL_ID_M ((CACHE_L1_CACHE_FAIL_ID_V)<<(CACHE_L1_CACHE_FAIL_ID_S))
#define CACHE_L1_CACHE_FAIL_ID_V 0xFFFF
#define CACHE_L1_CACHE_FAIL_ID_S 0
#define CACHE_L1_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x220)
/* CACHE_L1_CACHE_FAIL_A... | 1,836 |
.*/
#define CACHE_L1_CACHE_PLD_ERR_INT_ENA (BIT(11))
#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M (BIT(11))
#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V 0x1
#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S 11
/* CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of Ca... | 1,836 |
.*/
#define CACHE_SYNC_ERR_INT_CLR (BIT(13))
#define CACHE_SYNC_ERR_INT_CLR_M (BIT(13))
#define CACHE_SYNC_ERR_INT_CLR_V 0x1
#define CACHE_SYNC_ERR_INT_CLR_S 13
/* CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt of L1-Cache preload-operation e... | 1,836 |
.*/
#define CACHE_L1_CACHE_PLD_DONE_INT_CLR (BIT(4))
#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M (BIT(4))
#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V 0x1
#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S 4
#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x22C)
/* CACHE_SYNC_ERR_INT_RAW : R/WTC/... | 1,836 |
.*/
#define CACHE_SYNC_DONE_INT_RAW (BIT(6))
#define CACHE_SYNC_DONE_INT_RAW_M (BIT(6))
#define CACHE_SYNC_DONE_INT_RAW_V 0x1
#define CACHE_SYNC_DONE_INT_RAW_S 6
/* CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt that occurs only when L1-Cache... | 1,836 |
.*/
#define CACHE_L1_CACHE_PLD_ERR_INT_ST (BIT(11))
#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M (BIT(11))
#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V 0x1
#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S 11
/* CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit indicates the status of the interrupt t... | 1,836 |
.*/
#define CACHE_SYNC_ERR_CODE 0x00000003
#define CACHE_SYNC_ERR_CODE_M ((CACHE_SYNC_ERR_CODE_V)<<(CACHE_SYNC_ERR_CODE_S))
#define CACHE_SYNC_ERR_CODE_V 0x3
#define CACHE_SYNC_ERR_CODE_S 12
/* CACHE_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */
/*description: The value 2 is Only available which me... | 1,836 |
Recommend that this should
only be used to initialize preload-logic when some fatal error of preload-logic
occurs..*/
#define CACHE_L1_CACHE_PLD_RST (BIT(4))
#define CACHE_L1_CACHE_PLD_RST_M (BIT(4))
#define CACHE_L1_CACHE_PLD_RST_V 0x1
#define CACHE_L1_CACHE_PLD_RST_S 4
#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_... | 1,836 |
.*/
#define CACHE_L1_CACHE_UNALLOC_CLR (BIT(4))
#define CACHE_L1_CACHE_UNALLOC_CLR_M (BIT(4))
#define CACHE_L1_CACHE_UNALLOC_CLR_V 0x1
#define CACHE_L1_CACHE_UNALLOC_CLR_S 4
#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x248)
/* CACHE_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ... | 1,836 |
0: way0, 1
: way1, 2: way2, 3: way3, ?, 7: way7..*/
#define CACHE_L1_CACHE_WAY_OBJECT 0x00000007
#define CACHE_L1_CACHE_WAY_OBJECT_M ((CACHE_L1_CACHE_WAY_OBJECT_V)<<(CACHE_L1_CACHE_WAY_OBJECT_S))
#define CACHE_L1_CACHE_WAY_OBJECT_V 0x7
#define CACHE_L1_CACHE_WAY_OBJECT_S 0
#define CACHE_L1_CACHE_VADDR_REG ... | 1,836 |
.*/
#define CACHE_L1_CACHE_DEBUG_BUS 0xFFFFFFFF
#define CACHE_L1_CACHE_DEBUG_BUS_M ((CACHE_L1_CACHE_DEBUG_BUS_V)<<(CACHE_L1_CACHE_DEBUG_BUS_S))
#define CACHE_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFF
#define CACHE_L1_CACHE_DEBUG_BUS_S 0
#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3AC)
/* CACHE_CLK_EN : R/... | 1,836 |
.*/
#define CACHE_REDCY_SIG1 0xFFFFFFFF
#define CACHE_REDCY_SIG1_M ((CACHE_REDCY_SIG1_V)<<(CACHE_REDCY_SIG1_S))
#define CACHE_REDCY_SIG1_V 0xFFFFFFFF
#define CACHE_REDCY_SIG1_S 0
#define CACHE_REDUNDANCY_SIG2_REG (DR_REG_CACHE_BASE + 0x3B8)
/* CACHE_REDCY_SIG2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/... | 1,836 |
.*/
#define CACHE_REDCY_SIG4 0x0000000F
#define CACHE_REDCY_SIG4_M ((CACHE_REDCY_SIG4_V)<<(CACHE_REDCY_SIG4_S))
#define CACHE_REDCY_SIG4_V 0xF
#define CACHE_REDCY_SIG4_S 0
#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3FC)
/* CACHE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2207250 ; */
/*description: vers... | 1,836 |
/*
*/
#pragma once
/**
*/
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADD... | 1,837 |
/*
*/
#pragma once
#include
#include "soc/ext_mem_defs.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Defined for flash mmap */
#define SOC_MMU_REGIONS_COUNT 1
#define SOC_MMU_PAGES_PER_REGION 256
#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_ST... | 1,838 |
/**
*/
#pragma once
#include
#include "esp_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Interrupt registers */
/** Type of int_raw register
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
*/
uint32_t cal... | 1,840 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of lp_clk_conf register
*/
typedef union {
struct {
/** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
*/
uint32_t slow_clk_sel:2;
/** fast_clk_sel : R/W; bitpos: [3:2]... | 1,842 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory */
/** Group: Control / Configuration Registers */
/** Type of m_prime register
*/
typedef union {
struct {
/** m_prime : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t m_prime:32;
};
uint32_t ... | 1,844 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of regdma_conf register
*/
typedef union {
struct {
/** flow_err : RO; bitpos: [2:0]; default: 0;
*/
uint32_t flow_err:3;
/** start : WT; bitpos: [3]; default: 0;
... | 1,846 |
/*
*/
#pragma once
//+Terminology+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| ... | 1,847 |
/*
*/
#pragma once
#include "soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1)... | 1,851 |
csv
#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE + 0x4)
#define FUNC_GPIO0_FSPIQ 2
#define FUNC_GPIO0_GPIO0 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_GPIO1_U ... | 1,851 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SHA_MODE_REG register
*/
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
*/
#define SHA_MODE 0x00000007U
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
#define SHA_MODE_V 0x... | 1,852 |
/*
*/
#pragma once
#include
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum periph_retention_module_bitmap {
/* clock module, which includes system and modem */
SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = BIT(1),
SLEEP_RETENTION_MODULE_CLOCK_MODEM = BIT(2),
/* modem modul... | 1,853 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
*/
#define MEM_MONITOR_LOG_ENA 0x00000007U
#define M... | 1,855 |
/*
*/
#pragma once
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0)
/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
he bit will be cl... | 1,856 |
The
bit will be cleared once the operation done. 1: enable 0: disable..*/
#define SPI_MEM_FLASH_WRDI (BIT(29))
#define SPI_MEM_FLASH_WRDI_M (BIT(29))
#define SPI_MEM_FLASH_WRDI_V 0x1
#define SPI_MEM_FLASH_WRDI_S 29
/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
/*description: Read JEDEC ID . Re... | 1,856 |
Write status operation will be triggered when t
he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
ble..*/
#define SPI_MEM_FLASH_WRSR (BIT(26))
#define SPI_MEM_FLASH_WRSR_M (BIT(26))
#define SPI_MEM_FLASH_WRSR_V 0x1
#define SPI_MEM_FLASH_WRSR_S 26
/* SPI_MEM_FLASH_PP : R/W/SC ;bi... | 1,856 |
Block erase operation will be triggered when the bit
is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
#define SPI_MEM_FLASH_BE (BIT(23))
#define SPI_MEM_FLASH_BE_M (BIT(23))
#define SPI_MEM_FLASH_BE_V 0x1
#define SPI_MEM_FLASH_BE_S 23
/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;d... | 1,856 |
The bit will be cleared o
nce the operation done.1: enable 0: disable..*/
#define SPI_MEM_FLASH_RES (BIT(20))
#define SPI_MEM_FLASH_RES_M (BIT(20))
#define SPI_MEM_FLASH_RES_V 0x1
#define SPI_MEM_FLASH_RES_S 20
/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
/*description: Drive Flash into high pe... | 1,856 |
The bit is combined with spi_mem_usr bit. The bit will be cleared once the o
peration done.1: enable 0: disable..*/
#define SPI_MEM_FLASH_PE (BIT(17))
#define SPI_MEM_FLASH_PE_M (BIT(17))
#define SPI_MEM_FLASH_PE_V 0x1
#define SPI_MEM_FLASH_PE_S 17
/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
/*descr... | 1,856 |
.*/
#define SPI_MEM_MST_ST 0x0000000F
#define SPI_MEM_MST_ST_M ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
#define SPI_MEM_MST_ST_V 0xF
#define SPI_MEM_MST_ST_S 0
#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4)
/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: In us... | 1,856 |
0: Others..*/
#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30))
#define SPI_MEM_DQS_IE_ALWAYS_ON_M (BIT(30))
#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x1
#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30
/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: In the read operations address phase and read-data phase ap... | 1,856 |
1: output high, 0: output low..*/
#define SPI_MEM_WP_REG (BIT(21))
#define SPI_MEM_WP_REG_M (BIT(21))
#define SPI_MEM_WP_REG_V 0x1
#define SPI_MEM_WP_REG_S 21
/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.... | 1,856 |
1: enable 0: disable..*/
#define SPI_MEM_RESANDRES (BIT(15))
#define SPI_MEM_RESANDRES_M (BIT(15))
#define SPI_MEM_RESANDRES_V 0x1
#define SPI_MEM_RESANDRES_S 15
/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disab... | 1,856 |
Activ
e low..*/
#define SPI_MEM_FCS_CRC_EN (BIT(10))
#define SPI_MEM_FCS_CRC_EN_M (BIT(10))
#define SPI_MEM_FCS_CRC_EN_V 0x1
#define SPI_MEM_FCS_CRC_EN_S 10
/* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */
/*description: Apply 8 signals during command phase 1:enable 0: disable.*/
#define SPI_MEM_FCMD_OC... | 1,856 |
*/
#define SPI_MEM_FDIN_OCT (BIT(5))
#define SPI_MEM_FDIN_OCT_M (BIT(5))
#define SPI_MEM_FDIN_OCT_V 0x1
#define SPI_MEM_FDIN_OCT_S 5
/* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */
/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/
#define SPI_MEM_FDOUT_OCT (BIT(4))
#defin... | 1,856 |
It is use
d to mask invalid SPI_DQS in the half part of dummy phase..*/
#define SPI_MEM_FDUMMY_RIN (BIT(2))
#define SPI_MEM_FDUMMY_RIN_M (BIT(2))
#define SPI_MEM_FDUMMY_RIN_V 0x1
#define SPI_MEM_FDUMMY_RIN_S 2
/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: In the dummy phase of... | 1,856 |
Set this bit to reset these FIFO..*/
#define SPI_MEM_TXFIFO_RST (BIT(31))
#define SPI_MEM_TXFIFO_RST_M (BIT(31))
#define SPI_MEM_TXFIFO_RST_V 0x1
#define SPI_MEM_TXFIFO_RST_S 31
/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
/*description: The synchronous reset signal for SPI0 RX AFIFO and all the A... | 1,856 |
.*/
#define SPI_MEM_DUAL_RAM_EN (BIT(28))
#define SPI_MEM_DUAL_RAM_EN_M (BIT(28))
#define SPI_MEM_DUAL_RAM_EN_V 0x1
#define SPI_MEM_DUAL_RAM_EN_S 28
/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */
/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac
cessed. Whe... | 1,856 |
.*/
#define SPI_MEM_AR_SPLICE_EN (BIT(25))
#define SPI_MEM_AR_SPLICE_EN_M (BIT(25))
#define SPI_MEM_AR_SPLICE_EN_V 0x1
#define SPI_MEM_AR_SPLICE_EN_S 25
/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKA... | 1,856 |
0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN (BIT(22))
#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_M (BIT(22))
#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_V 0x1
#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_S 22
/* SPI_MEM_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
/*description... | 1,856 |
0: SPI clock is off when CS inactive 1: SPI clock is delaye
d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
ve 3: SPI clock is alwasy on..*/
#define SPI_MEM_CLK_MODE 0x00000003
#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
#define SPI_MEM_CLK_MODE_V 0x3
#... | 1,856 |
.*/
#define SPI_MEM_SPLIT_TRANS_EN (BIT(24))
#define SPI_MEM_SPLIT_TRANS_EN_M (BIT(24))
#define SPI_MEM_SPLIT_TRANS_EN_V 0x1
#define SPI_MEM_SPLIT_TRANS_EN_S 24
/* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */
/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC byt... | 1,856 |
.*/
#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007
#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S))
#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7
#define SPI_MEM_ECC_CS_HOLD_TIME_S 10
/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
/*description: SPI CS signal ... | 1,856 |
.*/
#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31))
#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31))
#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1
#define SPI_MEM_CLK_EQU_SYSCLK_S 31
/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequenc... | 1,856 |
.*/
#define SPI_MEM_USR_COMMAND (BIT(31))
#define SPI_MEM_USR_COMMAND_M (BIT(31))
#define SPI_MEM_USR_COMMAND_V 0x1
#define SPI_MEM_USR_COMMAND_S 31
/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: This bit enable the address phase of an operation..*/
#define SPI_MEM_USR_ADDR (BIT(30))... | 1,856 |
.*/
#define SPI_MEM_USR_MOSI (BIT(27))
#define SPI_MEM_USR_MOSI_M (BIT(27))
#define SPI_MEM_USR_MOSI_V 0x1
#define SPI_MEM_USR_MOSI_S 27
/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: spi clock is disable in dummy phase when the bit is enable..*/
#define SPI_MEM_USR_DUMMY_IDLE ... | 1,856 |
.*/
#define SPI_MEM_FWRITE_QIO (BIT(15))
#define SPI_MEM_FWRITE_QIO_M (BIT(15))
#define SPI_MEM_FWRITE_QIO_V 0x1
#define SPI_MEM_FWRITE_QIO_S 15
/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: In the write operations address phase and read-data phase apply 2 signals..*/
#define SPI_MEM... | 1,856 |
.*/
#define SPI_MEM_CK_OUT_EDGE (BIT(9))
#define SPI_MEM_CK_OUT_EDGE_M (BIT(9))
#define SPI_MEM_CK_OUT_EDGE_V 0x1
#define SPI_MEM_CK_OUT_EDGE_S 9
/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable..*/
#define SPI_MEM_CS_SE... | 1,856 |
*/
#define SPI_MEM_USR_DBYTELEN 0x00000007
#define SPI_MEM_USR_DBYTELEN_M ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S))
#define SPI_MEM_USR_DBYTELEN_V 0x7
#define SPI_MEM_USR_DBYTELEN_S 6
/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
/*description: The length in spi_mem_clk cycles o... | 1,856 |
.*/
#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF
#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF
#define SPI_MEM_USR_COMMAND_VALUE_S 0
#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24)
/* SPI_MEM_US... | 1,856 |
.*/
#define SPI_MEM_WB_MODE 0x000000FF
#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
#define SPI_MEM_WB_MODE_V 0xFF
#define SPI_MEM_WB_MODE_S 16
/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flas... | 1,856 |
*/
#define SPI_MEM_CK_IDLE_EDGE (BIT(9))
#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9))
#define SPI_MEM_CK_IDLE_EDGE_V 0x1
#define SPI_MEM_CK_IDLE_EDGE_S 9
/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */
/*description: For SPI0, sram is connected to SUBPINs..*/
#define SPI_MEM_SSUB_PIN (BIT(8))
#define SPI... | 1,856 |
.*/
#define SPI_MEM_CS0_DIS (BIT(0))
#define SPI_MEM_CS0_DIS_M (BIT(0))
#define SPI_MEM_CS0_DIS_V 0x1
#define SPI_MEM_CS0_DIS_S 0
#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38)
/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: For SPI1, the value of crc32.... | 1,856 |
.*/
#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN (BIT(30))
#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_M (BIT(30))
#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_V 0x1
#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_S 30
/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: For SPI0 flash, address phase apply 4 signals.... | 1,856 |
The bit is the
same with spi_mem_fread_qio..*/
#define SPI_MEM_FDIN_QUAD (BIT(6))
#define SPI_MEM_FDIN_QUAD_M (BIT(6))
#define SPI_MEM_FDIN_QUAD_V 0x1
#define SPI_MEM_FDIN_QUAD_S 6
/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: For SPI0 flash, address phase apply 2 signals. 1: enabl... | 1,856 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.