text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define SPI_MEM_SMEM_DOUT0_MODE (BIT(0))
#define SPI_MEM_SMEM_DOUT0_MODE_M (BIT(0))
#define SPI_MEM_SMEM_DOUT0_MODE_V 0x1
#define SPI_MEM_SMEM_DOUT0_MODE_S 0
#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A0)
/* SPI_MEM_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */
/*descri... | 1,856 |
.*/
#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN (BIT(16))
#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16))
#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V 0x1
#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_S 16
/* SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */
/*description: 1: SPI0 skips page corner ... | 1,856 |
.*/
#define SPI_MEM_SMEM_CS_HOLD_TIME 0x0000001F
#define SPI_MEM_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_CS_HOLD_TIME_S))
#define SPI_MEM_SMEM_CS_HOLD_TIME_V 0x1F
#define SPI_MEM_SMEM_CS_HOLD_TIME_S 7
/* SPI_MEM_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */
/*description: Fo... | 1,856 |
1: enable 0: d
isable..*/
#define SPI_MEM_SMEM_CS_SETUP (BIT(0))
#define SPI_MEM_SMEM_CS_SETUP_M (BIT(0))
#define SPI_MEM_SMEM_CS_SETUP_V 0x1
#define SPI_MEM_SMEM_CS_SETUP_S 0
#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200)
/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*descr... | 1,856 |
*/
#define SPI_MEM_MMU_ITEM_INDEX 0xFFFFFFFF
#define SPI_MEM_MMU_ITEM_INDEX_M ((SPI_MEM_MMU_ITEM_INDEX_V)<<(SPI_MEM_MMU_ITEM_INDEX_S))
#define SPI_MEM_MMU_ITEM_INDEX_V 0xFFFFFFFF
#define SPI_MEM_MMU_ITEM_INDEX_S 0
#define SPI_MEM_MMU_POWER_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x384)
/* SPI_MEM_RDN_RESULT ... | 1,856 |
*/
#define SPI_MEM_MMU_PAGE_SIZE 0x00000003
#define SPI_MEM_MMU_PAGE_SIZE_M ((SPI_MEM_MMU_PAGE_SIZE_V)<<(SPI_MEM_MMU_PAGE_SIZE_S))
#define SPI_MEM_MMU_PAGE_SIZE_V 0x3
#define SPI_MEM_MMU_PAGE_SIZE_S 3
/* SPI_MEM_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: Set this bit to force mmu-memory... | 1,856 |
*/
#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFF
#define SPI_MEM_REGISTERRND_ECO_HIGH_M ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S))
#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFF
#define SPI_MEM_REGISTERRND_ECO_HIGH_S 0
#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i) (REG_SPI_ME... | 1,856 |
/*
*/
#include "soc/hp_system_reg.h"
#include "intpri_reg.h"
// ESP32H2-TODO : TODO: IDF-5720
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0
| 1,857 |
/*
*/
#pragma once
#define ADC1_GPIO1_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 1
#define ADC1_GPIO2_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 2
#define ADC1_GPIO3_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 3
#define ADC1_GPIO4_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 4
#define ADC1_GPIO5_CHA... | 1,858 |
/*
*/
/*
*/
#pragma once
/* COMMON CAPS */
#define SOC_ADC_SUPPORTED 1
#define SOC_ANA_CMPR_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_ASYNC_ME... | 1,861 |
SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
/* SPI MEM CAPS */
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND ... | 1,861 |
< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
#... | 1,861 |
<Supports one bit per pin to configue the EXT1 trigger level */
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_MODEM_PD (1) /*!<modem includes BLE and 15.4 */
#define SOC_PM_SUPPORT_XTAL32K_PD (1)
#define SOC_PM_SUPPORT_RC32K_PD (1)
#define SOC_PM_SUPPORT_RC_FAST_PD (1)
#... | 1,861 |
< Support to connect an external oscillator, not a crystal */
#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */
#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL (1) /*!< Support LP_PLL clock as the LP_FAST clock source */
#define SOC_MODEM_CLOCK_IS_INDEPEND... | 1,861 |
< Support BLE EMBEDDED controller V1 */
#define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */
#define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */
#define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */
#define SOC_BLE_MULTI_CONN_OP... | 1,861 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct spi_mem_dev_s {
union {
struct {
uint32_t mst_st : 4; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend sta... | 1,865 |
1: enable 0: disable. */
uint32_t usr : 1; /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_hpm ... | 1,865 |
Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the op... | 1,865 |
1: enable 0: disable. */
uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_rdid : 1; /*Read JEDEC I... | 1,865 |
The bit will be cleared once the operation done. 1: enable 0: disable. */
};
uint32_t val;
} cmd;
uint32_t addr;
union {
struct {
uint32_t wdummy_dqs_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_... | 1,865 |
It is used to pre-drive flash.*/
uint32_t fdout_oct : 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/
uint32_t fdin_oct : 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/
uint32_t faddr_oct ... | 1,865 |
1: enable 0: disable. */
uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_... | 1,865 |
1: enable 0: disable. */
uint32_t fread_dio : 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
uint32_t fread_qio : 1; /*In the read operations address phase and read-data phase apply 4 signal... | 1,865 |
*/
uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
uint32_t reserved2 : 9; /*reserved*/
uint32_t reg_ar_size0_1_support_en : 1; /*1: MSPI supports ... | 1,865 |
*/
uint32_t ar_splice_en : 1; /*Set this bit to enable AXI Read Splice-transfer.*/
uint32_t aw_splice_en : 1; /*Set this bit to enable AXI Write Splice-transfer.*/
uint32_t ram0_en : 1; /*When SPI_MEM_DUAL_RAM_EN is ... | 1,865 |
Set this bit to reset these FIFO.*/
uint32_t txfifo_rst : 1; /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/
};
uint32_t val;
} ctrl1;
union {
struct {
... | 1,865 |
*/
uint32_t reserved15 : 9; /*reserved*/
uint32_t split_trans_en : 1; /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an EC... | 1,865 |
*/
uint32_t clkcnt_n : 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24 : 7; /*In the master mode it is pre-divider of spi_mem_clk. */
uint32_t clk_e... | 1,865 |
*/
uint32_t reserved10 : 2; /*reserved*/
uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals*/
uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals*/
... | 1,865 |
*/
uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation.*/
uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation.*/
uint32_t usr_dummy : 1; /*This bit enable the ... | 1,865 |
The register value shall be (bit_num-1).*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value : 16; /*The value of command.*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_command_bitlen... | 1,865 |
*/
uint32_t wb_mode : 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/
uint32_t reserved24 : 8; /*reserved*/
};
uint32_t val;
} rd_status;
uint32_t reserved_30;
union {
... | 1,865 |
*/
uint32_t reserved11 : 21; /*reserved*/
};
uint32_t val;
} misc;
uint32_t tx_crc;
union {
struct {
uint32_t axi_req_en : 1; /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/
uint32_t usr_a... | 1,865 |
1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t fdin_quad : 1; /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t fdout_quad : 1; /*For SPI0 flash... | 1,865 |
*/
uint32_t usr_sram_dio : 1; /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/
uint32_t usr_sram_qio : 1; /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/
uint32_t us... | 1,865 |
The register value shall be (bit_num-1).*/
uint32_t sram_usr_wcmd : 1; /*For SPI0, In the external RAM mode cache write sram for user define command*/
uint32_t sram_oct : 1; /*reserved*/
uint32_t sram_wdummy_cyclelen : 6; /*F... | 1,865 |
*/
uint32_t sdin_dual : 1; /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t sdout_dual : 1; /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disabl... | 1,865 |
1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t scmd_quad : 1; /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t sdin_oct : 1; /*Fo... | 1,865 |
*/
uint32_t sdummy_wout : 1; /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
uint32_t reg_smem_wdummy_dqs_always_out: 1; /*In the dummy phase of an MSPI write data transfer... | 1,865 |
0: Others.*/
};
uint32_t val;
} sram_cmd;
union {
struct {
uint32_t sram_usr_rd_cmd_value : 16; /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/
uint32_t reserved16 : 12; /*reserved*... | 1,865 |
*/
};
uint32_t val;
} sram_dwr_cmd;
union {
struct {
uint32_t sclkcnt_l : 8; /*For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N.*/
uint32_t sclkcnt_h : 8; /*For SPI0 external RAM interface, it ... | 1,865 |
*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} fsm;
uint32_t data_buf[16];
union {
struct {
uint32_t waiti_en : 1; /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto ... | 1,865 |
0: The wait idle command bit length is 8.*/
uint32_t waiti_dummy_cyclelen : 6; /*The dummy cycle length when wait flash idle(RDSR).*/
uint32_t waiti_cmd : 16; /*The command value to wait flash idle(RDSR).*/
};
uint32_t val;
} flash_waiti_... | 1,865 |
*/
uint32_t flash_pes_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
uint32_t pes_per_en : 1; /*Set... | 1,865 |
0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/
uint32_t per_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
uint32_t pes_end_en : 1; /*1: Both ... | 1,865 |
*/
};
uint32_t val;
} flash_sus_cmd;
union {
struct {
uint32_t flash_sus : 1; /*The status of flash suspend, only used in SPI1.*/
uint32_t wait_pesr_cmd_2b : 1; /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check S... | 1,865 |
0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
uint32_t flash_per_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS... | 1,865 |
0: The bit length of Program/Erase Suspend/Resume command is 8.*/
uint32_t flash_per_command : 16; /*Program/Erase resume command.*/
};
uint32_t val;
} sus_status;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
... | 1,865 |
*/
uint32_t pms_reject_en : 1; /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
uint32_t axi_raddr_err_en : 1; /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
uint32_t axi_wr_flash_err_en : 1; /*The enable bit for... | 1,865 |
*/
uint32_t slv_st_end : 1; /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
uint32_t mst_st_end : 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
uint32_t ecc_err : 1; /*The clear bit for SPI_M... | 1,865 |
1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
uint32_t pes_end : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
... | 1,865 |
When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of S... | 1,865 |
0: Others.*/
uint32_t axi_wr_flash_err : 1; /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
uint32_t axi_waddr_err : 1; /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Tr... | 1,865 |
*/
uint32_t pes_end : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t wpe_end : 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
uint32_t slv_st_end : 1; /*The status bit for SPI_MEM_... | 1,865 |
*/
uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t reserved11 : 21; /*reserved*/
};
uint32_t val;
} int_st;
uint32_t reserved_d0;
union {
struct {
uint32_t reg_... | 1,865 |
*/
uint32_t reg_fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/
uint32_t reg_fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to... | 1,865 |
*/
uint32_t reg_fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
uint32_t reg_fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
... | 1,865 |
*/
uint32_t reg_smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/
uint32_t reg_smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/
uint32_t reg_smem_ddr_cmd_dis : 1; /*the bit... | 1,865 |
It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
uint32_t reserved22 : 2; /*reserved*/
uint32_t reg_smem_clk_diff_en : 1; /*Set this bit to enable the diff... | 1,865 |
*/
uint32_t reg_smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
uint32_t reserved31 : 1; /*reserved*/
};
... | 1,865 |
The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
uint32_t reserved3 : 29; /*reserved*/
};
uint32_t val;
} spi_fmem_pms0_attr;
union {
struct {
uint32_t reg_fmem_pms1_rd_attr ... | 1,865 |
0: Not allowed.*/
uint32_t reg_fmem_pms2_wr_attr : 1; /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
uint32_t reg_fmem_pms2_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by... | 1,865 |
*/
uint32_t reserved3 : 29; /*reserved*/
};
uint32_t val;
} spi_fmem_pms3_attr;
union {
struct {
uint32_t reg_fmem_pms0_addr_s : 26; /*SPI1 flash ACE section $n start address value*/
uint32_t reserved26 ... | 1,865 |
0: Not allowed.*/
uint32_t reg_smem_pms0_wr_attr : 1; /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
uint32_t reg_smem_pms0_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE sectio... | 1,865 |
*/
uint32_t reserved3 : 29; /*reserved*/
};
uint32_t val;
} spi_smem_pms1_attr;
union {
struct {
uint32_t reg_smem_pms2_rd_attr : 1; /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
uint32_t r... | 1,865 |
0: Not allowed.*/
uint32_t reg_smem_pms3_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
uint32_t reserved3 ... | 1,865 |
It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
uint32_t pm_en : 1; /*Set this bit to enable SPI0/1 transfer permission control function.*/
uint32_t reserved27 : 1; /*reserved*/
uint32_t pms_ld ... | 1,865 |
*/
};
uint32_t val;
} pms_reject;
union {
struct {
uint32_t reserved0 : 11; /*reserved*/
uint32_t ecc_err_int_num : 6; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
u... | 1,865 |
*/
uint32_t reserved22 : 2; /*reserved*/
uint32_t ecc_continue_record_err_en : 1; /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC... | 1,865 |
It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */
uint32_t all_fifo_empty : 1; /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/
... | 1,865 |
*/
};
uint32_t val;
} axi_err_addr;
union {
struct {
uint32_t reserved0 : 17; /*reserved*/
uint32_t reg_smem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
... | 1,865 |
*/
uint32_t timing_cali : 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t dll_timing_cali ... | 1,865 |
..*/
uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delay... | 1,865 |
..*/
uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delay... | 1,865 |
*/
uint32_t reg_smem_timing_cali : 1; /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t reg_smem_extra_dummy_cyclelen : 3; /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reg_... | 1,865 |
..*/
uint32_t reg_smem_din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t reg_smem_din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delay... | 1,865 |
..*/
uint32_t reg_smem_din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t reg_smem_dins_num : 2; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: in... | 1,865 |
1: enable 0: disable. */
uint32_t reg_smem_cs_hold : 1; /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */
uint32_t reg_smem_cs_setup_time : 5; /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_... | 1,865 |
*/
uint32_t reserved17 : 8; /*reserved*/
uint32_t reg_smem_cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.... | 1,865 |
1: Enable. 0: Disable.*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} clock_gate;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uin... | 1,865 |
It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/
uint32_t reserved2 : 30; /*reserved*/
};
uint32_t val;
} xts_linesize;
union {
struct {
uint32_t reg_xts_destination : ... | 1,865 |
This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} xts_trigger;
... | 1,865 |
0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/
uint32_t reserved2 : 30; /*reserved*/
};
uint32_t val;
} xts_state;
union {
stru... | 1,865 |
*/
uint32_t reg_mmu_page_size : 2; /*0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8*/
uint32_t reserved5 : 11; /*reserved*/
uint32_t aux_ctrl : 14; /*MMU PSRAM aux control register*/
... | 1,865 |
1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
uint32_t reg_crypt_dpa_selectister : 1; /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
... | 1,865 |
*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} date;
} spi_mem_dev_t;
extern spi_mem_dev_t SPIMEM0;
extern spi_mem_dev_t SPIMEM1;
#ifdef __cplusplus
}
#endif
| 1,865 |
#define ETM_REG_BASE 0x600A4000
#define ETM_CHEN_AD0_REG (ETM_REG_BASE + 0x0000)
#define ETM_CHENSET_AD0_REG (ETM_REG_BASE + 0x0004)
#define ETM_CHENCLR_AD0_REG (ETM_REG_BASE + 0x0008)
#define ETM_CH0_EVT_ID_REG (ETM_REG_BASE + 0x0018)
#define ETM_CH0_TASK_ID_REG (ETM_REG_BASE + 0x001C)
#define ETM_CH_OFFSET 0x08
... | 1,866 |
/*
*/
#pragma once
#include
#include "soc.h"
#include "uart_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
*/
void esp_dport_access_read_buffer(uint32... | 1,867 |
/*
*/
#pragma once
#include "soc.h"
#include "soc/lpperi_reg.h"
/* Hardware random number generator register */
#define WDEV_RND_REG LPPERI_RNG_DATA_REG
| 1,868 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of sigmadeltan register
*/
typedef union {
struct {
/** duty : R/W; bitpos: [7:0]; default: 0;
*/
uint32_t duty:8;
/** prescale : R/W; bitpos: [15:8]; default: 255... | 1,871 |
/*
*/
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32H2.
#pragma once
//UART channels
#define UART_GPIO24_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 24
#define UART_GPIO23_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 23
#define U... | 1,874 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
/** Type of conf register
*/
typedef union {
struct {
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
*/
uint32_t systimer_clk_fo:1;
/** etm_en : R/W; bitpos:... | 1,875 |
/*
*/
#pragma once
#include "interrupt_matrix_reg.h"
#include "plic_reg.h"
#include "soc/soc_caps.h"
#define INTERRUPT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG PLIC_MXINT_THRESH_REG
/**
*/
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_... | 1,878 |
/**
*/
/* NOTE: this file is created manually for compatibility */
#pragma once
#include
#include "soc/gpio_ext_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct {
volatile gpio_pad_comp_config_reg_t *pad_comp_config;
volatile gpio_pad_comp_filter_reg_t *pad_comp_filter;
volatil... | 1,879 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Trace memory configuration registers */
/** Type of mem_start_addr register
*/
typedef union {
struct {
/** mem_staet_addr : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t mem_staet_addr:32;
};
uint32_... | 1,881 |
/*
*/
#pragma once
/**
*/
#define I2C_BIAS 0X6A
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS_DREG_0P8 0
#define I2C_BIAS_DREG_0P8_MSB 7
#define I2C_BIAS_DREG_0P8_LSB 4
#define I2C_BIAS_DREG_1P1_PVT 1
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
#define I2C_BIAS_DREG_1P1_PVT_LSB 0
| 1,886 |
/*
*/
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 23
#define U0TXD_GPIO_NUM 24
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U1RXD_G... | 1,887 |
/*
*/
#pragma once
/**
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
| 1,888 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define I2C_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
/* I2C_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C0_CTRL 0x01FFFFFFU
#define I2C_MST_I2C0_CTRL_M (I2C_MST_I2C0_CTR... | 1,890 |
*/
#define I2C_MST_I2C1_BUSY (BIT(25))
#define I2C_MST_I2C1_BUSY_M (I2C_MST_I2C1_BUSY_V << I2C_MST_I2C1_BUSY_S)
#define I2C_MST_I2C1_BUSY_V 0x00000001U
#define I2C_MST_I2C1_BUSY_S 25
#define I2C_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
/* I2C_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;*/
/* descrip... | 1,890 |
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