text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
/*
*/
/*
*/
#pragma once
/* COMMON CAPS */
// #define SOC_ADC_SUPPORTED 1 //TODO: IDF-6496
#define SOC_ANA_CMPR_SUPPORTED 1
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: IDF-7552
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA... | 2,388 |
SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
/* SPI MEM CAPS */
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
//#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND ... | 2,388 |
5
#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
#define ... | 2,388 |
Actually there are 15 Touch channels, but channel 14 is not pinned out, limit to 14 channels
#define SOC_TOUCH_PROXIMITY_CHANNEL_NUM (3) // Sopport touch proximity channel number.
#define SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED (1) // Sopport touch proximity channel measure done interrupt type.
#define... | 2,388 |
< The UART hardware FIFO length */
#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */
#def... | 2,388 |
<Supports CRC only the stub code in RTC memory */
#define SOC_PM_CPU_RETENTION_BY_SW (0)
#define SOC_PM_PAU_LINK_NUM (4)
/* PSRAM CAPS */
#define SOC_PSRAM_VDD_POWER_MPLL (1)
/* CLOCK SUBSYSTEM CAPS */
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
#define SOC_MODEM_CLOCK_IS_INDEPENDENT ... | 2,388 |
< Temperature sensor is a separate module, not share regs with ADC */
#define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM (1)
/* Memory CAPS */
#define SOC_MEM_TCM_SUPPORTED (1)
#define SOC_MEM_NON_CONTIGUOUS_SRAM (1)
/* EMAC */
#define SOC_EMAC_USE_IO_MUX ... | 2,388 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PAU_REGDMA_CONF_REG register
*/
#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
*/
#define PAU_FLOW_ERR 0x00000007U
#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_F... | 2,390 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
*/
typedef union {
struct {
/** log_mode : R/W; bitpos: [3:0]; default: 0;
*/
uint32_t log_mode:4;
/** log_mem_loop_enable : R/W; bitpos: [... | 2,391 |
/**
*/
#pragma once
#include "soc/spi_mem_c_struct.h"
#include "soc/spi1_mem_c_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct spi1_mem_c_dev_s spi_mem_dev_t;
extern spi_mem_dev_t SPIMEM1;
extern spi_mem_c_dev_t SPIMEM0;
#ifdef __cplusplus
}
#endif
| 2,395 |
/*
*/
#ifndef _DPORT_ACCESS_H_
#define _DPORT_ACCESS_H_
#include
#include "soc.h"
#include "uart_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
*/
voi... | 2,397 |
/*
*/
#pragma once
#include "soc.h"
#include "soc/lpperi_reg.h"
//TODO: IDF-6522
/* Hardware random number generator register */
#define WDEV_RND_REG 0x600260b0
| 2,398 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of sigmadeltan register
*/
typedef union {
struct {
/** duty : R/W; bitpos: [7:0]; default: 0;
*/
uint32_t duty: 8;
/** prescale : R/W; bitpos: [15:8]; default: 25... | 2,400 |
h
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
*/
uint32_t sclk_div_a:6; //HP UART's sclk_div_a is in hp_sys_clkrst_struct.h
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
*/
uint32_t sclk_div_num:8; //HP UART's sclk_div_num is in hp_sys_clkrst_struct... | 2,402 |
/*
*/
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32P4.
#pragma once
//UART0 channels
#define UART_GPIO37_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 37
#define UART_GPIO38_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 38
#define U... | 2,403 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
/** Type of conf register
*/
typedef union {
struct {
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
*/
uint32_t systimer_clk_fo:1;
/** etm_en : R/W; bitpos:... | 2,405 |
/*
*/
#pragma once
#include "soc/clic_reg.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF)
#define INTERRUPT_CORE0_CPU_INT_... | 2,409 |
/**
*/
/* NOTE: this file is created manually for compatibility */
#pragma once
#include
#include "soc/gpio_struct.h"
#include "soc/lp_system_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct {
volatile lp_system_reg_pad_comp_reg_t *pad_comp_config;
volatile gpio_zero_det_filter_cnt... | 2,410 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Trace memory configuration registers */
/** Type of mem_start_addr register
*/
typedef union {
struct {
/** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t mem_start_addr:32;
};
uint32_... | 2,412 |
/*
*/
#pragma once
/**
*/
#define I2C_BIAS 0x6A
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS_DREG_1P6 0
#define I2C_BIAS_DREG_1P6_MSB 3
#define I2C_BIAS_DREG_1P6_LSB 0
#define I2C_BIAS_DREG_1P1 0
#define I2C_BIAS_DREG_1P1_MSB 7
#define I2C_BIAS_DREG_1P1_LSB 4
#define I2C_BIAS_DREG_1P1_P... | 2,415 |
/*
*/
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 38
#define U0TXD_GPIO_NUM 37
#define U0RTS_GPIO_NUM 8
#define U0CTS_GPIO_NUM 9
#define U1RXD_GPIO_NUM... | 2,417 |
/*
*/
#pragma once
/**
*/
| 2,420 |
/*
*/
#pragma once
#define ANA_CMPR0_EXT_REF_GPIO 51 /*!< The GPIO that can be used as external reference voltage */
#define ANA_CMPR0_SRC_GPIO 52 /*!< The GPIO that used for inputting the source signal to compare */
#define ANA_CMPR1_EXT_REF_GPIO 53 /*!< The GPIO that can be used as exte... | 2,427 |
/*
*/
#pragma once
/**
*/
#define I2C_CPLL 0x67
#define I2C_CPLL_HOSTID 0
#define I2C_CPLL_IR_CAL_DELAY 0
#define I2C_CPLL_IR_CAL_DELAY_MSB 3
#define I2C_CPLL_IR_CAL_DELAY_LSB 0
#define I2C_CPLL_IR_CAL_CK_DIV 0
#define I2C_CPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_CPLL_IR_CAL_CK_DI... | 2,431 |
/**
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#ifdef __cplusplus
}
#endif
| 2,438 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of config0 register
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
*/
uint32_t wdt_pause_in_slp:1;
/** ... | 2,439 |
/*
*/
#pragma once
#include "soc/soc.h"
#include "esp32p4/rom/cache.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef union {
struct {
uint32_t cat0 : 2;
uint32_t cat1 : 2;
uint32_t cat2 : 2;
uint32_t res0 : 8;
uint32_t splitaddr : 8;
uin... | 2,442 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
*/
uint32_t set_start:1;
uint32_t reserv... | 2,443 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
*/
typedef union {
struct {
uint32_t reserved_0:16;
/** ck_en_rng : R/W; bitpos: [16]; default: 1;
*/
uint32_t ck_en_rng:1;
/** ck_en_lp_tsen... | 2,445 |
/*
*/
#pragma once
#define LP_I2C_SCL_PAD_IN_IDX 0
#define LP_I2C_SCL_PAD_OUT_IDX 0
#define LP_I2C_SDA_PAD_IN_IDX 1
#define LP_I2C_SDA_PAD_OUT_IDX 1
#define LP_UART_RXD_PAD_IN_IDX 2... | 2,446 |
/*
*/
#pragma once
// Normal IOMUX pins
#define SPI2_FUNC_NUM 3
#define SPI2_IOMUX_PIN_NUM_HD 6
#define SPI2_IOMUX_PIN_NUM_CS 7
#define SPI2_IOMUX_PIN_NUM_MOSI 8
#define SPI2_IOMUX_PIN_NUM_CLK 9
#define SPI2_IOMUX_PIN_NUM_MISO 10
#define SPI2_IOMUX_PIN_NUM_WP 11
// When ... | 2,448 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control and configuration registers */
/** Type of tx_inst_cfg0 register
*/
typedef union {
struct {
/** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t tx_inst_idx:3;
/** tx_inst_pos : R/W... | 2,450 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitp... | 2,451 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitp... | 2,453 |
/*
*/
/*
*/
#pragma once
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"
#include "soc/sdmmc_pins.h"
| 2,455 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: clk_en */
/** Type of clk_en0 register
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} iomux_ms... | 2,456 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_INTR_SW_INT_RAW_REG register
*/
#define LP_INTR_SW_INT_RAW_REG (DR_REG_LP_INTR_BASE + 0x0)
/** LP_INTR_LP_SW_INT_RAW : R/W/WTC; bitpos: [31]; default: 0;
*/
#define LP_INTR_LP_SW_INT_RAW (BIT(31))
#define LP_INTR_LP... | 2,461 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** I2S_INT_RAW_REG register
*/
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define I2S_RX_DONE_INT_RAW (BIT(0))
#define I2S_RX_DONE_INT_RAW_M (I2S_R... | 2,463 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC... | 2,465 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Interrupt Registers */
/** Type of sw_int_raw register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lp_sw_int_raw : R/W/WTC; bitpos: [31]; default: 0;
*/
uint32_t lp_sw_int_raw:1;
};
... | 2,467 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: key register */
/** Type of key_0 register
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_0_reg_t;
/** Type of key_1 regist... | 2,468 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C"
{
#endif
#include
typedef struct emac_dma_dev_s {
volatile union {
struct {
uint32_t sw_rst : 1; /*When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after ... | 2,470 |
*/
uint32_t alt_desc_size : 1; /*When set the size of the alternate descriptor increases to 32 bytes.*/
uint32_t prog_burst_len : 6; /*These bits indicate the maximum number of beats to be transferred in one DMA transaction. If the number of beats to be transferred is more than 32 then perfor... | 2,470 |
*/
uint32_t rx_dma_pbl : 6; /*This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst tran... | 2,470 |
*/
uint32_t dmaaddralibea : 1; /*When this bit is set high and the FIXED_BURST bit is 1 the AHB interface generates all bursts aligned to the start address LS bits. If the FIXED_BURST bit is 0 the first burst (accessing the start address of data buffer) is not aligned but subsequent bursts are aligned t... | 2,470 |
If that descriptor is not available (owned by the Host) the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available the transmission resumes.*/
uint32_t dmarxpolldemand; /*When these bits are written with any value the DMA reads the current descri... | 2,470 |
Therefore these LSB bits are read-only.*/
volatile union {
struct {
uint32_t trans_int : 1; /*This bit indicates that the frame transmission is complete. When transmission is complete Bit[31] (OWN) of TDES0 is reset and the specific frame status information is updated in the Descripto... | 2,470 |
When the Jabber Timeout occurs the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.*/
uint32_t recv_ovflow : 1; /*This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame ... | 2,470 |
The Receive Process is suspended. To resume processing Receive descriptors the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the... | 2,470 |
When this bit is set the corresponding DMA engine disables all of its bus accesses.*/
uint32_t early_recv_int : 1; /*This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whiche... | 2,470 |
*/
uint32_t norm_int_summ : 1; /*Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Recei... | 2,470 |
Transferring the TX packets data from receive buffer to host memory.*/
uint32_t trans_proc_state : 3; /*This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Transmit Command issued. 3'b001: Running. Fetching Transmit Transfer Descript... | 2,470 |
3'b101: Error during Tx DMA Descriptor Write Access. 3'b110: Error during Rx DMA Descriptor Read Access. 3'b111: Error during Tx DMA Descriptor Read Access.*/
uint32_t reserved26 : 1;
uint32_t reserved27 : 1;
uint32_t pmt_int : 1; /*This bit indicates an interrupt event in the... | 2,470 |
The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared the Rx DMA operation is stopped after the transfer of the current frame.*/
uint32_t opt_second_frame : 1; /*When this bit is set it instructs the DMA to process the second frame of ... | 2,470 |
*/
uint32_t fwd_err_frame : 1; /*When this bit is reset the Rx FIFO drops frames with error status (CRC error collision error giant frame watchdog timeout or overflow).*/
uint32_t reserved8 : 1;
uint32_t reserved9 : 2;
uint32_t reserved11 : 2;
uint32_t... | 2,470 |
3'b000: 64 3'b001: 128 3'b010: 192 3'b011: 256 3'b100: 40 3'b101: 32 3'b110: 24 3'b111: 16 .*/
uint32_t reserved17 : 3;
uint32_t flush_tx_fifo : 1; /*When this bit is set the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flu... | 2,470 |
*/
uint32_t dis_drop_tcpip_err_fram : 1; /*When this bit is set the MAC does not drop the frames which only have errors detected by the Receive Checksum engine.When this bit is reset all error frames are dropped if the Fwd_Err_Frame bit is reset.*/
uint32_t reserved27 : 5;
};
u... | 2,470 |
*/
uint32_t dmain_tjte : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset the Transmit Jabber Timeout Interrupt is disabled.*/
uint32_t dmain_oie : 1; /*When this bit is set with Abnormal Interr... | 2,470 |
When this bit is reset the Receive Buffer Unavailable Interrupt is disabled.*/
uint32_t dmain_rse : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped Interrupt is disabled.*/
uint32... | 2,470 |
*/
uint32_t dmain_erie : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Early Receive Interrupt is enabled. When this bit is reset the Early Receive Interrupt is disabled.*/
uint32_t dmain_aise : 1; /*When this bit is set abnormal interrupt summary is enabled. Wh... | 2,470 |
Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt.*/
uint32_t reserved17 : 15;
};
uint32_t val;
} dmain_en;
volatile union {
struct {
uint32_t missed_fc : 16; /*This field indicates the number of frames missed by the controller because of the Host ... | 2,470 |
The counter is cleared when this register is read.*/
uint32_t overflow_bfoc : 1; /*This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows that is the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario the overflow frame counter is reset to all-z... | 2,470 |
*/
uint32_t reserved8 : 24;
};
uint32_t val;
} dmarintwdtimer;
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t reserved_34;
uint32_t reserved_38;
uint32_t reserved_3c;
uint32_t reserved_40;
uint32_t reserved_44;
uint32_t dmat... | 2,470 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: ADC1 control registers. */
/** Type of reader1_ctrl register
*/
typedef union {
struct {
/** sar1_clk_div : R/W; bitpos: [7:0]; default: 2;
*/
uint32_t sar1_clk_div:8;
uint32_t reserved_8:20;
... | 2,472 |
*/
/** Type of reader2_ctrl register
*/
typedef union {
struct {
/** sar2_clk_div : R/W; bitpos: [7:0]; default: 2;
*/
uint32_t sar2_clk_div:8;
uint32_t reserved_8:8;
/** sar2_wait_arb_cycle : R/W; bitpos: [17:16]; default: 1;
*/
uint32_t sar2_wait_arb_cyc... | 2,472 |
*/
/** Type of force_wpd_sar register
*/
typedef union {
struct {
/** force_xpd_sar1 : R/W; bitpos: [1:0]; default: 0;
*/
uint32_t force_xpd_sar1:2;
/** force_xpd_sar2 : R/W; bitpos: [3:2]; default: 0;
*/
uint32_t force_xpd_sar2:2;
uint32_t reserved_4:28;
... | 2,472 |
*/
/** Type of wakeup1 register
*/
typedef union {
struct {
/** sar1_wakeup_th_low : R/W; bitpos: [11:0]; default: 0;
*/
uint32_t sar1_wakeup_th_low:12;
uint32_t reserved_12:2;
/** sar1_wakeup_th_high : R/W; bitpos: [25:14]; default: 4095;
*/
uint32_t sar1... | 2,472 |
/*
*/
#pragma once
// TODO: IDF-5731
#define PMU_ICG_APB_ENA_CORE0_CPU 0
#define PMU_ICG_APB_ENA_CORE1_CPU 1
#define PMU_ICG_APB_ENA_CORE0_CLIC 2
#define PMU_ICG_APB_ENA_CORE1_CLIC 3
#define PMU_ICG_APB_ENA_MISC_CPU 4
#define PMU_ICG_APB_ENA_MISC_SYS 5
#define P... | 2,475 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
*/
uint32_t work_mode:2;
/** ecc_curve : R/... | 2,476 |
/*
*/
#pragma once
// The following macros are matched with the 2D-DMA peri_sel field peripheral selection ID
#define SOC_DMA2D_TRIG_PERIPH_JPEG_RX (0)
#define SOC_DMA2D_TRIG_PERIPH_PPA_SR_RX (1)
#define SOC_DMA2D_TRIG_PERIPH_PPA_BLEND_RX (2)
#define SOC_DMA2D_TRIG_PERIPH_M2M_RX (-1) //... | 2,478 |
uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook).
uint32_t mc: 2;
uint32_t reserved: 1;
};
uint32_t val;
} usb_dwc_dieptsiz_reg_t;
typedef union {
struct {
uint32_t dmaddr;
};
uint32_t val;
} usb_dwc_diepdma_reg_t;
typedef uni... | 2,485 |
uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook).
uint32_t rxdpid: 2;
uint32_t reserved_31: 1;
};
uint32_t val;
} usb_dwc_doeptsiz_reg_t;
typedef union {
struct {
uint32_t dmaaddr;
};
uint32_t val;
} usb_dwc_doepdma_reg_t;
typ... | 2,485 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define ANA_CONFIG_REG 0x5012401C
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_CONFIG2_REG 0x50124020
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)
| 2,487 |
/*
*/
#pragma once
#include "uECC.h"
/* Version uECC_verify() that also copies message_hash to verified_hash
if the signature is valid, and does it in a way that is harder to attack
with fault injection.
*/
int uECC_verify_antifault(const uint8_t *public_key,
const uint8_t *message_has... | 2,491 |
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 2,492 |
/*
*/
#pragma once
#include
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/task.h"
#include "esp_debug_helpers.h"
#include "esp_log.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef void (*shared_stack_function)(void);
#define ESP_EXECUTE_EXPRESSION_WITH_STACK(lock, stack, stack_si... | 2,493 |
/*
*/
#pragma once
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_ESP_IPC_ISR_ENABLE
/**
*/
typedef void (*esp_ipc_isr_func_t)(void* arg);
/**
*/
void esp_ipc_isr_call(esp_ipc_isr_func_t func, void* arg) ;
/**
*/
#define esp_ipc_isr_asm_call(func, arg) esp_ipc_isr_call(func, arg)... | 2,494 |
/*
*/
#pragma once
#include "sdkconfig.h"
#include
#include
#if CONFIG_IDF_TARGET_ARCH_RISCV
#include "libunwind-riscv.h"
#elif CONFIG_IDF_TARGET_X86
#include "libunwind-x86.h"
#else
/* This header must be a standalone one, so, it shall not trigger an error when
#define UNW_UNKNOWN_TARGET 1
typedef void* Executio... | 2,495 |
/*
*/
#ifndef __ESP_FREERTOS_HOOKS_H__
#define __ESP_FREERTOS_HOOKS_H__
#include
#include "freertos/portmacro.h"
#include "esp_err.h"
#ifdef __cplusplus
extern "C"
{
#endif
/*
Definitions for the tickhook and idlehook callbacks
*/
typedef bool (*esp_freertos_idle_cb_t)(void);
typedef void (*esp_freertos_tick_c... | 2,496 |
/*
*/
#ifndef __ESP_SYSTEM_H__
#define __ESP_SYSTEM_H__
#include
#include
#include "esp_err.h"
#include "esp_attr.h"
#include "esp_bit_defs.h"
#include "esp_idf_version.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
ESP_RST_UNKNOWN, //!< Reset reason can not be determined
ESP_RST_POW... | 2,497 |
< Reset by JTAG
ESP_RST_EFUSE, //!< Reset due to efuse error
ESP_RST_PWR_GLITCH, //!< Reset due to power glitch detected
ESP_RST_CPU_LOCKUP, //!< Reset due to CPU lock up
} esp_reset_reason_t;
/**
*/
typedef void (*shutdown_handler_t)(void);
/**
*/
esp_err_t esp_register_shutdown_handler(shutdown_... | 2,497 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __ASSEMBLER__
#include
#include "sdkconfig.h"
#include "soc/soc.h" // [refactor-todo] IDF-2297
#include "esp_err.h"
#include "esp_cpu.h"
/*
*/
typedef struct {
uint32_t pc; /* PC of the current frame */
uint32_t sp; /* SP of ... | 2,498 |
/*
*/
/* Notes:
*/
#ifndef _ESP_TASK_H_
#define _ESP_TASK_H_
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "freertos/FreeRTOSConfig.h"
#define ESP_TASK_PRIO_MAX (configMAX_PRIORITIES)
#define ESP_TASK_PRIO_MIN (0)
/* Bt contoller Task */
/* controller */
#define ESP_TASK_BT_CONTROLLER_PRIO (ES... | 2,499 |
/*
*/
#pragma once
#include
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct {
uint32_t timeout_ms; /**< TWDT timeout duration in milliseconds */
uint32_t idle_core_mask; /**< Bitmask of the core whose id... | 2,500 |
/*
*/
#pragma once
#include "esp_err.h"
#include "esp_etm.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
esp_err_t esp_systick_new_etm_alarm_event(int core_id, esp_etm_event_handle_t *out_event);
#ifdef __cplusplus
}
#endif
| 2,501 |
/*
*/
#pragma once
#include
#include "esp_err.h"
#include "esp_intr_alloc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
typedef struct {
uint8_t timeout; /*!< Watchdog timeout */
bool auto_backup_clk_enable; /*!< Enable automatic switch to backup clock at timeout */
} esp_xt_wdt_config_... | 2,502 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(CONFIG_FREERTOS_UNICORE) || defined(CONFIG_APPTRACE_GCOV_ENABLE)
/*
*/
/**
*/
typedef void (*esp_ipc_func_t)(void* arg);
/**
*/
esp_err_t esp_ipc_call(uint32_t cpu_id, esp_ipc_func_t func, void* arg);
/**
*/
esp_err_t esp_ipc_... | 2,503 |
/*
*/
#ifndef __ESP_CROSSCORE_INT_H
#define __ESP_CROSSCORE_INT_H
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void esp_crosscore_int_init(void);
/**
*/
void esp_crosscore_int_send_yield(int core_id);
/**
*/
void esp_crosscore_int_send_freq_switch(int core_id);
void esp_crosscore_int_s... | 2,504 |
/*
*/
#pragma once
#include
#include
#include "esp_macros.h"
#include "soc/soc_caps.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
extern bool g_panic_abort;
extern char *g_panic_abort_details;
extern void *g_exc_frames[SOC_CPU_CORES_NUM];
// Function to print longer amounts of information s... | 2,505 |
CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
void panic_print_char(char c);
void panic_print_str(const char *str);
void panic_print_dec(int d);
void panic_print_hex(int h);
#else
#define panic_print_char(c) ESP_UNUSED(c)
#define panic_print_str(str) ESP_UNUSED(str)
#define panic_print_dec(d) ESP_UNUSED(d)
#define ... | 2,505 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "esp_system.h"
/**
*/
void esp_restart_noos(void) __attribute__((noreturn));
/**
*/
void esp_restart_noos_dig(void) __attribute__((noreturn));
/**
*/
void esp_reset_reason_set_hint(esp_reset_reason_t hint);
/**
*/
esp_reset_reason_t esp_rese... | 2,506 |
/*
*/
#pragma once
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_ESP_IPC_ISR_ENABLE
/**
*/
void esp_ipc_isr_init(void);
#endif // CONFIG_ESP_IPC_ISR_ENABLE
#ifdef __cplusplus
}
#endif
| 2,507 |
/*
*/
#pragma once
#include
#include
#include
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
/**
*/
typedef void (*esp_usb_console_cb_t)(void* arg);
/**
*/
esp_err_t esp_usb_console_init(void);
/**
*/
ssize_t esp_usb_console_write_buf(const char* buf, size_t size);
/**
*/
ssize_t es... | 2,508 |
/*
*/
/**
*/
#pragma once
#include "freertos/FreeRTOS.h"
#include "spinlock.h"
#ifdef __cplusplus
extern "C" {
#endif
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32P4
/**
*/
#define OS_SPINLOCK 1
#else
#define OS_SPINLOCK 0
#endif
#if OS_SPINLOCK... | 2,509 |
lock_name = portMUX_INITIALIZER_UNLOCKED,
#else
#define INIT_CRIT_SECTION_LOCK_IN_STRUCT(lock_name)
#endif
/**
*/
#if OS_SPINLOCK == 1
#define esp_os_enter_critical(lock) portENTER_CRITICAL(lock)
#else
#define esp_os_enter_critical(lock) vPortEnterCritical()
#endif
/**
*/
#if OS_SPINLOCK == 1
#defin... | 2,509 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void esp_int_wdt_init(void);
/**
*/
void esp_int_wdt_cpu_init(void);
#ifdef __cplusplus
}
#endif
| 2,510 |
/*
*/
#pragma once
#include "sdkconfig.h"
#include "esp_err.h"
#if CONFIG_ESP_TASK_WDT_EN
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef void* twdt_ctx_t;
/**
*/
typedef void (*twdt_isr_callback)(void*);
/**
*/
esp_err_t esp_task_wdt_stop(void);
/**
*/
esp_err_t esp_task_wdt_restart(void);
#ifdef _... | 2,511 |
/*
*/
#ifndef EH_FRAME_PARSER_H
#define EH_FRAME_PARSER_H
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void esp_eh_frame_print_backtrace(const void *frame_or);
#ifdef __cplusplus
}
#endif
#endif // EH_FRAME_PARSER_H
| 2,512 |
/*
*/
#pragma once
#include "esp_err.h"
#include "../esp_task_wdt.h"
#include "esp_private/esp_task_wdt.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
esp_err_t esp_task_wdt_impl_timer_allocate(const esp_task_wdt_config_t *config,
twdt_isr_callback callback,
... | 2,513 |
/*
*/
#pragma once
#include "esp_attr.h"
#include "esp_err.h"
#include "esp_bit_defs.h"
#include "esp_cpu.h"
#include "soc/soc_caps.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
// Port layer defines the entry point. It then transfer control to a `sys_startup_fn_t`, stored in this
// array, on... | 2,514 |
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