text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
uint32_t cmd9: 1; /*The enable bit for SPI slave CMD9 interrupt.*/
uint32_t cmda: 1; /*The enable bit for SPI slave CMDA interrupt.*/
uint32_t reserved16: 16; /*reserved*/
};
uint32_t val;... | 2,232 |
Can be configured in CONF state.*/
uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host. Can be configured in CONF state.*/
uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor. Can be ... | 2,232 |
0: Others. Can not be changed by CONF_buf.*/
uint32_t cmd6: 1; /*The raw bit for SPI slave CMD6 interrupt.*/
uint32_t cmd7: 1; /*The raw bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8: 1; /*The ... | 2,232 |
*/
uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The status bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The status bit for completing receivi... | 2,232 |
*/
uint32_t cmd7: 1; /*The status bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8: 1; /*The status bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9: 1; /*The status bit for SPI slave CMD9 interrupt... | 2,232 |
*/
uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor. Can be configured in CONF state.*/
uint32_t in_err_eof: 1; /*The clear bit for receiving error. Can be configured in CONF state.*/
uint32_t in_suc_eof: ... | 2,232 |
Can be changed by CONF_buf.*/
uint32_t outfifo_empty_err: 1; /*1: Clear spi_dma_outfifo_empty_err signal. 0: not valid. Can be changed by CONF_buf.*/
uint32_t cmd6: 1; /*The clear bit for SPI slave CMD6 interrupt.*/
uint32_t cmd7: ... | 2,232 |
*/
uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf1; /*The content of current in descri... | 2,232 |
*/
uint32_t out_dscr_state: 2; /*SPI dma out descriptor state.*/
uint32_t out_state: 3; /*SPI dma out data state.*/
uint32_t out_fifo_cnt: 7; /*The remains of SPI dma outfifo data.*/
uint32_t out_fifo_full: ... | 2,232 |
*/
};
uint32_t val;
} dma_in_status;
uint32_t data_buf[18]; /*data buffer*/
union {
struct {
uint32_t din0_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input w... | 2,232 |
Can be configured in CONF state.*/
uint32_t din4_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
... | 2,232 |
Can be configured in CONF state.*/
uint32_t timing_clk_ena: 1; /*1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state.*/
uint32_t reserved25: 7; /*reserved*/
};
uint32_t val;
} din_mode;
union {
st... | 2,232 |
.. Can be configured in CONF state.*/
uint32_t din4_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din5_num: 2; /*the input signals are... | 2,232 |
Can be configured in CONF state.*/
uint32_t dout1_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
... | 2,232 |
Can be configured in CONF state.*/
uint32_t dout5_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
... | 2,232 |
.. Can be configured in CONF state.*/
uint32_t dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t dout2_num: 2; /*the output signals are... | 2,232 |
.. Can be configured in CONF state.*/
uint32_t dout6_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t dout7_num: 2; /*the output signals are... | 2,232 |
*/
uint32_t lcd_mode_en: 1; /*1: Enable LCD mode output vsync hsync de. 0: Disable. Can be configured in CONF state.*/
};
uint32_t val;
} lcd_ctrl;
union {
struct {
uint32_t lcd_vb_front: 8; /*It is the vertical blank fro... | 2,232 |
*/
uint32_t reserved8: 8; /*reserved*/
uint32_t lcd_hsync_width: 7; /*It is the position of spi_hsync active pulse in a line. Can be configured in CONF state.*/
uint32_t hsync_idle_pol: 1; /*It is the idle value of spi_hsync. ... | 2,232 |
Can be configured in CONF state.*/
uint32_t d_de_mode: 3; /*the output spi_de is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
... | 2,232 |
0: spi_hsync pulse is valid only in active region lines in seg-trans.*/
uint32_t reserved17: 15; /*reserved*/
};
uint32_t val;
} lcd_d_mode;
union {
struct {
uint32_t d_dqs_num: 2; /*the output spi_dqs is delayed by sys... | 2,232 |
*/
uint32_t d_vsync_num: 2; /*the output spi_vsync is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t reserved10: 22; /*reserved*/
};
uint32_t val;
} lcd_d_... | 2,232 |
*/
uint32_t reserved28: 4; /*reserved*/
};
uint32_t val;
} date;
} spi_dev_t;
extern spi_dev_t GPSPI2; //FSPI
extern spi_dev_t GPSPI3; //HSPI
#ifndef __cplusplus
_Static_assert(sizeof(spi_dev_t)==0x400, "***invalid spi");
#endif
#ifdef __cplusplus
}
#endif
| 2,232 |
/**
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#ifdef __cplusplus
}
#endif
| 2,233 |
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 2,235 |
Finally, the actual
measured value of Tn is the value after subtracting lower bits of T0. */
#ifdef __cplusplus
}
#endif
| 2,235 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 2,236 |
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,237 |
// As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows.
#define SPI2_FUNC_NUM 4
#define SPI2_IOMUX_PIN_NUM_HD 9
#define SPI2_IOMUX_PIN_NUM_CS 10
#define SPI2_IOMUX_PIN_NUM_MOSI 11
#define SPI2_IOMUX_PIN_N... | 2,237 |
/*
*/
#pragma once
/**
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 1
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_C... | 2,239 |
/*
*/
#pragma once
#include "soc/usb_pins.h"
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"
#include "soc/touch_sensor_pins.h"
| 2,240 |
/*
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008)
/* I2S_RX_RESET_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define I2S_RX_RESET_ST (BIT(29))
#define I2S_RX_RESET_ST_M (BIT(29))
... | 2,242 |
*/
#define I2S_SIG_LOOPBACK (BIT(20))
#define I2S_SIG_LOOPBACK_M (BIT(20))
#define I2S_SIG_LOOPBACK_V 0x1
#define I2S_SIG_LOOPBACK_S 20
/* I2S_RX_LSB_FIRST_DMA : R/W ;bitpos:[19] ;default: 1'b1 ; */
/*description: 1:the data in DMA/APB transform from low bits*/
#define I2S_RX_LSB_FIRST_DMA (BIT(19))
#define I2S_RX... | 2,242 |
*/
#define I2S_DATA_ENABLE_DELAY 0x00000003
#define I2S_DATA_ENABLE_DELAY_M ((I2S_DATA_ENABLE_DELAY_V)= 88000/2^i2s_lc_fifo_timeout_shift*/
#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007
#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S))
#define I2S_LC_FIFO_TIMEOUT_SHIF... | 2,242 |
*/
#define I2S_RX_PCM_BYPASS (BIT(7))
#define I2S_RX_PCM_BYPASS_M (BIT(7))
#define I2S_RX_PCM_BYPASS_V 0x1
#define I2S_RX_PCM_BYPASS_S 7
/* I2S_RX_PCM_CONF : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
/*description: Compress/Decompress module configuration bits. 0: decompress
received data 1:compress received data*/
#... | 2,242 |
*/
#define I2S_EXT_ADC_START_EN (BIT(6))
#define I2S_EXT_ADC_START_EN_M (BIT(6))
#define I2S_EXT_ADC_START_EN_V 0x1
#define I2S_EXT_ADC_START_EN_S 6
/* I2S_LCD_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to enable LCD mode*/
#define I2S_LCD_EN (BIT(5))
#define I2S_LCD_EN_M (BIT(5))
#defin... | 2,242 |
*/
#define I2S_LCD_TX_SDX2_EN (BIT(2))
#define I2S_LCD_TX_SDX2_EN_M (BIT(2))
#define I2S_LCD_TX_SDX2_EN_V 0x1
#define I2S_LCD_TX_SDX2_EN_S 2
/* I2S_LCD_TX_WRX2_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: LCD WR double for one datum.*/
#define I2S_LCD_TX_WRX2_EN (BIT(1))
#define I2S_LCD_TX_WRX2_EN_M (B... | 2,242 |
*/
#define I2S_RX_BITS_MOD 0x0000003F
#define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S))
#define I2S_RX_BITS_MOD_V 0x3F
#define I2S_RX_BITS_MOD_S 18
/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:12] ;default: 6'd16 ; */
/*description: Set the bits to configure bit length of I2S transmitter channel.*/
#defi... | 2,242 |
0: XPD HALL is controlled by
FSM in ULP-coprocessor*/
#define SENS_XPD_HALL_FORCE (BIT(29))
#define SENS_XPD_HALL_FORCE_M (BIT(29))
#define SENS_XPD_HALL_FORCE_V 0x1
#define SENS_XPD_HALL_FORCE_S 29
/* SENS_XPD_HALL : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: Power on hall sensor and connect to VP and V... | 2,244 |
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 2,246 |
/*
*/
#pragma once
/**
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 1
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_O_DONE_FLAG 3
#define I2C_ULP_O_DONE_FLAG_MSB 0
#define I2C_ULP_O_DONE_FLAG_LSB 0
#define I2C_ULP_BG_O_DONE_FLAG 3
#define I2C_ULP_B... | 2,247 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,248 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
union {
struct {
uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/
uint32_t rx_reset: ... | 2,249 |
*/
uint32_t tx_bck_in_inv: 1; /*Set this bit to invert BCK signal input to the slave transmitter*/
uint32_t reserved25: 7;
};
uint32_t val;
} timing;
union {
struct {
uint32_t rx_data_num: 6; /*Threshold of da... | 2,249 |
1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t tx_24msb_en: 1; /*Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t reserved24: ... | 2,249 |
*/
uint32_t out_no_restart_clr: 1; /*don't use*/
uint32_t out_eof_mode: 1; /*DMA out EOF flag generation mode . 1: when dma has popped all data from the FIFO 0:when ahb has pushed all data to the FIFO*/
uint32_t outdscr_burst_en: 1; /*DMA ... | 2,249 |
0: 16 bytes 1: 32 bytes 2:64 bytes 3:reserved*/
uint32_t reserved16: 16;
};
uint32_t val;
} lc_conf;
union {
struct {
uint32_t wdata: 9;
uint32_t reserved9: 7;
uint32_t push: 1;
uint32_t... | 2,249 |
The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/
uint32_t reserved12: 20;
};
uint32_t val;
} lc_hung_conf;
uint32_t reserved_78;
uint32_t rese... | 2,249 |
*/
uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t tx_zeros_rm_en: 1; /*don't use*/
uint32_t reserved10: 22;
};
uint32_t val;
} conf1;
union {
... | 2,249 |
*/
uint32_t lcd_tx_sdx2_en: 1; /*Set this bit to duplicate data pairs (Frame Form 2) in LCD mode.*/
uint32_t data_enable_test_en: 1; /*for debug camera mode enable*/
uint32_t data_enable: 1; /*for debug camera mode enable*/
ui... | 2,249 |
*/
uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/
uint32_t tx_bits_mod: 6; /*Set the bits to configure bit length of I2S transmitter channel.*/
uint32_t rx_bits_mod: 6; /*Set the bits to configure b... | 2,249 |
0: external XTAL_32K 1: CLK from RTC pad X32P_C*/
#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23))
#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23))
#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1
#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23
/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
/*description: state of 32k_wdt*... | 2,250 |
0: XTAL div 4 1: CK8M*/
#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29))
#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29))
#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1
#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29
/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
/*description: CK8M force power up*/
#define RTC_CNTL_CK... | 2,250 |
2.3
/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
/*description: CK8M force no gating during sleep*/
#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16))
#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16))
#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1
#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16
/* RTC_CN... | 2,250 |
00: div128 01: div256 10: div512 11: div1024.*/
#define RTC_CNTL_CK8M_DIV 0x00000003
#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
#define RTC_CNTL_CK8M_DIV_V 0x3
#define RTC_CNTL_CK8M_DIV_S 4
/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: used to ... | 2,250 |
clear vld before set reg_rtc_ana_clk_div
then set vld to actually switch the clk*/
#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22))
#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22))
#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1
#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22
#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0... | 2,250 |
Only active when reg_sdio_force = 1*/
#define RTC_CNTL_DREFM_SDIO 0x00000003
#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S))
#define RTC_CNTL_DREFM_SDIO_V 0x3
#define RTC_CNTL_DREFM_SDIO_S 27
/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */
/*description: SW option... | 2,250 |
Only active when reg_sdio_force = 0*/
#define RTC_CNTL_SDIO_PD_EN (BIT(21))
#define RTC_CNTL_SDIO_PD_EN_M (BIT(21))
#define RTC_CNTL_SDIO_PD_EN_V 0x1
#define RTC_CNTL_SDIO_PD_EN_S 21
/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */
/*description: enable current limit*/
#define RTC_CNTL_SDIO_ENCURLI... | 2,250 |
0: no res 1: 6k 2: 4k 3: 2k*/
#define RTC_CNTL_SDIO_INITI 0x00000003
#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S))
#define RTC_CNTL_SDIO_INITI_V 0x3
#define RTC_CNTL_SDIO_INITI_S 13
/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */
/*description: ability to prev... | 2,250 |
Switch rtc main state*/
#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14))
#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14))
#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1
#define RTC_CNTL_COCPU_STATE_SWITCH_S 14
/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: ulp/cocpu should start to work*... | 2,250 |
1: IIR ? 2: IIR 1/8 3: Jitter*/
#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007
#define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S))
#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7
#define RTC_CNTL_TOUCH_FILTER_MODE_S 28
/* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;defa... | 2,250 |
uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook).
uint32_t pid: 2;
uint32_t dopng: 1;
};
uint32_t val;
} usb_dwc_hctsiz_reg_t;
typedef union {
struct {
uint32_t dmaaddr;
};
uint32_t val;
} usb_dwc_hcdma_reg_t;
typedef union {
... | 2,251 |
uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook).
uint32_t mc: 2;
uint32_t reserved: 1;
};
uint32_t val;
} usb_dwc_dieptsiz_reg_t;
typedef union {
struct {
uint32_t dmaddr;
};
uint32_t val;
} usb_dwc_diepdma_reg_t;
typedef uni... | 2,251 |
uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook).
uint32_t rxdpid: 2;
uint32_t reserved_31: 1;
};
uint32_t val;
} usb_dwc_doeptsiz_reg_t;
typedef union {
struct {
uint32_t dmaaddr;
};
uint32_t val;
} usb_dwc_doepdma_reg_t;
typ... | 2,251 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
/* Clear to enable APLL */
#define I2C_APLL_M (BIT(14))
/* Clear to enable BBPLL */
#define I2C_BBPLL_M (BIT(17))
/* Clear to en... | 2,252 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_LP_RTC_INTR_SOURCE = 0,
ETS_LP_WDT_INTR_SOURCE,
ETS_LP_TIMER_REG0_INTR_SOURCE,
ETS_LP_TIMER_REG1_INTR_SOURC... | 2,255 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of mode register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} sha_m... | 2,256 |
/*
*/
#pragma once
//Touch channels
/* Note: T14 is an internal channel that does not have a corresponding external GPIO. */
#define TOUCH_PAD_GPIO2_CHANNEL TOUCH_PAD_NUM0
#define TOUCH_PAD_NUM0_GPIO_NUM 2
#define TOUCH_PAD_GPIO3_CHANNEL TOUCH_PAD_NUM1
#define TOUCH_PAD_NUM1_GPIO_NUM 3
#define TO... | 2,258 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** KEYMNG_CLK_REG register
*/
#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1;
*/
#define KEYMNG_CLK_EN (BIT(0))
#define KEYMNG_CLK_EN_M (KEYMNG_CLK_EN_V << KEYMNG_CLK_E... | 2,260 |
*/
#define KEYMNG_USE_EFUSE_KEY_XTS (BIT(1))
#define KEYMNG_USE_EFUSE_KEY_XTS_M ((KEYMNG_USE_EFUSE_KEY_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_XTS_S))
#define KEYMNG_USE_EFUSE_KEY_XTS_V 0x1
#define KEYMNG_USE_EFUSE_KEY_XTS_S 1
/* KEYMNG_USE_EFUSE_KEY_ECDSA : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: Set this bit ... | 2,260 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */... | 2,264 |
< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
G... | 2,264 |
< GPIO33, input and output */
GPIO_NUM_34 = 34, /*!< GPIO34, input and output */
GPIO_NUM_35 = 35, /*!< GPIO35, input and output */
GPIO_NUM_36 = 36, /*!< GPIO36, input and output */
GPIO_NUM_37 = 37, /*!< GPIO37, input and output */
GPIO_NUM_38 = 38, /*!< GPIO38, input and output */
G... | 2,264 |
< GPIO51, input and output */
GPIO_NUM_52 = 52, /*!< GPIO52, input and output */
GPIO_NUM_53 = 53, /*!< GPIO53, input and output */
GPIO_NUM_54 = 54, /*!< GPIO54, input and output */
GPIO_NUM_MAX,
} gpio_num_t;
#ifdef __cplusplus
}
#endif
| 2,264 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tsens control registers. */
/** Type of ctrl register
*/
typedef union {
struct {
/** out : RO; bitpos: [7:0]; default: 0;
*/
uint32_t out:8;
/** ready : RO; bitpos: [8]; default: 0;
*/
... | 2,268 |
*/
/** Type of int_raw register
*/
typedef union {
struct {
/** cocpu_tsens_wake_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
*/
uint32_t cocpu_tsens_wake_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tsens_int_raw_reg_t;
/** Type of int_st register
*/
typedef un... | 2,268 |
*/
/** Type of clk_conf register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tsens_clk_conf_reg_t;
/** Group: Tsens wakeup control registers. */
/** Type of wakeup_ctrl register
... | 2,268 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_I2S_VAD_CONF_REG register
*/
#define LP_I2S_VAD_CONF_REG (DR_REG_LP_I2S_BASE + 0x0)
/** LP_I2S_VAD_EN : R/W; bitpos: [0]; default: 0;
*/
#define LP_I2S_VAD_EN (BIT(0))
#define LP_I2S_VAD_EN_M (LP_I2S_VAD_EN_V = 880... | 2,269 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// `LP_GPIO_MATRIX_CONST_ONE_INPUT` means connect logic 1 to the LP peripheral signal
#define LP_GPIO_MATRIX_CONST_ONE_INPUT (0x30)
// `LP_GPIO_MATRIX_CONST_ZERO_INPUT` means connect logic 0 to the LP peripheral signal
#define LP_GPIO_MATRIX_CONST_ZERO_IN... | 2,270 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RSA_M_MEM register
*/
#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
#define RSA_M_MEM_SIZE_BYTES 16
/** RSA_Z_MEM register
*/
#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
#define RSA_Z_MEM_SIZE_BYTES 16
/** RSA_Y_MEM registe... | 2,274 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define... | 2,276 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KE... | 2,278 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
union {
struct {
uint32_t target_lo: 32;
};
uint32_t val;
} lo;
union {
struct {
uint32_t target_hi: 16;
uint32_t reserved0: 15;
uint32_t e... | 2,280 |
/*
*/
#ifndef _SOC_BOOT_MODE_H_
#define _SOC_BOOT_MODE_H_
#include "soc.h"
/*SPI Boot*/
#define IS_1XXX(v) (((v)&0x08)==0x08)
/*Download Boot, SPI(or SDIO_V2)/UART0*/
#define IS_00XX(v) (((v)&0x0c)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
#def... | 2,281 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x3F)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3E)
#ifdef __cplusplus
}
#endif
| 2,282 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: I3C_SLV CONFIG REG */
/** Type of config register
*/
typedef union {
struct {
/** slvena : R/W; bitpos: [0]; default: 1;
*/
uint32_t slvena:1;
/** nack : R/W; bitpos: [1]; default: 0;
*/
... | 2,283 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
*/
#define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ... | 2,286 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ICM_VERID_FILEDS_REG register
*/
#define ICM_VERID_FILEDS_REG (DR_REG_ICM_BASE + 0x0)
/** ICM_REG_VERID : RO; bitpos: [31:0]; default: 875574314;
*/
#define ICM_REG_VERID 0xFFFFFFFFU
#define ICM_REG_VERID_M (ICM_REG_V... | 2,289 |
/*
*/
#pragma once
/**
*/
| 2,292 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TSENS_CTRL_REG register
*/
#define TSENS_CTRL_REG (DR_REG_TSENS_BASE + 0x0)
/** TSENS_OUT : RO; bitpos: [7:0]; default: 0;
*/
#define TSENS_OUT 0x000000FFU
#define TSENS_OUT_M (TSENS_OUT_V << TSENS_OUT_S)
#define TSEN... | 2,294 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HUK_CLK_REG register
*/
#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
*/
#define HUK_CLK_EN (BIT(0))
#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S)
#define HUK_CLK_EN_... | 2,295 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HM... | 2,297 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: ICM AXI VERID FILEDS REG */
/** Type of verid_fileds register
*/
typedef union {
struct {
/** reg_verid : RO; bitpos: [31:0]; default: 875574314;
*/
uint32_t reg_verid:32;
};
uint32_t val;
} icm_veri... | 2,302 |
/*
*/
#pragma once
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GP... | 2,303 |
/*
*/
#pragma once
/*
Note: These macros are deprecated.
We define them for P4 only for backward compatibility with older version of esp_tinyusb
Todo: Remove in IDF v6.0 (IDF-9029)
*/
#define USBPHY_VP_NUM -1
#define USBPHY_VM_NUM -1
#define USBPHY_RCV_NUM -1
#define USBPHY_OEN_NUM -1
#define USBPHY_VPO_NUM -1
#def... | 2,304 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of i2c0_ctrl register
*/
typedef union {
struct {
/** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
*/
uint32_t i2c0_ctrl:25;
/** i2c0_busy : RO; bitpos: [25]; default: ... | 2,307 |
/**
*/
#pragma once
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CLK 43
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CMD 44
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D0 39
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D1 40
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D2 41
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D3 42
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D4 45
#de... | 2,309 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
#define SOC_IRAM0_ADDRESS_LOW 0x4ff00000
#define SOC_IRAM0_ADDRESS_HIGH 0x4ffc0000
#define SOC_DRAM0_ADDRESS_LOW ... | 2,310 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: TEE PMS DATE REG */
/** Type of pms_date register
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [31:0]; default: 2294537;
*/
uint32_t tee_date:32;
};
uint32_t val;
} tee_pms_date_reg_t;
/... | 2,313 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32P4 Root Clock Source
*/
/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!, F
/**
*/
typedef... | 2,314 |
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