text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
< PLL_F25M_CLK is derived from MPLL (clock gating + configurable divider), it will have a frequency of 25MHz */
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from SPLL (clock gating + "fixed" divider of 6), it has a fixed frequency of 80MHz */
SOC_MOD_CLK_PLL_F160M, ... | 2,314 |
< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes f... | 2,314 |
< LP_PERI_CLK is derived from LP_DYN_FAST (configurable divider) */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
} soc_module_clk_t;
//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////... | 2,314 |
< Select PLL_F80M as the source clock */
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Selec... | 2,314 |
< Select PLL_F80M as the source clock */
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} s... | 2,314 |
< UART source clock is PLL_F80M */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F... | 2,314 |
< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
*/
#define SOC_MCPWM_CAPTURE_CLKS {... | 2,314 |
< Select XTAL as the source clock */
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
} soc_periph_mcpwm_carrier_clk_src_t;
///////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
*/
#define SOC_... | 2,314 |
< Select PLL_F160M as the source clock */
LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LCD_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
} so... | 2,314 |
< Select XTAL as MIPI DSI DPI source clock */
MIPI_DSI_DPI_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as MIPI DSI DPI source clock */
MIPI_DSI_DPI_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as MIPI DSI DPI source clock */
MIPI_DSI_DPI_CLK_SRC_DEFAULT = SOC_MOD_C... | 2,314 |
< Select XTAL as the source clock */
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
} soc_periph_i2c_clk_src_t;
////////////////////////////////////... | 2,314 |
< Select SOC_MOD_CLK_SPLL as PSRAM source clock */
PSRAM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select SOC_MOD_CLK_XTAL as PSRAM source clock */
PSRAM_CLK_SRC_CPLL = SOC_MOD_CLK_CPLL, /*!< Select SOC_MOD_CLK_CPLL as PSRAM source clock */
PSRAM_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, ... | 2,314 |
< Select SOC_MOD_CLK_CPLL as FLASH source clock */
FLASH_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SOC_MOD_CLK_SPLL as FLASH source clock */
} soc_periph_flash_clk_src_t;
/////////////////////////////////////////////////ISP////////////////////////////////////////////////////////////////////
/**
*/
... | 2,314 |
< Select XTAL clock as the source clock */
SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////... | 2,314 |
< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
TWAI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
#endif
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
} soc_periph_twai_clk_src_t;
////////////////////////... | 2,314 |
< Select XTAL 40 MHz as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
/**
*/
#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
/**
*/
typedef enum {
... | 2,314 |
< Select XTAL as the source clock */
PARLIO_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the... | 2,314 |
< Select LP_PERI as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_LP_PERI, /*!< Select LP_PERI as the default choice */
} soc_periph_temperature_sensor_clk_src_t;
#ifdef __cplusplus
}
#endif
| 2,314 |
/*
*/
#pragma once
#ifndef __ASSEMBLER__
#include
#include "esp_assert.h"
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#define PRO_CPU_NUM (0)
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6
#define REG_UART_BASE(i) ... | 2,320 |
__ASSEMBLER__ */
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 10*1000000 )
#define CPU_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_MHZ_BTLD (90) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader s... | 2,320 |
#define SOC_DIRAM_IRAM_LOW 0x4ff00000
#define SOC_DIRAM_IRAM_HIGH 0x4ffc0000
#define SOC_DIRAM_DRAM_LOW 0x4ff00000
#define SOC_DIRAM_DRAM_HIGH 0x4ffc0000
#define SOC_DIRAM_ROM_RESERVE_HIGH 0x4ff40000
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
#define SOC_DMA_LOW 0x4ff00000
#define S... | 2,320 |
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
//CPU0 Interrupt number reserved in riscv/vector_clic.S, do not touch this.
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_MEMPROT_ERR_INUM ... | 2,320 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: USB wrapper registers. */
/** Type of otg_conf register
*/
typedef union {
struct {
/** srp_sessend_override : R/W; bitpos: [0]; default: 0;
*/
uint32_t srp_sessend_override:1;
/** srp_sessend_value ... | 2,323 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
*/
typedef union {
struct {
/** filter_thres : R/W; bitpos: [9:0]; default: 16;
*/
uint32_t filter_thres:10;
/** filter_en : R/W; bitpos: [10];... | 2,325 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: clk_en */
/** Type of clk_en register
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_iomux_... | 2,327 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: csi bridge regbank clock gating control register. */
/** Type of clk_en register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
... | 2,329 |
*/
/** Type of dma_req_cfg register
*/
typedef union {
struct {
/** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
*/
uint32_t dma_burst_len:12;
/** dma_cfg_upd_by_blk : R/W; bitpos: [12]; default: 0;
*/
uint32_t dma_cfg_upd_by_blk:1;
uint32_t reserved... | 2,329 |
*/
/** Type of data_type_cfg register
*/
typedef union {
struct {
/** data_type_min : R/W; bitpos: [5:0]; default: 24;
*/
uint32_t data_type_min:6;
uint32_t reserved_6:2;
/** data_type_max : R/W; bitpos: [13:8]; default: 47;
*/
uint32_t data_type_max:6;
... | 2,329 |
*/
/** Type of int_raw register
*/
typedef union {
struct {
/** vadr_num_gt_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
*/
uint32_t vadr_num_gt_int_raw:1;
/** vadr_num_lt_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
*/
uint32_t vadr_num_lt_int_raw:1;
/** ... | 2,329 |
*/
/** Type of host_ctrl register
*/
typedef union {
struct {
/** csi_enableclk : R/W; bitpos: [0]; default: 1;
*/
uint32_t csi_enableclk:1;
/** csi_cfg_clk_en : R/W; bitpos: [1]; default: 1;
*/
uint32_t csi_cfg_clk_en:1;
/** loopbk_test_en : R/W; bitpos: ... | 2,329 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of set_start register
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t ... | 2,330 |
/*
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 -1
#define SOC_GDMA_TRIG_PERIPH_I3C0 0
#define SOC_GDMA_TRIG_PERIPH_UHCI0 2
#define SOC_GDMA_TRIG_PERIPH_I2S0 3
#define SOC_GDMA_TRIG_PERIPH_I2S... | 2,338 |
/*
*/
#pragma once
#include "soc/interrupts.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PERIPH_MSPI_FLASH_MODULE = 0,
PERIPH_MSPI_PSRAM_MODULE,
PERIPH_EMAC_MODULE,
PERIPH_MIPI_DSI_MODULE,
PERIPH_MIPI_CSI_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PER... | 2,340 |
/*
*/
#pragma once
#ifndef __HWCRYPTO_REG_H__
#define __HWCRYPTO_REG_H__
#include "soc/aes_reg.h"
#include "soc/ds_reg.h"
#include "soc/hmac_reg.h"
#include "soc/rsa_reg.h"
#include "soc/sha_reg.h"
#endif
| 2,341 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DS_Y_MEM register
*/
#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
#define DS_Y_MEM_SIZE_BYTES 512
/** DS_M_MEM register
*/
#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
#define DS_M_MEM_SIZE_BYTES 512
/** DS_RB_MEM register
*/
... | 2,342 |
/*
*/
#pragma once
/**
*/
#define I2C_MPLL 0x63
#define I2C_MPLL_HOSTID 0
#define I2C_MPLL_IR_CAL_RSTB 1
#define I2C_MPLL_IR_CAL_RSTB_MSB 5
#define I2C_MPLL_IR_CAL_RSTB_lSB 5
#define I2C_MPLL_DIV_REG_ADDR 2
#define I2C_MPLL_REF_DIV_ADDR I2C_MPLL_DIV_... | 2,343 |
/*
*/
#pragma once
/**
*/
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 0
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 0
| 2,344 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Interrupt registers */
/** Type of int_raw register
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
*/
uint32_t calc_done_int_raw:1;
... | 2,346 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Type of GPIO register
*/
typedef union {
struct {
/** mcu_oe : R/W; bitpos: [0]; default: 0;
*/
uint32_t mcu_oe:1;
/** slp_sel : R/W; bitpos: [1]; default: 0;
*/
uint32_t slp_sel:1;
... | 2,351 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
Configuration Set ID: 11
*/
/* 3.1 Basic Config Parameters */
#define OTG_MODE 0
#define OTG_ARCHITECTURE 2
#define OTG_SINGLE_POINT 0
#define OTG_ENABLE_LPM 0
#define OTG_EN_DED_TX_FIFO 1
#define OTG_EN_DESC_DM... | 2,353 |
5 Endpoint Channel FIFO Configuration Parameters */
#define OTG_DFIFO_DEPTH 1024
#define OTG_DFIFO_DYNAMIC 1
#define OTG_RX_DFIFO_DEPTH 1024
#define OTG_TX_HNPERIO_DFIFO_DEPTH 1024
#define OTG_TX_HPERIO_DFIFO_DEPTH 1024
#define OTG_NPERIO_TX_QUEUE_DEPTH 4
#define OTG_PERIO_TX_QUEUE_D... | 2,353 |
8 Device Periodic FIFO Depth Parameters */
/* 3.9 Device IN Endpoint FIFO Depth Parameters */
#define OTG_TX_DINEP_DFIFO_DEPTH_0 512
#define OTG_TX_DINEP_DFIFO_DEPTH_1 512
#define OTG_TX_DINEP_DFIFO_DEPTH_2 512
#define OTG_TX_DINEP_DFIFO_DEPTH_3 512
#define OTG_TX_DINEP_DFIFO_DEPTH_4 512
#define OTG_TX_DINEP_DFIF... | 2,353 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory */
/** Group: Control / Configuration Registers */
/** Type of m_prime register
*/
typedef union {
struct {
/** m_prime : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t m_prime:32;
};
uint32_t ... | 2,354 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** USB_WRAP_OTG_CONF_REG register
*/
#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0)
/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0;
*/
#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0))
#define U... | 2,357 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of regdma_conf register
*/
typedef union {
struct {
/** flow_err : RO; bitpos: [2:0]; default: 0;
*/
uint32_t flow_err:3;
/** start : WT; bitpos: [3]; default: 0;
... | 2,359 |
/*
*/
#pragma once
//+Terminology+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| ... | 2,360 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of int_raw register
*/
typedef union {
struct {
/** scan_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
*/
uint32_t scan_done_int_raw:1;
/** done_int_raw : R/WTC/SS;... | 2,362 |
/*
*/
#pragma once
/**
*/
#define I2C_SYSPLL 0x66
#define I2C_SYSPLL_HOSTID 0
#define I2C_SYSPLL_IR_CAL_DELAY 0
#define I2C_SYSPLL_IR_CAL_DELAY_MSB 3
#define I2C_SYSPLL_IR_CAL_DELAY_LSB 0
#define I2C_SYSPLL_IR_CAL_CK_DIV 0
#define I2C_SYSPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_SYS... | 2,364 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: clk_en */
/** Type of clk_en register
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_gpio_c... | 2,367 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define... | 2,368 |
/*
*/
#pragma once
/**
*/
#define I2C_DIG_REG 0x6D
#define I2C_DIG_REG_HOSTID 0
#define I2C_DIG_REG_EXT_RTC_DREG 4
#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
#define I2C_DIG_REG_ENX_RTC_DREG 4
#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7
#define I2C_DIG_REG_ENX... | 2,370 |
/*
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define NLBITS 3
#define CLIC_EXT_INTR_NUM_OFFSET 16
#define DUALCORE_CLIC_CTRL_OFF 0x10000
#define DR_REG_CLIC_BASE ( 0x20800000 )
#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 )
#define CLIC_INT_CONFIG_REG ... | 2,371 |
*/
#define CLIC_INT_CONFIG_NVBITS (BIT(0))
#define CLIC_INT_CONFIG_NVBITS_M (BIT(0))
#define CLIC_INT_CONFIG_NVBITS_V 0x1
#define CLIC_INT_CONFIG_NVBITS_S 0
#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4)
/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */
/*description: .*/
#define CL... | 2,371 |
*/
#define CLIC_CPU_INT_THRESH 0x000000FF
#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S))
#define CLIC_CPU_INT_THRESH_V 0xFF
#define CLIC_CPU_INT_THRESH_S 24
#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i) * 4)
/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'... | 2,371 |
*/
#define CLIC_INT_ATTR_SHV (BIT(16))
#define CLIC_INT_ATTR_SHV_M (BIT(16))
#define CLIC_INT_ATTR_SHV_V 0x1
#define CLIC_INT_ATTR_SHV_S 16
/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */
/*description: .*/
#define CLIC_INT_IE (BIT(8))
#define CLIC_INT_IE_M (BIT(8))
#define CLIC_INT_IE_V 0x1
#define CLI... | 2,371 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
*/
typedef union {
struct {
/** log_mode : R/W; bitpos: [3:0]; default: 0;
*/
uint32_t log_mode:4;
/** log_mem_loop_enable : R/W; bitpos: [... | 2,375 |
/*
*/
#pragma once
#include "soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1)... | 2,376 |
*/
#define IO_MUX_DATE 0x0FFFFFFF
#define IO_MUX_DATE_M ((IO_MUX_DATE_V)<<(IO_MUX_DATE_S))
#define IO_MUX_DATE_V 0xFFFFFFF
#define IO_MUX_DATE_S 0
| 2,376 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SHA_MODE_REG register
*/
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
*/
#define SHA_MODE 0x00000007U
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
#define SHA_MODE_V 0x... | 2,377 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
typedef struct emac_mac_dev_s {
volatile union {
struct {
uint32_t pltf : 2; /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs o... | 2,378 |
*/
uint32_t deferralcheck : 1; /*Deferral Check.*/
uint32_t backofflimit : 2; /*The Back-Off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. Th... | 2,378 |
When a collision occurs on the MII interface the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the hal... | 2,378 |
This bit is read only with default value of 1'b1 in the full-duplex-mode.*/
uint32_t loopback : 1; /*When this bit is set the MAC operates in the loopback mode MII. The MII Receive clock input (CLK_RX) is required for the loopback to work properly because the transmit clock is not looped-back intern... | 2,378 |
In the 10/100 Mbps-only operations the bit is always 1.*/
uint32_t disablecrs : 1; /*When set high this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during... | 2,378 |
*/
uint32_t reserved21 : 1;
uint32_t jabber : 1; /*When this bit is set the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16 383 bytes. When this bit is reset the MAC cuts off the transmitter if the application sends out more than 2 048 bytes of data ... | 2,378 |
When Bit[20] (JE) is not set the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit[20] (JE) is not set the MAC considers all received frames of size more than 1 518 bytes (1 522 bytes for tagged) as Giant frames. When Bit[20] is set setting this bit has no e... | 2,378 |
If Bit[30] is set to 1 the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted frames.*/
uint32_t reserved31 : 1;
};
uint32_t val;
} gmacconfig;
volatile union {
struct {
uint32_t pmode : 1; /*When this bit is set the Addr... | 2,378 |
*/
uint32_t dbf : 1; /*When this bit is set the AFM(Address Filtering Module) module blocks all incoming broadcast frames. In addition it overrides all other filter settings. When this bit is reset the AFM module passes all received broadcast Frames.*/
uint32_t pcf : 2; /*These bits control... | 2,378 |
Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.*/
uint32_t saif : 1; /*When this bit is set the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Addre... | 2,378 |
The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset the Receiver module passes only those frames to the Application that pass the SA or DA address Filter.*/
};
uint32_t val;
} gmacff;
uint32_t reserved_1008;... | 2,378 |
Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed there is no change in the functionality of this bit even when the PHY is not Present.*/
uint32_t miiwrite : 1; /*When set this bit indicates to the PHY that this is a Write operation using the MII Data re... | 2,378 |
*/
uint32_t reserved16 : 16;
};
uint32_t val;
} emacmiidata;
volatile union {
struct {
uint32_t fcbba : 1; /*This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the ful... | 2,378 |
*/
uint32_t tfce : 1; /*In the full-duplex mode when this bit is set the MAC enables the flow control operation to transmit Pause frames. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode when this bit is set... | 2,378 |
*/
uint32_t plt : 2; /*This field configures the threshold of the Pause timer automatic retransmission of the Pause frame.The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example if PT = 100H (256 slot-times) and PLT = 01 then a second Pause frame is automat... | 2,378 |
When this bit is reset normal operation with automatic Zero-Quanta Pause frame generation is enabled.*/
uint32_t reserved8 : 8;
uint32_t pause_time : 16; /*This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be do... | 2,378 |
MACRFFCS[0] represents the status of small FIFO Write controller.*/
uint32_t reserved3 : 1;
uint32_t mtlrfwcas : 1; /*When high this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO.*/
uint32_t mtlrfrcs : 2; /*This fiel... | 2,378 |
*/
uint32_t mactfcs : 2; /*This field indicates the state of the MAC Transmit Frame Controller module: 2'b00: IDLE state. 2'b01: Waiting for status of previous frame or IFG or backoff period to be over. 2'b10: Generating and transmitting a Pause frame (in the full-duplex mode). 2'b11: Transferring inp... | 2,378 |
*/
uint32_t reserved23 : 1;
uint32_t mtltfnes : 1; /*When high this bit indicates that the MTL Tx FIFO is not empty and some data is left for Transmission.*/
uint32_t mtltsffs : 1; /*When high this bit indicates that the MTL TxStatus FIFO is full. Therefore the MTL cannot accept a... | 2,378 |
This bit must only be set when MGKPKTEN GLBLUCAST or RWKPKTEN bit is set high.*/
uint32_t mgkpkten : 1; /*When set enables generation of a power management event because of magic packet reception.*/
uint32_t rwkpkten : 1; /*When set enables generation of a power management event because of r... | 2,378 |
*/
uint32_t reserved29 : 2;
uint32_t rwkfiltrst : 1; /*When this bit is set it resets the RWKPTR register to 3’b000.*/
};
uint32_t val;
} pmt_csr;
volatile union {
struct {
uint32_t tlpien : 1; /*When set this bit indicates that the MAC Transmitter h... | 2,378 |
This bit is cleared by a read into this register.*/
uint32_t reserved4 : 4;
uint32_t tlpist : 1; /*When set this bit indicates that the MAC is transmitting the LPI pattern on the MII interface.*/
uint32_t rlpist : 1; /*When set this bit indicates that the MAC is receiving the LPI ... | 2,378 |
If the LPITXA and LPIEN bits are set to 1 the MAC enters the LPI mode only after all outstanding frames and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame.When this bit is 0 the LPIEN bit directly controls behavior of the MAC when it is entering or coming ... | 2,378 |
The default value of the LPI_LS_Timer is 1000 (1 sec) as defined in the IEEE standard.*/
uint32_t reserved26 : 6;
};
uint32_t val;
} gmaclpitimerscontrol;
volatile union {
struct {
uint32_t reserved0 : 1;
uint32_t reserved1 : 1;
uint32_t r... | 2,378 |
This bit is cleared on reading Bit[0] of Register (LPI Control and Status Register).*/
uint32_t reserved11 : 1;
uint32_t reserved12 : 20;
};
uint32_t val;
} emacints;
volatile union {
struct {
uint32_t reserved0 : 1;
uint32_t reserved1 : 1... | 2,378 |
The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
uint32_t reserved16 : 15;
uint32_t address_enable0 : 1; /*This bit is always set to 1.*/
};
uint32_t val;
} emacaddr0high;
uint32_t emaca... | 2,378 |
Bit[28]: EMACADDR1 High [7:0]. Bit[27]: EMACADDR1 Low [31:24]. Bit[24]: EMACADDR1 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
uint32_t source_address : 1; /*When this bit is set the EMACADDR1[47:0] is used to compare... | 2,378 |
*/
uint32_t reserved16 : 8;
uint32_t mask_byte_control2 : 6; /*These bits are mask control bits for comparison of each of the EMACADDR2 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR2 registers. Each bit controls the maski... | 2,378 |
*/
};
uint32_t val;
} emacaddr2high;
uint32_t emacaddr2low; /*This field contains the lower 32 bits of the third 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process.*/
volatile union {
struct {
... | 2,378 |
*/
uint32_t source_address3 : 1; /*When this bit is set the EMACADDR3[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR3[47:0] is used to compare with the DA fields of the received frame.*/
uint32_t address_enable3 : 1; /*When this bit... | 2,378 |
When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR4 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR4 High [15:8]. Bit[28]: EMACADDR4 High [7:0]. Bit[27]: EMACADDR4 Low [31:24]. Bit[24]: EMACADDR4 Low [7:0].You can fi... | 2,378 |
The content of this field is undefined so the register needs to be configured after the initialization process.*/
volatile union {
struct {
uint32_t mac_address5_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the sixth 6-byte MAC address.*/
uint32_t reserved16 : 8... | 2,378 |
When this bit is reset the EMACADDR5[47:0] is used to compare with the DA fields of the received frame.*/
uint32_t address_enable5 : 1; /*When this bit is set the address filter module uses the sixth MAC address for perfect filtering. When this bit is reset the address filter module ignores the addre... | 2,378 |
Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR6 High [15:8]. Bit[28]: EMACADDR6 High [7:0]. Bit[27]: EMACADDR6 Low [31:24]. Bit[24]: EMACADDR6 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
uint32... | 2,378 |
*/
volatile union {
struct {
uint32_t mac_address7_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the eighth 6-byte MAC Address.*/
uint32_t reserved16 : 8;
uint32_t mask_byte_control7 : 6; /*These bits are mask control bits for comparison of each of the ... | 2,378 |
*/
uint32_t address_enable7 : 1; /*When this bit is set the address filter module uses the eighth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/
};
uint32_t val;
} emacaddr7high;
uint32_t emacaddr7low; /*T... | 2,378 |
1'b1: Full-duplex mode.*/
uint32_t link_speed : 2; /*This bit indicates the current speed of the link: 2'b00: 2.5 MHz. 2'b01: 25 MHz. 2'b10: 125 MHz.*/
uint32_t reserved3 : 1;
uint32_t jabber_timeout : 1; /*This bit indicates whether there is jabber timeout error (1'b1) in the ... | 2,378 |
When this bit is cleared the watchdog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20] (JE) in EMACCONFIG_REG.*/
uint32_t reserved17 : 15;
};
uint32_t val;
} emacwdogto;
} emac_mac_dev_t;
extern emac_mac_dev_t EMAC_MAC;
#ifdef __cplusplus
}
#endif... | 2,378 |
/**
*/
#pragma once
#include "soc/spi_mem_c_reg.h"
#include "soc/spi1_mem_c_reg.h"
| 2,383 |
/*
*/
#include "soc/hp_system_reg.h"
| 2,384 |
/*
*/
#pragma once
| 2,385 |
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