wikipedia_id stringlengths 2 8 | wikipedia_title stringlengths 1 243 | url stringlengths 44 370 | contents stringlengths 53 2.22k | id int64 0 6.14M |
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74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
acted as commentator.
On June 22, 2006, Playboy Enterprises announced that it had bought ClubJenna Inc., along with an agreement to have both Jameson and Grdina stay on as contracted executives. Playboy CEO Christie Hefner said that she expected to rapidly increase film production, producing about thirty... | 6,900 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
for failing to properly account for and pay royalties on revenue earned by Patrick's website, clubtera.com.
## Books.
Jameson's autobiography, "" was published in 2004. It was co-written with Neil Strauss, a contributor to "The New York Times" and "Rolling Stone", and published by ReganBooks, a division... | 6,901 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
in January 2006.
The book covers her early career from her beginning in show business living with her tattoo artist boyfriend, through receiving the Pornographic Hot d'Or award at Cannes, and wedding pictures from her second marriage. It does not omit sordid details, describing her two rapes, drug addict... | 6,902 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
day before the book's launch. In April 2005, ReganBooks and Jameson filed lawsuits against each other. The point of contention was a proposed reality show about Jameson's everyday life, discussed between her then-husband, Jay Grdina, and the A&E Network. ReganBooks maintained that any A&E deal was a breac... | 6,903 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
Regan on December 15, 2006, over an unrelated issue.
In January 2007, Jameson was reported in talks with producers on turning the autobiography into a movie. In March 2007, Jameson was reportedly missing meetings with producers, thus endangering the movie, due to problems with a recent vaginoplasty.
In ... | 6,904 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
She has said: "I've always embraced my hard-core roots, but becoming a household name was an important thing to me."
In 1995, Jameson sent photos of herself to radio host Howard Stern. She became a regular guest on his show, appearing more than 30 times, and played the role of "Mandy", the "First Nude Wo... | 6,905 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
was ECW's on-screen interviewer. In 1998, she filmed a vignette with Val Venis, a character in the WWE, for airing on WWE programming. In the late 1990s, Jameson guest hosted several episodes of the E! cable network's hit travel/adventure/party show "Wild On!", appearing scantily clad in tropical location... | 6,906 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
of "Family Guy" entitled "Brian Does Hollywood". Her character won an award for acting in a porn film directed by Brian Griffin, and at the close of the episode Peter Griffin kidnaps her. In 2002, Jameson and Ron Jeremy played themselves in Comedy Central's first feature television movie "Porn 'n Chicken"... | 6,907 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
both the appearance and the voice for "Daisy", a secret playable character for the video game "Tony Hawk's Pro Skater 4", who performs provocative tricks with her clothing and skateboard. In 2003, Jameson appeared in two episodes of the NBC prime-time television show "Mister Sterling" as the girlfriend of... | 6,908 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
filmed in 2002 but had sat unreleased until 2005, when it was re-cut and released as "". She had another minor horror film role in "Sin-Jin Smyth", delayed from release until late 2006.
In February 2006, Comedy Central announced plans to feature Jameson as "P-Whip", in a starring role in its first animat... | 6,909 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
appearance in the U.S. reality TV show "The Simple Life" in the fifth-season episode "Committed", broadcast on July 1, 2007; Paris Hilton and Nicole Richie, while working in a "love camp", brought her in to help throw a "love ceremony" vow for the five dysfunctional couples. In 2008, Jameson had another s... | 6,910 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
appearances.
Some of her mainstream appearances sparked controversy. An interview with Jameson contained in the 1999 Abercrombie & Fitch "A&F Quarterly" was part of the motivation for Michigan Attorney General Jennifer Granholm and Illinois Lieutenant Governor Corinne Wood to speak out against the hybrid... | 6,911 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
out of my element, but, I could never pass this chance up ... it's a once in a lifetime thing." In the end, her side won the debate 204 to 27.
In February 2003, Pony International planned to feature her as one of several pornographic actors in advertisements for athletic shoes. This was attacked by Bill ... | 6,912 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
she had had sex with 100 women and 30 men off-screen in her life, but by 2008 she described herself as "totally hetero". She has stated the best relationship she ever had was her lesbian relationship with porn actress Nikki Tyler, which she documents in her autobiography. They lived together at the start ... | 6,913 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
Wicked Pictures projects involving both of them. They legally separated and divorced in March 2001, after Brad discovered her sexual affair with Jorge Araya Montoya (whom she met on a visit to Costa Rica).
Jameson met former pornographic studio owner Jay Grdina (born John G. Grdina), scion of a wealthy c... | 6,914 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
to retire from adult entertainment upon becoming a mother. The couple resided in Scottsdale, Arizona, in a Spanish-style mansion, bought for $2 million in 2002.
In November 2004, Jameson was diagnosed with skin cancer. Though surgery removed it, she miscarried shortly after the diagnosis. She was unable ... | 6,915 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
it was reported that Jameson began dating mixed martial artist and former UFC champion Tito Ortiz, whom she met on Myspace. Ortiz canceled a November 12, 2006 appearance as the guest of honor at the United States Marine Corps birthday ball at the Marine Corps Air Station Miramar in San Diego, when the Cor... | 6,916 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
Movie Awards while she was presenting an award. She also made brief appearances on two episodes of "The Celebrity Apprentice" to help Ortiz on the tasks assigned in those episodes.
Jameson announced in August 2008 that she and Ortiz were expecting twins in April 2009. On March 16, 2009, Jameson gave birt... | 6,917 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
socialite and writer Britney Markham became Jameson's personal assistant after having met on Twitter. In a 2014 interview with "LA Weekly", Markham claimed that Jameson would make requests for drugs. Markham posited that the pills of choice were Xanax, Ambien and Suboxone along with alcohol. At the same t... | 6,918 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
announced that she and her Israeli boyfriend, Lior Bitton, were expecting their first child together. On April 6, 2017, they welcomed a daughter, Batel Lu.
In June 2015, Jameson announced that she was converting to Judaism, in order to marry Bitton. She was raised Catholic. In October of that year, Israe... | 6,919 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
Treatment of Animals as part of the group's campaign against KFC's treatment of chickens.
Jameson supported Democrat Hillary Clinton in the 2008 United States presidential election, but Republican Mitt Romney in the 2012 United States presidential election, stating: "I'm very looking forward to a Republi... | 6,920 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
for November 2017 Playmate.
## Legal issues.
On April 26, 2010, Jameson's then-boyfriend, Tito Ortiz was arrested for felony domestic abuse at the couple's Huntington Beach, California home. Jameson was photographed afterward that day with a bandaged arm, amid accusations by both parties against each ot... | 6,921 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
three misdemeanor counts for driving under the influence of alcohol or other drugs, driving with a blood-alcohol level over the state legal limit, and driving on a suspended license after her Range Rover struck a light pole. She initially pleaded not guilty to the charges, but later changed her plea to gu... | 6,922 |
74573 | Jenna Jameson | https://en.wikipedia.org/w/index.php?title=Jenna%20Jameson | Jenna Jameson
or counts for driving under the influence of alcohol or other drugs, driving with a blood-alcohol level over the state legal limit, and driving on a suspended license after her Range Rover struck a light pole. She initially pleaded not guilty to the charges, but later changed her plea to guilty. She was s... | 6,923 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
Dynamic random-access memory
Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a separate tiny capacitor within an integrated circuit. The capacitor can either be charged or discharged; these two states are taken to represen... | 6,924 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory (vs. non-volatile memory), since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.
DRAM is w... | 6,925 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
is typically used where speed is of greater concern than cost and size, such as the cache memories in processors.
Due to its need of a system to perform refreshing, DRAM has more complicated circuitry and timing requirements than SRAM, but it is much more widely used. The advantage of DRAM... | 6,926 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
amounts of power, with different ways for managing the power consumption.
DRAM had a 47% increase in the price-per-bit in 2017, the largest jump in 30 years since the 45% percent jump in 1988, while in recent years the price has been going down.
# History.
The cryptanalytic machine code-... | 6,927 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
to top up those still charged (hence the term 'dynamic')".
The Toshiba ""Toscal" BC-1411" electronic calculator, which was introduced in November 1965, used a form of capacitive DRAM (180 bit) built from discrete memory cells. The same year, Arnold Farber and Eugene Schlig, working for IBM... | 6,928 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
Dennard at the IBM Thomas J. Watson Research Center. He was granted U.S. patent number 3,387,286 in 1968. Capacitors had been used for earlier memory schemes such as the drum of the Atanasoff–Berry Computer, the Williams tube and the Selectron tube.
DRAM chips were commercially introduced ... | 6,929 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
Honeywell. This became the first commercially available DRAM, the Intel 1103, in October 1970, despite initial problems with low yield until the fifth revision of the masks. The 1103 was designed by Joel Karp and laid out by Pat Earhart. The masks were cut by Barbara Maness and Judy Garcia.... | 6,930 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
of address lines required, which enabled it to fit into packages with fewer pins, a cost advantage that grew with every jump in memory size. The MK4096 proved to be a very robust design for customer applications. At the 16 Kbit density, the cost advantage increased; the 16 Kbit Mostek MK411... | 6,931 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
the Samsung KM48SL2000, which had a capacity of 16Mb, and was introduced in 1992. The first commercial DDR SDRAM (double data rate SDRAM) memory chip was Samsung's 64Mb DDR SDRAM chip, released in 1998.
# Principles of operation.
DRAM is usually arranged in a rectangular array of charge s... | 6,932 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
to the right does not include this important detail). They are generally known as the "+" and "−" bit lines.
A sense amplifier is essentially a pair of cross-connected inverters between the bit-lines. The first inverter is connected with input from the + bit-line and output to the − bit-li... | 6,933 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
that are in between high and low logic levels (e.g., 0.5 V if the two levels are 0 and 1 V). The bit-lines are physically symmetrical to keep the capacitance equal, and therefore at this time their voltages are equal.
- 3. The precharge circuit is switched off. Because the bit-lines are re... | 6,934 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
the storage cell (if the stored value is 0). Since the capacitance of the bit-line is typically much higher than the capacitance of the storage cell, the voltage on the bit-line increases very slightly if the storage cell's capacitor is discharged and decreases very slightly if the storage ... | 6,935 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
until one bit line is fully at the lowest voltage and the other is at the maximum high voltage. Once this has happened, the row is "open" (the desired cell data is available).
- 6. All storage cells in the open row are sensed simultaneously, and the sense amplifier outputs latched. A colum... | 6,936 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
This reinforces (i.e. "refreshes") the charge in the storage cell by increasing the voltage in the storage capacitor if it was charged to begin with, or by keeping it discharged if it was empty. Note that due to the length of the bit-lines there is a fairly long propagation delay for the ch... | 6,937 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
precharged again.
## To write to memory.
To store data, a row is opened and a given column's sense amplifier is temporarily forced to the desired high or low voltage state, thus causing the bit-line to charge or discharge the cell storage capacitor to the desired value. Due to the sense a... | 6,938 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
Refresh rate.
Typically, manufacturers specify that each row must be refreshed every 64 ms or less, as defined by the JEDEC standard.
Some systems refresh every row in a burst of activity involving all rows every 64 ms. Other systems refresh one row at a time staggered throughout the 64 m... | 6,939 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
of the row that will be refreshed next is maintained by external logic or a counter within the DRAM. A system that provides the row address (and the refresh command) does so to have greater control over when to refresh and which row to refresh. This is done to minimize conflicts with memory... | 6,940 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
row address.
Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes.
## Memory timing.
Many parameters are required to fully describe the timing of DRAM operation. Here are some examples for two timing grades of asynch... | 6,941 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
a 10 ns clock), the 50 ns DRAM can perform the first read in five clock cycles, and additional reads within the same page every two clock cycles. This was generally described as timing, as bursts of four reads within a page were common.
When describing synchronous memory, timing is describ... | 6,942 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
and even the premium 20 ns variety is only 2.5 times better compared to the typical case (~2.22 times better). CAS latency has improved even less, from to 10 ns. However, the DDR3 memory does achieve 32 times higher bandwidth; due to internal pipelining and wide data paths, it can output tw... | 6,943 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
DRAM arrays. Multiple DRAM memory cell variants exist, but the most commonly used variant in modern DRAMs is the one-transistor, one-capacitor (1T1C) cell. The transistor is used to admit current into the capacitor during writes, and to discharge the capacitor during reads. The access trans... | 6,944 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
voltage of -V/2 across the capacitor is required to store a logic zero. The electrical charge stored in the capacitor is measured in coulombs. For a logic one, the charge is: formula_1, where "Q" is the charge in coulombs and "C" is the capacitance in farads. A logic zero has a charge of: f... | 6,945 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
terminal is above V. If the capacitor contains a logic zero, it begins to discharge when the gate terminal voltage is above V.
## Capacitor design.
Up until the mid-1980s, the capacitors in DRAM cells were co-planar with the access transistor (they were constructed on the surface of the s... | 6,946 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
capacity. Starting in the mid-1980s, the capacitor has been moved above or below the silicon substrate in order to meet these objectives. DRAM cells featuring capacitors above the substrate are referred to as "stacked" or "folded plate" capacitors; whereas those with capacitors buried benea... | 6,947 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
smaller manufacturers such Nanya Technology use the trench capacitor structure (Jacob, pp. 355–357).
The capacitor in the stacked capacitor scheme is constructed above the surface of the substrate. The capacitor is constructed from an oxide-nitride-oxide (ONO) dielectric sandwiched in betw... | 6,948 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
usually made of metal, and the bitline has a polysilicon contact that extends downwards to connect it to the access transistor's source terminal. In the latter variation, the capacitor is constructed above the bitline, which is almost always made of polysilicon, but is otherwise identical t... | 6,949 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
this, but suffer from difficulties in inserting contacts in between bitlines, since the size of features this close to the surface are at or near the minimum feature size of the process technology (Kenner, pp. 33–42).
The trench capacitor is constructed by etching a deep hole into the sili... | 6,950 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
(Kenner, pp. 42–44). A trench capacitor's depth-to-width ratio in DRAMs of the mid-2000s can exceed 50:1 (Jacob, p. 357).
Trench capacitors have numerous advantages. Since the capacitor is buried in the bulk of the substrate instead of lying on its surface, the area it occupies can be mini... | 6,951 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
them to be more easily made planar, which enables it to be integrated in a logic-optimized process technology, which have many levels of interconnect above the substrate. The fact that the capacitor is under the logic means that it is constructed before the transistors are. This allows high... | 6,952 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
terminal (Kenner, pg. 44).
## Historical cell designs.
First-generation DRAM ICs (those with capacities of 1 Kbit), of which the first was the Intel 1103, used a three-transistor, one-capacitor (3T1C) DRAM cell. By the second-generation, the requirement to increase density by fitting more... | 6,953 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
without discharging it, avoiding the need to write back what was read out (non-destructive read). A second performance advantage relates to the 3T1C cell has separate transistors for reading and writing; the memory controller can exploit this feature to perform atomic read-modify-writes, wh... | 6,954 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
to as "1T DRAM", particularly in comparison to the 3T and 4T DRAM which it replaced in the 1970s.
In 1T DRAM cells, the bit of data is still stored in a capacitive region controlled by a transistor, but this capacitance is no longer provided by a separate capacitor. 1T DRAM is a "capacitor... | 6,955 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
process technologies.
Refreshing of cells remains necessary, but unlike with 1T1C DRAM, reads in 1T DRAM are non-destructive; the stored charge causes a detectable shift in the threshold voltage of the transistor. Performance-wise, access times are significantly better than capacitor-based... | 6,956 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
designed so that two adjacent DRAM cells in a column share a single bitline contact to reduce their area. DRAM cell area is given as "n" F, where "n" is a number derived from the DRAM cell design, and "F" is the smallest feature size of a given process technology. This scheme permits compar... | 6,957 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
wordlines and bitlines are limited. The wordline length is limited by the desired performance of the array, since propagation time of the signal that must transverse the wordline is determined by the RC time constant. The bitline length is limited by its capacitance (which increases with le... | 6,958 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
are required to read the state contained in the DRAM cells. When the access transistor is activated, the electrical charge in the capacitor is shared with the bitline. The bitline's capacitance is much greater than that of the capacitor (approximately ten times). Thus, the change in bitline... | 6,959 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
amplifiers function effectively and efficient only if the capacitance and voltages of these bitline pairs are closely matched. Besides ensuring that the lengths of the bitlines and the number of attached DRAM cells attached to them are equal, two basic architectures to array design have eme... | 6,960 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
segments. Because the sense amplifiers are placed between bitline segments, to route their outputs outside the array, an additional layer of interconnect placed above those used to construct the wordlines and bitlines is required.
The DRAM cells that are on the edges of the array do not ha... | 6,961 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
to noise, which affects the effectiveness of the differential sense amplifiers. Since each bitline segment does not have any spatial relationship to the other, it is likely that noise would affect only one of the two bitline segments.
### Folded bitline arrays.
The folded bitline array ar... | 6,962 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
is referred to as "folded" because it takes its basis from the open array architecture from the perspective of the circuit schematic. The folded array architecture appears to remove DRAM cells in alternate pairs (because two DRAM cells share a single bitline contact) from a column, then mov... | 6,963 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
wires is inversely proportional to their pitch. The array folding and bitline twisting schemes that are used must increase in complexity in order to maintain sufficient noise reduction. Schemes that have desirable noise immunity characteristics for a minimal impact in area is the topic of c... | 6,964 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
area efficiency is an active area of research.
## Row and column redundancy.
The first DRAM integrated circuits did not have any redundancy. An integrated circuit with a defective DRAM cell would be discarded. Beginning with the 64 Kbit generation, DRAM arrays have included spare rows and... | 6,965 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
decoders (Jacob, pp. 358–361).
# Error detection and correction.
Electrical or magnetic interference inside a computer system can cause a single bit of DRAM to spontaneously flip to the opposite state. The majority of one-off ("soft") errors in DRAM chips occur as a result of background r... | 6,966 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
required logic is transparently implemented within DRAM chips or modules, enabling the ECC memory functionality for otherwise ECC-incapable systems. The extra memory bits are used to record parity and to enable missing data to be reconstructed by error-correcting code (ECC). Parity allows t... | 6,967 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
per hour, per gigabyte of memory to one bit error, per century, per gigabyte of memory. The Schroeder et al. 2009 study reported a 32% chance that a given computer in their study would suffer from at least one correctable error per year, and provided evidence that most such errors are inter... | 6,968 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
an approximately 26% chance for total memory) that a computer would have a memory error every eight months.
# Security.
## Data remanence.
Although dynamic memory is only specified and "guaranteed" to retain its contents when supplied with power and refreshed every short period of time (... | 6,969 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
rebooted, and the contents of the main memory read out; or by removing a computer's memory modules, cooling them to prolong data remanence, then transferring them to a different computer to be read out. Such an attack was demonstrated to circumvent popular disk encryption systems, such as t... | 6,970 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
a read operation can cause soft errors. In particular, there is a risk that some charge can leak between nearby cells, causing the refresh or read of one row to cause a "disturbance error" in an adjacent or even nearby row. The awareness of disturbance errors dates back to the first commerc... | 6,971 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
RAM ICs are usually packaged in molded epoxy cases, with an internal lead frame for interconnections between the silicon die and the package leads. The original IBM PC design used ICs packaged in dual in-line packages, soldered directly to the main board or mounted in sockets. As memory den... | 6,972 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
or error correction. Over the evolution of desktop computers, several standardized types of memory module have been developed. Laptop computers, game consoles, and specialized devices may have their own formats of memory modules not interchangeable with standard desktop parts for packaging ... | 6,973 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
logic, and modification of the basic logic-optimized process technology to accommodate the process steps required to build DRAM cell structures.
# Versions.
Since the fundamental DRAM cell and array has maintained the same basic structure for many years, the types of DRAM are mainly disti... | 6,974 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
rare.
### Principles of operation.
An asynchronous DRAM chip has power connections, some number of address inputs (typically 12), and a few (typically one or four) bidirectional data lines. There are four active-low control signals:
- , the Row Address Strobe. The address inputs are capt... | 6,975 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
the falling edge of .
- , Output Enable. This is an additional signal that controls output to the data I/O pins. The data pins are driven by the DRAM chip if and are low, is high, and is low. In many applications, can be permanently connected low (output always enabled), but it can be usef... | 6,976 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
the signals are typically generated by a clocked memory controller, which limits their timing to multiples of the controller's clock cycle.
#### RAS Only Refresh (ROR).
Classic asynchronous DRAM is refreshed by opening each row in turn.
The refresh cycles are distributed across the entir... | 6,977 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
by supplying a row address and pulsing low; it is not necessary to perform any cycles. An external counter is needed to iterate over the row addresses in turn.
#### CAS before RAS refresh (CBR).
For convenience, the counter was quickly incorporated into the DRAM chips themselves. If the l... | 6,978 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
to maintain data output. If is then asserted again, this performs a CBR refresh cycle while the DRAM outputs remain valid. Because data output is not interrupted, this is known as "hidden refresh".
### Page mode DRAM.
"Page mode DRAM" is a minor modification to the first-generation DRAM I... | 6,979 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
a column address. For reads, after a delay ("t"), valid data would appear on the data out pins, which were held at high-Z before the appearance of valid data. For writes, the write enable signal and write data would be presented along with the column address.
Page mode DRAM was later impro... | 6,980 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
Prior to being asserted, the data out pins were held at high-Z. FPM DRAM reduced "t" latency.
"Static column" is a variant of fast page mode in which the column address does not need to be stored in, but rather, the address inputs may be changed with held low, and the data output will be u... | 6,981 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
DRAM).
"EDO DRAM", sometimes referred to as Hyper Page Mode enabled DRAM, is similar to Fast Page Mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (p... | 6,982 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
rises again. It holds the output valid (thus extending the data output time) until either is deasserted, or a new falling edge selects a different column address.
Single-cycle EDO has the ability to carry out a complete memory transaction in one clock cycle. Otherwise, each sequential RAM ... | 6,983 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
form factor, and battery life limitations. An EDO system with L2 cache was tangibly faster than the older FPM/L2 combination.
Single-cycle EDO DRAM became very popular on video cards towards the end of the 1990s. It was very low cost, yet nearly as efficient for performance as the far more... | 6,984 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
During a memory-read operation, the first part accessed the data from the memory array to the output stage (second latch). The second part drove the data bus from this latch at the appropriate logic level. Since the data is already in the output buffer, quicker access time is achieved (up t... | 6,985 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
memory interface, adding a clock (and a clock enable) line. All other signals are received on the rising edge of the clock.
The /RAS and /CAS inputs no longer act as strobes, but are instead, along with /WE, part of a 3-bit command:
The /OE line's function is extended to a per-byte "DQM" ... | 6,986 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
itself, namely the CAS latency. This is the number of clock cycles allowed for internal operations between a read command and the first data word appearing on the data bus. The "Load mode register" command is used to transfer this value to the SDRAM chip. Other configurable parameters inclu... | 6,987 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
bank is in progress". By alternating banks, an SDRAM device can keep the data bus continuously busy, in a way that asynchronous DRAM cannot.
### Single data rate synchronous DRAM (SDR SDRAM).
"Single data rate SDRAM" (sometimes known as "SDR") is the original generation of SDRAM; it made ... | 6,988 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
edge. DDR2 and DDR3 increased this factor to 4× and 8×, respectively, delivering 4-word and 8-word bursts over 2 and 4 clock cycles, respectively. The internal access rate is mostly unchanged (200 million per second for DDR-400, DDR2-800 and DDR3-1600 memory), but each access transfers more... | 6,989 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
high bandwidth, mainly intended for networking and caching applications.
## Graphics RAM.
Graphics RAMs are asynchronous and synchronous DRAMs designed for graphics-related tasks such as texture memory and framebuffers, found on video cards.
### Video DRAM (VRAM).
VRAM is a dual-ported ... | 6,990 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
text drawing and block fills.
### Multibank DRAM (MDRAM).
"Multibank DRAM" is a type of specialized DRAM developed by MoSys. It is constructed from small memory banks of , which are operated in an interleaved fashion, providing bandwidths suitable for graphics cards at a lower cost to mem... | 6,991 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
A graphics card with of MDRAM had enough memory to provide 24-bit color at a resolution of 1024×768—a very popular setting at the time.
### Synchronous graphics RAM (SGRAM).
"SGRAM" is a specialized form of SDRAM for graphics adaptors. It adds functions such as bit masking (writing to a s... | 6,992 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
designed to be used as the main memory of graphics processing units (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface,... | 6,993 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
Numonyx) is used in the Apple iPhone and other embedded systems such as XFlar Platform.
Some DRAM components have a "self-refresh mode". While this involves much of the same logic that is needed for pseudo-static operation, this mode is often equivalent to a standby mode. It is provided pr... | 6,994 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
and Wii video game consoles.
# See also.
- DRAM price fixing
- Flash memory
- List of device bit rates
- Memory bank
- Memory geometry
# References.
- Brent Keeth, R. Jacob Baker, Brian Johnson, Feng Lin. DRAM Circuit Design: Fundamental and High-Speed Topics
# Further reading.
- ... | 6,995 |
74567 | Dynamic random-access memory | https://en.wikipedia.org/w/index.php?title=Dynamic%20random-access%20memory | Dynamic random-access memory
ys, especially with respect to error-correcting code schemes
- Tezzaron Semiconductor Soft Error White Paper 1994 literature review of memory error rate measurements.
- Scaling and Technology Issues for Soft Error Rates A Johnston—4th Annual Research Conference on Reliability Stanford Uni... | 6,996 |
43712 | Parsis | https://en.wikipedia.org/w/index.php?title=Parsis | Parsis
Parsis
Parsis () or Parsees (which means 'Persian' in the Persian language) are a Zoroastrian community who migrated to the Indian subcontinent from Persia during the Muslim conquest of Persia of CE 636–651; one of two such groups (the other being Iranis). According to the "Qissa-i Sanjan", Parsis migrated from... | 6,997 |
43712 | Parsis | https://en.wikipedia.org/w/index.php?title=Parsis | Parsis
During this time many Iranians (who are now called Parsis since the migration to India) chose to preserve their religious identity by fleeing from Persia to India.
The word , pronounced "Parsian", i.e., "Parsi" in the Persian language, literally means "Persian". Note that "Farsi" is an arabization of the word "... | 6,998 |
43712 | Parsis | https://en.wikipedia.org/w/index.php?title=Parsis | Parsis
dynasty and the general social and political tumult of late 19th- and early 20th-century Iran. After having spent centuries in South Gujarat, particularly Udvada, Valsad and Navsari, the majority of the Parsi diaspora speak Gujarati.
# Definition and identity.
According to the Encyclopædia Britannica,Parsi, al... | 6,999 |
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