repo_id
stringlengths 5
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| size
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genetel200/u-boot
| 11,866
|
arch/m68k/cpu/mcf5227x/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*/
#include <asm-offsets.h>
#include <config.h>
#include "version.h"
#include <asm/cache.h>
#define _START _start
#define _FAULT _fault
#define SAVE_ALL \
move.w #0x2700,%sr; /* disable intrs */ \
subl #60,%sp; /* space for 15 regs */ \
moveml %d0-%d7/%a0-%a6,%sp@;
#define RESTORE_ALL \
moveml %sp@,%d0-%d7/%a0-%a6; \
addl #60,%sp; /* space for 15 regs */ \
rte;
#if defined(CONFIG_CF_SBF)
#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \
CONFIG_SYS_INIT_RAM_ADDR)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
CONFIG_SYS_INIT_RAM_ADDR)
#endif
.text
/*
* Vector table. This is used for initial platform startup.
* These vectors are to catch any un-intended traps.
*/
_vectors:
#if defined(CONFIG_CF_SBF)
INITSP: .long 0 /* Initial SP */
INITPC: .long ASM_DRAMINIT /* Initial PC */
#else
INITSP: .long 0 /* Initial SP */
INITPC: .long _START /* Initial PC */
#endif
vector02_0F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector10_17:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector18_1F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
#if !defined(CONFIG_CF_SBF)
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector30_3F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector64_127:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector128_191:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
#endif
#if defined(CONFIG_CF_SBF)
/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
asm_sbf_img_hdr:
.long 0x00000000 /* checksum, not yet implemented */
.long 0x00020000 /* image length */
.long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
asm_dram_init:
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1 /* init Rambar */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
/* Must disable global address */
move.l #0xFC008000, %a1
move.l #(CONFIG_SYS_CS0_BASE), (%a1)
move.l #0xFC008008, %a1
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
/*
* Dram Initialization
* a1, a2, and d0
*/
move.l #0xFC0A4074, %a1
move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
nop
/* SDRAM Chip 0 and 1 */
move.l #0xFC0B8110, %a1
move.l #0xFC0B8114, %a2
/* calculate the size */
move.l #0x13, %d1
move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
#ifdef CONFIG_SYS_SDRAM_BASE1
lsr.l #1, %d2
#endif
dramsz_loop:
lsr.l #1, %d2
add.l #1, %d1
cmp.l #1, %d2
bne dramsz_loop
/* SDRAM Chip 0 and 1 */
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
or.l %d1, (%a1)
#ifdef CONFIG_SYS_SDRAM_BASE1
move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
or.l %d1, (%a2)
#endif
nop
/* dram cfg1 and cfg2 */
move.l #0xFC0B8008, %a1
move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
nop
move.l #0xFC0B800C, %a2
move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
nop
move.l #0xFC0B8000, %a1 /* Mode */
move.l #0xFC0B8004, %a2 /* Ctrl */
/* Issue PALL */
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
/* Issue LEMR */
move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
nop
move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
nop
move.l #1000, %d0
wait1000:
nop
subq.l #1, %d0
bne wait1000
/* Issue PALL */
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
/* Perform two refresh cycles */
move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
nop
move.l %d0, (%a2)
move.l %d0, (%a2)
nop
move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
and.l #0x7FFFFFFF, %d0
or.l #0x10000c00, %d0
move.l %d0, (%a2)
nop
/*
* DSPI Initialization
* a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
* a1 - dspi status
* a2 - dtfr
* a3 - drfr
* a4 - Dst addr
*/
/* Enable pins for DSPI mode - chip-selects are enabled later */
move.l #0xFC0A4036, %a0
move.b #0x3F, %d0
move.b %d0, (%a0)
/* DSPI CS */
#ifdef CONFIG_SYS_DSPI_CS0
move.b (%a0), %d0
or.l #0xC0, %d0
move.b %d0, (%a0)
#endif
#ifdef CONFIG_SYS_DSPI_CS2
move.l #0xFC0A4037, %a0
move.b (%a0), %d0
or.l #0x10, %d0
move.b %d0, (%a0)
#endif
nop
/* Configure DSPI module */
move.l #0xFC05C000, %a0
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
move.l #0xFC05C00C, %a0
move.l #0x3E000011, (%a0)
move.l #0xFC05C034, %a2 /* dtfr */
move.l #0xFC05C03B, %a3 /* drfr */
move.l #(ASM_SBF_IMG_HDR + 4), %a1
move.l (%a1)+, %d5
move.l (%a1), %a4
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
move.l #0xFC05C02C, %a1 /* dspi status */
/* Issue commands and address */
move.l #0x8004000B, %d2 /* Fast Read Cmd */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Address byte 2 */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Address byte 1 */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Address byte 0 */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Dummy Wr and Rd */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
/* Transfer serial boot header to sram */
asm_dspi_rd_loop1:
move.l #0x80040000, %d2
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.b %d1, (%a0) /* read, copy to dst */
add.l #1, %a0 /* inc dst by 1 */
sub.l #1, %d4 /* dec cnt by 1 */
bne asm_dspi_rd_loop1
/* Transfer u-boot from serial flash to memory */
asm_dspi_rd_loop2:
move.l #0x80040000, %d2
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.b %d1, (%a4) /* read, copy to dst */
add.l #1, %a4 /* inc dst by 1 */
sub.l #1, %d5 /* dec cnt by 1 */
bne asm_dspi_rd_loop2
move.l #0x00040000, %d2 /* Terminate */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
/* jump to memory and execute */
move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
move.l %a0, (%a1)
jmp (%a0)
asm_dspi_wr_status:
move.l (%a1), %d0 /* status */
and.l #0x0000F000, %d0
cmp.l #0x00003000, %d0
bgt asm_dspi_wr_status
move.l %d2, (%a2)
rts
asm_dspi_rd_status:
move.l (%a1), %d0 /* status */
and.l #0x000000F0, %d0
lsr.l #4, %d0
cmp.l #0, %d0
beq asm_dspi_rd_status
move.b (%a3), %d1
rts
#endif /* CONFIG_CF_SBF */
.text
. = 0x400
.globl _start
_start:
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
#if defined(CONFIG_CF_SBF)
move.l #CONFIG_SYS_TEXT_BASE, %d0
movec %d0, %VBR
#else
move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
/* invalidate and disable cache */
move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR1
/* initialize general use internal ram */
move.l #0, %d0
move.l #(ICACHE_STATUS), %a1 /* icache */
move.l #(DCACHE_STATUS), %a2 /* icache */
move.l %d0, (%a1)
move.l %d0, (%a2)
/* put relocation table address to a5 */
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
* then (and always) gd struct space will be reserved
*/
move.l %sp, -(%sp)
bsr board_init_f_alloc_reserve
/* update stack and frame-pointers */
move.l %d0, %sp
move.l %sp, %fp
/* initialize reserved area */
move.l %d0, -(%sp)
bsr board_init_f_init_reserve
/* run low-level CPU init code (from flash) */
bsr cpu_init_f
clr.l %sp@-
/* run low-level board init code (from flash) */
bsr board_init_f
/* board_init_f() does not return */
/******************************************************************************/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
link.w %a6,#0
move.l 8(%a6), %sp /* set new stack pointer */
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
1:
move.l (%a1)+, (%a3)+
cmp.l %a1,%a2
bgt.s 1b
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
clear_bss:
/*
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
bgt.s 6b
/*
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
sub.l #_start,%d1
add.l %a0,%d1
move.l %d1,(%a1)+
cmp.l %a2, %a1
bne 7b
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
jsr (%a1)
/******************************************************************************/
/* exception code */
.globl _fault
_fault:
bra _fault
.globl _exc_handler
_exc_handler:
SAVE_ALL
movel %sp,%sp@-
bsr exc_handler
addql #4,%sp
RESTORE_ALL
.globl _int_handler
_int_handler:
SAVE_ALL
movel %sp,%sp@-
bsr int_handler
addql #4,%sp
RESTORE_ALL
/******************************************************************************/
.globl version_string
version_string:
.ascii U_BOOT_VERSION_STRING, "\0"
.align 4
|
genetel200/u-boot
| 7,165
|
arch/m68k/cpu/mcf532x/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
* (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <asm-offsets.h>
#include <config.h>
#include "version.h"
#include <asm/cache.h>
#define _START _start
#define _FAULT _fault
#define SAVE_ALL \
move.w #0x2700,%sr; /* disable intrs */ \
subl #60,%sp; /* space for 15 regs */ \
moveml %d0-%d7/%a0-%a6,%sp@;
#define RESTORE_ALL \
moveml %sp@,%d0-%d7/%a0-%a6; \
addl #60,%sp; /* space for 15 regs */ \
rte;
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
.text
/*
* Vector table. This is used for initial platform startup.
* These vectors are to catch any un-intended traps.
*/
_vectors:
INITSP: .long 0x00000000 /* Initial SP */
INITPC: .long _START /* Initial PC */
vector02_0F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector10_17:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector18_1F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector30_3F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector64_127:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector128_191:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
.text
.globl _start
_start:
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
/* Set vector base register at the beginning of the Flash */
move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
#endif
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
move.l #CF_CACR_CINVA, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR1
#ifdef CONFIG_MCF5301x
move.l #(0xFC0a0010), %a0
move.w (%a0), %d0
and.l %d0, 0xEFFF
move.w %d0, (%a0)
#endif
/* initialize general use internal ram */
move.l #0, %d0
move.l #(ICACHE_STATUS), %a1 /* icache */
move.l #(DCACHE_STATUS), %a2 /* icache */
move.l %d0, (%a1)
move.l %d0, (%a2)
/* put relocation table address to a5 */
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
* then (and always) gd struct space will be reserved
*/
move.l %sp, -(%sp)
move.l #board_init_f_alloc_reserve, %a1
jsr (%a1)
/* update stack and frame-pointers */
move.l %d0, %sp
move.l %sp, %fp
/* initialize reserved area */
move.l %d0, -(%sp)
move.l #board_init_f_init_reserve, %a1
jsr (%a1)
/* run low-level CPU init code (from flash) */
move.l #cpu_init_f, %a1
jsr (%a1)
/* run low-level board init code (from flash) */
clr.l %sp@-
move.l #board_init_f, %a1
jsr (%a1)
/* board_init_f() does not return */
/******************************************************************************/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
link.w %a6,#0
move.l 8(%a6), %sp /* set new stack pointer */
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
1:
move.l (%a1)+, (%a3)+
cmp.l %a1,%a2
bgt.s 1b
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
clear_bss:
/*
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
bgt.s 6b
/*
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
sub.l #_start,%d1
add.l %a0,%d1
move.l %d1,(%a1)+
cmp.l %a2, %a1
bne 7b
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
jsr (%a1)
/******************************************************************************/
/* exception code */
.globl _fault
_fault:
bra _fault
.globl _exc_handler
_exc_handler:
SAVE_ALL
movel %sp,%sp@-
bsr exc_handler
addql #4,%sp
RESTORE_ALL
.globl _int_handler
_int_handler:
SAVE_ALL
movel %sp,%sp@-
bsr int_handler
addql #4,%sp
RESTORE_ALL
/******************************************************************************/
.globl version_string
version_string:
.ascii U_BOOT_VERSION_STRING, "\0"
.align 4
|
genetel200/u-boot
| 4,272
|
arch/nios2/cpu/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
/*
* icache and dcache configuration used only for start.S.
* the values are chosen so that it will work for all configuration.
*/
#define ICACHE_LINE_SIZE 32 /* fixed 32 */
#define ICACHE_SIZE_MAX 0x10000 /* 64k max */
#define DCACHE_LINE_SIZE_MIN 4 /* 4, 16, 32 */
#define DCACHE_SIZE_MAX 0x10000 /* 64k max */
/* RESTART */
.text
.global _start, _except_start, _except_end
_start:
wrctl status, r0 /* Disable interrupts */
/*
* ICACHE INIT -- only the icache line at the reset address
* is invalidated at reset. So the init must stay within
* the cache line size (8 words). If GERMS is used, we'll
* just be invalidating the cache a second time. If cache
* is not implemented initi behaves as nop.
*/
ori r4, r0, %lo(ICACHE_LINE_SIZE)
movhi r5, %hi(ICACHE_SIZE_MAX)
ori r5, r5, %lo(ICACHE_SIZE_MAX)
0: initi r5
sub r5, r5, r4
bgt r5, r0, 0b
br _except_end /* Skip the tramp */
/*
* EXCEPTION TRAMPOLINE -- the following gets copied
* to the exception address (below), but is otherwise at the
* default exception vector offset (0x0020).
*/
_except_start:
movhi et, %hi(_exception)
ori et, et, %lo(_exception)
jmp et
_except_end:
/*
* INTERRUPTS -- for now, all interrupts masked and globally
* disabled.
*/
wrctl ienable, r0 /* All disabled */
/*
* DCACHE INIT -- if dcache not implemented, initd behaves as
* nop.
*/
ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN)
movhi r5, %hi(DCACHE_SIZE_MAX)
ori r5, r5, %lo(DCACHE_SIZE_MAX)
mov r6, r0
1: initd 0(r6)
add r6, r6, r4
bltu r6, r5, 1b
/*
* RELOCATE CODE, DATA & COMMAND TABLE -- the following code
* assumes code, data and the command table are all
* contiguous. This lets us relocate everything as a single
* block. Make sure the linker script matches this ;-)
*/
nextpc r4
_cur: movhi r5, %hi(_cur - _start)
ori r5, r5, %lo(_cur - _start)
sub r4, r4, r5 /* r4 <- cur _start */
mov r8, r4
movhi r5, %hi(_start)
ori r5, r5, %lo(_start) /* r5 <- linked _start */
mov sp, r5 /* initial stack below u-boot code */
beq r4, r5, 3f
movhi r6, %hi(CONFIG_SYS_MONITOR_LEN)
ori r6, r6, %lo(CONFIG_SYS_MONITOR_LEN)
add r6, r6, r5
2: ldwio r7, 0(r4)
addi r4, r4, 4
stwio r7, 0(r5)
addi r5, r5, 4
bne r5, r6, 2b
3:
/* JUMP TO RELOC ADDR */
movhi r4, %hi(_reloc)
ori r4, r4, %lo(_reloc)
jmp r4
_reloc:
/* STACK INIT -- zero top two words for call back chain. */
addi sp, sp, -8
stw r0, 0(sp)
stw r0, 4(sp)
mov fp, sp
#ifdef CONFIG_DEBUG_UART
/* Set up the debug UART */
movhi r2, %hi(debug_uart_init@h)
ori r2, r2, %lo(debug_uart_init@h)
callr r2
#endif
/* Allocate and initialize reserved area, update SP */
mov r4, sp
movhi r2, %hi(board_init_f_alloc_reserve@h)
ori r2, r2, %lo(board_init_f_alloc_reserve@h)
callr r2
mov sp, r2
mov r4, sp
movhi r2, %hi(board_init_f_init_reserve@h)
ori r2, r2, %lo(board_init_f_init_reserve@h)
callr r2
/* Update frame-pointer */
mov fp, sp
/* Call board_init_f -- never returns */
mov r4, r0
movhi r2, %hi(board_init_f@h)
ori r2, r2, %lo(board_init_f@h)
callr r2
/*
* NEVER RETURNS -- but branch to the _start just
* in case ;-)
*/
br _start
/*
* relocate_code -- Nios2 handles the relocation above. But
* the generic board code monkeys with the heap, stack, etc.
* (it makes some assumptions that may not be appropriate
* for Nios). Nevertheless, we capitulate here.
*
* We'll call the board_init_r from here since this isn't
* supposed to return.
*
* void relocate_code (ulong sp, gd_t *global_data,
* ulong reloc_addr)
* __attribute__ ((noreturn));
*/
.text
.global relocate_code
relocate_code:
mov sp, r4 /* Set the new sp */
mov r4, r5
/*
* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
* and between __bss_start and __bss_end.
*/
movhi r5, %hi(__bss_start)
ori r5, r5, %lo(__bss_start)
movhi r6, %hi(__bss_end)
ori r6, r6, %lo(__bss_end)
beq r5, r6, 5f
4: stw r0, 0(r5)
addi r5, r5, 4
bne r5, r6, 4b
5:
movhi r8, %hi(board_init_r@h)
ori r8, r8, %lo(board_init_r@h)
callr r8
ret
|
genetel200/u-boot
| 2,684
|
arch/nios2/cpu/exceptions.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*/
#include <config.h>
#include <asm/opcodes.h>
.text
.align 4
.global _exception
.set noat
.set nobreak
_exception:
/* SAVE ALL REGS -- this allows trap and unimplemented
* instruction handlers to be coded conveniently in C
*/
addi sp, sp, -(33*4)
stw r0, 0(sp)
stw r1, 4(sp)
stw r2, 8(sp)
stw r3, 12(sp)
stw r4, 16(sp)
stw r5, 20(sp)
stw r6, 24(sp)
stw r7, 28(sp)
stw r8, 32(sp)
stw r9, 36(sp)
stw r10, 40(sp)
stw r11, 44(sp)
stw r12, 48(sp)
stw r13, 52(sp)
stw r14, 56(sp)
stw r15, 60(sp)
stw r16, 64(sp)
stw r17, 68(sp)
stw r19, 72(sp)
stw r19, 76(sp)
stw r20, 80(sp)
stw r21, 84(sp)
stw r22, 88(sp)
stw r23, 92(sp)
stw r24, 96(sp)
stw r25, 100(sp)
stw r26, 104(sp)
stw r27, 108(sp)
stw r28, 112(sp)
stw r29, 116(sp)
stw r30, 120(sp)
stw r31, 124(sp)
rdctl et, estatus
stw et, 128(sp)
/* If interrupts are disabled -- software interrupt */
rdctl et, estatus
andi et, et, 1
beq et, r0, 0f
/* If no interrupts are pending -- software interrupt */
rdctl et, ipending
beq et, r0, 0f
/* HARDWARE INTERRUPT: Call interrupt handler */
movhi r3, %hi(external_interrupt)
ori r3, r3, %lo(external_interrupt)
mov r4, sp /* ptr to regs */
callr r3
/* Return address fixup: execution resumes by re-issue of
* interrupted instruction at ea-4 (ea == r29). Here we do
* simple fixup to allow common exception return.
*/
ldw r3, 116(sp)
addi r3, r3, -4
stw r3, 116(sp)
br _exception_return
0:
/* TRAP EXCEPTION */
movhi r3, %hi(OPC_TRAP)
ori r3, r3, %lo(OPC_TRAP)
addi r1, ea, -4
ldw r1, 0(r1)
bne r1, r3, 1f
movhi r3, %hi(trap_handler)
ori r3, r3, %lo(trap_handler)
mov r4, sp /* ptr to regs */
callr r3
br _exception_return
1:
/* UNIMPLEMENTED INSTRUCTION EXCEPTION */
movhi r3, %hi(soft_emulation)
ori r3, r3, %lo(soft_emulation)
mov r4, sp /* ptr to regs */
callr r3
/* Restore regsisters and return from exception*/
_exception_return:
ldw r1, 4(sp)
ldw r2, 8(sp)
ldw r3, 12(sp)
ldw r4, 16(sp)
ldw r5, 20(sp)
ldw r6, 24(sp)
ldw r7, 28(sp)
ldw r8, 32(sp)
ldw r9, 36(sp)
ldw r10, 40(sp)
ldw r11, 44(sp)
ldw r12, 48(sp)
ldw r13, 52(sp)
ldw r14, 56(sp)
ldw r15, 60(sp)
ldw r16, 64(sp)
ldw r17, 68(sp)
ldw r19, 72(sp)
ldw r19, 76(sp)
ldw r20, 80(sp)
ldw r21, 84(sp)
ldw r22, 88(sp)
ldw r23, 92(sp)
ldw r24, 96(sp)
ldw r25, 100(sp)
ldw r26, 104(sp)
ldw r27, 108(sp)
ldw r28, 112(sp)
ldw r29, 116(sp)
ldw r30, 120(sp)
ldw r31, 124(sp)
addi sp, sp, (33*4)
eret
/*-------------------------------------------------------------*/
|
genetel200/u-boot
| 2,642
|
arch/sh/lib/ashrsi3.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
!
! __ashrsi3
!
! Entry:
!
! r4: Value to shift
! r5: Shifts
!
! Exit:
!
! r0: Result
!
! Destroys:
!
! (none)
!
.global __ashrsi3
.align 2
__ashrsi3:
mov #31,r0
and r0,r5
mova ashrsi3_table,r0
mov.b @(r0,r5),r5
#ifdef __sh1__
add r5,r0
jmp @r0
#else
braf r5
#endif
mov r4,r0
.align 2
ashrsi3_table:
.byte ashrsi3_0-ashrsi3_table
.byte ashrsi3_1-ashrsi3_table
.byte ashrsi3_2-ashrsi3_table
.byte ashrsi3_3-ashrsi3_table
.byte ashrsi3_4-ashrsi3_table
.byte ashrsi3_5-ashrsi3_table
.byte ashrsi3_6-ashrsi3_table
.byte ashrsi3_7-ashrsi3_table
.byte ashrsi3_8-ashrsi3_table
.byte ashrsi3_9-ashrsi3_table
.byte ashrsi3_10-ashrsi3_table
.byte ashrsi3_11-ashrsi3_table
.byte ashrsi3_12-ashrsi3_table
.byte ashrsi3_13-ashrsi3_table
.byte ashrsi3_14-ashrsi3_table
.byte ashrsi3_15-ashrsi3_table
.byte ashrsi3_16-ashrsi3_table
.byte ashrsi3_17-ashrsi3_table
.byte ashrsi3_18-ashrsi3_table
.byte ashrsi3_19-ashrsi3_table
.byte ashrsi3_20-ashrsi3_table
.byte ashrsi3_21-ashrsi3_table
.byte ashrsi3_22-ashrsi3_table
.byte ashrsi3_23-ashrsi3_table
.byte ashrsi3_24-ashrsi3_table
.byte ashrsi3_25-ashrsi3_table
.byte ashrsi3_26-ashrsi3_table
.byte ashrsi3_27-ashrsi3_table
.byte ashrsi3_28-ashrsi3_table
.byte ashrsi3_29-ashrsi3_table
.byte ashrsi3_30-ashrsi3_table
.byte ashrsi3_31-ashrsi3_table
ashrsi3_31:
rotcl r0
rts
subc r0,r0
ashrsi3_30:
shar r0
ashrsi3_29:
shar r0
ashrsi3_28:
shar r0
ashrsi3_27:
shar r0
ashrsi3_26:
shar r0
ashrsi3_25:
shar r0
ashrsi3_24:
shlr16 r0
shlr8 r0
rts
exts.b r0,r0
ashrsi3_23:
shar r0
ashrsi3_22:
shar r0
ashrsi3_21:
shar r0
ashrsi3_20:
shar r0
ashrsi3_19:
shar r0
ashrsi3_18:
shar r0
ashrsi3_17:
shar r0
ashrsi3_16:
shlr16 r0
rts
exts.w r0,r0
ashrsi3_15:
shar r0
ashrsi3_14:
shar r0
ashrsi3_13:
shar r0
ashrsi3_12:
shar r0
ashrsi3_11:
shar r0
ashrsi3_10:
shar r0
ashrsi3_9:
shar r0
ashrsi3_8:
shar r0
ashrsi3_7:
shar r0
ashrsi3_6:
shar r0
ashrsi3_5:
shar r0
ashrsi3_4:
shar r0
ashrsi3_3:
shar r0
ashrsi3_2:
shar r0
ashrsi3_1:
rts
shar r0
ashrsi3_0:
rts
nop
|
genetel200/u-boot
| 4,327
|
arch/sh/lib/movmem.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
.text
.balign 4
.global __movmem
.global __movstr
.set __movstr, __movmem
/* This would be a lot simpler if r6 contained the byte count
minus 64, and we wouldn't be called here for a byte count of 64. */
__movmem:
sts.l pr,@-r15
shll2 r6
bsr __movmemSI52+2
mov.l @(48,r5),r0
.balign 4
movmem_loop: /* Reached with rts */
mov.l @(60,r5),r0
add #-64,r6
mov.l r0,@(60,r4)
tst r6,r6
mov.l @(56,r5),r0
bt movmem_done
mov.l r0,@(56,r4)
cmp/pl r6
mov.l @(52,r5),r0
add #64,r5
mov.l r0,@(52,r4)
add #64,r4
bt __movmemSI52
! done all the large groups, do the remainder
! jump to movmem+
mova __movmemSI4+4,r0
add r6,r0
jmp @r0
movmem_done: ! share slot insn, works out aligned.
lds.l @r15+,pr
mov.l r0,@(56,r4)
mov.l @(52,r5),r0
rts
mov.l r0,@(52,r4)
.balign 4
.global __movmemSI64
.global __movstrSI64
.set __movstrSI64, __movmemSI64
__movmemSI64:
mov.l @(60,r5),r0
mov.l r0,@(60,r4)
.global __movmemSI60
.global __movstrSI60
.set __movstrSI60, __movmemSI60
__movmemSI60:
mov.l @(56,r5),r0
mov.l r0,@(56,r4)
.global __movmemSI56
.global __movstrSI56
.set __movstrSI56, __movmemSI56
__movmemSI56:
mov.l @(52,r5),r0
mov.l r0,@(52,r4)
.global __movmemSI52
.global __movstrSI52
.set __movstrSI52, __movmemSI52
__movmemSI52:
mov.l @(48,r5),r0
mov.l r0,@(48,r4)
.global __movmemSI48
.global __movstrSI48
.set __movstrSI48, __movmemSI48
__movmemSI48:
mov.l @(44,r5),r0
mov.l r0,@(44,r4)
.global __movmemSI44
.global __movstrSI44
.set __movstrSI44, __movmemSI44
__movmemSI44:
mov.l @(40,r5),r0
mov.l r0,@(40,r4)
.global __movmemSI40
.global __movstrSI40
.set __movstrSI40, __movmemSI40
__movmemSI40:
mov.l @(36,r5),r0
mov.l r0,@(36,r4)
.global __movmemSI36
.global __movstrSI36
.set __movstrSI36, __movmemSI36
__movmemSI36:
mov.l @(32,r5),r0
mov.l r0,@(32,r4)
.global __movmemSI32
.global __movstrSI32
.set __movstrSI32, __movmemSI32
__movmemSI32:
mov.l @(28,r5),r0
mov.l r0,@(28,r4)
.global __movmemSI28
.global __movstrSI28
.set __movstrSI28, __movmemSI28
__movmemSI28:
mov.l @(24,r5),r0
mov.l r0,@(24,r4)
.global __movmemSI24
.global __movstrSI24
.set __movstrSI24, __movmemSI24
__movmemSI24:
mov.l @(20,r5),r0
mov.l r0,@(20,r4)
.global __movmemSI20
.global __movstrSI20
.set __movstrSI20, __movmemSI20
__movmemSI20:
mov.l @(16,r5),r0
mov.l r0,@(16,r4)
.global __movmemSI16
.global __movstrSI16
.set __movstrSI16, __movmemSI16
__movmemSI16:
mov.l @(12,r5),r0
mov.l r0,@(12,r4)
.global __movmemSI12
.global __movstrSI12
.set __movstrSI12, __movmemSI12
__movmemSI12:
mov.l @(8,r5),r0
mov.l r0,@(8,r4)
.global __movmemSI8
.global __movstrSI8
.set __movstrSI8, __movmemSI8
__movmemSI8:
mov.l @(4,r5),r0
mov.l r0,@(4,r4)
.global __movmemSI4
.global __movstrSI4
.set __movstrSI4, __movmemSI4
__movmemSI4:
mov.l @(0,r5),r0
rts
mov.l r0,@(0,r4)
.global __movmem_i4_even
.global __movstr_i4_even
.set __movstr_i4_even, __movmem_i4_even
.global __movmem_i4_odd
.global __movstr_i4_odd
.set __movstr_i4_odd, __movmem_i4_odd
.global __movmemSI12_i4
.global __movstrSI12_i4
.set __movstrSI12_i4, __movmemSI12_i4
.p2align 5
L_movmem_2mod4_end:
mov.l r0,@(16,r4)
rts
mov.l r1,@(20,r4)
.p2align 2
__movmem_i4_even:
mov.l @r5+,r0
bra L_movmem_start_even
mov.l @r5+,r1
__movmem_i4_odd:
mov.l @r5+,r1
add #-4,r4
mov.l @r5+,r2
mov.l @r5+,r3
mov.l r1,@(4,r4)
mov.l r2,@(8,r4)
L_movmem_loop:
mov.l r3,@(12,r4)
dt r6
mov.l @r5+,r0
bt/s L_movmem_2mod4_end
mov.l @r5+,r1
add #16,r4
L_movmem_start_even:
mov.l @r5+,r2
mov.l @r5+,r3
mov.l r0,@r4
dt r6
mov.l r1,@(4,r4)
bf/s L_movmem_loop
mov.l r2,@(8,r4)
rts
mov.l r3,@(12,r4)
.p2align 4
__movmemSI12_i4:
mov.l @r5,r0
mov.l @(4,r5),r1
mov.l @(8,r5),r2
mov.l r0,@r4
mov.l r1,@(4,r4)
rts
mov.l r2,@(8,r4)
|
genetel200/u-boot
| 2,887
|
arch/sh/lib/lshrsi3.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
!
! __lshrsi3)
!
! Entry:
!
! r4: Value to shift
! r5: Shifts
!
! Exit:
!
! r0: Result
!
! Destroys:
!
! (none)
!
.global __lshrsi3
.align 2
__lshrsi3:
mov #31,r0
and r0,r5
mova __lshrsi3_table,r0
mov.b @(r0,r5),r5
#ifdef __sh1__
add r5,r0
jmp @r0
#else
braf r5
#endif
mov r4,r0
.align 2
__lshrsi3_table:
.byte __lshrsi3_0-__lshrsi3_table
.byte __lshrsi3_1-__lshrsi3_table
.byte __lshrsi3_2-__lshrsi3_table
.byte __lshrsi3_3-__lshrsi3_table
.byte __lshrsi3_4-__lshrsi3_table
.byte __lshrsi3_5-__lshrsi3_table
.byte __lshrsi3_6-__lshrsi3_table
.byte __lshrsi3_7-__lshrsi3_table
.byte __lshrsi3_8-__lshrsi3_table
.byte __lshrsi3_9-__lshrsi3_table
.byte __lshrsi3_10-__lshrsi3_table
.byte __lshrsi3_11-__lshrsi3_table
.byte __lshrsi3_12-__lshrsi3_table
.byte __lshrsi3_13-__lshrsi3_table
.byte __lshrsi3_14-__lshrsi3_table
.byte __lshrsi3_15-__lshrsi3_table
.byte __lshrsi3_16-__lshrsi3_table
.byte __lshrsi3_17-__lshrsi3_table
.byte __lshrsi3_18-__lshrsi3_table
.byte __lshrsi3_19-__lshrsi3_table
.byte __lshrsi3_20-__lshrsi3_table
.byte __lshrsi3_21-__lshrsi3_table
.byte __lshrsi3_22-__lshrsi3_table
.byte __lshrsi3_23-__lshrsi3_table
.byte __lshrsi3_24-__lshrsi3_table
.byte __lshrsi3_25-__lshrsi3_table
.byte __lshrsi3_26-__lshrsi3_table
.byte __lshrsi3_27-__lshrsi3_table
.byte __lshrsi3_28-__lshrsi3_table
.byte __lshrsi3_29-__lshrsi3_table
.byte __lshrsi3_30-__lshrsi3_table
.byte __lshrsi3_31-__lshrsi3_table
__lshrsi3_6:
shlr2 r0
__lshrsi3_4:
shlr2 r0
__lshrsi3_2:
rts
shlr2 r0
__lshrsi3_7:
shlr2 r0
__lshrsi3_5:
shlr2 r0
__lshrsi3_3:
shlr2 r0
__lshrsi3_1:
rts
shlr r0
__lshrsi3_14:
shlr2 r0
__lshrsi3_12:
shlr2 r0
__lshrsi3_10:
shlr2 r0
__lshrsi3_8:
rts
shlr8 r0
__lshrsi3_15:
shlr2 r0
__lshrsi3_13:
shlr2 r0
__lshrsi3_11:
shlr2 r0
__lshrsi3_9:
shlr8 r0
rts
shlr r0
__lshrsi3_22:
shlr2 r0
__lshrsi3_20:
shlr2 r0
__lshrsi3_18:
shlr2 r0
__lshrsi3_16:
rts
shlr16 r0
__lshrsi3_23:
shlr2 r0
__lshrsi3_21:
shlr2 r0
__lshrsi3_19:
shlr2 r0
__lshrsi3_17:
shlr16 r0
rts
shlr r0
__lshrsi3_30:
shlr2 r0
__lshrsi3_28:
shlr2 r0
__lshrsi3_26:
shlr2 r0
__lshrsi3_24:
shlr16 r0
rts
shlr8 r0
__lshrsi3_31:
shlr2 r0
__lshrsi3_29:
shlr2 r0
__lshrsi3_27:
shlr2 r0
__lshrsi3_25:
shlr16 r0
shlr8 r0
rts
shlr r0
__lshrsi3_0:
rts
nop
|
genetel200/u-boot
| 1,273
|
arch/sh/lib/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Vladimir Zapolskiy <vz@mleia.com>
* Copyright (C) 2007, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*/
#include <asm-offsets.h>
#include <config.h>
.text
.align 2
.global _start
_start:
#ifdef CONFIG_CPU_SH2
.long 0x00000010 /* Ppower ON reset PC*/
.long 0x00000000
.long 0x00000010 /* Manual reset PC */
.long 0x00000000
#endif
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
bsr 1f
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
add #(_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
mov.l r1, @r4
add #4, r4
cmp/hs r6, r4
bf 2b
mov.l ._bss_start, r4
mov.l ._bss_end, r5
mov #0, r1
3: mov.l r1, @r4 /* bss clear */
add #4, r4
cmp/hs r5, r4
bf 3b
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
mov.l ._sh_generic_init, r0
jsr @r0
mov #0, r4
loop:
bra loop
.align 2
._lowlevel_init: .long (lowlevel_init - (100b + 4))
._reloc_dst: .long _start
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._sh_generic_init: .long board_init_f
|
genetel200/u-boot
| 2,295
|
arch/sh/lib/udivsi3_i4i-Os.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2006 Free Software Foundation, Inc.
*/
/* Moderately Space-optimized libgcc routines for the Renesas SH /
STMicroelectronics ST40 CPUs.
Contributed by J"orn Rennecke joern.rennecke@st.com. */
/* Size: 186 bytes jointly for udivsi3_i4i and sdivsi3_i4i
sh4-200 run times:
udiv small divisor: 55 cycles
udiv large divisor: 52 cycles
sdiv small divisor, positive result: 59 cycles
sdiv large divisor, positive result: 56 cycles
sdiv small divisor, negative result: 65 cycles (*)
sdiv large divisor, negative result: 62 cycles (*)
(*): r2 is restored in the rts delay slot and has a lingering latency
of two more cycles. */
.balign 4
.global __udivsi3_i4i
.global __udivsi3_i4
.set __udivsi3_i4, __udivsi3_i4i
.type __udivsi3_i4i, @function
.type __sdivsi3_i4i, @function
__udivsi3_i4i:
sts pr,r1
mov.l r4,@-r15
extu.w r5,r0
cmp/eq r5,r0
swap.w r4,r0
shlr16 r4
bf/s large_divisor
div0u
mov.l r5,@-r15
shll16 r5
sdiv_small_divisor:
div1 r5,r4
bsr div6
div1 r5,r4
div1 r5,r4
bsr div6
div1 r5,r4
xtrct r4,r0
xtrct r0,r4
bsr div7
swap.w r4,r4
div1 r5,r4
bsr div7
div1 r5,r4
xtrct r4,r0
mov.l @r15+,r5
swap.w r0,r0
mov.l @r15+,r4
jmp @r1
rotcl r0
div7:
div1 r5,r4
div6:
div1 r5,r4; div1 r5,r4; div1 r5,r4
div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
divx3:
rotcl r0
div1 r5,r4
rotcl r0
div1 r5,r4
rotcl r0
rts
div1 r5,r4
large_divisor:
mov.l r5,@-r15
sdiv_large_divisor:
xor r4,r0
.rept 4
rotcl r0
bsr divx3
div1 r5,r4
.endr
mov.l @r15+,r5
mov.l @r15+,r4
jmp @r1
rotcl r0
.global __sdivsi3_i4i
.global __sdivsi3_i4
.global __sdivsi3
.set __sdivsi3_i4, __sdivsi3_i4i
.set __sdivsi3, __sdivsi3_i4i
__sdivsi3_i4i:
mov.l r4,@-r15
cmp/pz r5
mov.l r5,@-r15
bt/s pos_divisor
cmp/pz r4
neg r5,r5
extu.w r5,r0
bt/s neg_result
cmp/eq r5,r0
neg r4,r4
pos_result:
swap.w r4,r0
bra sdiv_check_divisor
sts pr,r1
pos_divisor:
extu.w r5,r0
bt/s pos_result
cmp/eq r5,r0
neg r4,r4
neg_result:
mova negate_result,r0
;
mov r0,r1
swap.w r4,r0
lds r2,macl
sts pr,r2
sdiv_check_divisor:
shlr16 r4
bf/s sdiv_large_divisor
div0u
bra sdiv_small_divisor
shll16 r5
.balign 4
negate_result:
neg r0,r0
jmp @r2
sts macl,r2
|
genetel200/u-boot
| 2,892
|
arch/sh/lib/ashlsi3.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
!
! GLOBAL(ashlsi3)
!
! Entry:
!
! r4: Value to shift
! r5: Shifts
!
! Exit:
!
! r0: Result
!
! Destroys:
!
! (none)
!
.global __ashlsi3
.align 2
__ashlsi3:
mov #31,r0
and r0,r5
mova __ashlsi3_table,r0
mov.b @(r0,r5),r5
#ifdef __sh1__
add r5,r0
jmp @r0
#else
braf r5
#endif
mov r4,r0
.align 2
__ashlsi3_table:
.byte __ashlsi3_0-__ashlsi3_table
.byte __ashlsi3_1-__ashlsi3_table
.byte __ashlsi3_2-__ashlsi3_table
.byte __ashlsi3_3-__ashlsi3_table
.byte __ashlsi3_4-__ashlsi3_table
.byte __ashlsi3_5-__ashlsi3_table
.byte __ashlsi3_6-__ashlsi3_table
.byte __ashlsi3_7-__ashlsi3_table
.byte __ashlsi3_8-__ashlsi3_table
.byte __ashlsi3_9-__ashlsi3_table
.byte __ashlsi3_10-__ashlsi3_table
.byte __ashlsi3_11-__ashlsi3_table
.byte __ashlsi3_12-__ashlsi3_table
.byte __ashlsi3_13-__ashlsi3_table
.byte __ashlsi3_14-__ashlsi3_table
.byte __ashlsi3_15-__ashlsi3_table
.byte __ashlsi3_16-__ashlsi3_table
.byte __ashlsi3_17-__ashlsi3_table
.byte __ashlsi3_18-__ashlsi3_table
.byte __ashlsi3_19-__ashlsi3_table
.byte __ashlsi3_20-__ashlsi3_table
.byte __ashlsi3_21-__ashlsi3_table
.byte __ashlsi3_22-__ashlsi3_table
.byte __ashlsi3_23-__ashlsi3_table
.byte __ashlsi3_24-__ashlsi3_table
.byte __ashlsi3_25-__ashlsi3_table
.byte __ashlsi3_26-__ashlsi3_table
.byte __ashlsi3_27-__ashlsi3_table
.byte __ashlsi3_28-__ashlsi3_table
.byte __ashlsi3_29-__ashlsi3_table
.byte __ashlsi3_30-__ashlsi3_table
.byte __ashlsi3_31-__ashlsi3_table
__ashlsi3_6:
shll2 r0
__ashlsi3_4:
shll2 r0
__ashlsi3_2:
rts
shll2 r0
__ashlsi3_7:
shll2 r0
__ashlsi3_5:
shll2 r0
__ashlsi3_3:
shll2 r0
__ashlsi3_1:
rts
shll r0
__ashlsi3_14:
shll2 r0
__ashlsi3_12:
shll2 r0
__ashlsi3_10:
shll2 r0
__ashlsi3_8:
rts
shll8 r0
__ashlsi3_15:
shll2 r0
__ashlsi3_13:
shll2 r0
__ashlsi3_11:
shll2 r0
__ashlsi3_9:
shll8 r0
rts
shll r0
__ashlsi3_22:
shll2 r0
__ashlsi3_20:
shll2 r0
__ashlsi3_18:
shll2 r0
__ashlsi3_16:
rts
shll16 r0
__ashlsi3_23:
shll2 r0
__ashlsi3_21:
shll2 r0
__ashlsi3_19:
shll2 r0
__ashlsi3_17:
shll16 r0
rts
shll r0
__ashlsi3_30:
shll2 r0
__ashlsi3_28:
shll2 r0
__ashlsi3_26:
shll2 r0
__ashlsi3_24:
shll16 r0
rts
shll8 r0
__ashlsi3_31:
shll2 r0
__ashlsi3_29:
shll2 r0
__ashlsi3_27:
shll2 r0
__ashlsi3_25:
shll16 r0
shll8 r0
rts
shll r0
__ashlsi3_0:
rts
nop
|
genetel200/u-boot
| 2,346
|
arch/sh/lib/ashiftrt.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
.global __ashiftrt_r4_0
.global __ashiftrt_r4_1
.global __ashiftrt_r4_2
.global __ashiftrt_r4_3
.global __ashiftrt_r4_4
.global __ashiftrt_r4_5
.global __ashiftrt_r4_6
.global __ashiftrt_r4_7
.global __ashiftrt_r4_8
.global __ashiftrt_r4_9
.global __ashiftrt_r4_10
.global __ashiftrt_r4_11
.global __ashiftrt_r4_12
.global __ashiftrt_r4_13
.global __ashiftrt_r4_14
.global __ashiftrt_r4_15
.global __ashiftrt_r4_16
.global __ashiftrt_r4_17
.global __ashiftrt_r4_18
.global __ashiftrt_r4_19
.global __ashiftrt_r4_20
.global __ashiftrt_r4_21
.global __ashiftrt_r4_22
.global __ashiftrt_r4_23
.global __ashiftrt_r4_24
.global __ashiftrt_r4_25
.global __ashiftrt_r4_26
.global __ashiftrt_r4_27
.global __ashiftrt_r4_28
.global __ashiftrt_r4_29
.global __ashiftrt_r4_30
.global __ashiftrt_r4_31
.global __ashiftrt_r4_32
.align 1
__ashiftrt_r4_32:
__ashiftrt_r4_31:
rotcl r4
rts
subc r4,r4
__ashiftrt_r4_30:
shar r4
__ashiftrt_r4_29:
shar r4
__ashiftrt_r4_28:
shar r4
__ashiftrt_r4_27:
shar r4
__ashiftrt_r4_26:
shar r4
__ashiftrt_r4_25:
shar r4
__ashiftrt_r4_24:
shlr16 r4
shlr8 r4
rts
exts.b r4,r4
__ashiftrt_r4_23:
shar r4
__ashiftrt_r4_22:
shar r4
__ashiftrt_r4_21:
shar r4
__ashiftrt_r4_20:
shar r4
__ashiftrt_r4_19:
shar r4
__ashiftrt_r4_18:
shar r4
__ashiftrt_r4_17:
shar r4
__ashiftrt_r4_16:
shlr16 r4
rts
exts.w r4,r4
__ashiftrt_r4_15:
shar r4
__ashiftrt_r4_14:
shar r4
__ashiftrt_r4_13:
shar r4
__ashiftrt_r4_12:
shar r4
__ashiftrt_r4_11:
shar r4
__ashiftrt_r4_10:
shar r4
__ashiftrt_r4_9:
shar r4
__ashiftrt_r4_8:
shar r4
__ashiftrt_r4_7:
shar r4
__ashiftrt_r4_6:
shar r4
__ashiftrt_r4_5:
shar r4
__ashiftrt_r4_4:
shar r4
__ashiftrt_r4_3:
shar r4
__ashiftrt_r4_2:
shar r4
__ashiftrt_r4_1:
rts
shar r4
__ashiftrt_r4_0:
rts
nop
|
genetel200/u-boot
| 9,109
|
arch/sh/lib/udivsi3_i4i.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
/* This code used shld, thus is not suitable for SH1 / SH2. */
/* Signed / unsigned division without use of FPU, optimized for SH4.
Uses a lookup table for divisors in the range -128 .. +128, and
div1 with case distinction for larger divisors in three more ranges.
The code is lumped together with the table to allow the use of mova. */
#ifdef CONFIG_CPU_LITTLE_ENDIAN
#define L_LSB 0
#define L_LSWMSB 1
#define L_MSWLSB 2
#else
#define L_LSB 3
#define L_LSWMSB 2
#define L_MSWLSB 1
#endif
.balign 4
.global __udivsi3_i4i
.global __udivsi3_i4
.set __udivsi3_i4, __udivsi3_i4i
.type __udivsi3_i4i, @function
__udivsi3_i4i:
mov.w c128_w, r1
div0u
mov r4,r0
shlr8 r0
cmp/hi r1,r5
extu.w r5,r1
bf udiv_le128
cmp/eq r5,r1
bf udiv_ge64k
shlr r0
mov r5,r1
shll16 r5
mov.l r4,@-r15
div1 r5,r0
mov.l r1,@-r15
div1 r5,r0
div1 r5,r0
bra udiv_25
div1 r5,r0
div_le128:
mova div_table_ix,r0
bra div_le128_2
mov.b @(r0,r5),r1
udiv_le128:
mov.l r4,@-r15
mova div_table_ix,r0
mov.b @(r0,r5),r1
mov.l r5,@-r15
div_le128_2:
mova div_table_inv,r0
mov.l @(r0,r1),r1
mov r5,r0
tst #0xfe,r0
mova div_table_clz,r0
dmulu.l r1,r4
mov.b @(r0,r5),r1
bt/s div_by_1
mov r4,r0
mov.l @r15+,r5
sts mach,r0
/* clrt */
addc r4,r0
mov.l @r15+,r4
rotcr r0
rts
shld r1,r0
div_by_1_neg:
neg r4,r0
div_by_1:
mov.l @r15+,r5
rts
mov.l @r15+,r4
div_ge64k:
bt/s div_r8
div0u
shll8 r5
bra div_ge64k_2
div1 r5,r0
udiv_ge64k:
cmp/hi r0,r5
mov r5,r1
bt udiv_r8
shll8 r5
mov.l r4,@-r15
div1 r5,r0
mov.l r1,@-r15
div_ge64k_2:
div1 r5,r0
mov.l zero_l,r1
.rept 4
div1 r5,r0
.endr
mov.l r1,@-r15
div1 r5,r0
mov.w m256_w,r1
div1 r5,r0
mov.b r0,@(L_LSWMSB,r15)
xor r4,r0
and r1,r0
bra div_ge64k_end
xor r4,r0
div_r8:
shll16 r4
bra div_r8_2
shll8 r4
udiv_r8:
mov.l r4,@-r15
shll16 r4
clrt
shll8 r4
mov.l r5,@-r15
div_r8_2:
rotcl r4
mov r0,r1
div1 r5,r1
mov r4,r0
rotcl r0
mov r5,r4
div1 r5,r1
.rept 5
rotcl r0; div1 r5,r1
.endr
rotcl r0
mov.l @r15+,r5
div1 r4,r1
mov.l @r15+,r4
rts
rotcl r0
.global __sdivsi3_i4i
.global __sdivsi3_i4
.global __sdivsi3
.set __sdivsi3_i4, __sdivsi3_i4i
.set __sdivsi3, __sdivsi3_i4i
.type __sdivsi3_i4i, @function
/* This is link-compatible with a __sdivsi3 call,
but we effectively clobber only r1. */
__sdivsi3_i4i:
mov.l r4,@-r15
cmp/pz r5
mov.w c128_w, r1
bt/s pos_divisor
cmp/pz r4
mov.l r5,@-r15
neg r5,r5
bt/s neg_result
cmp/hi r1,r5
neg r4,r4
pos_result:
extu.w r5,r0
bf div_le128
cmp/eq r5,r0
mov r4,r0
shlr8 r0
bf/s div_ge64k
cmp/hi r0,r5
div0u
shll16 r5
div1 r5,r0
div1 r5,r0
div1 r5,r0
udiv_25:
mov.l zero_l,r1
div1 r5,r0
div1 r5,r0
mov.l r1,@-r15
.rept 3
div1 r5,r0
.endr
mov.b r0,@(L_MSWLSB,r15)
xtrct r4,r0
swap.w r0,r0
.rept 8
div1 r5,r0
.endr
mov.b r0,@(L_LSWMSB,r15)
div_ge64k_end:
.rept 8
div1 r5,r0
.endr
mov.l @r15+,r4 ! zero-extension and swap using LS unit.
extu.b r0,r0
mov.l @r15+,r5
or r4,r0
mov.l @r15+,r4
rts
rotcl r0
div_le128_neg:
tst #0xfe,r0
mova div_table_ix,r0
mov.b @(r0,r5),r1
mova div_table_inv,r0
bt/s div_by_1_neg
mov.l @(r0,r1),r1
mova div_table_clz,r0
dmulu.l r1,r4
mov.b @(r0,r5),r1
mov.l @r15+,r5
sts mach,r0
/* clrt */
addc r4,r0
mov.l @r15+,r4
rotcr r0
shld r1,r0
rts
neg r0,r0
pos_divisor:
mov.l r5,@-r15
bt/s pos_result
cmp/hi r1,r5
neg r4,r4
neg_result:
extu.w r5,r0
bf div_le128_neg
cmp/eq r5,r0
mov r4,r0
shlr8 r0
bf/s div_ge64k_neg
cmp/hi r0,r5
div0u
mov.l zero_l,r1
shll16 r5
div1 r5,r0
mov.l r1,@-r15
.rept 7
div1 r5,r0
.endr
mov.b r0,@(L_MSWLSB,r15)
xtrct r4,r0
swap.w r0,r0
.rept 8
div1 r5,r0
.endr
mov.b r0,@(L_LSWMSB,r15)
div_ge64k_neg_end:
.rept 8
div1 r5,r0
.endr
mov.l @r15+,r4 ! zero-extension and swap using LS unit.
extu.b r0,r1
mov.l @r15+,r5
or r4,r1
div_r8_neg_end:
mov.l @r15+,r4
rotcl r1
rts
neg r1,r0
div_ge64k_neg:
bt/s div_r8_neg
div0u
shll8 r5
mov.l zero_l,r1
.rept 6
div1 r5,r0
.endr
mov.l r1,@-r15
div1 r5,r0
mov.w m256_w,r1
div1 r5,r0
mov.b r0,@(L_LSWMSB,r15)
xor r4,r0
and r1,r0
bra div_ge64k_neg_end
xor r4,r0
c128_w:
.word 128
div_r8_neg:
clrt
shll16 r4
mov r4,r1
shll8 r1
mov r5,r4
.rept 7
rotcl r1; div1 r5,r0
.endr
mov.l @r15+,r5
rotcl r1
bra div_r8_neg_end
div1 r4,r0
m256_w:
.word 0xff00
/* This table has been generated by divtab-sh4.c. */
.balign 4
div_table_clz:
.byte 0
.byte 1
.byte 0
.byte -1
.byte -1
.byte -2
.byte -2
.byte -2
.byte -2
.byte -3
.byte -3
.byte -3
.byte -3
.byte -3
.byte -3
.byte -3
.byte -3
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
/* Lookup table translating positive divisor to index into table of
normalized inverse. N.B. the '0' entry is also the last entry of the
previous table, and causes an unaligned access for division by zero. */
div_table_ix:
.byte -6
.byte -128
.byte -128
.byte 0
.byte -128
.byte -64
.byte 0
.byte 64
.byte -128
.byte -96
.byte -64
.byte -32
.byte 0
.byte 32
.byte 64
.byte 96
.byte -128
.byte -112
.byte -96
.byte -80
.byte -64
.byte -48
.byte -32
.byte -16
.byte 0
.byte 16
.byte 32
.byte 48
.byte 64
.byte 80
.byte 96
.byte 112
.byte -128
.byte -120
.byte -112
.byte -104
.byte -96
.byte -88
.byte -80
.byte -72
.byte -64
.byte -56
.byte -48
.byte -40
.byte -32
.byte -24
.byte -16
.byte -8
.byte 0
.byte 8
.byte 16
.byte 24
.byte 32
.byte 40
.byte 48
.byte 56
.byte 64
.byte 72
.byte 80
.byte 88
.byte 96
.byte 104
.byte 112
.byte 120
.byte -128
.byte -124
.byte -120
.byte -116
.byte -112
.byte -108
.byte -104
.byte -100
.byte -96
.byte -92
.byte -88
.byte -84
.byte -80
.byte -76
.byte -72
.byte -68
.byte -64
.byte -60
.byte -56
.byte -52
.byte -48
.byte -44
.byte -40
.byte -36
.byte -32
.byte -28
.byte -24
.byte -20
.byte -16
.byte -12
.byte -8
.byte -4
.byte 0
.byte 4
.byte 8
.byte 12
.byte 16
.byte 20
.byte 24
.byte 28
.byte 32
.byte 36
.byte 40
.byte 44
.byte 48
.byte 52
.byte 56
.byte 60
.byte 64
.byte 68
.byte 72
.byte 76
.byte 80
.byte 84
.byte 88
.byte 92
.byte 96
.byte 100
.byte 104
.byte 108
.byte 112
.byte 116
.byte 120
.byte 124
.byte -128
/* 1/64 .. 1/127, normalized. There is an implicit leading 1 in bit 32. */
.balign 4
zero_l:
.long 0x0
.long 0xF81F81F9
.long 0xF07C1F08
.long 0xE9131AC0
.long 0xE1E1E1E2
.long 0xDAE6076C
.long 0xD41D41D5
.long 0xCD856891
.long 0xC71C71C8
.long 0xC0E07039
.long 0xBACF914D
.long 0xB4E81B4F
.long 0xAF286BCB
.long 0xA98EF607
.long 0xA41A41A5
.long 0x9EC8E952
.long 0x9999999A
.long 0x948B0FCE
.long 0x8F9C18FA
.long 0x8ACB90F7
.long 0x86186187
.long 0x81818182
.long 0x7D05F418
.long 0x78A4C818
.long 0x745D1746
.long 0x702E05C1
.long 0x6C16C16D
.long 0x68168169
.long 0x642C8591
.long 0x60581606
.long 0x5C9882BA
.long 0x58ED2309
div_table_inv:
.long 0x55555556
.long 0x51D07EAF
.long 0x4E5E0A73
.long 0x4AFD6A06
.long 0x47AE147B
.long 0x446F8657
.long 0x41414142
.long 0x3E22CBCF
.long 0x3B13B13C
.long 0x38138139
.long 0x3521CFB3
.long 0x323E34A3
.long 0x2F684BDB
.long 0x2C9FB4D9
.long 0x29E4129F
.long 0x27350B89
.long 0x24924925
.long 0x21FB7813
.long 0x1F7047DD
.long 0x1CF06ADB
.long 0x1A7B9612
.long 0x18118119
.long 0x15B1E5F8
.long 0x135C8114
.long 0x11111112
.long 0xECF56BF
.long 0xC9714FC
.long 0xA6810A7
.long 0x8421085
.long 0x624DD30
.long 0x4104105
.long 0x2040811
/* maximum error: 0.987342 scaled: 0.921875*/
|
genetel200/u-boot
| 1,089
|
arch/sh/lib/udiv_qrnnd.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
/* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */
/* n1 < d, but n1 might be larger than d1. */
.global __udiv_qrnnd_16
.balign 8
__udiv_qrnnd_16:
div0u
cmp/hi r6,r0
bt .Lots
.rept 16
div1 r6,r0
.endr
extu.w r0,r1
bt 0f
add r6,r0
0: rotcl r1
mulu.w r1,r5
xtrct r4,r0
swap.w r0,r0
sts macl,r2
cmp/hs r2,r0
sub r2,r0
bt 0f
addc r5,r0
add #-1,r1
bt 0f
1: add #-1,r1
rts
add r5,r0
.balign 8
.Lots:
sub r5,r0
swap.w r4,r1
xtrct r0,r1
clrt
mov r1,r0
addc r5,r0
mov #-1,r1
bf/s 1b
shlr16 r1
0: rts
nop
|
genetel200/u-boot
| 1,227
|
arch/riscv/lib/setjmp.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) 2018 Alexander Graf <agraf@suse.de>
*/
#include <config.h>
#include <linux/linkage.h>
#ifdef CONFIG_ARCH_RV64I
#define STORE_IDX(reg, idx) sd reg, (idx*8)(a0)
#define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0)
#else
#define STORE_IDX(reg, idx) sw reg, (idx*4)(a0)
#define LOAD_IDX(reg, idx) lw reg, (idx*4)(a0)
#endif
.pushsection .text.setjmp, "ax"
ENTRY(setjmp)
/* Preserve all callee-saved registers and the SP */
STORE_IDX(s0, 0)
STORE_IDX(s1, 1)
STORE_IDX(s2, 2)
STORE_IDX(s3, 3)
STORE_IDX(s4, 4)
STORE_IDX(s5, 5)
STORE_IDX(s6, 6)
STORE_IDX(s7, 7)
STORE_IDX(s8, 8)
STORE_IDX(s9, 9)
STORE_IDX(s10, 10)
STORE_IDX(s11, 11)
STORE_IDX(ra, 12)
STORE_IDX(sp, 13)
li a0, 0
ret
ENDPROC(setjmp)
.popsection
.pushsection .text.longjmp, "ax"
ENTRY(longjmp)
LOAD_IDX(s0, 0)
LOAD_IDX(s1, 1)
LOAD_IDX(s2, 2)
LOAD_IDX(s3, 3)
LOAD_IDX(s4, 4)
LOAD_IDX(s5, 5)
LOAD_IDX(s6, 6)
LOAD_IDX(s7, 7)
LOAD_IDX(s8, 8)
LOAD_IDX(s9, 9)
LOAD_IDX(s10, 10)
LOAD_IDX(s11, 11)
LOAD_IDX(ra, 12)
LOAD_IDX(sp, 13)
/* Move the return value in place, but return 1 if passed 0. */
beq a1, zero, longjmp_1
mv a0, a1
ret
longjmp_1:
li a0, 1
ret
ENDPROC(longjmp)
.popsection
|
genetel200/u-boot
| 4,246
|
arch/riscv/lib/crt0_riscv_efi.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* crt0-efi-riscv.S - PE/COFF header for RISC-V EFI applications
*
* Copright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
* Copright (C) 2018 Alexander Graf <agraf@suse.de>
*
* This file is inspired by arch/arm/lib/crt0_aarch64_efi.S
*/
#include <asm-generic/pe.h>
#if __riscv_xlen == 64
#define SIZE_LONG 8
#define SAVE_LONG(reg, idx) sd reg, (idx*SIZE_LONG)(sp)
#define LOAD_LONG(reg, idx) ld reg, (idx*SIZE_LONG)(sp)
#define PE_MACHINE 0x5064
#else
#define SIZE_LONG 4
#define SAVE_LONG(reg, idx) sw reg, (idx*SIZE_LONG)(sp)
#define LOAD_LONG(reg, idx) lw reg, (idx*SIZE_LONG)(sp)
#define PE_MACHINE 0x5032
#endif
.section .text.head
/*
* Magic "MZ" signature for PE/COFF
*/
.globl ImageBase
ImageBase:
.ascii "MZ"
.skip 58 /* 'MZ' + pad + offset == 64 */
.long pe_header - ImageBase /* Offset to the PE header */
pe_header:
.ascii "PE"
.short 0
coff_header:
.short PE_MACHINE /* RISC-V 64/32-bit */
.short 2 /* nr_sections */
.long 0 /* TimeDateStamp */
.long 0 /* PointerToSymbolTable */
.long 0 /* NumberOfSymbols */
.short section_table - optional_header /* SizeOfOptionalHeader */
/* Characteristics */
.short (IMAGE_FILE_EXECUTABLE_IMAGE | \
IMAGE_FILE_LINE_NUMS_STRIPPED | \
IMAGE_FILE_LOCAL_SYMS_STRIPPED | \
IMAGE_FILE_DEBUG_STRIPPED)
optional_header:
.short 0x20b /* PE32+ format */
.byte 0x02 /* MajorLinkerVersion */
.byte 0x14 /* MinorLinkerVersion */
.long _edata - _start /* SizeOfCode */
.long 0 /* SizeOfInitializedData */
.long 0 /* SizeOfUninitializedData */
.long _start - ImageBase /* AddressOfEntryPoint */
.long _start - ImageBase /* BaseOfCode */
extra_header_fields:
.quad 0 /* ImageBase */
.long 0x20 /* SectionAlignment */
.long 0x8 /* FileAlignment */
.short 0 /* MajorOperatingSystemVersion */
.short 0 /* MinorOperatingSystemVersion */
.short 0 /* MajorImageVersion */
.short 0 /* MinorImageVersion */
.short 0 /* MajorSubsystemVersion */
.short 0 /* MinorSubsystemVersion */
.long 0 /* Win32VersionValue */
.long _edata - ImageBase /* SizeOfImage */
/*
* Everything before the kernel image is considered part of the header
*/
.long _start - ImageBase /* SizeOfHeaders */
.long 0 /* CheckSum */
.short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */
.short 0 /* DllCharacteristics */
.quad 0 /* SizeOfStackReserve */
.quad 0 /* SizeOfStackCommit */
.quad 0 /* SizeOfHeapReserve */
.quad 0 /* SizeOfHeapCommit */
.long 0 /* LoaderFlags */
.long 0x6 /* NumberOfRvaAndSizes */
.quad 0 /* ExportTable */
.quad 0 /* ImportTable */
.quad 0 /* ResourceTable */
.quad 0 /* ExceptionTable */
.quad 0 /* CertificationTable */
.quad 0 /* BaseRelocationTable */
/* Section table */
section_table:
/*
* The EFI application loader requires a relocation section
* because EFI applications must be relocatable. This is a
* dummy section as far as we are concerned.
*/
.ascii ".reloc"
.byte 0
.byte 0 /* end of 0 padding of section name */
.long 0
.long 0
.long 0 /* SizeOfRawData */
.long 0 /* PointerToRawData */
.long 0 /* PointerToRelocations */
.long 0 /* PointerToLineNumbers */
.short 0 /* NumberOfRelocations */
.short 0 /* NumberOfLineNumbers */
.long 0x42100040 /* Characteristics (section flags) */
.ascii ".text"
.byte 0
.byte 0
.byte 0 /* end of 0 padding of section name */
.long _edata - _start /* VirtualSize */
.long _start - ImageBase /* VirtualAddress */
.long _edata - _start /* SizeOfRawData */
.long _start - ImageBase /* PointerToRawData */
.long 0 /* PointerToRelocations (0 for executables) */
.long 0 /* PointerToLineNumbers (0 for executables) */
.short 0 /* NumberOfRelocations (0 for executables) */
.short 0 /* NumberOfLineNumbers (0 for executables) */
.long 0xe0500020 /* Characteristics (section flags) */
_start:
addi sp, sp, -(SIZE_LONG * 3)
SAVE_LONG(a0, 0)
SAVE_LONG(a1, 1)
SAVE_LONG(ra, 2)
lla a0, ImageBase
lla a1, _DYNAMIC
call _relocate
bne a0, zero, 0f
LOAD_LONG(a1, 1)
LOAD_LONG(a0, 0)
call efi_main
LOAD_LONG(ra, 2)
0: addi sp, sp, (SIZE_LONG * 3)
ret
|
genetel200/u-boot
| 2,624
|
arch/riscv/cpu/mtrap.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* M-mode Trap Handler Code for RISC-V Core
*
* Copyright (c) 2017 Microsemi Corporation.
* Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
*
* Copyright (C) 2017 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
#include <common.h>
#include <asm/encoding.h>
#ifdef CONFIG_32BIT
#define LREG lw
#define SREG sw
#define REGBYTES 4
#else
#define LREG ld
#define SREG sd
#define REGBYTES 8
#endif
.text
/* trap entry */
.align 2
.global trap_entry
trap_entry:
addi sp, sp, -32 * REGBYTES
SREG x1, 1 * REGBYTES(sp)
SREG x2, 2 * REGBYTES(sp)
SREG x3, 3 * REGBYTES(sp)
SREG x4, 4 * REGBYTES(sp)
SREG x5, 5 * REGBYTES(sp)
SREG x6, 6 * REGBYTES(sp)
SREG x7, 7 * REGBYTES(sp)
SREG x8, 8 * REGBYTES(sp)
SREG x9, 9 * REGBYTES(sp)
SREG x10, 10 * REGBYTES(sp)
SREG x11, 11 * REGBYTES(sp)
SREG x12, 12 * REGBYTES(sp)
SREG x13, 13 * REGBYTES(sp)
SREG x14, 14 * REGBYTES(sp)
SREG x15, 15 * REGBYTES(sp)
SREG x16, 16 * REGBYTES(sp)
SREG x17, 17 * REGBYTES(sp)
SREG x18, 18 * REGBYTES(sp)
SREG x19, 19 * REGBYTES(sp)
SREG x20, 20 * REGBYTES(sp)
SREG x21, 21 * REGBYTES(sp)
SREG x22, 22 * REGBYTES(sp)
SREG x23, 23 * REGBYTES(sp)
SREG x24, 24 * REGBYTES(sp)
SREG x25, 25 * REGBYTES(sp)
SREG x26, 26 * REGBYTES(sp)
SREG x27, 27 * REGBYTES(sp)
SREG x28, 28 * REGBYTES(sp)
SREG x29, 29 * REGBYTES(sp)
SREG x30, 30 * REGBYTES(sp)
SREG x31, 31 * REGBYTES(sp)
csrr a0, MODE_PREFIX(cause)
csrr a1, MODE_PREFIX(epc)
mv a2, sp
jal handle_trap
csrw MODE_PREFIX(epc), a0
LREG x1, 1 * REGBYTES(sp)
LREG x3, 3 * REGBYTES(sp)
LREG x4, 4 * REGBYTES(sp)
LREG x5, 5 * REGBYTES(sp)
LREG x6, 6 * REGBYTES(sp)
LREG x7, 7 * REGBYTES(sp)
LREG x8, 8 * REGBYTES(sp)
LREG x9, 9 * REGBYTES(sp)
LREG x10, 10 * REGBYTES(sp)
LREG x11, 11 * REGBYTES(sp)
LREG x12, 12 * REGBYTES(sp)
LREG x13, 13 * REGBYTES(sp)
LREG x14, 14 * REGBYTES(sp)
LREG x15, 15 * REGBYTES(sp)
LREG x16, 16 * REGBYTES(sp)
LREG x17, 17 * REGBYTES(sp)
LREG x18, 18 * REGBYTES(sp)
LREG x19, 19 * REGBYTES(sp)
LREG x20, 20 * REGBYTES(sp)
LREG x21, 21 * REGBYTES(sp)
LREG x22, 22 * REGBYTES(sp)
LREG x23, 23 * REGBYTES(sp)
LREG x24, 24 * REGBYTES(sp)
LREG x25, 25 * REGBYTES(sp)
LREG x26, 26 * REGBYTES(sp)
LREG x27, 27 * REGBYTES(sp)
LREG x28, 28 * REGBYTES(sp)
LREG x29, 29 * REGBYTES(sp)
LREG x30, 30 * REGBYTES(sp)
LREG x31, 31 * REGBYTES(sp)
LREG x2, 2 * REGBYTES(sp)
addi sp, sp, 32 * REGBYTES
MODE_PREFIX(ret)
|
genetel200/u-boot
| 4,524
|
arch/riscv/cpu/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Startup Code for RISC-V Core
*
* Copyright (c) 2017 Microsemi Corporation.
* Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
*
* Copyright (C) 2017 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
#include <elf.h>
#include <asm/encoding.h>
#include <generated/asm-offsets.h>
#ifdef CONFIG_32BIT
#define LREG lw
#define SREG sw
#define REGBYTES 4
#define RELOC_TYPE R_RISCV_32
#define SYM_INDEX 0x8
#define SYM_SIZE 0x10
#else
#define LREG ld
#define SREG sd
#define REGBYTES 8
#define RELOC_TYPE R_RISCV_64
#define SYM_INDEX 0x20
#define SYM_SIZE 0x18
#endif
.section .text
.globl _start
_start:
/* save hart id and dtb pointer */
mv s0, a0
mv s1, a1
la t0, trap_entry
csrw MODE_PREFIX(tvec), t0
/* mask all interrupts */
csrw MODE_PREFIX(ie), zero
/* Enable cache */
jal icache_enable
jal dcache_enable
/*
* Set stackpointer in internal/ex RAM to call board_init_f
*/
call_board_init_f:
li t0, -16
li t1, CONFIG_SYS_INIT_SP_ADDR
and sp, t1, t0 /* force 16 byte alignment */
#ifdef CONFIG_DEBUG_UART
jal debug_uart_init
#endif
call_board_init_f_0:
mv a0, sp
jal board_init_f_alloc_reserve
mv sp, a0
la t0, prior_stage_fdt_address
SREG s1, 0(t0)
jal board_init_f_init_reserve
/* save the boot hart id to global_data */
SREG s0, GD_BOOT_HART(gp)
mv a0, zero /* a0 <-- boot_flags = 0 */
la t5, board_init_f
jr t5 /* jump to board_init_f() */
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
*/
.globl relocate_code
relocate_code:
mv s2, a0 /* save addr_sp */
mv s3, a1 /* save addr of gd */
mv s4, a2 /* save addr of destination */
/*
*Set up the stack
*/
stack_setup:
mv sp, s2
la t0, _start
sub t6, s4, t0 /* t6 <- relocation offset */
beq t0, s4, clear_bss /* skip relocation */
mv t1, s4 /* t1 <- scratch for copy_loop */
la t3, __bss_start
sub t3, t3, t0 /* t3 <- __bss_start_ofs */
add t2, t0, t3 /* t2 <- source end address */
copy_loop:
LREG t5, 0(t0)
addi t0, t0, REGBYTES
SREG t5, 0(t1)
addi t1, t1, REGBYTES
blt t0, t2, copy_loop
/*
* Update dynamic relocations after board_init_f
*/
fix_rela_dyn:
la t1, __rel_dyn_start
la t2, __rel_dyn_end
beq t1, t2, clear_bss
add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
/*
* skip first reserved entry: address, type, addend
*/
bne t1, t2, 7f
6:
LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
LREG t3, -(REGBYTES*3)(t1)
LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
add t5, t5, t6 /* t5 <-- location to fix up in RAM */
add t3, t3, t6 /* t3 <-- location to fix up in RAM */
SREG t5, 0(t3)
7:
addi t1, t1, (REGBYTES*3)
ble t1, t2, 6b
8:
la t4, __dyn_sym_start
add t4, t4, t6
9:
LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
andi t5, t5, 0xFF /* t5 <--- relocation type */
li t3, RELOC_TYPE
bne t5, t3, 10f /* skip non-addned entries */
LREG t3, -(REGBYTES*3)(t1)
li t5, SYM_SIZE
mul t0, t0, t5
add s5, t4, t0
LREG t5, REGBYTES(s5)
add t5, t5, t6 /* t5 <-- location to fix up in RAM */
add t3, t3, t6 /* t3 <-- location to fix up in RAM */
SREG t5, 0(t3)
10:
addi t1, t1, (REGBYTES*3)
ble t1, t2, 9b
/*
* trap update
*/
la t0, trap_entry
add t0, t0, t6
csrw MODE_PREFIX(tvec), t0
clear_bss:
la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
beq t0, t1, call_board_init_r
clbss_l:
SREG zero, 0(t0) /* clear loop... */
addi t0, t0, REGBYTES
bne t0, t1, clbss_l
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
call_board_init_r:
jal invalidate_icache_all
jal flush_dcache_all
la t0, board_init_r
mv t4, t0 /* offset of board_init_r() */
add t4, t4, t6 /* real address of board_init_r() */
/*
* setup parameters for board_init_r
*/
mv a0, s3 /* gd_t */
mv a1, s4 /* dest_addr */
/*
* jump to it ...
*/
jr t4 /* jump to board_init_r() */
|
genetel200/u-boot
| 1,201
|
arch/powerpc/lib/_ashrdi3.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* This code was copied from arch/powerpc/kernel/misc_32.S in the Linux
* kernel sources (commit 85e2efbb1db9a18d218006706d6e4fbeb0216213, also
* known as 2.6.38-rc5). The source file copyrights are as follows:
*
* (C) Copyright 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
* and Paul Mackerras.
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <config.h>
/*
* Extended precision shifts.
*
* Updated to be valid for shift counts from 0 to 63 inclusive.
* -- Gabriel
*
* R3/R4 has 64 bit value
* R5 has shift count
* result in R3/R4
*
* ashrdi3: arithmetic right shift (sign propagation)
* lshrdi3: logical right shift
* ashldi3: left shift
*/
.globl __ashrdi3
__ashrdi3:
subfic r6,r5,32
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
addi r7,r5,32 # could be xori, or addi with -32
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
sraw r7,r3,r7 # t2 = MSW >> (count-32)
or r4,r4,r6 # LSW |= t1
slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
sraw r3,r3,r5 # MSW = MSW >> count
or r4,r4,r7 # LSW |= t2
blr
|
genetel200/u-boot
| 1,125
|
arch/powerpc/lib/_lshrdi3.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* This code was copied from arch/powerpc/kernel/misc_32.S in the Linux
* kernel sources (commit 85e2efbb1db9a18d218006706d6e4fbeb0216213, also
* known as 2.6.38-rc5). The source file copyrights are as follows:
*
* (C) Copyright 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
* and Paul Mackerras.
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <config.h>
/*
* Extended precision shifts.
*
* Updated to be valid for shift counts from 0 to 63 inclusive.
* -- Gabriel
*
* R3/R4 has 64 bit value
* R5 has shift count
* result in R3/R4
*
* ashrdi3: arithmetic right shift (sign propagation)
* lshrdi3: logical right shift
* ashldi3: left shift
*/
.globl __lshrdi3
__lshrdi3:
subfic r6,r5,32
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
addi r7,r5,32 # could be xori, or addi with -32
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
or r4,r4,r6 # LSW |= t1
srw r3,r3,r5 # MSW = MSW >> count
or r4,r4,r7 # LSW |= t2
blr
|
genetel200/u-boot
| 2,781
|
arch/powerpc/lib/ppccache.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
* Copyright Freescale Semiconductor, Inc. 2004, 2006.
*/
#include <config.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbf */
/* Description: Data Cache block flush */
/* Input: r3 = effective address */
/* Output: none. */
/*------------------------------------------------------------------------------- */
.globl ppcDcbf
ppcDcbf:
dcbf r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbi */
/* Description: Data Cache block Invalidate */
/* Input: r3 = effective address */
/* Output: none. */
/*------------------------------------------------------------------------------- */
.globl ppcDcbi
ppcDcbi:
dcbi r0,r3
blr
/*--------------------------------------------------------------------------
* Function: ppcDcbz
* Description: Data Cache block zero.
* Input: r3 = effective address
* Output: none.
*-------------------------------------------------------------------------- */
.globl ppcDcbz
ppcDcbz:
dcbz r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: ppcSync */
/* Description: Processor Synchronize */
/* Input: none. */
/* Output: none. */
/*------------------------------------------------------------------------------- */
.globl ppcSync
ppcSync:
sync
blr
/*
* Write any modified data cache blocks out to memory and invalidate them.
* Does not invalidate the corresponding instruction cache blocks.
*
* flush_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_dcache_range)
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
1: dcbf 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbst's to get to ram */
#endif
blr
/*
* Like above, but invalidate the D-cache. This is used by the 8xx
* to invalidate the cache so the PPC core doesn't get stale data
* from the CPM (no cache snooping here :-).
*
* invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(invalidate_dcache_range)
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
sync
1: dcbi 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbi's to get to ram */
#endif
blr
|
genetel200/u-boot
| 2,758
|
arch/powerpc/lib/ppcstring.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* String handling functions for PowerPC.
*
* Copyright (C) 1996 Paul Mackerras.
*/
#include <ppc_asm.tmpl>
#include <linux/errno.h>
.globl strcpy
strcpy:
addi r5,r3,-1
addi r4,r4,-1
1: lbzu r0,1(r4)
cmpwi 0,r0,0
stbu r0,1(r5)
bne 1b
blr
.globl strncpy
strncpy:
cmpwi 0,r5,0
beqlr
mtctr r5
addi r6,r3,-1
addi r4,r4,-1
1: lbzu r0,1(r4)
cmpwi 0,r0,0
stbu r0,1(r6)
bdnzf 2,1b /* dec ctr, branch if ctr != 0 && !cr0.eq */
blr
.globl strcat
strcat:
addi r5,r3,-1
addi r4,r4,-1
1: lbzu r0,1(r5)
cmpwi 0,r0,0
bne 1b
addi r5,r5,-1
1: lbzu r0,1(r4)
cmpwi 0,r0,0
stbu r0,1(r5)
bne 1b
blr
.globl strcmp
strcmp:
addi r5,r3,-1
addi r4,r4,-1
1: lbzu r3,1(r5)
cmpwi 1,r3,0
lbzu r0,1(r4)
subf. r3,r0,r3
beqlr 1
beq 1b
blr
.globl strlen
strlen:
addi r4,r3,-1
1: lbzu r0,1(r4)
cmpwi 0,r0,0
bne 1b
subf r3,r3,r4
blr
.globl memset
memset:
rlwimi r4,r4,8,16,23
rlwimi r4,r4,16,0,15
addi r6,r3,-4
cmplwi 0,r5,4
blt 7f
stwu r4,4(r6)
beqlr
andi. r0,r6,3
add r5,r0,r5
subf r6,r0,r6
rlwinm r0,r5,32-2,2,31
mtctr r0
bdz 6f
1: stwu r4,4(r6)
bdnz 1b
6: andi. r5,r5,3
7: cmpwi 0,r5,0
beqlr
mtctr r5
addi r6,r6,3
8: stbu r4,1(r6)
bdnz 8b
blr
.globl memmove
memmove:
cmplw 0,r3,r4
bgt backwards_memcpy
/* fall through */
.globl memcpy
memcpy:
rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */
addi r6,r3,-4
addi r4,r4,-4
beq 2f /* if less than 8 bytes to do */
andi. r0,r6,3 /* get dest word aligned */
mtctr r7
bne 5f
1: lwz r7,4(r4)
lwzu r8,8(r4)
stw r7,4(r6)
stwu r8,8(r6)
bdnz 1b
andi. r5,r5,7
2: cmplwi 0,r5,4
blt 3f
lwzu r0,4(r4)
addi r5,r5,-4
stwu r0,4(r6)
3: cmpwi 0,r5,0
beqlr
mtctr r5
addi r4,r4,3
addi r6,r6,3
4: lbzu r0,1(r4)
stbu r0,1(r6)
bdnz 4b
blr
5: subfic r0,r0,4
mtctr r0
6: lbz r7,4(r4)
addi r4,r4,1
stb r7,4(r6)
addi r6,r6,1
bdnz 6b
subf r5,r0,r5
rlwinm. r7,r5,32-3,3,31
beq 2b
mtctr r7
b 1b
.globl backwards_memcpy
backwards_memcpy:
rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */
add r6,r3,r5
add r4,r4,r5
beq 2f
andi. r0,r6,3
mtctr r7
bne 5f
1: lwz r7,-4(r4)
lwzu r8,-8(r4)
stw r7,-4(r6)
stwu r8,-8(r6)
bdnz 1b
andi. r5,r5,7
2: cmplwi 0,r5,4
blt 3f
lwzu r0,-4(r4)
subi r5,r5,4
stwu r0,-4(r6)
3: cmpwi 0,r5,0
beqlr
mtctr r5
4: lbzu r0,-1(r4)
stbu r0,-1(r6)
bdnz 4b
blr
5: mtctr r0
6: lbzu r7,-1(r4)
stbu r7,-1(r6)
bdnz 6b
subf r5,r0,r5
rlwinm. r7,r5,32-3,3,31
beq 2b
mtctr r7
b 1b
.globl memcmp
memcmp:
cmpwi 0,r5,0
ble- 2f
mtctr r5
addi r6,r3,-1
addi r4,r4,-1
1: lbzu r3,1(r6)
lbzu r0,1(r4)
subf. r3,r0,r3
bdnzt 2,1b
blr
2: li r3,0
blr
.global memchr
memchr:
cmpwi 0,r5,0
ble- 2f
mtctr r5
addi r3,r3,-1
1: lbzu r0,1(r3)
cmpw 0,r0,r4
bdnzf 2,1b
beqlr
2: li r3,0
blr
|
genetel200/u-boot
| 1,125
|
arch/powerpc/lib/_ashldi3.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* This code was copied from arch/powerpc/kernel/misc_32.S in the Linux
* kernel sources (commit 85e2efbb1db9a18d218006706d6e4fbeb0216213, also
* known as 2.6.38-rc5). The source file copyrights are as follows:
*
* (C) Copyright 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
* and Paul Mackerras.
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <config.h>
/*
* Extended precision shifts.
*
* Updated to be valid for shift counts from 0 to 63 inclusive.
* -- Gabriel
*
* R3/R4 has 64 bit value
* R5 has shift count
* result in R3/R4
*
* ashrdi3: arithmetic right shift (sign propagation)
* lshrdi3: logical right shift
* ashldi3: left shift
*/
.globl __ashldi3
__ashldi3:
subfic r6,r5,32
slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
addi r7,r5,32 # could be xori, or addi with -32
srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
or r3,r3,r6 # MSW |= t1
slw r4,r4,r5 # LSW = LSW << count
or r3,r3,r7 # MSW |= t2
blr
|
genetel200/u-boot
| 1,225
|
arch/powerpc/lib/ticks.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2000, 2001
* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
* base on code by
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <config.h>
#include <watchdog.h>
/*
* unsigned long long get_ticks(void);
*
* read timebase as "long long"
*/
.globl get_ticks
get_ticks:
1: mftbu r3
mftb r4
mftbu r5
cmp 0,r3,r5
bne 1b
blr
/*
* Delay for a number of ticks
*/
.globl wait_ticks
wait_ticks:
stwu r1, -16(r1)
mflr r0 /* save link register */
stw r0, 20(r1) /* Use r0 or GDB will be unhappy */
stw r14, 12(r1) /* save used registers */
stw r15, 8(r1)
mr r14, r3 /* save tick count */
bl get_ticks /* Get start time */
/* Calculate end time */
addc r14, r4, r14 /* Compute end time lower */
addze r15, r3 /* and end time upper */
WATCHDOG_RESET /* Trigger watchdog, if needed */
1: bl get_ticks /* Get current time */
subfc r4, r4, r14 /* Subtract current time from end time */
subfe. r3, r3, r15
bge 1b /* Loop until time expired */
lwz r15, 8(r1) /* restore saved registers */
lwz r14, 12(r1)
lwz r0, 20(r1)
addi r1,r1,16
mtlr r0
blr
|
genetel200/u-boot
| 12,759
|
arch/powerpc/cpu/mpc8xx/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
*/
/* U-Boot - Startup Code for PowerPC based Embedded Boards
*
*
* The processor starts at 0x00000100 and the code is executed
* from flash. The code is organized to be at an other address
* in memory, but as long we don't jump around before relocating,
* board_init lies at a quite high address and when the cpu has
* jumped there, everything is ok.
* This works because the cpu gives the FLASH (CS0) the whole
* address space at startup, and board_init lies as a echo of
* the flash somewhere up there in the memory map.
*
* board_init will change CS0 to be positioned at the correct
* address and (s)dram will be positioned at address 0
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc8xx.h>
#include <version.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/u-boot.h>
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
/*
* Set up GOT: Global Offset Table
*
* Use r12 to access the GOT
*/
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
/*
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
.ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
_start:
lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
mtspr 638, r3
/* Initialize machine status; enable machine check interrupt */
/*----------------------------------------------------------------------*/
li r3, MSR_KERNEL /* Set ME, RI flags */
mtmsr r3
mtspr SRR1, r3 /* Make SRR1 match MSR */
mfspr r3, ICR /* clear Interrupt Cause Register */
/* Initialize debug port registers */
/*----------------------------------------------------------------------*/
xor r0, r0, r0 /* Clear R0 */
mtspr LCTRL1, r0 /* Initialize debug port regs */
mtspr LCTRL2, r0
mtspr COUNTA, r0
mtspr COUNTB, r0
/* Reset the caches */
/*----------------------------------------------------------------------*/
mfspr r3, IC_CST /* Clear error bits */
mfspr r3, DC_CST
lis r3, IDC_UNALL@h /* Unlock all */
mtspr IC_CST, r3
mtspr DC_CST, r3
lis r3, IDC_INVALL@h /* Invalidate all */
mtspr IC_CST, r3
mtspr DC_CST, r3
lis r3, IDC_DISABLE@h /* Disable data cache */
mtspr DC_CST, r3
lis r3, IDC_ENABLE@h /* Enable instruction cache */
mtspr IC_CST, r3
/* invalidate all tlb's */
/*----------------------------------------------------------------------*/
tlbia
isync
/*
* Calculate absolute address in FLASH and jump there
*----------------------------------------------------------------------*/
lis r3, CONFIG_SYS_MONITOR_BASE@h
ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
in_flash:
/* initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
/*
* Disable serialized ifetch and show cycles
* (i.e. set processor to normal mode).
* This is also a silicon bug workaround, see errata
*/
li r2, 0x0007
mtspr ICTRL, r2
/* Set up debug mode entry */
lis r2, CONFIG_SYS_DER@h
ori r2, r2, CONFIG_SYS_DER@l
mtspr DER, r2
/* set up the stack on top of internal DPRAM */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
stw r0, -4(r3)
stw r0, -8(r3)
addi r1, r3, -8
bl board_init_f_alloc_reserve
addi r1, r3, -8
/* Zeroise the CPM dpram */
lis r4, CONFIG_SYS_IMMR@h
ori r4, r4, (0x2000 - 4)
li r0, (0x2000 / 4)
mtctr r0
li r0, 0
1: stwu r0, 4(r4)
bdnz 1b
bl board_init_f_init_reserve
/* let the C-code set up the rest */
/* */
/* Be careful to keep code relocatable ! */
/*----------------------------------------------------------------------*/
GET_GOT /* initialize GOT access */
lis r3, CONFIG_SYS_IMMR@h
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f /* run 1st part of board init code (from Flash) */
/* NOTREACHED - board_init_f() does not return */
.globl _start_of_vectors
_start_of_vectors:
/* Machine check */
STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. "Never" generated on the 860. */
STD_EXCEPTION(0x300, DataStorage, UnknownException)
/* Instruction Storage exception. "Never" generated on the 860. */
STD_EXCEPTION(0x400, InstStorage, UnknownException)
/* External Interrupt exception. */
STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
MSR_KERNEL, COPY_EE)
/* No FPU on MPC8xx. This exception is not supposed to happen.
*/
STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
/* I guess we could implement decrementer, and may have
* to someday for timekeeping.
*/
STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
STD_EXCEPTION(0xc00, SystemCall, UnknownException)
STD_EXCEPTION(0xd00, SingleStep, UnknownException)
STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
/* On the MPC8xx, this is a software emulation interrupt. It occurs
* for all unimplemented and illegal instructions.
*/
STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
STD_EXCEPTION(0x1500, Reserved5, UnknownException)
STD_EXCEPTION(0x1600, Reserved6, UnknownException)
STD_EXCEPTION(0x1700, Reserved7, UnknownException)
STD_EXCEPTION(0x1800, Reserved8, UnknownException)
STD_EXCEPTION(0x1900, Reserved9, UnknownException)
STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
.globl _end_of_vectors
_end_of_vectors:
. = 0x2000
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
* Register r21 is pointer into trap frame, r1 has new stack pointer.
*/
.globl transfer_to_handler
transfer_to_handler:
stw r22,_NIP(r21)
lis r22,MSR_POW@h
andc r23,r23,r22
stw r23,_MSR(r21)
SAVE_GPR(7, r21)
SAVE_4GPRS(8, r21)
SAVE_8GPRS(12, r21)
SAVE_8GPRS(24, r21)
mflr r23
andi. r24,r23,0x3f00 /* get vector offset */
stw r24,TRAP(r21)
li r22,0
stw r22,RESULT(r21)
mtspr SPRG2,r22 /* r1 is now kernel sp */
lwz r24,0(r23) /* virtual address of handler */
lwz r23,4(r23) /* where to go when done */
mtspr SRR0,r24
mtspr SRR1,r20
mtlr r23
SYNC
rfi /* jump to handler, enable MMU */
int_return:
mfmsr r28 /* Disable interrupts */
li r4,0
ori r4,r4,MSR_EE
andc r28,r28,r4
SYNC /* Some chip revs need this... */
mtmsr r28
SYNC
lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
lwz r2,_XER(r1)
lwz r0,_CCR(r1)
mtspr XER,r2
mtcrf 0xFF,r0
REST_10GPRS(3, r1)
REST_10GPRS(13, r1)
REST_8GPRS(23, r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr SRR0,r2
mtspr SRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfi
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Global Data pointer */
mr r10, r5 /* Save copy of Destination Address */
GET_GOT
mr r3, r5 /* Destination Address */
lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
sub r15, r10, r4
/* First our own GOT */
add r12, r12, r15
/* then the one used by the C code */
add r30, r30, r15
/*
* Now relocate code
*/
cmplw cr1,r3,r4
addi r0,r5,3
srwi. r0,r0,2
beq cr1,4f /* In place copy is not necessary */
beq 7f /* Protect against 0 count */
mtctr r0
bge cr1,2f
la r8,-4(r4)
la r7,-4(r3)
1: lwzu r0,4(r8)
stwu r0,4(r7)
bdnz 1b
b 4f
2: slwi r0,r0,2
add r8,r4,r0
add r7,r3,r0
3: lwzu r0,-4(r8)
stwu r0,-4(r7)
bdnz 3b
/*
* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
*/
4: cmpwi r6,0
add r5,r3,r5
beq 7f /* Always flush prefetch queue in any case */
subi r0,r6,1
andc r3,r3,r0
mr r4,r3
5: dcbst 0,r4
add r4,r4,r6
cmplw r4,r5
blt 5b
sync /* Wait for all dcbst to complete on bus */
mr r4,r3
6: icbi 0,r4
add r4,r4,r6
cmplw r4,r5
blt 6b
7: sync /* Wait for all icbi to complete on bus */
isync
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
mtlr r0
blr
in_ram:
/*
* Relocation Function, r12 point to got2+0x8000
*
* Adjust got2 pointers, no need to check for 0, this code
* already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
lwz r11,GOT(_GOT2_TABLE_)
mtctr r0
sub r11,r3,r11
addi r3,r3,-4
1: lwzu r0,4(r3)
cmpwi r0,0
beq- 2f
add r0,r0,r11
stw r0,0(r3)
2: bdnz 1b
/*
* Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
li r0,__fixup_entries@sectoff@l
lwz r3,GOT(_FIXUP_TABLE_)
cmpwi r0,0
mtctr r0
addi r3,r3,-4
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
cmpwi r0,0
add r0,r0,r11
stw r4,0(r3)
beq- 5f
stw r0,0(r4)
5: bdnz 3b
4:
clear_bss:
/*
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
li r0, 0
5:
stw r0, 0(r3)
addi r3, r3, 4
cmplw 0, r3, r4
bne 5b
6:
mr r3, r9 /* Global Data pointer */
mr r4, r10 /* Destination Address */
bl board_init_r
/*
* Copy exception vector code to low memory
*
* r3: dest_addr
* r7: source address, r8: end address, r9: target address
*/
.globl trap_init
trap_init:
mflr r4 /* save link register */
GET_GOT
lwz r7, GOT(_start)
lwz r8, GOT(_end_of_vectors)
li r9, 0x100 /* reset vector always at 0x100 */
cmplw 0, r7, r8
bgelr /* return if r7>=r8 - just in case */
1:
lwz r0, 0(r7)
stw r0, 0(r9)
addi r7, r7, 4
addi r9, r9, 4
cmplw 0, r7, r8
bne 1b
/*
* relocate `hdlr' and `int_return' entries
*/
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
li r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 2b
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 3b
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 4b
mtlr r4 /* restore link register */
blr
|
genetel200/u-boot
| 30,189
|
arch/powerpc/cpu/mpc83xx/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
* Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
*/
/*
* U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc83xx.h>
#include <version.h>
#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/u-boot.h>
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
/*
* Floating Point enable, Machine Check and Recoverable Interr.
*/
#ifdef DEBUG
#define MSR_KERNEL (MSR_FP|MSR_RI)
#else
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif
#if defined(CONFIG_NAND_SPL) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
#define MINIMAL_SPL
#endif
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
!defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_FLASHBOOT
#endif
/*
* Set up GOT: Global Offset Table
*
* Use r12 to access the GOT
*/
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(__bss_start)
GOT_ENTRY(__bss_end)
#ifndef MINIMAL_SPL
GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
#endif
END_GOT
/*
* The Hard Reset Configuration Word (HRCW) table is in the first 64
* (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
* times so the processor can fetch it out of flash whether the flash
* is 8, 16, 32, or 64 bits wide (hardware trickery).
*/
.text
#define _HRCW_TABLE_ENTRY(w) \
.fill 8,1,(((w)>>24)&0xff); \
.fill 8,1,(((w)>>16)&0xff); \
.fill 8,1,(((w)>> 8)&0xff); \
.fill 8,1,(((w) )&0xff)
_HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
_HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
/*
* Magic number and version string - put it after the HRCW since it
* cannot be first in flash like it is in many other processors.
*/
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
.ascii U_BOOT_VERSION_STRING, "\0"
.align 2
.globl enable_addr_trans
enable_addr_trans:
/* enable address translation */
mfmsr r5
ori r5, r5, (MSR_IR | MSR_DR)
mtmsr r5
isync
blr
.globl disable_addr_trans
disable_addr_trans:
/* disable address translation */
mflr r4
mfmsr r3
andi. r0, r3, (MSR_IR | MSR_DR)
beqlr
andc r3, r3, r0
mtspr SRR0, r4
mtspr SRR1, r3
rfi
.globl ppcDWstore
ppcDWstore:
lfd 1, 0(r4)
stfd 1, 0(r3)
blr
.globl ppcDWload
ppcDWload:
lfd 1, 0(r3)
stfd 1, 0(r4)
blr
#ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined
#endif /* CONFIG_DEFAULT_IMMR */
#ifndef CONFIG_SYS_IMMR
#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
#endif /* CONFIG_SYS_IMMR */
/*
* After configuration, a system reset exception is executed using the
* vector at offset 0x100 relative to the base set by MSR[IP]. If
* MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
* base address is 0xfff00000. In the case of a Power On Reset or Hard
* Reset, the value of MSR[IP] is determined by the CIP field in the
* HRCW.
*
* Other bits in the HRCW set up the Base Address and Port Size in BR0.
* This determines the location of the boot ROM (flash or EPROM) in the
* processor's address space at boot time. As long as the HRCW is set up
* so that we eventually end up executing the code below when the
* processor executes the reset exception, the actual values used should
* not matter.
*
* Once we have got here, the address mask in OR0 is cleared so that the
* bottom 32K of the boot ROM is effectively repeated all throughout the
* processor's address space, after which we can jump to the absolute
* address at which the boot ROM was linked at compile time, and proceed
* to initialise the memory controller without worrying if the rug will
* be pulled out from under us, so to speak (it will be fine as long as
* we configure BR0 with the same boot ROM link address).
*/
. = EXC_OFF_SYS_RESET
.globl _start
_start: /* time t 0 */
lis r4, CONFIG_DEFAULT_IMMR@h
nop
mfmsr r5 /* save msr contents */
/* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
bl 1f
1: mflr r7
lis r3, CONFIG_SYS_IMMR@h
ori r3, r3, CONFIG_SYS_IMMR@l
lwz r6, IMMRBAR(r4)
isync
stw r3, IMMRBAR(r4)
lwz r6, 0(r7) /* Arbitrary external load */
isync
lwz r6, IMMRBAR(r3)
isync
/* Initialise the E300 processor core */
/*------------------------------------------*/
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
defined(CONFIG_NAND_SPL)
/* The FCM begins execution after only the first page
* is loaded. Wait for the rest before branching
* to another flash page.
*/
1: lwz r6, 0x50b0(r3)
andi. r6, r6, 1
beq 1b
#endif
bl init_e300_core
#ifdef CONFIG_SYS_FLASHBOOT
/* Inflate flash location so it appears everywhere, calculate */
/* the absolute address in final location of the FLASH, jump */
/* there and deflate the flash size back to minimal size */
/*------------------------------------------------------------*/
bl map_flash_by_law1
lis r4, (CONFIG_SYS_MONITOR_BASE)@h
ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r5
blr
in_flash:
#if 1 /* Remapping flash with LAW0. */
bl remap_flash_by_law0
#endif
#endif /* CONFIG_SYS_FLASHBOOT */
/* setup the bats */
bl setup_bats
sync
/*
* Cache must be enabled here for stack-in-cache trick.
* This means we need to enable the BATS.
* This means:
* 1) for the EVB, original gt regs need to be mapped
* 2) need to have an IBAT for the 0xf region,
* we are running there!
* Cache should be turned on after BATs, since by default
* everything is write-through.
* The init-mem BAT can be reused after reloc. The old
* gt-regs BAT can be reused after board_init_f calls
* board_early_init_f (EVB only).
*/
/* enable address translation */
bl enable_addr_trans
sync
/* enable the data cache */
bl dcache_enable
sync
#ifdef CONFIG_SYS_INIT_RAM_LOCK
bl lock_ram_in_cache
sync
#endif
/* set up the stack pointer in our newly created
* cache-ram; use r3 to keep the new SP for now to
* avoid overiding the SP it uselessly */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
/* r4 = end of GD area */
addi r4, r3, GENERATED_GBL_DATA_SIZE
/* Zero GD area */
li r0, 0
1:
subi r4, r4, 1
stb r0, 0(r4)
cmplw r3, r4
bne 1b
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
/* r3 = new stack pointer / pre-reloc malloc area */
subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN)
/* Set pointer to pre-reloc malloc area in GD */
stw r3, GD_MALLOC_BASE(r4)
#endif
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r3) /* clear final stack frame so that */
stwu r0, -4(r3) /* stack backtraces terminate cleanly */
/* Finally, actually set SP */
mr r1, r3
/* let the C-code set up the rest */
/* */
/* Be careful to keep code relocatable & stack humble */
/*------------------------------------------------------*/
GET_GOT /* initialize GOT access */
/* Needed for -msingle-pic-base */
bl _GLOBAL_OFFSET_TABLE_@local-4
mflr r30
/* r3: IMMR */
lis r3, CONFIG_SYS_IMMR@h
/* run low-level CPU init code (in Flash)*/
bl cpu_init_f
/* run 1st part of board init code (in Flash)*/
li r3, 0 /* clear boot_flag for calling board_init_f */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
#ifndef MINIMAL_SPL
/*
* Vector Table
*/
.globl _start_of_vectors
_start_of_vectors:
/* Machine check */
STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. */
STD_EXCEPTION(0x300, DataStorage, UnknownException)
/* Instruction Storage exception. */
STD_EXCEPTION(0x400, InstStorage, UnknownException)
/* External Interrupt exception. */
#ifndef FIXME
STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
#endif
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
MSR_KERNEL, COPY_EE)
STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
/* I guess we could implement decrementer, and may have
* to someday for timekeeping.
*/
STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
STD_EXCEPTION(0xc00, SystemCall, UnknownException)
STD_EXCEPTION(0xd00, SingleStep, UnknownException)
STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
#ifdef DEBUG
. = 0x1300
/*
* This exception occurs when the program counter matches the
* Instruction Address Breakpoint Register (IABR).
*
* I want the cpu to halt if this occurs so I can hunt around
* with the debugger and look at things.
*
* When DEBUG is defined, both machine check enable (in the MSR)
* and checkstop reset enable (in the reset mode register) are
* turned off and so a checkstop condition will result in the cpu
* halting.
*
* I force the cpu into a checkstop condition by putting an illegal
* instruction here (at least this is the theory).
*
* well - that didnt work, so just do an infinite loop!
*/
1: b 1b
#else
STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
#endif
STD_EXCEPTION(0x1400, SMI, UnknownException)
STD_EXCEPTION(0x1500, Trap_15, UnknownException)
STD_EXCEPTION(0x1600, Trap_16, UnknownException)
STD_EXCEPTION(0x1700, Trap_17, UnknownException)
STD_EXCEPTION(0x1800, Trap_18, UnknownException)
STD_EXCEPTION(0x1900, Trap_19, UnknownException)
STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
STD_EXCEPTION(0x2000, Trap_20, UnknownException)
STD_EXCEPTION(0x2100, Trap_21, UnknownException)
STD_EXCEPTION(0x2200, Trap_22, UnknownException)
STD_EXCEPTION(0x2300, Trap_23, UnknownException)
STD_EXCEPTION(0x2400, Trap_24, UnknownException)
STD_EXCEPTION(0x2500, Trap_25, UnknownException)
STD_EXCEPTION(0x2600, Trap_26, UnknownException)
STD_EXCEPTION(0x2700, Trap_27, UnknownException)
STD_EXCEPTION(0x2800, Trap_28, UnknownException)
STD_EXCEPTION(0x2900, Trap_29, UnknownException)
STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
.globl _end_of_vectors
_end_of_vectors:
. = 0x3000
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
* Register r21 is pointer into trap frame, r1 has new stack pointer.
*/
.globl transfer_to_handler
transfer_to_handler:
stw r22,_NIP(r21)
lis r22,MSR_POW@h
andc r23,r23,r22
stw r23,_MSR(r21)
SAVE_GPR(7, r21)
SAVE_4GPRS(8, r21)
SAVE_8GPRS(12, r21)
SAVE_8GPRS(24, r21)
mflr r23
andi. r24,r23,0x3f00 /* get vector offset */
stw r24,TRAP(r21)
li r22,0
stw r22,RESULT(r21)
lwz r24,0(r23) /* virtual address of handler */
lwz r23,4(r23) /* where to go when done */
mtspr SRR0,r24
mtspr SRR1,r20
mtlr r23
SYNC
rfi /* jump to handler, enable MMU */
int_return:
mfmsr r28 /* Disable interrupts */
li r4,0
ori r4,r4,MSR_EE
andc r28,r28,r4
SYNC /* Some chip revs need this... */
mtmsr r28
SYNC
lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
lwz r2,_XER(r1)
lwz r0,_CCR(r1)
mtspr XER,r2
mtcrf 0xFF,r0
REST_10GPRS(3, r1)
REST_10GPRS(13, r1)
REST_8GPRS(23, r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr SRR0,r2
mtspr SRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfi
#endif /* !MINIMAL_SPL */
/*
* This code initialises the E300 processor core
* (conforms to PowerPC 603e spec)
* Note: expects original MSR contents to be in r5.
*/
.globl init_e300_core
init_e300_core: /* time t 10 */
/* Initialize machine status; enable machine check interrupt */
/*-----------------------------------------------------------*/
li r3, MSR_KERNEL /* Set ME and RI flags */
rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
#ifdef DEBUG
rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
#endif
SYNC /* Some chip revs need this... */
mtmsr r3
SYNC
mtspr SRR1, r3 /* Make SRR1 match MSR */
lis r3, CONFIG_SYS_IMMR@h
#if defined(CONFIG_WATCHDOG)
/* Initialise the Watchdog values and reset it (if req) */
/*------------------------------------------------------*/
lis r4, CONFIG_SYS_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
stw r4, SWCRR(r3)
/* and reset it */
li r4, 0x556C
sth r4, SWSRR@l(r3)
li r4, -0x55C7
sth r4, SWSRR@l(r3)
#else
/* Disable Watchdog */
/*-------------------*/
lwz r4, SWCRR(r3)
/* Check to see if its enabled for disabling
once disabled by SW you can't re-enable */
andi. r4, r4, 0x4
beq 1f
xor r4, r4, r4
stw r4, SWCRR(r3)
1:
#endif /* CONFIG_WATCHDOG */
#if defined(CONFIG_MASK_AER_AO)
/* Write the Arbiter Event Enable to mask Address Only traps. */
/* This prevents the dcbz instruction from being trapped when */
/* HID0_ABE Address Broadcast Enable is set and the MEMORY */
/* COHERENCY bit is set in the WIMG bits, which is often */
/* needed for PCI operation. */
lwz r4, 0x0808(r3)
rlwinm r0, r4, 0, ~AER_AO
stw r0, 0x0808(r3)
#endif /* CONFIG_MASK_AER_AO */
/* Initialize the Hardware Implementation-dependent Registers */
/* HID0 also contains cache control */
/* - force invalidation of data and instruction caches */
/*------------------------------------------------------*/
lis r3, CONFIG_SYS_HID0_INIT@h
ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
SYNC
mtspr HID0, r3
lis r3, CONFIG_SYS_HID0_FINAL@h
ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
SYNC
mtspr HID0, r3
lis r3, CONFIG_SYS_HID2@h
ori r3, r3, CONFIG_SYS_HID2@l
SYNC
mtspr HID2, r3
/* Done! */
/*------------------------------*/
blr
/* setup_bats - set them up to some initial state */
.globl setup_bats
setup_bats:
addis r0, r0, 0x0000
/* IBAT 0 */
addis r4, r0, CONFIG_SYS_IBAT0L@h
ori r4, r4, CONFIG_SYS_IBAT0L@l
addis r3, r0, CONFIG_SYS_IBAT0U@h
ori r3, r3, CONFIG_SYS_IBAT0U@l
mtspr IBAT0L, r4
mtspr IBAT0U, r3
/* DBAT 0 */
addis r4, r0, CONFIG_SYS_DBAT0L@h
ori r4, r4, CONFIG_SYS_DBAT0L@l
addis r3, r0, CONFIG_SYS_DBAT0U@h
ori r3, r3, CONFIG_SYS_DBAT0U@l
mtspr DBAT0L, r4
mtspr DBAT0U, r3
/* IBAT 1 */
addis r4, r0, CONFIG_SYS_IBAT1L@h
ori r4, r4, CONFIG_SYS_IBAT1L@l
addis r3, r0, CONFIG_SYS_IBAT1U@h
ori r3, r3, CONFIG_SYS_IBAT1U@l
mtspr IBAT1L, r4
mtspr IBAT1U, r3
/* DBAT 1 */
addis r4, r0, CONFIG_SYS_DBAT1L@h
ori r4, r4, CONFIG_SYS_DBAT1L@l
addis r3, r0, CONFIG_SYS_DBAT1U@h
ori r3, r3, CONFIG_SYS_DBAT1U@l
mtspr DBAT1L, r4
mtspr DBAT1U, r3
/* IBAT 2 */
addis r4, r0, CONFIG_SYS_IBAT2L@h
ori r4, r4, CONFIG_SYS_IBAT2L@l
addis r3, r0, CONFIG_SYS_IBAT2U@h
ori r3, r3, CONFIG_SYS_IBAT2U@l
mtspr IBAT2L, r4
mtspr IBAT2U, r3
/* DBAT 2 */
addis r4, r0, CONFIG_SYS_DBAT2L@h
ori r4, r4, CONFIG_SYS_DBAT2L@l
addis r3, r0, CONFIG_SYS_DBAT2U@h
ori r3, r3, CONFIG_SYS_DBAT2U@l
mtspr DBAT2L, r4
mtspr DBAT2U, r3
/* IBAT 3 */
addis r4, r0, CONFIG_SYS_IBAT3L@h
ori r4, r4, CONFIG_SYS_IBAT3L@l
addis r3, r0, CONFIG_SYS_IBAT3U@h
ori r3, r3, CONFIG_SYS_IBAT3U@l
mtspr IBAT3L, r4
mtspr IBAT3U, r3
/* DBAT 3 */
addis r4, r0, CONFIG_SYS_DBAT3L@h
ori r4, r4, CONFIG_SYS_DBAT3L@l
addis r3, r0, CONFIG_SYS_DBAT3U@h
ori r3, r3, CONFIG_SYS_DBAT3U@l
mtspr DBAT3L, r4
mtspr DBAT3U, r3
#ifdef CONFIG_HIGH_BATS
/* IBAT 4 */
addis r4, r0, CONFIG_SYS_IBAT4L@h
ori r4, r4, CONFIG_SYS_IBAT4L@l
addis r3, r0, CONFIG_SYS_IBAT4U@h
ori r3, r3, CONFIG_SYS_IBAT4U@l
mtspr IBAT4L, r4
mtspr IBAT4U, r3
/* DBAT 4 */
addis r4, r0, CONFIG_SYS_DBAT4L@h
ori r4, r4, CONFIG_SYS_DBAT4L@l
addis r3, r0, CONFIG_SYS_DBAT4U@h
ori r3, r3, CONFIG_SYS_DBAT4U@l
mtspr DBAT4L, r4
mtspr DBAT4U, r3
/* IBAT 5 */
addis r4, r0, CONFIG_SYS_IBAT5L@h
ori r4, r4, CONFIG_SYS_IBAT5L@l
addis r3, r0, CONFIG_SYS_IBAT5U@h
ori r3, r3, CONFIG_SYS_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
/* DBAT 5 */
addis r4, r0, CONFIG_SYS_DBAT5L@h
ori r4, r4, CONFIG_SYS_DBAT5L@l
addis r3, r0, CONFIG_SYS_DBAT5U@h
ori r3, r3, CONFIG_SYS_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
/* IBAT 6 */
addis r4, r0, CONFIG_SYS_IBAT6L@h
ori r4, r4, CONFIG_SYS_IBAT6L@l
addis r3, r0, CONFIG_SYS_IBAT6U@h
ori r3, r3, CONFIG_SYS_IBAT6U@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
/* DBAT 6 */
addis r4, r0, CONFIG_SYS_DBAT6L@h
ori r4, r4, CONFIG_SYS_DBAT6L@l
addis r3, r0, CONFIG_SYS_DBAT6U@h
ori r3, r3, CONFIG_SYS_DBAT6U@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
/* IBAT 7 */
addis r4, r0, CONFIG_SYS_IBAT7L@h
ori r4, r4, CONFIG_SYS_IBAT7L@l
addis r3, r0, CONFIG_SYS_IBAT7U@h
ori r3, r3, CONFIG_SYS_IBAT7U@l
mtspr IBAT7L, r4
mtspr IBAT7U, r3
/* DBAT 7 */
addis r4, r0, CONFIG_SYS_DBAT7L@h
ori r4, r4, CONFIG_SYS_DBAT7L@l
addis r3, r0, CONFIG_SYS_DBAT7U@h
ori r3, r3, CONFIG_SYS_DBAT7U@l
mtspr DBAT7L, r4
mtspr DBAT7U, r3
#endif
isync
/* invalidate all tlb's
*
* From the 603e User Manual: "The 603e provides the ability to
* invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
* instruction invalidates the TLB entry indexed by the EA, and
* operates on both the instruction and data TLBs simultaneously
* invalidating four TLB entries (both sets in each TLB). The
* index corresponds to bits 15-19 of the EA. To invalidate all
* entries within both TLBs, 32 tlbie instructions should be
* issued, incrementing this field by one each time."
*
* "Note that the tlbia instruction is not implemented on the
* 603e."
*
* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
* incrementing by 0x1000 each time. The code below is sort of
* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
*
*/
lis r3, 0
lis r5, 2
1:
tlbie r3
addi r3, r3, 0x1000
cmp 0, 0, r3, r5
blt 1b
blr
/* Cache functions.
*
* Note: requires that all cache bits in
* HID0 are in the low half word.
*/
#ifndef MINIMAL_SPL
.globl icache_enable
icache_enable:
mfspr r3, HID0
ori r3, r3, HID0_ICE
li r4, HID0_ICFI|HID0_ILOCK
andc r3, r3, r4
ori r4, r3, HID0_ICFI
isync
mtspr HID0, r4 /* sets enable and invalidate, clears lock */
isync
mtspr HID0, r3 /* clears invalidate */
blr
.globl icache_disable
icache_disable:
mfspr r3, HID0
lis r4, 0
ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
andc r3, r3, r4
isync
mtspr HID0, r3 /* clears invalidate, enable and lock */
blr
.globl icache_status
icache_status:
mfspr r3, HID0
rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
blr
#endif /* !MINIMAL_SPL */
.globl dcache_enable
dcache_enable:
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
andc r3, r3, r5
ori r3, r3, HID0_DCE
sync
mtspr HID0, r3 /* enable, no invalidate */
blr
.globl dcache_disable
dcache_disable:
mflr r4
bl flush_dcache /* uses r3 and r5 */
mfspr r3, HID0
li r5, HID0_DCE|HID0_DLOCK
andc r3, r3, r5
ori r5, r3, HID0_DCFI
sync
mtspr HID0, r5 /* sets invalidate, clears enable and lock */
sync
mtspr HID0, r3 /* clears invalidate */
mtlr r4
blr
.globl dcache_status
dcache_status:
mfspr r3, HID0
rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
blr
.globl flush_dcache
flush_dcache:
lis r3, 0
lis r5, CONFIG_SYS_CACHELINE_SIZE
1: cmp 0, 1, r3, r5
bge 2f
lwz r5, 0(r3)
lis r5, CONFIG_SYS_CACHELINE_SIZE
addi r3, r3, 0x4
b 1b
2: blr
/*-------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Global Data pointer */
mr r10, r5 /* Save copy of Destination Address */
GET_GOT
mr r3, r5 /* Destination Address */
lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__bss_start)
sub r5, r5, r4
li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
* + Destination Address
*
* Offset:
*/
sub r15, r10, r4
/* First our own GOT */
add r12, r12, r15
/* then the one used by the C code */
add r30, r30, r15
/*
* Now relocate code
*/
cmplw cr1,r3,r4
addi r0,r5,3
srwi. r0,r0,2
beq cr1,4f /* In place copy is not necessary */
beq 7f /* Protect against 0 count */
mtctr r0
bge cr1,2f
la r8,-4(r4)
la r7,-4(r3)
/* copy */
1: lwzu r0,4(r8)
stwu r0,4(r7)
bdnz 1b
addi r0,r5,3
srwi. r0,r0,2
mtctr r0
la r8,-4(r4)
la r7,-4(r3)
/* and compare */
20: lwzu r20,4(r8)
lwzu r21,4(r7)
xor. r22, r20, r21
bne 30f
bdnz 20b
b 4f
/* compare failed */
30: li r3, 0
blr
2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
add r8,r4,r0
add r7,r3,r0
3: lwzu r0,-4(r8)
stwu r0,-4(r7)
bdnz 3b
/*
* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
*/
4: cmpwi r6,0
add r5,r3,r5
beq 7f /* Always flush prefetch queue in any case */
subi r0,r6,1
andc r3,r3,r0
mr r4,r3
5: dcbst 0,r4
add r4,r4,r6
cmplw r4,r5
blt 5b
sync /* Wait for all dcbst to complete on bus */
mr r4,r3
6: icbi 0,r4
add r4,r4,r6
cmplw r4,r5
blt 6b
7: sync /* Wait for all icbi to complete on bus */
isync
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
mtlr r0
blr
in_ram:
/*
* Relocation Function, r12 point to got2+0x8000
*
* Adjust got2 pointers, no need to check for 0, this code
* already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
lwz r11,GOT(_GOT2_TABLE_)
mtctr r0
sub r11,r3,r11
addi r3,r3,-4
1: lwzu r0,4(r3)
cmpwi r0,0
beq- 2f
add r0,r0,r11
stw r0,0(r3)
2: bdnz 1b
#ifndef MINIMAL_SPL
/*
* Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
li r0,__fixup_entries@sectoff@l
lwz r3,GOT(_FIXUP_TABLE_)
cmpwi r0,0
mtctr r0
addi r3,r3,-4
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
cmpwi r0,0
add r0,r0,r11
stw r4,0(r3)
beq- 5f
stw r0,0(r4)
5: bdnz 3b
4:
#endif
clear_bss:
/*
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
li r0, 0
5:
stw r0, 0(r3)
addi r3, r3, 4
cmplw 0, r3, r4
bne 5b
6:
mr r3, r9 /* Global Data pointer */
mr r4, r10 /* Destination Address */
bl board_init_r
#ifndef MINIMAL_SPL
/*
* Copy exception vector code to low memory
*
* r3: dest_addr
* r7: source address, r8: end address, r9: target address
*/
.globl trap_init
trap_init:
mflr r4 /* save link register */
GET_GOT
lwz r7, GOT(_start)
lwz r8, GOT(_end_of_vectors)
li r9, 0x100 /* reset vector always at 0x100 */
cmplw 0, r7, r8
bgelr /* return if r7>=r8 - just in case */
1:
lwz r0, 0(r7)
stw r0, 0(r9)
addi r7, r7, 4
addi r9, r9, 4
cmplw 0, r7, r8
bne 1b
/*
* relocate `hdlr' and `int_return' entries
*/
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
li r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 2b
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 3b
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 4b
mfmsr r3 /* now that the vectors have */
lis r7, MSR_IP@h /* relocated into low memory */
ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
andc r3, r3, r7 /* (if it was on) */
SYNC /* Some chip revs need this... */
mtmsr r3
SYNC
mtlr r4 /* restore link register */
blr
#endif /* !MINIMAL_SPL */
#ifdef CONFIG_SYS_INIT_RAM_LOCK
lock_ram_in_cache:
/* Allocate Initial RAM in data cache.
*/
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
dcbz r0, r3
addi r3, r3, 32
bdnz 1b
/* Lock the data cache */
mfspr r0, HID0
ori r0, r0, HID0_DLOCK
sync
mtspr HID0, r0
sync
blr
#ifndef MINIMAL_SPL
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1: icbi r0, r3
dcbi r0, r3
addi r3, r3, 32
bdnz 1b
sync /* Wait for all icbi to complete on bus */
isync
/* Unlock the data cache and invalidate it */
mfspr r3, HID0
li r5, HID0_DLOCK|HID0_DCFI
andc r3, r3, r5 /* no invalidate, unlock */
ori r5, r3, HID0_DCFI /* invalidate, unlock */
sync
mtspr HID0, r5 /* invalidate, unlock */
sync
mtspr HID0, r3 /* no invalidate, unlock */
blr
#endif /* !MINIMAL_SPL */
#endif /* CONFIG_SYS_INIT_RAM_LOCK */
#ifdef CONFIG_SYS_FLASHBOOT
map_flash_by_law1:
/* When booting from ROM (Flash or EPROM), clear the */
/* Address Mask in OR0 so ROM appears everywhere */
/*----------------------------------------------------*/
lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
lwz r4, OR0@l(r3)
li r5, 0x7fff /* r5 <= 0x00007FFFF */
and r4, r4, r5
stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
/* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
* system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
* reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
* from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
* 0xFF800. From the hard resetting to here, the processor fetched and
* executed the instructions one by one. There is not absolutely
* jumping happened. Laterly, the u-boot code has to do an absolutely
* jumping to tell the CPU instruction fetching component what the
* u-boot TEXT base address is. Because the TEXT base resides in the
* boot ROM memory space, to garantee the code can run smoothly after
* that jumping, we must map in the entire boot ROM by Local Access
* Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
* address for boot ROM, such as 0xFE000000. In this case, the default
* LBIU Local Access Widow 0 will not cover this memory space. So, we
* need another window to map in it.
*/
lis r4, (CONFIG_SYS_FLASH_BASE)@h
ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
/* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
lis r4, (0x80000012)@h
ori r4, r4, (0x80000012)@l
li r5, CONFIG_SYS_FLASH_SIZE
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
addi r4, r4, 1
bne 1b
stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
/* Wait for HW to catch up */
lwz r4, LBLAWAR1(r3)
twi 0,r4,0
isync
blr
/* Though all the LBIU Local Access Windows and LBC Banks will be
* initialized in the C code, we'd better configure boot ROM's
* window 0 and bank 0 correctly at here.
*/
remap_flash_by_law0:
/* Initialize the BR0 with the boot ROM starting address. */
lwz r4, BR0(r3)
li r5, 0x7FFF
and r4, r4, r5
lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
or r5, r5, r4
stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
lwz r4, OR0(r3)
lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
or r4, r4, r5
stw r4, OR0(r3)
lis r4, (CONFIG_SYS_FLASH_BASE)@h
ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
/* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
lis r4, (0x80000012)@h
ori r4, r4, (0x80000012)@l
li r5, CONFIG_SYS_FLASH_SIZE
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
addi r4, r4, 1
bne 1b
stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
xor r4, r4, r4
stw r4, LBLAWBAR1(r3)
stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
/* Wait for HW to catch up */
lwz r4, LBLAWAR1(r3)
twi 0,r4,0
isync
blr
#endif /* CONFIG_SYS_FLASHBOOT */
|
genetel200/u-boot
| 11,805
|
arch/powerpc/cpu/mpc85xx/release.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2008-2012 Freescale Semiconductor, Inc.
* Kumar Gala <kumar.gala@freescale.com>
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
/* To boot secondary cpus, we need a place for them to start up.
* Normally, they start at 0xfffffffc, but that's usually the
* firmware, and we don't want to have to run the firmware again.
* Instead, the primary cpu will set the BPTR to point here to
* this page. We then set up the core, and head to
* start_secondary. Note that this means that the code below
* must never exceed 1023 instructions (the branch at the end
* would then be the 1024th).
*/
.globl __secondary_start_page
.align 12
__secondary_start_page:
#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
msync
isync
mfspr r3, SPRN_HDBCR0
oris r3, r3, 0x0080
mtspr SPRN_HDBCR0, r3
#endif
/* First do some preliminary setup */
lis r3, HID0_EMCP@h /* enable machine check */
#ifndef CONFIG_E500MC
ori r3,r3,HID0_TBEN@l /* enable Timebase */
#endif
#ifdef CONFIG_PHYS_64BIT
ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
#endif
mtspr SPRN_HID0,r3
#ifndef CONFIG_E500MC
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r0,PVR
andi. r0,r0,0xff
cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
blt 1f
/* Set MBDD bit also */
ori r3, r3, HID1_MBDD@l
1:
mtspr SPRN_HID1,r3
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
mfspr r3,SPRN_HDBCR1
oris r3,r3,0x0100
mtspr SPRN_HDBCR1,r3
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
mfspr r3,SPRN_SVR
rlwinm r3,r3,0,0xff
li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
cmpw r3,r4
beq 1f
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
cmpw r3,r4
beq 1f
#endif
/* Not a supported revision affected by erratum */
b 2f
1: /* Erratum says set bits 55:60 to 001001 */
msync
isync
mfspr r3,SPRN_HDBCR0
li r4,0x48
rlwimi r3,r4,0,0x1f8
mtspr SPRN_HDBCR0,r3
isync
2:
#endif
/* Enable branch prediction */
lis r3,BUCSR_ENABLE@h
ori r3,r3,BUCSR_ENABLE@l
mtspr SPRN_BUCSR,r3
/* Ensure TB is 0 */
li r3,0
mttbl r3
mttbu r3
/* Enable/invalidate the I-Cache */
lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
mtspr SPRN_L1CSR1,r2
1:
mfspr r3,SPRN_L1CSR1
and. r1,r3,r2
bne 1b
lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
mtspr SPRN_L1CSR1,r3
isync
2:
mfspr r3,SPRN_L1CSR1
andi. r1,r3,L1CSR1_ICE@l
beq 2b
/* Enable/invalidate the D-Cache */
lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
mtspr SPRN_L1CSR0,r2
1:
mfspr r3,SPRN_L1CSR0
and. r1,r3,r2
bne 1b
lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
mtspr SPRN_L1CSR0,r3
isync
2:
mfspr r3,SPRN_L1CSR0
andi. r1,r3,L1CSR0_DCE@l
beq 2b
#define toreset(x) (x - __secondary_start_page + 0xfffff000)
/* get our PIR to figure out our table entry */
lis r3,toreset(__spin_table_addr)@h
ori r3,r3,toreset(__spin_table_addr)@l
lwz r3,0(r3)
mfspr r0,SPRN_PIR
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
* PIR definition for Chassis 2
* 0-17 Reserved (logic 0s)
* 18-19 CHIP_ID, 2'b00 - SoC 1
* all others - reserved
* 20-24 CLUSTER_ID 5'b00000 - CCM 1
* all others - reserved
* 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
* 2'b01 - cluster 2
* 2'b10 - cluster 3
* 2'b11 - cluster 4
* 27-28 CORE_ID 2'b00 - core 0
* 2'b01 - core 1
* 2'b10 - core 2
* 2'b11 - core 3
* 29-31 THREAD_ID 3'b000 - thread 0
* 3'b001 - thread 1
*
* Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
* and clusters by 0x20.
*
* We renumber PIR so that all threads in the system are consecutive.
*/
rlwinm r8,r0,29,0x03 /* r8 = core within cluster */
srwi r10,r0,5 /* r10 = cluster */
mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
add r5,r5,r8 /* for spin table index */
mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */
#elif defined(CONFIG_E500MC)
rlwinm r4,r0,27,27,31
mr r5,r4
#else
mr r4,r0
mr r5,r4
#endif
/*
* r10 has the base address for the entry.
* we cannot access it yet before setting up a new TLB
*/
slwi r8,r5,6 /* spin table is padded to 64 byte */
add r10,r3,r8
mtspr SPRN_PIR,r4 /* write to PIR register */
#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
mfspr r8, L1CSR2
clrrwi r8, r8, 10 /* clear bit [54-63] DCSTASHID */
mtspr L1CSR2, r8
#else
#ifdef CONFIG_SYS_CACHE_STASHING
/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
slwi r8,r4,1
addi r8,r8,32
mtspr L1CSR2,r8
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
*/
mfspr r3,SPRN_SVR
rlwinm r6,r3,24,~0x800 /* clear E bit */
lis r5,SVR_P4080@h
ori r5,r5,SVR_P4080@l
cmpw r6,r5
bne 1f
rlwinm r3,r3,0,0xf0
li r5,0x30
cmpw r3,r5
bge 2f
1:
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
lis r3,toreset(enable_cpu_a011_workaround)@ha
lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
cmpwi r3,0
beq 2f
#endif
mfspr r3,L1CSR2
oris r3,r3,(L1CSR2_DCWS)@h
mtspr L1CSR2,r3
2:
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
/*
* A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
* write shadow mode. This code should run after other code setting
* DCWS.
*/
mfspr r3,L1CSR2
andis. r3,r3,(L1CSR2_DCWS)@h
beq 1f
mfspr r3, SPRN_HDBCR0
oris r3, r3, 0x8000
mtspr SPRN_HDBCR0, r3
1:
#endif
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* skip L2 setup on P2040/P2040E as they have no L2 */
mfspr r3,SPRN_SVR
rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
lis r3,SVR_P2040@h
ori r3,r3,SVR_P2040@l
cmpw r6,r3
beq 3f
/* Enable/invalidate the L2 cache */
msync
lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
mtspr SPRN_L2CSR0,r2
1:
mfspr r3,SPRN_L2CSR0
and. r1,r3,r2
bne 1b
#ifdef CONFIG_SYS_CACHE_STASHING
/* set stash id to (coreID) * 2 + 32 + L2 (1) */
addi r3,r8,1
mtspr SPRN_L2CSR1,r3
#endif
lis r3,CONFIG_SYS_INIT_L2CSR0@h
ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
mtspr SPRN_L2CSR0,r3
isync
2:
mfspr r3,SPRN_L2CSR0
andis. r1,r3,L2CSR0_L2E@h
beq 2b
#endif
3:
/* setup mapping for the spin table, WIMGE=0b00100 */
lis r13,toreset(__spin_table_addr)@h
ori r13,r13,toreset(__spin_table_addr)@l
lwz r13,0(r13)
/* mask by 4K */
rlwinm r13,r13,0,0,19
lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
mtspr SPRN_MAS0,r11
lis r11,(MAS1_VALID|MAS1_IPROT)@h
ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
mtspr SPRN_MAS1,r11
oris r11,r13,(MAS2_M|MAS2_G)@h
ori r11,r13,(MAS2_M|MAS2_G)@l
mtspr SPRN_MAS2,r11
oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
mtspr SPRN_MAS3,r11
li r11,0
mtspr SPRN_MAS7,r11
tlbwe
/*
* __bootpg_addr has the address of __second_half_boot_page
* jump there in AS=1 space with cache enabled
*/
lis r13,toreset(__bootpg_addr)@h
ori r13,r13,toreset(__bootpg_addr)@l
lwz r11,0(r13)
mtspr SPRN_SRR0,r11
mfmsr r13
ori r12,r13,MSR_IS|MSR_DS@l
mtspr SPRN_SRR1,r12
rfi
/*
* Allocate some space for the SDRAM address of the bootpg.
* This variable has to be in the boot page so that it can
* be accessed by secondary cores when they come out of reset.
*/
.align L1_CACHE_SHIFT
.globl __bootpg_addr
__bootpg_addr:
.long 0
.global __spin_table_addr
__spin_table_addr:
.long 0
/*
* This variable is set by cpu_init_r() after parsing hwconfig
* to enable workaround for erratum NMG_CPU_A011.
*/
.align L1_CACHE_SHIFT
.global enable_cpu_a011_workaround
enable_cpu_a011_workaround:
.long 1
/* Fill in the empty space. The actual reset vector is
* the last word of the page */
__secondary_start_code_end:
.space 4092 - (__secondary_start_code_end - __secondary_start_page)
__secondary_reset_vector:
b __secondary_start_page
/* this is a separated page for the spin table and cacheable boot code */
.align L1_CACHE_SHIFT
.global __second_half_boot_page
__second_half_boot_page:
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
lis r3,(spin_table_compat - __second_half_boot_page)@h
ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
lwz r14,0(r3)
#endif
#define ENTRY_ADDR_UPPER 0
#define ENTRY_ADDR_LOWER 4
#define ENTRY_R3_UPPER 8
#define ENTRY_R3_LOWER 12
#define ENTRY_RESV 16
#define ENTRY_PIR 20
#define ENTRY_SIZE 64
/*
* setup the entry
* r10 has the base address of the spin table.
* spin table is defined as
* struct {
* uint64_t entry_addr;
* uint64_t r3;
* uint32_t rsvd1;
* uint32_t pir;
* };
* we pad this struct to 64 bytes so each entry is in its own cacheline
*/
li r3,0
li r8,1
mfspr r4,SPRN_PIR
stw r3,ENTRY_ADDR_UPPER(r10)
stw r3,ENTRY_R3_UPPER(r10)
stw r4,ENTRY_R3_LOWER(r10)
stw r3,ENTRY_RESV(r10)
stw r4,ENTRY_PIR(r10)
msync
stw r8,ENTRY_ADDR_LOWER(r10)
/* spin waiting for addr */
3:
/*
* To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
* memory. Old OS may not work with this change. A patch is waiting to be
* accepted for Linux kernel. Other OS needs similar fix to spin table.
* For OSes with old spin table code, we can enable this temporary fix by
* setting environmental variable "spin_table_compat". For new OSes, set
* "spin_table_compat=no". After Linux is fixed, we can remove this macro
* and related code. For now, it is enabled by default.
*/
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
cmpwi r14,0
beq 4f
dcbf 0, r10
sync
4:
#endif
lwz r4,ENTRY_ADDR_LOWER(r10)
andi. r11,r4,1
bne 3b
isync
/* get the upper bits of the addr */
lwz r11,ENTRY_ADDR_UPPER(r10)
/* setup branch addr */
mtspr SPRN_SRR0,r4
/* mark the entry as released */
li r8,3
stw r8,ENTRY_ADDR_LOWER(r10)
/* mask by ~64M to setup our tlb we will jump to */
rlwinm r12,r4,0,0,5
/*
* setup r3, r4, r5, r6, r7, r8, r9
* r3 contains the value to put in the r3 register at secondary cpu
* entry. The high 32-bits are ignored on 32-bit chip implementations.
* 64-bit chip implementations however shall load all 64-bits
*/
#ifdef CONFIG_SYS_PPC64
ld r3,ENTRY_R3_UPPER(r10)
#else
lwz r3,ENTRY_R3_LOWER(r10)
#endif
li r4,0
li r5,0
li r6,0
lis r7,(64*1024*1024)@h
li r8,0
li r9,0
/* load up the pir */
lwz r0,ENTRY_PIR(r10)
mtspr SPRN_PIR,r0
mfspr r0,SPRN_PIR
stw r0,ENTRY_PIR(r10)
mtspr IVPR,r12
/*
* Coming here, we know the cpu has one TLB mapping in TLB1[0]
* which maps 0xfffff000-0xffffffff one-to-one. We set up a
* second mapping that maps addr 1:1 for 64M, and then we jump to
* addr
*/
lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
mtspr SPRN_MAS0,r10
lis r10,(MAS1_VALID|MAS1_IPROT)@h
ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
mtspr SPRN_MAS1,r10
/* WIMGE = 0b00000 for now */
mtspr SPRN_MAS2,r12
ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
mtspr SPRN_MAS3,r12
#ifdef CONFIG_ENABLE_36BIT_PHYS
mtspr SPRN_MAS7,r11
#endif
tlbwe
/* Now we have another mapping for this page, so we jump to that
* mapping
*/
mtspr SPRN_SRR1,r13
rfi
.align 6
.globl __spin_table
__spin_table:
.space CONFIG_MAX_CPUS*ENTRY_SIZE
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
.align L1_CACHE_SHIFT
.global spin_table_compat
spin_table_compat:
.long 1
#endif
__spin_table_end:
.space 4096 - (__spin_table_end - __spin_table)
|
genetel200/u-boot
| 43,554
|
arch/powerpc/cpu/mpc85xx/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
*/
/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
*
* The processor starts at 0xfffffffc and the code is first executed in the
* last 4K page(0xfffff000-0xffffffff) in flash/rom.
*
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
#include <version.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#undef MSR_KERNEL
#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
#define LAW_EN 0x80000000
#if defined(CONFIG_NAND_SPL) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
#define MINIMAL_SPL
#endif
#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
!defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define NOR_BOOT
#endif
/*
* Set up GOT: Global Offset Table
*
* Use r12 to access the GOT
*/
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
#ifndef MINIMAL_SPL
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
#endif
GOT_ENTRY(__init_end)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
/*
* e500 Startup -- after reset only the last 4KB of the effective
* address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
* section is located at THIS LAST page and basically does three
* things: clear some registers, set up exception tables and
* add more TLB entries for 'larger spaces'(e.g. the boot rom) to
* continue the boot procedure.
* Once the boot rom is mapped by TLB entries we can proceed
* with normal startup.
*
*/
.section .bootpg,"ax"
.globl _start_e500
_start_e500:
/* Enable debug exception */
li r1,MSR_DE
mtmsr r1
/*
* If we got an ePAPR device tree pointer passed in as r3, we need that
* later in cpu_init_early_f(). Save it to a safe register before we
* clobber it so that we can fetch it from there later.
*/
mr r24, r3
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
mfspr r3,SPRN_SVR
rlwinm r3,r3,0,0xff
li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
cmpw r3,r4
beq 1f
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
cmpw r3,r4
beq 1f
#endif
/* Not a supported revision affected by erratum */
li r27,0
b 2f
1: li r27,1 /* Remember for later that we have the erratum */
/* Erratum says set bits 55:60 to 001001 */
msync
isync
mfspr r3,SPRN_HDBCR0
li r4,0x48
rlwimi r3,r4,0,0x1f8
mtspr SPRN_HDBCR0,r3
isync
2:
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
msync
isync
mfspr r3, SPRN_HDBCR0
oris r3, r3, 0x0080
mtspr SPRN_HDBCR0, r3
#endif
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
!defined(CONFIG_E6500)
/* ISBC uses L2 as stack.
* Disable L2 cache here so that u-boot can enable it later
* as part of it's normal flow
*/
/* Check if L2 is enabled */
mfspr r3, SPRN_L2CSR0
lis r2, L2CSR0_L2E@h
ori r2, r2, L2CSR0_L2E@l
and. r4, r3, r2
beq l2_disabled
mfspr r3, SPRN_L2CSR0
/* Flush L2 cache */
lis r2,(L2CSR0_L2FL)@h
ori r2, r2, (L2CSR0_L2FL)@l
or r3, r2, r3
sync
isync
mtspr SPRN_L2CSR0,r3
isync
1:
mfspr r3, SPRN_L2CSR0
and. r1, r3, r2
bne 1b
mfspr r3, SPRN_L2CSR0
lis r2, L2CSR0_L2E@h
ori r2, r2, L2CSR0_L2E@l
andc r4, r3, r2
sync
isync
mtspr SPRN_L2CSR0,r4
isync
l2_disabled:
#endif
/* clear registers/arrays not reset by hardware */
/* L1 */
li r0,2
mtspr L1CSR0,r0 /* invalidate d-cache */
mtspr L1CSR1,r0 /* invalidate i-cache */
mfspr r1,DBSR
mtspr DBSR,r1 /* Clear all valid bits */
.macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
mtspr MAS0, \scratch
lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
mtspr MAS1, \scratch
lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
mtspr MAS2, \scratch
lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
mtspr MAS3, \scratch
lis \scratch, \phy_high@h
ori \scratch, \scratch, \phy_high@l
mtspr MAS7, \scratch
isync
msync
tlbwe
isync
.endm
.macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
mtspr MAS0, \scratch
lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
mtspr MAS1, \scratch
lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
mtspr MAS2, \scratch
lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
mtspr MAS3, \scratch
lis \scratch, \phy_high@h
ori \scratch, \scratch, \phy_high@l
mtspr MAS7, \scratch
isync
msync
tlbwe
isync
.endm
.macro delete_tlb1_entry esel scratch
lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
mtspr MAS0, \scratch
li \scratch, 0
mtspr MAS1, \scratch
isync
msync
tlbwe
isync
.endm
.macro delete_tlb0_entry esel epn wimg scratch
lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
mtspr MAS0, \scratch
li \scratch, 0
mtspr MAS1, \scratch
lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
mtspr MAS2, \scratch
isync
msync
tlbwe
isync
.endm
/* Interrupt vectors do not fit in minimal SPL. */
#if !defined(MINIMAL_SPL)
/* Setup interrupt vectors */
lis r1,CONFIG_SYS_MONITOR_BASE@h
mtspr IVPR,r1
li r4,CriticalInput@l
mtspr IVOR0,r4 /* 0: Critical input */
li r4,MachineCheck@l
mtspr IVOR1,r4 /* 1: Machine check */
li r4,DataStorage@l
mtspr IVOR2,r4 /* 2: Data storage */
li r4,InstStorage@l
mtspr IVOR3,r4 /* 3: Instruction storage */
li r4,ExtInterrupt@l
mtspr IVOR4,r4 /* 4: External interrupt */
li r4,Alignment@l
mtspr IVOR5,r4 /* 5: Alignment */
li r4,ProgramCheck@l
mtspr IVOR6,r4 /* 6: Program check */
li r4,FPUnavailable@l
mtspr IVOR7,r4 /* 7: floating point unavailable */
li r4,SystemCall@l
mtspr IVOR8,r4 /* 8: System call */
/* 9: Auxiliary processor unavailable(unsupported) */
li r4,Decrementer@l
mtspr IVOR10,r4 /* 10: Decrementer */
li r4,IntervalTimer@l
mtspr IVOR11,r4 /* 11: Interval timer */
li r4,WatchdogTimer@l
mtspr IVOR12,r4 /* 12: Watchdog timer */
li r4,DataTLBError@l
mtspr IVOR13,r4 /* 13: Data TLB error */
li r4,InstructionTLBError@l
mtspr IVOR14,r4 /* 14: Instruction TLB error */
li r4,DebugBreakpoint@l
mtspr IVOR15,r4 /* 15: Debug */
#endif
/* Clear and set up some registers. */
li r0,0x0000
lis r1,0xffff
mtspr DEC,r0 /* prevent dec exceptions */
mttbl r0 /* prevent fit & wdt exceptions */
mttbu r0
mtspr TSR,r1 /* clear all timer exception status */
mtspr TCR,r0 /* disable all */
mtspr ESR,r0 /* clear exception syndrome register */
mtspr MCSR,r0 /* machine check syndrome register */
mtxer r0 /* clear integer exception register */
#ifdef CONFIG_SYS_BOOK3E_HV
mtspr MAS8,r0 /* make sure MAS8 is clear */
#endif
/* Enable Time Base and Select Time Base Clock */
lis r0,HID0_EMCP@h /* Enable machine check */
#if defined(CONFIG_ENABLE_36BIT_PHYS)
ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
#endif
#ifndef CONFIG_E500MC
ori r0,r0,HID0_TBEN@l /* Enable Timebase */
#endif
mtspr HID0,r0
#if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500)
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r3,PVR
andi. r3,r3, 0xff
cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
blt 1f
/* Set MBDD bit also */
ori r0, r0, HID1_MBDD@l
1:
mtspr HID1,r0
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
mfspr r3,SPRN_HDBCR1
oris r3,r3,0x0100
mtspr SPRN_HDBCR1,r3
#endif
/* Enable Branch Prediction */
#if defined(CONFIG_BTB)
lis r0,BUCSR_ENABLE@h
ori r0,r0,BUCSR_ENABLE@l
mtspr SPRN_BUCSR,r0
#endif
#if defined(CONFIG_SYS_INIT_DBCR)
lis r1,0xffff
ori r1,r1,0xffff
mtspr DBSR,r1 /* Clear all status bits */
lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
ori r0,r0,CONFIG_SYS_INIT_DBCR@l
mtspr DBCR0,r0
#endif
#ifdef CONFIG_ARCH_MPC8569
#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
/* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
* use address space which is more than 12bits, and it must be done in
* the 4K boot page. So we set this bit here.
*/
/* create a temp mapping TLB0[0] for LBCR */
create_tlb0_entry 0, \
0, BOOKE_PAGESZ_4K, \
CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
0, r6
/* Set LBCR register */
lis r4,CONFIG_SYS_LBCR_ADDR@h
ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
lis r5,CONFIG_SYS_LBC_LBCR@h
ori r5,r5,CONFIG_SYS_LBC_LBCR@l
stw r5,0(r4)
isync
/* invalidate this temp TLB */
lis r4,CONFIG_SYS_LBC_ADDR@h
ori r4,r4,CONFIG_SYS_LBC_ADDR@l
tlbivax 0,r4
isync
#endif /* CONFIG_ARCH_MPC8569 */
/*
* Search for the TLB that covers the code we're executing, and shrink it
* so that it covers only this 4K page. That will ensure that any other
* TLB we create won't interfere with it. We assume that the TLB exists,
* which is why we don't check the Valid bit of MAS1. We also assume
* it is in TLB1.
*
* This is necessary, for example, when booting from the on-chip ROM,
* which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
*/
bl nexti /* Find our address */
nexti: mflr r1 /* R1 = our PC */
li r2, 0
mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
isync
msync
tlbsx 0, r1 /* This must succeed */
mfspr r14, MAS0 /* Save ESEL for later */
rlwinm r14, r14, 16, 0xfff
/* Set the size of the TLB to 4KB */
mfspr r3, MAS1
li r2, 0xF80
andc r3, r3, r2 /* Clear the TSIZE bits */
ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
oris r3, r3, MAS1_IPROT@h
mtspr MAS1, r3
/*
* Set the base address of the TLB to our PC. We assume that
* virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
*/
lis r3, MAS2_EPN@h
ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
and r1, r1, r3 /* Our PC, rounded down to the nearest page */
mfspr r2, MAS2
andc r2, r2, r3
or r2, r2, r1
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
cmpwi r27,0
beq 1f
andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
rlwinm r2, r2, 0, ~MAS2_I
ori r2, r2, MAS2_G
1:
#endif
mtspr MAS2, r2 /* Set the EPN to our PC base address */
mfspr r2, MAS3
andc r2, r2, r3
or r2, r2, r1
mtspr MAS3, r2 /* Set the RPN to our PC base address */
isync
msync
tlbwe
/*
* Clear out any other TLB entries that may exist, to avoid conflicts.
* Our TLB entry is in r14.
*/
li r0, TLBIVAX_ALL | TLBIVAX_TLB0
tlbivax 0, r0
tlbsync
mfspr r4, SPRN_TLB1CFG
rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
li r3, 0
mtspr MAS1, r3
1: cmpw r3, r14
rlwinm r5, r3, 16, MAS0_ESEL_MSK
addi r3, r3, 1
beq 2f /* skip the entry we're executing from */
oris r5, r5, MAS0_TLBSEL(1)@h
mtspr MAS0, r5
isync
tlbwe
isync
msync
2: cmpw r3, r4
blt 1b
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
!defined(CONFIG_SECURE_BOOT)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
* As on debug exception MSR is cleared i.e. Address space is changed
* to 0. A TLB entry (in AS0) is required to handle debug exception generated
* in AS1.
*/
#ifdef NOR_BOOT
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
* and this window is outside of 4K boot window.
*/
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
0, BOOKE_PAGESZ_4M, \
CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#else
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* because "nexti" will resize TLB to 4K
*/
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
0, BOOKE_PAGESZ_256K, \
CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#endif
#endif
/*
* Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
* location is not where we want it. This typically happens on a 36-bit
* system, where we want to move CCSR to near the top of 36-bit address space.
*
* To move CCSR, we create two temporary TLBs, one for the old location, and
* another for the new location. On CoreNet systems, we also need to create
* a special, temporary LAW.
*
* As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
* long-term TLBs, so we use TLB0 here.
*/
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
#endif
create_ccsr_new_tlb:
/*
* Create a TLB for the new location of CCSR. Register R8 is reserved
* for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
*/
lis r8, CONFIG_SYS_CCSRBAR@h
ori r8, r8, CONFIG_SYS_CCSRBAR@l
lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
create_tlb0_entry 0, \
0, BOOKE_PAGESZ_4K, \
CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
/*
* Create a TLB for the current location of CCSR. Register R9 is reserved
* for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
*/
create_ccsr_old_tlb:
create_tlb0_entry 1, \
0, BOOKE_PAGESZ_4K, \
CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
0, r3 /* The default CCSR address is always a 32-bit number */
/*
* We have a TLB for what we think is the current (old) CCSR. Let's
* verify that, otherwise we won't be able to move it.
* CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
* need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
*/
verify_old_ccsr:
lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
#ifdef CONFIG_FSL_CORENET
lwz r1, 4(r9) /* CCSRBARL */
#else
lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
slwi r1, r1, 12
#endif
cmpl 0, r0, r1
/*
* If the value we read from CCSRBARL is not what we expect, then
* enter an infinite loop. This will at least allow a debugger to
* halt execution and examine TLBs, etc. There's no point in going
* on.
*/
infinite_debug_loop:
bne infinite_debug_loop
#ifdef CONFIG_FSL_CORENET
#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
#define LAW_SIZE_4K 0xb
#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
#define CCSRAR_C 0x80000000 /* Commit */
create_temp_law:
/*
* On CoreNet systems, we create the temporary LAW using a special LAW
* target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
*/
lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
lis r2, CCSRBAR_LAWAR@h
ori r2, r2, CCSRBAR_LAWAR@l
stw r0, 0xc00(r9) /* LAWBARH0 */
stw r1, 0xc04(r9) /* LAWBARL0 */
sync
stw r2, 0xc08(r9) /* LAWAR0 */
/*
* Read back from LAWAR to ensure the update is complete. e500mc
* cores also require an isync.
*/
lwz r0, 0xc08(r9) /* LAWAR0 */
isync
/*
* Read the current CCSRBARH and CCSRBARL using load word instructions.
* Follow this with an isync instruction. This forces any outstanding
* accesses to configuration space to completion.
*/
read_old_ccsrbar:
lwz r0, 0(r9) /* CCSRBARH */
lwz r0, 4(r9) /* CCSRBARL */
isync
/*
* Write the new values for CCSRBARH and CCSRBARL to their old
* locations. The CCSRBARH has a shadow register. When the CCSRBARH
* has a new value written it loads a CCSRBARH shadow register. When
* the CCSRBARL is written, the CCSRBARH shadow register contents
* along with the CCSRBARL value are loaded into the CCSRBARH and
* CCSRBARL registers, respectively. Follow this with a sync
* instruction.
*/
write_new_ccsrbar:
lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
lis r2, CCSRAR_C@h
ori r2, r2, CCSRAR_C@l
stw r0, 0(r9) /* Write to CCSRBARH */
sync /* Make sure we write to CCSRBARH first */
stw r1, 4(r9) /* Write to CCSRBARL */
sync
/*
* Write a 1 to the commit bit (C) of CCSRAR at the old location.
* Follow this with a sync instruction.
*/
stw r2, 8(r9)
sync
/* Delete the temporary LAW */
delete_temp_law:
li r1, 0
stw r1, 0xc08(r8)
sync
stw r1, 0xc00(r8)
stw r1, 0xc04(r8)
sync
#else /* #ifdef CONFIG_FSL_CORENET */
write_new_ccsrbar:
/*
* Read the current value of CCSRBAR using a load word instruction
* followed by an isync. This forces all accesses to configuration
* space to complete.
*/
sync
lwz r0, 0(r9)
isync
/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
(CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
/* Write the new value to CCSRBAR. */
lis r0, CCSRBAR_PHYS_RS12@h
ori r0, r0, CCSRBAR_PHYS_RS12@l
stw r0, 0(r9)
sync
/*
* The manual says to perform a load of an address that does not
* access configuration space or the on-chip SRAM using an existing TLB,
* but that doesn't appear to be necessary. We will do the isync,
* though.
*/
isync
/*
* Read the contents of CCSRBAR from its new location, followed by
* another isync.
*/
lwz r0, 0(r8)
isync
#endif /* #ifdef CONFIG_FSL_CORENET */
/* Delete the temporary TLBs */
delete_temp_tlbs:
delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
create_ccsr_l2_tlb:
/*
* Create a TLB for the MMR location of CCSR
* to access L2CSR0 register
*/
create_tlb0_entry 0, \
0, BOOKE_PAGESZ_4K, \
CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
enable_l2_cluster_l2:
/* enable L2 cache */
lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
li r4, 33 /* stash id */
stw r4, 4(r3)
lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
sync
stw r4, 0(r3) /* invalidate L2 */
/* Poll till the bits are cleared */
1: sync
lwz r0, 0(r3)
twi 0, r0, 0
isync
and. r1, r0, r4
bne 1b
/* L2PE must be set before L2 cache is enabled */
lis r4, (L2CSR0_L2PE)@h
ori r4, r4, (L2CSR0_L2PE)@l
sync
stw r4, 0(r3) /* enable L2 parity/ECC error checking */
/* Poll till the bit is set */
1: sync
lwz r0, 0(r3)
twi 0, r0, 0
isync
and. r1, r0, r4
beq 1b
lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
ori r4, r4, (L2CSR0_L2REP_MODE)@l
sync
stw r4, 0(r3) /* enable L2 */
/* Poll till the bit is set */
1: sync
lwz r0, 0(r3)
twi 0, r0, 0
isync
and. r1, r0, r4
beq 1b
delete_ccsr_l2_tlb:
delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
#endif
/*
* Enable the L1. On e6500, this has to be done
* after the L2 is up.
*/
#ifdef CONFIG_SYS_CACHE_STASHING
/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
li r2,(32 + 0)
mtspr L1CSR2,r2
#endif
/* Enable/invalidate the I-Cache */
lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
mtspr SPRN_L1CSR1,r2
1:
mfspr r3,SPRN_L1CSR1
and. r1,r3,r2
bne 1b
lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
mtspr SPRN_L1CSR1,r3
isync
2:
mfspr r3,SPRN_L1CSR1
andi. r1,r3,L1CSR1_ICE@l
beq 2b
/* Enable/invalidate the D-Cache */
lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
mtspr SPRN_L1CSR0,r2
1:
mfspr r3,SPRN_L1CSR0
and. r1,r3,r2
bne 1b
lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
mtspr SPRN_L1CSR0,r3
isync
2:
mfspr r3,SPRN_L1CSR0
andi. r1,r3,L1CSR0_DCE@l
beq 2b
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
#define LAW_SIZE_1M 0x13
#define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
cmpwi r27,0
beq 9f
/*
* Create a TLB entry for CCSR
*
* We're executing out of TLB1 entry in r14, and that's the only
* TLB entry that exists. To allocate some TLB entries for our
* own use, flip a bit high enough that we won't flip it again
* via incrementing.
*/
xori r8, r14, 32
lis r0, MAS0_TLBSEL(1)@h
rlwimi r0, r8, 16, MAS0_ESEL_MSK
lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
lis r7, CONFIG_SYS_CCSRBAR@h
ori r7, r7, CONFIG_SYS_CCSRBAR@l
ori r2, r7, MAS2_I|MAS2_G
lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
mtspr MAS0, r0
mtspr MAS1, r1
mtspr MAS2, r2
mtspr MAS3, r3
mtspr MAS7, r4
isync
tlbwe
isync
msync
/* Map DCSR temporarily to physical address zero */
li r0, 0
lis r3, DCSRBAR_LAWAR@h
ori r3, r3, DCSRBAR_LAWAR@l
stw r0, 0xc00(r7) /* LAWBARH0 */
stw r0, 0xc04(r7) /* LAWBARL0 */
sync
stw r3, 0xc08(r7) /* LAWAR0 */
/* Read back from LAWAR to ensure the update is complete. */
lwz r3, 0xc08(r7) /* LAWAR0 */
isync
/* Create a TLB entry for DCSR at zero */
addi r9, r8, 1
lis r0, MAS0_TLBSEL(1)@h
rlwimi r0, r9, 16, MAS0_ESEL_MSK
lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
li r6, 0 /* DCSR effective address */
ori r2, r6, MAS2_I|MAS2_G
li r3, MAS3_SW|MAS3_SR
li r4, 0
mtspr MAS0, r0
mtspr MAS1, r1
mtspr MAS2, r2
mtspr MAS3, r3
mtspr MAS7, r4
isync
tlbwe
isync
msync
/* enable the timebase */
#define CTBENR 0xe2084
li r3, 1
addis r4, r7, CTBENR@ha
stw r3, CTBENR@l(r4)
lwz r3, CTBENR@l(r4)
twi 0,r3,0
isync
.macro erratum_set_ccsr offset value
addis r3, r7, \offset@ha
lis r4, \value@h
addi r3, r3, \offset@l
ori r4, r4, \value@l
bl erratum_set_value
.endm
.macro erratum_set_dcsr offset value
addis r3, r6, \offset@ha
lis r4, \value@h
addi r3, r3, \offset@l
ori r4, r4, \value@l
bl erratum_set_value
.endm
erratum_set_dcsr 0xb0e08 0xe0201800
erratum_set_dcsr 0xb0e18 0xe0201800
erratum_set_dcsr 0xb0e38 0xe0400000
erratum_set_dcsr 0xb0008 0x00900000
erratum_set_dcsr 0xb0e40 0xe00a0000
erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
#ifdef CONFIG_RAMBOOT_PBL
erratum_set_ccsr 0x10f00 0x495e5000
#else
erratum_set_ccsr 0x10f00 0x415e5000
#endif
erratum_set_ccsr 0x11f00 0x415e5000
/* Make temp mapping uncacheable again, if it was initially */
bl 2f
2: mflr r3
tlbsx 0, r3
mfspr r4, MAS2
rlwimi r4, r15, 0, MAS2_I
rlwimi r4, r15, 0, MAS2_G
mtspr MAS2, r4
isync
tlbwe
isync
msync
/* Clear the cache */
lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
sync
isync
mtspr SPRN_L1CSR1,r3
isync
2: sync
mfspr r4,SPRN_L1CSR1
and. r4,r4,r3
bne 2b
lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
sync
isync
mtspr SPRN_L1CSR1,r3
isync
2: sync
mfspr r4,SPRN_L1CSR1
and. r4,r4,r3
beq 2b
/* Remove temporary mappings */
lis r0, MAS0_TLBSEL(1)@h
rlwimi r0, r9, 16, MAS0_ESEL_MSK
li r3, 0
mtspr MAS0, r0
mtspr MAS1, r3
isync
tlbwe
isync
msync
li r3, 0
stw r3, 0xc08(r7) /* LAWAR0 */
lwz r3, 0xc08(r7)
isync
lis r0, MAS0_TLBSEL(1)@h
rlwimi r0, r8, 16, MAS0_ESEL_MSK
li r3, 0
mtspr MAS0, r0
mtspr MAS1, r3
isync
tlbwe
isync
msync
b 9f
/* r3 = addr, r4 = value, clobbers r5, r11, r12 */
erratum_set_value:
/* Lock two cache lines into I-Cache */
sync
mfspr r11, SPRN_L1CSR1
rlwinm r11, r11, 0, ~L1CSR1_ICUL
sync
isync
mtspr SPRN_L1CSR1, r11
isync
mflr r12
bl 5f
5: mflr r5
addi r5, r5, 2f - 5b
icbtls 0, 0, r5
addi r5, r5, 64
sync
mfspr r11, SPRN_L1CSR1
3: andi. r11, r11, L1CSR1_ICUL
bne 3b
icbtls 0, 0, r5
addi r5, r5, 64
sync
mfspr r11, SPRN_L1CSR1
3: andi. r11, r11, L1CSR1_ICUL
bne 3b
b 2f
.align 6
/* Inside a locked cacheline, wait a while, write, then wait a while */
2: sync
mfspr r5, SPRN_TBRL
addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
4: mfspr r5, SPRN_TBRL
subf. r5, r5, r11
bgt 4b
stw r4, 0(r3)
mfspr r5, SPRN_TBRL
addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
4: mfspr r5, SPRN_TBRL
subf. r5, r5, r11
bgt 4b
sync
/*
* Fill out the rest of this cache line and the next with nops,
* to ensure that nothing outside the locked area will be
* fetched due to a branch.
*/
.rept 19
nop
.endr
sync
mfspr r11, SPRN_L1CSR1
rlwinm r11, r11, 0, ~L1CSR1_ICUL
sync
isync
mtspr SPRN_L1CSR1, r11
isync
mtlr r12
blr
9:
#endif
create_init_ram_area:
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
#ifdef NOR_BOOT
/* create a temp mapping in AS=1 to the 4M boot window */
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_4M, \
CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
/* create a temp mapping in AS = 1 for Flash mapping
* created by PBL for ISBC code
*/
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
/*
* For Targets without CONFIG_SPL like P3, P5
* and for targets with CONFIG_SPL like T1, T2, T4, only for
* u-boot-spl i.e. CONFIG_SPL_BUILD
*/
#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) && \
(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
/* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
* to L3 Address configured by PBL for ISBC code
*/
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#else
/*
* create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
* image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
*/
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#endif
/* create a temp mapping in AS=1 to the stack */
#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
create_tlb1_entry 14, \
1, BOOKE_PAGESZ_16K, \
CONFIG_SYS_INIT_RAM_ADDR, 0, \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
#else
create_tlb1_entry 14, \
1, BOOKE_PAGESZ_16K, \
CONFIG_SYS_INIT_RAM_ADDR, 0, \
CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#endif
lis r6,MSR_IS|MSR_DS|MSR_DE@h
ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
lis r7,switch_as@h
ori r7,r7,switch_as@l
mtspr SPRN_SRR0,r7
mtspr SPRN_SRR1,r6
rfi
switch_as:
/* L1 DCache is used for initial RAM */
/* Allocate Initial RAM in data cache.
*/
lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
mfspr r2, L1CFG0
andi. r2, r2, 0x1ff
/* cache size * 1024 / (2 * L1 line size) */
slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
mtctr r2
li r0,0
1:
dcbz r0,r3
#ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */
dcbtls 2, r0, r3
dcbtls 0, r0, r3
#else
dcbtls 0, r0, r3
#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
/* Jump out the last 4K page and continue to 'normal' start */
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
/* We assume that we're already running at the address we're linked at */
b _start_cont
#else
/* Calculate absolute address in FLASH and jump there */
/*--------------------------------------------------------------*/
lis r3,CONFIG_SYS_MONITOR_BASE@h
ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
addi r3,r3,_start_cont - _start
mtlr r3
blr
#endif
.text
.globl _start
_start:
.long 0x27051956 /* U-BOOT Magic Number */
.globl version_string
version_string:
.ascii U_BOOT_VERSION_STRING, "\0"
.align 4
.globl _start_cont
_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
/* Leave 16+ byte for back chain termination and NULL return address */
subi r3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf)
#endif
/* End of RAM */
lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
li r0,0
1: subi r4,r4,4
stw r0,0(r4)
cmplw r4,r3
bne 1b
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
addi r3,r3,16 /* Pre-relocation malloc area */
stw r3,GD_MALLOC_BASE(r4)
subi r3,r3,16
#endif
li r0,0
stw r0,0(r3) /* Terminate Back Chain */
stw r0,+4(r3) /* NULL return address. */
mr r1,r3 /* Transfer to SP(r1) */
GET_GOT
/* Needed for -msingle-pic-base */
bl _GLOBAL_OFFSET_TABLE_@local-4
mflr r30
/* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
mr r3, r24
bl cpu_init_early_f
/* switch back to AS = 0 */
lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
mtmsr r3
isync
bl cpu_init_f /* return boot_flag for calling board_init_f */
bl board_init_f
isync
/* NOTREACHED - board_init_f() does not return */
#ifndef MINIMAL_SPL
.globl _start_of_vectors
_start_of_vectors:
/* Critical input. */
CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
/* Machine check */
MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. */
STD_EXCEPTION(0x0300, DataStorage, UnknownException)
/* Instruction Storage exception. */
STD_EXCEPTION(0x0400, InstStorage, UnknownException)
/* External Interrupt exception. */
STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
/* Alignment exception. */
Alignment:
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException,
MSR_KERNEL, COPY_EE)
/* Program check exception */
ProgramCheck:
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException,
MSR_KERNEL, COPY_EE)
/* No FPU on MPC85xx. This exception is not supposed to happen.
*/
STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
STD_EXCEPTION(0x0900, SystemCall, UnknownException)
STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
.globl _end_of_vectors
_end_of_vectors:
. = . + (0x100 - ( . & 0xff )) /* align for debug */
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
* Register r21 is pointer into trap frame, r1 has new stack pointer.
* r23 is the address of the handler.
*/
.globl transfer_to_handler
transfer_to_handler:
SAVE_GPR(7, r21)
SAVE_4GPRS(8, r21)
SAVE_8GPRS(12, r21)
SAVE_8GPRS(24, r21)
li r22,0
stw r22,RESULT(r21)
mtspr SPRG2,r22 /* r1 is now kernel sp */
mtctr r23 /* virtual address of handler */
mtmsr r20
bctrl
int_return:
mfmsr r28 /* Disable interrupts */
li r4,0
ori r4,r4,MSR_EE
andc r28,r28,r4
SYNC /* Some chip revs need this... */
mtmsr r28
SYNC
lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
lwz r2,_XER(r1)
lwz r0,_CCR(r1)
mtspr XER,r2
mtcrf 0xFF,r0
REST_10GPRS(3, r1)
REST_10GPRS(13, r1)
REST_8GPRS(23, r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr SRR0,r2
mtspr SRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfi
/* Cache functions.
*/
.globl flush_icache
flush_icache:
.globl invalidate_icache
invalidate_icache:
mfspr r0,L1CSR1
ori r0,r0,L1CSR1_ICFI
msync
isync
mtspr L1CSR1,r0
isync
blr /* entire I cache */
.globl invalidate_dcache
invalidate_dcache:
mfspr r0,L1CSR0
ori r0,r0,L1CSR0_DCFI
msync
isync
mtspr L1CSR0,r0
isync
blr
.globl icache_enable
icache_enable:
mflr r8
bl invalidate_icache
mtlr r8
isync
mfspr r4,L1CSR1
ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
mtspr L1CSR1,r4
isync
blr
.globl icache_disable
icache_disable:
mfspr r0,L1CSR1
lis r3,0
ori r3,r3,L1CSR1_ICE
andc r0,r0,r3
mtspr L1CSR1,r0
isync
blr
.globl icache_status
icache_status:
mfspr r3,L1CSR1
andi. r3,r3,L1CSR1_ICE
blr
.globl dcache_enable
dcache_enable:
mflr r8
bl invalidate_dcache
mtlr r8
isync
mfspr r0,L1CSR0
ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l
oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h
msync
isync
mtspr L1CSR0,r0
isync
blr
.globl dcache_disable
dcache_disable:
mfspr r3,L1CSR0
lis r4,0
ori r4,r4,L1CSR0_DCE
andc r3,r3,r4
mtspr L1CSR0,r3
isync
blr
.globl dcache_status
dcache_status:
mfspr r3,L1CSR0
andi. r3,r3,L1CSR0_DCE
blr
/*------------------------------------------------------------------------------- */
/* Function: in8 */
/* Description: Input 8 bits */
/*------------------------------------------------------------------------------- */
.globl in8
in8:
lbz r3,0x0000(r3)
blr
/*------------------------------------------------------------------------------- */
/* Function: out8 */
/* Description: Output 8 bits */
/*------------------------------------------------------------------------------- */
.globl out8
out8:
stb r4,0x0000(r3)
sync
blr
/*------------------------------------------------------------------------------- */
/* Function: out16 */
/* Description: Output 16 bits */
/*------------------------------------------------------------------------------- */
.globl out16
out16:
sth r4,0x0000(r3)
sync
blr
/*------------------------------------------------------------------------------- */
/* Function: out16r */
/* Description: Byte reverse and output 16 bits */
/*------------------------------------------------------------------------------- */
.globl out16r
out16r:
sthbrx r4,r0,r3
sync
blr
/*------------------------------------------------------------------------------- */
/* Function: out32 */
/* Description: Output 32 bits */
/*------------------------------------------------------------------------------- */
.globl out32
out32:
stw r4,0x0000(r3)
sync
blr
/*------------------------------------------------------------------------------- */
/* Function: out32r */
/* Description: Byte reverse and output 32 bits */
/*------------------------------------------------------------------------------- */
.globl out32r
out32r:
stwbrx r4,r0,r3
sync
blr
/*------------------------------------------------------------------------------- */
/* Function: in16 */
/* Description: Input 16 bits */
/*------------------------------------------------------------------------------- */
.globl in16
in16:
lhz r3,0x0000(r3)
blr
/*------------------------------------------------------------------------------- */
/* Function: in16r */
/* Description: Input 16 bits and byte reverse */
/*------------------------------------------------------------------------------- */
.globl in16r
in16r:
lhbrx r3,r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: in32 */
/* Description: Input 32 bits */
/*------------------------------------------------------------------------------- */
.globl in32
in32:
lwz 3,0x0000(3)
blr
/*------------------------------------------------------------------------------- */
/* Function: in32r */
/* Description: Input 32 bits and byte reverse */
/*------------------------------------------------------------------------------- */
.globl in32r
in32r:
lwbrx r3,r0,r3
blr
#endif /* !MINIMAL_SPL */
/*------------------------------------------------------------------------------*/
/*
* void write_tlb(mas0, mas1, mas2, mas3, mas7)
*/
.globl write_tlb
write_tlb:
mtspr MAS0,r3
mtspr MAS1,r4
mtspr MAS2,r5
mtspr MAS3,r6
#ifdef CONFIG_ENABLE_36BIT_PHYS
mtspr MAS7,r7
#endif
li r3,0
#ifdef CONFIG_SYS_BOOK3E_HV
mtspr MAS8,r3
#endif
isync
tlbwe
msync
isync
blr
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
mr r1,r3 /* Set new stack pointer */
mr r9,r4 /* Save copy of Init Data pointer */
mr r10,r5 /* Save copy of Destination Address */
GET_GOT
#ifndef CONFIG_SPL_SKIP_RELOCATE
mr r3,r5 /* Destination Address */
lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
lwz r5,GOT(__init_end)
sub r5,r5,r4
li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
sub r15,r10,r4
/* First our own GOT */
add r12,r12,r15
/* the the one used by the C code */
add r30,r30,r15
/*
* Now relocate code
*/
cmplw cr1,r3,r4
addi r0,r5,3
srwi. r0,r0,2
beq cr1,4f /* In place copy is not necessary */
beq 7f /* Protect against 0 count */
mtctr r0
bge cr1,2f
la r8,-4(r4)
la r7,-4(r3)
1: lwzu r0,4(r8)
stwu r0,4(r7)
bdnz 1b
b 4f
2: slwi r0,r0,2
add r8,r4,r0
add r7,r3,r0
3: lwzu r0,-4(r8)
stwu r0,-4(r7)
bdnz 3b
/*
* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
*/
4: cmpwi r6,0
add r5,r3,r5
beq 7f /* Always flush prefetch queue in any case */
subi r0,r6,1
andc r3,r3,r0
mr r4,r3
5: dcbst 0,r4
add r4,r4,r6
cmplw r4,r5
blt 5b
sync /* Wait for all dcbst to complete on bus */
mr r4,r3
6: icbi 0,r4
add r4,r4,r6
cmplw r4,r5
blt 6b
7: sync /* Wait for all icbi to complete on bus */
isync
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
addi r0,r10,in_ram - _start
/*
* As IVPR is going to point RAM address,
* Make sure IVOR15 has valid opcode to support debugger
*/
mtspr IVOR15,r0
/*
* Re-point the IVPR at RAM
*/
mtspr IVPR,r10
mtlr r0
blr /* NEVER RETURNS! */
#endif
.globl in_ram
in_ram:
/*
* Relocation Function, r12 point to got2+0x8000
*
* Adjust got2 pointers, no need to check for 0, this code
* already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
lwz r11,GOT(_GOT2_TABLE_)
mtctr r0
sub r11,r3,r11
addi r3,r3,-4
1: lwzu r0,4(r3)
cmpwi r0,0
beq- 2f
add r0,r0,r11
stw r0,0(r3)
2: bdnz 1b
/*
* Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
li r0,__fixup_entries@sectoff@l
lwz r3,GOT(_FIXUP_TABLE_)
cmpwi r0,0
mtctr r0
addi r3,r3,-4
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
cmpwi r0,0
add r0,r0,r11
stw r4,0(r3)
beq- 5f
stw r0,0(r4)
5: bdnz 3b
4:
clear_bss:
/*
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
lwz r4,GOT(__bss_end)
cmplw 0,r3,r4
beq 6f
li r0,0
5:
stw r0,0(r3)
addi r3,r3,4
cmplw 0,r3,r4
blt 5b
6:
mr r3,r9 /* Init Data pointer */
mr r4,r10 /* Destination Address */
bl board_init_r
#ifndef MINIMAL_SPL
/*
* Copy exception vector code to low memory
*
* r3: dest_addr
* r7: source address, r8: end address, r9: target address
*/
.globl trap_init
trap_init:
mflr r11
bl _GLOBAL_OFFSET_TABLE_-4
mflr r12
/* Update IVORs as per relocation */
mtspr IVPR,r3
lwz r4,CriticalInput@got(r12)
mtspr IVOR0,r4 /* 0: Critical input */
lwz r4,MachineCheck@got(r12)
mtspr IVOR1,r4 /* 1: Machine check */
lwz r4,DataStorage@got(r12)
mtspr IVOR2,r4 /* 2: Data storage */
lwz r4,InstStorage@got(r12)
mtspr IVOR3,r4 /* 3: Instruction storage */
lwz r4,ExtInterrupt@got(r12)
mtspr IVOR4,r4 /* 4: External interrupt */
lwz r4,Alignment@got(r12)
mtspr IVOR5,r4 /* 5: Alignment */
lwz r4,ProgramCheck@got(r12)
mtspr IVOR6,r4 /* 6: Program check */
lwz r4,FPUnavailable@got(r12)
mtspr IVOR7,r4 /* 7: floating point unavailable */
lwz r4,SystemCall@got(r12)
mtspr IVOR8,r4 /* 8: System call */
/* 9: Auxiliary processor unavailable(unsupported) */
lwz r4,Decrementer@got(r12)
mtspr IVOR10,r4 /* 10: Decrementer */
lwz r4,IntervalTimer@got(r12)
mtspr IVOR11,r4 /* 11: Interval timer */
lwz r4,WatchdogTimer@got(r12)
mtspr IVOR12,r4 /* 12: Watchdog timer */
lwz r4,DataTLBError@got(r12)
mtspr IVOR13,r4 /* 13: Data TLB error */
lwz r4,InstructionTLBError@got(r12)
mtspr IVOR14,r4 /* 14: Instruction TLB error */
lwz r4,DebugBreakpoint@got(r12)
mtspr IVOR15,r4 /* 15: Debug */
mtlr r11
blr
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
mfspr r4,L1CFG0
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: dcbi r0,r3
#ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */
dcblc 2, r0, r3
dcblc 0, r0, r3
#else
dcblc r0,r3
#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync
/* Invalidate the TLB entries for the cache */
lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
tlbivax 0,r3
addi r3,r3,0x1000
tlbivax 0,r3
addi r3,r3,0x1000
tlbivax 0,r3
addi r3,r3,0x1000
tlbivax 0,r3
isync
blr
.globl flush_dcache
flush_dcache:
mfspr r3,SPRN_L1CFG0
rlwinm r5,r3,9,3 /* Extract cache block size */
twlgti r5,1 /* Only 32 and 64 byte cache blocks
* are currently defined.
*/
li r4,32
subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
* log2(number of ways)
*/
slw r5,r4,r5 /* r5 = cache block size */
rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
mulli r7,r7,13 /* An 8-way cache will require 13
* loads per set.
*/
slw r7,r7,r6
/* save off HID0 and set DCFA */
mfspr r8,SPRN_HID0
ori r9,r8,HID0_DCFA@l
mtspr SPRN_HID0,r9
isync
lis r4,0
mtctr r7
1: lwz r3,0(r4) /* Load... */
add r4,r4,r5
bdnz 1b
msync
lis r4,0
mtctr r7
1: dcbf 0,r4 /* ...and flush. */
add r4,r4,r5
bdnz 1b
/* restore HID0 */
mtspr SPRN_HID0,r8
isync
blr
#endif /* !MINIMAL_SPL */
|
genetel200/u-boot
| 2,902
|
arch/powerpc/cpu/mpc86xx/release.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2004, 2007, 2008 Freescale Semiconductor.
* Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
*/
#include <config.h>
#include <mpc86xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
/* If this is a multi-cpu system then we need to handle the
* 2nd cpu. The assumption is that the 2nd cpu is being
* held in boot holdoff mode until the 1st cpu unlocks it
* from Linux. We'll do some basic cpu init and then pass
* it to the Linux Reset Vector.
* Sri: Much of this initialization is not required. Linux
* rewrites the bats, and the sprs and also enables the L1 cache.
*
* Core 0 must copy this to a 1M aligned region and set BPTR
* to point to it.
*/
.align 12
.globl __secondary_start_page
__secondary_start_page:
.space 0x100 /* space over to reset vector loc */
mfspr r0, MSSCR0
andi. r0, r0, 0x0020
rlwinm r0,r0,27,31,31
mtspr PIR, r0
/* Invalidate BATs */
li r0, 0
mtspr IBAT0U, r0
mtspr IBAT1U, r0
mtspr IBAT2U, r0
mtspr IBAT3U, r0
mtspr IBAT4U, r0
mtspr IBAT5U, r0
mtspr IBAT6U, r0
mtspr IBAT7U, r0
isync
mtspr DBAT0U, r0
mtspr DBAT1U, r0
mtspr DBAT2U, r0
mtspr DBAT3U, r0
mtspr DBAT4U, r0
mtspr DBAT5U, r0
mtspr DBAT6U, r0
mtspr DBAT7U, r0
isync
sync
/* enable extended addressing */
mfspr r0, HID0
lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
mtspr HID0, r0
sync
isync
#ifdef CONFIG_SYS_L2
/* init the L2 cache */
addis r3, r0, L2_INIT@h
ori r3, r3, L2_INIT@l
sync
mtspr l2cr, r3
#ifdef CONFIG_ALTIVEC
dssall
#endif
/* invalidate the L2 cache */
mfspr r3, l2cr
rlwinm. r3, r3, 0, 0, 0
beq 1f
mfspr r3, l2cr
rlwinm r3, r3, 0, 1, 31
#ifdef CONFIG_ALTIVEC
dssall
#endif
sync
mtspr l2cr, r3
sync
1: mfspr r3, l2cr
oris r3, r3, L2CR_L2I@h
mtspr l2cr, r3
invl2:
mfspr r3, l2cr
andis. r3, r3, L2CR_L2I@h
bne invl2
sync
#endif
/* enable and invalidate the data cache */
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
andc r3, r3, r5
mtspr HID0, r3 /* no invalidate, unlock */
ori r3, r3, HID0_DCE
ori r5, r3, HID0_DCFI
mtspr HID0, r5 /* enable + invalidate */
mtspr HID0, r3 /* enable */
sync
#ifdef CONFIG_SYS_L2
sync
lis r3, L2_ENABLE@h
ori r3, r3, L2_ENABLE@l
mtspr l2cr, r3
isync
sync
#endif
/* enable and invalidate the instruction cache*/
mfspr r3, HID0
li r5, HID0_ICFI|HID0_ILOCK
andc r3, r3, r5
ori r3, r3, HID0_ICE
ori r5, r3, HID0_ICFI
mtspr HID0, r5
mtspr HID0, r3
isync
sync
/* TBEN in HID0 */
mfspr r4, HID0
oris r4, r4, 0x0400
mtspr HID0, r4
sync
isync
/* MCP|SYNCBE|ABE in HID1 */
mfspr r4, HID1
oris r4, r4, 0x8000
ori r4, r4, 0x0C00
mtspr HID1, r4
sync
isync
lis r3, CONFIG_LINUX_RESET_VEC@h
ori r3, r3, CONFIG_LINUX_RESET_VEC@l
mtlr r3
blr
/* Never Returns, Running in Linux Now */
|
genetel200/u-boot
| 20,353
|
arch/powerpc/cpu/mpc86xx/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2004, 2007, 2011 Freescale Semiconductor.
* Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
*/
/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
*
*
* The processor starts at 0xfff00100 and the code is executed
* from flash. The code is organized to be at an other address
* in memory, but as long we don't jump around before relocating.
* board_init lies at a quite high address and when the cpu has
* jumped there, everything is ok.
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc86xx.h>
#include <version.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/u-boot.h>
/*
* Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
*/
/*
* Set up GOT: Global Offset Table
*
* Use r12 to access the GOT
*/
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
/*
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
.ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
_start:
b boot_cold
/* the boot code is located below the exception table */
.globl _start_of_vectors
_start_of_vectors:
/* Machine check */
STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. */
STD_EXCEPTION(0x300, DataStorage, UnknownException)
/* Instruction Storage exception. */
STD_EXCEPTION(0x400, InstStorage, UnknownException)
/* External Interrupt exception. */
STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
MSR_KERNEL, COPY_EE)
STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
/* I guess we could implement decrementer, and may have
* to someday for timekeeping.
*/
STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
STD_EXCEPTION(0xc00, SystemCall, UnknownException)
STD_EXCEPTION(0xd00, SingleStep, UnknownException)
STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
STD_EXCEPTION(0x1500, Reserved5, UnknownException)
STD_EXCEPTION(0x1600, Reserved6, UnknownException)
STD_EXCEPTION(0x1700, Reserved7, UnknownException)
STD_EXCEPTION(0x1800, Reserved8, UnknownException)
STD_EXCEPTION(0x1900, Reserved9, UnknownException)
STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
.globl _end_of_vectors
_end_of_vectors:
. = 0x2000
boot_cold:
/*
* NOTE: Only Cpu 0 will ever come here. Other cores go to an
* address specified by the BPTR
*/
1:
#ifdef CONFIG_SYS_RAMBOOT
/* disable everything */
li r0, 0
mtspr HID0, r0
sync
mtmsr 0
#endif
/* Invalidate BATs */
bl invalidate_bats
sync
/* Invalidate all of TLB before MMU turn on */
bl clear_tlbs
sync
#ifdef CONFIG_SYS_L2
/* init the L2 cache */
lis r3, L2_INIT@h
ori r3, r3, L2_INIT@l
mtspr l2cr, r3
/* invalidate the L2 cache */
bl l2cache_invalidate
sync
#endif
/*
* Calculate absolute address in FLASH and jump there
*------------------------------------------------------*/
lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
in_flash:
/* let the C-code set up the rest */
/* */
/* Be careful to keep code relocatable ! */
/*------------------------------------------------------*/
/* perform low-level init */
/* enable extended addressing */
bl enable_ext_addr
/* setup the bats */
bl early_bats
/*
* Cache must be enabled here for stack-in-cache trick.
* This means we need to enable the BATS.
* Cache should be turned on after BATs, since by default
* everything is write-through.
*/
/* enable address translation */
mfmsr r5
ori r5, r5, (MSR_IR | MSR_DR)
lis r3,addr_trans_enabled@h
ori r3, r3, addr_trans_enabled@l
mtspr SPRN_SRR0,r3
mtspr SPRN_SRR1,r5
rfi
addr_trans_enabled:
/* enable and invalidate the data cache */
/* bl l1dcache_enable */
bl dcache_enable
sync
#if 1
bl icache_enable
#endif
#ifdef CONFIG_SYS_INIT_RAM_LOCK
bl lock_ram_in_cache
sync
#endif
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
bl setup_ccsrbar
#endif
/* set up the stack pointer in our newly created
* cache-ram (r1) */
lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
GET_GOT /* initialize GOT access */
/* run low-level CPU init code (from Flash) */
bl cpu_init_f
sync
#ifdef RUN_DIAG
/* Load PX_AUX register address in r4 */
lis r4, PIXIS_BASE@h
ori r4, r4, 0x6
/* Load contents of PX_AUX in r3 bits 24 to 31*/
lbz r3, 0(r4)
/* Mask and obtain the bit in r3 */
rlwinm. r3, r3, 0, 24, 24
/* If not zero, jump and continue with u-boot */
bne diag_done
/* Load back contents of PX_AUX in r3 bits 24 to 31 */
lbz r3, 0(r4)
/* Set the MSB of the register value */
ori r3, r3, 0x80
/* Write value in r3 back to PX_AUX */
stb r3, 0(r4)
/* Get the address to jump to in r3*/
lis r3, CONFIG_SYS_DIAG_ADDR@h
ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
/* Load the LR with the branch address */
mtlr r3
/* Branch to diagnostic */
blr
diag_done:
#endif
/* bl l2cache_enable */
/* run 1st part of board init code (from Flash) */
li r3, 0 /* clear boot_flag for calling board_init_f */
bl board_init_f
sync
/* NOTREACHED - board_init_f() does not return */
.globl invalidate_bats
invalidate_bats:
li r0, 0
/* invalidate BATs */
mtspr IBAT0U, r0
mtspr IBAT1U, r0
mtspr IBAT2U, r0
mtspr IBAT3U, r0
mtspr IBAT4U, r0
mtspr IBAT5U, r0
mtspr IBAT6U, r0
mtspr IBAT7U, r0
isync
mtspr DBAT0U, r0
mtspr DBAT1U, r0
mtspr DBAT2U, r0
mtspr DBAT3U, r0
mtspr DBAT4U, r0
mtspr DBAT5U, r0
mtspr DBAT6U, r0
mtspr DBAT7U, r0
isync
sync
blr
#define CONFIG_BAT_PAIR(n) \
lis r4, CONFIG_SYS_IBAT##n##L@h; \
ori r4, r4, CONFIG_SYS_IBAT##n##L@l; \
lis r3, CONFIG_SYS_IBAT##n##U@h; \
ori r3, r3, CONFIG_SYS_IBAT##n##U@l; \
mtspr IBAT##n##L, r4; \
mtspr IBAT##n##U, r3; \
lis r4, CONFIG_SYS_DBAT##n##L@h; \
ori r4, r4, CONFIG_SYS_DBAT##n##L@l; \
lis r3, CONFIG_SYS_DBAT##n##U@h; \
ori r3, r3, CONFIG_SYS_DBAT##n##U@l; \
mtspr DBAT##n##L, r4; \
mtspr DBAT##n##U, r3;
/*
* setup_bats:
*
* Set up the final BAT registers now that setup is done.
*
* Assumes that:
* 1) Address translation is enabled upon entry
* 2) The boot rom is still accessible via 1:1 translation
*/
.globl setup_bats
setup_bats:
mflr r5
sync
/*
* When we disable address translation, we will get 1:1 (VA==PA)
* translation. The only place we know for sure is safe for that is
* the bootrom where we originally started out. Pop back into there.
*/
lis r4, CONFIG_SYS_MONITOR_BASE_EARLY@h
ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY@l
addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET
/* disable address translation */
mfmsr r3
rlwinm r3, r3, 0, 28, 25
mtspr SRR0, r4
mtspr SRR1, r3
rfi
trans_disabled:
#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \
&& defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
CONFIG_BAT_PAIR(0)
#endif
CONFIG_BAT_PAIR(1)
CONFIG_BAT_PAIR(2)
CONFIG_BAT_PAIR(3)
CONFIG_BAT_PAIR(4)
CONFIG_BAT_PAIR(5)
CONFIG_BAT_PAIR(6)
CONFIG_BAT_PAIR(7)
sync
isync
/* Turn translation back on and return */
mfmsr r3
ori r3, r3, (MSR_IR | MSR_DR)
mtspr SPRN_SRR0,r5
mtspr SPRN_SRR1,r3
rfi
/*
* early_bats:
*
* Set up bats needed early on - this is usually the BAT for the
* stack-in-cache, the Flash, and CCSR space
*/
.globl early_bats
early_bats:
/* IBAT 3 */
lis r4, CONFIG_SYS_IBAT3L@h
ori r4, r4, CONFIG_SYS_IBAT3L@l
lis r3, CONFIG_SYS_IBAT3U@h
ori r3, r3, CONFIG_SYS_IBAT3U@l
mtspr IBAT3L, r4
mtspr IBAT3U, r3
isync
/* DBAT 3 */
lis r4, CONFIG_SYS_DBAT3L@h
ori r4, r4, CONFIG_SYS_DBAT3L@l
lis r3, CONFIG_SYS_DBAT3U@h
ori r3, r3, CONFIG_SYS_DBAT3U@l
mtspr DBAT3L, r4
mtspr DBAT3U, r3
isync
/* IBAT 5 */
lis r4, CONFIG_SYS_IBAT5L@h
ori r4, r4, CONFIG_SYS_IBAT5L@l
lis r3, CONFIG_SYS_IBAT5U@h
ori r3, r3, CONFIG_SYS_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
isync
/* DBAT 5 */
lis r4, CONFIG_SYS_DBAT5L@h
ori r4, r4, CONFIG_SYS_DBAT5L@l
lis r3, CONFIG_SYS_DBAT5U@h
ori r3, r3, CONFIG_SYS_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
isync
/* IBAT 6 */
lis r4, CONFIG_SYS_IBAT6L_EARLY@h
ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
lis r3, CONFIG_SYS_IBAT6U_EARLY@h
ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
isync
/* DBAT 6 */
lis r4, CONFIG_SYS_DBAT6L_EARLY@h
ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
lis r3, CONFIG_SYS_DBAT6U_EARLY@h
ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
isync
#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
/* IBAT 7 */
lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
mtspr IBAT7L, r4
mtspr IBAT7U, r3
isync
/* DBAT 7 */
lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
mtspr DBAT7L, r4
mtspr DBAT7U, r3
isync
#endif
blr
.globl clear_tlbs
clear_tlbs:
addis r3, 0, 0x0000
addis r5, 0, 0x4
isync
tlblp:
tlbie r3
sync
addi r3, r3, 0x1000
cmp 0, 0, r3, r5
blt tlblp
blr
.globl disable_addr_trans
disable_addr_trans:
/* disable address translation */
mflr r4
mfmsr r3
andi. r0, r3, (MSR_IR | MSR_DR)
beqlr
andc r3, r3, r0
mtspr SRR0, r4
mtspr SRR1, r3
rfi
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
* Register r21 is pointer into trap frame, r1 has new stack pointer.
*/
.globl transfer_to_handler
transfer_to_handler:
stw r22,_NIP(r21)
lis r22,MSR_POW@h
andc r23,r23,r22
stw r23,_MSR(r21)
SAVE_GPR(7, r21)
SAVE_4GPRS(8, r21)
SAVE_8GPRS(12, r21)
SAVE_8GPRS(24, r21)
mflr r23
andi. r24,r23,0x3f00 /* get vector offset */
stw r24,TRAP(r21)
li r22,0
stw r22,RESULT(r21)
mtspr SPRG2,r22 /* r1 is now kernel sp */
lwz r24,0(r23) /* virtual address of handler */
lwz r23,4(r23) /* where to go when done */
mtspr SRR0,r24
mtspr SRR1,r20
mtlr r23
SYNC
rfi /* jump to handler, enable MMU */
int_return:
mfmsr r28 /* Disable interrupts */
li r4,0
ori r4,r4,MSR_EE
andc r28,r28,r4
SYNC /* Some chip revs need this... */
mtmsr r28
SYNC
lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
lwz r2,_XER(r1)
lwz r0,_CCR(r1)
mtspr XER,r2
mtcrf 0xFF,r0
REST_10GPRS(3, r1)
REST_10GPRS(13, r1)
REST_8GPRS(23, r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr SRR0,r2
mtspr SRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfi
.globl dc_read
dc_read:
blr
/*
* Function: in8
* Description: Input 8 bits
*/
.globl in8
in8:
lbz r3,0x0000(r3)
blr
/*
* Function: out8
* Description: Output 8 bits
*/
.globl out8
out8:
stb r4,0x0000(r3)
blr
/*
* Function: out16
* Description: Output 16 bits
*/
.globl out16
out16:
sth r4,0x0000(r3)
blr
/*
* Function: out16r
* Description: Byte reverse and output 16 bits
*/
.globl out16r
out16r:
sthbrx r4,r0,r3
blr
/*
* Function: out32
* Description: Output 32 bits
*/
.globl out32
out32:
stw r4,0x0000(r3)
blr
/*
* Function: out32r
* Description: Byte reverse and output 32 bits
*/
.globl out32r
out32r:
stwbrx r4,r0,r3
blr
/*
* Function: in16
* Description: Input 16 bits
*/
.globl in16
in16:
lhz r3,0x0000(r3)
blr
/*
* Function: in16r
* Description: Input 16 bits and byte reverse
*/
.globl in16r
in16r:
lhbrx r3,r0,r3
blr
/*
* Function: in32
* Description: Input 32 bits
*/
.globl in32
in32:
lwz 3,0x0000(3)
blr
/*
* Function: in32r
* Description: Input 32 bits and byte reverse
*/
.globl in32r
in32r:
lwbrx r3,r0,r3
blr
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Global Data pointer */
mr r10, r5 /* Save copy of Destination Address */
GET_GOT
mr r3, r5 /* Destination Address */
lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
sub r15, r10, r4
/* First our own GOT */
add r12, r12, r15
/* then the one used by the C code */
add r30, r30, r15
/*
* Now relocate code
*/
cmplw cr1,r3,r4
addi r0,r5,3
srwi. r0,r0,2
beq cr1,4f /* In place copy is not necessary */
beq 7f /* Protect against 0 count */
mtctr r0
bge cr1,2f
la r8,-4(r4)
la r7,-4(r3)
1: lwzu r0,4(r8)
stwu r0,4(r7)
bdnz 1b
b 4f
2: slwi r0,r0,2
add r8,r4,r0
add r7,r3,r0
3: lwzu r0,-4(r8)
stwu r0,-4(r7)
bdnz 3b
/*
* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
*/
4: cmpwi r6,0
add r5,r3,r5
beq 7f /* Always flush prefetch queue in any case */
subi r0,r6,1
andc r3,r3,r0
mr r4,r3
5: dcbst 0,r4
add r4,r4,r6
cmplw r4,r5
blt 5b
sync /* Wait for all dcbst to complete on bus */
mr r4,r3
6: icbi 0,r4
add r4,r4,r6
cmplw r4,r5
blt 6b
7: sync /* Wait for all icbi to complete on bus */
isync
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
mtlr r0
blr
in_ram:
/*
* Relocation Function, r12 point to got2+0x8000
*
* Adjust got2 pointers, no need to check for 0, this code
* already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
lwz r11,GOT(_GOT2_TABLE_)
mtctr r0
sub r11,r3,r11
addi r3,r3,-4
1: lwzu r0,4(r3)
cmpwi r0,0
beq- 2f
add r0,r0,r11
stw r0,0(r3)
2: bdnz 1b
/*
* Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
li r0,__fixup_entries@sectoff@l
lwz r3,GOT(_FIXUP_TABLE_)
cmpwi r0,0
mtctr r0
addi r3,r3,-4
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
cmpwi r0,0
add r0,r0,r11
stw r4,0(r3)
beq- 5f
stw r0,0(r4)
5: bdnz 3b
4:
/* clear_bss: */
/*
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
li r0, 0
5:
stw r0, 0(r3)
addi r3, r3, 4
cmplw 0, r3, r4
bne 5b
6:
mr r3, r9 /* Init Date pointer */
mr r4, r10 /* Destination Address */
bl board_init_r
/* not reached - end relocate_code */
/*-----------------------------------------------------------------------*/
/*
* Copy exception vector code to low memory
*
* r3: dest_addr
* r7: source address, r8: end address, r9: target address
*/
.globl trap_init
trap_init:
mflr r4 /* save link register */
GET_GOT
lwz r7, GOT(_start)
lwz r8, GOT(_end_of_vectors)
li r9, 0x100 /* reset vector always at 0x100 */
cmplw 0, r7, r8
bgelr /* return if r7>=r8 - just in case */
1:
lwz r0, 0(r7)
stw r0, 0(r9)
addi r7, r7, 4
addi r9, r9, 4
cmplw 0, r7, r8
bne 1b
/*
* relocate `hdlr' and `int_return' entries
*/
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
li r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 2b
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 3b
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 4b
/* enable execptions from RAM vectors */
mfmsr r7
li r8,MSR_IP
andc r7,r7,r8
ori r7,r7,MSR_ME /* Enable Machine Check */
mtmsr r7
mtlr r4 /* restore link register */
blr
.globl enable_ext_addr
enable_ext_addr:
mfspr r0, HID0
lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
mtspr HID0, r0
sync
isync
blr
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
.globl setup_ccsrbar
setup_ccsrbar:
/* Special sequence needed to update CCSRBAR itself */
lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
srwi r5,r5,12
li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
rlwimi r5,r6,20,8,11
stw r5, 0(r4) /* Store physical value of CCSR */
isync
lis r5, CONFIG_SYS_TEXT_BASE@h
ori r5,r5,CONFIG_SYS_TEXT_BASE@l
lwz r5, 0(r5)
isync
/* Use VA of CCSR to do read */
lis r3, CONFIG_SYS_CCSRBAR@h
lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
isync
blr
#endif
#ifdef CONFIG_SYS_INIT_RAM_LOCK
lock_ram_in_cache:
/* Allocate Initial RAM in data cache.
*/
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
dcbz r0, r3
addi r3, r3, 32
bdnz 1b
#if 1
/* Lock the data cache */
mfspr r0, HID0
ori r0, r0, 0x1000
sync
mtspr HID0, r0
sync
blr
#endif
#if 0
/* Lock the first way of the data cache */
mfspr r0, LDSTCR
ori r0, r0, 0x0080
#if defined(CONFIG_ALTIVEC)
dssall
#endif
sync
mtspr LDSTCR, r0
sync
isync
blr
#endif
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1: icbi r0, r3
addi r3, r3, 32
bdnz 1b
sync /* Wait for all icbi to complete on bus */
isync
#if 1
/* Unlock the data cache and invalidate it */
mfspr r0, HID0
li r3,0x1000
andc r0,r0,r3
li r3,0x0400
or r0,r0,r3
sync
mtspr HID0, r0
sync
blr
#endif
#if 0
/* Unlock the first way of the data cache */
mfspr r0, LDSTCR
li r3,0x0080
andc r0,r0,r3
#ifdef CONFIG_ALTIVEC
dssall
#endif
sync
mtspr LDSTCR, r0
sync
isync
li r3,0x0400
or r0,r0,r3
sync
mtspr HID0, r0
sync
blr
#endif
#endif
|
genetel200/u-boot
| 6,507
|
arch/powerpc/cpu/mpc86xx/cache.S
|
#include <config.h>
#include <mpc86xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#ifndef CACHE_LINE_SIZE
# define CACHE_LINE_SIZE L1_CACHE_BYTES
#endif
#if CACHE_LINE_SIZE == 128
#define LG_CACHE_LINE_SIZE 7
#elif CACHE_LINE_SIZE == 32
#define LG_CACHE_LINE_SIZE 5
#elif CACHE_LINE_SIZE == 16
#define LG_CACHE_LINE_SIZE 4
#elif CACHE_LINE_SIZE == 8
#define LG_CACHE_LINE_SIZE 3
#else
# error "Invalid cache line size!"
#endif
/*
* Most of this code is taken from 74xx_7xx/cache.S
* and then cleaned up a bit
*/
/*
* Invalidate L1 instruction cache.
*/
_GLOBAL(invalidate_l1_instruction_cache)
/* use invalidate-all bit in HID0 */
mfspr r3,HID0
ori r3,r3,HID0_ICFI
mtspr HID0,r3
isync
blr
/*
* Invalidate L1 data cache.
*/
_GLOBAL(invalidate_l1_data_cache)
mfspr r3,HID0
ori r3,r3,HID0_DCFI
mtspr HID0,r3
isync
blr
/*
* Flush data cache.
*/
_GLOBAL(flush_dcache)
lis r3,0
lis r5,CACHE_LINE_SIZE
flush:
cmp 0,1,r3,r5
bge done
lwz r5,0(r3)
lis r5,CACHE_LINE_SIZE
addi r3,r3,0x4
b flush
done:
blr
/*
* Write any modified data cache blocks out to memory
* and invalidate the corresponding instruction cache blocks.
* This is a no-op on the 601.
*
* flush_icache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_icache_range)
li r5,CACHE_LINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,LG_CACHE_LINE_SIZE
beqlr
mtctr r4
mr r6,r3
1: dcbst 0,r3
addi r3,r3,CACHE_LINE_SIZE
bdnz 1b
sync /* wait for dcbst's to get to ram */
mtctr r4
2: icbi 0,r6
addi r6,r6,CACHE_LINE_SIZE
bdnz 2b
sync /* additional sync needed on g4 */
isync
blr
/*
* Write any modified data cache blocks out to memory.
* Does not invalidate the corresponding cache lines (especially for
* any corresponding instruction cache).
*
* clean_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(clean_dcache_range)
li r5,CACHE_LINE_SIZE-1
andc r3,r3,r5 /* align r3 down to cache line */
subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
add r4,r4,r5 /* r4 += cache_line_size-1 */
srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
beqlr /* if r4 == 0 return */
mtctr r4 /* ctr = r4 */
sync
1: dcbst 0,r3
addi r3,r3,CACHE_LINE_SIZE
bdnz 1b
sync /* wait for dcbst's to get to ram */
blr
/*
* Flush a particular page from the data cache to RAM.
* Note: this is necessary because the instruction cache does *not*
* snoop from the data cache.
*
* void __flush_page_to_ram(void *page)
*/
_GLOBAL(__flush_page_to_ram)
rlwinm r3,r3,0,0,19 /* Get page base address */
li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
mtctr r4
mr r6,r3
0: dcbst 0,r3 /* Write line to ram */
addi r3,r3,CACHE_LINE_SIZE
bdnz 0b
sync
mtctr r4
1: icbi 0,r6
addi r6,r6,CACHE_LINE_SIZE
bdnz 1b
sync
isync
blr
/*
* Flush a particular page from the instruction cache.
* Note: this is necessary because the instruction cache does *not*
* snoop from the data cache.
*
* void __flush_icache_page(void *page)
*/
_GLOBAL(__flush_icache_page)
li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
mtctr r4
1: icbi 0,r3
addi r3,r3,CACHE_LINE_SIZE
bdnz 1b
sync
isync
blr
/*
* Clear a page using the dcbz instruction, which doesn't cause any
* memory traffic (except to write out any cache lines which get
* displaced). This only works on cacheable memory.
*/
_GLOBAL(clear_page)
li r0,4096/CACHE_LINE_SIZE
mtctr r0
1: dcbz 0,r3
addi r3,r3,CACHE_LINE_SIZE
bdnz 1b
blr
/*
* Enable L1 Instruction cache
*/
_GLOBAL(icache_enable)
mfspr r3, HID0
li r5, HID0_ICFI|HID0_ILOCK
andc r3, r3, r5
ori r3, r3, HID0_ICE
ori r5, r3, HID0_ICFI
mtspr HID0, r5
mtspr HID0, r3
isync
blr
/*
* Disable L1 Instruction cache
*/
_GLOBAL(icache_disable)
mflr r4
bl invalidate_l1_instruction_cache /* uses r3 */
sync
mtlr r4
mfspr r3, HID0
li r5, 0
ori r5, r5, HID0_ICE
andc r3, r3, r5
mtspr HID0, r3
isync
blr
/*
* Is instruction cache enabled?
*/
_GLOBAL(icache_status)
mfspr r3, HID0
andi. r3, r3, HID0_ICE
blr
_GLOBAL(l1dcache_enable)
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
andc r3, r3, r5
mtspr HID0, r3 /* no invalidate, unlock */
ori r3, r3, HID0_DCE
ori r5, r3, HID0_DCFI
mtspr HID0, r5 /* enable + invalidate */
mtspr HID0, r3 /* enable */
sync
blr
/*
* Enable data cache(s) - L1 and optionally L2
* Calls l2cache_enable. LR saved in r5
*/
_GLOBAL(dcache_enable)
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
andc r3, r3, r5
mtspr HID0, r3 /* no invalidate, unlock */
ori r3, r3, HID0_DCE
ori r5, r3, HID0_DCFI
mtspr HID0, r5 /* enable + invalidate */
mtspr HID0, r3 /* enable */
sync
#ifdef CONFIG_SYS_L2
mflr r5
bl l2cache_enable /* uses r3 and r4 */
sync
mtlr r5
#endif
blr
/*
* Disable data cache(s) - L1 and optionally L2
* Calls flush_dcache and l2cache_disable_no_flush.
* LR saved in r4
*/
_GLOBAL(dcache_disable)
mflr r4 /* save link register */
bl flush_dcache /* uses r3 and r5 */
sync
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
andc r3, r3, r5
mtspr HID0, r3 /* no invalidate, unlock */
li r5, HID0_DCE|HID0_DCFI
andc r3, r3, r5 /* no enable, no invalidate */
mtspr HID0, r3
sync
#ifdef CONFIG_SYS_L2
bl l2cache_disable_no_flush /* uses r3 */
#endif
mtlr r4 /* restore link register */
blr
/*
* Is data cache enabled?
*/
_GLOBAL(dcache_status)
mfspr r3, HID0
andi. r3, r3, HID0_DCE
blr
/*
* Invalidate L2 cache using L2I, assume L2 is enabled
*/
_GLOBAL(l2cache_invalidate)
mfspr r3, l2cr
rlwinm. r3, r3, 0, 0, 0
beq 1f
mfspr r3, l2cr
rlwinm r3, r3, 0, 1, 31
#ifdef CONFIG_ALTIVEC
dssall
#endif
sync
mtspr l2cr, r3
sync
1: mfspr r3, l2cr
oris r3, r3, L2CR_L2I@h
mtspr l2cr, r3
invl2:
mfspr r3, l2cr
andis. r3, r3, L2CR_L2I@h
bne invl2
blr
/*
* Enable L2 cache
* Calls l2cache_invalidate. LR is saved in r4
*/
_GLOBAL(l2cache_enable)
mflr r4 /* save link register */
bl l2cache_invalidate /* uses r3 */
sync
lis r3, L2_ENABLE@h
ori r3, r3, L2_ENABLE@l
mtspr l2cr, r3
isync
mtlr r4 /* restore link register */
blr
/*
* Disable L2 cache
* Calls flush_dcache. LR is saved in r4
*/
_GLOBAL(l2cache_disable)
mflr r4 /* save link register */
bl flush_dcache /* uses r3 and r5 */
sync
mtlr r4 /* restore link register */
l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
lis r3, L2_INIT@h
ori r3, r3, L2_INIT@l
mtspr l2cr, r3
isync
blr
|
genetel200/u-boot
| 7,750
|
arch/microblaze/cpu/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2007 Michal Simek
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Michal SIMEK <monstr@monstr.eu>
* Yasushi SHOJI <yashi@atmark-techno.com>
*/
#include <asm-offsets.h>
#include <config.h>
.text
.global _start
_start:
/*
* reserve registers:
* r10: Stores little/big endian offset for vectors
* r2: Stores imm opcode
* r3: Stores brai opcode
*/
mts rmsr, r0 /* disable cache */
addi r8, r0, __end
mts rslr, r8
/* TODO: Redo this code to call board_init_f_*() */
#if defined(CONFIG_SPL_BUILD)
addi r1, r0, CONFIG_SPL_STACK_ADDR
mts rshr, r1
addi r1, r1, -4 /* Decrement SP to top of memory */
#else
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_VAL(SYS_MALLOC_F_LEN)
#else
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
#endif
mts rshr, r1
addi r1, r1, -4 /* Decrement SP to top of memory */
/* Find-out if u-boot is running on BIG/LITTLE endian platform
* There are some steps which is necessary to keep in mind:
* 1. Setup offset value to r6
* 2. Store word offset value to address 0x0
* 3. Load just byte from address 0x0
* 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
* value that's why is on address 0x0
* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
*/
addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
lwi r7, r0, 0x28
swi r6, r0, 0x28 /* used first unused MB vector */
lbui r10, r0, 0x28 /* used first unused MB vector */
swi r7, r0, 0x28
/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
#ifdef CONFIG_SYS_RESET_ADDRESS
/* reset address */
swi r2, r0, 0x0 /* reset address - imm opcode */
swi r3, r0, 0x4 /* reset address - brai opcode */
addik r6, r0, CONFIG_SYS_RESET_ADDRESS
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x2
sh r7, r0, r8
rsubi r8, r10, 0x6
sh r6, r0, r8
#endif
#ifdef CONFIG_SYS_USR_EXCEP
/* user_vector_exception */
swi r2, r0, 0x8 /* user vector exception - imm opcode */
swi r3, r0, 0xC /* user vector exception - brai opcode */
addik r6, r0, _exception_handler
sw r6, r1, r0
/*
* BIG ENDIAN memory map for user exception
* 0x8: 0xB000XXXX
* 0xC: 0xB808XXXX
*
* then it is necessary to count address for storing the most significant
* 16bits from _exception_handler address and copy it to
* 0xa address. Big endian use offset in r10=0 that's why is it just
* 0xa address. The same is done for the least significant 16 bits
* for 0xe address.
*
* LITTLE ENDIAN memory map for user exception
* 0x8: 0xXXXX00B0
* 0xC: 0xXXXX08B8
*
* Offset is for little endian setup to 0x2. rsubi instruction decrease
* address value to ensure that points to proper place which is
* 0x8 for the most significant 16 bits and
* 0xC for the least significant 16 bits
*/
lhu r7, r1, r10
rsubi r8, r10, 0xa
sh r7, r0, r8
rsubi r8, r10, 0xe
sh r6, r0, r8
#endif
/* interrupt_handler */
swi r2, r0, 0x10 /* interrupt - imm opcode */
swi r3, r0, 0x14 /* interrupt - brai opcode */
addik r6, r0, _interrupt_handler
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x12
sh r7, r0, r8
rsubi r8, r10, 0x16
sh r6, r0, r8
/* hardware exception */
swi r2, r0, 0x20 /* hardware exception - imm opcode */
swi r3, r0, 0x24 /* hardware exception - brai opcode */
addik r6, r0, _hw_exception_handler
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x22
sh r7, r0, r8
rsubi r8, r10, 0x26
sh r6, r0, r8
#endif /* CONFIG_SPL_BUILD */
/* Flush cache before enable cache */
addik r5, r0, 0
addik r6, r0, XILINX_DCACHE_BYTE_SIZE
bralid r15, flush_cache
nop
/* enable instruction and data cache */
mfs r12, rmsr
ori r12, r12, 0x1a0
mts rmsr, r12
/* TODO: Redo this code to call board_init_f_*() */
clear_bss:
/* clear BSS segments */
addi r5, r0, __bss_start
addi r4, r0, __bss_end
cmp r6, r5, r4
beqi r6, 3f
2:
swi r0, r5, 0 /* write zero to loc */
addi r5, r5, 4 /* increment to next loc */
cmp r6, r5, r4 /* check if we have reach the end */
bnei r6, 2b
3: /* jumping to board_init */
#ifdef CONFIG_DEBUG_UART
bralid r15, debug_uart_init
nop
#endif
#ifndef CONFIG_SPL_BUILD
or r5, r0, r0 /* flags - empty */
addi r31, r0, _gd
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
addi r6, r0, CONFIG_SYS_INIT_SP_OFFSET
swi r6, r31, GD_MALLOC_BASE
#endif
brai board_init_f
#else
addi r31, r0, _gd
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
addi r6, r0, CONFIG_SPL_STACK_ADDR
swi r6, r31, GD_MALLOC_BASE
#endif
brai board_init_r
#endif
1: bri 1b
.section .bss
.align 4
_gd:
.space GENERATED_GBL_DATA_SIZE
#ifndef CONFIG_SPL_BUILD
/*
* Read 16bit little endian
*/
.text
.global in16
.ent in16
.align 2
in16: lhu r3, r0, r5
bslli r4, r3, 8
bsrli r3, r3, 8
andi r4, r4, 0xffff
or r3, r3, r4
rtsd r15, 8
sext16 r3, r3
.end in16
/*
* Write 16bit little endian
* first parameter(r5) - address, second(r6) - short value
*/
.text
.global out16
.ent out16
.align 2
out16: bslli r3, r6, 8
bsrli r6, r6, 8
andi r3, r3, 0xffff
or r3, r3, r6
sh r3, r0, r5
rtsd r15, 8
or r0, r0, r0
.end out16
/*
* Relocate u-boot
*/
.text
.global relocate_code
.ent relocate_code
.align 2
relocate_code:
/*
* r5 - start_addr_sp
* r6 - new_gd
* r7 - reloc_addr
*/
addi r1, r5, 0 /* Start to use new SP */
addi r31, r6, 0 /* Start to use new GD */
add r23, r0, r7 /* Move reloc addr to r23 */
/* Relocate text and data - r12 temp value */
addi r21, r0, _start
addi r22, r0, __end - 4 /* Include BSS too */
rsub r6, r21, r22
or r5, r0, r0
1: lw r12, r21, r5 /* Load u-boot data */
sw r12, r23, r5 /* Write zero to loc */
cmp r12, r5, r6 /* Check if we have reach the end */
bneid r12, 1b
addi r5, r5, 4 /* Increment to next loc - relocate code */
/* R23 points to the base address. */
add r23, r0, r7 /* Move reloc addr to r23 */
addi r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */
rsub r23, r24, r23 /* keep - this is already here gd->reloc_off */
addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
lwi r7, r0, 0x28
swi r6, r0, 0x28 /* used first unused MB vector */
lbui r10, r0, 0x28 /* used first unused MB vector */
swi r7, r0, 0x28
#ifdef CONFIG_SYS_USR_EXCEP
addik r6, r0, _exception_handler
addk r6, r6, r23 /* add offset */
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0xa
sh r7, r0, r8
rsubi r8, r10, 0xe
sh r6, r0, r8
#endif
addik r6, r0, _hw_exception_handler
addk r6, r6, r23 /* add offset */
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x22
sh r7, r0, r8
rsubi r8, r10, 0x26
sh r6, r0, r8
addik r6, r0, _interrupt_handler
addk r6, r6, r23 /* add offset */
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x12
sh r7, r0, r8
rsubi r8, r10, 0x16
sh r6, r0, r8
/* Check if GOT exist */
addik r21, r23, _got_start
addik r22, r23, _got_end
cmpu r12, r21, r22
beqi r12, 2f /* No GOT table - jump over */
/* Skip last 3 entries plus 1 because of loop boundary below */
addik r22, r22, -0x10
/* Relocate the GOT. */
3: lw r12, r21, r0 /* Load entry */
addk r12, r12, r23 /* Add reloc offset */
sw r12, r21, r0 /* Save entry back */
cmpu r12, r21, r22 /* Check if this cross boundary */
bneid r12, 3b
addik r21. r21, 4
/* Update pointer to GOT */
mfs r20, rpc
addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8
addk r20, r20, r23
/* Flush caches to ensure consistency */
addik r5, r0, 0
addik r6, r0, XILINX_DCACHE_BYTE_SIZE
bralid r15, flush_cache
nop
2: addi r5, r31, 0 /* gd is initialized in board_r.c */
addi r6, r0, CONFIG_SYS_TEXT_BASE
addi r12, r23, board_init_r
bra r12 /* Jump to relocated code */
.end relocate_code
#endif
|
genetel200/u-boot
| 1,369
|
arch/microblaze/cpu/irq.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*/
#include <config.h>
#include <asm/asm.h>
.text
.global _interrupt_handler
_interrupt_handler:
addik r1, r1, -124
swi r2, r1, 4
swi r3, r1, 8
swi r4, r1, 12
swi r5, r1, 16
swi r6, r1, 20
swi r7, r1, 24
swi r8, r1, 28
swi r9, r1, 32
swi r10, r1, 36
swi r11, r1, 40
swi r12, r1, 44
swi r13, r1, 48
swi r14, r1, 52
swi r15, r1, 56
swi r16, r1, 60
swi r17, r1, 64
swi r18, r1, 68
swi r19, r1, 72
swi r20, r1, 76
swi r21, r1, 80
swi r22, r1, 84
swi r23, r1, 88
swi r24, r1, 92
swi r25, r1, 96
swi r26, r1, 100
swi r27, r1, 104
swi r28, r1, 108
swi r29, r1, 112
swi r30, r1, 116
swi r31, r1, 120
brlid r15, interrupt_handler
nop
lwi r31, r1, 120
lwi r30, r1, 116
lwi r29, r1, 112
lwi r28, r1, 108
lwi r27, r1, 104
lwi r26, r1, 100
lwi r25, r1, 96
lwi r24, r1, 92
lwi r23, r1, 88
lwi r22, r1, 84
lwi r21, r1, 80
lwi r20, r1, 76
lwi r19, r1, 72
lwi r18, r1, 68
lwi r17, r1, 64
lwi r16, r1, 60
lwi r15, r1, 56
lwi r14, r1, 52
lwi r13, r1, 48
lwi r12, r1, 44
lwi r11, r1, 40
lwi r10, r1, 36
lwi r9, r1, 32
lwi r8, r1, 28
lwi r7, r1, 24
lwi r6, r1, 20
lwi r5, r1, 16
lwi r4, r1, 12
lwi r3, r1, 8
lwi r2, r1, 4
addik r1, r1, 124
rtid r14, 0
nop
.size _interrupt_handler,.-_interrupt_handler
|
genetel200/u-boot
| 11,902
|
arch/nds32/cpu/n1213/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Andesboot - Startup Code for Whitiger core
*
* Copyright (C) 2006 Andes Technology Corporation
* Copyright (C) 2006 Shawn Lin <nobuhiro@andestech.com>
* Copyright (C) 2011 Macpaul Lin <macpaul@andestech.com>
* Greentime Hu <greentime@andestech.com>
*/
.pic
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
#include <asm/macro.h>
/*
* Jump vector table for EVIC mode
*/
#define ENA_DCAC 2UL
#define DIS_DCAC ~ENA_DCAC
#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
#define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
#define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
#define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
#define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
#define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
#define PSW $ir0
#define EIT_INTR_PSW $ir1 ! interruption $PSW
#define EIT_PREV_IPSW $ir2 ! previous $IPSW
#define EIT_IVB $ir3 ! intr vector base address
#define EIT_EVA $ir4 ! MMU related Exception VA reg
#define EIT_PREV_EVA $ir5 ! previous $eva
#define EIT_ITYPE $ir6 ! interruption type
#define EIT_PREV_ITYPE $ir7 ! prev intr type
#define EIT_MACH_ERR $ir8 ! machine error log
#define EIT_INTR_PC $ir9 ! Interruption PC
#define EIT_PREV_IPC $ir10 ! previous $IPC
#define EIT_OVL_INTR_PC $ir11 ! overflow interruption PC
#define EIT_PREV_P0 $ir12 ! prev $P0
#define EIT_PREV_P1 $ir13 ! prev $p1
#define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
#define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
#define MR_CAC_CTL $mr8
.globl _start
_start: j reset
j tlb_fill
j tlb_not_present
j tlb_misc
j tlb_vlpt_miss
j machine_error
j debug
j general_exception
j syscall
j internal_interrupt ! H0I
j internal_interrupt ! H1I
j internal_interrupt ! H2I
j internal_interrupt ! H3I
j internal_interrupt ! H4I
j internal_interrupt ! H5I
j software_interrupt ! S0I
.balign 16
/*
* Andesboot Startup Code (reset vector)
*
* 1. bootstrap
* 1.1 reset - start of u-boot
* 1.2 to superuser mode - as is when reset
* 1.4 Do lowlevel_init
* - (this will jump out to lowlevel_init.S in SoC)
* - (lowlevel_init)
* 1.3 Turn off watchdog timer
* - (this will jump out to watchdog.S in SoC)
* - (turnoff_watchdog)
* 2. Do critical init when reboot (not from mem)
* 3. Relocate andesboot to ram
* 4. Setup stack
* 5. Jump to second stage (board_init_r)
*/
/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
.globl _TEXT_BASE
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* The bootstrap code of nds32 core
*/
reset:
/*
* gp = ~0 for burn mode
* = ~load_address for load mode
*/
reset_gp:
.relax_hint 0
sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
.relax_hint 0
ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
add5.pc $gp
set_ivb:
li $r0, 0x0
/* turn on BTB */
mtsr $r0, $misc_ctl
/* set IVIC, vector size: 4 bytes, base: 0x0 */
mtsr $r0, $ivb
/*
* MMU_CTL NTC0 Non-cacheable
*/
li $r0, ~0x6
mfsr $r1, $mr0
and $r1, $r1, $r0
mtsr $r1, $mr0
li $r0, ~0x3
mfsr $r1, $mr8
and $r1, $r1, $r0
mtsr $r1, $mr8
#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
/*
* MMU_CTL NTC0 Cacheable/Write-Back
*/
li $r0, 0x4
mfsr $r1, $mr0
or $r1, $r1, $r0
mtsr $r1, $mr0
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
#ifdef CONFIG_ARCH_MAP_SYSMEM
/*
* MMU_CTL NTC1 Non-cacheable
*/
li $r0, ~0x18
mfsr $r1, $mr0
and $r1, $r1, $r0
mtsr $r1, $mr0
/*
* MMU_CTL NTM1 mapping for partition 0
*/
li $r0, ~0x6000
mfsr $r1, $mr0
and $r1, $r1, $r0
mtsr $r1, $mr0
#endif
#endif
#if !defined(CONFIG_SYS_ICACHE_OFF)
li $r0, 0x1
mfsr $r1, $mr8
or $r1, $r1, $r0
mtsr $r1, $mr8
#endif
#if !defined(CONFIG_SYS_DCACHE_OFF)
li $r0, 0x2
mfsr $r1, $mr8
or $r1, $r1, $r0
mtsr $r1, $mr8
#endif
jal mem_init
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
jal lowlevel_init
/*
* gp = ~VMA for burn mode
* = ~load_address for load mode
*/
update_gp:
.relax_hint 0
sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
.relax_hint 0
ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
add5.pc $gp
#endif
/*
* do critical initializations first (shall be in short time)
* do self_relocation ASAP.
*/
/*
* Set the N1213 (Whitiger) core to superuser mode
* According to spec, it is already when reset
*/
#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
jal turnoff_watchdog
#endif
/*
* Set stackpointer in internal RAM to call board_init_f
* $sp must be 8-byte alignment for ABI compliance.
*/
call_board_init_f:
li $sp, CONFIG_SYS_INIT_SP_ADDR
move $r0, $sp
bal board_init_f_alloc_reserve
move $sp, $r0
bal board_init_f_init_reserve
#ifdef CONFIG_DEBUG_UART
bal debug_uart_init
#endif
li $r0, 0x00000000
#ifdef __PIC__
#ifdef __NDS32_N1213_43U1H__
/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
la $r15, board_init_f ! store function address into $r15
#endif
#endif
j board_init_f ! jump to board_init_f() in lib/board.c
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
*/
/*
* gp = ~RAM_SIZE - TEXT_SIZE for burn/load mode
*/
.globl relocate_code
relocate_code:
move $r4, $r0 /* save addr_sp */
move $r5, $r1 /* save addr of gd */
move $r6, $r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
move $sp, $r4
la $r0, _start@GOTOFF
beq $r0, $r6, clear_bss /* skip relocation */
la $r1, _end@GOTOFF
move $r2, $r6 /* r2 <- scratch for copy_loop */
copy_loop:
lmw.bim $r11, [$r0], $r18
smw.bim $r11, [$r2], $r18
blt $r0, $r1, copy_loop
/*
* fix relocations related issues
*/
fix_relocations:
l.w $r0, _TEXT_BASE@GOTOFF /* r0 <- Text base */
sub $r9, $r6, $r0 /* r9 <- relocation offset */
la $r7, __rel_dyn_start@GOTOFF
add $r7, $r7, $r9 /* r2 <- rel __got_start in RAM */
la $r8, __rel_dyn_end@GOTOFF
add $r8, $r8, $r9 /* r2 <- rel __got_start in RAM */
li $r3, #0x2a /* R_NDS32_RELATIVE */
1:
lmw.bim $r0, [$r7], $r2 /* r0,r1,r2 <- adr,type,addend */
bne $r1, $r3, 2f
add $r0, $r0, $r9
add $r2, $r2, $r9
sw $r2, [$r0]
2:
blt $r7, $r8, 1b
clear_bss:
la $r0, __bss_start@GOTOFF /* r0 <- rel __bss_start in FLASH */
add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */
la $r1, __bss_end@GOTOFF /* r1 <- rel __bss_end in RAM */
add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */
li $r2, 0x00000000 /* clear */
clbss_l:
sw $r2, [$r0] /* clear loop... */
addi $r0, $r0, #4
bne $r0, $r1, clbss_l
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
call_board_init_r:
bal invalidate_icache_all
bal flush_dcache_all
la $r0, board_init_r@GOTOFF
move $lp, $r0 /* offset of board_init_r() */
add $lp, $lp, $r9 /* real address of board_init_r() */
/* setup parameters for board_init_r */
move $r0, $r5 /* gd_t */
move $r1, $r6 /* dest_addr */
#ifdef __PIC__
#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA */
move $r15, $lp /* store function address into $r15 */
#endif
#endif
/* jump to it ... */
jr $lp /* jump to board_init_r() */
/*
* Invalidate I$
*/
invalidate_icac:
! read $cr1(I CAC/MEM cfg. reg.) configuration
mfsr $t0, CR_ICAC_MEM
! Get the ISZ field
andi $p0, $t0, ICAC_MEM_KBF_ISZ
! if $p0=0, then no I CAC existed
beqz $p0, end_flush_icache
! get $p0 the index of I$ block
srli $p0, $p0, 6
! $t1= bit width of I cache line size(ISZ)
addi $t1, $p0, 2
li $t4, 1
sll $t5, $t4, $t1 ! get $t5 cache line size
andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
addi $t2, $p1, 6 ! $t2= bit width of ISET
andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
srli $p1, $p1, 3
addi $p1, $p1, 1 ! then $p1 is I way number
add $t3, $t2, $t1 ! SHIFT
sll $p1, $p1, $t3 ! GET the total cache size
ICAC_LOOP:
sub $p1, $p1, $t5
cctl $p1, L1I_IX_INVAL
bnez $p1, ICAC_LOOP
end_flush_icache:
ret
/*
* Invalidate D$
*/
invalidate_dcac:
! read $cr2(D CAC/MEM cfg. reg.) configuration
mfsr $t0, CR_DCAC_MEM
! Get the DSZ field
andi $p0, $t0, DCAC_MEM_KBF_DSZ
! if $p0=0, then no D CAC existed
beqz $p0, end_flush_dcache
! get $p0 the index of D$ block
srli $p0, $p0, 6
! $t1= bit width of D cache line size(DSZ)
addi $t1, $p0, 2
li $t4, 1
sll $t5, $t4, $t1 ! get $t5 cache line size
andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
addi $t2, $p1, 6 ! $t2= bit width of DSET
andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
srli $p1, $p1, 3
addi $p1, $p1, 1 ! then $p1 is D way number
add $t3, $t2, $t1 ! SHIFT
sll $p1, $p1, $t3 ! GET the total cache size
DCAC_LOOP:
sub $p1, $p1, $t5
cctl $p1, L1D_IX_INVAL
bnez $p1, DCAC_LOOP
end_flush_dcache:
ret
/*
* Interrupt handling
*/
/*
* exception handlers
*/
.align 5
.macro SAVE_ALL
! FIXME: Other way to get PC?
! FIXME: Update according to the newest spec!!
1:
li $r28, 1
push $r28
mfsr $r28, PSW ! $PSW
push $r28
mfsr $r28, EIT_EVA ! $ir1 $EVA
push $r28
mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE
push $r28
mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error
push $r28
mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW
push $r28
mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW
push $r28
mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA
push $r28
mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE
push $r28
mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC
push $r28
mfsr $r28, EIT_PREV_IPC ! $ir10 prev INTR_PC
push $r28
mfsr $r28, EIT_OVL_INTR_PC ! $ir11 Overflowed INTR_PC
push $r28
mfusr $r28, $d1.lo
push $r28
mfusr $r28, $d1.hi
push $r28
mfusr $r28, $d0.lo
push $r28
mfusr $r28, $d0.hi
push $r28
pushm $r0, $r30 ! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
addi $sp, $sp, -4 ! make room for implicit pt_regs parameters
.endm
.align 5
tlb_fill:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 1 ! Determine interruption type
bal do_interruption
.align 5
tlb_not_present:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 2 ! Determine interruption type
bal do_interruption
.align 5
tlb_misc:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 3 ! Determine interruption type
bal do_interruption
.align 5
tlb_vlpt_miss:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 4 ! Determine interruption type
bal do_interruption
.align 5
machine_error:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 5 ! Determine interruption type
bal do_interruption
.align 5
debug:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 6 ! Determine interruption type
bal do_interruption
.align 5
general_exception:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 7 ! Determine interruption type
bal do_interruption
.align 5
syscall:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 8 ! Determine interruption type
bal do_interruption
.align 5
internal_interrupt:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 9 ! Determine interruption type
bal do_interruption
.align 5
software_interrupt:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 10 ! Determine interruption type
bal do_interruption
.align 5
/*
* void reset_cpu(ulong addr);
* $r0: input address to jump to
*/
.globl reset_cpu
reset_cpu:
/* No need to disable MMU because we never enable it */
bal invalidate_icac
bal invalidate_dcac
mfsr $p0, $MMU_CFG
andi $p0, $p0, 0x3 ! MMPS
li $p1, 0x2 ! TLB MMU
bne $p0, $p1, 1f
tlbop flushall ! Flush TLB
1:
mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
li $p1, DIS_DCAC
and $p0, $p0, $p1 ! Clear the DC_EN bit
mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg
br $r0 ! Jump to the input address
|
genetel200/u-boot
| 3,377
|
arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*/
.pic
.text
#include <common.h>
#include <config.h>
#include <asm/macro.h>
#include <generated/asm-offsets.h>
/*
* parameters for the SDRAM controller
*/
#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
/*
* for Orca and Emerald
*/
#define BOARD_ID_REG 0x104
#define BOARD_ID_FAMILY_MASK 0xfff000
#define BOARD_ID_FAMILY_V5 0x556000
#define BOARD_ID_FAMILY_K7 0x74b000
/*
* parameters for the static memory controller
*/
#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
/*
* for Orca and Emerald
*/
#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
/*
* parameters for the pmu controoler
*/
#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
/*
* numeric 7 segment display
*/
.macro led, num
write32 CONFIG_DEBUG_LED, \num
.endm
/*
* Waiting for SDRAM to set up
*/
.macro wait_sdram
li $r0, CONFIG_FTSDMC021_BASE
1:
lwi $r1, [$r0+FTSDMC021_CR2]
bnez $r1, 1b
.endm
.globl mem_init
mem_init:
move $r11, $lp
li $r0, SMC_BANK0_CR_A
lwi $r1, [$r0+#0x00]
ori $r1, $r1, 0x8f0
xori $r1, $r1, 0x8f0
/* 16-bit mode */
ori $r1, $r1, 0x60
li $r2, 0x00153153
swi $r1, [$r0+#0x00]
swi $r2, [$r0+#0x04]
move $lp, $r11
ret
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
.globl lowlevel_init
lowlevel_init:
move $r10, $lp
jal remap
#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
jal enable_fpu
#endif
ret $r10
remap:
move $r11, $lp
relo_base:
mfusr $r0, $pc
#ifdef CONFIG_MEM_REMAP
li $r4, 0x00000000
li $r5, 0x80000000
la $r6, _end@GOTOFF
1:
lmw.bim $r12, [$r5], $r19
smw.bim $r12, [$r4], $r19
blt $r5, $r6, 1b
#endif /* #ifdef CONFIG_MEM_REMAP */
move $lp, $r11
2:
ret
/*
* enable_fpu:
* Some of Andes CPU version support FPU coprocessor, if so,
* and toolchain support FPU instruction set, we should enable it.
*/
#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
enable_fpu:
mfsr $r0, $CPU_VER /* enable FPU if it exists */
srli $r0, $r0, 3
andi $r0, $r0, 1
beqz $r0, 1f /* skip if no COP */
mfsr $r0, $FUCOP_EXIST
srli $r0, $r0, 31
beqz $r0, 1f /* skip if no FPU */
mfsr $r0, $FUCOP_CTL
ori $r0, $r0, 1
mtsr $r0, $FUCOP_CTL
1:
ret
#endif
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
|
genetel200/u-boot
| 7,616
|
arch/nds32/cpu/n1213/ag101/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*/
.pic
.text
#include <common.h>
#include <config.h>
#include <asm/macro.h>
#include <generated/asm-offsets.h>
/*
* parameters for the SDRAM controller
*/
#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
/*
* for Orca and Emerald
*/
#define BOARD_ID_REG 0x104
#define BOARD_ID_FAMILY_MASK 0xfff000
#define BOARD_ID_FAMILY_V5 0x556000
#define BOARD_ID_FAMILY_K7 0x74b000
/*
* parameters for the static memory controller
*/
#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
/*
* parameters for the ahbc controller
*/
#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
/*
* for Orca and Emerald
*/
#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
/*
* parameters for the pmu controoler
*/
#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
/*
* numeric 7 segment display
*/
.macro led, num
write32 CONFIG_DEBUG_LED, \num
.endm
/*
* Waiting for SDRAM to set up
*/
.macro wait_sdram
li $r0, CONFIG_FTSDMC021_BASE
1:
lwi $r1, [$r0+FTSDMC021_CR2]
bnez $r1, 1b
.endm
.globl mem_init
mem_init:
move $r11, $lp
/*
* mem_init:
* There are 2 bank connected to FTSMC020 on AG101
* BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
* we need to set onboard SDRAM before remap and relocation.
*/
led 0x01
/*
* for Orca and Emerald
* disable write protection and reset bank size
*/
li $r0, SMC_BANK0_CR_A
lwi $r1, [$r0+#0x00]
ori $r1, $r1, 0x8f0
xori $r1, $r1, 0x8f0
/* check board */
li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
lwi $r3, [$r3]
li $r4, BOARD_ID_FAMILY_MASK
and $r3, $r3, $r4
li $r4, BOARD_ID_FAMILY_K7
xor $r4, $r3, $r4
beqz $r4, use_flash_16bit_boot
/* 32-bit mode */
use_flash_32bit_boot:
ori $r1, $r1, 0x50
li $r2, 0x00151151
j sdram_b0_cr
/* 16-bit mode */
use_flash_16bit_boot:
ori $r1, $r1, 0x60
li $r2, 0x00153153
/* SRAM bank0 config */
sdram_b0_cr:
swi $r1, [$r0+#0x00]
swi $r2, [$r0+#0x04]
/* config AHB Controller */
led 0x02
/*
* config PMU controller
*/
/* ftpmu010_dlldis_disable, must do it in lowleve_init */
led 0x03
setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
/*
* config SDRAM controller
*/
led 0x04
write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
led 0x05
write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
led 0x06
write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
led 0x07
write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
wait_sdram
led 0x08
write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
wait_sdram
led 0x09
write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
wait_sdram
led 0x0a
move $lp, $r11
ret
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
.globl lowlevel_init
lowlevel_init:
move $r10, $lp
led 0x10
jal remap
#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
led 0x1f
jal enable_fpu
#endif
led 0x20
ret $r10
remap:
move $r11, $lp
#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
bal 2f
relo_base:
move $r0, $lp
#else
relo_base:
mfusr $r0, $pc
#endif /* __NDS32_N1213_43U1H__ */
/* Remapping */
led 0x1a
write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800
write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880
/* clear empty BSR registers */
led 0x1b
li $r4, CONFIG_FTSDMC021_BASE
li $r5, 0x0
swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
#ifdef CONFIG_MEM_REMAP
/*
* Copy ROM code to SDRAM base for memory remap layout.
* This is not the real relocation, the real relocation is the function
* relocate_code() is start.S which supports the systems is memory
* remapped or not.
*/
/*
* Doing memory remap is essential for preparing some non-OS or RTOS
* applications.
*
* This is also a must on ADP-AG101 board.
* The reason is because the ROM/FLASH circuit on PCB board.
* AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
* ROM/FLASH is used to boot.
*
* When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
* and the FLASH is connected to BANK1.
* When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
* and the FLASH is connected to BANK0.
* It will occur problem when doing flash probing if the flash is at
* BANK0 (0x00000000) while memory remapping was skipped.
*
* Other board like ADP-AG101P may not enable this since there is only
* a FLASH connected to bank0.
*/
led 0x11
/*
* for Orca and Emerald
* read sdram base address automatically
*/
li $r5, AHBC_BSR6_A
lwi $r8, [$r5]
li $r4, 0xfff00000 /* r4 = bank6 base */
and $r4, $r4, $r8
la $r5, _start@GOTOFF
la $r6, _end@GOTOFF
1:
lwi.p $r7, [$r5], #4
swi.p $r7, [$r4], #4
blt $r5, $r6, 1b
/* set remap bit */
/*
* MEM remap bit is operational
* - use it to map writeable memory at 0x00000000, in place of flash
* - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
* - after remap: flash/rom 0x80000000, sdram: 0x00000000
*/
led 0x1c
write32 SDMC_B0_BSR_A, 0x00001000
write32 SDMC_B1_BSR_A, 0x00001200
li $r5, CONFIG_SYS_TEXT_BASE /* flash base address */
add $r11, $r11, $r5 /* add flash address offset for ret */
add $r10, $r10, $r5
move $lp, $r11
setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
/*
* for Orca and Emerald
* extend sdram size from 256MB to 2GB
*/
li $r5, AHBC_BSR6_A
lwi $r6, [$r5]
li $r4, 0xfff0ffff
and $r6 ,$r4, $r6
li $r4, 0x000b0000
or $r6, $r4, $r6
swi $r6, [$r5]
/*
* for Orca and Emerald
* extend rom base from 256MB to 2GB
*/
li $r4, AHBC_BSR4_A
lwi $r5, [$r4]
li $r6, 0xffffff
and $r5, $r5, $r6
li $r6, 0x80000000
or $r5, $r5, $r6
swi $r5, [$r4]
#endif /* #ifdef CONFIG_MEM_REMAP */
move $lp, $r11
2:
ret
/*
* enable_fpu:
* Some of Andes CPU version support FPU coprocessor, if so,
* and toolchain support FPU instruction set, we should enable it.
*/
#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
enable_fpu:
mfsr $r0, $CPU_VER /* enable FPU if it exists */
srli $r0, $r0, 3
andi $r0, $r0, 1
beqz $r0, 1f /* skip if no COP */
mfsr $r0, $FUCOP_EXIST
srli $r0, $r0, 31
beqz $r0, 1f /* skip if no FPU */
mfsr $r0, $FUCOP_CTL
ori $r0, $r0, 1
mtsr $r0, $FUCOP_CTL
1:
ret
#endif
.globl show_led
show_led:
li $r8, (CONFIG_DEBUG_LED)
swi $r7, [$r8]
ret
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
|
genetel200/u-boot
| 3,891
|
arch/mips/lib/genex.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2002, 2007 Maciej W. Rozycki
* Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
*/
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/asm-offsets.h>
#define STATMASK 0x1f
.set noreorder
/*
* Macros copied and adapted from Linux MIPS
*/
.macro SAVE_AT
.set push
.set noat
LONG_S $1, PT_R1(sp)
.set pop
.endm
.macro SAVE_TEMP
#if __mips_isa_rev < 6
mfhi v1
#endif
#ifdef CONFIG_32BIT
LONG_S $8, PT_R8(sp)
LONG_S $9, PT_R9(sp)
#endif
LONG_S $10, PT_R10(sp)
LONG_S $11, PT_R11(sp)
LONG_S $12, PT_R12(sp)
#if __mips_isa_rev < 6
LONG_S v1, PT_HI(sp)
mflo v1
#endif
LONG_S $13, PT_R13(sp)
LONG_S $14, PT_R14(sp)
LONG_S $15, PT_R15(sp)
LONG_S $24, PT_R24(sp)
#if __mips_isa_rev < 6
LONG_S v1, PT_LO(sp)
#endif
.endm
.macro SAVE_STATIC
LONG_S $16, PT_R16(sp)
LONG_S $17, PT_R17(sp)
LONG_S $18, PT_R18(sp)
LONG_S $19, PT_R19(sp)
LONG_S $20, PT_R20(sp)
LONG_S $21, PT_R21(sp)
LONG_S $22, PT_R22(sp)
LONG_S $23, PT_R23(sp)
LONG_S $30, PT_R30(sp)
.endm
.macro SAVE_SOME
.set push
.set noat
PTR_SUBU k1, sp, PT_SIZE
LONG_S sp, PT_R29(k1)
move sp, k1
LONG_S $3, PT_R3(sp)
LONG_S $0, PT_R0(sp)
mfc0 v1, CP0_STATUS
LONG_S $2, PT_R2(sp)
LONG_S v1, PT_STATUS(sp)
LONG_S $4, PT_R4(sp)
mfc0 v1, CP0_CAUSE
LONG_S $5, PT_R5(sp)
LONG_S v1, PT_CAUSE(sp)
LONG_S $6, PT_R6(sp)
MFC0 v1, CP0_EPC
LONG_S $7, PT_R7(sp)
#ifdef CONFIG_64BIT
LONG_S $8, PT_R8(sp)
LONG_S $9, PT_R9(sp)
#endif
LONG_S v1, PT_EPC(sp)
LONG_S $25, PT_R25(sp)
LONG_S $28, PT_R28(sp)
LONG_S $31, PT_R31(sp)
.set pop
.endm
.macro RESTORE_AT
.set push
.set noat
LONG_L $1, PT_R1(sp)
.set pop
.endm
.macro RESTORE_TEMP
#if __mips_isa_rev < 6
LONG_L $24, PT_LO(sp)
mtlo $24
LONG_L $24, PT_HI(sp)
mthi $24
#endif
#ifdef CONFIG_32BIT
LONG_L $8, PT_R8(sp)
LONG_L $9, PT_R9(sp)
#endif
LONG_L $10, PT_R10(sp)
LONG_L $11, PT_R11(sp)
LONG_L $12, PT_R12(sp)
LONG_L $13, PT_R13(sp)
LONG_L $14, PT_R14(sp)
LONG_L $15, PT_R15(sp)
LONG_L $24, PT_R24(sp)
.endm
.macro RESTORE_STATIC
LONG_L $16, PT_R16(sp)
LONG_L $17, PT_R17(sp)
LONG_L $18, PT_R18(sp)
LONG_L $19, PT_R19(sp)
LONG_L $20, PT_R20(sp)
LONG_L $21, PT_R21(sp)
LONG_L $22, PT_R22(sp)
LONG_L $23, PT_R23(sp)
LONG_L $30, PT_R30(sp)
.endm
.macro RESTORE_SOME
.set push
.set reorder
.set noat
mfc0 a0, CP0_STATUS
ori a0, STATMASK
xori a0, STATMASK
mtc0 a0, CP0_STATUS
li v1, ST0_CU1 | ST0_FR | ST0_IM
and a0, v1
LONG_L v0, PT_STATUS(sp)
nor v1, $0, v1
and v0, v1
or v0, a0
mtc0 v0, CP0_STATUS
LONG_L v1, PT_EPC(sp)
MTC0 v1, CP0_EPC
LONG_L $31, PT_R31(sp)
LONG_L $28, PT_R28(sp)
LONG_L $25, PT_R25(sp)
#ifdef CONFIG_64BIT
LONG_L $8, PT_R8(sp)
LONG_L $9, PT_R9(sp)
#endif
LONG_L $7, PT_R7(sp)
LONG_L $6, PT_R6(sp)
LONG_L $5, PT_R5(sp)
LONG_L $4, PT_R4(sp)
LONG_L $3, PT_R3(sp)
LONG_L $2, PT_R2(sp)
.set pop
.endm
.macro RESTORE_SP
LONG_L sp, PT_R29(sp)
.endm
NESTED(except_vec3_generic, 0, sp)
PTR_LA k1, handle_reserved
jr k1
nop
END(except_vec3_generic)
NESTED(except_vec_ejtag_debug, 0, sp)
PTR_LA k1, handle_ejtag_debug
jr k1
nop
END(except_vec_ejtag_debug)
NESTED(handle_reserved, PT_SIZE, sp)
SAVE_SOME
SAVE_AT
SAVE_TEMP
SAVE_STATIC
PTR_LA t9, do_reserved
jr t9
move a0, sp
END(handle_reserved)
NESTED(handle_ejtag_debug, PT_SIZE, sp)
.set push
.set noat
MTC0 k1, CP0_DESAVE
/* Check for SDBBP */
MFC0 k1, CP0_DEBUG
sll k1, k1, 30
bgez k1, ejtag_return
nop
SAVE_SOME
SAVE_AT
SAVE_TEMP
SAVE_STATIC
PTR_LA t9, do_ejtag_debug
jalr t9
move a0, sp
RESTORE_TEMP
RESTORE_STATIC
RESTORE_AT
RESTORE_SOME
RESTORE_SP
ejtag_return:
MFC0 k1, CP0_DESAVE
deret
.set pop
END(handle_ejtag_debug)
|
genetel200/u-boot
| 11,070
|
arch/mips/lib/cache_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Cache-handling routined for MIPS CPUs
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#include <asm/cm.h>
.macro f_fill64 dst, offset, val
LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
#if LONGSIZE == 4
LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
#endif
.endm
.macro cache_loop curr, end, line_sz, op
10: cache \op, 0(\curr)
PTR_ADDU \curr, \curr, \line_sz
bne \curr, \end, 10b
.endm
.macro l1_info sz, line_sz, off
.set push
.set noat
mfc0 $1, CP0_CONFIG, 1
/* detect line size */
srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
move \sz, zero
beqz \line_sz, 10f
li \sz, 2
sllv \line_sz, \sz, \line_sz
/* detect associativity */
srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
addiu \sz, \sz, 1
/* sz *= line_sz */
mul \sz, \sz, \line_sz
/* detect log32(sets) */
srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF)
addiu $1, $1, 1
andi $1, $1, 0x7
/* sz <<= log32(sets) */
sllv \sz, \sz, $1
/* sz *= 32 */
li $1, 32
mul \sz, \sz, $1
10:
.set pop
.endm
/*
* mips_cache_reset - low level initialisation of the primary caches
*
* This routine initialises the primary caches to ensure that they have good
* parity. It must be called by the ROM before any cached locations are used
* to prevent the possibility of data with bad parity being written to memory.
*
* To initialise the instruction cache it is essential that a source of data
* with good parity is available. This routine will initialise an area of
* memory starting at location zero to be used as a source of parity.
*
* Note that this function does not follow the standard calling convention &
* may clobber typically callee-saved registers.
*
* RETURNS: N/A
*
*/
#define R_RETURN s0
#define R_IC_SIZE s1
#define R_IC_LINE s2
#define R_DC_SIZE s3
#define R_DC_LINE s4
#define R_L2_SIZE s5
#define R_L2_LINE s6
#define R_L2_BYPASSED s7
#define R_L2_L2C t8
LEAF(mips_cache_reset)
move R_RETURN, ra
#ifdef CONFIG_MIPS_L2_CACHE
/*
* For there to be an L2 present, Config2 must be present. If it isn't
* then we proceed knowing there's no L2 cache.
*/
move R_L2_SIZE, zero
move R_L2_LINE, zero
move R_L2_BYPASSED, zero
move R_L2_L2C, zero
mfc0 t0, CP0_CONFIG, 1
bgez t0, l2_probe_done
/*
* From MIPSr6 onwards the L2 cache configuration might not be reported
* by Config2. The Config5.L2C bit indicates whether this is the case,
* and if it is then we need knowledge of where else to look. For cores
* from Imagination Technologies this is a CM GCR.
*/
# if __mips_isa_rev >= 6
/* Check that Config5 exists */
mfc0 t0, CP0_CONFIG, 2
bgez t0, l2_probe_cop0
mfc0 t0, CP0_CONFIG, 3
bgez t0, l2_probe_cop0
mfc0 t0, CP0_CONFIG, 4
bgez t0, l2_probe_cop0
/* Check Config5.L2C is set */
mfc0 t0, CP0_CONFIG, 5
and R_L2_L2C, t0, MIPS_CONF5_L2C
beqz R_L2_L2C, l2_probe_cop0
/* Config5.L2C is set */
# ifdef CONFIG_MIPS_CM
/* The CM will provide L2 configuration */
PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
lw t1, GCR_L2_CONFIG(t0)
bgez t1, l2_probe_done
ext R_L2_LINE, t1, \
GCR_L2_CONFIG_LINESZ_SHIFT, GCR_L2_CONFIG_LINESZ_BITS
beqz R_L2_LINE, l2_probe_done
li t2, 2
sllv R_L2_LINE, t2, R_L2_LINE
ext t2, t1, GCR_L2_CONFIG_ASSOC_SHIFT, GCR_L2_CONFIG_ASSOC_BITS
addiu t2, t2, 1
mul R_L2_SIZE, R_L2_LINE, t2
ext t2, t1, GCR_L2_CONFIG_SETSZ_SHIFT, GCR_L2_CONFIG_SETSZ_BITS
sllv R_L2_SIZE, R_L2_SIZE, t2
li t2, 64
mul R_L2_SIZE, R_L2_SIZE, t2
/* Bypass the L2 cache so that we can init the L1s early */
or t1, t1, GCR_L2_CONFIG_BYPASS
sw t1, GCR_L2_CONFIG(t0)
sync
li R_L2_BYPASSED, 1
/* Zero the L2 tag registers */
sw zero, GCR_L2_TAG_ADDR(t0)
sw zero, GCR_L2_TAG_ADDR_UPPER(t0)
sw zero, GCR_L2_TAG_STATE(t0)
sw zero, GCR_L2_TAG_STATE_UPPER(t0)
sw zero, GCR_L2_DATA(t0)
sw zero, GCR_L2_DATA_UPPER(t0)
sync
# else
/* We don't know how to retrieve L2 configuration on this system */
# endif
b l2_probe_done
# endif
/*
* For pre-r6 systems, or r6 systems with Config5.L2C==0, probe the L2
* cache configuration from the cop0 Config2 register.
*/
l2_probe_cop0:
mfc0 t0, CP0_CONFIG, 2
srl R_L2_LINE, t0, MIPS_CONF2_SL_SHF
andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
beqz R_L2_LINE, l2_probe_done
li t1, 2
sllv R_L2_LINE, t1, R_L2_LINE
srl t1, t0, MIPS_CONF2_SA_SHF
andi t1, t1, MIPS_CONF2_SA >> MIPS_CONF2_SA_SHF
addiu t1, t1, 1
mul R_L2_SIZE, R_L2_LINE, t1
srl t1, t0, MIPS_CONF2_SS_SHF
andi t1, t1, MIPS_CONF2_SS >> MIPS_CONF2_SS_SHF
sllv R_L2_SIZE, R_L2_SIZE, t1
li t1, 64
mul R_L2_SIZE, R_L2_SIZE, t1
/* Attempt to bypass the L2 so that we can init the L1s early */
or t0, t0, MIPS_CONF2_L2B
mtc0 t0, CP0_CONFIG, 2
ehb
mfc0 t0, CP0_CONFIG, 2
and R_L2_BYPASSED, t0, MIPS_CONF2_L2B
/* Zero the L2 tag registers */
mtc0 zero, CP0_TAGLO, 4
ehb
l2_probe_done:
#endif
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li R_IC_SIZE, CONFIG_SYS_ICACHE_SIZE
li R_IC_LINE, CONFIG_SYS_ICACHE_LINE_SIZE
#else
l1_info R_IC_SIZE, R_IC_LINE, MIPS_CONF1_IA_SHF
#endif
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li R_DC_SIZE, CONFIG_SYS_DCACHE_SIZE
li R_DC_LINE, CONFIG_SYS_DCACHE_LINE_SIZE
#else
l1_info R_DC_SIZE, R_DC_LINE, MIPS_CONF1_DA_SHF
#endif
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Determine the largest L1 cache size */
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
li v0, CONFIG_SYS_ICACHE_SIZE
#else
li v0, CONFIG_SYS_DCACHE_SIZE
#endif
#else
move v0, R_IC_SIZE
sltu t1, R_IC_SIZE, R_DC_SIZE
movn v0, R_DC_SIZE, t1
#endif
/*
* Now clear that much memory starting from zero.
*/
PTR_LI a0, CKSEG1ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
PTR_ADDU a1, a0, v0
2: PTR_ADDIU a0, 64
f_fill64 a0, -64, zero
bne a0, a1, 2b
#endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
#ifdef CONFIG_MIPS_L2_CACHE
/*
* If the L2 is bypassed, init the L1 first so that we can execute the
* rest of the cache initialisation using the L1 instruction cache.
*/
bnez R_L2_BYPASSED, l1_init
l2_init:
PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
PTR_ADDU t1, t0, R_L2_SIZE
1: cache INDEX_STORE_TAG_SD, 0(t0)
PTR_ADDU t0, t0, R_L2_LINE
bne t0, t1, 1b
/*
* If the L2 was bypassed then we already initialised the L1s before
* the L2, so we are now done.
*/
bnez R_L2_BYPASSED, l2_unbypass
#endif
/*
* The TagLo registers used depend upon the CPU implementation, but the
* architecture requires that it is safe for software to write to both
* TagLo selects 0 & 2 covering supported cases.
*/
l1_init:
mtc0 zero, CP0_TAGLO
mtc0 zero, CP0_TAGLO, 2
ehb
/*
* The caches are probably in an indeterminate state, so we force good
* parity into them by doing an invalidate for each line. If
* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to
* perform a load/fill & a further invalidate for each line, assuming
* that the bottom of RAM (having just been cleared) will generate good
* parity for the cache.
*/
/*
* Initialize the I-cache first,
*/
blez R_IC_SIZE, 1f
PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
PTR_ADDU t1, t0, R_IC_SIZE
/* clear tag to invalidate */
cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* fill once, so data field parity is correct */
PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
cache_loop t0, t1, R_IC_LINE, FILL
/* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
#endif
sync
/*
* Enable use of the I-cache by setting Config.K0. The code for this
* must be executed from KSEG1. Jump from KSEG0 to KSEG1 to do this.
* Jump back to KSEG0 after caches are enabled and insert an
* instruction hazard barrier.
*/
PTR_LA t0, change_k0_cca
li t1, CPHYSADDR(~0)
and t0, t0, t1
PTR_LI t1, CKSEG1
or t0, t0, t1
li a0, CONF_CM_CACHABLE_NONCOHERENT
jalr.hb t0
/*
* then initialize D-cache.
*/
1: blez R_DC_SIZE, 3f
PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
PTR_ADDU t1, t0, R_DC_SIZE
/* clear all tags */
cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* load from each line (in cached space) */
PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
2: LONG_L zero, 0(t0)
PTR_ADDU t0, R_DC_LINE
bne t0, t1, 2b
/* clear all tags */
PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
#endif
3:
#ifdef CONFIG_MIPS_L2_CACHE
/* If the L2 isn't bypassed then we're done */
beqz R_L2_BYPASSED, return
/* The L2 is bypassed - go initialise it */
b l2_init
l2_unbypass:
# if __mips_isa_rev >= 6
beqz R_L2_L2C, 1f
li t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
lw t1, GCR_L2_CONFIG(t0)
xor t1, t1, GCR_L2_CONFIG_BYPASS
sw t1, GCR_L2_CONFIG(t0)
sync
ehb
b 2f
# endif
1: mfc0 t0, CP0_CONFIG, 2
xor t0, t0, MIPS_CONF2_L2B
mtc0 t0, CP0_CONFIG, 2
ehb
2:
# ifdef CONFIG_MIPS_CM
/* Config3 must exist for a CM to be present */
mfc0 t0, CP0_CONFIG, 1
bgez t0, 2f
mfc0 t0, CP0_CONFIG, 2
bgez t0, 2f
/* Check Config3.CMGCR to determine CM presence */
mfc0 t0, CP0_CONFIG, 3
and t0, t0, MIPS_CONF3_CMGCR
beqz t0, 2f
/* Change Config.K0 to a coherent CCA */
PTR_LA t0, change_k0_cca
li a0, CONF_CM_CACHABLE_COW
jalr t0
/*
* Join the coherent domain such that the caches of this core are kept
* coherent with those of other cores.
*/
PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
lw t1, GCR_REV(t0)
li t2, GCR_REV_CM3
li t3, GCR_Cx_COHERENCE_EN
bge t1, t2, 1f
li t3, GCR_Cx_COHERENCE_DOM_EN
1: sw t3, GCR_Cx_COHERENCE(t0)
ehb
2:
# endif
#endif
return:
/* Ensure all cache operations complete before returning */
sync
jr R_RETURN
END(mips_cache_reset)
LEAF(change_k0_cca)
mfc0 t0, CP0_CONFIG
#if __mips_isa_rev >= 2
ins t0, a0, 0, 3
#else
xor a0, a0, t0
andi a0, a0, CONF_CM_CMASK
xor a0, a0, t0
#endif
mtc0 a0, CP0_CONFIG
jr.hb ra
END(change_k0_cca)
|
genetel200/u-boot
| 6,107
|
arch/mips/mach-mt7620/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (c) 2018 Stefan Roese <sr@denx.de>
*
* This code is mostly based on the code extracted from this MediaTek
* github repository:
*
* https://github.com/MediaTek-Labs/linkit-smart-uboot.git
*
* I was not able to find a specific license or other developers
* copyrights here, so I can't add them here.
*/
#include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/asm.h>
#include "mt76xx.h"
#ifndef BIT
#define BIT(nr) (1 << (nr))
#endif
#define DELAY_USEC(us) ((us) / 100)
#define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16)
#define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12)
#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
#define DDR_CFG1_SIZE_VAL 0x222e2323
#define DDR_CFG4_SIZE_VAL 7
#endif
#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
#define DDR_CFG1_SIZE_VAL 0x22322323
#define DDR_CFG4_SIZE_VAL 9
#endif
#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
#define DDR_CFG1_SIZE_VAL 0x22362323
#define DDR_CFG4_SIZE_VAL 9
#endif
#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
#define DDR_CFG1_SIZE_VAL 0x223a2323
#define DDR_CFG4_SIZE_VAL 9
#endif
#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT)
#define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16)
#endif
#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT)
#define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16)
#endif
#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT)
#define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12)
#endif
#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT)
#define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12)
#endif
.set noreorder
LEAF(lowlevel_init)
/* Load base addresses as physical addresses for later usage */
li s0, CKSEG1ADDR(MT76XX_SYSCTL_BASE)
li s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE)
li s2, CKSEG1ADDR(MT76XX_RGCTRL_BASE)
/* polling CPLL is ready */
li t1, DELAY_USEC(1000000)
la t5, MT76XX_ROM_STATUS_REG
1:
lw t2, 0(t5)
andi t2, t2, 0x1
bnez t2, CPLL_READY
subu t1, t1, 1
bgtz t1, 1b
nop
la t0, MT76XX_CLKCFG0_REG
lw t3, 0(t0)
ori t3, t3, 0x1
sw t3, 0(t0)
b CPLL_DONE
nop
CPLL_READY:
la t0, MT76XX_CLKCFG0_REG
lw t1, 0(t0)
li t2, ~0x0c
and t1, t1, t2
ori t1, t1, 0xc
sw t1, 0(t0)
la t0, MT76XX_DYN_CFG0_REG
lw t3, 0(t0)
li t5, ~((0x0f << 8) | (0x0f << 0))
and t3, t3, t5
li t5, (10 << 8) | (1 << 0)
or t3, t3, t5
sw t3, 0(t0)
la t0, MT76XX_CLKCFG0_REG
lw t3, 0(t0)
li t4, ~0x0F
and t3, t3, t4
ori t3, t3, 0xc
sw t3, 0(t0)
lw t3, 0(t0)
ori t3, t3, 0x08
sw t3, 0(t0)
CPLL_DONE:
/* Reset MC */
lw t2, 0x34(s0)
ori t2, BIT(10)
sw t2, 0x34(s0)
nop
/*
* SDR and DDR initialization: delay 200us
*/
li t0, DELAY_USEC(200 + 40)
li t1, 0x1
1:
sub t0, t0, t1
bnez t0, 1b
nop
/* set DRAM IO PAD for MT7628IC */
/* DDR LDO Enable */
lw t4, 0x100(s2)
li t2, BIT(31)
or t4, t4, t2
sw t4, 0x100(s2)
lw t4, 0x10c(s2)
j LDO_1P8V
nop
LDO_1P8V:
li t2, ~BIT(6)
and t4, t4, t2
sw t4, 0x10c(s2)
j DDRLDO_SOFT_START
LDO_2P5V:
/* suppose external DDR1 LDO 2.5V */
li t2, BIT(6)
or t4, t4, t2
sw t4, 0x10c(s2)
DDRLDO_SOFT_START:
lw t2, 0x10c(s2)
li t3, BIT(16)
or t2, t2, t3
sw t2, 0x10c(s2)
li t3, DELAY_USEC(250*50)
LDO_DELAY:
subu t3, t3, 1
bnez t3, LDO_DELAY
nop
lw t2, 0x10c(s2)
li t3, BIT(18)
or t2, t2, t3
sw t2, 0x10c(s2)
SET_RG_BUCK_FPWM:
lw t2, 0x104(s2)
ori t2, t2, BIT(10)
sw t2, 0x104(s2)
DDR_PAD_CFG:
/* clean CLK PAD */
lw t2, 0x704(s2)
li t8, 0xfffff0f0
and t2, t2, t8
/* clean CMD PAD */
lw t3, 0x70c(s2)
li t8, 0xfffff0f0
and t3, t3, t8
/* clean DQ IPAD */
lw t4, 0x710(s2)
li t8, 0xfffff8ff
and t4, t4, t8
/* clean DQ OPAD */
lw t5, 0x714(s2)
li t8, 0xfffff0f0
and t5, t5, t8
/* clean DQS IPAD */
lw t6, 0x718(s2)
li t8, 0xfffff8ff
and t6, t6, t8
/* clean DQS OPAD */
lw t7, 0x71c(s2)
li t8, 0xfffff0f0
and t7, t7, t8
lw t9, 0xc(s0)
srl t9, t9, 16
andi t9, t9, 0x1
bnez t9, MT7628_AN_DDR1_PAD
MT7628_KN_PAD:
li t8, 0x00000303
or t2, t2, t8
or t3, t3, t8
or t5, t5, t8
or t7, t7, t8
li t8, 0x00000000
or t4, t4, t8
or t6, t6, t8
j SET_PAD_CFG
MT7628_AN_DDR1_PAD:
lw t1, 0x10(s0)
andi t1, t1, 0x1
beqz t1, MT7628_AN_DDR2_PAD
li t8, 0x00000c0c
or t2, t2, t8
li t8, 0x00000202
or t3, t3, t8
li t8, 0x00000707
or t5, t5, t8
li t8, 0x00000c0c
or t7, t7, t8
li t8, 0x00000000
or t4, t4, t8
or t6, t6, t8
j SET_PAD_CFG
MT7628_AN_DDR2_PAD:
li t8, 0x00000c0c
or t2, t2, t8
li t8, 0x00000202
or t3, t3, t8
li t8, 0x00000404
or t5, t5, t8
li t8, 0x00000c0c
or t7, t7, t8
li t8, 0x00000000 /* ODT off */
or t4, t4, t8
or t6, t6, t8
SET_PAD_CFG:
sw t2, 0x704(s2)
sw t3, 0x70c(s2)
sw t4, 0x710(s2)
sw t5, 0x714(s2)
sw t6, 0x718(s2)
sw t7, 0x71c(s2)
/*
* DDR initialization: reset pin to 0
*/
lw t2, 0x34(s0)
and t2, ~BIT(10)
sw t2, 0x34(s0)
nop
/*
* DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
*/
DDR_READY:
li t1, DDR_CFG1_REG
lw t0, 0(t1)
nop
and t2, t0, BIT(21)
beqz t2, DDR_READY
nop
/*
* DDR initialization
*
* Only DDR2 supported right now. DDR2 support can be added, once
* boards using it will get added to mainline U-Boot.
*/
li t1, DDR_CFG2_REG
lw t0, 0(t1)
nop
and t0, ~BIT(30)
and t0, ~(7 << 4)
or t0, (4 << 4)
or t0, BIT(30)
or t0, BIT(11)
sw t0, 0(t1)
nop
li t1, DDR_CFG3_REG
lw t2, 0(t1)
/* Disable ODT; reference board ok, ev board fail */
and t2, ~BIT(6)
or t2, BIT(2)
li t0, DDR_CFG4_REG
lw t1, 0(t0)
li t2, ~(0x01f | 0x0f0)
and t1, t1, t2
ori t1, t1, DDR_CFG4_SIZE_VAL
sw t1, 0(t0)
nop
/*
* DDR initialization: config size and width on reg DDR_CFG1
*/
li t6, DDR_CFG1_SIZE_VAL
and t6, ~DDR_CFG1_CHIP_WIDTH_MASK
or t6, DDR_CFG1_CHIP_WIDTH_VAL
/* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
and t6, ~DDR_CFG1_BUS_WIDTH_MASK
or t6, DDR_CFG1_BUS_WIDTH_VAL
li t5, DDR_CFG1_REG
sw t6, 0(t5)
nop
/*
* DDR: enable self auto refresh for power saving
* enable it by default for both RAM and ROM version (for CoC)
*/
lw t1, 0x14(s1)
nop
and t1, 0xff000000
or t1, 0x01
sw t1, 0x14(s1)
nop
lw t1, 0x10(s1)
nop
or t1, 0x10
sw t1, 0x10(s1)
nop
jr ra
nop
END(lowlevel_init)
|
genetel200/u-boot
| 1,634
|
arch/mips/mach-jz47xx/start.S
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Startup Code for MIPS32 XBURST CPU-core
*
* Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
*/
#include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#include <asm/cache.h>
#include <mach/jz4780.h>
.set noreorder
.globl _start
.text
_start:
#ifdef CONFIG_SPL_BUILD
/* magic value ("MSPL") */
.word 0x4d53504c
/* Invalidate BTB */
mfc0 t0, CP0_CONFIG, 7
nop
ori t0, 2
mtc0 t0, CP0_CONFIG, 7
nop
/*
* CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
*/
li t0, 0x0040FC04
mtc0 t0, CP0_STATUS
/* CAUSE register */
/* IV=1, use the specical interrupt vector (0x200) */
li t1, 0x00800000
mtc0 t1, CP0_CAUSE
#ifdef CONFIG_SOC_JZ4780
/* enable bridge radical mode */
la t0, CPM_BASE
lw t1, 0x24(t0)
ori t1, t1, 0x22
sw t1, 0x24(t0)
#endif
/* Set up stack */
li sp, CONFIG_SPL_STACK
b board_init_f
nop
#ifdef CONFIG_SOC_JZ4780
.globl enable_caches
.ent enable_caches
enable_caches:
mtc0 zero, CP0_TAGLO
mtc0 zero, CP0_TAGHI
li t0, KSEG0
addu t1, t0, CONFIG_SYS_DCACHE_SIZE
1:
cache INDEX_STORE_TAG_D, 0(t0)
bne t0, t1, 1b
addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
li t0, KSEG0
addu t1, t0, CONFIG_SYS_ICACHE_SIZE
2:
cache INDEX_STORE_TAG_I, 0(t0)
bne t0, t1, 2b
addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
/* Invalidate BTB */
mfc0 t0, CP0_CONFIG, 7
nop
ori t0, 2
mtc0 t0, CP0_CONFIG, 7
nop
/* Enable caches */
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
nop
jr ra
nop
.end enable_caches
#endif /* CONFIG_SOC_JZ4780 */
#endif /* !CONFIG_SPL_BUILD */
|
genetel200/u-boot
| 1,691
|
arch/mips/mach-mscc/lowlevel_init_luton.S
|
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2018 Microsemi Corporation
*/
#include <asm/asm.h>
#include <asm/regdef.h>
#define BASE_MACRO 0x600a0000
#define REG_OFFSET(t, o) (t + (o*4))
#define REG_MACRO(x) REG_OFFSET(BASE_MACRO, x)
#define BIT(nr) (1 << (nr))
#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 REG_MACRO(6)
#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS BIT(0)
#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 REG_MACRO(2)
#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 REG_MACRO(0)
#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV (0x3F << 6)
#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(x) (x << 6)
.set noreorder
LEAF(pll_init)
/* Make sure PLL is locked */
lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
bne v1, zero, 1f
nop
/* Black magic from frontend */
li v1, 0x00610400
sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
li v1, 0x00610c00
sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
li v1, 0x00610800
sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
li v1, 0x00610000
sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
/* Wait for lock */
2: lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
/* Keep looping if zero (no lock bit yet) */
beq v1, zero, 2b
nop
/* Setup PLL CPU clock divider for 416MHz */
1: lw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0
/* Keep reserved bits */
li v1, ~MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV
and v0, v0, v1
/* Set code 6 ~ 416.66 MHz */
ori v0, v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(6)
sw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0
jr ra
nop
END(pll_init)
|
genetel200/u-boot
| 5,261
|
arch/mips/cpu/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#ifndef CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_SP_OFFSET)
#endif
#ifdef CONFIG_32BIT
# define MIPS_RELOC 3
# define STATUS_SET 0
#endif
#ifdef CONFIG_64BIT
# ifdef CONFIG_SYS_LITTLE_ENDIAN
# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
# else
# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
# endif
# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
# define STATUS_SET ST0_KX
#endif
.set noreorder
.macro init_wr sel
MTC0 zero, CP0_WATCHLO,\sel
mtc0 t1, CP0_WATCHHI,\sel
mfc0 t0, CP0_WATCHHI,\sel
bgez t0, wr_done
nop
.endm
.macro uhi_mips_exception
move k0, t9 # preserve t9 in k0
move k1, a0 # preserve a0 in k1
li t9, 15 # UHI exception operation
li a0, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
.endm
.macro setup_stack_gd
li t0, -16
PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
and sp, t1, t0 # force 16 byte alignment
PTR_SUBU \
sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0 # force 16 byte alignment
move k0, sp # save gd pointer
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_SUBU \
sp, sp, t2 # reserve space for early malloc
and sp, sp, t0 # force 16 byte alignment
#endif
move fp, sp
/* Clear gd */
move t0, k0
1:
PTR_S zero, 0(t0)
blt t0, t1, 1b
PTR_ADDIU t0, PTRSIZE
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
#endif
.endm
ENTRY(_start)
/* U-Boot entry point */
b reset
mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
#if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG)
/*
* Store some board-specific boot configuration. This is used by some
* MIPS systems like Malta.
*/
.org 0x10
.word CONFIG_MIPS_BOOT_CONFIG_WORD0
.word CONFIG_MIPS_BOOT_CONFIG_WORD1
#endif
#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
/*
* Exception vector entry points. When running from ROM, an exception
* cannot be handled. Halt execution and transfer control to debugger,
* if one is attached.
*/
.org 0x200
/* TLB refill, 32 bit task */
uhi_mips_exception
.org 0x280
/* XTLB refill, 64 bit task */
uhi_mips_exception
.org 0x300
/* Cache error exception */
uhi_mips_exception
.org 0x380
/* General exception */
uhi_mips_exception
.org 0x400
/* Catch interrupt exceptions */
uhi_mips_exception
.org 0x480
/* EJTAG debug exception */
1: b 1b
nop
.org 0x500
#endif
reset:
#if __mips_isa_rev >= 6
mfc0 t0, CP0_CONFIG, 5
and t0, t0, MIPS_CONF5_VP
beqz t0, 1f
nop
b 2f
mfc0 t0, CP0_GLOBALNUMBER
#endif
#ifdef CONFIG_ARCH_BMIPS
1: mfc0 t0, CP0_DIAGNOSTIC, 3
and t0, t0, (1 << 31)
#else
1: mfc0 t0, CP0_EBASE
and t0, t0, EBASE_CPUNUM
#endif
/* Hang if this isn't the first CPU in the system */
2: beqz t0, 4f
nop
3: wait
b 3b
nop
/* Init CP0 Status */
4: mfc0 t0, CP0_STATUS
and t0, ST0_IMPL
or t0, ST0_BEV | ST0_ERL | STATUS_SET
mtc0 t0, CP0_STATUS
/*
* Check whether CP0 Config1 is implemented. If not continue
* with legacy Watch register initialization.
*/
mfc0 t0, CP0_CONFIG
bgez t0, wr_legacy
nop
/*
* Check WR bit in CP0 Config1 to determine if Watch registers
* are implemented.
*/
mfc0 t0, CP0_CONFIG, 1
andi t0, (1 << 3)
beqz t0, wr_done
nop
/* Clear Watch Status bits and disable watch exceptions */
li t1, 0x7 # Clear I, R and W conditions
init_wr 0
init_wr 1
init_wr 2
init_wr 3
init_wr 4
init_wr 5
init_wr 6
init_wr 7
b wr_done
nop
wr_legacy:
MTC0 zero, CP0_WATCHLO
mtc0 zero, CP0_WATCHHI
wr_done:
/* Clear WP, IV and SW interrupts */
mtc0 zero, CP0_CAUSE
/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
mtc0 zero, CP0_COMPARE
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
mfc0 t0, CP0_CONFIG
and t0, t0, MIPS_CONF_IMPL
or t0, t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
ehb
#endif
#ifdef CONFIG_MIPS_CM
PTR_LA t9, mips_cm_map
jalr t9
nop
#endif
#ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
/* Set up initial stack and global data */
setup_stack_gd
# ifdef CONFIG_DEBUG_UART
/* Earliest point to set up debug uart */
PTR_LA t9, debug_uart_init
jalr t9
nop
# endif
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Initialize any external memory */
PTR_LA t9, lowlevel_init
jalr t9
nop
# endif
/* Initialize caches... */
PTR_LA t9, mips_cache_reset
jalr t9
nop
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Initialize any external memory */
PTR_LA t9, lowlevel_init
jalr t9
nop
# endif
#endif
#ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
/* Set up initial stack and global data */
setup_stack_gd
# ifdef CONFIG_DEBUG_UART
/* Earliest point to set up debug uart */
PTR_LA t9, debug_uart_init
jalr t9
nop
# endif
#endif
move a0, zero # a0 <-- boot_flags = 0
PTR_LA t9, board_init_f
jr t9
move ra, zero
END(_start)
|
genetel200/u-boot
| 5,934
|
arch/mips/mach-ath79/qca953x/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
* Based on Atheros LSDK/QSDK
*/
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <mach/ar71xx_regs.h>
#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
(((0x3F & divint) << 10) | \
((0x1F & refdiv) << 16) | \
((0x1 & range) << 21) | \
((0x7 & outdiv) << 23) )
#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
(((0x3 & (cpudiv - 1)) << 5) | \
((0x3 & (ddrdiv - 1)) << 10) | \
((0x3 & (ahbdiv - 1)) << 15) )
#define SET_FIELD(name, v) (((v) & QCA953X_##name##_MASK) << \
QCA953X_##name##_SHIFT)
#define DPLL2_KI(v) SET_FIELD(SRIF_DPLL2_KI, v)
#define DPLL2_KD(v) SET_FIELD(SRIF_DPLL2_KD, v)
#define DPLL2_PWD QCA953X_SRIF_DPLL2_PWD
#define MK_DPLL2(ki, kd) (DPLL2_KI(ki) | DPLL2_KD(kd) | DPLL2_PWD)
#define PLL_CPU_NFRAC(v) SET_FIELD(PLL_CPU_CONFIG_NFRAC, v)
#define PLL_CPU_NINT(v) SET_FIELD(PLL_CPU_CONFIG_NINT, v)
#define PLL_CPU_REFDIV(v) SET_FIELD(PLL_CPU_CONFIG_REFDIV, v)
#define PLL_CPU_OUTDIV(v) SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v)
#define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \
(PLL_CPU_NFRAC(frac) | \
PLL_CPU_NINT(nint) | \
PLL_CPU_REFDIV(ref) | \
PLL_CPU_OUTDIV(outdiv))
#define PLL_DDR_NFRAC(v) SET_FIELD(PLL_DDR_CONFIG_NFRAC, v)
#define PLL_DDR_NINT(v) SET_FIELD(PLL_DDR_CONFIG_NINT, v)
#define PLL_DDR_REFDIV(v) SET_FIELD(PLL_DDR_CONFIG_REFDIV, v)
#define PLL_DDR_OUTDIV(v) SET_FIELD(PLL_DDR_CONFIG_OUTDIV, v)
#define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \
(PLL_DDR_NFRAC(frac) | \
PLL_DDR_REFDIV(ref) | \
PLL_DDR_NINT(nint) | \
PLL_DDR_OUTDIV(outdiv) | \
QCA953X_PLL_CONFIG_PWD)
#define PLL_CPU_CONF_VAL MK_PLL_CPU_CONF(0, 26, 1, 0)
#define PLL_DDR_CONF_VAL MK_PLL_DDR_CONF(0, 15, 1, 0)
#define PLL_CLK_CTRL_PLL_BYPASS (QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS | \
QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS | \
QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
#define PLL_CLK_CTRL_CPU_DIV(v) SET_FIELD(PLL_CLK_CTRL_CPU_POST_DIV, v)
#define PLL_CLK_CTRL_DDR_DIV(v) SET_FIELD(PLL_CLK_CTRL_DDR_POST_DIV, v)
#define PLL_CLK_CTRL_AHB_DIV(v) SET_FIELD(PLL_CLK_CTRL_AHB_POST_DIV, v)
#define MK_PLL_CLK_CTRL(cpu, ddr, ahb) \
(PLL_CLK_CTRL_CPU_DIV(cpu) | \
PLL_CLK_CTRL_DDR_DIV(ddr) | \
PLL_CLK_CTRL_AHB_DIV(ahb))
#define PLL_CLK_CTRL_VAL (MK_PLL_CLK_CTRL(0, 0, 2) | \
PLL_CLK_CTRL_PLL_BYPASS | \
QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | \
QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
#define PLL_DDR_DIT_FRAC_MAX(v) SET_FIELD(PLL_DDR_DIT_FRAC_MAX, v)
#define PLL_DDR_DIT_FRAC_MIN(v) SET_FIELD(PLL_DDR_DIT_FRAC_MIN, v)
#define PLL_DDR_DIT_FRAC_STEP(v) SET_FIELD(PLL_DDR_DIT_FRAC_STEP, v)
#define PLL_DDR_DIT_UPD_CNT(v) SET_FIELD(PLL_DDR_DIT_UPD_CNT, v)
#define PLL_CPU_DIT_FRAC_MAX(v) SET_FIELD(PLL_CPU_DIT_FRAC_MAX, v)
#define PLL_CPU_DIT_FRAC_MIN(v) SET_FIELD(PLL_CPU_DIT_FRAC_MIN, v)
#define PLL_CPU_DIT_FRAC_STEP(v) SET_FIELD(PLL_CPU_DIT_FRAC_STEP, v)
#define PLL_CPU_DIT_UPD_CNT(v) SET_FIELD(PLL_CPU_DIT_UPD_CNT, v)
#define MK_PLL_DDR_DIT_FRAC(max, min, step, cnt) \
(QCA953X_PLL_DIT_FRAC_EN | \
PLL_DDR_DIT_FRAC_MAX(max) | \
PLL_DDR_DIT_FRAC_MIN(min) | \
PLL_DDR_DIT_FRAC_STEP(step) | \
PLL_DDR_DIT_UPD_CNT(cnt))
#define MK_PLL_CPU_DIT_FRAC(max, min, step, cnt) \
(QCA953X_PLL_DIT_FRAC_EN | \
PLL_CPU_DIT_FRAC_MAX(max) | \
PLL_CPU_DIT_FRAC_MIN(min) | \
PLL_CPU_DIT_FRAC_STEP(step) | \
PLL_CPU_DIT_UPD_CNT(cnt))
#define PLL_CPU_DIT_FRAC_VAL MK_PLL_CPU_DIT_FRAC(63, 0, 1, 15)
#define PLL_DDR_DIT_FRAC_VAL MK_PLL_DDR_DIT_FRAC(763, 635, 1, 15)
.text
.set noreorder
LEAF(lowlevel_init)
/* RTC Reset */
li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
li t2, 0x08000000
or t1, t1, t2
sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
nop
lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
li t2, 0xf7ffffff
and t1, t1, t2
sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
nop
/* RTC Force Wake */
li t0, CKSEG1ADDR(QCA953X_RTC_BASE)
li t1, 0x01
sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
nop
nop
/* Wait for RTC in on state */
1:
lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
andi t1, t1, 0x02
beqz t1, 1b
nop
li t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
li t1, MK_DPLL2(2, 16)
sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
sw t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0)
sw t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
sw t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
ori t1, PLL_CLK_CTRL_PLL_BYPASS
sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
nop
li t1, PLL_CPU_CONF_VAL
sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
nop
li t1, PLL_DDR_CONF_VAL
sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
nop
li t1, PLL_CLK_CTRL_VAL
sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
nop
lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
li t2, ~QCA953X_PLL_CONFIG_PWD
and t1, t1, t2
sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
nop
lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
li t2, ~QCA953X_PLL_CONFIG_PWD
and t1, t1, t2
sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
nop
lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
li t2, ~PLL_CLK_CTRL_PLL_BYPASS
and t1, t1, t2
sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
nop
li t1, PLL_DDR_DIT_FRAC_VAL
sw t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0)
nop
li t1, PLL_CPU_DIT_FRAC_VAL
sw t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0)
nop
li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
lui t1, 0x03fc
sw t1, 0xb4(t0)
nop
jr ra
nop
END(lowlevel_init)
|
genetel200/u-boot
| 6,733
|
arch/mips/mach-ath79/ar933x/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
* Based on Atheros LSDK/QSDK and u-boot_mod project
*/
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <mach/ar71xx_regs.h>
#define SET_BIT(val, bit) ((val) | (1 << (bit)))
#define SET_PLL_PD(val) SET_BIT(val, 30)
#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16)
#define PLL_BYPASS(val) SET_BIT(val, 2)
#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
(((0x3F & divint) << 10) | \
((0x1F & refdiv) << 16) | \
((0x1 & range) << 21) | \
((0x7 & outdiv) << 23) )
#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
(((0x3 & (cpudiv - 1)) << 5) | \
((0x3 & (ddrdiv - 1)) << 10) | \
((0x3 & (ahbdiv - 1)) << 15) )
/*
* PLL_CPU_CONFIG_VAL
*
* Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
* After PLL configuration we need to clear this bit
*
* Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
*
* bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL)
* => 32 (0x20) VCOOUT = XTAL * DIV_INT
* bits 16..20 (5bit) REFDIV (Reference clock divider)
* => 1 (0x1) [Must start at values 1]
* bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL)
* => 0 (0x0) [Doesn't impact clock values]
* bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output)
* => 1 (0x1) [0 is illegal!]
* PLLOUT = VCOOUT * (1/2^OUTDIV)
*/
/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1)
/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1)
/*
* PLL_CLK_CONTROL_VAL
*
* In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
* After PLL configuration we need to clear this bit
*
* Values written into CPU Clock Control Register CLOCK_CONTROL
*
* bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test.
* Software must enable the CPU PLL for normal and
* then set this bit to 0)
* bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1)
* CPU_CLK = PLLOUT / CPU_POST_DIV
* bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1)
* DDR_CLK = PLLOUT / DDR_POST_DIV
* bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2)
* AHB_CLK = PLLOUT / AHB_POST_DIV
*
*/
#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
.text
.set noreorder
LEAF(lowlevel_init)
/* These three WLAN_RESET will avoid original issue */
li t3, 0x03
1:
li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
ori t1, t1, 0x0800
sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
nop
lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
li t2, 0xfffff7ff
and t1, t1, t2
sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
nop
addi t3, t3, -1
bnez t3, 1b
nop
li t2, 0x20
2:
beqz t2, 1b
nop
addi t2, t2, -1
lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
andi t1, t5, 0x10
bnez t1, 2b
nop
li t1, 0x02110E
sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
nop
/* RTC Force Wake */
li t0, CKSEG1ADDR(AR933X_RTC_BASE)
li t1, 0x03
sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
nop
nop
/* RTC Reset */
li t1, 0x00
sw t1, AR933X_RTC_REG_RESET(t0)
nop
nop
li t1, 0x01
sw t1, AR933X_RTC_REG_RESET(t0)
nop
nop
/* Wait for RTC in on state */
1:
lw t1, AR933X_RTC_REG_STATUS(t0)
andi t1, t1, 0x02
beqz t1, 1b
nop
/* Program ki/kd */
li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
andi t1, t5, 0x01 # t5 BOOT_STRAP
bnez t1, 1f
nop
li t1, 0x19e82f01
b 2f
nop
1:
li t1, 0x18e82f01
2:
sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
/* Program phase shift */
lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
li t2, 0xc07fffff
and t1, t1, t2
li t2, 0x800000
or t1, t1, t2
sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
nop
/* in some cases, the SoC doesn't start with higher clock on AHB */
li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
nop
/* Set SETTLE_TIME in CPU PLL */
andi t1, t5, 0x01 # t5 BOOT_STRAP
bnez t1, 1f
nop
li t1, 0x0352
b 2f
nop
1:
li t1, 0x0550
2:
sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
nop
/* Set nint, frac, refdiv, outdiv, range according to xtal */
0:
andi t1, t5, 0x01 # t5 BOOT_STRAP
bnez t1, 1f
nop
li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
b 2f
nop
1:
li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
2:
sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
nop
1:
lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
li t2, 0x80000000
and t1, t1, t2
bnez t1, 1b
nop
/* Put frac bit19:10 configuration */
li t1, 0x1003E8
sw t1, AR933X_PLL_DITHER_FRAC_REG(t0)
nop
/* Clear PLL power down bit in CPU PLL configuration */
andi t1, t5, 0x01 # t5 BOOT_STRAP
bnez t1, 1f
nop
li t1, PLL_CPU_CONFIG_VAL_25M
b 2f
nop
1:
li t1, PLL_CPU_CONFIG_VAL_40M
2:
sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
nop
/* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
1:
lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
li t2, 0x80000000
and t1, t1, t2
bnez t1, 1b
nop
/* Confirm DDR PLL lock */
li t3, 100
li t4, 0
2:
addi t4, t4, 1
bgt t4, t3, 0b
nop
li t3, 5
3:
/* Clear do_meas */
li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
li t2, 0xBFFFFFFF
and t1, t1, t2
sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
nop
li t2, 10
1:
subu t2, t2, 1
bnez t2, 1b
nop
/* Set do_meas */
li t2, 0x40000000
or t1, t1, t2
sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
nop
/* Check meas_done */
1:
lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
andi t1, t1, 0x8
beqz t1, 1b
nop
lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
li t2, 0x007FFFF8
and t1, t1, t2
srl t1, t1, 3
li t2, 0x4000
bgt t1, t2, 2b
nop
addi t3, t3, -1
bnez t3, 3b
nop
/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
li t1, PLL_CLK_CONTROL_VAL
sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
nop
nop
jr ra
nop
END(lowlevel_init)
|
genetel200/u-boot
| 2,202
|
arch/arm/mach-tegra/psci.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, NVIDIA
* Copyright (C) 2015, Siemens AG
*
* Authors:
* Thierry Reding <treding@nvidia.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*/
#include <linux/linkage.h>
#include <asm/macro.h>
#include <asm/psci.h>
.pushsection ._secure.text, "ax"
.arch_extension sec
#define TEGRA_SB_CSR_0 0x6000c200
#define NS_RST_VEC_WR_DIS (1 << 1)
#define TEGRA_RESET_EXCEPTION_VECTOR 0x6000f100
#define TEGRA_FLOW_CTRL_BASE 0x60007000
#define FLOW_CTRL_CPU_CSR 0x08
#define CSR_ENABLE (1 << 0)
#define CSR_IMMEDIATE_WAKE (1 << 3)
#define CSR_WAIT_WFI_SHIFT 8
#define FLOW_CTRL_CPU1_CSR 0x18
@ converts CPU ID into FLOW_CTRL_CPUn_CSR offset
.macro get_csr_reg cpu, ofs, tmp
cmp \cpu, #0 @ CPU0?
lsl \tmp, \cpu, #3 @ multiple by 8 (register offset CPU1-3)
moveq \ofs, #FLOW_CTRL_CPU_CSR
addne \ofs, \tmp, #FLOW_CTRL_CPU1_CSR - 8
.endm
ENTRY(psci_arch_init)
mov r6, lr
mrc p15, 0, r5, c1, c1, 0 @ Read SCR
bic r5, r5, #1 @ Secure mode
mcr p15, 0, r5, c1, c1, 0 @ Write SCR
isb
@ lock reset vector for non-secure
ldr r4, =TEGRA_SB_CSR_0
ldr r5, [r4]
orr r5, r5, #NS_RST_VEC_WR_DIS
str r5, [r4]
bl psci_get_cpu_id @ CPU ID => r0
adr r5, _sys_clock_freq
cmp r0, #0
mrceq p15, 0, r7, c14, c0, 0 @ read CNTFRQ from CPU0
streq r7, [r5]
ldrne r7, [r5]
mcrne p15, 0, r7, c14, c0, 0 @ write CNTFRQ to CPU1..3
bx r6
ENDPROC(psci_arch_init)
_sys_clock_freq:
.word 0
ENTRY(psci_cpu_off)
bl psci_cpu_off_common
bl psci_get_cpu_id @ CPU ID => r0
get_csr_reg r0, r2, r3
ldr r6, =TEGRA_FLOW_CTRL_BASE
mov r5, #(CSR_ENABLE)
mov r4, #(1 << CSR_WAIT_WFI_SHIFT)
add r5, r4, lsl r0
str r5, [r6, r2]
_loop: wfi
b _loop
ENDPROC(psci_cpu_off)
ENTRY(psci_cpu_on)
push {r4, r5, r6, lr}
mov r4, r1
mov r0, r1
mov r1, r2
mov r2, r3
bl psci_save @ store target PC and context id
mov r1, r4
ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
ldr r5, =psci_cpu_entry
str r5, [r6]
get_csr_reg r1, r2, r3
ldr r6, =TEGRA_FLOW_CTRL_BASE
mov r5, #(CSR_IMMEDIATE_WAKE | CSR_ENABLE)
str r5, [r6, r2]
mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
pop {r4, r5, r6, pc}
ENDPROC(psci_cpu_on)
.popsection
|
genetel200/u-boot
| 1,392
|
arch/arm/mach-mvebu/lowlevel_spl.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
#include <config.h>
#include <linux/linkage.h>
ENTRY(save_boot_params)
stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
str sp, [r12]
b save_boot_params_ret
ENDPROC(save_boot_params)
ENTRY(return_to_bootrom)
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
ldr sp, [r12]
mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */
ENDPROC(return_to_bootrom)
/*
* cache_inv - invalidate Cache line
* r0 - dest
*/
.global cache_inv
.type cache_inv, %function
cache_inv:
stmfd sp!, {r1-r12}
mcr p15, 0, r0, c7, c6, 1
ldmfd sp!, {r1-r12}
bx lr
/*
* flush_l1_v6 - l1 cache clean invalidate
* r0 - dest
*/
.global flush_l1_v6
.type flush_l1_v6, %function
flush_l1_v6:
stmfd sp!, {r1-r12}
mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
ldmfd sp!, {r1-r12}
bx lr
/*
* flush_l1_v7 - l1 cache clean invalidate
* r0 - dest
*/
.global flush_l1_v7
.type flush_l1_v7, %function
flush_l1_v7:
stmfd sp!, {r1-r12}
dmb /* @data memory barrier */
mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
dsb /* @data sync barrier */
ldmfd sp!, {r1-r12}
bx lr
|
genetel200/u-boot
| 2,578
|
arch/arm/lib/relocate_64.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - common relocation function for AArch64 U-Boot
*
* (C) Copyright 2013
* Albert ARIBAUD <albert.u.boot@aribaud.net>
* David Feng <fenghua@phytium.com.cn>
*/
#include <asm-offsets.h>
#include <config.h>
#include <elf.h>
#include <linux/linkage.h>
#include <asm/macro.h>
/*
* void relocate_code (addr_moni)
*
* This function relocates the monitor code.
* x0 holds the destination address.
*/
ENTRY(relocate_code)
stp x29, x30, [sp, #-32]! /* create a stack frame */
mov x29, sp
str x0, [sp, #16]
/*
* Copy u-boot from flash to RAM
*/
adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */
subs x9, x0, x1 /* x8 <- Run to copy offset */
b.eq relocate_done /* skip relocation */
/*
* Don't ldr x1, __image_copy_start here, since if the code is already
* running at an address other than it was linked to, that instruction
* will load the relocated value of __image_copy_start. To
* correctly apply relocations, we need to know the linked value.
*
* Linked &__image_copy_start, which we know was at
* CONFIG_SYS_TEXT_BASE, which is stored in _TEXT_BASE, as a non-
* relocated value, since it isn't a symbol reference.
*/
ldr x1, _TEXT_BASE /* x1 <- Linked &__image_copy_start */
subs x9, x0, x1 /* x9 <- Link to copy offset */
adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */
adr x2, __image_copy_end /* x2 <- Run &__image_copy_end */
copy_loop:
ldp x10, x11, [x1], #16 /* copy from source address [x1] */
stp x10, x11, [x0], #16 /* copy to target address [x0] */
cmp x1, x2 /* until source end address [x2] */
b.lo copy_loop
str x0, [sp, #24]
/*
* Fix .rela.dyn relocations
*/
adr x2, __rel_dyn_start /* x2 <- Run &__rel_dyn_start */
adr x3, __rel_dyn_end /* x3 <- Run &__rel_dyn_end */
fixloop:
ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */
ldr x4, [x2], #8 /* x4 <- addend */
and x1, x1, #0xffffffff
cmp x1, #R_AARCH64_RELATIVE
bne fixnext
/* relative fix: store addend plus offset at dest location */
add x0, x0, x9
add x4, x4, x9
str x4, [x0]
fixnext:
cmp x2, x3
b.lo fixloop
relocate_done:
switch_el x1, 3f, 2f, 1f
bl hang
3: mrs x0, sctlr_el3
b 0f
2: mrs x0, sctlr_el2
b 0f
1: mrs x0, sctlr_el1
0: tbz w0, #2, 5f /* skip flushing cache if disabled */
tbz w0, #12, 4f /* skip invalidating i-cache if disabled */
ic iallu /* i-cache invalidate all */
isb sy
4: ldp x0, x1, [sp, #16]
bl __asm_flush_dcache_range
bl __asm_flush_l3_dcache
5: ldp x29, x30, [sp],#32
ret
ENDPROC(relocate_code)
|
genetel200/u-boot
| 3,817
|
arch/arm/lib/crt0_aarch64_efi.S
|
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-2-Clause */
/*
* crt0-efi-aarch64.S - PE/COFF header for aarch64 EFI applications
*
* Copright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
*
*
* This file is taken and modified from the gnu-efi project.
*/
#include <asm-generic/pe.h>
.section .text.head
/*
* Magic "MZ" signature for PE/COFF
*/
.globl ImageBase
ImageBase:
.ascii "MZ"
.skip 58 /* 'MZ' + pad + offset == 64 */
.long pe_header - ImageBase /* Offset to the PE header */
pe_header:
.ascii "PE"
.short 0
coff_header:
.short 0xaa64 /* AArch64 */
.short 2 /* nr_sections */
.long 0 /* TimeDateStamp */
.long 0 /* PointerToSymbolTable */
.long 0 /* NumberOfSymbols */
.short section_table - optional_header /* SizeOfOptionalHeader */
/* Characteristics */
.short (IMAGE_FILE_EXECUTABLE_IMAGE | \
IMAGE_FILE_LINE_NUMS_STRIPPED | \
IMAGE_FILE_LOCAL_SYMS_STRIPPED | \
IMAGE_FILE_DEBUG_STRIPPED)
optional_header:
.short 0x20b /* PE32+ format */
.byte 0x02 /* MajorLinkerVersion */
.byte 0x14 /* MinorLinkerVersion */
.long _edata - _start /* SizeOfCode */
.long 0 /* SizeOfInitializedData */
.long 0 /* SizeOfUninitializedData */
.long _start - ImageBase /* AddressOfEntryPoint */
.long _start - ImageBase /* BaseOfCode */
extra_header_fields:
.quad 0 /* ImageBase */
.long 0x20 /* SectionAlignment */
.long 0x8 /* FileAlignment */
.short 0 /* MajorOperatingSystemVersion */
.short 0 /* MinorOperatingSystemVersion */
.short 0 /* MajorImageVersion */
.short 0 /* MinorImageVersion */
.short 0 /* MajorSubsystemVersion */
.short 0 /* MinorSubsystemVersion */
.long 0 /* Win32VersionValue */
.long _edata - ImageBase /* SizeOfImage */
/*
* Everything before the kernel image is considered part of the header
*/
.long _start - ImageBase /* SizeOfHeaders */
.long 0 /* CheckSum */
.short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */
.short 0 /* DllCharacteristics */
.quad 0 /* SizeOfStackReserve */
.quad 0 /* SizeOfStackCommit */
.quad 0 /* SizeOfHeapReserve */
.quad 0 /* SizeOfHeapCommit */
.long 0 /* LoaderFlags */
.long 0x6 /* NumberOfRvaAndSizes */
.quad 0 /* ExportTable */
.quad 0 /* ImportTable */
.quad 0 /* ResourceTable */
.quad 0 /* ExceptionTable */
.quad 0 /* CertificationTable */
.quad 0 /* BaseRelocationTable */
/* Section table */
section_table:
/*
* The EFI application loader requires a relocation section
* because EFI applications must be relocatable. This is a
* dummy section as far as we are concerned.
*/
.ascii ".reloc"
.byte 0
.byte 0 /* end of 0 padding of section name */
.long 0
.long 0
.long 0 /* SizeOfRawData */
.long 0 /* PointerToRawData */
.long 0 /* PointerToRelocations */
.long 0 /* PointerToLineNumbers */
.short 0 /* NumberOfRelocations */
.short 0 /* NumberOfLineNumbers */
.long 0x42100040 /* Characteristics (section flags) */
.ascii ".text"
.byte 0
.byte 0
.byte 0 /* end of 0 padding of section name */
.long _edata - _start /* VirtualSize */
.long _start - ImageBase /* VirtualAddress */
.long _edata - _start /* SizeOfRawData */
.long _start - ImageBase /* PointerToRawData */
.long 0 /* PointerToRelocations (0 for executables) */
.long 0 /* PointerToLineNumbers (0 for executables) */
.short 0 /* NumberOfRelocations (0 for executables) */
.short 0 /* NumberOfLineNumbers (0 for executables) */
.long 0xe0500020 /* Characteristics (section flags) */
_start:
stp x29, x30, [sp, #-32]!
mov x29, sp
stp x0, x1, [sp, #16]
adr x0, ImageBase
adrp x1, _DYNAMIC
add x1, x1, #:lo12:_DYNAMIC
bl _relocate
cbnz x0, 0f
ldp x0, x1, [sp, #16]
bl efi_main
0: ldp x29, x30, [sp], #32
ret
|
genetel200/u-boot
| 5,062
|
arch/arm/lib/gic_64.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* GIC Initialization Routines.
*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/macro.h>
/*************************************************************************
*
* void gic_init_secure(DistributorBase);
*
* Initialize secure copy of GIC at EL3.
*
*************************************************************************/
ENTRY(gic_init_secure)
/*
* Initialize Distributor
* x0: Distributor Base
*/
#if defined(CONFIG_GICV3)
mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */
/* EnableGrp1S | ARE_S | ARE_NS */
str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
ldr w9, [x0, GICD_TYPER]
and w10, w9, #0x1f /* ITLinesNumber */
cbz w10, 1f /* No SPIs */
add x11, x0, (GICD_IGROUPRn + 4)
add x12, x0, (GICD_IGROUPMODRn + 4)
mov w9, #~0
0: str w9, [x11], #0x4
str wzr, [x12], #0x4 /* Config SPIs as Group1NS */
sub w10, w10, #0x1
cbnz w10, 0b
#elif defined(CONFIG_GICV2)
mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */
str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
ldr w9, [x0, GICD_TYPER]
and w10, w9, #0x1f /* ITLinesNumber */
cbz w10, 1f /* No SPIs */
add x11, x0, GICD_IGROUPRn
mov w9, #~0 /* Config SPIs as Grp1 */
str w9, [x11], #0x4
0: str w9, [x11], #0x4
sub w10, w10, #0x1
cbnz w10, 0b
ldr x1, =GICC_BASE /* GICC_CTLR */
mov w0, #3 /* EnableGrp0 | EnableGrp1 */
str w0, [x1]
mov w0, #1 << 7 /* allow NS access to GICC_PMR */
str w0, [x1, #4] /* GICC_PMR */
#endif
1:
ret
ENDPROC(gic_init_secure)
/*************************************************************************
* For Gicv2:
* void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase);
* For Gicv3:
* void gic_init_secure_percpu(ReDistributorBase);
*
* Initialize secure copy of GIC at EL3.
*
*************************************************************************/
ENTRY(gic_init_secure_percpu)
#if defined(CONFIG_GICV3)
/*
* Initialize ReDistributor
* x0: ReDistributor Base
*/
mrs x10, mpidr_el1
lsr x9, x10, #32
bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */
mov x9, x0
1: ldr x11, [x9, GICR_TYPER]
lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */
cmp w10, w11
b.eq 2f
add x9, x9, #(2 << 16)
b 1b
/* x9: ReDistributor Base Address of Current CPU */
2: mov w10, #~0x2
ldr w11, [x9, GICR_WAKER]
and w11, w11, w10 /* Clear ProcessorSleep */
str w11, [x9, GICR_WAKER]
dsb st
isb
3: ldr w10, [x9, GICR_WAKER]
tbnz w10, #2, 3b /* Wait Children be Alive */
add x10, x9, #(1 << 16) /* SGI_Base */
mov w11, #~0
str w11, [x10, GICR_IGROUPRn]
str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
mov w11, #0x1 /* Enable SGI 0 */
str w11, [x10, GICR_ISENABLERn]
switch_el x10, 3f, 2f, 1f
3:
/* Initialize Cpu Interface */
mrs x10, ICC_SRE_EL3
orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
/* Allow EL2 access to ICC_SRE_EL2 */
msr ICC_SRE_EL3, x10
isb
mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
msr ICC_IGRPEN1_EL3, x10
isb
msr ICC_CTLR_EL3, xzr
isb
2:
mrs x10, ICC_SRE_EL2
orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
/* Allow EL1 access to ICC_SRE_EL1 */
msr ICC_SRE_EL2, x10
isb
1:
msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
isb
mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */
msr ICC_PMR_EL1, x10
isb
#elif defined(CONFIG_GICV2)
/*
* Initialize SGIs and PPIs
* x0: Distributor Base
* x1: Cpu Interface Base
*/
mov w9, #~0 /* Config SGIs and PPIs as Grp1 */
str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */
mov w9, #0x1 /* Enable SGI 0 */
str w9, [x0, GICD_ISENABLERn]
/* Initialize Cpu Interface */
mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */
/* Enable Ack Group1 Interrupt & */
/* EnableGrp0 & EnableGrp1 */
str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */
mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */
str w9, [x1, GICC_PMR]
#endif
ret
ENDPROC(gic_init_secure_percpu)
/*************************************************************************
* For Gicv2:
* void gic_kick_secondary_cpus(DistributorBase);
* For Gicv3:
* void gic_kick_secondary_cpus(void);
*
*************************************************************************/
ENTRY(gic_kick_secondary_cpus)
#if defined(CONFIG_GICV3)
mov x9, #(1 << 40)
msr ICC_ASGI1R_EL1, x9
isb
#elif defined(CONFIG_GICV2)
mov w9, #0x8000
movk w9, #0x100, lsl #16
str w9, [x0, GICD_SGIR]
#endif
ret
ENDPROC(gic_kick_secondary_cpus)
/*************************************************************************
* For Gicv2:
* void gic_wait_for_interrupt(CpuInterfaceBase);
* For Gicv3:
* void gic_wait_for_interrupt(void);
*
* Wait for SGI 0 from master.
*
*************************************************************************/
ENTRY(gic_wait_for_interrupt)
#if defined(CONFIG_GICV3)
gic_wait_for_interrupt_m x9
#elif defined(CONFIG_GICV2)
gic_wait_for_interrupt_m x0, w9
#endif
ret
ENDPROC(gic_wait_for_interrupt)
|
genetel200/u-boot
| 4,596
|
arch/arm/lib/uldivmod.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2010, Google Inc.
*
* Brought in from coreboot uldivmod.S
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* A, Q = r0 + (r1 << 32)
* B, R = r2 + (r3 << 32)
* A / B = Q ... R
*/
A_0 .req r0
A_1 .req r1
B_0 .req r2
B_1 .req r3
C_0 .req r4
C_1 .req r5
D_0 .req r6
D_1 .req r7
Q_0 .req r0
Q_1 .req r1
R_0 .req r2
R_1 .req r3
THUMB(
TMP .req r8
)
.pushsection .text.__aeabi_uldivmod, "ax"
ENTRY(__aeabi_uldivmod)
stmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
@ Test if B == 0
orrs ip, B_0, B_1 @ Z set -> B == 0
beq L_div_by_0
@ Test if B is power of 2: (B & (B - 1)) == 0
subs C_0, B_0, #1
sbc C_1, B_1, #0
tst C_0, B_0
tsteq B_1, C_1
beq L_pow2
@ Test if A_1 == B_1 == 0
orrs ip, A_1, B_1
beq L_div_32_32
L_div_64_64:
/* CLZ only exists in ARM architecture version 5 and above. */
#ifdef HAVE_CLZ
mov C_0, #1
mov C_1, #0
@ D_0 = clz A
teq A_1, #0
clz D_0, A_1
clzeq ip, A_0
addeq D_0, D_0, ip
@ D_1 = clz B
teq B_1, #0
clz D_1, B_1
clzeq ip, B_0
addeq D_1, D_1, ip
@ if clz B - clz A > 0
subs D_0, D_1, D_0
bls L_done_shift
@ B <<= (clz B - clz A)
subs D_1, D_0, #32
rsb ip, D_0, #32
movmi B_1, B_1, lsl D_0
ARM( orrmi B_1, B_1, B_0, lsr ip )
THUMB( lsrmi TMP, B_0, ip )
THUMB( orrmi B_1, B_1, TMP )
movpl B_1, B_0, lsl D_1
mov B_0, B_0, lsl D_0
@ C = 1 << (clz B - clz A)
movmi C_1, C_1, lsl D_0
ARM( orrmi C_1, C_1, C_0, lsr ip )
THUMB( lsrmi TMP, C_0, ip )
THUMB( orrmi C_1, C_1, TMP )
movpl C_1, C_0, lsl D_1
mov C_0, C_0, lsl D_0
L_done_shift:
mov D_0, #0
mov D_1, #0
@ C: current bit; D: result
#else
@ C: current bit; D: result
mov C_0, #1
mov C_1, #0
mov D_0, #0
mov D_1, #0
L_lsl_4:
cmp B_1, #0x10000000
cmpcc B_1, A_1
cmpeq B_0, A_0
bcs L_lsl_1
@ B <<= 4
mov B_1, B_1, lsl #4
orr B_1, B_1, B_0, lsr #28
mov B_0, B_0, lsl #4
@ C <<= 4
mov C_1, C_1, lsl #4
orr C_1, C_1, C_0, lsr #28
mov C_0, C_0, lsl #4
b L_lsl_4
L_lsl_1:
cmp B_1, #0x80000000
cmpcc B_1, A_1
cmpeq B_0, A_0
bcs L_subtract
@ B <<= 1
mov B_1, B_1, lsl #1
orr B_1, B_1, B_0, lsr #31
mov B_0, B_0, lsl #1
@ C <<= 1
mov C_1, C_1, lsl #1
orr C_1, C_1, C_0, lsr #31
mov C_0, C_0, lsl #1
b L_lsl_1
#endif
L_subtract:
@ if A >= B
cmp A_1, B_1
cmpeq A_0, B_0
bcc L_update
@ A -= B
subs A_0, A_0, B_0
sbc A_1, A_1, B_1
@ D |= C
orr D_0, D_0, C_0
orr D_1, D_1, C_1
L_update:
@ if A == 0: break
orrs ip, A_1, A_0
beq L_exit
@ C >>= 1
movs C_1, C_1, lsr #1
movs C_0, C_0, rrx
@ if C == 0: break
orrs ip, C_1, C_0
beq L_exit
@ B >>= 1
movs B_1, B_1, lsr #1
mov B_0, B_0, rrx
b L_subtract
L_exit:
@ Note: A, B & Q, R are aliases
mov R_0, A_0
mov R_1, A_1
mov Q_0, D_0
mov Q_1, D_1
ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
L_div_32_32:
@ Note: A_0 & r0 are aliases
@ Q_1 r1
mov r1, B_0
bl __aeabi_uidivmod
mov R_0, r1
mov R_1, #0
mov Q_1, #0
ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
L_pow2:
#ifdef HAVE_CLZ
@ Note: A, B and Q, R are aliases
@ R = A & (B - 1)
and C_0, A_0, C_0
and C_1, A_1, C_1
@ Q = A >> log2(B)
@ Note: B must not be 0 here!
clz D_0, B_0
add D_1, D_0, #1
rsbs D_0, D_0, #31
bpl L_1
clz D_0, B_1
rsb D_0, D_0, #31
mov A_0, A_1, lsr D_0
add D_0, D_0, #32
L_1:
movpl A_0, A_0, lsr D_0
ARM( orrpl A_0, A_0, A_1, lsl D_1 )
THUMB( lslpl TMP, A_1, D_1 )
THUMB( orrpl A_0, A_0, TMP )
mov A_1, A_1, lsr D_0
@ Mov back C to R
mov R_0, C_0
mov R_1, C_1
ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
#else
@ Note: A, B and Q, R are aliases
@ R = A & (B - 1)
and C_0, A_0, C_0
and C_1, A_1, C_1
@ Q = A >> log2(B)
@ Note: B must not be 0 here!
@ Count the leading zeroes in B.
mov D_0, #0
orrs B_0, B_0, B_0
@ If B is greater than 1 << 31, divide A and B by 1 << 32.
moveq A_0, A_1
moveq A_1, #0
moveq B_0, B_1
@ Count the remaining leading zeroes in B.
movs B_1, B_0, lsl #16
addeq D_0, #16
moveq B_0, B_0, lsr #16
tst B_0, #0xff
addeq D_0, #8
moveq B_0, B_0, lsr #8
tst B_0, #0xf
addeq D_0, #4
moveq B_0, B_0, lsr #4
tst B_0, #0x3
addeq D_0, #2
moveq B_0, B_0, lsr #2
tst B_0, #0x1
addeq D_0, #1
@ Shift A to the right by the appropriate amount.
rsb D_1, D_0, #32
mov Q_0, A_0, lsr D_0
ARM( orr Q_0, Q_0, A_1, lsl D_1 )
THUMB( lsl A_1, D_1 )
THUMB( orr Q_0, A_1 )
mov Q_1, A_1, lsr D_0
@ Move C to R
mov R_0, C_0
mov R_1, C_1
ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
#endif
L_div_by_0:
bl __div0
@ As wrong as it could be
mov Q_0, #0
mov Q_1, #0
mov R_0, #0
mov R_1, #0
ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
ENDPROC(__aeabi_uldivmod)
.popsection
|
genetel200/u-boot
| 3,976
|
arch/arm/lib/div64.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/arch/arm/lib/div64.S
*
* Optimized computation of 64-bit dividend / 32-bit divisor
*
* Author: Nicolas Pitre
* Created: Oct 5, 2003
* Copyright: Monta Vista Software, Inc.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#ifdef __UBOOT__
#define UNWIND(x...)
#endif
#ifdef __ARMEB__
#define xh r0
#define xl r1
#define yh r2
#define yl r3
#else
#define xl r0
#define xh r1
#define yl r2
#define yh r3
#endif
/*
* __do_div64: perform a division with 64-bit dividend and 32-bit divisor.
*
* Note: Calling convention is totally non standard for optimal code.
* This is meant to be used by do_div() from include/asm/div64.h only.
*
* Input parameters:
* xh-xl = dividend (clobbered)
* r4 = divisor (preserved)
*
* Output values:
* yh-yl = result
* xh = remainder
*
* Clobbered regs: xl, ip
*/
.pushsection .text.__do_div64, "ax"
ENTRY(__do_div64)
UNWIND(.fnstart)
@ Test for easy paths first.
subs ip, r4, #1
bls 9f @ divisor is 0 or 1
tst ip, r4
beq 8f @ divisor is power of 2
@ See if we need to handle upper 32-bit result.
cmp xh, r4
mov yh, #0
blo 3f
@ Align divisor with upper part of dividend.
@ The aligned divisor is stored in yl preserving the original.
@ The bit position is stored in ip.
#if __LINUX_ARM_ARCH__ >= 5
clz yl, r4
clz ip, xh
sub yl, yl, ip
mov ip, #1
mov ip, ip, lsl yl
mov yl, r4, lsl yl
#else
mov yl, r4
mov ip, #1
1: cmp yl, #0x80000000
cmpcc yl, xh
movcc yl, yl, lsl #1
movcc ip, ip, lsl #1
bcc 1b
#endif
@ The division loop for needed upper bit positions.
@ Break out early if dividend reaches 0.
2: cmp xh, yl
orrcs yh, yh, ip
subscs xh, xh, yl
movsne ip, ip, lsr #1
mov yl, yl, lsr #1
bne 2b
@ See if we need to handle lower 32-bit result.
3: cmp xh, #0
mov yl, #0
cmpeq xl, r4
movlo xh, xl
retlo lr
@ The division loop for lower bit positions.
@ Here we shift remainer bits leftwards rather than moving the
@ divisor for comparisons, considering the carry-out bit as well.
mov ip, #0x80000000
4: movs xl, xl, lsl #1
adcs xh, xh, xh
beq 6f
cmpcc xh, r4
5: orrcs yl, yl, ip
subcs xh, xh, r4
movs ip, ip, lsr #1
bne 4b
ret lr
@ The top part of remainder became zero. If carry is set
@ (the 33th bit) this is a false positive so resume the loop.
@ Otherwise, if lower part is also null then we are done.
6: bcs 5b
cmp xl, #0
reteq lr
@ We still have remainer bits in the low part. Bring them up.
#if __LINUX_ARM_ARCH__ >= 5
clz xh, xl @ we know xh is zero here so...
add xh, xh, #1
mov xl, xl, lsl xh
mov ip, ip, lsr xh
#else
7: movs xl, xl, lsl #1
mov ip, ip, lsr #1
bcc 7b
#endif
@ Current remainder is now 1. It is worthless to compare with
@ divisor at this point since divisor can not be smaller than 3 here.
@ If possible, branch for another shift in the division loop.
@ If no bit position left then we are done.
movs ip, ip, lsr #1
mov xh, #1
bne 4b
ret lr
8: @ Division by a power of 2: determine what that divisor order is
@ then simply shift values around
#if __LINUX_ARM_ARCH__ >= 5
clz ip, r4
rsb ip, ip, #31
#else
mov yl, r4
cmp r4, #(1 << 16)
mov ip, #0
movhs yl, yl, lsr #16
movhs ip, #16
cmp yl, #(1 << 8)
movhs yl, yl, lsr #8
addhs ip, ip, #8
cmp yl, #(1 << 4)
movhs yl, yl, lsr #4
addhs ip, ip, #4
cmp yl, #(1 << 2)
addhi ip, ip, #3
addls ip, ip, yl, lsr #1
#endif
mov yh, xh, lsr ip
mov yl, xl, lsr ip
rsb ip, ip, #32
ARM( orr yl, yl, xh, lsl ip )
THUMB( lsl xh, xh, ip )
THUMB( orr yl, yl, xh )
mov xh, xl, lsl ip
mov xh, xh, lsr ip
ret lr
@ eq -> division by 1: obvious enough...
9: moveq yl, xl
moveq yh, xh
moveq xh, #0
reteq lr
UNWIND(.fnend)
UNWIND(.fnstart)
UNWIND(.pad #4)
UNWIND(.save {lr})
Ldiv0_64:
@ Division by 0:
str lr, [sp, #-8]!
bl __div0
@ as wrong as it could be...
mov yl, #0
mov yh, #0
mov xh, #0
ldr pc, [sp], #8
UNWIND(.fnend)
ENDPROC(__do_div64)
.popsection
|
genetel200/u-boot
| 3,868
|
arch/arm/lib/crt0_arm_efi.S
|
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-2-Clause */
/*
* crt0-efi-arm.S - PE/COFF header for ARM EFI applications
*
* Copright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
*
* This file is taken and modified from the gnu-efi project.
*/
#include <asm-generic/pe.h>
.section .text.head
/*
* Magic "MZ" signature for PE/COFF
*/
.globl image_base
image_base:
.ascii "MZ"
.skip 58 /* 'MZ' + pad + offset == 64 */
.long pe_header - image_base /* Offset to the PE header */
pe_header:
.ascii "PE"
.short 0
coff_header:
.short 0x1c2 /* Mixed ARM/Thumb */
.short 2 /* nr_sections */
.long 0 /* TimeDateStamp */
.long 0 /* PointerToSymbolTable */
.long 0 /* NumberOfSymbols */
.short section_table - optional_header /* SizeOfOptionalHeader */
/* Characteristics */
.short (IMAGE_FILE_EXECUTABLE_IMAGE | \
IMAGE_FILE_LINE_NUMS_STRIPPED | \
IMAGE_FILE_LOCAL_SYMS_STRIPPED | \
IMAGE_FILE_32BIT_MACHINE | \
IMAGE_FILE_DEBUG_STRIPPED)
optional_header:
.short 0x10b /* PE32 format */
.byte 0x02 /* MajorLinkerVersion */
.byte 0x14 /* MinorLinkerVersion */
.long _edata - _start /* SizeOfCode */
.long 0 /* SizeOfInitializedData */
.long 0 /* SizeOfUninitializedData */
.long _start - image_base /* AddressOfEntryPoint */
.long _start - image_base /* BaseOfCode */
.long 0 /* BaseOfData */
extra_header_fields:
.long 0 /* image_base */
.long 0x20 /* SectionAlignment */
.long 0x8 /* FileAlignment */
.short 0 /* MajorOperatingSystemVersion */
.short 0 /* MinorOperatingSystemVersion */
.short 0 /* MajorImageVersion */
.short 0 /* MinorImageVersion */
.short 0 /* MajorSubsystemVersion */
.short 0 /* MinorSubsystemVersion */
.long 0 /* Win32VersionValue */
.long _edata - image_base /* SizeOfImage */
/*
* Everything before the kernel image is considered part of the header
*/
.long _start - image_base /* SizeOfHeaders */
.long 0 /* CheckSum */
.short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */
.short 0 /* DllCharacteristics */
.long 0 /* SizeOfStackReserve */
.long 0 /* SizeOfStackCommit */
.long 0 /* SizeOfHeapReserve */
.long 0 /* SizeOfHeapCommit */
.long 0 /* LoaderFlags */
.long 0x6 /* NumberOfRvaAndSizes */
.quad 0 /* ExportTable */
.quad 0 /* ImportTable */
.quad 0 /* ResourceTable */
.quad 0 /* ExceptionTable */
.quad 0 /* CertificationTable */
.quad 0 /* BaseRelocationTable */
section_table:
/*
* The EFI application loader requires a relocation section
* because EFI applications must be relocatable. This is a
* dummy section as far as we are concerned.
*/
.ascii ".reloc"
.byte 0
.byte 0 /* end of 0 padding of section name */
.long 0
.long 0
.long 0 /* SizeOfRawData */
.long 0 /* PointerToRawData */
.long 0 /* PointerToRelocations */
.long 0 /* PointerToLineNumbers */
.short 0 /* NumberOfRelocations */
.short 0 /* NumberOfLineNumbers */
.long 0x42100040 /* Characteristics (section flags) */
.ascii ".text"
.byte 0
.byte 0
.byte 0 /* end of 0 padding of section name */
.long _edata - _start /* VirtualSize */
.long _start - image_base /* VirtualAddress */
.long _edata - _start /* SizeOfRawData */
.long _start - image_base /* PointerToRawData */
.long 0 /* PointerToRelocations (0 for executables) */
.long 0 /* PointerToLineNumbers (0 for executables) */
.short 0 /* NumberOfRelocations (0 for executables) */
.short 0 /* NumberOfLineNumbers (0 for executables) */
.long 0xe0500020 /* Characteristics (section flags) */
_start:
stmfd sp!, {r0-r2, lr}
adr r1, .L_DYNAMIC
ldr r0, [r1]
add r1, r0, r1
adr r0, image_base
bl _relocate
teq r0, #0
bne 0f
ldmfd sp, {r0-r1}
bl efi_main
0: add sp, sp, #12
ldr pc, [sp], #4
.L_DYNAMIC:
.word _DYNAMIC - .
|
genetel200/u-boot
| 1,836
|
arch/arm/lib/ccn504.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015 Freescale Semiconductor
*
* Extracted from gic_64.S
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
/*************************************************************************
*
* void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST,
* CCI_MN_DVM_DOMAIN_CTL_SET);
*
* Add fully-coherent masters to DVM domain
*
*************************************************************************/
ENTRY(ccn504_add_masters_to_dvm)
/*
* x0: CCI_MN_BASE
* x1: CCI_MN_RNF_NODEID_LIST
* x2: CCI_MN_DVM_DOMAIN_CTL_SET
*/
/* Add fully-coherent masters to DVM domain */
ldr x9, [x0, x1]
str x9, [x0, x2]
1: ldr x10, [x0, x2]
mvn x11, x10
tst x11, x10 /* Wait for domain addition to complete */
b.ne 1b
ret
ENDPROC(ccn504_add_masters_to_dvm)
/*************************************************************************
*
* void ccn504_set_qos(CCI_Sx_QOS_CONTROL_BASE, QoS Value);
*
* Initialize QoS settings for AR/AW override.
* Right now, this function sets the same QoS value for all RN-I ports
*
*************************************************************************/
ENTRY(ccn504_set_qos)
/*
* x0: CCI_Sx_QOS_CONTROL_BASE
* x1: QoS Value
*/
/* Set all RN-I ports to QoS value denoted by x1 */
ldr x9, [x0]
mov x10, x1
orr x9, x9, x10
str x9, [x0]
ret
ENDPROC(ccn504_set_qos)
/*************************************************************************
*
* void ccn504_set_aux(CCI_AUX_CONTROL_BASE, Value);
*
* Initialize AUX control settings
*
*************************************************************************/
ENTRY(ccn504_set_aux)
/*
* x0: CCI_AUX_CONTROL_BASE
* x1: Value
*/
ldr x9, [x0]
mov x10, x1
orr x9, x9, x10
str x9, [x0]
ret
ENDPROC(ccn504_set_aux)
|
genetel200/u-boot
| 8,771
|
arch/arm/lib/lib1funcs.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
*
* Author: Nicolas Pitre <nico@fluxnic.net>
* - contributed to gcc-3.4 on Sep 30, 2003
* - adapted for the Linux kernel on Oct 2, 2003
*/
/*
* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* U-Boot compatibility bit, define empty UNWIND() macro as, since we
* do not support stack unwinding and define CONFIG_AEABI to make all
* of the functions available without diverging from Linux code.
*/
#ifdef __UBOOT__
#define UNWIND(x...)
#define CONFIG_AEABI
#endif
.macro ARM_DIV_BODY dividend, divisor, result, curbit
#if __LINUX_ARM_ARCH__ >= 5
clz \curbit, \divisor
clz \result, \dividend
sub \result, \curbit, \result
mov \curbit, #1
mov \divisor, \divisor, lsl \result
mov \curbit, \curbit, lsl \result
mov \result, #0
#else
@ Initially shift the divisor left 3 bits if possible,
@ set curbit accordingly. This allows for curbit to be located
@ at the left end of each 4 bit nibbles in the division loop
@ to save one loop in most cases.
tst \divisor, #0xe0000000
moveq \divisor, \divisor, lsl #3
moveq \curbit, #8
movne \curbit, #1
@ Unless the divisor is very big, shift it up in multiples of
@ four bits, since this is the amount of unwinding in the main
@ division loop. Continue shifting until the divisor is
@ larger than the dividend.
1: cmp \divisor, #0x10000000
cmplo \divisor, \dividend
movlo \divisor, \divisor, lsl #4
movlo \curbit, \curbit, lsl #4
blo 1b
@ For very big divisors, we must shift it a bit at a time, or
@ we will be in danger of overflowing.
1: cmp \divisor, #0x80000000
cmplo \divisor, \dividend
movlo \divisor, \divisor, lsl #1
movlo \curbit, \curbit, lsl #1
blo 1b
mov \result, #0
#endif
@ Division loop
1: cmp \dividend, \divisor
subhs \dividend, \dividend, \divisor
orrhs \result, \result, \curbit
cmp \dividend, \divisor, lsr #1
subhs \dividend, \dividend, \divisor, lsr #1
orrhs \result, \result, \curbit, lsr #1
cmp \dividend, \divisor, lsr #2
subhs \dividend, \dividend, \divisor, lsr #2
orrhs \result, \result, \curbit, lsr #2
cmp \dividend, \divisor, lsr #3
subhs \dividend, \dividend, \divisor, lsr #3
orrhs \result, \result, \curbit, lsr #3
cmp \dividend, #0 @ Early termination?
movsne \curbit, \curbit, lsr #4 @ No, any more bits to do?
movne \divisor, \divisor, lsr #4
bne 1b
.endm
.macro ARM_DIV2_ORDER divisor, order
#if __LINUX_ARM_ARCH__ >= 5
clz \order, \divisor
rsb \order, \order, #31
#else
cmp \divisor, #(1 << 16)
movhs \divisor, \divisor, lsr #16
movhs \order, #16
movlo \order, #0
cmp \divisor, #(1 << 8)
movhs \divisor, \divisor, lsr #8
addhs \order, \order, #8
cmp \divisor, #(1 << 4)
movhs \divisor, \divisor, lsr #4
addhs \order, \order, #4
cmp \divisor, #(1 << 2)
addhi \order, \order, #3
addls \order, \order, \divisor, lsr #1
#endif
.endm
.macro ARM_MOD_BODY dividend, divisor, order, spare
#if __LINUX_ARM_ARCH__ >= 5
clz \order, \divisor
clz \spare, \dividend
sub \order, \order, \spare
mov \divisor, \divisor, lsl \order
#else
mov \order, #0
@ Unless the divisor is very big, shift it up in multiples of
@ four bits, since this is the amount of unwinding in the main
@ division loop. Continue shifting until the divisor is
@ larger than the dividend.
1: cmp \divisor, #0x10000000
cmplo \divisor, \dividend
movlo \divisor, \divisor, lsl #4
addlo \order, \order, #4
blo 1b
@ For very big divisors, we must shift it a bit at a time, or
@ we will be in danger of overflowing.
1: cmp \divisor, #0x80000000
cmplo \divisor, \dividend
movlo \divisor, \divisor, lsl #1
addlo \order, \order, #1
blo 1b
#endif
@ Perform all needed subtractions to keep only the reminder.
@ Do comparisons in batch of 4 first.
subs \order, \order, #3 @ yes, 3 is intended here
blt 2f
1: cmp \dividend, \divisor
subhs \dividend, \dividend, \divisor
cmp \dividend, \divisor, lsr #1
subhs \dividend, \dividend, \divisor, lsr #1
cmp \dividend, \divisor, lsr #2
subhs \dividend, \dividend, \divisor, lsr #2
cmp \dividend, \divisor, lsr #3
subhs \dividend, \dividend, \divisor, lsr #3
cmp \dividend, #1
mov \divisor, \divisor, lsr #4
subsge \order, \order, #4
bge 1b
tst \order, #3
teqne \dividend, #0
beq 5f
@ Either 1, 2 or 3 comparison/subtractions are left.
2: cmn \order, #2
blt 4f
beq 3f
cmp \dividend, \divisor
subhs \dividend, \dividend, \divisor
mov \divisor, \divisor, lsr #1
3: cmp \dividend, \divisor
subhs \dividend, \dividend, \divisor
mov \divisor, \divisor, lsr #1
4: cmp \dividend, \divisor
subhs \dividend, \dividend, \divisor
5:
.endm
.pushsection .text.__udivsi3, "ax"
ENTRY(__udivsi3)
ENTRY(__aeabi_uidiv)
UNWIND(.fnstart)
subs r2, r1, #1
reteq lr
bcc Ldiv0
cmp r0, r1
bls 11f
tst r1, r2
beq 12f
ARM_DIV_BODY r0, r1, r2, r3
mov r0, r2
ret lr
11: moveq r0, #1
movne r0, #0
ret lr
12: ARM_DIV2_ORDER r1, r2
mov r0, r0, lsr r2
ret lr
UNWIND(.fnend)
ENDPROC(__udivsi3)
ENDPROC(__aeabi_uidiv)
.popsection
.pushsection .text.__umodsi3, "ax"
ENTRY(__umodsi3)
UNWIND(.fnstart)
subs r2, r1, #1 @ compare divisor with 1
bcc Ldiv0
cmpne r0, r1 @ compare dividend with divisor
moveq r0, #0
tsthi r1, r2 @ see if divisor is power of 2
andeq r0, r0, r2
retls lr
ARM_MOD_BODY r0, r1, r2, r3
ret lr
UNWIND(.fnend)
ENDPROC(__umodsi3)
.popsection
.pushsection .text.__divsi3, "ax"
ENTRY(__divsi3)
ENTRY(__aeabi_idiv)
UNWIND(.fnstart)
cmp r1, #0
eor ip, r0, r1 @ save the sign of the result.
beq Ldiv0
rsbmi r1, r1, #0 @ loops below use unsigned.
subs r2, r1, #1 @ division by 1 or -1 ?
beq 10f
movs r3, r0
rsbmi r3, r0, #0 @ positive dividend value
cmp r3, r1
bls 11f
tst r1, r2 @ divisor is power of 2 ?
beq 12f
ARM_DIV_BODY r3, r1, r0, r2
cmp ip, #0
rsbmi r0, r0, #0
ret lr
10: teq ip, r0 @ same sign ?
rsbmi r0, r0, #0
ret lr
11: movlo r0, #0
moveq r0, ip, asr #31
orreq r0, r0, #1
ret lr
12: ARM_DIV2_ORDER r1, r2
cmp ip, #0
mov r0, r3, lsr r2
rsbmi r0, r0, #0
ret lr
UNWIND(.fnend)
ENDPROC(__divsi3)
ENDPROC(__aeabi_idiv)
.popsection
.pushsection .text.__modsi3, "ax"
ENTRY(__modsi3)
UNWIND(.fnstart)
cmp r1, #0
beq Ldiv0
rsbmi r1, r1, #0 @ loops below use unsigned.
movs ip, r0 @ preserve sign of dividend
rsbmi r0, r0, #0 @ if negative make positive
subs r2, r1, #1 @ compare divisor with 1
cmpne r0, r1 @ compare dividend with divisor
moveq r0, #0
tsthi r1, r2 @ see if divisor is power of 2
andeq r0, r0, r2
bls 10f
ARM_MOD_BODY r0, r1, r2, r3
10: cmp ip, #0
rsbmi r0, r0, #0
ret lr
UNWIND(.fnend)
ENDPROC(__modsi3)
.popsection
#ifdef CONFIG_AEABI
.pushsection .text.__aeabi_uidivmod, "ax"
ENTRY(__aeabi_uidivmod)
UNWIND(.fnstart)
UNWIND(.save {r0, r1, ip, lr} )
stmfd sp!, {r0, r1, ip, lr}
bl __aeabi_uidiv
ldmfd sp!, {r1, r2, ip, lr}
mul r3, r0, r2
sub r1, r1, r3
ret lr
UNWIND(.fnend)
ENDPROC(__aeabi_uidivmod)
.popsection
.pushsection .text.__aeabi_uidivmod, "ax"
ENTRY(__aeabi_idivmod)
UNWIND(.fnstart)
UNWIND(.save {r0, r1, ip, lr} )
stmfd sp!, {r0, r1, ip, lr}
bl __aeabi_idiv
ldmfd sp!, {r1, r2, ip, lr}
mul r3, r0, r2
sub r1, r1, r3
ret lr
UNWIND(.fnend)
ENDPROC(__aeabi_idivmod)
.popsection
#endif
.pushsection .text.Ldiv0, "ax"
Ldiv0:
UNWIND(.fnstart)
UNWIND(.pad #4)
UNWIND(.save {lr})
str lr, [sp, #-8]!
bl __div0
mov r0, #0 @ About as wrong as it could be.
ldr pc, [sp], #8
UNWIND(.fnend)
ENDPROC(Ldiv0)
.popsection
/* Thumb-1 specialities */
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2)
.pushsection .text.__gnu_thumb1_case_sqi, "ax"
ENTRY(__gnu_thumb1_case_sqi)
push {r1}
mov r1, lr
lsrs r1, r1, #1
lsls r1, r1, #1
ldrsb r1, [r1, r0]
lsls r1, r1, #1
add lr, lr, r1
pop {r1}
bx lr
ENDPROC(__gnu_thumb1_case_sqi)
.popsection
.pushsection .text.__gnu_thumb1_case_uqi, "ax"
ENTRY(__gnu_thumb1_case_uqi)
push {r1}
mov r1, lr
lsrs r1, r1, #1
lsls r1, r1, #1
ldrb r1, [r1, r0]
lsls r1, r1, #1
add lr, lr, r1
pop {r1}
bx lr
ENDPROC(__gnu_thumb1_case_uqi)
.popsection
.pushsection .text.__gnu_thumb1_case_shi, "ax"
ENTRY(__gnu_thumb1_case_shi)
push {r0, r1}
mov r1, lr
lsrs r1, r1, #1
lsls r0, r0, #1
lsls r1, r1, #1
ldrsh r1, [r1, r0]
lsls r1, r1, #1
add lr, lr, r1
pop {r0, r1}
bx lr
ENDPROC(__gnu_thumb1_case_shi)
.popsection
.pushsection .text.__gnu_thumb1_case_uhi, "ax"
ENTRY(__gnu_thumb1_case_uhi)
push {r0, r1}
mov r1, lr
lsrs r1, r1, #1
lsls r0, r0, #1
lsls r1, r1, #1
ldrh r1, [r1, r0]
lsls r1, r1, #1
add lr, lr, r1
pop {r0, r1}
bx lr
ENDPROC(__gnu_thumb1_case_uhi)
.popsection
#endif
|
genetel200/u-boot
| 2,354
|
arch/arm/lib/memset.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/arch/arm/lib/memset.S
*
* Copyright (C) 1995-2000 Russell King
*
* ASM optimised string functions
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
.text
.align 5
.syntax unified
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD)
.thumb
.thumb_func
#endif
ENTRY(memset)
ands r3, r0, #3 @ 1 unaligned?
mov ip, r0 @ preserve r0 as return value
bne 6f @ 1
/*
* we know that the pointer in ip is aligned to a word boundary.
*/
1: orr r1, r1, r1, lsl #8
orr r1, r1, r1, lsl #16
mov r3, r1
cmp r2, #16
blt 4f
#if ! CALGN(1)+0
/*
* We need 2 extra registers for this loop - use r8 and the LR
*/
stmfd sp!, {r8, lr}
mov r8, r1
mov lr, r1
2: subs r2, r2, #64
stmiage ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
stmiage ip!, {r1, r3, r8, lr}
stmiage ip!, {r1, r3, r8, lr}
stmiage ip!, {r1, r3, r8, lr}
bgt 2b
ldmfdeq sp!, {r8, pc} @ Now <64 bytes to go.
/*
* No need to correct the count; we're only testing bits from now on
*/
tst r2, #32
stmiane ip!, {r1, r3, r8, lr}
stmiane ip!, {r1, r3, r8, lr}
tst r2, #16
stmiane ip!, {r1, r3, r8, lr}
ldmfd sp!, {r8, lr}
#else
/*
* This version aligns the destination pointer in order to write
* whole cache lines at once.
*/
stmfd sp!, {r4-r8, lr}
mov r4, r1
mov r5, r1
mov r6, r1
mov r7, r1
mov r8, r1
mov lr, r1
cmp r2, #96
tstgt ip, #31
ble 3f
and r8, ip, #31
rsb r8, r8, #32
sub r2, r2, r8
movs r8, r8, lsl #(32 - 4)
stmiacs ip!, {r4, r5, r6, r7}
stmiami ip!, {r4, r5}
tst r8, #(1 << 30)
mov r8, r1
strne r1, [ip], #4
3: subs r2, r2, #64
stmiage ip!, {r1, r3-r8, lr}
stmiage ip!, {r1, r3-r8, lr}
bgt 3b
ldmfdeq sp!, {r4-r8, pc}
tst r2, #32
stmiane ip!, {r1, r3-r8, lr}
tst r2, #16
stmiane ip!, {r4-r7}
ldmfd sp!, {r4-r8, lr}
#endif
4: tst r2, #8
stmiane ip!, {r1, r3}
tst r2, #4
strne r1, [ip], #4
/*
* When we get here, we've got less than 4 bytes to zero. We
* may have an unaligned pointer as well.
*/
5: tst r2, #2
strbne r1, [ip], #1
strbne r1, [ip], #1
tst r2, #1
strbne r1, [ip], #1
ret lr
6: subs r2, r2, #4 @ 1 do we have enough
blt 5b @ 1 bytes to align with?
cmp r3, #2 @ 1
strblt r1, [ip], #1 @ 1
strble r1, [ip], #1 @ 1
strb r1, [ip], #1 @ 1
add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
b 1b
ENDPROC(memset)
|
genetel200/u-boot
| 3,407
|
arch/arm/lib/relocate.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - common relocation function for ARM U-Boot
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <asm-offsets.h>
#include <asm/assembler.h>
#include <config.h>
#include <elf.h>
#include <linux/linkage.h>
#ifdef CONFIG_CPU_V7M
#include <asm/armv7m.h>
#endif
/*
* Default/weak exception vectors relocation routine
*
* This routine covers the standard ARM cases: normal (0x00000000),
* high (0xffff0000) and VBAR. SoCs which do not comply with any of
* the standard cases must provide their own, strong, version.
*/
.section .text.relocate_vectors,"ax",%progbits
.weak relocate_vectors
ENTRY(relocate_vectors)
#ifdef CONFIG_CPU_V7M
/*
* On ARMv7-M we only have to write the new vector address
* to VTOR register.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
ldr r1, =V7M_SCB_BASE
str r0, [r1, V7M_SCB_VTOR]
#else
#ifdef CONFIG_HAS_VBAR
/*
* If the ARM processor has the security extensions,
* use VBAR to relocate the exception vectors.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
#else
/*
* Copy the relocated exception vectors to the
* correct address
* CP15 c1 V bit gives us the location of the vectors:
* 0x00000000 or 0xFFFF0000.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
ands r2, r2, #(1 << 13)
ldreq r1, =0x00000000 /* If V=0 */
ldrne r1, =0xFFFF0000 /* If V=1 */
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
#endif
#endif
bx lr
ENDPROC(relocate_vectors)
/*
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*
* NOTE:
* To prevent the code below from containing references with an R_ARM_ABS32
* relocation record type, we never refer to linker-defined symbols directly.
* Instead, we declare literals which contain their relative location with
* respect to relocate_code, and at run time, add relocate_code back to them.
*/
ENTRY(relocate_code)
ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */
subs r4, r0, r1 /* r4 <- relocation offset */
beq relocate_done /* skip relocation */
ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */
copy_loop:
ldmia r1!, {r10-r11} /* copy from source address [r1] */
stmia r0!, {r10-r11} /* copy to target address [r0] */
cmp r1, r2 /* until source end address [r2] */
blo copy_loop
/*
* fix .rel.dyn relocations
*/
ldr r2, =__rel_dyn_start /* r2 <- SRC &__rel_dyn_start */
ldr r3, =__rel_dyn_end /* r3 <- SRC &__rel_dyn_end */
fixloop:
ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */
and r1, r1, #0xff
cmp r1, #R_ARM_RELATIVE
bne fixnext
/* relative fix: increase location by offset */
add r0, r0, r4
ldr r1, [r0]
add r1, r1, r4
str r1, [r0]
fixnext:
cmp r2, r3
blo fixloop
relocate_done:
#ifdef __XSCALE__
/*
* On xscale, icache must be invalidated and write buffers drained,
* even with cache disabled - 4.2.7 of xscale core developer's manual
*/
mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
#endif
/* ARMv4- don't know bx lr but the assembler fails to see that */
#ifdef __ARM_ARCH_4__
mov pc, lr
#else
bx lr
#endif
ENDPROC(relocate_code)
|
genetel200/u-boot
| 5,046
|
arch/arm/lib/crt0_64.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* crt0 - C-runtime startup Code for AArch64 U-Boot
*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* (C) Copyright 2012
* Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <config.h>
#include <asm-offsets.h>
#include <asm/macro.h>
#include <linux/linkage.h>
/*
* This file handles the target-independent stages of the U-Boot
* start-up where a C runtime environment is needed. Its entry point
* is _main and is branched into from the target's start.S file.
*
* _main execution sequence is:
*
* 1. Set up initial environment for calling board_init_f().
* This environment only provides a stack and a place to store
* the GD ('global data') structure, both located in some readily
* available RAM (SRAM, locked cache...). In this context, VARIABLE
* global data, initialized or not (BSS), are UNAVAILABLE; only
* CONSTANT initialized data are available. GD should be zeroed
* before board_init_f() is called.
*
* 2. Call board_init_f(). This function prepares the hardware for
* execution from system RAM (DRAM, DDR...) As system RAM may not
* be available yet, , board_init_f() must use the current GD to
* store any data which must be passed on to later stages. These
* data include the relocation destination, the future stack, and
* the future GD location.
*
* 3. Set up intermediate environment where the stack and GD are the
* ones allocated by board_init_f() in system RAM, but BSS and
* initialized non-const data are still not available.
*
* 4a.For U-Boot proper (not SPL), call relocate_code(). This function
* relocates U-Boot from its current location into the relocation
* destination computed by board_init_f().
*
* 4b.For SPL, board_init_f() just returns (to crt0). There is no
* code relocation in SPL.
*
* 5. Set up final environment for calling board_init_r(). This
* environment has BSS (initialized to 0), initialized non-const
* data (initialized to their intended value), and stack in system
* RAM (for SPL moving the stack and GD into RAM is optional - see
* CONFIG_SPL_STACK_R). GD has retained values set by board_init_f().
*
* TODO: For SPL, implement stack relocation on AArch64.
*
* 6. For U-Boot proper (not SPL), some CPUs have some work left to do
* at this point regarding memory, so call c_runtime_cpu_setup.
*
* 7. Branch to board_init_r().
*
* For more information see 'Board Initialisation Flow in README.
*/
ENTRY(_main)
/*
* Set up initial C runtime environment and call board_init_f(0).
*/
#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
ldr x0, =(CONFIG_TPL_STACK)
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr x0, =(CONFIG_SPL_STACK)
#elif defined(CONFIG_SYS_INIT_SP_BSS_OFFSET)
adr x0, __bss_start
add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET
#else
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
#endif
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
mov x0, sp
bl board_init_f_alloc_reserve
mov sp, x0
/* set up gd here, outside any C code */
mov x18, x0
bl board_init_f_init_reserve
mov x0, #0
bl board_init_f
#if !defined(CONFIG_SPL_BUILD)
/*
* Set up intermediate environment (new sp and gd) and call
* relocate_code(addr_moni). Trick here is that we'll return
* 'here' but relocated.
*/
ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
ldr x18, [x18, #GD_NEW_GD] /* x18 <- gd->new_gd */
adr lr, relocation_return
#if CONFIG_POSITION_INDEPENDENT
/* Add in link-vs-runtime offset */
adr x0, _start /* x0 <- Runtime value of _start */
ldr x9, _TEXT_BASE /* x9 <- Linked value of _start */
sub x9, x9, x0 /* x9 <- Run-vs-link offset */
add lr, lr, x9
#endif
/* Add in link-vs-relocation offset */
ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */
add lr, lr, x9 /* new return address after relocation */
ldr x0, [x18, #GD_RELOCADDR] /* x0 <- gd->relocaddr */
b relocate_code
relocation_return:
/*
* Set up final (full) environment
*/
bl c_runtime_cpu_setup /* still call old routine */
#endif /* !CONFIG_SPL_BUILD */
#if defined(CONFIG_SPL_BUILD)
bl spl_relocate_stack_gd /* may return NULL */
/* set up gd here, outside any C code, if new stack is returned */
cmp x0, #0
csel x18, x0, x18, ne
/*
* Perform 'sp = (x0 != NULL) ? x0 : sp' while working
* around the constraint that conditional moves can not
* have 'sp' as an operand
*/
mov x1, sp
cmp x0, #0
csel x0, x0, x1, ne
mov sp, x0
#endif
/*
* Clear BSS section
*/
ldr x0, =__bss_start /* this is auto-relocated! */
ldr x1, =__bss_end /* this is auto-relocated! */
clear_loop:
str xzr, [x0], #8
cmp x0, x1
b.lo clear_loop
/* call board_init_r(gd_t *id, ulong dest_addr) */
mov x0, x18 /* gd_t */
ldr x1, [x18, #GD_RELOCADDR] /* dest_addr */
b board_init_r /* PC relative jump */
/* NOTREACHED - board_init_r() does not return */
ENDPROC(_main)
|
genetel200/u-boot
| 1,579
|
arch/arm/lib/vectors_m.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*/
#include <config.h>
#include <asm/assembler.h>
#include <linux/linkage.h>
.type __hard_fault_entry, %function
__hard_fault_entry:
mov r0, sp @ pass auto-saved registers as argument
b do_hard_fault
.type __mm_fault_entry, %function
__mm_fault_entry:
mov r0, sp @ pass auto-saved registers as argument
b do_mm_fault
.type __bus_fault_entry, %function
__bus_fault_entry:
mov r0, sp @ pass auto-saved registers as argument
b do_bus_fault
.type __usage_fault_entry, %function
__usage_fault_entry:
mov r0, sp @ pass auto-saved registers as argument
b do_usage_fault
.type __invalid_entry, %function
__invalid_entry:
mov r0, sp @ pass auto-saved registers as argument
b do_invalid_entry
.section .vectors
ENTRY(_start)
.long CONFIG_SYS_INIT_SP_ADDR @ 0 - Reset stack pointer
.long reset @ 1 - Reset
.long __invalid_entry @ 2 - NMI
.long __hard_fault_entry @ 3 - HardFault
.long __mm_fault_entry @ 4 - MemManage
.long __bus_fault_entry @ 5 - BusFault
.long __usage_fault_entry @ 6 - UsageFault
.long __invalid_entry @ 7 - Reserved
.long __invalid_entry @ 8 - Reserved
.long __invalid_entry @ 9 - Reserved
.long __invalid_entry @ 10 - Reserved
.long __invalid_entry @ 11 - SVCall
.long __invalid_entry @ 12 - Debug Monitor
.long __invalid_entry @ 13 - Reserved
.long __invalid_entry @ 14 - PendSV
.long __invalid_entry @ 15 - SysTick
.rept 255 - 16
.long __invalid_entry @ 16..255 - External Interrupts
.endr
|
genetel200/u-boot
| 6,715
|
arch/arm/lib/vectors.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* vectors - Generic ARM exception table code
*
* Copyright (c) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (c) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (c) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2002 Kyle Harris <kharris@nexus-tech.net>
*/
#include <config.h>
/*
* A macro to allow insertion of an ARM exception vector either
* for the non-boot0 case or by a boot0-header.
*/
.macro ARM_VECTORS
#ifdef CONFIG_ARCH_K3
ldr pc, _reset
#else
b reset
#endif
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
.endm
/*
*************************************************************************
*
* Symbol _start is referenced elsewhere, so make it global
*
*************************************************************************
*/
.globl _start
/*
*************************************************************************
*
* Vectors have their own section so linker script can map them easily
*
*************************************************************************
*/
.section ".vectors", "ax"
#if defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
/*
* Various SoCs need something special and SoC-specific up front in
* order to boot, allow them to set that in their boot0.h file and then
* use it here.
*
* To allow a boot0 hook to insert a 'special' sequence after the vector
* table (e.g. for the socfpga), the presence of a boot0 hook supresses
* the below vector table and assumes that the vector table is filled in
* by the boot0 hook. The requirements for a boot0 hook thus are:
* (1) defines '_start:' as appropriate
* (2) inserts the vector table using ARM_VECTORS as appropriate
*/
#ifdef CONFIG_ARCH_ROCKCHIP
#include <asm/arch-rockchip/boot0.h>
#else
#include <asm/arch/boot0.h>
#endif
#else
/*
*************************************************************************
*
* Exception vectors as described in ARM reference manuals
*
* Uses indirect branch to allow reaching handlers anywhere in memory.
*
*************************************************************************
*/
_start:
#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
.word CONFIG_SYS_DV_NOR_BOOT_CFG
#endif
ARM_VECTORS
#endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */
/*
*************************************************************************
*
* Indirect vectors table
*
* Symbols referenced here must be defined somewhere else
*
*************************************************************************
*/
.globl _reset
.globl _undefined_instruction
.globl _software_interrupt
.globl _prefetch_abort
.globl _data_abort
.globl _not_used
.globl _irq
.globl _fiq
#ifdef CONFIG_ARCH_K3
_reset: .word reset
#endif
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
/* SPL interrupt handling: just hang */
#ifdef CONFIG_SPL_BUILD
.align 5
undefined_instruction:
software_interrupt:
prefetch_abort:
data_abort:
not_used:
irq:
fiq:
1:
b 1b /* hang and never return */
#else /* !CONFIG_SPL_BUILD */
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
#ifdef IRAM_BASE_ADDR
.word IRAM_BASE_ADDR + 0x20
#else
.word 0x0badc0de
#endif
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
@ carve out a frame on current user stack
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, IRQ_STACK_START_IN
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp @ save current stack into r0 (param register)
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
str lr, [r13, #4] @ save spsr in position 1 of saved stack
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
msr spsr, r13 @ switch modes, make sure moves will execute
mov lr, pc @ capture return pc
movs pc, lr @ jump to next instruction & switch modes.
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
/*
* exception handlers
*/
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif /* CONFIG_SPL_BUILD */
|
genetel200/u-boot
| 2,196
|
arch/arm/lib/debug.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* linux/arch/arm/kernel/debug.S
*
* Copyright (C) 1994-1999 Russell King
*
* 32-bit debugging code
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
.text
/*
* Some debugging routines (useful if you've got MM problems and
* printk isn't working). For DEBUGGING ONLY!!! Do not leave
* references to these in a production kernel!
*/
#if !defined(CONFIG_DEBUG_SEMIHOSTING)
#include CONFIG_DEBUG_LL_INCLUDE
#endif
#ifdef CONFIG_MMU
.macro addruart_current, rx, tmp1, tmp2
addruart \tmp1, \tmp2, \rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1
moveq \rx, \tmp1
movne \rx, \tmp2
.endm
#else /* !CONFIG_MMU */
.macro addruart_current, rx, tmp1, tmp2
addruart \rx, \tmp1, \tmp2
.endm
#endif /* CONFIG_MMU */
/*
* Useful debugging routines
*/
ENTRY(printhex8)
mov r1, #8
b printhex
ENDPROC(printhex8)
ENTRY(printhex4)
mov r1, #4
b printhex
ENDPROC(printhex4)
ENTRY(printhex2)
mov r1, #2
printhex: adr r2, hexbuf
add r3, r2, r1
mov r1, #0
strb r1, [r3]
1: and r1, r0, #15
mov r0, r0, lsr #4
cmp r1, #10
addlt r1, r1, #'0'
addge r1, r1, #'a' - 10
strb r1, [r3, #-1]!
teq r3, r2
bne 1b
mov r0, r2
b printascii
ENDPROC(printhex2)
hexbuf: .space 16
.ltorg
#ifndef CONFIG_DEBUG_SEMIHOSTING
ENTRY(printascii)
addruart_current r3, r1, r2
b 2f
1: waituart r2, r3
senduart r1, r3
busyuart r2, r3
teq r1, #'\n'
moveq r1, #'\r'
beq 1b
2: teq r0, #0
ldrneb r1, [r0], #1
teqne r1, #0
bne 1b
mov pc, lr
ENDPROC(printascii)
ENTRY(printch)
addruart_current r3, r1, r2
mov r1, r0
mov r0, #0
b 1b
ENDPROC(printch)
#ifdef CONFIG_MMU
ENTRY(debug_ll_addr)
addruart r2, r3, ip
str r2, [r0]
str r3, [r1]
mov pc, lr
ENDPROC(debug_ll_addr)
#endif
#else
ENTRY(printascii)
mov r1, r0
mov r0, #0x04 @ SYS_WRITE0
ARM( svc #0x123456 )
THUMB( svc #0xab )
mov pc, lr
ENDPROC(printascii)
ENTRY(printch)
adr r1, hexbuf
strb r0, [r1]
mov r0, #0x03 @ SYS_WRITEC
ARM( svc #0x123456 )
THUMB( svc #0xab )
mov pc, lr
ENDPROC(printch)
ENTRY(debug_ll_addr)
mov r2, #0
str r2, [r0]
str r2, [r1]
mov pc, lr
ENDPROC(debug_ll_addr)
#endif
|
genetel200/u-boot
| 4,903
|
arch/arm/lib/crt0.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* crt0 - C-runtime startup Code for ARM U-Boot
*
* Copyright (c) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <config.h>
#include <asm-offsets.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* This file handles the target-independent stages of the U-Boot
* start-up where a C runtime environment is needed. Its entry point
* is _main and is branched into from the target's start.S file.
*
* _main execution sequence is:
*
* 1. Set up initial environment for calling board_init_f().
* This environment only provides a stack and a place to store
* the GD ('global data') structure, both located in some readily
* available RAM (SRAM, locked cache...). In this context, VARIABLE
* global data, initialized or not (BSS), are UNAVAILABLE; only
* CONSTANT initialized data are available. GD should be zeroed
* before board_init_f() is called.
*
* 2. Call board_init_f(). This function prepares the hardware for
* execution from system RAM (DRAM, DDR...) As system RAM may not
* be available yet, , board_init_f() must use the current GD to
* store any data which must be passed on to later stages. These
* data include the relocation destination, the future stack, and
* the future GD location.
*
* 3. Set up intermediate environment where the stack and GD are the
* ones allocated by board_init_f() in system RAM, but BSS and
* initialized non-const data are still not available.
*
* 4a.For U-Boot proper (not SPL), call relocate_code(). This function
* relocates U-Boot from its current location into the relocation
* destination computed by board_init_f().
*
* 4b.For SPL, board_init_f() just returns (to crt0). There is no
* code relocation in SPL.
*
* 5. Set up final environment for calling board_init_r(). This
* environment has BSS (initialized to 0), initialized non-const
* data (initialized to their intended value), and stack in system
* RAM (for SPL moving the stack and GD into RAM is optional - see
* CONFIG_SPL_STACK_R). GD has retained values set by board_init_f().
*
* 6. For U-Boot proper (not SPL), some CPUs have some work left to do
* at this point regarding memory, so call c_runtime_cpu_setup.
*
* 7. Branch to board_init_r().
*
* For more information see 'Board Initialisation Flow in README.
*/
/*
* entry point of crt0 sequence
*/
ENTRY(_main)
/*
* Set up initial C runtime environment and call board_init_f(0).
*/
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
#endif
bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
mov sp, r0
bl board_init_f_alloc_reserve
mov sp, r0
/* set up gd here, outside any C code */
mov r9, r0
bl board_init_f_init_reserve
mov r0, #0
bl board_init_f
#if ! defined(CONFIG_SPL_BUILD)
/*
* Set up intermediate environment (new sp and gd) and call
* relocate_code(addr_moni). Trick here is that we'll return
* 'here' but relocated.
*/
ldr r0, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */
bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
mov sp, r0
ldr r9, [r9, #GD_BD] /* r9 = gd->bd */
sub r9, r9, #GD_SIZE /* new GD is below bd */
adr lr, here
ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */
add lr, lr, r0
#if defined(CONFIG_CPU_V7M)
orr lr, #1 /* As required by Thumb-only */
#endif
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
b relocate_code
here:
/*
* now relocate vectors
*/
bl relocate_vectors
/* Set up final (full) environment */
bl c_runtime_cpu_setup /* we still call old routine here */
#endif
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FRAMEWORK)
# ifdef CONFIG_SPL_BUILD
/* Use a DRAM stack for the rest of SPL, if requested */
bl spl_relocate_stack_gd
cmp r0, #0
movne sp, r0
movne r9, r0
# endif
ldr r0, =__bss_start /* this is auto-relocated! */
#ifdef CONFIG_USE_ARCH_MEMSET
ldr r3, =__bss_end /* this is auto-relocated! */
mov r1, #0x00000000 /* prepare zero to clear BSS */
subs r2, r3, r0 /* r2 = memset len */
bl memset
#else
ldr r1, =__bss_end /* this is auto-relocated! */
mov r2, #0x00000000 /* prepare zero to clear BSS */
clbss_l:cmp r0, r1 /* while not at end of BSS */
strlo r2, [r0] /* clear 32-bit BSS word */
addlo r0, r0, #4 /* move to next */
blo clbss_l
#endif
#if ! defined(CONFIG_SPL_BUILD)
bl coloured_LED_init
bl red_led_on
#endif
/* call board_init_r(gd_t *id, ulong dest_addr) */
mov r0, r9 /* gd_t */
ldr r1, [r9, #GD_RELOCADDR] /* dest_addr */
/* call board_init_r */
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
ldr lr, =board_init_r /* this is auto-relocated! */
bx lr
#else
ldr pc, =board_init_r /* this is auto-relocated! */
#endif
/* we should not return here. */
#endif
ENDPROC(_main)
|
genetel200/u-boot
| 5,306
|
arch/arm/lib/memcpy.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/arch/arm/lib/memcpy.S
*
* Author: Nicolas Pitre
* Created: Sep 28, 2005
* Copyright: MontaVista Software, Inc.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#define LDR1W_SHIFT 0
#define STR1W_SHIFT 0
.macro ldr1w ptr reg abort
W(ldr) \reg, [\ptr], #4
.endm
.macro ldr4w ptr reg1 reg2 reg3 reg4 abort
ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
.endm
.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
.endm
.macro ldr1b ptr reg cond=al abort
ldrb\cond\() \reg, [\ptr], #1
.endm
.macro str1w ptr reg abort
W(str) \reg, [\ptr], #4
.endm
.macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
.endm
.macro str1b ptr reg cond=al abort
strb\cond\() \reg, [\ptr], #1
.endm
.macro enter reg1 reg2
stmdb sp!, {r0, \reg1, \reg2}
.endm
.macro exit reg1 reg2
ldmfd sp!, {r0, \reg1, \reg2}
.endm
.text
/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
.syntax unified
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
.thumb
.thumb_func
#endif
ENTRY(memcpy)
cmp r0, r1
bxeq lr
enter r4, lr
subs r2, r2, #4
blt 8f
ands ip, r0, #3
PLD( pld [r1, #0] )
bne 9f
ands ip, r1, #3
bne 10f
1: subs r2, r2, #(28)
stmfd sp!, {r5 - r8}
blt 5f
CALGN( ands ip, r0, #31 )
CALGN( rsb r3, ip, #32 )
CALGN( sbcsne r4, r3, r2 ) @ C is always set here
CALGN( bcs 2f )
CALGN( adr r4, 6f )
CALGN( subs r2, r2, r3 ) @ C gets set
CALGN( add pc, r4, ip )
PLD( pld [r1, #0] )
2: PLD( subs r2, r2, #96 )
PLD( pld [r1, #28] )
PLD( blt 4f )
PLD( pld [r1, #60] )
PLD( pld [r1, #92] )
3: PLD( pld [r1, #124] )
4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
subs r2, r2, #32
str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
bge 3b
PLD( cmn r2, #96 )
PLD( bge 4b )
5: ands ip, r2, #28
rsb ip, ip, #32
#if LDR1W_SHIFT > 0
lsl ip, ip, #LDR1W_SHIFT
#endif
addne pc, pc, ip @ C is always clear here
b 7f
6:
.rept (1 << LDR1W_SHIFT)
W(nop)
.endr
ldr1w r1, r3, abort=20f
ldr1w r1, r4, abort=20f
ldr1w r1, r5, abort=20f
ldr1w r1, r6, abort=20f
ldr1w r1, r7, abort=20f
ldr1w r1, r8, abort=20f
ldr1w r1, lr, abort=20f
#if LDR1W_SHIFT < STR1W_SHIFT
lsl ip, ip, #STR1W_SHIFT - LDR1W_SHIFT
#elif LDR1W_SHIFT > STR1W_SHIFT
lsr ip, ip, #LDR1W_SHIFT - STR1W_SHIFT
#endif
add pc, pc, ip
nop
.rept (1 << STR1W_SHIFT)
W(nop)
.endr
str1w r0, r3, abort=20f
str1w r0, r4, abort=20f
str1w r0, r5, abort=20f
str1w r0, r6, abort=20f
str1w r0, r7, abort=20f
str1w r0, r8, abort=20f
str1w r0, lr, abort=20f
CALGN( bcs 2b )
7: ldmfd sp!, {r5 - r8}
8: movs r2, r2, lsl #31
ldr1b r1, r3, ne, abort=21f
ldr1b r1, r4, cs, abort=21f
ldr1b r1, ip, cs, abort=21f
str1b r0, r3, ne, abort=21f
str1b r0, r4, cs, abort=21f
str1b r0, ip, cs, abort=21f
exit r4, lr
bx lr
9: rsb ip, ip, #4
cmp ip, #2
ldr1b r1, r3, gt, abort=21f
ldr1b r1, r4, ge, abort=21f
ldr1b r1, lr, abort=21f
str1b r0, r3, gt, abort=21f
str1b r0, r4, ge, abort=21f
subs r2, r2, ip
str1b r0, lr, abort=21f
blt 8b
ands ip, r1, #3
beq 1b
10: bic r1, r1, #3
cmp ip, #2
ldr1w r1, lr, abort=21f
beq 17f
bgt 18f
.macro forward_copy_shift pull push
subs r2, r2, #28
blt 14f
CALGN( ands ip, r0, #31 )
CALGN( rsb ip, ip, #32 )
CALGN( sbcsne r4, ip, r2 ) @ C is always set here
CALGN( subcc r2, r2, ip )
CALGN( bcc 15f )
11: stmfd sp!, {r5 - r9}
PLD( pld [r1, #0] )
PLD( subs r2, r2, #96 )
PLD( pld [r1, #28] )
PLD( blt 13f )
PLD( pld [r1, #60] )
PLD( pld [r1, #92] )
12: PLD( pld [r1, #124] )
13: ldr4w r1, r4, r5, r6, r7, abort=19f
mov r3, lr, lspull #\pull
subs r2, r2, #32
ldr4w r1, r8, r9, ip, lr, abort=19f
orr r3, r3, r4, lspush #\push
mov r4, r4, lspull #\pull
orr r4, r4, r5, lspush #\push
mov r5, r5, lspull #\pull
orr r5, r5, r6, lspush #\push
mov r6, r6, lspull #\pull
orr r6, r6, r7, lspush #\push
mov r7, r7, lspull #\pull
orr r7, r7, r8, lspush #\push
mov r8, r8, lspull #\pull
orr r8, r8, r9, lspush #\push
mov r9, r9, lspull #\pull
orr r9, r9, ip, lspush #\push
mov ip, ip, lspull #\pull
orr ip, ip, lr, lspush #\push
str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
bge 12b
PLD( cmn r2, #96 )
PLD( bge 13b )
ldmfd sp!, {r5 - r9}
14: ands ip, r2, #28
beq 16f
15: mov r3, lr, lspull #\pull
ldr1w r1, lr, abort=21f
subs ip, ip, #4
orr r3, r3, lr, lspush #\push
str1w r0, r3, abort=21f
bgt 15b
CALGN( cmp r2, #0 )
CALGN( bge 11b )
16: sub r1, r1, #(\push / 8)
b 8b
.endm
forward_copy_shift pull=8 push=24
17: forward_copy_shift pull=16 push=16
18: forward_copy_shift pull=24 push=8
/*
* Abort preamble and completion macros.
* If a fixup handler is required then those macros must surround it.
* It is assumed that the fixup code will handle the private part of
* the exit macro.
*/
.macro copy_abort_preamble
19: ldmfd sp!, {r5 - r9}
b 21f
20: ldmfd sp!, {r5 - r8}
21:
.endm
.macro copy_abort_end
ldmfd sp!, {r4, lr}
bx lr
.endm
ENDPROC(memcpy)
|
genetel200/u-boot
| 1,685
|
arch/arm/mach-rmobile/lowlevel_init_gen3.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S
* This file is lowlevel initialize routine.
*
* (C) Copyright 2015 Renesas Electronics Corporation
*
* This file is based on the arch/arm/cpu/armv8/start.S
*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
#ifndef CONFIG_ARMV8_MULTIENTRY
/*
* For single-entry systems the lowlevel init is very simple.
*/
ldr x0, =GICD_BASE
bl gic_init_secure
#else /* CONFIG_ARMV8_MULTIENTRY is set */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
bl gic_init_secure
1:
#if defined(CONFIG_GICV3)
ldr x0, =GICR_BASE
bl gic_init_secure_percpu
#elif defined(CONFIG_GICV2)
ldr x0, =GICD_BASE
ldr x1, =GICC_BASE
bl gic_init_secure_percpu
#endif
#endif
branch_if_master x0, x1, 2f
/*
* Slave should wait for master clearing spin table.
* This sync prevent salves observing incorrect
* value of spin table and jumping to wrong place.
*/
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
#ifdef CONFIG_GICV2
ldr x0, =GICC_BASE
#endif
bl gic_wait_for_interrupt
#endif
/*
* All slaves will enter EL2 and optionally EL1.
*/
adr x4, lowlevel_in_el2
ldr x5, =ES_TO_AARCH64
bl armv8_switch_to_el2
lowlevel_in_el2:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
adr x4, lowlevel_in_el1
ldr x5, =ES_TO_AARCH64
bl armv8_switch_to_el1
lowlevel_in_el1:
#endif
#endif /* CONFIG_ARMV8_MULTIENTRY */
bl s_init
2:
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
|
genetel200/u-boot
| 1,776
|
arch/arm/mach-rmobile/lowlevel_init_ca15.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
* This file is lager low level initialize.
*
* Copyright (C) 2013, 2014 Renesas Electronics Corporation
*/
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
#ifndef CONFIG_SPL_BUILD
mrc p15, 0, r4, c0, c0, 5 /* mpidr */
orr r4, r4, r4, lsr #6
and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
b do_lowlevel_init
.pool
/*
* CPU ID #1-#3 come here
*/
.align 4
do_cpu_waiting:
ldr r1, =0xe6180000 /* sysc */
1: ldr r0, [r1, #0x20] /* sbar */
tst r0, r0
beq 1b
bx r0
/*
* Only CPU ID #0 comes here
*/
.align 4
do_lowlevel_init:
ldr r2, =0xFF000044 /* PRR */
ldr r1, [r2]
and r1, r1, #0x7F00
lsrs r1, r1, #8
cmp r1, #0x4C /* 0x4C is ID of r8a7794 */
beq _enable_actlr_smp
/* surpress wfe if ca15 */
tst r4, #4
mrceq p15, 0, r0, c1, c0, 1 /* actlr */
orreq r0, r0, #(1<<7)
mcreq p15, 0, r0, c1, c0, 1
/* and set l2 latency */
mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
and r0, r0, #0xf00
lsr r0, r0, #8
tst r0, #1 /* only need for cluster 0 */
bne _exit_init_l2_a15
mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
and r1, r0, #7
cmp r1, #3 /* has already been set up */
bicne r0, r0, #0xe7
orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
#if defined(CONFIG_R8A7790)
orrne r0, r0, #0x20 /* L2CTLR[5] */
#endif
mcrne p15, 1, r0, c9, c0, 2
b _exit_init_l2_a15
_enable_actlr_smp: /* R8A7794 only (CA7) */
#ifndef CONFIG_DCACHE_OFF
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #0x40
mcr p15, 0, r0, c1, c0, 1
#endif
_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
str lr, [sp]
/* initialize system */
bl s_init
ldr lr, [sp]
#endif
mov pc, lr
nop
ENDPROC(lowlevel_init)
.ltorg
|
genetel200/u-boot
| 3,677
|
arch/arm/mach-exynos/sec_boot.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013 Samsung Electronics
* Akshay Saraswat <akshay.s@samsung.com>
*/
#include <config.h>
#include <asm/arch/cpu.h>
.globl relocate_wait_code
relocate_wait_code:
adr r0, code_base @ r0: source address (start)
adr r1, code_end @ r1: source address (end)
ldr r2, =0x02073000 @ r2: target address
1:
ldmia r0!, {r3-r6}
stmia r2!, {r3-r6}
cmp r0, r1
blt 1b
b code_end
.ltorg
/*
* Secondary core waits here until Primary wake it up.
* Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE.
* This is a workaround code which is supposed to act as a
* substitute/supplement to the iROM code.
*
* This workaround code is relocated to the address 0x02073000
* because that comes out to be the last 4KB of the iRAM
* (Base Address - 0x02020000, Limit Address - 0x020740000).
*
* U-Boot and kernel are aware of this code and flags by the simple
* fact that we are implementing a workaround in the last 4KB
* of the iRAM and we have already defined these flag and address
* values in both kernel and U-Boot for our use.
*/
code_base:
b 1f
/*
* These addresses are being used as flags in u-boot and kernel.
*
* Jump address for resume and flag to check for resume/reset:
* Resume address - 0x2073008
* Resume flag - 0x207300C
*
* Jump address for cluster switching:
* Switch address - 0x2073018
*
* Jump address for core hotplug:
* Hotplug address - 0x207301C
*
* Jump address for C2 state (Reserved for future not being used right now):
* C2 address - 0x2073024
*
* Managed per core status for the active cluster:
* CPU0 state - 0x2073028
* CPU1 state - 0x207302C
* CPU2 state - 0x2073030
* CPU3 state - 0x2073034
*
* Managed per core GIC status for the active cluster:
* CPU0 gic state - 0x2073038
* CPU1 gic state - 0x207303C
* CPU2 gic state - 0x2073040
* CPU3 gic state - 0x2073044
*
* Logic of the code:
* Step-1: Read current CPU status.
* Step-2: If it's a resume then continue, else jump to step 4.
* Step-3: Clear inform1 PMU register and jump to inform0 value.
* Step-4: If it's a switch, C2 or reset, get the hotplug address.
* Step-5: If address is not available, enter WFE.
* Step-6: If address is available, jump to that address.
*/
nop @ for backward compatibility
.word 0x0 @ REG0: RESUME_ADDR
.word 0x0 @ REG1: RESUME_FLAG
.word 0x0 @ REG2
.word 0x0 @ REG3
_switch_addr:
.word 0x0 @ REG4: SWITCH_ADDR
_hotplug_addr:
.word 0x0 @ REG5: CPU1_BOOT_REG
.word 0x0 @ REG6
_c2_addr:
.word 0x0 @ REG7: REG_C2_ADDR
_cpu_state:
.word 0x1 @ CPU0_STATE : RESET
.word 0x2 @ CPU1_STATE : SECONDARY RESET
.word 0x2 @ CPU2_STATE : SECONDARY RESET
.word 0x2 @ CPU3_STATE : SECONDARY RESET
_gic_state:
.word 0x0 @ CPU0 - GICD_IGROUPR0
.word 0x0 @ CPU1 - GICD_IGROUPR0
.word 0x0 @ CPU2 - GICD_IGROUPR0
.word 0x0 @ CPU3 - GICD_IGROUPR0
1:
adr r0, _cpu_state
mrc p15, 0, r7, c0, c0, 5 @ read MPIDR
and r7, r7, #0xf @ r7 = cpu id
/* Read the current cpu state */
ldr r10, [r0, r7, lsl #2]
svc_entry:
tst r10, #(1 << 4)
adrne r0, _switch_addr
bne wait_for_addr
/* Clear INFORM1 */
ldr r0, =(0x10040000 + 0x804)
ldr r1, [r0]
cmp r1, #0x0
movne r1, #0x0
strne r1, [r0]
/* Get INFORM0 */
ldrne r1, =(0x10040000 + 0x800)
ldrne pc, [r1]
tst r10, #(1 << 0)
ldrne pc, =0x23e00000
adr r0, _hotplug_addr
wait_for_addr:
ldr r1, [r0]
cmp r1, #0x0
bxne r1
wfe
b wait_for_addr
.ltorg
code_end:
mov pc, lr
|
genetel200/u-boot
| 7,325
|
arch/arm/mach-orion5x/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*/
#include <config.h>
#include "asm/arch/orion5x.h"
/*
* Configuration values for SDRAM access setup
*/
#define SDRAM_CONFIG 0x3148400
#define SDRAM_MODE 0x62
#define SDRAM_CONTROL 0x4041000
#define SDRAM_TIME_CTRL_LOW 0x11602220
#define SDRAM_TIME_CTRL_HI 0x40c
#define SDRAM_OPEN_PAGE_EN 0x0
/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
#define SDRAM_BANK0_SIZE 0x3ff0001
#define SDRAM_ADDR_CTRL 0x10
#define SDRAM_OP_NOP 0x05
#define SDRAM_OP_SETMODE 0x03
#define SDRAM_PAD_CTRL_WR_EN 0x80000000
#define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
#define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
#define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
/*
* For Guideline MEM-3 - Drive Strength value
*/
#define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
#define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
/*
* For Guideline MEM-4 - DQS Reference Delay Tuning
*/
#define MSAR_ARMDDRCLCK_MASK 0x000000f0
#define MSAR_ARMDDRCLCK_H_MASK 0x00000100
#define MSAR_ARMDDRCLCK_333_167 0x00000000
#define MSAR_ARMDDRCLCK_500_167 0x00000030
#define MSAR_ARMDDRCLCK_667_167 0x00000060
#define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
#define MSAR_ARMDDRCLCK_400_200 0x00000010
#define MSAR_ARMDDRCLCK_600_200 0x00000050
#define MSAR_ARMDDRCLCK_800_200 0x00000070
#define FTDLL_DDR1_166MHZ 0x0047F001
#define FTDLL_DDR1_200MHZ 0x0044D001
/*
* Low-level init happens right after start.S has switched to SVC32,
* flushed and disabled caches and disabled MMU. We're still running
* from the boot chip select, so the first thing SPL should do is to
* set up the RAM to copy U-Boot into.
*/
.globl lowlevel_init
lowlevel_init:
#ifdef CONFIG_SPL_BUILD
/* Use 'r2 as the base for internal register accesses */
ldr r2, =ORION5X_REGS_PHY_BASE
/* move internal registers from the default 0xD0000000
* to their intended location, defined by SoC */
ldr r3, =0xD0000000
add r3, r3, #0x20000
str r2, [r3, #0x80]
/* Use R3 as the base for DRAM registers */
add r3, r2, #0x01000
/*DDR SDRAM Initialization Control */
ldr r0, =0x00000001
str r0, [r3, #0x480]
/* Use R3 as the base for PCI registers */
add r3, r2, #0x31000
/* Disable arbiter */
ldr r0, =0x00000030
str r0, [r3, #0xd00]
/* Use R3 as the base for DRAM registers */
add r3, r2, #0x01000
/* set all dram windows to 0 */
mov r0, #0
str r0, [r3, #0x504]
str r0, [r3, #0x50C]
str r0, [r3, #0x514]
str r0, [r3, #0x51C]
/* 1) Configure SDRAM */
ldr r0, =SDRAM_CONFIG
str r0, [r3, #0x400]
/* 2) Set SDRAM Control reg */
ldr r0, =SDRAM_CONTROL
str r0, [r3, #0x404]
/* 3) Write SDRAM address control register */
ldr r0, =SDRAM_ADDR_CTRL
str r0, [r3, #0x410]
/* 4) Write SDRAM bank 0 size register */
ldr r0, =SDRAM_BANK0_SIZE
str r0, [r3, #0x504]
/* keep other banks disabled */
/* 5) Write SDRAM open pages control register */
ldr r0, =SDRAM_OPEN_PAGE_EN
str r0, [r3, #0x414]
/* 6) Write SDRAM timing Low register */
ldr r0, =SDRAM_TIME_CTRL_LOW
str r0, [r3, #0x408]
/* 7) Write SDRAM timing High register */
ldr r0, =SDRAM_TIME_CTRL_HI
str r0, [r3, #0x40C]
/* 8) Write SDRAM mode register */
/* The CPU must not attempt to change the SDRAM Mode register setting */
/* prior to DRAM controller completion of the DRAM initialization */
/* sequence. To guarantee this restriction, it is recommended that */
/* the CPU sets the SDRAM Operation register to NOP command, performs */
/* read polling until the register is back in Normal operation value, */
/* and then sets SDRAM Mode register to its new value. */
/* 8.1 write 'nop' to SDRAM operation */
ldr r0, =SDRAM_OP_NOP
str r0, [r3, #0x418]
/* 8.2 poll SDRAM operation until back in 'normal' mode. */
1:
ldr r0, [r3, #0x418]
cmp r0, #0
bne 1b
/* 8.3 Now its safe to write new value to SDRAM Mode register */
ldr r0, =SDRAM_MODE
str r0, [r3, #0x41C]
/* 8.4 Set new mode */
ldr r0, =SDRAM_OP_SETMODE
str r0, [r3, #0x418]
/* 8.5 poll SDRAM operation until back in 'normal' mode. */
2:
ldr r0, [r3, #0x418]
cmp r0, #0
bne 2b
/* DDR SDRAM Address/Control Pads Calibration */
ldr r0, [r3, #0x4C0]
/* Set Bit [31] to make the register writable */
orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
str r0, [r3, #0x4C0]
bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
/* Get the final N locked value of driving strength [22:17] */
mov r1, r0
mov r1, r1, LSL #9
mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
orr r0, r0, r1
str r0, [r3, #0x4C0]
/* DDR SDRAM Data Pads Calibration */
ldr r0, [r3, #0x4C4]
/* Set Bit [31] to make the register writable */
orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
str r0, [r3, #0x4C4]
bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
/* Get the final N locked value of driving strength [22:17] */
mov r1, r0
mov r1, r1, LSL #9
mov r1, r1, LSR #26
orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
orr r0, r0, r1
str r0, [r3, #0x4C4]
/* Implement Guideline (GL# MEM-3) Drive Strength Value */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
ldr r0, [r3, #0x4C0]
orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
str r0, [r3, #0x4C0]
/* Correct strength and disable writes again */
bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK
orr r0, r0, r1
str r0, [r3, #0x4C0]
/* Enable writes to DDR SDRAM Data Pads Calibration register */
ldr r0, [r3, #0x4C4]
orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
str r0, [r3, #0x4C4]
/* Correct strength and disable writes again */
bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK
bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
orr r0, r0, r1
str r0, [r3, #0x4C4]
/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
/* Get the "sample on reset" register for the DDR frequancy */
ldr r3, =0x10000
ldr r0, [r3, #0x010]
ldr r1, =MSAR_ARMDDRCLCK_MASK
and r1, r0, r1
ldr r0, =FTDLL_DDR1_166MHZ
cmp r1, #MSAR_ARMDDRCLCK_333_167
beq 3f
cmp r1, #MSAR_ARMDDRCLCK_500_167
beq 3f
cmp r1, #MSAR_ARMDDRCLCK_667_167
beq 3f
ldr r0, =FTDLL_DDR1_200MHZ
cmp r1, #MSAR_ARMDDRCLCK_400_200_1
beq 3f
cmp r1, #MSAR_ARMDDRCLCK_400_200
beq 3f
cmp r1, #MSAR_ARMDDRCLCK_600_200
beq 3f
cmp r1, #MSAR_ARMDDRCLCK_800_200
beq 3f
ldr r0, =0
3:
/* Use R3 as the base for DRAM registers */
add r3, r2, #0x01000
ldr r2, [r3, #0x484]
orr r2, r2, r0
str r2, [r3, #0x484]
/* enable for 2 GB DDR; detection should find out real amount */
sub r0, r0, r0
str r0, [r3, #0x500]
ldr r0, =0x7fff0001
str r0, [r3, #0x504]
#endif /* CONFIG_SPL_BUILD */
/* Return to U-Boot via saved link register */
mov pc, lr
|
genetel200/u-boot
| 13,262
|
arch/arm/mach-davinci/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Low-level board setup code for TI DaVinci SoC based boards.
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Partially based on TI sources, original copyrights follow:
*/
/*
* Board specific setup info
*
* (C) Copyright 2003
* Texas Instruments, <www.ti.com>
* Kshitij Gupta <Kshitij@ti.com>
*
* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
*
* Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
*
* Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
*
* Modified for DV-EVM board by Swaminathan S, Nov 2005
*/
#include <config.h>
#define MDSTAT_STATE 0x3f
.globl lowlevel_init
lowlevel_init:
#ifdef CONFIG_SOC_DM644X
/*-------------------------------------------------------*
* Mask all IRQs by setting all bits in the EINT default *
*-------------------------------------------------------*/
mov r1, $0
ldr r0, =EINT_ENABLE0
str r1, [r0]
ldr r0, =EINT_ENABLE1
str r1, [r0]
/*------------------------------------------------------*
* Put the GEM in reset *
*------------------------------------------------------*/
/* Put the GEM in reset */
ldr r8, PSC_GEM_FLAG_CLEAR
ldr r6, MDCTL_GEM
ldr r7, [r6]
and r7, r7, r8
str r7, [r6]
/* Enable the Power Domain Transition Command */
ldr r6, PTCMD
ldr r7, [r6]
orr r7, r7, $0x02
str r7, [r6]
/* Check for Transition Complete(PTSTAT) */
checkStatClkStopGem:
ldr r6, PTSTAT
ldr r7, [r6]
ands r7, r7, $0x02
bne checkStatClkStopGem
/* Check for GEM Reset Completion */
checkGemStatClkStop:
ldr r6, MDSTAT_GEM
ldr r7, [r6]
ands r7, r7, $0x100
bne checkGemStatClkStop
/* Do this for enabling a WDT initiated reset this is a workaround
for a chip bug. Not required under normal situations */
ldr r6, P1394
mov r10, $0
str r10, [r6]
/*------------------------------------------------------*
* Enable L1 & L2 Memories in Fast mode *
*------------------------------------------------------*/
ldr r6, DFT_ENABLE
mov r10, $0x01
str r10, [r6]
ldr r6, MMARG_BRF0
ldr r10, MMARG_BRF0_VAL
str r10, [r6]
ldr r6, DFT_ENABLE
mov r10, $0
str r10, [r6]
/*------------------------------------------------------*
* DDR2 PLL Initialization *
*------------------------------------------------------*/
/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
mov r10, $0
ldr r6, PLL2_CTL
ldr r7, PLL_CLKSRC_MASK
ldr r8, [r6]
and r8, r8, r7
mov r9, r10, lsl $8
orr r8, r8, r9
str r8, [r6]
/* Select the PLLEN source */
ldr r7, PLL_ENSRC_MASK
and r8, r8, r7
str r8, [r6]
/* Bypass the PLL */
ldr r7, PLL_BYPASS_MASK
and r8, r8, r7
str r8, [r6]
/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
mov r10, $0x20
WaitPPL2Loop:
subs r10, r10, $1
bne WaitPPL2Loop
/* Reset the PLL */
ldr r7, PLL_RESET_MASK
and r8, r8, r7
str r8, [r6]
/* Power up the PLL */
ldr r7, PLL_PWRUP_MASK
and r8, r8, r7
str r8, [r6]
/* Enable the PLL from Disable Mode */
ldr r7, PLL_DISABLE_ENABLE_MASK
and r8, r8, r7
str r8, [r6]
/* Program the PLL Multiplier */
ldr r6, PLL2_PLLM
mov r2, $0x17 /* 162 MHz */
str r2, [r6]
/* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV2
mov r3, $0x01
str r3, [r6]
/* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV1
mov r4, $0x0b /* 54 MHz */
str r4, [r6]
/* PLL2 DIV2 MMR */
ldr r8, PLL2_DIV_MASK
ldr r6, PLL2_DIV2
ldr r9, [r6]
and r8, r8, r9
mov r9, $0x01
mov r9, r9, lsl $15
orr r8, r8, r9
str r8, [r6]
/* Program the GOSET bit to take new divider values */
ldr r6, PLL2_PLLCMD
ldr r7, [r6]
orr r7, r7, $0x01
str r7, [r6]
/* Wait for Done */
ldr r6, PLL2_PLLSTAT
doneLoop_0:
ldr r7, [r6]
ands r7, r7, $0x01
bne doneLoop_0
/* PLL2 DIV1 MMR */
ldr r8, PLL2_DIV_MASK
ldr r6, PLL2_DIV1
ldr r9, [r6]
and r8, r8, r9
mov r9, $0x01
mov r9, r9, lsl $15
orr r8, r8, r9
str r8, [r6]
/* Program the GOSET bit to take new divider values */
ldr r6, PLL2_PLLCMD
ldr r7, [r6]
orr r7, r7, $0x01
str r7, [r6]
/* Wait for Done */
ldr r6, PLL2_PLLSTAT
doneLoop:
ldr r7, [r6]
ands r7, r7, $0x01
bne doneLoop
/* Wait for PLL to Reset Properly */
mov r10, $0x218
ResetPPL2Loop:
subs r10, r10, $1
bne ResetPPL2Loop
/* Bring PLL out of Reset */
ldr r6, PLL2_CTL
ldr r8, [r6]
orr r8, r8, $0x08
str r8, [r6]
/* Wait for PLL to Lock */
ldr r10, PLL_LOCK_COUNT
PLL2Lock:
subs r10, r10, $1
bne PLL2Lock
/* Enable the PLL */
ldr r6, PLL2_CTL
ldr r8, [r6]
orr r8, r8, $0x01
str r8, [r6]
/*------------------------------------------------------*
* Issue Soft Reset to DDR Module *
*------------------------------------------------------*/
/* Shut down the DDR2 LPSC Module */
ldr r8, PSC_FLAG_CLEAR
ldr r6, MDCTL_DDR2
ldr r7, [r6]
and r7, r7, r8
orr r7, r7, $0x03
str r7, [r6]
/* Enable the Power Domain Transition Command */
ldr r6, PTCMD
ldr r7, [r6]
orr r7, r7, $0x01
str r7, [r6]
/* Check for Transition Complete(PTSTAT) */
checkStatClkStop:
ldr r6, PTSTAT
ldr r7, [r6]
ands r7, r7, $0x01
bne checkStatClkStop
/* Check for DDR2 Controller Enable Completion */
checkDDRStatClkStop:
ldr r6, MDSTAT_DDR2
ldr r7, [r6]
and r7, r7, $MDSTAT_STATE
cmp r7, $0x03
bne checkDDRStatClkStop
/*------------------------------------------------------*
* Program DDR2 MMRs for 162MHz Setting *
*------------------------------------------------------*/
/* Program PHY Control Register */
ldr r6, DDRCTL
ldr r7, DDRCTL_VAL
str r7, [r6]
/* Program SDRAM Bank Config Register */
ldr r6, SDCFG
ldr r7, SDCFG_VAL
str r7, [r6]
/* Program SDRAM TIM-0 Config Register */
ldr r6, SDTIM0
ldr r7, SDTIM0_VAL_162MHz
str r7, [r6]
/* Program SDRAM TIM-1 Config Register */
ldr r6, SDTIM1
ldr r7, SDTIM1_VAL_162MHz
str r7, [r6]
/* Program the SDRAM Bank Config Control Register */
ldr r10, MASK_VAL
ldr r8, SDCFG
ldr r9, SDCFG_VAL
and r9, r9, r10
str r9, [r8]
/* Program SDRAM SDREF Config Register */
ldr r6, SDREF
ldr r7, SDREF_VAL
str r7, [r6]
/*------------------------------------------------------*
* Issue Soft Reset to DDR Module *
*------------------------------------------------------*/
/* Issue a Dummy DDR2 read/write */
ldr r8, DDR2_START_ADDR
ldr r7, DUMMY_VAL
str r7, [r8]
ldr r7, [r8]
/* Shut down the DDR2 LPSC Module */
ldr r8, PSC_FLAG_CLEAR
ldr r6, MDCTL_DDR2
ldr r7, [r6]
and r7, r7, r8
orr r7, r7, $0x01
str r7, [r6]
/* Enable the Power Domain Transition Command */
ldr r6, PTCMD
ldr r7, [r6]
orr r7, r7, $0x01
str r7, [r6]
/* Check for Transition Complete(PTSTAT) */
checkStatClkStop2:
ldr r6, PTSTAT
ldr r7, [r6]
ands r7, r7, $0x01
bne checkStatClkStop2
/* Check for DDR2 Controller Enable Completion */
checkDDRStatClkStop2:
ldr r6, MDSTAT_DDR2
ldr r7, [r6]
and r7, r7, $MDSTAT_STATE
cmp r7, $0x01
bne checkDDRStatClkStop2
/*------------------------------------------------------*
* Turn DDR2 Controller Clocks On *
*------------------------------------------------------*/
/* Enable the DDR2 LPSC Module */
ldr r6, MDCTL_DDR2
ldr r7, [r6]
orr r7, r7, $0x03
str r7, [r6]
/* Enable the Power Domain Transition Command */
ldr r6, PTCMD
ldr r7, [r6]
orr r7, r7, $0x01
str r7, [r6]
/* Check for Transition Complete(PTSTAT) */
checkStatClkEn2:
ldr r6, PTSTAT
ldr r7, [r6]
ands r7, r7, $0x01
bne checkStatClkEn2
/* Check for DDR2 Controller Enable Completion */
checkDDRStatClkEn2:
ldr r6, MDSTAT_DDR2
ldr r7, [r6]
and r7, r7, $MDSTAT_STATE
cmp r7, $0x03
bne checkDDRStatClkEn2
/* DDR Writes and Reads */
ldr r6, CFGTEST
mov r3, $0x01
str r3, [r6]
/*------------------------------------------------------*
* System PLL Initialization *
*------------------------------------------------------*/
/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
mov r2, $0
ldr r6, PLL1_CTL
ldr r7, PLL_CLKSRC_MASK
ldr r8, [r6]
and r8, r8, r7
mov r9, r2, lsl $8
orr r8, r8, r9
str r8, [r6]
/* Select the PLLEN source */
ldr r7, PLL_ENSRC_MASK
and r8, r8, r7
str r8, [r6]
/* Bypass the PLL */
ldr r7, PLL_BYPASS_MASK
and r8, r8, r7
str r8, [r6]
/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
mov r10, $0x20
WaitLoop:
subs r10, r10, $1
bne WaitLoop
/* Reset the PLL */
ldr r7, PLL_RESET_MASK
and r8, r8, r7
str r8, [r6]
/* Disable the PLL */
orr r8, r8, $0x10
str r8, [r6]
/* Power up the PLL */
ldr r7, PLL_PWRUP_MASK
and r8, r8, r7
str r8, [r6]
/* Enable the PLL from Disable Mode */
ldr r7, PLL_DISABLE_ENABLE_MASK
and r8, r8, r7
str r8, [r6]
/* Program the PLL Multiplier */
ldr r6, PLL1_PLLM
mov r3, $0x15 /* For 594MHz */
str r3, [r6]
/* Wait for PLL to Reset Properly */
mov r10, $0xff
ResetLoop:
subs r10, r10, $1
bne ResetLoop
/* Bring PLL out of Reset */
ldr r6, PLL1_CTL
orr r8, r8, $0x08
str r8, [r6]
/* Wait for PLL to Lock */
ldr r10, PLL_LOCK_COUNT
PLL1Lock:
subs r10, r10, $1
bne PLL1Lock
/* Enable the PLL */
orr r8, r8, $0x01
str r8, [r6]
nop
nop
nop
nop
/*------------------------------------------------------*
* AEMIF configuration for NOR Flash (double check) *
*------------------------------------------------------*/
ldr r0, _PINMUX0
ldr r1, _DEV_SETTING
str r1, [r0]
ldr r0, WAITCFG
ldr r1, WAITCFG_VAL
ldr r2, [r0]
orr r2, r2, r1
str r2, [r0]
ldr r0, ACFG3
ldr r1, ACFG3_VAL
ldr r2, [r0]
and r1, r2, r1
str r1, [r0]
ldr r0, ACFG4
ldr r1, ACFG4_VAL
ldr r2, [r0]
and r1, r2, r1
str r1, [r0]
ldr r0, ACFG5
ldr r1, ACFG5_VAL
ldr r2, [r0]
and r1, r2, r1
str r1, [r0]
/*--------------------------------------*
* VTP manual Calibration *
*--------------------------------------*/
ldr r0, VTPIOCR
ldr r1, VTP_MMR0
str r1, [r0]
ldr r0, VTPIOCR
ldr r1, VTP_MMR1
str r1, [r0]
/* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
ldr r10, VTP_LOCK_COUNT
VTPLock:
subs r10, r10, $1
bne VTPLock
ldr r6, DFT_ENABLE
mov r10, $0x01
str r10, [r6]
ldr r6, DDRVTPR
ldr r7, [r6]
mov r8, r7, LSL #32-10
mov r8, r8, LSR #32-10 /* grab low 10 bits */
ldr r7, VTP_RECAL
orr r8, r7, r8
ldr r7, VTP_EN
orr r8, r7, r8
str r8, [r0]
/* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
ldr r10, VTP_LOCK_COUNT
VTP1Lock:
subs r10, r10, $1
bne VTP1Lock
ldr r1, [r0]
ldr r2, VTP_MASK
and r2, r1, r2
str r2, [r0]
ldr r6, DFT_ENABLE
mov r10, $0
str r10, [r6]
/*
* Call board-specific lowlevel init.
* That MUST be present and THAT returns
* back to arch calling code with "mov pc, lr."
*/
b dv_board_init
.ltorg
_PINMUX0:
.word 0x01c40000 /* Device Configuration Registers */
_PINMUX1:
.word 0x01c40004 /* Device Configuration Registers */
_DEV_SETTING:
.word 0x00000c1f
WAITCFG:
.word 0x01e00004
WAITCFG_VAL:
.word 0
ACFG3:
.word 0x01e00014
ACFG3_VAL:
.word 0x3ffffffd
ACFG4:
.word 0x01e00018
ACFG4_VAL:
.word 0x3ffffffd
ACFG5:
.word 0x01e0001c
ACFG5_VAL:
.word 0x3ffffffd
MDCTL_DDR2:
.word 0x01c41a34
MDSTAT_DDR2:
.word 0x01c41834
PTCMD:
.word 0x01c41120
PTSTAT:
.word 0x01c41128
EINT_ENABLE0:
.word 0x01c48018
EINT_ENABLE1:
.word 0x01c4801c
PSC_FLAG_CLEAR:
.word 0xffffffe0
PSC_GEM_FLAG_CLEAR:
.word 0xfffffeff
/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
DDRCTL:
.word 0x200000e4
DDRCTL_VAL:
.word 0x50006405
SDREF:
.word 0x2000000c
SDREF_VAL:
.word 0x000005c3
SDCFG:
.word 0x20000008
SDCFG_VAL:
#ifdef DDR_4BANKS
.word 0x00178622
#elif defined DDR_8BANKS
.word 0x00178632
#else
#error "Unknown DDR configuration!!!"
#endif
SDTIM0:
.word 0x20000010
SDTIM0_VAL_162MHz:
.word 0x28923211
SDTIM1:
.word 0x20000014
SDTIM1_VAL_162MHz:
.word 0x0016c722
VTPIOCR:
.word 0x200000f0 /* VTP IO Control register */
DDRVTPR:
.word 0x01c42030 /* DDR VPTR MMR */
VTP_MMR0:
.word 0x201f
VTP_MMR1:
.word 0xa01f
DFT_ENABLE:
.word 0x01c4004c
VTP_LOCK_COUNT:
.word 0x5b0
VTP_MASK:
.word 0xffffdfff
VTP_RECAL:
.word 0x08000
VTP_EN:
.word 0x02000
CFGTEST:
.word 0x80010000
MASK_VAL:
.word 0x00000fff
/* GEM Power Up & LPSC Control Register */
MDCTL_GEM:
.word 0x01c41a9c
MDSTAT_GEM:
.word 0x01c4189c
/* For WDT reset chip bug */
P1394:
.word 0x01c41a20
PLL_CLKSRC_MASK:
.word 0xfffffeff /* Mask the Clock Mode bit */
PLL_ENSRC_MASK:
.word 0xffffffdf /* Select the PLLEN source */
PLL_BYPASS_MASK:
.word 0xfffffffe /* Put the PLL in BYPASS */
PLL_RESET_MASK:
.word 0xfffffff7 /* Put the PLL in Reset Mode */
PLL_PWRUP_MASK:
.word 0xfffffffd /* PLL Power up Mask Bit */
PLL_DISABLE_ENABLE_MASK:
.word 0xffffffef /* Enable the PLL from Disable */
PLL_LOCK_COUNT:
.word 0x2000
/* PLL1-SYSTEM PLL MMRs */
PLL1_CTL:
.word 0x01c40900
PLL1_PLLM:
.word 0x01c40910
/* PLL2-SYSTEM PLL MMRs */
PLL2_CTL:
.word 0x01c40d00
PLL2_PLLM:
.word 0x01c40d10
PLL2_DIV1:
.word 0x01c40d18
PLL2_DIV2:
.word 0x01c40d1c
PLL2_PLLCMD:
.word 0x01c40d38
PLL2_PLLSTAT:
.word 0x01c40d3c
PLL2_DIV_MASK:
.word 0xffff7fff
MMARG_BRF0:
.word 0x01c42010 /* BRF margin mode 0 (R/W)*/
MMARG_BRF0_VAL:
.word 0x00444400
DDR2_START_ADDR:
.word 0x80000000
DUMMY_VAL:
.word 0xa55aa55a
#else /* CONFIG_SOC_DM644X */
mov pc, lr
#endif
|
genetel200/u-boot
| 1,834
|
arch/arm/mach-omap2/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Board specific setup info
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
*/
#include <config.h>
#include <asm/arch/omap.h>
#include <asm/omap_common.h>
#include <asm/arch/spl.h>
#include <linux/linkage.h>
.arch_extension sec
#ifdef CONFIG_SPL
ENTRY(save_boot_params)
ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
str r0, [r1]
b save_boot_params_ret
ENDPROC(save_boot_params)
#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE)
ENTRY(switch_to_hypervisor)
/*
* Switch to hypervisor mode
*/
adr r0, save_sp
str sp, [r0]
adr r1, restore_from_hyp
ldr r0, =0x102
b omap_smc1
restore_from_hyp:
adr r0, save_sp
ldr sp, [r0]
MRC p15, 4, R0, c1, c0, 0
ldr r1, =0X1004 @Set cache enable bits for hypervisor mode
orr r0, r0, r1
MCR p15, 4, R0, c1, c0, 0
b switch_to_hypervisor_ret
save_sp:
.word 0x0
ENDPROC(switch_to_hypervisor)
#endif
#endif
ENTRY(omap_smc1)
push {r4-r12, lr} @ save registers - ROM code may pollute
@ our registers
mov r12, r0 @ Service
mov r0, r1 @ Argument
dsb
dmb
smc 0 @ SMC #0 to enter monitor mode
@ call ROM Code API for the service requested
pop {r4-r12, pc}
ENDPROC(omap_smc1)
ENTRY(omap_smc_sec)
push {r4-r12, lr} @ save registers - ROM code may pollute
@ our registers
mov r6, #0xFF @ Indicate new Task call
mov r12, #0x00 @ Secure Service ID in R12
dsb
dmb
smc 0 @ SMC #0 to enter monitor mode
b omap_smc_sec_end @ exit at end of the service execution
nop
@ In case of IRQ happening in Secure, then ARM will branch here.
@ At that moment, IRQ will be pending and ARM will jump to Non Secure
@ IRQ handler
mov r12, #0xFE
dsb
dmb
smc 0 @ SMC #0 to enter monitor mode
omap_smc_sec_end:
pop {r4-r12, pc}
ENDPROC(omap_smc_sec)
|
genetel200/u-boot
| 1,797
|
arch/arm/mach-sunxi/rmr_switch.S
|
@
@ ARMv8 RMR reset sequence on Allwinner SoCs.
@
@ All 64-bit capable Allwinner SoCs reset in AArch32 (and continue to
@ exectute the Boot ROM in this state), so we need to switch to AArch64
@ at some point.
@ Section G6.2.133 of the ARMv8 ARM describes the Reset Management Register
@ (RMR), which triggers a warm-reset of a core and can request to switch
@ into a different execution state (AArch32 or AArch64).
@ The address at which execution starts after the reset is held in the
@ RVBAR system register, which is architecturally read-only.
@ Allwinner provides a writable alias of this register in MMIO space, so
@ we can easily set the start address of AArch64 code.
@ This code below switches to AArch64 and starts execution at the specified
@ start address. It needs to be assembled by an ARM(32) assembler and
@ the machine code must be inserted as verbatim .word statements into the
@ beginning of the AArch64 U-Boot code.
@ To get the encoded bytes, use:
@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S
@ ${CROSS_COMPILE}objdump -d rmr_switch.o
@
@ The resulting words should be inserted into the U-Boot file at
@ arch/arm/include/asm/arch-sunxi/boot0.h.
@
@ This file is not build by the U-Boot build system, but provided only as a
@ reference and to be able to regenerate a (probably fixed) version of this
@ code found in encoded form in boot0.h.
#include <config.h>
.text
#ifndef CONFIG_MACH_SUN50I_H6
ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register
#else
ldr r1, =0x09010040 @ MMIO mapped RVBAR[0] register
#endif
ldr r0, =0x57aA7add @ start address, to be replaced
str r0, [r1]
dsb sy
isb sy
mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
orr r0, r0, #3 @ request reset in AArch64
mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
isb sy
1: wfi
b 1b
|
genetel200/u-boot
| 1,114
|
arch/arm/mach-tegra/tegra186/cache.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016, NVIDIA CORPORATION.
*/
#include <config.h>
#include <linux/linkage.h>
#define SMC_SIP_INVOKE_MCE 0x82FFFF00
#define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11)
#define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14)
#define MCE_SMC_ROC_CLEAN_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 15)
ENTRY(__asm_tegra_cache_smc)
mov x1, #0
mov x2, #0
mov x3, #0
mov x4, #0
mov x5, #0
mov x6, #0
smc #0
mov x0, #0
ret
ENDPROC(__asm_invalidate_l3_dcache)
ENTRY(__asm_invalidate_l3_dcache)
mov x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff)
movk x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16
b __asm_tegra_cache_smc
ENDPROC(__asm_invalidate_l3_dcache)
ENTRY(__asm_flush_l3_dcache)
mov x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff)
movk x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16
b __asm_tegra_cache_smc
ENDPROC(__asm_flush_l3_dcache)
ENTRY(__asm_invalidate_l3_icache)
mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
b __asm_tegra_cache_smc
ENDPROC(__asm_invalidate_l3_icache)
|
genetel200/u-boot
| 1,664
|
arch/arm/mach-mediatek/mt7629/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 MediaTek Inc.
*/
#include <linux/linkage.h>
#define WAIT_CODE_SRAM_BASE 0x0010ff00
#define SLAVE_JUMP_REG 0x10202034
#define SLAVE1_MAGIC_REG 0x10202038
#define SLAVE1_MAGIC_NUM 0x534c4131
#define GIC_CPU_BASE 0x10320000
ENTRY(lowlevel_init)
#ifndef CONFIG_SPL_BUILD
/* Return to U-Boot via saved link register */
mov pc, lr
#else
/*
* Arch timer :
* set CNTFRQ = 20Mhz, set CNTVOFF = 0
*/
movw r0, #0x2d00
movt r0, #0x131
mcr p15, 0, r0, c14, c0, 0
/* enable SMP bit */
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #0x40
mcr p15, 0, r0, c1, c0, 1
/* if MP core, handle secondary cores */
mrc p15, 0, r0, c0, c0, 5
ands r1, r0, #0x40000000
bne go @ Go if UP
/* read slave CPU number */
ands r0, r0, #0x0f
beq go @ Go if core0 on primary core tile
b secondary
go:
/* master CPU */
mov pc, lr
secondary:
/* enable GIC as cores will be waken up by IPI */
ldr r2, =GIC_CPU_BASE
mov r1, #0xf0
str r1, [r2, #4]
mov r1, #1
str r1, [r2, #0]
ldr r1, [r2]
orr r1, #1
str r1, [r2]
/* copy wait code into SRAM */
ldr r0, =slave_cpu_wait
ldm r0, {r1 - r8} @ slave_cpu_wait has eight insns
ldr r0, =WAIT_CODE_SRAM_BASE
stm r0, {r1 - r8}
/* pass args to slave_cpu_wait */
ldr r0, =SLAVE1_MAGIC_REG
ldr r1, =SLAVE1_MAGIC_NUM
/* jump to wait code in SRAM */
ldr pc, =WAIT_CODE_SRAM_BASE
#endif
ENDPROC(lowlevel_init)
/* This function will be copied into SRAM */
ENTRY(slave_cpu_wait)
wfi
ldr r2, [r0]
cmp r2, r1
bne slave_cpu_wait
movw r0, #:lower16:SLAVE_JUMP_REG
movt r0, #:upper16:SLAVE_JUMP_REG
ldr r1, [r0]
mov pc, r1
ENDPROC(slave_cpu_wait)
|
genetel200/u-boot
| 3,729
|
arch/arm/mach-uniphier/arm32/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012-2015 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#include <config.h>
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
ENTRY(lowlevel_init)
mov r8, lr @ persevere link reg across call
/*
* The UniPhier Boot ROM loads SPL code to the L2 cache.
* But CPUs can only do instruction fetch now because start.S has
* cleared C and M bits.
* First we need to turn on MMU and Dcache again to get back
* data access to L2.
*/
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_DEBUG_LL
bl debug_ll_init
#endif
bl setup_init_ram @ RAM area for stack and page table
/*
* Now we are using the page table embedded in the Boot ROM.
* What we need to do next is to create a page table and switch
* over to it.
*/
bl create_page_table
bl __v7_flush_dcache_all
/* Disable MMU and Dcache before switching Page Table */
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
bl enable_mmu
mov lr, r8 @ restore link
mov pc, lr @ back to my caller
ENDPROC(lowlevel_init)
ENTRY(enable_mmu)
mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
bic r0, r0, #0x37
orr r0, r0, #0x20 @ disable TTBR1
mcr p15, 0, r0, c2, c0, 2
orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA
mcr p15, 0, r0, c2, c0, 0 @ TTBR0
mov r0, #0
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
mov r0, #-1 @ manager for all domains (No permission check)
mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
dsb
isb
/*
* MMU on:
* TLBs was already invalidated in "../start.S"
* So, we don't need to invalidate it here.
*/
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
mcr p15, 0, r0, c1, c0, 0
mov pc, lr
ENDPROC(enable_mmu)
/*
* For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
* It is large enough for tmp RAM.
*/
#define BOOT_RAM_SIZE (SZ_32K)
#define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
#define BOOT_RAM_WAYS (0x00000100) @ way 8
#define SSCO_BASE 0x506c0000
#define SSCOPE 0x244
#define SSCOQM 0x248
#define SSCOQAD 0x24c
#define SSCOQSZ 0x250
#define SSCOQWN 0x258
#define SSCOPPQSEF 0x25c
#define SSCOLPQS 0x260
ENTRY(setup_init_ram)
ldr r1, = SSCO_BASE
/* Touch to zero for the boot way */
0: ldr r0, = 0x00408006 @ touch to zero with address range
str r0, [r1, #SSCOQM]
ldr r0, = BOOT_RAM_BASE
str r0, [r1, #SSCOQAD]
ldr r0, = BOOT_RAM_SIZE
str r0, [r1, #SSCOQSZ]
ldr r0, = BOOT_RAM_WAYS
str r0, [r1, #SSCOQWN]
ldr r0, [r1, #SSCOPPQSEF]
cmp r0, #0 @ check if the command is successfully set
bne 0b @ try again if an error occurs
1: ldr r0, [r1, #SSCOLPQS]
cmp r0, #0x4
bne 1b @ wait until the operation is completed
str r0, [r1, #SSCOLPQS] @ clear the complete notification flag
mov pc, lr
ENDPROC(setup_init_ram)
#define DEVICE 0x00002002 /* Non-shareable Device */
#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
ENTRY(create_page_table)
ldr r0, = DEVICE
ldr r1, = BOOT_RAM_BASE
mov r12, r1 @ r12 is preserved during D-cache flush
0: str r0, [r1], #4 @ specify all the sections as Device
adds r0, r0, #0x00100000
bcc 0b
ldr r0, = NORMAL
str r0, [r12] @ mark the first section as Normal
add r0, r0, #0x00100000
str r0, [r12, #4] @ mark the second section as Normal
mov pc, lr
ENDPROC(create_page_table)
|
genetel200/u-boot
| 3,449
|
arch/arm/mach-uniphier/arm32/debug_ll.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* On-chip UART initializaion for low-level debugging
*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#include <linux/serial_reg.h>
#include <linux/linkage.h>
#include "../bcu/bcu-regs.h"
#include "../sc-regs.h"
#include "../sg-regs.h"
#if !defined(CONFIG_DEBUG_SEMIHOSTING)
#include CONFIG_DEBUG_LL_INCLUDE
#endif
#define BAUDRATE 115200
#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
ENTRY(debug_ll_init)
ldr r0, =SG_REVISION
ldr r1, [r0]
and r1, r1, #SG_REVISION_TYPE_MASK
mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
#define UNIPHIER_LD4_UART_CLK 36864000
cmp r1, #0x26
bne ld4_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)
b init_uart
ld4_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
#define UNIPHIER_PRO4_UART_CLK 73728000
cmp r1, #0x28
bne pro4_end
sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
ldr r0, =SG_LOADPINCTRL
mov r1, #1
str r1, [r0]
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)
b init_uart
pro4_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
#define UNIPHIER_SLD8_UART_CLK 80000000
cmp r1, #0x29
bne sld8_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
ldr r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE)
b init_uart
sld8_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
#define UNIPHIER_PRO5_UART_CLK 73728000
cmp r1, #0x2A
bne pro5_end
sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
ldr r0, =SG_LOADPINCTRL
mov r1, #1
str r1, [r0]
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
ldr r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE)
b init_uart
pro5_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
#define UNIPHIER_PXS2_UART_CLK 88900000
cmp r1, #0x2E
bne pxs2_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0
sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1
sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
ldr r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE)
b init_uart
pxs2_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
#define UNIPHIER_LD6B_UART_CLK 88900000
cmp r1, #0x2F
bne ld6b_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0
sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
ldr r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE)
b init_uart
ld6b_end:
#endif
mov pc, lr
init_uart:
addruart r0, r1, r2
mov r1, #UART_LCR_WLEN8 << 8
str r1, [r0, #0x10]
str r3, [r0, #0x24]
mov pc, lr
ENDPROC(debug_ll_init)
|
genetel200/u-boot
| 3,595
|
arch/arm/include/asm/arch-mx35/lowlevel_macro.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
*/
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
#include <asm/macro.h>
/*
* AIPS setup - Only setup MPROTx registers.
* The PACR default values are good.
*
* Default argument values:
* - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
* user-mode.
* - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
* SDMA to access them.
*/
.macro init_aips mpr=0x77777777, opacr=0x00000000
ldr r0, =AIPS1_BASE_ADDR
ldr r1, =\mpr
str r1, [r0, #AIPS_MPR_0_7]
str r1, [r0, #AIPS_MPR_8_15]
ldr r2, =AIPS2_BASE_ADDR
str r1, [r2, #AIPS_MPR_0_7]
str r1, [r2, #AIPS_MPR_8_15]
/* Did not change the AIPS control registers access type. */
ldr r1, =\opacr
str r1, [r0, #AIPS_OPACR_0_7]
str r1, [r0, #AIPS_OPACR_8_15]
str r1, [r0, #AIPS_OPACR_16_23]
str r1, [r0, #AIPS_OPACR_24_31]
str r1, [r0, #AIPS_OPACR_32_39]
str r1, [r2, #AIPS_OPACR_0_7]
str r1, [r2, #AIPS_OPACR_8_15]
str r1, [r2, #AIPS_OPACR_16_23]
str r1, [r2, #AIPS_OPACR_24_31]
str r1, [r2, #AIPS_OPACR_32_39]
.endm
/*
* MAX (Multi-Layer AHB Crossbar Switch) setup
*
* Default argument values:
* - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
* - SGPCR: always park on last master
* - MGPCR: restore default values
*/
.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
ldr r0, =MAX_BASE_ADDR
ldr r1, =\mpr
str r1, [r0, #MAX_MPR0] /* for S0 */
str r1, [r0, #MAX_MPR1] /* for S1 */
str r1, [r0, #MAX_MPR2] /* for S2 */
str r1, [r0, #MAX_MPR3] /* for S3 */
str r1, [r0, #MAX_MPR4] /* for S4 */
ldr r1, =\sgpcr
str r1, [r0, #MAX_SGPCR0] /* for S0 */
str r1, [r0, #MAX_SGPCR1] /* for S1 */
str r1, [r0, #MAX_SGPCR2] /* for S2 */
str r1, [r0, #MAX_SGPCR3] /* for S3 */
str r1, [r0, #MAX_SGPCR4] /* for S4 */
ldr r1, =\mgpcr
str r1, [r0, #MAX_MGPCR0] /* for M0 */
str r1, [r0, #MAX_MGPCR1] /* for M1 */
str r1, [r0, #MAX_MGPCR2] /* for M2 */
str r1, [r0, #MAX_MGPCR3] /* for M3 */
str r1, [r0, #MAX_MGPCR4] /* for M4 */
str r1, [r0, #MAX_MGPCR5] /* for M5 */
.endm
/*
* M3IF setup
*
* Default argument values:
* - CTL:
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
* MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000
* MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000
* MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000
* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
* MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
* MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
* ------------
* 0x00000040
*/
.macro init_m3if ctl=0x00000040
/* M3IF Control Register (M3IFCTL) */
write32 M3IF_BASE_ADDR, \ctl
.endm
.macro core_init
mrc p15, 0, r1, c1, c0, 0
/* Set branch prediction enable */
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #7
mcr p15, 0, r0, c1, c0, 1
orr r1, r1, #1 << 11
/* Set unaligned access enable */
orr r1, r1, #1 << 22
/* Set low int latency enable */
orr r1, r1, #1 << 21
mcr p15, 0, r1, c1, c0, 0
mov r0, #0
mcr p15, 0, r0, c15, c2, 4
mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */
mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
/* Setup the Peripheral Port Memory Remap Register */
ldr r0, =0x40000015 /* Start from AIPS 2-GB region */
mcr p15, 0, r0, c15, c2, 4
.endm
|
genetel200/u-boot
| 4,327
|
arch/arm/include/asm/arch-mx6/mx6_plugin.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*/
#include <config.h>
#ifdef CONFIG_ROM_UNIFIED_SECTIONS
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
#define ROM_VERSION_OFFSET 0x80
#else
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0
#define ROM_VERSION_OFFSET 0x48
#endif
#define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4
#define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4
#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
#define ROM_VERSION_TO10 0x10
#define ROM_VERSION_TO12 0x12
#define ROM_VERSION_TO15 0x15
plugin_start:
push {r0-r4, lr}
imx6_ddr_setting
imx6_clock_gating
imx6_qos_setting
/*
* The following is to fill in those arguments for this ROM function
* pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
* This function is used to copy data from the storage media into DDR.
* start - Initial (possibly partial) image load address on entry.
* Final image load address on exit.
* bytes - Initial (possibly partial) image size on entry.
* Final image size on exit.
* boot_data - Initial @ref ivt Boot Data load address.
*/
adr r0, boot_data2
adr r1, image_len2
adr r2, boot_data2
#ifdef CONFIG_NOR_BOOT
#ifdef CONFIG_MX6SX
ldr r3, =ROM_VERSION_OFFSET
ldr r4, [r3]
cmp r4, #ROM_VERSION_TO10
bgt before_calling_rom___pu_irom_hwcnfg_setup
ldr r3, =0x00900b00
ldr r4, =0x50000000
str r4, [r3, #0x5c]
#else
ldr r3, =0x00900800
ldr r4, =0x08000000
str r4, [r3, #0xc0]
#endif
#endif
/*
* check the _pu_irom_api_table for the address
*/
before_calling_rom___pu_irom_hwcnfg_setup:
ldr r3, =ROM_VERSION_OFFSET
ldr r4, [r3]
#if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL)
ldr r3, =ROM_VERSION_TO12
cmp r4, r3
ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12
ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
#elif defined(CONFIG_MX6Q)
ldr r3, =ROM_VERSION_TO15
cmp r4, r3
ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15
ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
#else
ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
#endif
ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
blx r4
after_calling_rom___pu_irom_hwcnfg_setup:
/*
* ROM_API_HWCNFG_SETUP function enables MMU & Caches.
* Thus disable MMU & Caches.
*/
mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0*/
ands r0, r0, #0x1 /* check if MMU is enabled */
beq mmu_disable_notreq /* exit if MMU is already disabled */
/* Disable caches, MMU */
mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0 */
bic r0, r0, #(1 << 2) /* disable D Cache */
bic r0, r0, #0x1 /* clear bit 0 ; MMU off */
bic r0, r0, #(0x1 << 11) /* disable Z, branch prediction */
bic r0, r0, #(0x1 << 1) /* disable A, Strict alignment */
/* check enabled. */
mcr p15, 0, r0, c1, c0, 0 /* write CP15 register 1 */
mov r0, r0
mov r0, r0
mov r0, r0
mov r0, r0
mmu_disable_notreq:
NOP
/* To return to ROM from plugin, we need to fill in these argument.
* Here is what need to do:
* Need to construct the paramters for this function before return to ROM:
* plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
*/
pop {r0-r4, lr}
push {r5}
ldr r5, boot_data2
str r5, [r0]
ldr r5, image_len2
str r5, [r1]
ldr r5, second_ivt_offset
str r5, [r2]
mov r0, #1
pop {r5}
/* return back to ROM code */
bx lr
/* make the following data right in the end of the output*/
.ltorg
#if (defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT))
#define FLASH_OFFSET 0x1000
#else
#define FLASH_OFFSET 0x400
#endif
/*
* second_ivt_offset is the offset from the "second_ivt_header" to
* "image_copy_start", which involves FLASH_OFFSET, plus the first
* ivt_header, the plugin code size itself recorded by "ivt2_header"
*/
second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET)
/*
* The following is the second IVT header plus the second boot data
*/
ivt2_header: .long 0x0
app2_code_jump_v: .long 0x0
reserv3: .long 0x0
dcd2_ptr: .long 0x0
boot_data2_ptr: .long 0x0
self_ptr2: .long 0x0
app_code_csf2: .long 0x0
reserv4: .long 0x0
boot_data2: .long 0x0
image_len2: .long 0x0
plugin2: .long 0x0
|
genetel200/u-boot
| 2,770
|
arch/arm/include/asm/arch-mx7/mx7_plugin.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*/
#include <config.h>
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
#define ROM_VERSION_OFFSET 0x80
#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
plugin_start:
push {r0-r4, lr}
imx7_ddr_setting
imx7_clock_gating
imx7_qos_setting
/*
* Check if we are in USB serial download mode and immediately return to ROM
* Need to check USB CTRL clock firstly, then check the USBx_nASYNCLISTADDR
*/
ldr r0, =0x30384680
ldr r1, [r0]
cmp r1, #0
beq normal_boot
ldr r0, =0x30B10158
ldr r1, [r0]
cmp r1, #0
beq normal_boot
pop {r0-r4, lr}
bx lr
normal_boot:
/*
* The following is to fill in those arguments for this ROM function
* pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
* This function is used to copy data from the storage media into DDR.
* start - Initial (possibly partial) image load address on entry.
* Final image load address on exit.
* bytes - Initial (possibly partial) image size on entry.
* Final image size on exit.
* boot_data - Initial @ref ivt Boot Data load address.
*/
adr r0, boot_data2
adr r1, image_len2
adr r2, boot_data2
/*
* check the _pu_irom_api_table for the address
*/
before_calling_rom___pu_irom_hwcnfg_setup:
ldr r3, =ROM_VERSION_OFFSET
ldr r4, [r3]
ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
blx r4
after_calling_rom___pu_irom_hwcnfg_setup:
/* To return to ROM from plugin, we need to fill in these argument.
* Here is what need to do:
* Need to construct the paramters for this function before return to ROM:
* plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
*/
pop {r0-r4, lr}
push {r5}
ldr r5, boot_data2
str r5, [r0]
ldr r5, image_len2
str r5, [r1]
ldr r5, second_ivt_offset
str r5, [r2]
mov r0, #1
pop {r5}
/* return back to ROM code */
bx lr
/* make the following data right in the end of the output*/
.ltorg
#define FLASH_OFFSET 0x400
/*
* second_ivt_offset is the offset from the "second_ivt_header" to
* "image_copy_start", which involves FLASH_OFFSET, plus the first
* ivt_header, the plugin code size itself recorded by "ivt2_header"
*/
second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET)
/*
* The following is the second IVT header plus the second boot data
*/
ivt2_header: .long 0x0
app2_code_jump_v: .long 0x0
reserv3: .long 0x0
dcd2_ptr: .long 0x0
boot_data2_ptr: .long 0x0
self_ptr2: .long 0x0
app_code_csf2: .long 0x0
reserv4: .long 0x0
boot_data2: .long 0x0
image_len2: .long 0x0
plugin2: .long 0x0
|
genetel200/u-boot
| 12,571
|
arch/arm/mach-omap2/omap3/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Board specific setup info
*
* (C) Copyright 2008
* Texas Instruments, <www.ti.com>
*
* Initial Code by:
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*/
#include <config.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks_omap3.h>
#include <linux/linkage.h>
/*
* Funtion for making PPA HAL API calls in secure devices
* Input:
* R0 - Service ID
* R1 - paramer list
*/
/* TODO: Re-evaluate the comment at the end regarding armv5 vs armv7 */
ENTRY(do_omap3_emu_romcode_call)
PUSH {r4-r12, lr} @ Save all registers from ROM code!
MOV r12, r0 @ Copy the Secure Service ID in R12
MOV r3, r1 @ Copy the pointer to va_list in R3
MOV r1, #0 @ Process ID - 0
MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
@ to va_list in R3
MOV r6, #0xFF @ Indicate new Task call
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c10, 5 @ DMB
.word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
@ because we use -march=armv5
POP {r4-r12, pc}
ENDPROC(do_omap3_emu_romcode_call)
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
/**************************************************************************
* cpy_clk_code: relocates clock code into SRAM where its safer to execute
* R1 = SRAM destination address.
*************************************************************************/
ENTRY(cpy_clk_code)
/* Copy DPLL code into SRAM */
adr r0, go_to_speed /* copy from start of go_to_speed... */
adr r2, lowlevel_init /* ... up to start of low_level_init */
next2:
ldmia r0!, {r3 - r10} /* copy from source address [r0] */
stmia r1!, {r3 - r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo next2
mov pc, lr /* back to caller */
ENDPROC(cpy_clk_code)
/* ***************************************************************************
* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
* -executed from SRAM.
* R0 = CM_CLKEN_PLL-bypass value
* R1 = CM_CLKSEL1_PLL-m, n, and divider values
* R2 = CM_CLKSEL_CORE-divider values
* R3 = CM_IDLEST_CKGEN - addr dpll lock wait
*
* Note: If core unlocks/relocks and SDRAM is running fast already it gets
* confused. A reset of the controller gets it back. Taking away its
* L3 when its not in self refresh seems bad for it. Normally, this
* code runs from flash before SDR is init so that should be ok.
****************************************************************************/
ENTRY(go_to_speed)
stmfd sp!, {r4 - r6}
/* move into fast relock bypass */
ldr r4, pll_ctl_add
str r0, [r4]
wait1:
ldr r5, [r3] /* get status */
and r5, r5, #0x1 /* isolate core status */
cmp r5, #0x1 /* still locked? */
beq wait1 /* if lock, loop */
/* set new dpll dividers _after_ in bypass */
ldr r5, pll_div_add1
str r1, [r5] /* set m, n, m2 */
ldr r5, pll_div_add2
str r2, [r5] /* set l3/l4/.. dividers*/
ldr r5, pll_div_add3 /* wkup */
ldr r2, pll_div_val3 /* rsm val */
str r2, [r5]
ldr r5, pll_div_add4 /* gfx */
ldr r2, pll_div_val4
str r2, [r5]
ldr r5, pll_div_add5 /* emu */
ldr r2, pll_div_val5
str r2, [r5]
/* now prepare GPMC (flash) for new dpll speed */
/* flash needs to be stable when we jump back to it */
ldr r5, flash_cfg3_addr
ldr r2, flash_cfg3_val
str r2, [r5]
ldr r5, flash_cfg4_addr
ldr r2, flash_cfg4_val
str r2, [r5]
ldr r5, flash_cfg5_addr
ldr r2, flash_cfg5_val
str r2, [r5]
ldr r5, flash_cfg1_addr
ldr r2, [r5]
orr r2, r2, #0x3 /* up gpmc divider */
str r2, [r5]
/* lock DPLL3 and wait a bit */
orr r0, r0, #0x7 /* set up for lock mode */
str r0, [r4] /* lock */
nop /* ARM slow at this point working at sys_clk */
nop
nop
nop
wait2:
ldr r5, [r3] /* get status */
and r5, r5, #0x1 /* isolate core status */
cmp r5, #0x1 /* still locked? */
bne wait2 /* if lock, loop */
nop
nop
nop
nop
ldmfd sp!, {r4 - r6}
mov pc, lr /* back to caller, locked */
ENDPROC(go_to_speed)
_go_to_speed: .word go_to_speed
/* these constants need to be close for PIC code */
/* The Nor has to be in the Flash Base CS0 for this condition to happen */
flash_cfg1_addr:
.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
flash_cfg3_addr:
.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
flash_cfg3_val:
.word STNOR_GPMC_CONFIG3
flash_cfg4_addr:
.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
flash_cfg4_val:
.word STNOR_GPMC_CONFIG4
flash_cfg5_val:
.word STNOR_GPMC_CONFIG5
flash_cfg5_addr:
.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
pll_ctl_add:
.word CM_CLKEN_PLL
pll_div_add1:
.word CM_CLKSEL1_PLL
pll_div_add2:
.word CM_CLKSEL_CORE
pll_div_add3:
.word CM_CLKSEL_WKUP
pll_div_val3:
.word (WKUP_RSM << 1)
pll_div_add4:
.word CM_CLKSEL_GFX
pll_div_val4:
.word (GFX_DIV << 0)
pll_div_add5:
.word CM_CLKSEL1_EMU
pll_div_val5:
.word CLSEL1_EMU_VAL
#endif
ENTRY(lowlevel_init)
ldr sp, SRAM_STACK
str ip, [sp] /* stash ip register */
mov ip, lr /* save link reg across call */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
/*
* No need to copy/exec the clock code - DPLL adjust already done
* in NAND/oneNAND Boot.
*/
ldr r1, =SRAM_CLK_CODE
bl cpy_clk_code
#endif /* NAND Boot */
mov lr, ip /* restore link reg */
ldr ip, [sp] /* restore save ip */
/* tail-call s_init to setup pll, mux, memory */
b s_init
ENDPROC(lowlevel_init)
/* the literal pools origin */
.ltorg
REG_CONTROL_STATUS:
.word CONTROL_STATUS
SRAM_STACK:
.word LOW_LEVEL_SRAM_STACK
/* DPLL(1-4) PARAM TABLES */
/*
* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
* OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
* The values are defined for all possible sysclk and for ES1 and ES2.
*/
mpu_dpll_param:
/* 12MHz */
/* ES1 */
.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
/* ES2 */
.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
/* 3410 */
.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
/* 13MHz */
/* ES1 */
.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
/* ES2 */
.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
/* 3410 */
.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
/* 19.2MHz */
/* ES1 */
.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
/* ES2 */
.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
/* 3410 */
.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
/* 26MHz */
/* ES1 */
.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
/* ES2 */
.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
/* 3410 */
.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
/* 38.4MHz */
/* ES1 */
.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
/* ES2 */
.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
/* 3410 */
.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
.globl get_mpu_dpll_param
get_mpu_dpll_param:
adr r0, mpu_dpll_param
mov pc, lr
iva_dpll_param:
/* 12MHz */
/* ES1 */
.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
/* ES2 */
.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
/* 3410 */
.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
/* 13MHz */
/* ES1 */
.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
/* ES2 */
.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
/* 3410 */
.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
/* 19.2MHz */
/* ES1 */
.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
/* ES2 */
.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
/* 3410 */
.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
/* 26MHz */
/* ES1 */
.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
/* ES2 */
.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
/* 3410 */
.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
/* 38.4MHz */
/* ES1 */
.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
/* ES2 */
.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
/* 3410 */
.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
.globl get_iva_dpll_param
get_iva_dpll_param:
adr r0, iva_dpll_param
mov pc, lr
/* Core DPLL targets for L3 at 166 & L133 */
core_dpll_param:
/* 12MHz */
/* ES1 */
.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
/* ES2 */
.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
/* 3410 */
.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
/* 13MHz */
/* ES1 */
.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
/* ES2 */
.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
/* 3410 */
.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
/* 19.2MHz */
/* ES1 */
.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
/* ES2 */
.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
/* 3410 */
.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
/* 26MHz */
/* ES1 */
.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
/* ES2 */
.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
/* 3410 */
.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
/* 38.4MHz */
/* ES1 */
.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
/* ES2 */
.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
/* 3410 */
.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
.globl get_core_dpll_param
get_core_dpll_param:
adr r0, core_dpll_param
mov pc, lr
/* PER DPLL values are same for both ES1 and ES2 */
per_dpll_param:
/* 12MHz */
.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
/* 13MHz */
.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
/* 19.2MHz */
.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
/* 26MHz */
.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
/* 38.4MHz */
.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
.globl get_per_dpll_param
get_per_dpll_param:
adr r0, per_dpll_param
mov pc, lr
/* PER2 DPLL values */
per2_dpll_param:
/* 12MHz */
.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
/* 13MHz */
.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
/* 19.2MHz */
.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
/* 26MHz */
.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
/* 38.4MHz */
.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
.globl get_per2_dpll_param
get_per2_dpll_param:
adr r0, per2_dpll_param
mov pc, lr
/*
* Tables for 36XX/37XX devices
*
*/
mpu_36x_dpll_param:
/* 12MHz */
.word 50, 0, 0, 1
/* 13MHz */
.word 600, 12, 0, 1
/* 19.2MHz */
.word 125, 3, 0, 1
/* 26MHz */
.word 300, 12, 0, 1
/* 38.4MHz */
.word 125, 7, 0, 1
iva_36x_dpll_param:
/* 12MHz */
.word 130, 2, 0, 1
/* 13MHz */
.word 20, 0, 0, 1
/* 19.2MHz */
.word 325, 11, 0, 1
/* 26MHz */
.word 10, 0, 0, 1
/* 38.4MHz */
.word 325, 23, 0, 1
core_36x_dpll_param:
/* 12MHz */
.word 100, 2, 0, 1
/* 13MHz */
.word 400, 12, 0, 1
/* 19.2MHz */
.word 375, 17, 0, 1
/* 26MHz */
.word 200, 12, 0, 1
/* 38.4MHz */
.word 375, 35, 0, 1
per_36x_dpll_param:
/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
.word 12000, 360, 4, 9, 16, 5, 4, 3, 1
.word 13000, 864, 12, 9, 16, 9, 4, 3, 1
.word 19200, 360, 7, 9, 16, 5, 4, 3, 1
.word 26000, 432, 12, 9, 16, 9, 4, 3, 1
.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
per2_36x_dpll_param:
/* 12MHz */
.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
/* 13MHz */
.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
/* 19.2MHz */
.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
/* 26MHz */
.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
/* 38.4MHz */
.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
ENTRY(get_36x_mpu_dpll_param)
adr r0, mpu_36x_dpll_param
mov pc, lr
ENDPROC(get_36x_mpu_dpll_param)
ENTRY(get_36x_iva_dpll_param)
adr r0, iva_36x_dpll_param
mov pc, lr
ENDPROC(get_36x_iva_dpll_param)
ENTRY(get_36x_core_dpll_param)
adr r0, core_36x_dpll_param
mov pc, lr
ENDPROC(get_36x_core_dpll_param)
ENTRY(get_36x_per_dpll_param)
adr r0, per_36x_dpll_param
mov pc, lr
ENDPROC(get_36x_per_dpll_param)
ENTRY(get_36x_per2_dpll_param)
adr r0, per2_36x_dpll_param
mov pc, lr
ENDPROC(get_36x_per2_dpll_param)
|
genetel200/u-boot
| 2,909
|
arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Secure entry function for CPU Core #1
*
* (C) Copyright 2016
* Texas Instruments, <www.ti.com>
*
* Author :
* Harinarayan Bhatta <harinarayan@ti.com>
*/
#include <config.h>
#include <asm/arch/omap.h>
#include <asm/omap_common.h>
#include <linux/linkage.h>
.arch_extension sec
#if !defined(CONFIG_SYS_DCACHE_OFF)
.global flush_dcache_range
#endif
#define AUX_CORE_BOOT_0 0x48281800
#define AUX_CORE_BOOT_1 0x48281804
#ifdef CONFIG_DRA7XX
/* DRA7xx ROM code function "startup_BootSlave". This function is where CPU1
* waits on WFE, polling on AUX_CORE_BOOT_x registers.
* This address is same for J6 and J6 Eco.
*/
#define ROM_FXN_STARTUP_BOOTSLAVE 0x00038a64
#endif
/* Assembly core where CPU1 is woken up into
* No need to save-restore registers, does not use stack.
*/
LENTRY(cpu1_entry)
ldr r4, =omap_smc_sec_cpu1_args
ldm r4, {r0,r1,r2,r3} @ Retrieve args
mov r6, #0xFF @ Indicate new Task call
mov r12, #0x00 @ Secure Service ID in R12
dsb
dmb
smc 0 @ SMC #0 to enter monitor mode
b .Lend @ exit at end of the service execution
nop
@ In case of IRQ happening in Secure, then ARM will branch here.
@ At that moment, IRQ will be pending and ARM will jump to Non Secure
@ IRQ handler
mov r12, #0xFE
dsb
dmb
smc 0 @ SMC #0 to enter monitor mode
.Lend:
ldr r4, =omap_smc_sec_cpu1_args
str r0, [r4, #0x10] @ save return value
ldr r4, =AUX_CORE_BOOT_0
mov r5, #0x0
str r5, [r4]
ldr r4, =ROM_FXN_STARTUP_BOOTSLAVE
sev @ Tell CPU0 we are done
bx r4 @ Jump back to ROM
END(cpu1_entry)
/*
* u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
*
* Makes a secure ROM/PPA call on CPU Core #1 on supported platforms.
* Assumes that CPU #1 is waiting in ROM code and not yet woken up or used by
* u-boot.
*/
ENTRY(omap_smc_sec_cpu1)
push {r4, r5, lr}
ldr r4, =omap_smc_sec_cpu1_args
stm r4, {r0,r1,r2,r3} @ Save args to memory
#if !defined(CONFIG_SYS_DCACHE_OFF)
mov r0, r4
mov r1, #CONFIG_SYS_CACHELINE_SIZE
add r1, r0, r1 @ dcache is not enabled on CPU1, so
blx flush_dcache_range @ flush the cache on args buffer
#endif
ldr r4, =AUX_CORE_BOOT_1
ldr r5, =cpu1_entry
str r5, [r4] @ Setup CPU1 entry function
ldr r4, =AUX_CORE_BOOT_0
mov r5, #0x10
str r5, [r4] @ Tell ROM to exit while loop
sev @ Wake up CPU1
.Lwait:
wfe @ Wait for CPU1 to finish
nop
ldr r5, [r4] @ Check if CPU1 is done
cmp r5, #0
bne .Lwait
ldr r4, =omap_smc_sec_cpu1_args
ldr r0, [r4, #0x10] @ Retrieve return value
pop {r4, r5, pc}
ENDPROC(omap_smc_sec_cpu1)
/*
* Buffer to save function arguments and return value for omap_smc_sec_cpu1
*/
.section .data
omap_smc_sec_cpu1_args:
#if !defined(CONFIG_SYS_DCACHE_OFF)
.balign CONFIG_SYS_CACHELINE_SIZE
.rept CONFIG_SYS_CACHELINE_SIZE/4
.word 0
.endr
#else
.rept 5
.word 0
.endr
#endif
END(omap_smc_sec_cpu1_args)
|
genetel200/u-boot
| 3,620
|
arch/arm/mach-at91/arm920t/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the at91rm9200dk board by
* (C) Copyright 2004
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*/
#include <config.h>
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#include <asm/arch/hardware.h>
#include <asm/arch/at91_mc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
_MTEXT_BASE:
#undef START_FROM_MEM
#ifdef START_FROM_MEM
.word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
#else
.word CONFIG_SYS_TEXT_BASE
#endif
.globl lowlevel_init
lowlevel_init:
ldr r1, =AT91_ASM_PMC_MOR
/* Main oscillator Enable register */
#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
ldr r0, =0x0000FF01 /* Enable main oscillator */
#else
ldr r0, =0x0000FF00 /* Disable main oscillator */
#endif
str r0, [r1] /*AT91C_CKGR_MOR] */
/* Add loop to compensate Main Oscillator startup time */
ldr r0, =0x00000010
LoopOsc:
subs r0, r0, #1
bhi LoopOsc
/* memory control configuration */
/* this isn't very elegant, but what the heck */
ldr r0, =SMRDATA
ldr r1, _MTEXT_BASE
sub r0, r0, r1
ldr r2, =SMRDATAE
sub r2, r2, r1
pllloop:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne pllloop
/* delay - this is all done by guess */
ldr r0, =0x00010000
/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
lock:
subs r0, r0, #1
bhi lock
ldr r0, =SMRDATA1
ldr r1, _MTEXT_BASE
sub r0, r0, r1
ldr r2, =SMRDATA1E
sub r2, r2, r1
sdinit:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne sdinit
/* switch from FastBus to Asynchronous clock mode */
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #ARM920T_CONTROL
mcr p15, 0, r0, c1, c0, 0
/* everything is fine now */
mov pc, lr
.ltorg
SMRDATA:
.word AT91_ASM_MC_EBI_CFG
.word CONFIG_SYS_EBI_CFGR_VAL
.word AT91_ASM_MC_SMC_CSR0
.word CONFIG_SYS_SMC_CSR0_VAL
.word AT91_ASM_PMC_PLLAR
.word CONFIG_SYS_PLLAR_VAL
.word AT91_ASM_PMC_PLLBR
.word CONFIG_SYS_PLLBR_VAL
.word AT91_ASM_PMC_MCKR
.word CONFIG_SYS_MCKR_VAL
SMRDATAE:
/* here there's a delay */
SMRDATA1:
.word AT91_ASM_PIOC_ASR
.word CONFIG_SYS_PIOC_ASR_VAL
.word AT91_ASM_PIOC_BSR
.word CONFIG_SYS_PIOC_BSR_VAL
.word AT91_ASM_PIOC_PDR
.word CONFIG_SYS_PIOC_PDR_VAL
.word AT91_ASM_MC_EBI_CSA
.word CONFIG_SYS_EBI_CSA_VAL
.word AT91_ASM_MC_SDRAMC_CR
.word CONFIG_SYS_SDRC_CR_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
.word CONFIG_SYS_SDRAM1
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
SMRDATA1E:
/* SMRDATA1 is 176 bytes long */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
genetel200/u-boot
| 6,439
|
arch/arm/mach-at91/arm926ejs/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*/
#include <config.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_wdt.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_rstc.h>
#ifdef CONFIG_ATMEL_LEGACY
#include <asm/arch/at91sam9_matrix.h>
#endif
#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
#endif
.globl lowlevel_init
.type lowlevel_init,function
lowlevel_init:
POS1:
adr r5, POS1 /* r5 = POS1 run time */
ldr r0, =POS1 /* r0 = POS1 compile */
sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */
/* memory control configuration 1 */
ldr r0, =SMRDATA
ldr r2, =SMRDATA1
add r0, r0, r5
add r2, r2, r5
0:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne 0b
/* ----------------------------------------------------------------------------
* PMC Init Step 1.
* ----------------------------------------------------------------------------
* - Check if the PLL is already initialized
* ----------------------------------------------------------------------------
*/
ldr r1, =(AT91_ASM_PMC_MCKR)
ldr r0, [r1]
and r0, r0, #3
cmp r0, #0
bne PLL_setup_end
/* ---------------------------------------------------------------------------
* - Enable the Main Oscillator
* ---------------------------------------------------------------------------
*/
ldr r1, =(AT91_ASM_PMC_MOR)
ldr r2, =(AT91_ASM_PMC_SR)
/* Main oscillator Enable register PMC_MOR: */
ldr r0, =CONFIG_SYS_MOR_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Main Oscillator is enabled */
mov r4, #AT91_PMC_IXR_MOSCS
MOSCS_Loop:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_IXR_MOSCS
bne MOSCS_Loop
/* ----------------------------------------------------------------------------
* PMC Init Step 2.
* ----------------------------------------------------------------------------
* Setup PLLA
* ----------------------------------------------------------------------------
*/
ldr r1, =(AT91_ASM_PMC_PLLAR)
ldr r0, =CONFIG_SYS_PLLAR_VAL
str r0, [r1]
/* Reading the PMC Status register to detect when the PLLA is locked */
mov r4, #AT91_PMC_IXR_LOCKA
MOSCS_Loop1:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_IXR_LOCKA
bne MOSCS_Loop1
/* ----------------------------------------------------------------------------
* PMC Init Step 3.
* ----------------------------------------------------------------------------
* - Switch on the Main Oscillator
* ----------------------------------------------------------------------------
*/
ldr r1, =(AT91_ASM_PMC_MCKR)
/* -Master Clock Controller register PMC_MCKR */
ldr r0, =CONFIG_SYS_MCKR1_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
mov r4, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop
ldr r0, =CONFIG_SYS_MCKR2_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
mov r4, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop1:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop1
PLL_setup_end:
/* ----------------------------------------------------------------------------
* - memory control configuration 2
* ----------------------------------------------------------------------------
*/
ldr r0, =(AT91_ASM_SDRAMC_TR)
ldr r1, [r0]
cmp r1, #0
bne SDRAM_setup_end
ldr r0, =SMRDATA1
ldr r2, =SMRDATA2
add r0, r0, r5
add r2, r2, r5
2:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne 2b
SDRAM_setup_end:
/* everything is fine now */
mov pc, lr
.ltorg
SMRDATA:
.word AT91_ASM_WDT_MR
.word CONFIG_SYS_WDTC_WDMR_VAL
/* configure PIOx as EBI0 D[16-31] */
#if defined(CONFIG_AT91SAM9263)
.word AT91_ASM_PIOD_PDR
.word CONFIG_SYS_PIOD_PDR_VAL1
.word AT91_ASM_PIOD_PUDR
.word CONFIG_SYS_PIOD_PPUDR_VAL
.word AT91_ASM_PIOD_ASR
.word CONFIG_SYS_PIOD_PPUDR_VAL
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
|| defined(CONFIG_AT91SAM9G20)
.word AT91_ASM_PIOC_PDR
.word CONFIG_SYS_PIOC_PDR_VAL1
.word AT91_ASM_PIOC_PUDR
.word CONFIG_SYS_PIOC_PPUDR_VAL
#endif
.word AT91_ASM_MATRIX_CSA0
.word CONFIG_SYS_MATRIX_EBICSA_VAL
/* flash */
.word AT91_ASM_SMC_MODE0
.word CONFIG_SYS_SMC0_MODE0_VAL
.word AT91_ASM_SMC_CYCLE0
.word CONFIG_SYS_SMC0_CYCLE0_VAL
.word AT91_ASM_SMC_PULSE0
.word CONFIG_SYS_SMC0_PULSE0_VAL
.word AT91_ASM_SMC_SETUP0
.word CONFIG_SYS_SMC0_SETUP0_VAL
SMRDATA1:
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
.word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL1
.word AT91_ASM_SDRAMC_CR
.word CONFIG_SYS_SDRC_CR_VAL
.word AT91_ASM_SDRAMC_MDR
.word CONFIG_SYS_SDRC_MDR_VAL
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL1
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL2
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL3
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL4
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL5
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL6
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL7
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL8
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL9
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL4
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL10
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL5
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL11
.word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL2
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL12
/* User reset enable*/
.word AT91_ASM_RSTC_MR
.word CONFIG_SYS_RSTC_RMR_VAL
#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
/* MATRIX_MCFG - REMAP all masters */
.word AT91_ASM_MATRIX_MCFG
.word 0x1FF
#endif
SMRDATA2:
.word 0
|
genetel200/u-boot
| 1,199
|
arch/arm/mach-imx/mx7/psci-suspend.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/armv7.h>
#include <asm/psci.h>
.pushsection ._secure.text, "ax"
.arch_extension sec
.globl v7_invalidate_l1
v7_invalidate_l1:
mov r0, #0
mcr p15, 2, r0, c0, c0, 0
mrc p15, 1, r0, c0, c0, 0
movw r1, #0x7fff
and r2, r1, r0, lsr #13
movw r1, #0x3ff
and r3, r1, r0, lsr #3 @ NumWays - 1
add r2, r2, #1 @ NumSets
and r0, r0, #0x7
add r0, r0, #4 @ SetShift
clz r1, r3 @ WayShift
add r4, r3, #1 @ NumWays
1:
sub r2, r2, #1 @ NumSets--
mov r3, r4 @ Temp = NumWays
2:
subs r3, r3, #1 @ Temp--
mov r5, r3, lsl r1
mov r6, r2, lsl r0
orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
mcr p15, 0, r5, c7, c6, 2
bgt 2b
cmp r2, #0
bgt 1b
dsb st
isb
mov pc, lr
.globl psci_system_resume
psci_system_resume:
mov sp, r0
/* invalidate L1 I-cache first */
mov r6, #0x0
mcr p15, 0, r6, c7, c5, 0
mcr p15, 0, r6, c7, c5, 6
/* enable the Icache and branch prediction */
mov r6, #0x1800
mcr p15, 0, r6, c1, c0, 0
isb
bl v7_invalidate_l1
b imx_system_resume
.popsection
|
genetel200/u-boot
| 9,285
|
arch/arm/mach-imx/mx5/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*/
#include <config.h>
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
#include <linux/linkage.h>
.section ".text.init", "x"
.macro init_arm_erratum
/* ARM erratum ID #468414 */
mrc 15, 0, r1, c1, c0, 1
orr r1, r1, #(1 << 5) /* enable L1NEON bit */
mcr 15, 0, r1, c1, c0, 1
.endm
/*
* L2CC Cache setup/invalidation/disable
*/
.macro init_l2cc
/* explicitly disable L2 cache */
mrc 15, 0, r0, c1, c0, 1
bic r0, r0, #0x2
mcr 15, 0, r0, c1, c0, 1
/* reconfigure L2 cache aux control reg */
ldr r0, =0xC0 | /* tag RAM */ \
0x4 | /* data RAM */ \
1 << 24 | /* disable write allocate delay */ \
1 << 23 | /* disable write allocate combine */ \
1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51)
ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */
orrls r0, r0, #1 << 25
#endif
mcr 15, 1, r0, c9, c0, 2
/* enable L2 cache */
mrc 15, 0, r0, c1, c0, 1
orr r0, r0, #2
mcr 15, 0, r0, c1, c0, 1
.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
* The PACR default values are good.*/
.macro init_aips
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
ldr r0, =AIPS1_BASE_ADDR
ldr r1, =0x77777777
str r1, [r0, #0x0]
str r1, [r0, #0x4]
ldr r0, =AIPS2_BASE_ADDR
str r1, [r0, #0x0]
str r1, [r0, #0x4]
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
.endm /* init_aips */
/* M4IF setup */
.macro init_m4if
#ifdef CONFIG_MX51
/* VPU and IPU given higher priority (0x4)
* IPU accesses with ID=0x1 given highest priority (=0xA)
*/
ldr r0, =M4IF_BASE_ADDR
ldr r1, =0x00000203
str r1, [r0, #0x40]
str r4, [r0, #0x44]
ldr r1, =0x00120125
str r1, [r0, #0x9C]
ldr r1, =0x001901A3
str r1, [r0, #0x48]
#endif
.endm /* init_m4if */
.macro setup_pll pll, freq
ldr r0, =\pll
adr r2, W_DP_\freq
bl setup_pll_func
.endm
#define W_DP_OP 0
#define W_DP_MFD 4
#define W_DP_MFN 8
setup_pll_func:
ldr r1, =0x00001232
str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
ldr r1, [r2, #W_DP_OP]
str r1, [r0, #PLL_DP_OP]
str r1, [r0, #PLL_DP_HFS_OP]
ldr r1, [r2, #W_DP_MFD]
str r1, [r0, #PLL_DP_MFD]
str r1, [r0, #PLL_DP_HFS_MFD]
ldr r1, [r2, #W_DP_MFN]
str r1, [r0, #PLL_DP_MFN]
str r1, [r0, #PLL_DP_HFS_MFN]
ldr r1, =0x00001232
str r1, [r0, #PLL_DP_CTL]
1: ldr r1, [r0, #PLL_DP_CTL]
ands r1, r1, #0x1
beq 1b
/* r10 saved upper lr */
mov pc, lr
.macro setup_pll_errata pll, freq
ldr r2, =\pll
str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
ldr r1, =0x00001236
str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
ands r1, r1, #0x1
beq 1b
ldr r5, \freq
str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
str r5, [r2, #PLL_DP_HFS_MFN]
mov r1, #0x1
str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
2: ldr r1, [r2, #PLL_DP_CONFIG]
tst r1, #1
bne 2b
ldr r1, =100 /* Wait at least 4 us */
3: subs r1, r1, #1
bge 3b
mov r1, #0x2
str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
.endm
.macro init_clock
#if defined (CONFIG_MX51)
ldr r0, =CCM_BASE_ADDR
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
str r4, [r0, #CLKCTL_CCGR1]
str r4, [r0, #CLKCTL_CCGR2]
str r4, [r0, #CLKCTL_CCGR3]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
ldr r1, =0x00FFF030
str r1, [r0, #CLKCTL_CCGR5]
ldr r1, =0x00000300
str r1, [r0, #CLKCTL_CCGR6]
/* Disable IPU and HSC dividers */
mov r1, #0x60000
str r1, [r0, #CLKCTL_CCDR]
/* Make sure to switch the DDR away from PLL 1 */
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51_PLL_ERRATA)
setup_pll PLL1_BASE_ADDR, 864
setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
#else
setup_pll PLL1_BASE_ADDR, 800
#endif
setup_pll PLL3_BASE_ADDR, 665
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
setup_pll PLL2_BASE_ADDR, 665
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
setup_pll PLL3_BASE_ADDR, 216
/* Set the platform clock dividers */
ldr r0, =ARM_BASE_ADDR
ldr r1, =0x00000725
str r1, [r0, #0x14]
ldr r0, =CCM_BASE_ADDR
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
str r4, [r0, #CLKCTL_CCSR]
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
str r1, [r0, #CLKCTL_CCGR1]
str r1, [r0, #CLKCTL_CCGR2]
str r1, [r0, #CLKCTL_CCGR3]
str r1, [r0, #CLKCTL_CCGR4]
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, =0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
str r4, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
#else /* CONFIG_MX53 */
ldr r0, =CCM_BASE_ADDR
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
str r4, [r0, #CLKCTL_CCGR1]
str r4, [r0, #CLKCTL_CCGR2]
str r4, [r0, #CLKCTL_CCGR3]
str r4, [r0, #CLKCTL_CCGR7]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
ldr r1, =0x00FFF030
str r1, [r0, #CLKCTL_CCGR5]
ldr r1, =0x0F00030F
str r1, [r0, #CLKCTL_CCGR6]
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
setup_pll PLL1_BASE_ADDR, 800
setup_pll PLL3_BASE_ADDR, 400
/* Switch peripheral to PLL3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00015154
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x02898945
str r1, [r0, #CLKCTL_CBCDR]
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
setup_pll PLL2_BASE_ADDR, 400
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00888945
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154
str r1, [r0, #CLKCTL_CBCMR]
/*change uart clk parent to pll2*/
ldr r1, [r0, #CLKCTL_CSCMR1]
and r1, r1, #0xfcffffff
orr r1, r1, #0x01000000
str r1, [r0, #CLKCTL_CSCMR1]
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
setup_pll PLL3_BASE_ADDR, 216
setup_pll PLL4_BASE_ADDR, 455
/* Set the platform clock dividers */
ldr r0, =ARM_BASE_ADDR
ldr r1, =0x00000124
str r1, [r0, #0x14]
ldr r0, =CCM_BASE_ADDR
mov r1, #0
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1. */
mov r1, #0x0
str r1, [r0, #CLKCTL_CCSR]
/* make uart div=6 */
ldr r1, [r0, #CLKCTL_CSCDR1]
and r1, r1, #0xffffffc0
orr r1, r1, #0x0a
str r1, [r0, #CLKCTL_CSCDR1]
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
str r1, [r0, #CLKCTL_CCGR1]
str r1, [r0, #CLKCTL_CCGR2]
str r1, [r0, #CLKCTL_CCGR3]
str r1, [r0, #CLKCTL_CCGR4]
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
str r1, [r0, #CLKCTL_CCGR7]
mov r1, #0x00000
str r1, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
#endif /* CONFIG_MX53 */
.endm
ENTRY(lowlevel_init)
mov r10, lr
mov r4, #0 /* Fix R4 to 0 */
#if defined(CONFIG_SYS_MAIN_PWR_ON)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
orr r1, r1, #1 << 23
str r1, [r0, #0x0]
ldr r1, [r0, #0x4]
orr r1, r1, #1 << 23
str r1, [r0, #0x4]
#endif
init_arm_erratum
init_l2cc
init_aips
init_m4if
init_clock
mov pc, r10
ENDPROC(lowlevel_init)
/* Board level setting value */
#if defined(CONFIG_MX51_PLL_ERRATA)
W_DP_864: .word DP_OP_864
.word DP_MFD_864
.word DP_MFN_864
W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
#else
W_DP_800: .word DP_OP_800
.word DP_MFD_800
.word DP_MFN_800
#endif
#if defined(CONFIG_MX51)
W_DP_665: .word DP_OP_665
.word DP_MFD_665
.word DP_MFN_665
#endif
W_DP_216: .word DP_OP_216
.word DP_MFD_216
.word DP_MFN_216
W_DP_400: .word DP_OP_400
.word DP_MFD_400
.word DP_MFN_400
W_DP_455: .word DP_OP_455
.word DP_MFD_455
.word DP_MFN_455
|
genetel200/u-boot
| 1,255
|
arch/arm/mach-imx/imx8m/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
*/
#include <config.h>
.align 8
.global rom_pointer
rom_pointer:
.space 256
/*
* Routine: save_boot_params (called after reset from start.S)
*/
.global save_boot_params
save_boot_params:
/* The firmware provided ATAG/FDT address can be found in r2/x0 */
adr x0, rom_pointer
stp x1, x2, [x0], #16
stp x3, x4, [x0], #16
stp x5, x6, [x0], #16
stp x7, x8, [x0], #16
stp x9, x10, [x0], #16
stp x11, x12, [x0], #16
stp x13, x14, [x0], #16
stp x15, x16, [x0], #16
stp x17, x18, [x0], #16
stp x19, x20, [x0], #16
stp x21, x22, [x0], #16
stp x23, x24, [x0], #16
stp x25, x26, [x0], #16
stp x27, x28, [x0], #16
stp x29, x30, [x0], #16
mov x30, sp
str x30, [x0], #8
/* Returns */
b save_boot_params_ret
.global restore_boot_params
restore_boot_params:
adr x0, rom_pointer
ldp x1, x2, [x0], #16
ldp x3, x4, [x0], #16
ldp x5, x6, [x0], #16
ldp x7, x8, [x0], #16
ldp x9, x10, [x0], #16
ldp x11, x12, [x0], #16
ldp x13, x14, [x0], #16
ldp x15, x16, [x0], #16
ldp x17, x18, [x0], #16
ldp x19, x20, [x0], #16
ldp x21, x22, [x0], #16
ldp x23, x24, [x0], #16
ldp x25, x26, [x0], #16
ldp x27, x28, [x0], #16
ldp x29, x30, [x0], #16
ldr x0, [x0]
mov sp, x0
ret
|
genetel200/u-boot
| 4,898
|
arch/arm/cpu/pxa/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for XScale CPU-core
*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
* Copyright (C) 2001 Marius Groger <mag@sysgo.de>
* Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
* Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
* Copyright (C) 2003 Kshitij <kshitij@ti.com>
* Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*/
#include <asm-offsets.h>
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
#ifdef CONFIG_CPU_PXA25X
bl lock_cache_for_stack
#endif
#ifdef CONFIG_CPU_PXA27X
/*
* enable clock for SRAM
*/
ldr r0,=CKEN
ldr r1,[r0]
orr r1,r1,#(1 << 20)
str r1,[r0]
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
#ifdef CONFIG_CPU_PXA25X
/*
* Unlock (actually, disable) the cache now that board_init_f
* is done. We could do this earlier but we would need to add
* a new C runtime hook, whereas c_runtime_cpu_setup already
* exists.
* As this routine is just a call to cpu_init_crit, let us
* tail-optimize and do a simple branch here.
*/
b cpu_init_crit
#else
bx lr
#endif
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 1 (A) Align
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
/*
* Enable MMU to use DCache as DRAM.
*
* This is useful on PXA25x and PXA26x in early bootstages, where there is no
* other possible memory available to hold stack.
*/
#ifdef CONFIG_CPU_PXA25X
.macro CPWAIT reg
mrc p15, 0, \reg, c2, c0, 0
mov \reg, \reg
sub pc, pc, #4
.endm
lock_cache_for_stack:
/* Domain access -- enable for all CPs */
ldr r0, =0x0000ffff
mcr p15, 0, r0, c3, c0, 0
/* Point TTBR to MMU table */
ldr r0, =mmutable
mcr p15, 0, r0, c2, c0, 0
/* Kick in MMU, ICache, DCache, BTB */
mrc p15, 0, r0, c1, c0, 0
bic r0, #0x1b00
bic r0, #0x0087
orr r0, #0x1800
orr r0, #0x0005
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
/* Unlock Icache, Dcache */
mcr p15, 0, r0, c9, c1, 1
mcr p15, 0, r0, c9, c2, 1
/* Flush Icache, Dcache, BTB */
mcr p15, 0, r0, c7, c7, 0
/* Unlock I-TLB, D-TLB */
mcr p15, 0, r0, c10, c4, 1
mcr p15, 0, r0, c10, c8, 1
/* Flush TLB */
mcr p15, 0, r0, c8, c7, 0
/* Allocate 4096 bytes of Dcache as RAM */
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r4, #0x00
mov r5, #0x00
mov r2, #0x01
mcr p15, 0, r0, c9, c2, 0
CPWAIT r0
/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
mov r0, #128
ldr r1, =0xfffff000
alloc:
mcr p15, 0, r1, c7, c2, 5
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
subs r0, #0x01
bne alloc
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r2, #0x00
mcr p15, 0, r2, c9, c2, 0
CPWAIT r0
mov pc, lr
.section .mmutable, "a"
mmutable:
.align 14
/* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
.set __base, 0
.rept 0xfff
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
/* 0xfff00000 : 1:1, cached mapping */
.word (0xfff << 20) | 0x1c1e
#endif /* CONFIG_CPU_PXA25X */
|
genetel200/u-boot
| 2,783
|
arch/arm/cpu/arm1176/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM1176 CPU-core
*
* Copyright (c) 2007 Samsung Electronics
*
* Copyright (C) 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
* 2007-09-21 - Added MoviNAND and OneNAND boot codes by
* jsgood (jsgood.yang@samsung.com)
* Base codes by scsuh (sc.suh)
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#endif
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl reset
reset:
/* Allow the board to save important registers */
b save_boot_params
.globl save_boot_params_ret
save_boot_params_ret:
/*
* set the cpu to SVC32 mode
*/
mrs r0, cpsr
bic r0, r0, #0x3f
orr r0, r0, #0xd3
msr cpsr, r0
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
cpu_init_crit:
/*
* When booting from NAND - it has definitely been a reset, so, no need
* to flush caches and disable the MMU
*/
#ifndef CONFIG_SPL_BUILD
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 1 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
/* Prepare to disable the MMU */
adr r2, mmu_disable_phys
sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
b mmu_disable
.align 5
/* Run in a single cache-line */
mmu_disable:
mcr p15, 0, r0, c1, c0, 0
nop
nop
mov pc, r2
mmu_disable_phys:
#endif
/*
* Go setup Memory and board specific bits prior to relocation.
*/
bl lowlevel_init /* go setup pll,mux,memory */
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
WEAK(save_boot_params)
b save_boot_params_ret /* back to my caller */
ENDPROC(save_boot_params)
|
genetel200/u-boot
| 2,428
|
arch/arm/cpu/arm946es/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Texas Instruments
*
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
*/
#include <asm-offsets.h>
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Go setup Memory and board specific bits prior to relocation.
*/
mov ip, lr /* perserve link reg across call */
bl lowlevel_init /* go setup memory */
mov lr, ip /* restore link */
#endif
mov pc, lr /* back to my caller */
#endif
|
genetel200/u-boot
| 2,388
|
arch/arm/cpu/arm920t/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM920 CPU-core
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
*/
#include <asm-offsets.h>
#include <common.h>
#include <config.h>
/*
*************************************************************************
*
* Startup Code (called from the ARM reset exception vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0, cpsr
bic r0, r0, #0x1f
orr r0, r0, #0xd3
msr cpsr, r0
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
/*
* relocate exception table
*/
ldr r0, =_start
ldr r1, =0x0
mov r2, #16
copyex:
subs r2, r2, #1
ldr r3, [r0], #4
str r3, [r1], #4
bne copyex
#endif
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 1 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
* find a lowlevel_init.S in your board directory.
*/
mov ip, lr
bl lowlevel_init
mov lr, ip
#endif
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
genetel200/u-boot
| 8,393
|
arch/arm/cpu/armv8/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
#include <asm/armv8/mmu.h>
/*************************************************************************
*
* Startup Code (reset vector)
*
*************************************************************************/
.globl _start
_start:
#if defined(LINUX_KERNEL_IMAGE_HEADER)
#include <asm/boot0-linux-kernel-header.h>
#elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
/*
* Various SoCs need something special and SoC-specific up front in
* order to boot, allow them to set that in their boot0.h file and then
* use it here.
*/
#ifdef CONFIG_ARCH_ROCKCHIP
#include <asm/arch-rockchip/boot0.h>
#else
#include <asm/arch/boot0.h>
#endif
#else
b reset
#endif
.align 3
.globl _TEXT_BASE
_TEXT_BASE:
.quad CONFIG_SYS_TEXT_BASE
/*
* These are defined in the linker script.
*/
.globl _end_ofs
_end_ofs:
.quad _end - _start
.globl _bss_start_ofs
_bss_start_ofs:
.quad __bss_start - _start
.globl _bss_end_ofs
_bss_end_ofs:
.quad __bss_end - _start
reset:
/* Allow the board to save important registers */
b save_boot_params
.globl save_boot_params_ret
save_boot_params_ret:
#if CONFIG_POSITION_INDEPENDENT
/*
* Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
* executed at a different address than it was linked at.
*/
pie_fixup:
adr x0, _start /* x0 <- Runtime value of _start */
ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
sub x9, x0, x1 /* x9 <- Run-vs-link offset */
adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
pie_fix_loop:
ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
ldr x4, [x2], #8 /* x4 <- addend */
cmp w1, #1027 /* relative fixup? */
bne pie_skip_reloc
/* relative fix: store addend plus offset at dest location */
add x0, x0, x9
add x4, x4, x9
str x4, [x0]
pie_skip_reloc:
cmp x2, x3
b.lo pie_fix_loop
pie_fixup_done:
#endif
#ifdef CONFIG_SYS_RESET_SCTRL
bl reset_sctrl
#endif
#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
.macro set_vbar, regname, reg
msr \regname, \reg
.endm
adr x0, vectors
#else
.macro set_vbar, regname, reg
.endm
#endif
/*
* Could be EL3/EL2/EL1, Initial State:
* Little Endian, MMU Disabled, i/dCache Disabled
*/
switch_el x1, 3f, 2f, 1f
3: set_vbar vbar_el3, x0
mrs x0, scr_el3
orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
msr scr_el3, x0
msr cptr_el3, xzr /* Enable FP/SIMD */
#ifdef COUNTER_FREQUENCY
ldr x0, =COUNTER_FREQUENCY
msr cntfrq_el0, x0 /* Initialize CNTFRQ */
#endif
b 0f
2: set_vbar vbar_el2, x0
mov x0, #0x33ff
msr cptr_el2, x0 /* Enable FP/SIMD */
b 0f
1: set_vbar vbar_el1, x0
mov x0, #3 << 20
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
/*
* Enable SMPEN bit for coherency.
* This register is not architectural but at the moment
* this bit should be set for A53/A57/A72.
*/
#ifdef CONFIG_ARMV8_SET_SMPEN
switch_el x1, 3f, 1f, 1f
3:
mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
orr x0, x0, #0x40
msr S3_1_c15_c2_1, x0
1:
#endif
/* Apply ARM core specific erratas */
bl apply_core_errata
/*
* Cache/BPB/TLB Invalidate
* i-cache is invalidated before enabled in icache_enable()
* tlb is invalidated before mmu is enabled in dcache_enable()
* d-cache is invalidated before enabled in dcache_enable()
*/
/* Processor specific initialization */
bl lowlevel_init
#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
branch_if_master x0, x1, master_cpu
b spin_table_secondary_jump
/* never return */
#elif defined(CONFIG_ARMV8_MULTIENTRY)
branch_if_master x0, x1, master_cpu
/*
* Slave CPUs
*/
slave_cpu:
wfe
ldr x1, =CPU_RELEASE_ADDR
ldr x0, [x1]
cbz x0, slave_cpu
br x0 /* branch to the given address */
#endif /* CONFIG_ARMV8_MULTIENTRY */
master_cpu:
bl _main
#ifdef CONFIG_SYS_RESET_SCTRL
reset_sctrl:
switch_el x1, 3f, 2f, 1f
3:
mrs x0, sctlr_el3
b 0f
2:
mrs x0, sctlr_el2
b 0f
1:
mrs x0, sctlr_el1
0:
ldr x1, =0xfdfffffa
and x0, x0, x1
switch_el x1, 6f, 5f, 4f
6:
msr sctlr_el3, x0
b 7f
5:
msr sctlr_el2, x0
b 7f
4:
msr sctlr_el1, x0
7:
dsb sy
isb
b __asm_invalidate_tlb_all
ret
#endif
/*-----------------------------------------------------------------------*/
WEAK(apply_core_errata)
mov x29, lr /* Save LR */
/* For now, we support Cortex-A53, Cortex-A57 specific errata */
/* Check if we are running on a Cortex-A53 core */
branch_if_a53_core x0, apply_a53_core_errata
/* Check if we are running on a Cortex-A57 core */
branch_if_a57_core x0, apply_a57_core_errata
0:
mov lr, x29 /* Restore LR */
ret
apply_a53_core_errata:
#ifdef CONFIG_ARM_ERRATA_855873
mrs x0, midr_el1
tst x0, #(0xf << 20)
b.ne 0b
mrs x0, midr_el1
and x0, x0, #0xf
cmp x0, #3
b.lt 0b
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Enable data cache clean as data cache clean/invalidate */
orr x0, x0, #1 << 44
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
b 0b
apply_a57_core_errata:
#ifdef CONFIG_ARM_ERRATA_828024
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable non-allocate hint of w-b-n-a memory type */
orr x0, x0, #1 << 49
/* Disable write streaming no L1-allocate threshold */
orr x0, x0, #3 << 25
/* Disable write streaming no-allocate threshold */
orr x0, x0, #3 << 27
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_826974
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable speculative load execution ahead of a DMB */
orr x0, x0, #1 << 59
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_833471
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* FPSCR write flush.
* Note that in some cases where a flush is unnecessary this
could impact performance. */
orr x0, x0, #1 << 38
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_829520
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable Indirect Predictor bit will prevent this erratum
from occurring
* Note that in some cases where a flush is unnecessary this
could impact performance. */
orr x0, x0, #1 << 4
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_833069
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable Enable Invalidates of BTB bit */
and x0, x0, #0xE
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
b 0b
ENDPROC(apply_core_errata)
/*-----------------------------------------------------------------------*/
WEAK(lowlevel_init)
mov x29, lr /* Save LR */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
bl gic_init_secure
1:
#if defined(CONFIG_GICV3)
ldr x0, =GICR_BASE
bl gic_init_secure_percpu
#elif defined(CONFIG_GICV2)
ldr x0, =GICD_BASE
ldr x1, =GICC_BASE
bl gic_init_secure_percpu
#endif
#endif
#ifdef CONFIG_ARMV8_MULTIENTRY
branch_if_master x0, x1, 2f
/*
* Slave should wait for master clearing spin table.
* This sync prevent salves observing incorrect
* value of spin table and jumping to wrong place.
*/
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
#ifdef CONFIG_GICV2
ldr x0, =GICC_BASE
#endif
bl gic_wait_for_interrupt
#endif
/*
* All slaves will enter EL2 and optionally EL1.
*/
adr x4, lowlevel_in_el2
ldr x5, =ES_TO_AARCH64
bl armv8_switch_to_el2
lowlevel_in_el2:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
adr x4, lowlevel_in_el1
ldr x5, =ES_TO_AARCH64
bl armv8_switch_to_el1
lowlevel_in_el1:
#endif
#endif /* CONFIG_ARMV8_MULTIENTRY */
2:
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
WEAK(smp_kick_all_cpus)
/* Kick secondary cpus up by SGI 0 interrupt */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
ldr x0, =GICD_BASE
b gic_kick_secondary_cpus
#endif
ret
ENDPROC(smp_kick_all_cpus)
/*-----------------------------------------------------------------------*/
ENTRY(c_runtime_cpu_setup)
#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
/* Relocate vBAR */
adr x0, vectors
switch_el x1, 3f, 2f, 1f
3: msr vbar_el3, x0
b 0f
2: msr vbar_el2, x0
b 0f
1: msr vbar_el1, x0
0:
#endif
ret
ENDPROC(c_runtime_cpu_setup)
WEAK(save_boot_params)
b save_boot_params_ret /* back to my caller */
ENDPROC(save_boot_params)
|
genetel200/u-boot
| 1,052
|
arch/arm/cpu/armv8/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* A lowlevel_init function that sets up the stack to call a C function to
* perform further init.
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
/*
* Setup a temporary stack. Global data is not available yet.
*/
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr w0, =CONFIG_SPL_STACK
#else
ldr w0, =CONFIG_SYS_INIT_SP_ADDR
#endif
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
/*
* Save the old LR(passed in x29) and the current LR to stack
*/
stp x29, x30, [sp, #-16]!
/*
* Call the very early init function. This should do only the
* absolute bare minimum to get started. It should not:
*
* - set up DRAM
* - use global_data
* - clear BSS
* - try to start a console
*
* For boards with SPL this should be empty since SPL can do all of
* this init in the SPL board_init_f() function which is called
* immediately after this.
*/
bl s_init
ldp x29, x30, [sp]
ret
ENDPROC(lowlevel_init)
|
genetel200/u-boot
| 4,382
|
arch/arm/cpu/armv8/exceptions.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/ptrace.h>
#include <asm/macro.h>
#include <linux/linkage.h>
/*
* AArch64 exception vectors:
* We have four types of exceptions:
* - synchronous: traps, data aborts, undefined instructions, ...
* - IRQ: group 1 (normal) interrupts
* - FIQ: group 0 or secure interrupts
* - SError: fatal system errors
* There are entries for all four of those for different contexts:
* - from same exception level, when using the SP_EL0 stack pointer
* - from same exception level, when using the SP_ELx stack pointer
* - from lower exception level, when this is AArch64
* - from lower exception level, when this is AArch32
* Each of those 16 entries have space for 32 instructions, each entry must
* be 128 byte aligned, the whole table must be 2K aligned.
* The 32 instructions are not enough to save and restore all registers and
* to branch to the actual handler, so we split this up:
* Each entry saves the LR, branches to the save routine, then to the actual
* handler, then to the restore routine. The save and restore routines are
* each split in half and stuffed in the unused gap between the entries.
* Also as we do not run anything in a lower exception level, we just provide
* the first 8 entries for exceptions from the same EL.
*/
.align 11
.globl vectors
vectors:
.align 7 /* Current EL Synchronous Thread */
stp x29, x30, [sp, #-16]!
bl _exception_entry
bl do_bad_sync
b exception_exit
/*
* Save (most of) the GP registers to the stack frame.
* This is the first part of the shared routine called into from all entries.
*/
_exception_entry:
stp x27, x28, [sp, #-16]!
stp x25, x26, [sp, #-16]!
stp x23, x24, [sp, #-16]!
stp x21, x22, [sp, #-16]!
stp x19, x20, [sp, #-16]!
stp x17, x18, [sp, #-16]!
stp x15, x16, [sp, #-16]!
stp x13, x14, [sp, #-16]!
stp x11, x12, [sp, #-16]!
stp x9, x10, [sp, #-16]!
stp x7, x8, [sp, #-16]!
stp x5, x6, [sp, #-16]!
stp x3, x4, [sp, #-16]!
stp x1, x2, [sp, #-16]!
b _save_el_regs /* jump to the second part */
.align 7 /* Current EL IRQ Thread */
stp x29, x30, [sp, #-16]!
bl _exception_entry
bl do_bad_irq
b exception_exit
/*
* Save exception specific context: ESR and ELR, for all exception levels.
* This is the second part of the shared routine called into from all entries.
*/
_save_el_regs:
/* Could be running at EL3/EL2/EL1 */
switch_el x11, 3f, 2f, 1f
3: mrs x1, esr_el3
mrs x2, elr_el3
b 0f
2: mrs x1, esr_el2
mrs x2, elr_el2
b 0f
1: mrs x1, esr_el1
mrs x2, elr_el1
0:
stp x2, x0, [sp, #-16]!
mov x0, sp
ret
.align 7 /* Current EL FIQ Thread */
stp x29, x30, [sp, #-16]!
bl _exception_entry
bl do_bad_fiq
/* falling through to _exception_exit */
/*
* Restore the exception return address, for all exception levels.
* This is the first part of the shared routine called into from all entries.
*/
exception_exit:
ldp x2, x0, [sp],#16
switch_el x11, 3f, 2f, 1f
3: msr elr_el3, x2
b _restore_regs
2: msr elr_el2, x2
b _restore_regs
1: msr elr_el1, x2
b _restore_regs /* jump to the second part */
.align 7 /* Current EL Error Thread */
stp x29, x30, [sp, #-16]!
bl _exception_entry
bl do_bad_error
b exception_exit
/*
* Restore the general purpose registers from the exception stack, then return.
* This is the second part of the shared routine called into from all entries.
*/
_restore_regs:
ldp x1, x2, [sp],#16
ldp x3, x4, [sp],#16
ldp x5, x6, [sp],#16
ldp x7, x8, [sp],#16
ldp x9, x10, [sp],#16
ldp x11, x12, [sp],#16
ldp x13, x14, [sp],#16
ldp x15, x16, [sp],#16
ldp x17, x18, [sp],#16
ldp x19, x20, [sp],#16
ldp x21, x22, [sp],#16
ldp x23, x24, [sp],#16
ldp x25, x26, [sp],#16
ldp x27, x28, [sp],#16
ldp x29, x30, [sp],#16
eret
.align 7 /* Current EL (SP_ELx) Synchronous Handler */
stp x29, x30, [sp, #-16]!
bl _exception_entry
bl do_sync
b exception_exit
.align 7 /* Current EL (SP_ELx) IRQ Handler */
stp x29, x30, [sp, #-16]!
bl _exception_entry
bl do_irq
b exception_exit
.align 7 /* Current EL (SP_ELx) FIQ Handler */
stp x29, x30, [sp, #-16]!
bl _exception_entry
bl do_fiq
b exception_exit
.align 7 /* Current EL (SP_ELx) Error Handler */
stp x29, x30, [sp, #-16]!
bl _exception_entry
bl do_error
b exception_exit
|
genetel200/u-boot
| 1,131
|
arch/arm/cpu/armv8/transition.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
.pushsection .text.armv8_switch_to_el2, "ax"
ENTRY(armv8_switch_to_el2)
switch_el x6, 1f, 0f, 0f
0:
cmp x5, #ES_TO_AARCH64
b.eq 2f
/*
* When loading 32-bit kernel, it will jump
* to secure firmware again, and never return.
*/
bl armv8_el2_to_aarch32
2:
/*
* x4 is kernel entry point or switch_to_el1
* if CONFIG_ARMV8_SWITCH_TO_EL1 is defined.
* When running in EL2 now, jump to the
* address saved in x4.
*/
br x4
1: armv8_switch_to_el2_m x4, x5, x6
ENDPROC(armv8_switch_to_el2)
.popsection
.pushsection .text.armv8_switch_to_el1, "ax"
ENTRY(armv8_switch_to_el1)
switch_el x6, 0f, 1f, 0f
0:
/* x4 is kernel entry point. When running in EL1
* now, jump to the address saved in x4.
*/
br x4
1: armv8_switch_to_el1_m x4, x5, x6
ENDPROC(armv8_switch_to_el1)
.popsection
.pushsection .text.armv8_el2_to_aarch32, "ax"
WEAK(armv8_el2_to_aarch32)
ret
ENDPROC(armv8_el2_to_aarch32)
.popsection
|
genetel200/u-boot
| 1,208
|
arch/arm/cpu/armv8/smccc-call.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015, Linaro Limited
*/
#include <linux/linkage.h>
#include <linux/arm-smccc.h>
#include <generated/asm-offsets.h>
#ifdef CONFIG_EFI_LOADER
.section .text.efi_runtime
#endif
.macro SMCCC instr
.cfi_startproc
\instr #0
ldr x4, [sp]
stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
ldr x4, [sp, #8]
cbz x4, 1f /* no quirk structure */
ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6
b.ne 1f
str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
1: ret
.cfi_endproc
.endm
/*
* void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
* unsigned long a3, unsigned long a4, unsigned long a5,
* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
* struct arm_smccc_quirk *quirk)
*/
ENTRY(__arm_smccc_smc)
SMCCC smc
ENDPROC(__arm_smccc_smc)
/*
* void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
* unsigned long a3, unsigned long a4, unsigned long a5,
* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
* struct arm_smccc_quirk *quirk)
*/
ENTRY(__arm_smccc_hvc)
SMCCC hvc
ENDPROC(__arm_smccc_hvc)
|
genetel200/u-boot
| 8,502
|
arch/arm/cpu/armv8/psci.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Author: Hongbo Zhang <hongbo.zhang@nxp.com>
* This file implements LS102X platform PSCI SYSTEM-SUSPEND function
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/psci.h>
/* Default PSCI function, return -1, Not Implemented */
#define PSCI_DEFAULT(__fn) \
ENTRY(__fn); \
mov w0, #ARM_PSCI_RET_NI; \
ret; \
ENDPROC(__fn); \
.weak __fn
/* PSCI function and ID table definition*/
#define PSCI_TABLE(__id, __fn) \
.word __id; \
.word __fn
.pushsection ._secure.text, "ax"
/* 32 bits PSCI default functions */
PSCI_DEFAULT(psci_version)
PSCI_DEFAULT(psci_cpu_suspend)
PSCI_DEFAULT(psci_cpu_off)
PSCI_DEFAULT(psci_cpu_on)
PSCI_DEFAULT(psci_affinity_info)
PSCI_DEFAULT(psci_migrate)
PSCI_DEFAULT(psci_migrate_info_type)
PSCI_DEFAULT(psci_migrate_info_up_cpu)
PSCI_DEFAULT(psci_system_off)
PSCI_DEFAULT(psci_system_reset)
PSCI_DEFAULT(psci_features)
PSCI_DEFAULT(psci_cpu_freeze)
PSCI_DEFAULT(psci_cpu_default_suspend)
PSCI_DEFAULT(psci_node_hw_state)
PSCI_DEFAULT(psci_system_suspend)
PSCI_DEFAULT(psci_set_suspend_mode)
PSCI_DEFAULT(psi_stat_residency)
PSCI_DEFAULT(psci_stat_count)
.align 3
_psci_32_table:
PSCI_TABLE(ARM_PSCI_FN_CPU_SUSPEND, psci_cpu_suspend)
PSCI_TABLE(ARM_PSCI_FN_CPU_OFF, psci_cpu_off)
PSCI_TABLE(ARM_PSCI_FN_CPU_ON, psci_cpu_on)
PSCI_TABLE(ARM_PSCI_FN_MIGRATE, psci_migrate)
PSCI_TABLE(ARM_PSCI_0_2_FN_PSCI_VERSION, psci_version)
PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_SUSPEND, psci_cpu_suspend)
PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_OFF, psci_cpu_off)
PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_ON, psci_cpu_on)
PSCI_TABLE(ARM_PSCI_0_2_FN_AFFINITY_INFO, psci_affinity_info)
PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE, psci_migrate)
PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE, psci_migrate_info_type)
PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu)
PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_OFF, psci_system_off)
PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_RESET, psci_system_reset)
PSCI_TABLE(ARM_PSCI_1_0_FN_PSCI_FEATURES, psci_features)
PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_FREEZE, psci_cpu_freeze)
PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend)
PSCI_TABLE(ARM_PSCI_1_0_FN_NODE_HW_STATE, psci_node_hw_state)
PSCI_TABLE(ARM_PSCI_1_0_FN_SYSTEM_SUSPEND, psci_system_suspend)
PSCI_TABLE(ARM_PSCI_1_0_FN_SET_SUSPEND_MODE, psci_set_suspend_mode)
PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_RESIDENCY, psi_stat_residency)
PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_COUNT, psci_stat_count)
PSCI_TABLE(0, 0)
/* 64 bits PSCI default functions */
PSCI_DEFAULT(psci_cpu_suspend_64)
PSCI_DEFAULT(psci_cpu_on_64)
PSCI_DEFAULT(psci_affinity_info_64)
PSCI_DEFAULT(psci_migrate_64)
PSCI_DEFAULT(psci_migrate_info_up_cpu_64)
PSCI_DEFAULT(psci_cpu_default_suspend_64)
PSCI_DEFAULT(psci_node_hw_state_64)
PSCI_DEFAULT(psci_system_suspend_64)
PSCI_DEFAULT(psci_stat_residency_64)
PSCI_DEFAULT(psci_stat_count_64)
.align 3
_psci_64_table:
PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_SUSPEND, psci_cpu_suspend_64)
PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_ON, psci_cpu_on_64)
PSCI_TABLE(ARM_PSCI_0_2_FN64_AFFINITY_INFO, psci_affinity_info_64)
PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE, psci_migrate_64)
PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu_64)
PSCI_TABLE(ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend_64)
PSCI_TABLE(ARM_PSCI_1_0_FN64_NODE_HW_STATE, psci_node_hw_state_64)
PSCI_TABLE(ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND, psci_system_suspend_64)
PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_RESIDENCY, psci_stat_residency_64)
PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_COUNT, psci_stat_count_64)
PSCI_TABLE(0, 0)
.macro psci_enter
/* PSCI call is Fast Call(atomic), so mask DAIF */
mrs x15, DAIF
stp x15, xzr, [sp, #-16]!
ldr x15, =0x3C0
msr DAIF, x15
/* SMC convention, x18 ~ x30 should be saved by callee */
stp x29, x30, [sp, #-16]!
stp x27, x28, [sp, #-16]!
stp x25, x26, [sp, #-16]!
stp x23, x24, [sp, #-16]!
stp x21, x22, [sp, #-16]!
stp x19, x20, [sp, #-16]!
mrs x15, elr_el3
stp x18, x15, [sp, #-16]!
.endm
.macro psci_return
/* restore registers */
ldp x18, x15, [sp], #16
msr elr_el3, x15
ldp x19, x20, [sp], #16
ldp x21, x22, [sp], #16
ldp x23, x24, [sp], #16
ldp x25, x26, [sp], #16
ldp x27, x28, [sp], #16
ldp x29, x30, [sp], #16
/* restore DAIF */
ldp x15, xzr, [sp], #16
msr DAIF, x15
eret
.endm
/* Caller must put PSCI function-ID table base in x9 */
handle_psci:
psci_enter
1: ldr x10, [x9] /* Load PSCI function table */
ubfx x11, x10, #32, #32
ubfx x10, x10, #0, #32
cbz x10, 3f /* If reach the end, bail out */
cmp x10, x0
b.eq 2f /* PSCI function found */
add x9, x9, #8 /* If not match, try next entry */
b 1b
2: blr x11 /* Call PSCI function */
psci_return
3: mov x0, #ARM_PSCI_RET_NI
psci_return
unknown_smc_id:
ldr x0, =0xFFFFFFFF
eret
handle_smc32:
/* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */
ldr w9, =0x8400001F
cmp w0, w9
b.gt unknown_smc_id
ldr w9, =0x84000000
cmp w0, w9
b.lt unknown_smc_id
adr x9, _psci_32_table
b handle_psci
handle_smc64:
/* check SMC32 or SMC64 calls */
ubfx x9, x0, #30, #1
cbz x9, handle_smc32
/* SMC function ID 0xC4000000-0xC400001F: 64 bits PSCI */
ldr x9, =0xC400001F
cmp x0, x9
b.gt unknown_smc_id
ldr x9, =0xC4000000
cmp x0, x9
b.lt unknown_smc_id
adr x9, _psci_64_table
b handle_psci
/*
* Get CPU ID from MPIDR, suppose every cluster has same number of CPU cores,
* Platform with asymmetric clusters should implement their own interface.
* In case this function being called by other platform's C code, the ARM
* Architecture Procedure Call Standard is considered, e.g. register X0 is
* used for the return value, while in this PSCI environment, X0 usually holds
* the SMC function identifier, so X0 should be saved by caller function.
*/
ENTRY(psci_get_cpu_id)
#ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
mrs x9, MPIDR_EL1
ubfx x9, x9, #8, #8
ldr x10, =CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
mul x9, x10, x9
#else
mov x9, xzr
#endif
mrs x10, MPIDR_EL1
ubfx x10, x10, #0, #8
add x0, x10, x9
ret
ENDPROC(psci_get_cpu_id)
.weak psci_get_cpu_id
/* CPU ID input in x0, stack top output in x0*/
LENTRY(psci_get_cpu_stack_top)
adr x9, __secure_stack_end
lsl x0, x0, #ARM_PSCI_STACK_SHIFT
sub x0, x9, x0
ret
ENDPROC(psci_get_cpu_stack_top)
unhandled_exception:
b unhandled_exception /* simply dead loop */
handle_sync:
mov x15, x30
mov x14, x0
bl psci_get_cpu_id
bl psci_get_cpu_stack_top
mov x9, #1
msr spsel, x9
mov sp, x0
mov x0, x14
mov x30, x15
mrs x9, esr_el3
ubfx x9, x9, #26, #6
cmp x9, #0x13
b.eq handle_smc32
cmp x9, #0x17
b.eq handle_smc64
b unhandled_exception
#ifdef CONFIG_ARMV8_EA_EL3_FIRST
/*
* Override this function if custom error handling is
* needed for asynchronous aborts
*/
ENTRY(plat_error_handler)
ret
ENDPROC(plat_error_handler)
.weak plat_error_handler
handle_error:
bl psci_get_cpu_id
bl psci_get_cpu_stack_top
mov x9, #1
msr spsel, x9
mov sp, x0
bl plat_error_handler /* Platform specific error handling */
deadloop:
b deadloop /* Never return */
#endif
.align 11
.globl el3_exception_vectors
el3_exception_vectors:
b unhandled_exception /* Sync, Current EL using SP0 */
.align 7
b unhandled_exception /* IRQ, Current EL using SP0 */
.align 7
b unhandled_exception /* FIQ, Current EL using SP0 */
.align 7
b unhandled_exception /* SError, Current EL using SP0 */
.align 7
b unhandled_exception /* Sync, Current EL using SPx */
.align 7
b unhandled_exception /* IRQ, Current EL using SPx */
.align 7
b unhandled_exception /* FIQ, Current EL using SPx */
.align 7
b unhandled_exception /* SError, Current EL using SPx */
.align 7
b handle_sync /* Sync, Lower EL using AArch64 */
.align 7
b unhandled_exception /* IRQ, Lower EL using AArch64 */
.align 7
b unhandled_exception /* FIQ, Lower EL using AArch64 */
.align 7
#ifdef CONFIG_ARMV8_EA_EL3_FIRST
b handle_error /* SError, Lower EL using AArch64 */
#else
b unhandled_exception /* SError, Lower EL using AArch64 */
#endif
.align 7
b unhandled_exception /* Sync, Lower EL using AArch32 */
.align 7
b unhandled_exception /* IRQ, Lower EL using AArch32 */
.align 7
b unhandled_exception /* FIQ, Lower EL using AArch32 */
.align 7
b unhandled_exception /* SError, Lower EL using AArch32 */
ENTRY(psci_setup_vectors)
adr x0, el3_exception_vectors
msr vbar_el3, x0
ret
ENDPROC(psci_setup_vectors)
ENTRY(psci_arch_init)
ret
ENDPROC(psci_arch_init)
.weak psci_arch_init
.popsection
|
genetel200/u-boot
| 1,430
|
arch/arm/cpu/armv8/sec_firmware_asm.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 NXP Semiconductor, Inc.
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/system.h>
#include <asm/macro.h>
WEAK(_sec_firmware_entry)
/*
* x0: Secure Firmware entry point
* x1: Exception return address Low
* x2: Exception return address High
*/
/* Save stack pointer for EL2 */
mov x3, sp
msr sp_el2, x3
/* Set exception return address hold pointer */
adr x4, 1f
mov x3, x4
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
rev w3, w3
#endif
str w3, [x1]
lsr x3, x4, #32
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
rev w3, w3
#endif
str w3, [x2]
/* Call SEC monitor */
br x0
1:
mov x0, #0
ret
ENDPROC(_sec_firmware_entry)
#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI
ENTRY(_sec_firmware_support_psci_version)
mov x0, 0x84000000
mov x1, 0x0
mov x2, 0x0
mov x3, 0x0
smc #0
ret
ENDPROC(_sec_firmware_support_psci_version)
/*
* Switch from AArch64 EL2 to AArch32 EL2
* @param inputs:
* x0: argument, zero
* x1: machine nr
* x2: fdt address
* x3: input argument
* x4: kernel entry point
* @param outputs for secure firmware:
* x0: function id
* x1: kernel entry point
* x2: machine nr
* x3: fdt address
*/
ENTRY(armv8_el2_to_aarch32)
mov x3, x2
mov x2, x1
mov x1, x4
ldr x0, =0xc200ff17
smc #0
ret
ENDPROC(armv8_el2_to_aarch32)
#endif
|
genetel200/u-boot
| 6,046
|
arch/arm/cpu/armv8/cache.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* This file is based on sample code from ARMv8 ARM.
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/macro.h>
#include <asm/system.h>
#include <linux/linkage.h>
/*
* void __asm_dcache_level(level)
*
* flush or invalidate one level cache.
*
* x0: cache level
* x1: 0 clean & invalidate, 1 invalidate only
* x2~x9: clobbered
*/
.pushsection .text.__asm_dcache_level, "ax"
ENTRY(__asm_dcache_level)
lsl x12, x0, #1
msr csselr_el1, x12 /* select cache level */
isb /* sync change of cssidr_el1 */
mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
add x2, x2, #4 /* x2 <- log2(cache line size) */
mov x3, #0x3ff
and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
clz w5, w3 /* bit position of #ways */
mov x4, #0x7fff
and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
/* x12 <- cache level << 1 */
/* x2 <- line length offset */
/* x3 <- number of cache ways - 1 */
/* x4 <- number of cache sets - 1 */
/* x5 <- bit position of #ways */
loop_set:
mov x6, x3 /* x6 <- working copy of #ways */
loop_way:
lsl x7, x6, x5
orr x9, x12, x7 /* map way and level to cisw value */
lsl x7, x4, x2
orr x9, x9, x7 /* map set number to cisw value */
tbz w1, #0, 1f
dc isw, x9
b 2f
1: dc cisw, x9 /* clean & invalidate by set/way */
2: subs x6, x6, #1 /* decrement the way */
b.ge loop_way
subs x4, x4, #1 /* decrement the set */
b.ge loop_set
ret
ENDPROC(__asm_dcache_level)
.popsection
/*
* void __asm_flush_dcache_all(int invalidate_only)
*
* x0: 0 clean & invalidate, 1 invalidate only
*
* flush or invalidate all data cache by SET/WAY.
*/
.pushsection .text.__asm_dcache_all, "ax"
ENTRY(__asm_dcache_all)
mov x1, x0
dsb sy
mrs x10, clidr_el1 /* read clidr_el1 */
lsr x11, x10, #24
and x11, x11, #0x7 /* x11 <- loc */
cbz x11, finished /* if loc is 0, exit */
mov x15, lr
mov x0, #0 /* start flush at cache level 0 */
/* x0 <- cache level */
/* x10 <- clidr_el1 */
/* x11 <- loc */
/* x15 <- return address */
loop_level:
lsl x12, x0, #1
add x12, x12, x0 /* x0 <- tripled cache level */
lsr x12, x10, x12
and x12, x12, #7 /* x12 <- cache type */
cmp x12, #2
b.lt skip /* skip if no cache or icache */
bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */
skip:
add x0, x0, #1 /* increment cache level */
cmp x11, x0
b.gt loop_level
mov x0, #0
msr csselr_el1, x0 /* restore csselr_el1 */
dsb sy
isb
mov lr, x15
finished:
ret
ENDPROC(__asm_dcache_all)
.popsection
.pushsection .text.__asm_flush_dcache_all, "ax"
ENTRY(__asm_flush_dcache_all)
mov x0, #0
b __asm_dcache_all
ENDPROC(__asm_flush_dcache_all)
.popsection
.pushsection .text.__asm_invalidate_dcache_all, "ax"
ENTRY(__asm_invalidate_dcache_all)
mov x0, #0x1
b __asm_dcache_all
ENDPROC(__asm_invalidate_dcache_all)
.popsection
/*
* void __asm_flush_dcache_range(start, end)
*
* clean & invalidate data cache in the range
*
* x0: start address
* x1: end address
*/
.pushsection .text.__asm_flush_dcache_range, "ax"
ENTRY(__asm_flush_dcache_range)
mrs x3, ctr_el0
lsr x3, x3, #16
and x3, x3, #0xf
mov x2, #4
lsl x2, x2, x3 /* cache line size */
/* x2 <- minimal cache line size in cache system */
sub x3, x2, #1
bic x0, x0, x3
1: dc civac, x0 /* clean & invalidate data or unified cache */
add x0, x0, x2
cmp x0, x1
b.lo 1b
dsb sy
ret
ENDPROC(__asm_flush_dcache_range)
.popsection
/*
* void __asm_invalidate_dcache_range(start, end)
*
* invalidate data cache in the range
*
* x0: start address
* x1: end address
*/
.pushsection .text.__asm_invalidate_dcache_range, "ax"
ENTRY(__asm_invalidate_dcache_range)
mrs x3, ctr_el0
ubfm x3, x3, #16, #19
mov x2, #4
lsl x2, x2, x3 /* cache line size */
/* x2 <- minimal cache line size in cache system */
sub x3, x2, #1
bic x0, x0, x3
1: dc ivac, x0 /* invalidate data or unified cache */
add x0, x0, x2
cmp x0, x1
b.lo 1b
dsb sy
ret
ENDPROC(__asm_invalidate_dcache_range)
.popsection
/*
* void __asm_invalidate_icache_all(void)
*
* invalidate all tlb entries.
*/
.pushsection .text.__asm_invalidate_icache_all, "ax"
ENTRY(__asm_invalidate_icache_all)
ic ialluis
isb sy
ret
ENDPROC(__asm_invalidate_icache_all)
.popsection
.pushsection .text.__asm_invalidate_l3_dcache, "ax"
ENTRY(__asm_invalidate_l3_dcache)
mov x0, #0 /* return status as success */
ret
ENDPROC(__asm_invalidate_l3_dcache)
.weak __asm_invalidate_l3_dcache
.popsection
.pushsection .text.__asm_flush_l3_dcache, "ax"
ENTRY(__asm_flush_l3_dcache)
mov x0, #0 /* return status as success */
ret
ENDPROC(__asm_flush_l3_dcache)
.weak __asm_flush_l3_dcache
.popsection
.pushsection .text.__asm_invalidate_l3_icache, "ax"
ENTRY(__asm_invalidate_l3_icache)
mov x0, #0 /* return status as success */
ret
ENDPROC(__asm_invalidate_l3_icache)
.weak __asm_invalidate_l3_icache
.popsection
/*
* void __asm_switch_ttbr(ulong new_ttbr)
*
* Safely switches to a new page table.
*/
.pushsection .text.__asm_switch_ttbr, "ax"
ENTRY(__asm_switch_ttbr)
/* x2 = SCTLR (alive throghout the function) */
switch_el x4, 3f, 2f, 1f
3: mrs x2, sctlr_el3
b 0f
2: mrs x2, sctlr_el2
b 0f
1: mrs x2, sctlr_el1
0:
/* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */
movn x1, #(CR_M | CR_C | CR_I)
and x1, x2, x1
switch_el x4, 3f, 2f, 1f
3: msr sctlr_el3, x1
b 0f
2: msr sctlr_el2, x1
b 0f
1: msr sctlr_el1, x1
0: isb
/* This call only clobbers x30 (lr) and x9 (unused) */
mov x3, x30
bl __asm_invalidate_tlb_all
/* From here on we're running safely with caches disabled */
/* Set TTBR to our first argument */
switch_el x4, 3f, 2f, 1f
3: msr ttbr0_el3, x0
b 0f
2: msr ttbr0_el2, x0
b 0f
1: msr ttbr0_el1, x0
0: isb
/* Restore original SCTLR and thus enable caches again */
switch_el x4, 3f, 2f, 1f
3: msr sctlr_el3, x2
b 0f
2: msr sctlr_el2, x2
b 0f
1: msr sctlr_el1, x2
0: isb
ret x3
ENDPROC(__asm_switch_ttbr)
.popsection
|
genetel200/u-boot
| 1,657
|
arch/arm/cpu/arm720t/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM720 CPU-core
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
*/
#include <asm-offsets.h>
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from RAM!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
bl cpu_init_crit
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
cpu_init_crit:
mov ip, lr
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependent, you will
* find a lowlevel_init.S in your board directory.
*/
bl lowlevel_init
mov lr, ip
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
genetel200/u-boot
| 2,432
|
arch/arm/cpu/arm1136/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for OMP2420/ARM1136 CPU-core
*
* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
*/
#include <asm-offsets.h>
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
bx lr
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 1 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Jump to board specific initialization... The Mask ROM will have already initialized
* basic memory. Go here to bump up clock rate and handle wake up conditions.
*/
mov ip, lr /* persevere link reg across call */
bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
genetel200/u-boot
| 5,656
|
arch/arm/cpu/armv7/nonsec_virt.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* code for switching cores into non-secure state and into HYP mode
*
* Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/armv7.h>
#include <asm/proc-armv/ptrace.h>
.arch_extension sec
.arch_extension virt
.pushsection ._secure.text, "ax"
.align 5
/* the vector table for secure state and HYP mode */
_monitor_vectors:
.word 0 /* reset */
.word 0 /* undef */
adr pc, _secure_monitor
.word 0
.word 0
.word 0
.word 0
.word 0
.macro is_cpu_virt_capable tmp
mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT)
.endm
/*
* secure monitor handler
* U-Boot calls this "software interrupt" in start.S
* This is executed on a "smc" instruction, we use a "smc #0" to switch
* to non-secure state.
* r0, r1, r2: passed to the callee
* ip: target PC
*/
_secure_monitor:
#ifdef CONFIG_ARMV7_PSCI
ldr r5, =_psci_vectors @ Switch to the next monitor
mcr p15, 0, r5, c12, c0, 1
isb
@ Obtain a secure stack
bl psci_stack_setup
@ Configure the PSCI backend
push {r0, r1, r2, ip}
bl psci_arch_init
pop {r0, r1, r2, ip}
#endif
#ifdef CONFIG_ARM_ERRATA_773022
mrc p15, 0, r5, c1, c0, 1
orr r5, r5, #(1 << 1)
mcr p15, 0, r5, c1, c0, 1
isb
#endif
#ifdef CONFIG_ARM_ERRATA_774769
mrc p15, 0, r5, c1, c0, 1
orr r5, r5, #(1 << 25)
mcr p15, 0, r5, c1, c0, 1
isb
#endif
mrc p15, 0, r5, c1, c1, 0 @ read SCR
bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
orr r5, r5, #0x31 @ enable NS, AW, FW bits
@ FIQ preserved for secure mode
mov r6, #SVC_MODE @ default mode is SVC
is_cpu_virt_capable r4
#ifdef CONFIG_ARMV7_VIRT
orreq r5, r5, #0x100 @ allow HVC instruction
moveq r6, #HYP_MODE @ Enter the kernel as HYP
mrseq r3, sp_svc
msreq sp_hyp, r3 @ migrate SP
#endif
mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
isb
bne 1f
@ Reset CNTVOFF to 0 before leaving monitor mode
mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
movne r4, #0
mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
1:
mov lr, ip
mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
tst lr, #1 @ Check for Thumb PC
orrne ip, ip, #T_BIT @ Set T if Thumb
orr ip, ip, r6 @ Slot target mode in
msr spsr_cxfs, ip @ Set full SPSR
movs pc, lr @ ERET to non-secure
ENTRY(_do_nonsec_entry)
mov ip, r0
mov r0, r1
mov r1, r2
mov r2, r3
smc #0
ENDPROC(_do_nonsec_entry)
.macro get_cbar_addr addr
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS
#else
mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
bfc \addr, #0, #15 @ clear reserved bits
#endif
.endm
.macro get_gicd_addr addr
get_cbar_addr \addr
add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
.endm
.macro get_gicc_addr addr, tmp
get_cbar_addr \addr
is_cpu_virt_capable \tmp
movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
add \addr, \addr, \tmp
.endm
#ifndef CONFIG_ARMV7_PSCI
/*
* Secondary CPUs start here and call the code for the core specific parts
* of the non-secure and HYP mode transition. The GIC distributor specific
* code has already been executed by a C function before.
* Then they go back to wfi and wait to be woken up by the kernel again.
*/
ENTRY(_smp_pen)
cpsid i
cpsid f
bl _nonsec_init
adr r0, _smp_pen @ do not use this address again
b smp_waitloop @ wait for IPIs, board specific
ENDPROC(_smp_pen)
#endif
/*
* Switch a core to non-secure state.
*
* 1. initialize the GIC per-core interface
* 2. allow coprocessor access in non-secure modes
*
* Called from smp_pen by secondary cores and directly by the BSP.
* Do not assume that the stack is available and only use registers
* r0-r3 and r12.
*
* PERIPHBASE is used to get the GIC address. This could be 40 bits long,
* though, but we check this in C before calling this function.
*/
ENTRY(_nonsec_init)
get_gicd_addr r3
mvn r1, #0 @ all bits to 1
str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
get_gicc_addr r3, r1
mov r1, #3 @ Enable both groups
str r1, [r3, #GICC_CTLR] @ and clear all other bits
mov r1, #0xff
str r1, [r3, #GICC_PMR] @ set priority mask register
mrc p15, 0, r0, c1, c1, 2
movw r1, #0x3fff
movt r1, #0x0004
orr r0, r0, r1
mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec
/* The CNTFRQ register of the generic timer needs to be
* programmed in secure state. Some primary bootloaders / firmware
* omit this, so if the frequency is provided in the configuration,
* we do this here instead.
* But first check if we have the generic timer.
*/
#ifdef COUNTER_FREQUENCY
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
ldreq r1, =COUNTER_FREQUENCY
mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
#endif
adr r1, _monitor_vectors
mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
isb
mov r0, r3 @ return GICC address
bx lr
ENDPROC(_nonsec_init)
#ifdef CONFIG_SMP_PEN_ADDR
/* void __weak smp_waitloop(unsigned previous_address); */
ENTRY(smp_waitloop)
wfi
ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
ldr r1, [r1]
#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
rev r1, r1
#endif
cmp r0, r1 @ make sure we dont execute this code
beq smp_waitloop @ again (due to a spurious wakeup)
mov r0, r1
b _do_nonsec_entry
ENDPROC(smp_waitloop)
.weak smp_waitloop
#endif
.popsection
|
genetel200/u-boot
| 10,436
|
arch/arm/cpu/armv7/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
*
* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/system.h>
#include <linux/linkage.h>
#include <asm/armv7.h>
/*************************************************************************
*
* Startup Code (reset vector)
*
* Do important init only if we don't start from memory!
* Setup memory and board specific bits prior to relocation.
* Relocate armboot to ram. Setup stack.
*
*************************************************************************/
.globl reset
.globl save_boot_params_ret
.type save_boot_params_ret,%function
#ifdef CONFIG_ARMV7_LPAE
.global switch_to_hypervisor_ret
#endif
reset:
/* Allow the board to save important registers */
b save_boot_params
save_boot_params_ret:
#ifdef CONFIG_ARMV7_LPAE
/*
* check for Hypervisor support
*/
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
beq switch_to_hypervisor
switch_to_hypervisor_ret:
#endif
/*
* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
* except if in HYP mode already
*/
mrs r0, cpsr
and r1, r0, #0x1f @ mask mode bits
teq r1, #0x1a @ test for HYP mode
bicne r0, r0, #0x1f @ clear all mode bits
orrne r0, r0, #0x13 @ set SVC mode
orr r0, r0, #0xc0 @ disable FIQ and IRQ
msr cpsr,r0
/*
* Setup vector:
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
* Continue to use ROM code vector only in OMAP4 spl)
*/
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
bic r0, #CR_V @ V = 0
mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
#ifdef CONFIG_HAS_VBAR
/* Set vector address in CP15 VBAR register */
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
#endif
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_CPU_V7A
bl cpu_init_cp15
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
bl cpu_init_crit
#endif
#endif
bl _main
/*------------------------------------------------------------------------------*/
ENTRY(c_runtime_cpu_setup)
/*
* If I-cache is enabled invalidate it
*/
#ifndef CONFIG_SYS_ICACHE_OFF
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
#endif
bx lr
ENDPROC(c_runtime_cpu_setup)
/*************************************************************************
*
* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
* __attribute__((weak));
*
* Stack pointer is not yet initialized at this moment
* Don't save anything to stack even if compiled with -O0
*
*************************************************************************/
ENTRY(save_boot_params)
b save_boot_params_ret @ back to my caller
ENDPROC(save_boot_params)
.weak save_boot_params
#ifdef CONFIG_ARMV7_LPAE
ENTRY(switch_to_hypervisor)
b switch_to_hypervisor_ret
ENDPROC(switch_to_hypervisor)
.weak switch_to_hypervisor
#endif
/*************************************************************************
*
* cpu_init_cp15
*
* Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
* CONFIG_SYS_ICACHE_OFF is defined.
*
*************************************************************************/
ENTRY(cpu_init_cp15)
/*
* Invalidate L1 I/D
*/
mov r0, #0 @ set up for MCR
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
#ifdef CONFIG_SYS_ICACHE_OFF
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
#else
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
#endif
mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_ARM_ERRATA_716044
mrc p15, 0, r0, c1, c0, 0 @ read system control register
orr r0, r0, #1 << 11 @ set bit #11
mcr p15, 0, r0, c1, c0, 0 @ write system control register
#endif
#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 4 @ set bit #4
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 6 @ set bit #6
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_751472
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 11 @ set bit #11
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_761320
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 21 @ set bit #21
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_845369
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 22 @ set bit #22
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
mov r5, lr @ Store my Caller
mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
mov r3, r1, lsr #20 @ get variant field
and r3, r3, #0xf @ r3 has CPU variant
and r4, r1, #0xf @ r4 has CPU revision
mov r2, r3, lsl #4 @ shift variant field for combined value
orr r2, r4, r2 @ r2 has combined CPU variant + revision
/* Early stack for ERRATA that needs into call C code */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
#endif
bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
mov sp, r0
#ifdef CONFIG_ARM_ERRATA_798870
cmp r2, #0x30 @ Applies to lower than R3p0
bge skip_errata_798870 @ skip if not affected rev
cmp r2, #0x20 @ Applies to including and above R2p0
blt skip_errata_798870 @ skip if not affected rev
mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_l2aux_ctrl
isb @ Recommended ISB after l2actlr update
pop {r1-r5} @ Restore the cpu info - fall through
skip_errata_798870:
#endif
#ifdef CONFIG_ARM_ERRATA_801819
cmp r2, #0x24 @ Applies to lt including R2p4
bgt skip_errata_801819 @ skip if not affected rev
cmp r2, #0x20 @ Applies to including and above R2p0
blt skip_errata_801819 @ skip if not affected rev
mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
and r0, r0, #1 << 3 @ check REVIDR[3]
cmp r0, #1 << 3
beq skip_errata_801819 @ skip erratum if REVIDR[3] is set
mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate
@ lines allocate in the L1 or L2 cache.
orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate
@ lines allocate in the L1 cache.
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
skip_errata_801819:
#endif
#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715
mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
orr r0, r0, #1 << 0 @ Enable invalidates of BTB
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
#endif
#ifdef CONFIG_ARM_ERRATA_454179
mrc p15, 0, r0, c1, c0, 1 @ Read ACR
cmp r2, #0x21 @ Only on < r2p1
orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
#endif
#if defined(CONFIG_ARM_ERRATA_430973) || defined (CONFIG_ARM_CORTEX_A8_CVE_2017_5715)
mrc p15, 0, r0, c1, c0, 1 @ Read ACR
#ifdef CONFIG_ARM_CORTEX_A8_CVE_2017_5715
orr r0, r0, #(0x1 << 6) @ Set IBE bit always to enable OS WA
#else
cmp r2, #0x21 @ Only on < r2p1
orrlt r0, r0, #(0x1 << 6) @ Set IBE bit
#endif
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
#endif
#ifdef CONFIG_ARM_ERRATA_621766
mrc p15, 0, r0, c1, c0, 1 @ Read ACR
cmp r2, #0x21 @ Only on < r2p1
orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
#endif
#ifdef CONFIG_ARM_ERRATA_725233
mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR
cmp r2, #0x21 @ Only on < r2p1 (Cortex A8)
orrlt r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_l2aux_ctrl
pop {r1-r5} @ Restore the cpu info - fall through
#endif
#ifdef CONFIG_ARM_ERRATA_852421
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 24 @ set bit #24
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_852423
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 12 @ set bit #12
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
mov pc, r5 @ back to my caller
ENDPROC(cpu_init_cp15)
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
/*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************/
ENTRY(cpu_init_crit)
/*
* Jump to board specific initialization...
* The Mask ROM will have already initialized
* basic memory. Go here to bump up clock rate and handle
* wake up conditions.
*/
b lowlevel_init @ go setup pll,mux,memory
ENDPROC(cpu_init_crit)
#endif
|
genetel200/u-boot
| 1,501
|
arch/arm/cpu/armv7/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* A lowlevel_init function that sets up the stack to call a C function to
* perform further init.
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
.pushsection .text.s_init, "ax"
WEAK(s_init)
bx lr
ENDPROC(s_init)
.popsection
.pushsection .text.lowlevel_init, "ax"
WEAK(lowlevel_init)
/*
* Setup a temporary stack. Global data is not available yet.
*/
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =CONFIG_SPL_STACK
#else
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
#endif
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#ifdef CONFIG_SPL_DM
mov r9, #0
#else
/*
* Set up global data for boards that still need it. This will be
* removed soon.
*/
#ifdef CONFIG_SPL_BUILD
ldr r9, =gdata
#else
sub sp, sp, #GD_SIZE
bic sp, sp, #7
mov r9, sp
#endif
#endif
/*
* Save the old lr(passed in ip) and the current lr to stack
*/
push {ip, lr}
/*
* Call the very early init function. This should do only the
* absolute bare minimum to get started. It should not:
*
* - set up DRAM
* - use global_data
* - clear BSS
* - try to start a console
*
* For boards with SPL this should be empty since SPL can do all of
* this init in the SPL board_init_f() function which is called
* immediately after this.
*/
bl s_init
pop {ip, pc}
ENDPROC(lowlevel_init)
.popsection
|
genetel200/u-boot
| 5,149
|
arch/arm/cpu/armv7/cache_v7_asm.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
#include <config.h>
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
#define ARM(x...)
#define THUMB(x...) x
#else
#define ARM(x...) x
#define THUMB(x...)
#endif
/*
* v7_flush_dcache_all()
*
* Flush the whole D-cache.
*
* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
*
* Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
*/
ENTRY(__v7_flush_dcache_all)
dmb @ ensure ordering with previous memory accesses
mrc p15, 1, r0, c0, c0, 1 @ read clidr
mov r3, r0, lsr #23 @ move LoC into position
ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
beq finished @ if loc is 0, then no need to clean
start_flush_levels:
mov r10, #0 @ start clean at cache level 0
flush_levels:
add r2, r10, r10, lsr #1 @ work out 3x current cache level
mov r1, r0, lsr r2 @ extract cache type bits from clidr
and r1, r1, #7 @ mask of the bits for current cache only
cmp r1, #2 @ see what cache we have at this level
blt skip @ skip if no cache, or just i-cache
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
isb @ isb to sych the new cssr&csidr
mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
and r2, r1, #7 @ extract the length of the cache lines
add r2, r2, #4 @ add 4 (line length offset)
movw r4, #0x3ff
ands r4, r4, r1, lsr #3 @ find maximum number on the way size
clz r5, r4 @ find bit position of way size increment
movw r7, #0x7fff
ands r7, r7, r1, lsr #13 @ extract max number of the index size
loop1:
mov r9, r7 @ create working copy of max index
loop2:
ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
THUMB( lsl r6, r4, r5 )
THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
THUMB( lsl r6, r9, r2 )
THUMB( orr r11, r11, r6 ) @ factor index number into r11
mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
subs r9, r9, #1 @ decrement the index
bge loop2
subs r4, r4, #1 @ decrement the way
bge loop1
skip:
add r10, r10, #2 @ increment cache number
cmp r3, r10
bgt flush_levels
finished:
mov r10, #0 @ swith back to cache level 0
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
dsb st
isb
bx lr
ENDPROC(__v7_flush_dcache_all)
ENTRY(v7_flush_dcache_all)
ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
bl __v7_flush_dcache_all
ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
bx lr
ENDPROC(v7_flush_dcache_all)
/*
* v7_invalidate_dcache_all()
*
* Invalidate the whole D-cache.
*
* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
*
* Note: copied from __v7_flush_dcache_all above with
* mcr p15, 0, r11, c7, c14, 2
* Replaced with:
* mcr p15, 0, r11, c7, c6, 2
*/
ENTRY(__v7_invalidate_dcache_all)
dmb @ ensure ordering with previous memory accesses
mrc p15, 1, r0, c0, c0, 1 @ read clidr
mov r3, r0, lsr #23 @ move LoC into position
ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
beq inval_finished @ if loc is 0, then no need to clean
mov r10, #0 @ start clean at cache level 0
inval_levels:
add r2, r10, r10, lsr #1 @ work out 3x current cache level
mov r1, r0, lsr r2 @ extract cache type bits from clidr
and r1, r1, #7 @ mask of the bits for current cache only
cmp r1, #2 @ see what cache we have at this level
blt inval_skip @ skip if no cache, or just i-cache
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
isb @ isb to sych the new cssr&csidr
mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
and r2, r1, #7 @ extract the length of the cache lines
add r2, r2, #4 @ add 4 (line length offset)
movw r4, #0x3ff
ands r4, r4, r1, lsr #3 @ find maximum number on the way size
clz r5, r4 @ find bit position of way size increment
movw r7, #0x7fff
ands r7, r7, r1, lsr #13 @ extract max number of the index size
inval_loop1:
mov r9, r7 @ create working copy of max index
inval_loop2:
ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
THUMB( lsl r6, r4, r5 )
THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
THUMB( lsl r6, r9, r2 )
THUMB( orr r11, r11, r6 ) @ factor index number into r11
mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
subs r9, r9, #1 @ decrement the index
bge inval_loop2
subs r4, r4, #1 @ decrement the way
bge inval_loop1
inval_skip:
add r10, r10, #2 @ increment cache number
cmp r3, r10
bgt inval_levels
inval_finished:
mov r10, #0 @ swith back to cache level 0
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
dsb st
isb
bx lr
ENDPROC(__v7_invalidate_dcache_all)
ENTRY(v7_invalidate_dcache_all)
ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
bl __v7_invalidate_dcache_all
ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
bx lr
ENDPROC(v7_invalidate_dcache_all)
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