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georgevio/IoT-Embedded
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esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_s16_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_61, 458755
# Program Unit: dspi_dotprod_off_s16_aes3
.type dspi_dotprod_off_s16_aes3, @function
.align 4
.global dspi_dotprod_off_s16_aes3
dspi_dotprod_off_s16_aes3: # 0x4
.LBB1_dspi_dotprod_off_s16_aes3: # 0x4
entry a1,128 #
l32i.n a10,a2,4 # [0] id:760
l32i.n a12,a2,12 # [1] id:759
mull a8,a10,a5 # [2]
blt a12,a8,.LBB83_dspi_dotprod_off_s16_aes3 # [4]
l32i.n a13,a2,8 # [0] id:761
l32i.n a9,a2,16 # [1] id:762
mull a11,a13,a6 # [2]
blt a9,a11,.LBB83_dspi_dotprod_off_s16_aes3 # [4]
l32i.n a15,a3,4 # [0] id:764
l32i.n a14,a3,12 # [1] id:763
mull a11,a15,a5 # [2]
blt a14,a11,.LBB83_dspi_dotprod_off_s16_aes3 # [4]
l32i.n a8,a3,16 # [0] id:766
l32i.n a9,a3,8 # [1] id:765
s32i a9,a1,88 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB83_dspi_dotprod_off_s16_aes3 # [5]
l32i.n a8,a3,0 # [0] id:767
s32i a8,a1,84 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_36354 # [2]
bne a14,a11,.Lt_0_36354 # [0]
bnei a15,1,.Lt_0_36354 # [0]
l32i a9,a1,88 # [0] gra_spill_temp_2
beqi a9,1,.Lt_0_19458 # [2]
.Lt_0_36354: # 0x46
.Lt_0_19714: # 0x46
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16si a8,a1,128 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:875
.type dspi_dotprod_off_s16_ansi, @function
call8 dspi_dotprod_off_s16_ansi # [8] dspi_dotprod_off_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB83_dspi_dotprod_off_s16_aes3: # 0x5e
l32r a2,.LC0_1_61 # [0]
retw.n # [1]
.Lt_0_19458: # 0x63
addi.n a9,a10,-1 # [0]
bnez a9,.Lt_0_37122 # [1]
addi.n a10,a13,-1 # [0]
bnez a10,.Lt_0_37122 # [1]
extui a11,a5,0,3 # [0]
bnez.n a11,.Lt_0_37122 # [1]
blti a6,4,.Lt_0_37122 # [0]
movi.n a14,32 # [0]
blt a14,a5,.LBB27_dspi_dotprod_off_s16_aes3 # [1]
.Lt_0_37634: # 0x7a
.Lt_0_21506: # 0x7a
l32i a15,a1,84 # [0] gra_spill_temp_1
l32i.n a2,a2,0 # [1] id:769
l16si a9,a1,128 # [2] id:768 offset+0x0
mull a10,a12,a13 # [3]
addi a8,a1,16 # [4] temp_offset
slli a10,a10,1 # [5]
s32i a10,a1,80 # [6] gra_spill_temp_0
movi.n a10,2 # [7]
# loop-count fixed at 2
loop a10,.LBB137_dspi_dotprod_off_s16_aes3 # [8]
.LBB132_dspi_dotprod_off_s16_aes3: # 0x93
s16i a9,a8,0 # [0*II+0] id:770 temp_offset+0x0
s16i a9,a8,2 # [0*II+1] id:770 temp_offset+0x0
s16i a9,a8,4 # [0*II+2] id:770 temp_offset+0x0
s16i a9,a8,6 # [0*II+3] id:770 temp_offset+0x0
s16i a9,a8,8 # [0*II+4] id:770 temp_offset+0x0
s16i a9,a8,10 # [0*II+5] id:770 temp_offset+0x0
s16i a9,a8,12 # [0*II+6] id:770 temp_offset+0x0
s16i a9,a8,14 # [0*II+7] id:770 temp_offset+0x0
addi a8,a8,16 # [0*II+8]
.LBB137_dspi_dotprod_off_s16_aes3: # 0xae
mov.n a3,a6 # [0]
addi a11,a5,-24 # [1]
addi a12,a1,24 # [3] temp_offset+8
movi.n a13,0 # [4]
wur.sar_byte a13 # [5]
wur.accx_0 a13 # [6]
wur.accx_1 a13 # [7]
ee.vld.128.ip q6,a12,0 # [8] id:771
s32i.n a12,a1,48 # [9] offset_data_ptr
beqz a11,.LBB34_dspi_dotprod_off_s16_aes3 # [10]
.Lt_0_25602: # 0xc8
.Lt_0_25090: # 0xc8
ee.vld.128.ip q0,a15,16 # [0] id:786
addi a14,a5,-16 # [1]
beqz a14,.LBB40_dspi_dotprod_off_s16_aes3 # [2]
.Lt_0_27138: # 0xd1
.Lt_0_26626: # 0xd1
addi a8,a5,-8 # [0]
beqz a8,.LBB46_dspi_dotprod_off_s16_aes3 # [1]
.Lt_0_28674: # 0xd7
.Lt_0_28162: # 0xd7
addi a9,a5,-32 # [0]
beqz a9,.LBB52_dspi_dotprod_off_s16_aes3 # [1]
.Lt_0_30210: # 0xdd
.Lt_0_29698: # 0xdd
addi a10,a5,-64 # [0]
beqz a10,.LBB58_dspi_dotprod_off_s16_aes3 # [1]
movi.n a11,64 # [0]
bge a11,a5,.Lt_0_33026 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a2,16 # [1] id:848
ee.ld.128.usar.ip q2,a2,16 # [2] id:849
ee.src.q.ld.ip q3,a2,16,q1,q2 # [4] id:850
beqz.n a3,.Lt_0_33026 # [5]
slli a8,a5,1 # [0]
l32i a14,a1,80 # [1] gra_spill_temp_0
addi a13,a5,31 # [2]
movgez a13,a5,a5 # [3]
srai a13,a13,5 # [4]
sub a14,a14,a8 # [5]
addi a14,a14,16 # [6]
addi.n a13,a13,-1 # [7]
.Lt_0_33794: # 0x10c
beqz.n a13,.Lt_0_34050 # [0]
loopnez a13,.LBB273_dspi_dotprod_off_s16_aes3 # [0]
.LBB271_dspi_dotprod_off_s16_aes3: # 0x111
ee.vmulas.s16.accx.ld.ip.qup q0,a2,16,q0,q1,q2,q3 # [0*II+0] id:851
ee.vmulas.s16.accx.ld.ip q1,a15,16,q1,q6 # [0*II+1] id:852
ee.vmulas.s16.accx.ld.ip.qup q1,a2,16,q1,q2,q3,q0 # [0*II+3] id:853
ee.vmulas.s16.accx.ld.ip q4,a15,16,q2,q6 # [0*II+4] id:854
ee.vmulas.s16.accx.ld.ip.qup q2,a2,16,q4,q3,q0,q1 # [0*II+6] id:855
ee.vmulas.s16.accx.ld.ip q4,a15,16,q3,q6 # [0*II+7] id:856
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q4,q0,q1,q2 # [0*II+9] id:857
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [0*II+10] id:858
.LBB273_dspi_dotprod_off_s16_aes3: # 0x131
.Lt_0_34050: # 0x131
ee.vmulas.s16.accx.ld.ip.qup q0,a2,16,q0,q1,q2,q3 # [0] id:859
ee.vmulas.s16.accx.ld.ip q1,a15,16,q1,q6 # [1] id:860
movi.n a9,32 # [2]
ee.vmulas.s16.accx.ld.xp.qup q7,a2,a14,q1,q2,q3,q0 # [3] id:861
ee.vmulas.s16.accx.ld.ip q5,a15,16,q2,q6 # [4] id:862
movi.n a10,-16 # [5]
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a10,q5,q3,q0,q7 # [6] id:863
ee.vmulas.s16.accx.ld.ip q4,a15,16,q3,q6 # [7] id:865
ee.ld.128.usar.xp q1,a2,a9 # [8] id:864
addi.n a12,a12,1 # [9]
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q4,q0,q1,q2 # [10] id:866
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [11] id:867
bne a12,a3,.Lt_0_33794 # [12]
.Lt_0_33026: # 0x15d
.Lt_0_32770: # 0x15d
rur.accx_0 a9 # [0]
rur.accx_1 a10 # [1]
blti a7,1,.Lt_0_35586 # [2]
movi.n a2,0 # [0]
addi a13,a7,-33 # [1]
addi.n a14,a7,-1 # [2]
ssr a14 # [3]
sra a12,a10 # [4]
src a11,a10,a9 # [5]
movgez a11,a12,a13 # [6]
addi.n a11,a11,1 # [7]
srai a11,a11,1 # [8]
s16i a11,a4,0 # [9] id:873
retw.n # [10]
.Lt_0_37122: # 0x183
.Lt_0_20738: # 0x183
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16si a8,a1,128 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:876
call8 dspi_dotprod_off_s16_ansi # [8] dspi_dotprod_off_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB27_dspi_dotprod_off_s16_aes3: # 0x19b
extui a9,a5,0,1 # [0]
beqz a9,.Lt_0_37634 # [1]
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16si a8,a1,128 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:877
call8 dspi_dotprod_off_s16_ansi # [8] dspi_dotprod_off_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB34_dspi_dotprod_off_s16_aes3: # 0x1b9
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i a12,a1,80 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q0,a2,16 # [3] id:776
ee.ld.128.usar.ip q2,a2,16 # [4] id:777
addi a12,a12,-32 # [5]
ee.src.q.ld.ip q3,a2,16,q0,q2 # [6] id:778
loopgtz a6,.LBB159_dspi_dotprod_off_s16_aes3 # [7]
.LBB157_dspi_dotprod_off_s16_aes3: # 0x1cf
ee.vmulas.s16.accx.ld.ip q1,a15,16,q0,q6 # [0*II+0] id:779
ee.vmulas.s16.accx.ld.xp.qup q1,a2,a12,q1,q0,q2,q3 # [0*II+2] id:780
ee.vmulas.s16.accx.ld.ip q0,a15,16,q2,q6 # [0*II+3] id:781
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q0,q2,q3,q1 # [0*II+5] id:782
ee.vmulas.s16.accx.ld.ip q1,a15,16,q3,q6 # [0*II+6] id:784
ee.ld.128.usar.xp q0,a2,a10 # [0*II+7] id:783
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q1,q3,q0,q2 # [0*II+9] id:785
.LBB159_dspi_dotprod_off_s16_aes3: # 0x1ea
j .Lt_0_25602 # [0]
.LBB40_dspi_dotprod_off_s16_aes3: # 0x1ed
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
srli a3,a6,1 # [2]
l32i a12,a1,80 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:787
ee.ld.128.usar.ip q2,a2,16 # [5] id:788
addi a12,a12,-16 # [7]
ee.src.q.ld.xp q3,a2,a12,q1,q2 # [8] id:789
loopnez a3,.LBB182_dspi_dotprod_off_s16_aes3 # [9]
.LBB180_dspi_dotprod_off_s16_aes3: # 0x206
ee.vmulas.s16.accx.ld.xp.qup q0,a2,a11,q0,q1,q2,q3 # [0*II+0] id:790
ee.vmulas.s16.accx.ld.ip q3,a15,16,q1,q6 # [0*II+1] id:791
ee.ld.128.usar.xp q1,a2,a10 # [0*II+2] id:792
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a12,q3,q2,q1,q0 # [0*II+4] id:793
ee.vmulas.s16.accx.ld.ip q4,a15,16,q2,q6 # [0*II+5] id:794
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q4,q1,q0,q3 # [0*II+7] id:795
ee.vmulas.s16.accx.ld.ip q3,a15,16,q1,q6 # [0*II+8] id:796
ee.ld.128.usar.xp q1,a2,a10 # [0*II+9] id:797
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a12,q3,q0,q1,q2 # [0*II+11] id:798
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [0*II+12] id:799
.LBB182_dspi_dotprod_off_s16_aes3: # 0x22c
j .Lt_0_27138 # [0]
.LBB46_dspi_dotprod_off_s16_aes3: # 0x22f
movi.n a10,-16 # [0]
l32i a11,a1,80 # [1] gra_spill_temp_0
addi a8,a2,16 # [2]
addi a11,a11,16 # [3]
ee.ld.128.usar.xp q2,a8,a10 # [4] id:800
ee.ld.128.usar.xp q1,a8,a11 # [5] id:801
ee.src.q.ld.xp q3,a8,a10,q1,q2 # [7] id:802
ee.ld.128.usar.xp q2,a8,a11 # [8] id:803
srli a3,a3,2 # [9]
mov.n a2,a8 # [10]
loopnez a3,.LBB205_dspi_dotprod_off_s16_aes3 # [11]
.LBB203_dspi_dotprod_off_s16_aes3: # 0x24e
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a10,q0,q1,q2,q3 # [0*II+0] id:804
ee.vmulas.s16.accx.ld.ip q0,a15,16,q1,q6 # [0*II+1] id:805
ee.ld.128.usar.xp q1,a2,a11 # [0*II+2] id:806
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a10,q0,q2,q1,q3 # [0*II+4] id:807
ee.vmulas.s16.accx.ld.ip q0,a15,16,q2,q6 # [0*II+5] id:808
ee.ld.128.usar.xp q4,a2,a11 # [0*II+6] id:809
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a10,q0,q1,q4,q3 # [0*II+8] id:810
ee.vmulas.s16.accx.ld.ip q0,a15,16,q1,q6 # [0*II+9] id:811
ee.ld.128.usar.xp q1,a2,a11 # [0*II+10] id:812
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a10,q0,q4,q1,q3 # [0*II+12] id:813
ee.vmulas.s16.accx.ld.ip q0,a15,16,q4,q6 # [0*II+13] id:814
ee.ld.128.usar.xp q2,a2,a11 # [0*II+14] id:815
.LBB205_dspi_dotprod_off_s16_aes3: # 0x27a
j .Lt_0_28674 # [0]
.LBB52_dspi_dotprod_off_s16_aes3: # 0x27d
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i a12,a1,80 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:816
ee.ld.128.usar.ip q2,a2,16 # [5] id:817
sub a12,a12,a13 # [6]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [8] id:818
addi a12,a12,16 # [9]
loopnez a3,.LBB228_dspi_dotprod_off_s16_aes3 # [10]
.LBB226_dspi_dotprod_off_s16_aes3: # 0x299
ee.vmulas.s16.accx.ld.ip.qup q0,a2,16,q0,q1,q2,q3 # [0*II+0] id:819
ee.vmulas.s16.accx.ld.ip q4,a15,16,q1,q6 # [0*II+1] id:820
ee.vmulas.s16.accx.ld.xp.qup q4,a2,a12,q4,q2,q3,q0 # [0*II+3] id:821
ee.vmulas.s16.accx.ld.ip q1,a15,16,q2,q6 # [0*II+4] id:822
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q1,q3,q0,q4 # [0*II+6] id:823
ee.vmulas.s16.accx.ld.ip q4,a15,16,q3,q6 # [0*II+7] id:825
ee.ld.128.usar.xp q1,a2,a10 # [0*II+8] id:824
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q4,q0,q1,q2 # [0*II+10] id:826
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [0*II+11] id:827
.LBB228_dspi_dotprod_off_s16_aes3: # 0x2bc
j .Lt_0_30210 # [0]
.LBB58_dspi_dotprod_off_s16_aes3: # 0x2bf
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i a12,a1,80 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:828
ee.ld.128.usar.ip q2,a2,16 # [5] id:829
sub a12,a12,a13 # [7]
addi a12,a12,16 # [8]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [9] id:830
mov.n a8,a2 # [10]
loopnez a3,.LBB250_dspi_dotprod_off_s16_aes3 # [11]
.LBB248_dspi_dotprod_off_s16_aes3: # 0x2dd
ee.vmulas.s16.accx.ld.ip.qup q0,a8,16,q0,q1,q2,q3 # [0*II+0] id:831
ee.vmulas.s16.accx.ld.ip q4,a15,16,q1,q6 # [0*II+1] id:832
ee.vmulas.s16.accx.ld.ip.qup q4,a8,16,q4,q2,q3,q0 # [0*II+3] id:833
ee.vmulas.s16.accx.ld.ip q1,a15,16,q2,q6 # [0*II+4] id:834
ee.vmulas.s16.accx.ld.ip.qup q1,a8,16,q1,q3,q0,q4 # [0*II+6] id:835
ee.vmulas.s16.accx.ld.ip q5,a15,16,q3,q6 # [0*II+7] id:836
ee.vmulas.s16.accx.ld.ip.qup q5,a8,16,q5,q0,q4,q1 # [0*II+9] id:837
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [0*II+10] id:838
ee.vmulas.s16.accx.ld.ip.qup q0,a8,16,q0,q4,q1,q5 # [0*II+12] id:839
ee.vmulas.s16.accx.ld.ip q4,a15,16,q4,q6 # [0*II+13] id:840
ee.vmulas.s16.accx.ld.xp.qup q4,a8,a12,q4,q1,q5,q0 # [0*II+15] id:841
ee.vmulas.s16.accx.ld.ip q1,a15,16,q1,q6 # [0*II+16] id:842
ee.vmulas.s16.accx.ld.xp.qup q2,a8,a11,q1,q5,q0,q4 # [0*II+18] id:843
ee.vmulas.s16.accx.ld.ip q4,a15,16,q5,q6 # [0*II+19] id:845
ee.ld.128.usar.xp q1,a8,a10 # [0*II+20] id:844
ee.vmulas.s16.accx.ld.ip.qup q3,a8,16,q4,q0,q1,q2 # [0*II+22] id:846
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [0*II+23] id:847
.LBB250_dspi_dotprod_off_s16_aes3: # 0x320
j .Lt_0_33026 # [0]
.Lt_0_35586: # 0x323
movi.n a2,0 # [0]
sext a14,a9,15 # [1]
s16i a14,a4,0 # [2] id:874
retw.n # [3]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,626
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_u8_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_u8_arp4
.global dspi_dotprod_u8_ansi
.type dspi_dotprod_u8_arp4,@function
// esp_err_t dspi_dotprod_u8_arp4(image2d_t *in_image, image2d_t *filter, uint8_t *out_value, int count_x, int count_y, int shift);
dspi_dotprod_u8_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 15
or t1, t1, t2
beqz t1, .dspi_dotprod_u8_arp4_body
j dspi_dotprod_u8_ansi
.dspi_dotprod_u8_arp4_body:
add sp, sp, -16
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
srli t6, a3, 4 // t5 = len/16
addi a6, a5, -1
li t4, 1
sll t4, t4, a6
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q0, t4, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q1, t5, 16 // q1 - f_data
.loop_count_x: esp.vmulas.u8.xacc.ld.ip q0, t4, 16, q0, q1 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.u.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 2,851
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_s8_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_off_s8_arp4
.global dspi_dotprod_off_s8_ansi
.type dspi_dotprod_off_s8_arp4,@function
// esp_err_t dspi_dotprod_off_s8_arp4(image2d_t *in_image, image2d_t *filter, int16_t *out_value, int count_x, int count_y, int shift, int8_t offset);
dspi_dotprod_off_s8_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// offset - a6
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 15
or t1, t1, t2
beqz t1, .dspi_dotprod_off_s8_arp4_body
j dspi_dotprod_off_s8_ansi
.dspi_dotprod_off_s8_arp4_body:
add sp, sp, -16
sw a6, 0(sp)
mv t6, sp
esp.vldbc.8.ip q2, t6, 0
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
srli t6, a3, 4 // t5 = len/16
addi a7, a5, -1
li t4, 1
sll t4, t4, a7
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q1, t5, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q0, t4, 16 // q1 - f_data
esp.vadd.s8 q3, q2, q1
.loop_count_x: esp.vmulas.s8.xacc.ld.ip q1, t5, 16, q0, q3 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.s.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 2,713
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_s16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_s16_arp4
.global dspi_dotprod_s16_ansi
.type dspi_dotprod_s16_arp4,@function
// esp_err_t dspi_dotprod_s16_arp4(image2d_t *in_image, image2d_t *filter, int16_t *out_value, int count_x, int count_y, int shift);
dspi_dotprod_s16_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 7
or t1, t1, t2
beqz t1, .dspi_dotprod_s16_arp4_body
j dspi_dotprod_s16_ansi
.dspi_dotprod_s16_arp4_body:
add sp, sp, -16
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
slli t2, t2, 1 // i_step = i_step<<1
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
slli t3, t3, 1 // f_step = f_step<<1
srli t6, a3, 3 // t5 = len/8
addi a6, a5, -1
li t4, 1
sll t4, t4, a6
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q0, t4, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q1, t5, 16 // q1 - f_data
.loop_count_x: esp.vmulas.s16.xacc.ld.ip q0, t4, 16, q0, q1 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.s.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 1,893
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dsps_dotprod_s16_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dsps_dotprod_s16_ae32_enabled == 1)
#include "dsps_dotprod_s16_m_ae32.S"
#include "dsp_err_codes.h"
.text
.align 4
.global dsps_dotprod_s16_ae32
.type dsps_dotprod_s16_ae32,@function
//esp_err_t dsps_dotprod_s16_ae32(const int16_t* src1, const int16_t* src2, int16_t* dest, int len, int8_t shift);
dsps_dotprod_s16_ae32:
// src1 - a2
// src2 - a3
// dest - a4
// len - a5
// shift - a6
entry a1, 16
// Check minimum length
movi a8, 4
blt a5, a8, dsps_dotprod_s16_ae32_error
// Clear accumulator
movi a8, 0
wsr a8, acchi
// Prepare and load round value
movi a8, 0x7fff
ssr a6
srl a8, a8
wsr a8, acclo // initialize acc with shifted round value
// Compensate for pre-increment
// Right shift to 16 bits
// RS = -shift + 15
neg a6, a6
addi a6, a6, 15
/* number of loop iterations (see below):
* a7 = count / 4 - 1
*/
srli a7, a5, 2
addi a7, a7, -1
movi.n a10, 0 // load 0 to the a10 to increment second array
dotprod_s16_ae32_full a2, a3, a7, a5
/* Get accumulator */
ssr a6
rsr a2, acchi
rsr a3, acclo
src a2, a2, a3
s16i a2, a4, 0
movi.n a2, 0
retw.n
dsps_dotprod_s16_ae32_error:
movi.n a2, ESP_ERR_DSP_INVALID_LENGTH
retw.n
#endif // dsps_dotprod_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 14,668
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_u16_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_55, 458755
# Program Unit: dspi_dotprod_u16_aes3
.type dspi_dotprod_u16_aes3, @function
.align 4
.global dspi_dotprod_u16_aes3
dspi_dotprod_u16_aes3: # 0x4
.LBB1_dspi_dotprod_u16_aes3: # 0x4
entry a1,64 #
l32i.n a10,a2,4 # [0] id:681
l32i.n a11,a2,12 # [1] id:680
mull a8,a10,a5 # [2]
blt a11,a8,.LBB81_dspi_dotprod_u16_aes3 # [4]
l32i.n a12,a2,8 # [0] id:682
l32i.n a9,a2,16 # [1] id:683
mull a13,a12,a6 # [2]
blt a9,a13,.LBB81_dspi_dotprod_u16_aes3 # [4]
l32i.n a15,a3,4 # [0] id:685
l32i.n a14,a3,12 # [1] id:684
mull a13,a15,a5 # [2]
blt a14,a13,.LBB81_dspi_dotprod_u16_aes3 # [4]
l32i.n a8,a3,16 # [0] id:687
l32i.n a9,a3,8 # [1] id:686
s32i.n a9,a1,24 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB81_dspi_dotprod_u16_aes3 # [5]
l32i.n a8,a3,0 # [0] id:688
s32i.n a8,a1,20 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_34050 # [2]
bne a14,a13,.Lt_0_34050 # [0]
bnei a15,1,.Lt_0_34050 # [0]
l32i.n a9,a1,24 # [0] gra_spill_temp_2
beqi a9,1,.Lt_0_18178 # [2]
.Lt_0_34050: # 0x43
.Lt_0_18434: # 0x43
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
.type dspi_dotprod_s16_ansi, @function
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB81_dspi_dotprod_u16_aes3: # 0x56
l32r a2,.LC0_1_55 # [0]
retw.n # [1]
.Lt_0_18178: # 0x5b
addi.n a13,a10,-1 # [0]
bnez a13,.Lt_0_34818 # [1]
addi.n a14,a12,-1 # [0]
bnez a14,.Lt_0_34818 # [1]
extui a15,a5,0,3 # [0]
bnez.n a15,.Lt_0_34818 # [1]
blti a6,4,.Lt_0_34818 # [0]
movi.n a8,32 # [0]
bge a8,a5,.Lt_0_35330 # [1]
extui a9,a5,0,1 # [0]
bnez a9,.LBB28_dspi_dotprod_u16_aes3 # [1]
.Lt_0_35330: # 0x78
.Lt_0_20226: # 0x78
mov.n a3,a6 # [0]
addi a10,a5,-24 # [1]
mull a13,a11,a12 # [2]
l32i.n a15,a1,20 # [3] gra_spill_temp_1
l32i.n a2,a2,0 # [4] id:689
movi.n a14,0 # [5]
wur.sar_byte a14 # [6]
wur.accx_0 a14 # [8]
wur.accx_1 a14 # [9]
ee.vld.128.ip q0,a15,16 # [10] id:693
slli a13,a13,1 # [11]
s32i.n a13,a1,16 # [12] gra_spill_temp_0
beqz a10,.LBB32_dspi_dotprod_u16_aes3 # [13]
.Lt_0_23298: # 0x99
.Lt_0_22786: # 0x99
addi a8,a5,-16 # [0]
beqz a8,.LBB38_dspi_dotprod_u16_aes3 # [1]
.Lt_0_24834: # 0x9f
.Lt_0_24322: # 0x9f
addi a9,a5,-8 # [0]
beqz a9,.LBB44_dspi_dotprod_u16_aes3 # [1]
.Lt_0_26370: # 0xa5
.Lt_0_25858: # 0xa5
addi a10,a5,-32 # [0]
beqz a10,.LBB50_dspi_dotprod_u16_aes3 # [1]
.Lt_0_27906: # 0xab
.Lt_0_27394: # 0xab
addi a11,a5,-64 # [0]
beqz a11,.LBB56_dspi_dotprod_u16_aes3 # [1]
movi.n a12,64 # [0]
bge a12,a5,.Lt_0_30722 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a2,16 # [1] id:765
ee.ld.128.usar.ip q2,a2,16 # [2] id:766
ee.src.q.ld.ip q3,a2,16,q1,q2 # [4] id:767
beqz.n a3,.Lt_0_30722 # [5]
slli a8,a5,1 # [0]
l32i.n a14,a1,16 # [1] gra_spill_temp_0
addi a13,a5,31 # [2]
movgez a13,a5,a5 # [3]
srai a13,a13,5 # [4]
sub a14,a14,a8 # [5]
addi a14,a14,16 # [6]
addi.n a13,a13,-1 # [7]
.Lt_0_31490: # 0xd9
addi.n a12,a12,1 # [0]
movi.n a9,32 # [1]
beqz.n a13,.Lt_0_31746 # [2]
loopnez a13,.LBB221_dspi_dotprod_u16_aes3 # [0]
.LBB219_dspi_dotprod_u16_aes3: # 0xe2
ee.vld.128.ip q5,a15,16 # [0*II+0] id:769
ee.vmulas.u16.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:768
ee.vld.128.ip q0,a15,16 # [0*II+2] id:771
ee.vmulas.u16.accx.ld.ip.qup q1,a2,16,q5,q2,q3,q4 # [0*II+3] id:770
ee.vld.128.ip q5,a15,16 # [0*II+4] id:773
ee.vmulas.u16.accx.ld.ip.qup q2,a2,16,q0,q3,q4,q1 # [0*II+5] id:772
ee.vld.128.ip q0,a15,16 # [0*II+6] id:775
ee.vmulas.u16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+7] id:774
.LBB221_dspi_dotprod_u16_aes3: # 0xfe
.Lt_0_31746: # 0xfe
ee.vmulas.u16.accx.ld.ip.qup q5,a2,16,q0,q1,q2,q3 # [0] id:776
movi.n a10,-16 # [1]
ee.vld.128.ip q0,a15,16 # [2] id:777
ee.vld.128.ip q6,a15,16 # [3] id:779
ee.vmulas.u16.accx.ld.xp.qup q7,a2,a14,q0,q2,q3,q5 # [4] id:778
ee.vld.128.ip q4,a15,16 # [5] id:782
ee.vmulas.u16.accx.ld.xp.qup q2,a2,a10,q6,q3,q5,q7 # [6] id:780
ee.ld.128.usar.xp q1,a2,a9 # [7] id:781
ee.vld.128.ip q0,a15,16 # [8] id:784
ee.vmulas.u16.accx.ld.ip.qup q3,a2,16,q4,q5,q1,q2 # [9] id:783
bne a12,a3,.Lt_0_31490 # [10]
.Lt_0_30722: # 0x122
.Lt_0_30466: # 0x122
rur.accx_0 a9 # [0]
rur.accx_1 a10 # [1]
blti a7,1,.Lt_0_33282 # [2]
movi.n a2,0 # [0]
addi a13,a7,-33 # [1]
addi.n a14,a7,-1 # [2]
ssr a14 # [3]
sra a12,a10 # [4]
src a11,a10,a9 # [5]
movgez a11,a12,a13 # [6]
addi.n a11,a11,1 # [7]
srli a11,a11,1 # [8]
s16i a11,a4,0 # [9] id:790
retw.n # [10]
.Lt_0_34818: # 0x148
.Lt_0_19458: # 0x148
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB32_dspi_dotprod_u16_aes3: # 0x15b
ee.ld.128.usar.ip q1,a2,16 # [0] id:694
ee.ld.128.usar.ip q2,a2,16 # [1] id:695
ee.src.q.ld.ip q3,a2,16,q1,q2 # [3] id:696
beqz.n a6,.Lt_0_23298 # [4]
addi a12,a13,-32 # [0]
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
loopgtz a6,.LBB107_dspi_dotprod_u16_aes3 # [3]
.LBB105_dspi_dotprod_u16_aes3: # 0x170
ee.vld.128.ip q4,a15,16 # [0*II+0] id:698
ee.vmulas.u16.accx.ld.xp.qup q1,a2,a12,q0,q1,q2,q3 # [0*II+1] id:697
ee.vld.128.ip q5,a15,16 # [0*II+2] id:700
ee.vmulas.u16.accx.ld.xp.qup q2,a2,a11,q4,q2,q3,q1 # [0*II+3] id:699
ee.ld.128.usar.xp q1,a2,a10 # [0*II+4] id:701
ee.vld.128.ip q0,a15,16 # [0*II+5] id:703
ee.vmulas.u16.accx.ld.ip.qup q3,a2,16,q5,q3,q1,q2 # [0*II+6] id:702
.LBB107_dspi_dotprod_u16_aes3: # 0x188
j .Lt_0_23298 # [0]
.LBB38_dspi_dotprod_u16_aes3: # 0x18b
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
srli a3,a6,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:704
ee.ld.128.usar.ip q2,a2,16 # [5] id:705
addi a12,a12,-16 # [7]
ee.src.q.ld.xp q3,a2,a12,q1,q2 # [8] id:706
loopnez a3,.LBB130_dspi_dotprod_u16_aes3 # [9]
.LBB128_dspi_dotprod_u16_aes3: # 0x1a3
ee.vld.128.ip q4,a15,16 # [0*II+0] id:708
ee.vmulas.u16.accx.ld.xp.qup q3,a2,a11,q0,q1,q2,q3 # [0*II+1] id:707
ee.ld.128.usar.xp q1,a2,a10 # [0*II+2] id:709
ee.vld.128.ip q0,a15,16 # [0*II+3] id:711
ee.vmulas.u16.accx.ld.xp.qup q4,a2,a12,q4,q2,q1,q3 # [0*II+4] id:710
ee.vld.128.ip q5,a15,16 # [0*II+5] id:713
ee.vmulas.u16.accx.ld.xp.qup q2,a2,a11,q0,q1,q3,q4 # [0*II+6] id:712
ee.ld.128.usar.xp q1,a2,a10 # [0*II+7] id:714
ee.vld.128.ip q0,a15,16 # [0*II+8] id:716
ee.vmulas.u16.accx.ld.xp.qup q3,a2,a12,q5,q3,q1,q2 # [0*II+9] id:715
.LBB130_dspi_dotprod_u16_aes3: # 0x1c5
j .Lt_0_24834 # [0]
.LBB44_dspi_dotprod_u16_aes3: # 0x1c8
srli a3,a3,2 # [0]
movi.n a10,-16 # [1]
l32i.n a11,a1,16 # [2] gra_spill_temp_0
addi a8,a2,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a8,a10 # [5] id:717
ee.ld.128.usar.xp q1,a8,a11 # [6] id:718
ee.src.q.ld.xp q3,a8,a10,q1,q2 # [8] id:719
ee.ld.128.usar.xp q2,a8,a11 # [9] id:720
loopnez a3,.LBB153_dspi_dotprod_u16_aes3 # [10]
.LBB151_dspi_dotprod_u16_aes3: # 0x1e4
ee.vld.128.ip q4,a15,16 # [0*II+0] id:722
ee.vmulas.u16.accx.ld.xp.qup q3,a8,a10,q0,q1,q2,q3 # [0*II+1] id:721
ee.ld.128.usar.xp q1,a8,a11 # [0*II+2] id:723
ee.vld.128.ip q0,a15,16 # [0*II+3] id:725
ee.vmulas.u16.accx.ld.xp.qup q4,a8,a10,q4,q2,q1,q3 # [0*II+4] id:724
ee.ld.128.usar.xp q3,a8,a11 # [0*II+5] id:726
ee.vld.128.ip q5,a15,16 # [0*II+6] id:728
ee.vmulas.u16.accx.ld.xp.qup q4,a8,a10,q0,q1,q3,q4 # [0*II+7] id:727
ee.ld.128.usar.xp q1,a8,a11 # [0*II+8] id:729
ee.vld.128.ip q0,a15,16 # [0*II+9] id:731
ee.vmulas.u16.accx.ld.xp.qup q3,a8,a10,q5,q3,q1,q4 # [0*II+10] id:730
ee.ld.128.usar.xp q2,a8,a11 # [0*II+11] id:732
.LBB153_dspi_dotprod_u16_aes3: # 0x20c
mov.n a2,a8 # [0]
j .Lt_0_26370 # [1]
.LBB50_dspi_dotprod_u16_aes3: # 0x211
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:733
ee.ld.128.usar.ip q2,a2,16 # [5] id:734
sub a12,a12,a13 # [6]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [8] id:735
addi a12,a12,16 # [9]
loopnez a3,.LBB176_dspi_dotprod_u16_aes3 # [10]
.LBB174_dspi_dotprod_u16_aes3: # 0x22c
ee.vld.128.ip q5,a15,16 # [0*II+0] id:737
ee.vmulas.u16.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:736
ee.vld.128.ip q1,a15,16 # [0*II+2] id:739
ee.vmulas.u16.accx.ld.xp.qup q0,a2,a12,q5,q2,q3,q4 # [0*II+3] id:738
ee.vld.128.ip q5,a15,16 # [0*II+4] id:742
ee.vmulas.u16.accx.ld.xp.qup q2,a2,a11,q1,q3,q4,q0 # [0*II+5] id:740
ee.ld.128.usar.xp q1,a2,a10 # [0*II+6] id:741
ee.vld.128.ip q0,a15,16 # [0*II+7] id:744
ee.vmulas.u16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+8] id:743
.LBB176_dspi_dotprod_u16_aes3: # 0x24b
j .Lt_0_27906 # [0]
.LBB56_dspi_dotprod_u16_aes3: # 0x24e
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:745
ee.ld.128.usar.ip q2,a2,16 # [5] id:746
sub a12,a12,a13 # [7]
addi a12,a12,16 # [8]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [9] id:747
loopnez a3,.LBB198_dspi_dotprod_u16_aes3 # [10]
.LBB196_dspi_dotprod_u16_aes3: # 0x269
ee.vld.128.ip q4,a15,16 # [0*II+0] id:749
ee.vmulas.u16.accx.ld.ip.qup q1,a2,16,q0,q1,q2,q3 # [0*II+1] id:748
ee.vld.128.ip q0,a15,16 # [0*II+2] id:751
ee.vmulas.u16.accx.ld.ip.qup q4,a2,16,q4,q2,q3,q1 # [0*II+3] id:750
ee.vld.128.ip q5,a15,16 # [0*II+4] id:753
ee.vmulas.u16.accx.ld.ip.qup q0,a2,16,q0,q3,q1,q4 # [0*II+5] id:752
ee.vld.128.ip q6,a15,16 # [0*II+6] id:755
ee.vmulas.u16.accx.ld.ip.qup q1,a2,16,q5,q1,q4,q0 # [0*II+7] id:754
ee.vld.128.ip q5,a15,16 # [0*II+8] id:757
ee.vmulas.u16.accx.ld.ip.qup q4,a2,16,q6,q4,q0,q1 # [0*II+9] id:756
ee.vld.128.ip q6,a15,16 # [0*II+10] id:759
ee.vmulas.u16.accx.ld.xp.qup q0,a2,a12,q5,q0,q1,q4 # [0*II+11] id:758
ee.vld.128.ip q5,a15,16 # [0*II+12] id:762
ee.vmulas.u16.accx.ld.xp.qup q2,a2,a11,q6,q1,q4,q0 # [0*II+13] id:760
ee.ld.128.usar.xp q1,a2,a10 # [0*II+14] id:761
ee.vld.128.ip q0,a15,16 # [0*II+15] id:764
ee.vmulas.u16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+16] id:763
.LBB198_dspi_dotprod_u16_aes3: # 0x2a4
j .Lt_0_30722 # [0]
.Lt_0_33282: # 0x2a7
movi.n a2,0 # [0]
sext a14,a9,15 # [1]
s16i a14,a4,0 # [2] id:791
retw.n # [3]
.LBB28_dspi_dotprod_u16_aes3: # 0x2b1
mov.n a15,a7 # [0]
mov.n a14,a6 # [1]
mov.n a13,a5 # [2]
mov.n a12,a4 # [3]
mov.n a11,a3 # [4]
mov.n a10,a2 # [5]
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,937
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_u16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_off_u16_arp4
.global dspi_dotprod_off_u16_ansi
.type dspi_dotprod_off_u16_arp4,@function
// esp_err_t dspi_dotprod_off_u16_arp4(image2d_t *in_image, image2d_t *filter, int16_t *out_value, int count_x, int count_y, int shift, unt16_t offset);
dspi_dotprod_off_u16_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// offset - a6
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 7
or t1, t1, t2
beqz t1, .dspi_dotprod_off_u16_arp4_body
j dspi_dotprod_off_u16_ansi
.dspi_dotprod_off_u16_arp4_body:
add sp, sp, -16
sw a6, 0(sp)
mv t6, sp
esp.vldbc.16.ip q2, t6, 0
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
slli t2, t2, 1 // i_step = i_step<<1
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
slli t3, t3, 1 // f_step = f_step<<1
srli t6, a3, 3 // t5 = len/8
addi a7, a5, -1
li t4, 1
sll t4, t4, a7
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q1, t5, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q0, t4, 16 // q1 - f_data
esp.vadd.u16 q3, q2, q1
.loop_count_x: esp.vmulas.u16.xacc.ld.ip q1, t5, 16, q0, q3 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.u.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 17,082
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_s8_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_57, 458755
# Program Unit: dspi_dotprod_off_s8_aes3
.type dspi_dotprod_off_s8_aes3, @function
.align 4
.global dspi_dotprod_off_s8_aes3
dspi_dotprod_off_s8_aes3: # 0x4
.LBB1_dspi_dotprod_off_s8_aes3: # 0x4
entry a1,112 #
l32i.n a10,a2,4 # [0] id:745
l32i.n a12,a2,12 # [1] id:744
mull a8,a10,a5 # [2]
blt a12,a8,.LBB86_dspi_dotprod_off_s8_aes3 # [4]
l32i.n a13,a2,8 # [0] id:746
l32i.n a9,a2,16 # [1] id:747
mull a11,a13,a6 # [2]
blt a9,a11,.LBB86_dspi_dotprod_off_s8_aes3 # [4]
l32i.n a15,a3,4 # [0] id:749
l32i.n a14,a3,12 # [1] id:748
mull a11,a15,a5 # [2]
blt a14,a11,.LBB86_dspi_dotprod_off_s8_aes3 # [4]
l32i.n a8,a3,16 # [0] id:751
l32i.n a9,a3,8 # [1] id:750
s32i a9,a1,72 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB86_dspi_dotprod_off_s8_aes3 # [5]
l32i.n a8,a3,0 # [0] id:752
s32i a8,a1,68 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_35330 # [2]
bne a14,a11,.Lt_0_35330 # [0]
bnei a15,1,.Lt_0_35330 # [0]
l32i a11,a1,72 # [0] gra_spill_temp_2
beqi a11,1,.Lt_0_18946 # [2]
.Lt_0_35330: # 0x46
.Lt_0_19202: # 0x46
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
.type dspi_dotprod_s8_ansi, @function
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB86_dspi_dotprod_off_s8_aes3: # 0x59
l32r a2,.LC0_1_57 # [0]
retw.n # [1]
.Lt_0_18946: # 0x5e
addi.n a14,a10,-1 # [0]
bnez a14,.Lt_0_36098 # [1]
addi.n a15,a13,-1 # [0]
bnez a15,.Lt_0_36098 # [1]
extui a8,a5,0,4 # [0]
bnez.n a8,.Lt_0_36098 # [1]
blti a6,4,.Lt_0_36098 # [0]
movi.n a9,64 # [0]
blt a9,a5,.LBB27_dspi_dotprod_off_s8_aes3 # [1]
.Lt_0_36610: # 0x75
.Lt_0_20994: # 0x75
mov.n a8,a1 # [0]
l8ui a9,a1,112 # [1] id:754 offset+0x0
l32i.n a15,a2,0 # [2] id:753
mull a10,a12,a13 # [3]
l32i a2,a1,68 # [4] gra_spill_temp_1
s32i a10,a1,64 # [5] gra_spill_temp_0
sext a9,a9,7 # [6]
movi.n a10,4 # [7]
# loop-count fixed at 4
loop a10,.LBB140_dspi_dotprod_off_s8_aes3 # [8]
.LBB135_dspi_dotprod_off_s8_aes3: # 0x8d
s8i a9,a8,0 # [0*II+0] id:755 temp_offset+0x0
s8i a9,a8,1 # [0*II+1] id:755 temp_offset+0x0
s8i a9,a8,2 # [0*II+2] id:755 temp_offset+0x0
s8i a9,a8,3 # [0*II+3] id:755 temp_offset+0x0
s8i a9,a8,4 # [0*II+4] id:755 temp_offset+0x0
s8i a9,a8,5 # [0*II+5] id:755 temp_offset+0x0
s8i a9,a8,6 # [0*II+6] id:755 temp_offset+0x0
s8i a9,a8,7 # [0*II+7] id:755 temp_offset+0x0
addi.n a8,a8,8 # [0*II+8]
.LBB140_dspi_dotprod_off_s8_aes3: # 0xa7
mov.n a3,a6 # [0]
addi a11,a5,-48 # [1]
addi.n a12,a1,8 # [3] temp_offset+8
movi.n a13,0 # [4]
wur.accx_0 a13 # [5]
wur.accx_1 a13 # [6]
ee.vld.128.ip q6,a12,0 # [7] id:756
s32i.n a12,a1,32 # [8] offset_data_ptr
beqz a11,.LBB34_dspi_dotprod_off_s8_aes3 # [9]
l32i a2,a1,68 # [0] gra_spill_temp_1
ee.vld.128.ip q0,a2,16 # [2] id:771
st.qr q0,a1,48 # [3] q0
.Lt_0_24578: # 0xc6
addi a14,a5,-32 # [0]
beqz a14,.LBB43_dspi_dotprod_off_s8_aes3 # [1]
.Lt_0_26626: # 0xcc
.Lt_0_26114: # 0xcc
addi a8,a5,-16 # [0]
beqz a8,.LBB50_dspi_dotprod_off_s8_aes3 # [1]
.Lt_0_28162: # 0xd2
.Lt_0_27650: # 0xd2
addi a9,a5,-64 # [0]
beqz a9,.LBB57_dspi_dotprod_off_s8_aes3 # [1]
.Lt_0_29698: # 0xd8
.Lt_0_29186: # 0xd8
addi a10,a5,-128 # [0]
beqz a10,.LBB64_dspi_dotprod_off_s8_aes3 # [1]
movi a11,128 # [0]
bge a11,a5,.Lt_0_32514 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a15,16 # [1] id:833
ee.ld.128.usar.ip q2,a15,16 # [2] id:834
ee.src.q.ld.ip q3,a15,16,q1,q2 # [4] id:835
beqz.n a3,.Lt_0_32514 # [5]
ld.qr q0,a1,48 # [0] q0
l32i a14,a1,64 # [1] gra_spill_temp_0
addi a13,a5,31 # [2]
movgez a13,a5,a5 # [3]
srai a13,a13,5 # [4]
sub a14,a14,a5 # [5]
addi a14,a14,16 # [6]
addi.n a13,a13,-1 # [7]
.Lt_0_33282: # 0x108
beqz.n a13,.Lt_0_33538 # [0]
loopnez a13,.LBB277_dspi_dotprod_off_s8_aes3 # [0]
.LBB275_dspi_dotprod_off_s8_aes3: # 0x10d
ee.vmulas.s8.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:836
ee.vmulas.s8.accx.ld.ip q1,a2,16,q1,q6 # [0*II+1] id:837
ee.vmulas.s8.accx.ld.ip.qup q1,a15,16,q1,q2,q3,q0 # [0*II+3] id:838
ee.vmulas.s8.accx.ld.ip q4,a2,16,q2,q6 # [0*II+4] id:839
ee.vmulas.s8.accx.ld.ip.qup q2,a15,16,q4,q3,q0,q1 # [0*II+6] id:840
ee.vmulas.s8.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:841
ee.vmulas.s8.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+9] id:842
ee.vmulas.s8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:843
.LBB277_dspi_dotprod_off_s8_aes3: # 0x12d
.Lt_0_33538: # 0x12d
ee.vmulas.s8.accx.ld.ip.qup q4,a15,16,q0,q1,q2,q3 # [0] id:844
ee.vmulas.s8.accx.ld.ip q1,a2,16,q1,q6 # [1] id:845
movi.n a8,32 # [2]
ee.vmulas.s8.accx.ld.xp.qup q0,a15,a14,q1,q2,q3,q4 # [3] id:846
ee.vmulas.s8.accx.ld.ip q7,a2,16,q2,q6 # [4] id:847
movi.n a9,-16 # [5]
ee.vmulas.s8.accx.ld.xp.qup q2,a15,a9,q7,q3,q4,q0 # [6] id:848
ee.vmulas.s8.accx.ld.ip q5,a2,16,q3,q6 # [7] id:850
ee.ld.128.usar.xp q1,a15,a8 # [8] id:849
addi.n a12,a12,1 # [9]
ee.vmulas.s8.accx.ld.ip.qup q3,a15,16,q5,q4,q1,q2 # [10] id:851
ee.vmulas.s8.accx.ld.ip q0,a2,16,q4,q6 # [11] id:852
bne a12,a3,.Lt_0_33282 # [12]
.Lt_0_32514: # 0x159
.Lt_0_32258: # 0x159
movi.n a2,0 # [0]
rur.accx_0 a10 # [1]
addi.n a12,a7,-1 # [2]
movi.n a11,1 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:854
retw.n # [10]
.Lt_0_36098: # 0x175
.Lt_0_20226: # 0x175
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB27_dspi_dotprod_off_s8_aes3: # 0x188
extui a14,a5,0,1 # [0]
beqz a14,.Lt_0_36610 # [1]
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB34_dspi_dotprod_off_s8_aes3: # 0x1a1
ee.ld.128.usar.ip q0,a15,16 # [0] id:760
ee.ld.128.usar.ip q2,a15,16 # [1] id:761
ee.src.q.ld.ip q3,a15,16,q0,q2 # [3] id:762
beqz.n a6,.Lt_0_24578 # [4]
movi.n a10,32 # [0]
l32i a12,a1,64 # [1] gra_spill_temp_0
movi.n a11,-16 # [2]
addi a12,a12,-32 # [3]
loopgtz a6,.LBB163_dspi_dotprod_off_s8_aes3 # [4]
.LBB161_dspi_dotprod_off_s8_aes3: # 0x1b9
ee.vmulas.s8.accx.ld.ip q1,a2,16,q0,q6 # [0*II+0] id:763
ee.vmulas.s8.accx.ld.xp.qup q1,a15,a12,q1,q0,q2,q3 # [0*II+2] id:764
ee.vmulas.s8.accx.ld.ip q0,a2,16,q2,q6 # [0*II+3] id:765
ee.vmulas.s8.accx.ld.xp.qup q2,a15,a11,q0,q2,q3,q1 # [0*II+5] id:766
ee.vmulas.s8.accx.ld.ip q1,a2,16,q3,q6 # [0*II+6] id:768
ee.ld.128.usar.xp q0,a15,a10 # [0*II+7] id:767
ee.vmulas.s8.accx.ld.ip.qup q3,a15,16,q1,q3,q0,q2 # [0*II+9] id:769
.LBB163_dspi_dotprod_off_s8_aes3: # 0x1d4
st.qr q1,a1,48 # [0] q0
j .Lt_0_24578 # [1]
.LBB43_dspi_dotprod_off_s8_aes3: # 0x1da
srli a3,a6,1 # [0]
l32i a12,a1,64 # [1] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [2] id:772
ee.ld.128.usar.ip q2,a15,16 # [3] id:773
addi a12,a12,-16 # [5]
ee.src.q.ld.xp q3,a15,a12,q1,q2 # [6] id:774
beqz.n a3,.Lt_0_26626 # [7]
ld.qr q0,a1,48 # [0] q0
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
loopnez a3,.LBB186_dspi_dotprod_off_s8_aes3 # [3]
.LBB184_dspi_dotprod_off_s8_aes3: # 0x1f8
ee.vmulas.s8.accx.ld.xp.qup q0,a15,a11,q0,q1,q2,q3 # [0*II+0] id:775
ee.vmulas.s8.accx.ld.ip q3,a2,16,q1,q6 # [0*II+1] id:776
ee.ld.128.usar.xp q1,a15,a10 # [0*II+2] id:777
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a12,q3,q2,q1,q0 # [0*II+4] id:778
ee.vmulas.s8.accx.ld.ip q4,a2,16,q2,q6 # [0*II+5] id:779
ee.vmulas.s8.accx.ld.xp.qup q2,a15,a11,q4,q1,q0,q3 # [0*II+7] id:780
ee.vmulas.s8.accx.ld.ip q3,a2,16,q1,q6 # [0*II+8] id:781
ee.ld.128.usar.xp q1,a15,a10 # [0*II+9] id:782
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a12,q3,q0,q1,q2 # [0*II+11] id:783
ee.vmulas.s8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+12] id:784
.LBB186_dspi_dotprod_off_s8_aes3: # 0x21e
st.qr q0,a1,48 # [0] q0
j .Lt_0_26626 # [1]
.LBB50_dspi_dotprod_off_s8_aes3: # 0x224
srli a3,a3,2 # [0]
movi.n a13,-16 # [1]
l32i a11,a1,64 # [2] gra_spill_temp_0
addi a15,a15,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a15,a13 # [5] id:785
ee.ld.128.usar.xp q1,a15,a11 # [6] id:786
ee.src.q.ld.xp q3,a15,a13,q1,q2 # [8] id:787
ee.ld.128.usar.xp q2,a15,a11 # [9] id:788
beqz.n a3,.Lt_0_28162 # [10]
ld.qr q0,a1,48 # [0] q0
movi.n a10,-16 # [1]
loopnez a3,.LBB209_dspi_dotprod_off_s8_aes3 # [2]
.LBB207_dspi_dotprod_off_s8_aes3: # 0x248
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a10,q0,q1,q2,q3 # [0*II+0] id:789
ee.vmulas.s8.accx.ld.ip q0,a2,16,q1,q6 # [0*II+1] id:790
ee.ld.128.usar.xp q1,a15,a11 # [0*II+2] id:791
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a10,q0,q2,q1,q3 # [0*II+4] id:792
ee.vmulas.s8.accx.ld.ip q0,a2,16,q2,q6 # [0*II+5] id:793
ee.ld.128.usar.xp q4,a15,a11 # [0*II+6] id:794
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a10,q0,q1,q4,q3 # [0*II+8] id:795
ee.vmulas.s8.accx.ld.ip q0,a2,16,q1,q6 # [0*II+9] id:796
ee.ld.128.usar.xp q1,a15,a11 # [0*II+10] id:797
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a10,q0,q4,q1,q3 # [0*II+12] id:798
ee.vmulas.s8.accx.ld.ip q0,a2,16,q4,q6 # [0*II+13] id:799
ee.ld.128.usar.xp q2,a15,a11 # [0*II+14] id:800
.LBB209_dspi_dotprod_off_s8_aes3: # 0x274
st.qr q0,a1,48 # [0] q0
j .Lt_0_28162 # [1]
.LBB57_dspi_dotprod_off_s8_aes3: # 0x27a
ee.ld.128.usar.ip q1,a15,16 # [0] id:801
ee.ld.128.usar.ip q2,a15,16 # [1] id:802
ee.src.q.ld.ip q3,a15,16,q1,q2 # [3] id:803
beqz.n a3,.Lt_0_29698 # [4]
ld.qr q0,a1,48 # [0] q0
movi.n a10,32 # [1]
l32i a12,a1,64 # [2] gra_spill_temp_0
movi.n a11,-16 # [3]
sub a12,a12,a5 # [4]
addi a12,a12,16 # [5]
loopnez a3,.LBB232_dspi_dotprod_off_s8_aes3 # [6]
.LBB230_dspi_dotprod_off_s8_aes3: # 0x298
ee.vmulas.s8.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:804
ee.vmulas.s8.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:805
ee.vmulas.s8.accx.ld.xp.qup q4,a15,a12,q4,q2,q3,q0 # [0*II+3] id:806
ee.vmulas.s8.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:807
ee.vmulas.s8.accx.ld.xp.qup q2,a15,a11,q1,q3,q0,q4 # [0*II+6] id:808
ee.vmulas.s8.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:809
ee.ld.128.usar.xp q1,a15,a10 # [0*II+8] id:810
ee.vmulas.s8.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+10] id:811
ee.vmulas.s8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+11] id:812
.LBB232_dspi_dotprod_off_s8_aes3: # 0x2bb
st.qr q0,a1,48 # [0] q0
j .Lt_0_29698 # [1]
.LBB64_dspi_dotprod_off_s8_aes3: # 0x2c1
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i a12,a1,64 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [3] id:813
ee.ld.128.usar.ip q2,a15,16 # [4] id:814
sub a12,a12,a5 # [6]
addi a12,a12,16 # [7]
ld.qr q0,a1,48 # [8] q0
ee.src.q.ld.ip q3,a15,16,q1,q2 # [9] id:815
mov.n a8,a15 # [10]
loopnez a3,.LBB254_dspi_dotprod_off_s8_aes3 # [11]
.LBB252_dspi_dotprod_off_s8_aes3: # 0x2df
ee.vmulas.s8.accx.ld.ip.qup q0,a8,16,q0,q1,q2,q3 # [0*II+0] id:816
ee.vmulas.s8.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:817
ee.vmulas.s8.accx.ld.ip.qup q4,a8,16,q4,q2,q3,q0 # [0*II+3] id:818
ee.vmulas.s8.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:819
ee.vmulas.s8.accx.ld.ip.qup q1,a8,16,q1,q3,q0,q4 # [0*II+6] id:820
ee.vmulas.s8.accx.ld.ip q5,a2,16,q3,q6 # [0*II+7] id:821
ee.vmulas.s8.accx.ld.ip.qup q5,a8,16,q5,q0,q4,q1 # [0*II+9] id:822
ee.vmulas.s8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:823
ee.vmulas.s8.accx.ld.ip.qup q0,a8,16,q0,q4,q1,q5 # [0*II+12] id:824
ee.vmulas.s8.accx.ld.ip q4,a2,16,q4,q6 # [0*II+13] id:825
ee.vmulas.s8.accx.ld.xp.qup q4,a8,a12,q4,q1,q5,q0 # [0*II+15] id:826
ee.vmulas.s8.accx.ld.ip q1,a2,16,q1,q6 # [0*II+16] id:827
ee.vmulas.s8.accx.ld.xp.qup q2,a8,a11,q1,q5,q0,q4 # [0*II+18] id:828
ee.vmulas.s8.accx.ld.ip q4,a2,16,q5,q6 # [0*II+19] id:829
ee.ld.128.usar.xp q1,a8,a10 # [0*II+20] id:830
ee.vmulas.s8.accx.ld.ip.qup q3,a8,16,q4,q0,q1,q2 # [0*II+22] id:831
ee.vmulas.s8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+23] id:832
.LBB254_dspi_dotprod_off_s8_aes3: # 0x322
movi.n a2,0 # [0]
movi.n a11,1 # [1]
addi.n a12,a7,-1 # [2]
rur.accx_0 a10 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:854
retw.n # [10]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,214
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dsps_dotprod_s16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dsps_dotprod_s16_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dsps_dotprod_s16_arp4
.global dsps_dotprod_s16_ansi
.type dsps_dotprod_s16_arp4,@function
//esp_err_t dsps_dotprod_s16_arp4(const int16_t* src1, const int16_t* src2, int16_t* dest, int len, int8_t shift);
dsps_dotprod_s16_arp4:
// src1 - a0
// src2 - a1
// dest - a2
// len - a3
// shift - a4
andi a5, a3, 7
beqz a5, .dsps_dotprod_s16_arp4_body
j dsps_dotprod_s16_ansi
.dsps_dotprod_s16_arp4_body:
add sp,sp,-16
// Enable analigned data access
esp.movx.r.cfg t6
or t6, t6, 2
esp.movx.w.cfg t6
add t6, a4, -15
neg t6, t6 // t6 - real_shift
li t3, 0x7fff
srl t3, t3, a4
esp.zero.xacc
esp.movx.w.xacc.l t3
mv t3, a0
mv t4, a1
esp.vld.128.ip q0, t3, 16 //q0 - src1
srli t5, a3, 3 // t5 = len>>3
# esp.lp.setup 0, t5, .main_loop
# esp.vld.128.ip q1, t4, 16 // q1 - src1
# .main_loop: esp.vmulas.s16.xacc.ld.ip q0, t3, 16, q0, q1 // q0 - src2
.main_loop:
esp.vld.128.ip q1, t4, 16 // q1 - src1
esp.vmulas.s16.xacc.ld.ip q0, t3, 16, q0, q1 // q0 - src2
add t5, t5, -1
bgtz t5, .main_loop
esp.srs.s.xacc t5, t6 // shift accx register by final_shift amount (a6), save the lower 32bits to a15
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dsps_dotprod_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 14,763
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_u8_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_52, 458755
.type dspi_dotprod_u8_aes3, @function
.align 4
.global dspi_dotprod_u8_aes3
dspi_dotprod_u8_aes3: # 0x4
.LBB1_dspi_dotprod_u8_aes3: # 0x4
entry a1,48 #
l32i.n a10,a2,4 # [0] id:669
l32i.n a11,a2,12 # [1] id:668
mull a8,a10,a5 # [2]
blt a11,a8,.LBB78_dspi_dotprod_u8_aes3 # [4]
l32i.n a12,a2,8 # [0] id:670
l32i.n a9,a2,16 # [1] id:671
mull a13,a12,a6 # [2]
blt a9,a13,.LBB78_dspi_dotprod_u8_aes3 # [4]
l32i.n a15,a3,4 # [0] id:673
l32i.n a14,a3,12 # [1] id:672
mull a13,a15,a5 # [2]
blt a14,a13,.LBB78_dspi_dotprod_u8_aes3 # [4]
l32i.n a8,a3,16 # [0] id:675
l32i.n a9,a3,8 # [1] id:674
s32i.n a9,a1,8 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB78_dspi_dotprod_u8_aes3 # [5]
l32i.n a8,a3,0 # [0] id:676
s32i.n a8,a1,4 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_33026 # [2]
bne a14,a13,.Lt_0_33026 # [0]
bnei a15,1,.Lt_0_33026 # [0]
l32i.n a13,a1,8 # [0] gra_spill_temp_2
beqi a13,1,.Lt_0_17666 # [2]
.Lt_0_33026: # 0x43
.Lt_0_17922: # 0x43
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
.type dspi_dotprod_u8_ansi, @function
call8 dspi_dotprod_u8_ansi # [6] dspi_dotprod_u8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB78_dspi_dotprod_u8_aes3: # 0x56
l32r a2,.LC0_1_52 # [0]
retw.n # [1]
.Lt_0_17666: # 0x5b
addi.n a14,a10,-1 # [0]
bnez a14,.Lt_0_33794 # [1]
addi.n a15,a12,-1 # [0]
bnez a15,.Lt_0_33794 # [1]
extui a8,a5,0,4 # [0]
bnez.n a8,.Lt_0_33794 # [1]
blti a6,4,.Lt_0_33794 # [0]
movi.n a9,64 # [0]
bge a9,a5,.Lt_0_34306 # [1]
extui a10,a5,0,1 # [0]
bnez a10,.LBB28_dspi_dotprod_u8_aes3 # [1]
.Lt_0_34306: # 0x78
.Lt_0_19714: # 0x78
mov.n a3,a6 # [0]
addi a13,a5,-48 # [1]
movi.n a14,0 # [2]
mull a15,a11,a12 # [3]
l32i.n a2,a2,0 # [4] id:677
s32i.n a15,a1,0 # [6] gra_spill_temp_0
wur.accx_0 a14 # [7]
l32i.n a15,a1,4 # [8] gra_spill_temp_1
wur.accx_1 a14 # [9]
ee.vld.128.ip q0,a15,16 # [10] id:680
beqz a13,.LBB32_dspi_dotprod_u8_aes3 # [11]
.Lt_0_22786: # 0x93
.Lt_0_22274: # 0x93
addi a8,a5,-32 # [0]
beqz a8,.LBB38_dspi_dotprod_u8_aes3 # [1]
.Lt_0_24322: # 0x99
.Lt_0_23810: # 0x99
addi a9,a5,-16 # [0]
beqz a9,.LBB44_dspi_dotprod_u8_aes3 # [1]
.Lt_0_25858: # 0x9f
.Lt_0_25346: # 0x9f
addi a10,a5,-64 # [0]
beqz a10,.LBB50_dspi_dotprod_u8_aes3 # [1]
.Lt_0_27394: # 0xa5
.Lt_0_26882: # 0xa5
addi a11,a5,-128 # [0]
beqz a11,.LBB56_dspi_dotprod_u8_aes3 # [1]
movi a12,128 # [0]
bge a12,a5,.Lt_0_30210 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a2,16 # [1] id:752
ee.ld.128.usar.ip q2,a2,16 # [2] id:753
ee.src.q.ld.ip q3,a2,16,q1,q2 # [4] id:754
beqz.n a3,.Lt_0_30210 # [5]
l32i.n a14,a1,0 # [0] gra_spill_temp_0
addi a13,a5,31 # [1]
movgez a13,a5,a5 # [2]
srai a13,a13,5 # [3]
sub a14,a14,a5 # [4]
addi a14,a14,16 # [5]
addi.n a13,a13,-1 # [6]
.Lt_0_30978: # 0xd1
addi.n a12,a12,1 # [0]
movi.n a8,32 # [1]
movi.n a9,-16 # [2]
beqz.n a13,.Lt_0_31234 # [3]
loopnez a13,.LBB218_dspi_dotprod_u8_aes3 # [0]
.LBB216_dspi_dotprod_u8_aes3: # 0xdc
ee.vld.128.ip q5,a15,16 # [0*II+0] id:756
ee.vmulas.u8.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:755
ee.vld.128.ip q0,a15,16 # [0*II+2] id:758
ee.vmulas.u8.accx.ld.ip.qup q1,a2,16,q5,q2,q3,q4 # [0*II+3] id:757
ee.vld.128.ip q5,a15,16 # [0*II+4] id:760
ee.vmulas.u8.accx.ld.ip.qup q2,a2,16,q0,q3,q4,q1 # [0*II+5] id:759
ee.vld.128.ip q0,a15,16 # [0*II+6] id:762
ee.vmulas.u8.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+7] id:761
.LBB218_dspi_dotprod_u8_aes3: # 0xf8
.Lt_0_31234: # 0xf8
ee.vmulas.u8.accx.ld.ip.qup q5,a2,16,q0,q1,q2,q3 # [0] id:763
ee.vld.128.ip q0,a15,16 # [1] id:764
ee.vld.128.ip q6,a15,16 # [2] id:766
ee.vmulas.u8.accx.ld.xp.qup q7,a2,a14,q0,q2,q3,q5 # [3] id:765
ee.vld.128.ip q4,a15,16 # [4] id:769
ee.vmulas.u8.accx.ld.xp.qup q2,a2,a9,q6,q3,q5,q7 # [5] id:767
ee.ld.128.usar.xp q1,a2,a8 # [6] id:768
ee.vld.128.ip q0,a15,16 # [7] id:771
ee.vmulas.u8.accx.ld.ip.qup q3,a2,16,q4,q5,q1,q2 # [8] id:770
bne a12,a3,.Lt_0_30978 # [9]
.Lt_0_30210: # 0x11a
.Lt_0_29954: # 0x11a
movi.n a2,0 # [0]
rur.accx_0 a10 # [1]
addi.n a12,a7,-1 # [2]
movi.n a11,1 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
srl a10,a10 # [8]
s8i a10,a4,0 # [9] id:773
retw.n # [10]
.Lt_0_33794: # 0x136
.Lt_0_18946: # 0x136
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_u8_ansi # [6] dspi_dotprod_u8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB32_dspi_dotprod_u8_aes3: # 0x149
ee.ld.128.usar.ip q1,a2,16 # [0] id:681
ee.ld.128.usar.ip q2,a2,16 # [1] id:682
ee.src.q.ld.ip q3,a2,16,q1,q2 # [3] id:683
beqz.n a6,.Lt_0_22786 # [4]
movi.n a10,32 # [0]
l32i.n a12,a1,0 # [1] gra_spill_temp_0
movi.n a11,-16 # [2]
addi a12,a12,-32 # [3]
loopgtz a6,.LBB104_dspi_dotprod_u8_aes3 # [4]
.LBB102_dspi_dotprod_u8_aes3: # 0x160
ee.vld.128.ip q4,a15,16 # [0*II+0] id:685
ee.vmulas.u8.accx.ld.xp.qup q1,a2,a12,q0,q1,q2,q3 # [0*II+1] id:684
ee.vld.128.ip q5,a15,16 # [0*II+2] id:687
ee.vmulas.u8.accx.ld.xp.qup q2,a2,a11,q4,q2,q3,q1 # [0*II+3] id:686
ee.ld.128.usar.xp q1,a2,a10 # [0*II+4] id:688
ee.vld.128.ip q0,a15,16 # [0*II+5] id:690
ee.vmulas.u8.accx.ld.ip.qup q3,a2,16,q5,q3,q1,q2 # [0*II+6] id:689
.LBB104_dspi_dotprod_u8_aes3: # 0x178
j .Lt_0_22786 # [0]
.LBB38_dspi_dotprod_u8_aes3: # 0x17b
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
srli a3,a6,1 # [2]
l32i.n a12,a1,0 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:691
ee.ld.128.usar.ip q2,a2,16 # [5] id:692
addi a12,a12,-16 # [7]
ee.src.q.ld.xp q3,a2,a12,q1,q2 # [8] id:693
loopnez a3,.LBB127_dspi_dotprod_u8_aes3 # [9]
.LBB125_dspi_dotprod_u8_aes3: # 0x193
ee.vld.128.ip q4,a15,16 # [0*II+0] id:695
ee.vmulas.u8.accx.ld.xp.qup q3,a2,a11,q0,q1,q2,q3 # [0*II+1] id:694
ee.ld.128.usar.xp q1,a2,a10 # [0*II+2] id:696
ee.vld.128.ip q0,a15,16 # [0*II+3] id:698
ee.vmulas.u8.accx.ld.xp.qup q4,a2,a12,q4,q2,q1,q3 # [0*II+4] id:697
ee.vld.128.ip q5,a15,16 # [0*II+5] id:700
ee.vmulas.u8.accx.ld.xp.qup q2,a2,a11,q0,q1,q3,q4 # [0*II+6] id:699
ee.ld.128.usar.xp q1,a2,a10 # [0*II+7] id:701
ee.vld.128.ip q0,a15,16 # [0*II+8] id:703
ee.vmulas.u8.accx.ld.xp.qup q3,a2,a12,q5,q3,q1,q2 # [0*II+9] id:702
.LBB127_dspi_dotprod_u8_aes3: # 0x1b5
j .Lt_0_24322 # [0]
.LBB44_dspi_dotprod_u8_aes3: # 0x1b8
srli a3,a3,2 # [0]
movi.n a10,-16 # [1]
l32i.n a11,a1,0 # [2] gra_spill_temp_0
addi a8,a2,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a8,a10 # [5] id:704
ee.ld.128.usar.xp q1,a8,a11 # [6] id:705
ee.src.q.ld.xp q3,a8,a10,q1,q2 # [8] id:706
ee.ld.128.usar.xp q2,a8,a11 # [9] id:707
loopnez a3,.LBB150_dspi_dotprod_u8_aes3 # [10]
.LBB148_dspi_dotprod_u8_aes3: # 0x1d4
ee.vld.128.ip q4,a15,16 # [0*II+0] id:709
ee.vmulas.u8.accx.ld.xp.qup q3,a8,a10,q0,q1,q2,q3 # [0*II+1] id:708
ee.ld.128.usar.xp q1,a8,a11 # [0*II+2] id:710
ee.vld.128.ip q0,a15,16 # [0*II+3] id:712
ee.vmulas.u8.accx.ld.xp.qup q4,a8,a10,q4,q2,q1,q3 # [0*II+4] id:711
ee.ld.128.usar.xp q3,a8,a11 # [0*II+5] id:713
ee.vld.128.ip q5,a15,16 # [0*II+6] id:715
ee.vmulas.u8.accx.ld.xp.qup q4,a8,a10,q0,q1,q3,q4 # [0*II+7] id:714
ee.ld.128.usar.xp q1,a8,a11 # [0*II+8] id:716
ee.vld.128.ip q0,a15,16 # [0*II+9] id:718
ee.vmulas.u8.accx.ld.xp.qup q3,a8,a10,q5,q3,q1,q4 # [0*II+10] id:717
ee.ld.128.usar.xp q2,a8,a11 # [0*II+11] id:719
.LBB150_dspi_dotprod_u8_aes3: # 0x1fc
mov.n a2,a8 # [0]
j .Lt_0_25858 # [1]
.LBB50_dspi_dotprod_u8_aes3: # 0x201
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i.n a12,a1,0 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [3] id:720
ee.ld.128.usar.ip q2,a2,16 # [4] id:721
sub a12,a12,a5 # [5]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [7] id:722
addi a12,a12,16 # [8]
loopnez a3,.LBB173_dspi_dotprod_u8_aes3 # [9]
.LBB171_dspi_dotprod_u8_aes3: # 0x219
ee.vld.128.ip q5,a15,16 # [0*II+0] id:724
ee.vmulas.u8.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:723
ee.vld.128.ip q1,a15,16 # [0*II+2] id:726
ee.vmulas.u8.accx.ld.xp.qup q0,a2,a12,q5,q2,q3,q4 # [0*II+3] id:725
ee.vld.128.ip q5,a15,16 # [0*II+4] id:729
ee.vmulas.u8.accx.ld.xp.qup q2,a2,a11,q1,q3,q4,q0 # [0*II+5] id:727
ee.ld.128.usar.xp q1,a2,a10 # [0*II+6] id:728
ee.vld.128.ip q0,a15,16 # [0*II+7] id:731
ee.vmulas.u8.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+8] id:730
.LBB173_dspi_dotprod_u8_aes3: # 0x238
j .Lt_0_27394 # [0]
.LBB56_dspi_dotprod_u8_aes3: # 0x23b
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i.n a12,a1,0 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [3] id:732
ee.ld.128.usar.ip q2,a2,16 # [4] id:733
sub a12,a12,a5 # [6]
addi a12,a12,16 # [7]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [8] id:734
loopnez a3,.LBB195_dspi_dotprod_u8_aes3 # [9]
.LBB193_dspi_dotprod_u8_aes3: # 0x253
ee.vld.128.ip q4,a15,16 # [0*II+0] id:736
ee.vmulas.u8.accx.ld.ip.qup q1,a2,16,q0,q1,q2,q3 # [0*II+1] id:735
ee.vld.128.ip q0,a15,16 # [0*II+2] id:738
ee.vmulas.u8.accx.ld.ip.qup q4,a2,16,q4,q2,q3,q1 # [0*II+3] id:737
ee.vld.128.ip q5,a15,16 # [0*II+4] id:740
ee.vmulas.u8.accx.ld.ip.qup q0,a2,16,q0,q3,q1,q4 # [0*II+5] id:739
ee.vld.128.ip q6,a15,16 # [0*II+6] id:742
ee.vmulas.u8.accx.ld.ip.qup q1,a2,16,q5,q1,q4,q0 # [0*II+7] id:741
ee.vld.128.ip q5,a15,16 # [0*II+8] id:744
ee.vmulas.u8.accx.ld.ip.qup q4,a2,16,q6,q4,q0,q1 # [0*II+9] id:743
ee.vld.128.ip q6,a15,16 # [0*II+10] id:746
ee.vmulas.u8.accx.ld.xp.qup q0,a2,a12,q5,q0,q1,q4 # [0*II+11] id:745
ee.vld.128.ip q5,a15,16 # [0*II+12] id:749
ee.vmulas.u8.accx.ld.xp.qup q2,a2,a11,q6,q1,q4,q0 # [0*II+13] id:747
ee.ld.128.usar.xp q1,a2,a10 # [0*II+14] id:748
ee.vld.128.ip q0,a15,16 # [0*II+15] id:751
ee.vmulas.u8.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+16] id:750
.LBB195_dspi_dotprod_u8_aes3: # 0x28e
movi.n a2,0 # [0]
movi.n a11,1 # [1]
addi.n a12,a7,-1 # [2]
rur.accx_0 a10 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
srl a10,a10 # [8]
s8i a10,a4,0 # [9] id:773
retw.n # [10]
.LBB28_dspi_dotprod_u8_aes3: # 0x2aa
mov.n a15,a7 # [0]
mov.n a14,a6 # [1]
mov.n a13,a5 # [2]
mov.n a12,a4 # [3]
mov.n a11,a3 # [4]
mov.n a10,a2 # [5]
call8 dspi_dotprod_u8_ansi # [6] dspi_dotprod_u8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,828
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_u8_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_off_u8_arp4
.global dspi_dotprod_off_u8_ansi
.type dspi_dotprod_off_u8_arp4,@function
// esp_err_t dspi_dotprod_off_u8_arp4(image2d_t *in_image, image2d_t *filter, uint16_t *out_value, int count_x, int count_y, int shift, uint8_t offset);
dspi_dotprod_off_u8_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// offset - a6
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 15
or t1, t1, t2
beqz t1, .dspi_dotprod_off_u8_arp4_body
j dspi_dotprod_off_u8_ansi
.dspi_dotprod_off_u8_arp4_body:
add sp, sp, -16
sw a6, 0(sp)
mv t6, sp
esp.vldbc.8.ip q2, t6, 0
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
srli t6, a3, 4 // t5 = len/16
addi a7, a5, -1
li t4, 1
sll t4, t4, a7
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q1, t5, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q0, t4, 16 // q1 - f_data
esp.vadd.u8 q3, q2, q1
.loop_count_x: esp.vmulas.u8.xacc.ld.ip q1, t5, 16, q0, q3 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.u.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 2,983
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fir/float/dsps_fird_f32_arp4.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fir_platform.h"
#if (dsps_fird_f32_arp4_enabled == 1)
// This is FIR filter for esp32p4 processor.
.text
.align 4
.global dsps_fird_f32_arp4
.type dsps_fird_f32_arp4,@function
// The function implements the following C code:
//esp_err_t dsps_fird_f32_arp4(fir_f32_t* fir, const float* input, float* output, int len);
dsps_fird_f32_arp4:
add sp,sp,-16
mv a6, a3
lw t1, 4(a0) // t1 - delay
lw a4, 4(a0) // a4 - delay
lw t2, 8(a0) // t2 - N :FIR filter coefficients amount
lw t3, 12(a0) // t3 - pos
lw t4, 16(a0) // t4 - decim
slli t3, t3, 2 // t5 = pos*4 (bytes)
add t1, t1, t3 // delay[pos]
slli t6, t2, 2 // t6 = N*4 (bytes)
add t3, a4, t6 // last position for the daly[N]
nop
.fird_loop_len:
// p.lw a1, 4(a1)
//fmv.w.x fa5,zero
flw fa0, 0(a1) // f0 = x[i], first load
esp.lp.setup 0, t4, .fird_load_data // label to the last executed instruction
add a1, a1, 4 // i++
fsw fa0, 0(t1) // delay[pos]
add t1, t1, 4
blt t1, t3, .do_not_reset_pos # if t0 < t1 then target
lw t1, 4(a0) // t1 - delay
.do_not_reset_pos:
.fird_load_data: flw fa0, 0(a1) // f0 = x[i]
lw t0, 0(a0) // t0 - coeffs
sub t5, t3, t1 // (last_pos - pos)*4
srli t5, t5, 2 // N-pos
sub t6, t1, a4
srli t6, t6, 2 // pos
fmv.w.x fa2,zero
lw a5, 0(a0) // a5 - coeffs
esp.lp.setup 0, t5, .first_fird_loop
flw fa1, 0(a5)
flw fa0, 0(t1)
addi a5, a5, 4
fmadd.s fa2, fa1, fa0, fa2
.first_fird_loop: addi t1, t1, 4
lw t1, 4(a0) // t1 - delay
beqz t6, .skeep_loop
esp.lp.setup 0, t6, .second_fird_loop
flw fa1, 0(a5)
flw fa0, 0(t1)
addi a5, a5, 4
fmadd.s fa2, fa1, fa0, fa2
.second_fird_loop: addi t1, t1, 4
.skeep_loop:
// Store result
fsw fa2, 0(a2)
addi a2, a2, 4
addi a3, a3, -1
BNEZ a3, .fird_loop_len// Jump if > 0
sub t6, t1, a4
srli t6, t6, 2 // pos
sw t6, 12(a0) // t3 - pos
mv a0, a6
add sp,sp,16
ret
#endif //
|
georgevio/IoT-Embedded
| 7,929
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fir/float/dsps_fird_f32_aes3.S
|
// Copyright 2018-2023 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fir_platform.h"
#if (dsps_fird_f32_aes3_enabled == 1)
// This is FIR filter for Esp32s3 processor.
.text
.align 4
.global dsps_fird_f32_aes3
.type dsps_fird_f32_aes3,@function
// The function implements the following C code:
//esp_err_t dsps_fird_f32_aes3(fir_f32_t* fir, const float* input, float* output, int len);
dsps_fird_f32_aes3:
// fir - a2
// input - a3
// output - a4
// len - a5
// a2 - fir structure
// a3 - input
// a4 - output
// a5 - length
// a6 - fir length
// a7 - position in delay line
// a8 - temp
// a10 - coeffs ptr
// a11 - delay line ptr
// a12 - const
// a13 -
// a14 - temp for loops
// a15 - delay line rounded to 16
entry a1, 16
// Array increment for floating point data should be 4
l32i a7, a2, 12 // a7 - pos
l32i a6, a2, 8 // a6 - N - amount of coefficients
l32i a10, a2, 0 // a10 - coeffs
l32i a11, a2, 4 // a11 - delay line
addx4 a11, a7, a11 // a11 = a11 + a7*4
l32i a6, a2, 8 // a6 - N
mov.n a9, a5
movi.n a12, 3
movi.n a12, -16
movi.n a13, 15
// Main loop for input samples
.fird_loop_len:
// Store K values from input to delay line:
l32i a14, a2, 16 // a14 - decimation
loopnez a14, .fird_load_data // K loops
// Store to delay line
lsip f15, a3, 4 // a3 += 4, f15 = input[n]
ssip f15, a11, 4 // a11 += 4, *a11 = f15
addi a7, a7, 1 // a7++ - position in delay line
blt a7, a6, .do_not_reset_a11
l32i a11, a2, 4 // Load delay line
movi a7, 0
.do_not_reset_a11:
and a15, a11, a12
.fird_load_data:
//
// Process data
//
// Load rounded delay line address
l32i a10, a2, 0 // a10 - coeffs
// Clear f4, f5 for multiplications
const.s f4, 0
const.s f5, 0
const.s f6, 0
const.s f7, 0
and a8, a11, a13 // a8 = a11 & 15
beqz a8, .offset_0
addi a8, a8, -4
beqz a8, .offset_1
addi a8, a8, -4
beqz a8, .offset_2
addi a8, a8, -4
beqz a8, .offset_3
// a10 - coeffs
// a11 - delay line
.offset_0:
sub a14, a6, a7 // a14 = N-pos
srli a14, a14, 2
loopnez a14, .first_fir_loop_0 // pos...N-1
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
madd.s f4, f0, f8
madd.s f5, f1, f9
madd.s f6, f2, f10
madd.s f7, f3, f11
.first_fir_loop_0:
l32i a15, a2, 4 // a11 - delay line [0]
srli a14, a7, 2
loopnez a14, .second_fir_loop_0 // 0..pos
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
madd.s f4, f0, f8
madd.s f5, f1, f9
madd.s f6, f2, f10
madd.s f7, f3, f11
.second_fir_loop_0:
j .store_fir_result;
.offset_1:
sub a14, a6, a7 // a14 = N-pos
addi a14, a14, 3
srli a14, a14, 2
EE.LDF.128.IP f11, f10, f9, f12, a15, 16 // Load data from delay line
// f12 - delay[N-1], store for the last operation
// f9..f11 - delay[0..2]
loopnez a14, .first_fir_loop_1 // pos...N-1
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f4, f0, f9
madd.s f5, f1, f10
madd.s f6, f2, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
madd.s f7, f3, f8
.first_fir_loop_1:
l32i a15, a2, 4 // a11 - delay line [0]
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
srli a14, a7, 2
loopnez a14, .second_fir_loop_1 // 0..pos
madd.s f4, f3, f8
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f5, f0, f9
madd.s f6, f1, f10
madd.s f7, f2, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
.second_fir_loop_1:
madd.s f4, f3, f12
j .store_fir_result;
.offset_2:
sub a14, a6, a7 // a14 = N-pos
addi a14, a14, 3
srli a14, a14, 2
EE.LDF.128.IP f11, f10, f13, f12, a15, 16 // Load data from delay line
// f12, f13 - delay[N-1], delay[N-2], store for the last operation
// f10..f11 - delay[0..1]
loopnez a14, .first_fir_loop_2 // pos...N-1
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f4, f0, f10
madd.s f5, f1, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
madd.s f6, f2, f8
madd.s f7, f3, f9
.first_fir_loop_2:
l32i a15, a2, 4 // a11 - delay line [0]
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
srli a14, a7, 2
loopnez a14, .second_fir_loop_2 // 0..pos
madd.s f4, f2, f8
madd.s f5, f3, f9
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f6, f0, f10
madd.s f7, f1, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
.second_fir_loop_2:
madd.s f4, f2, f12
madd.s f5, f3, f13
j .store_fir_result;
.offset_3:
sub a14, a6, a7 // a14 = N-pos
addi a14, a14, 3
srli a14, a14, 2
EE.LDF.128.IP f11, f14, f13, f12, a15, 16 // Load data from delay line
// f12, f13, f14 - delay[N-1], delay[N-2], delay[N-3], store for the last operation
// f11 - delay[0]
loopnez a14, .first_fir_loop_3 // pos...N-1
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f4, f0, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
madd.s f5, f1, f8
madd.s f6, f2, f9
madd.s f7, f3, f10
.first_fir_loop_3:
l32i a15, a2, 4 // a11 - delay line [0]
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
srli a14, a7, 2
loopnez a14, .second_fir_loop_3 // 0..pos
madd.s f4, f1, f8
madd.s f5, f2, f9
madd.s f6, f3, f10
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f7, f0, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
.second_fir_loop_3:
madd.s f4, f1, f12
madd.s f5, f2, f13
madd.s f4, f3, f14
.store_fir_result:
add.s f4, f4, f5
add.s f6, f6, f7
add.s f4, f4, f6
// Store result
ssip f4, a4, 4 // y++ - save result and increment output pointer
// Check loop length
addi a5, a5, -1
bnez a5, .fird_loop_len
// store state
s32i a7, a2, 12 // pos = a7
mov.n a2, a9
retw.n
#endif // dsps_fir_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 7,701
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fir/float/dsps_fir_f32_aes3.S
|
// Copyright 2018-2023 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fir_platform.h"
#if (dsps_fir_f32_aes3_enabled == 1)
// This is FIR filter for Esp32s3 processor.
.text
.align 4
.global dsps_fir_f32_aes3
.type dsps_fir_f32_aes3,@function
// The function implements the following C code:
//esp_err_t dsps_fir_f32_aes3(fir_f32_t* fir, const float* input, float* output, int len);
dsps_fir_f32_aes3:
// fir - a2
// input - a3
// output - a4
// len - a5
// a2 - fir structure
// a3 - input
// a4 - output
// a5 - length
// a6 - fir length
// a7 - position in delay line
// a8 - temp
// a9 - const 0
// a10 - coeffs ptr
// a11 - delay line ptr
// a12 - const
// a13 -
// a14 - temp for loops
// a15 - delay line rounded to 16
entry a1, 16
// Array increment for floating point data should be 4
l32i a7, a2, 12 // a7 - pos
l32i a6, a2, 8 // a6 - N - amount of coefficients
l32i a10, a2, 0 // a10 - coeffs
l32i a11, a2, 4 // a11 - delay line
addx4 a11, a7, a11 // a11 = a11 + a7*4
l32i a6, a2, 8 // a6 - N
movi.n a9, 0
movi.n a12, 3
movi.n a12, -16
movi.n a13, 15
// Main loop for input samples
.fir_loop_len:
// Store to delay line
lsip f15, a3, 4 // a3 += 4, f15 = input[n]
ssip f15, a11, 4 // a11 += 4, *a11 = f15
addi a7, a7, 1 // a7++ - position in delay line
//
blt a7, a6, .do_not_reset_a11
l32i a11, a2, 4 // Load delay line
movi a7, 0
.do_not_reset_a11:
// Load rounded delay line address
and a15, a11, a12
l32i a10, a2, 0 // a10 - coeffs
// Clear f4, f5 for multiplications
const.s f4, 0
const.s f5, 0
const.s f6, 0
const.s f7, 0
and a8, a11, a13 // a8 = a11 & 15
beqz a8, .offset_0
addi a8, a8, -4
beqz a8, .offset_1
addi a8, a8, -4
beqz a8, .offset_2
addi a8, a8, -4
beqz a8, .offset_3
// a10 - coeffs
// a11 - delay line
.offset_0:
sub a14, a6, a7 // a14 = N-pos
srli a14, a14, 2
loopnez a14, .first_fir_loop_0 // pos...N-1
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
madd.s f4, f0, f8
madd.s f5, f1, f9
madd.s f6, f2, f10
madd.s f7, f3, f11
.first_fir_loop_0:
l32i a15, a2, 4 // a11 - delay line [0]
srli a14, a7, 2
loopnez a14, .second_fir_loop_0 // 0..pos
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
madd.s f4, f0, f8
madd.s f5, f1, f9
madd.s f6, f2, f10
madd.s f7, f3, f11
.second_fir_loop_0:
j .store_fir_result;
.offset_1:
sub a14, a6, a7 // a14 = N-pos
addi a14, a14, 3
srli a14, a14, 2
EE.LDF.128.IP f11, f10, f9, f12, a15, 16 // Load data from delay line
// f12 - delay[N-1], store for the last operation
// f9..f11 - delay[0..2]
loopnez a14, .first_fir_loop_1 // pos...N-1
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f4, f0, f9
madd.s f5, f1, f10
madd.s f6, f2, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
madd.s f7, f3, f8
.first_fir_loop_1:
l32i a15, a2, 4 // a11 - delay line [0]
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
srli a14, a7, 2
loopnez a14, .second_fir_loop_1 // 0..pos
madd.s f4, f3, f8
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f5, f0, f9
madd.s f6, f1, f10
madd.s f7, f2, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
.second_fir_loop_1:
madd.s f4, f3, f12
j .store_fir_result;
.offset_2:
sub a14, a6, a7 // a14 = N-pos
addi a14, a14, 3
srli a14, a14, 2
EE.LDF.128.IP f11, f10, f13, f12, a15, 16 // Load data from delay line
// f12, f13 - delay[N-1], delay[N-2], store for the last operation
// f10..f11 - delay[0..1]
loopnez a14, .first_fir_loop_2 // pos...N-1
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f4, f0, f10
madd.s f5, f1, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
madd.s f6, f2, f8
madd.s f7, f3, f9
.first_fir_loop_2:
l32i a15, a2, 4 // a11 - delay line [0]
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
srli a14, a7, 2
loopnez a14, .second_fir_loop_2 // 0..pos
madd.s f4, f2, f8
madd.s f5, f3, f9
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f6, f0, f10
madd.s f7, f1, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
.second_fir_loop_2:
madd.s f4, f2, f12
madd.s f5, f3, f13
j .store_fir_result;
.offset_3:
sub a14, a6, a7 // a14 = N-pos
addi a14, a14, 3
srli a14, a14, 2
EE.LDF.128.IP f11, f14, f13, f12, a15, 16 // Load data from delay line
// f12, f13, f14 - delay[N-1], delay[N-2], delay[N-3], store for the last operation
// f11 - delay[0]
loopnez a14, .first_fir_loop_3 // pos...N-1
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f4, f0, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
madd.s f5, f1, f8
madd.s f6, f2, f9
madd.s f7, f3, f10
.first_fir_loop_3:
l32i a15, a2, 4 // a11 - delay line [0]
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
srli a14, a7, 2
loopnez a14, .second_fir_loop_3 // 0..pos
madd.s f4, f1, f8
madd.s f5, f2, f9
madd.s f6, f3, f10
EE.LDF.128.IP f3, f2, f1, f0, a10, 16 // Load coeffs
madd.s f7, f0, f11
EE.LDF.128.IP f11, f10, f9, f8, a15, 16 // Load data from delay line
.second_fir_loop_3:
madd.s f4, f1, f12
madd.s f5, f2, f13
madd.s f4, f3, f14
.store_fir_result:
add.s f4, f4, f5
add.s f6, f6, f7
add.s f4, f4, f6
// Store result
ssip f4, a4, 4 // y++ - save result and increment output pointer
// Check loop length
addi a5, a5, -1
bnez a5, .fir_loop_len
// store state
s32i a7, a2, 12 // pos = a7
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_fir_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 2,795
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fir/float/dsps_fir_f32_ae32.S
|
// Copyright 2018-2023 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fir_platform.h"
#if (dsps_fir_f32_ae32_enabled == 1)
#include "dsps_dotprod_f32_m_ae32.S"
// This is FIR filter for ESP32 processor.
.text
.align 4
.global dsps_fir_f32_ae32
.type dsps_fir_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_fir_f32_ae32(fir_f32_t* fir, const float* input, float* output, int len);
dsps_fir_f32_ae32:
// fir - a2
// input - a3
// output - a4
// len - a5
entry a1, 16
// Array increment for floating point data should be 4
l32i a7, a2, 12 // a7 - pos
movi a10, 4
mull a13, a7, a10// a13 - a7*4
l32i a6, a2, 8 // a6 - N
mull a6, a6, a10// a6 = a6*4
l32i a10, a2, 0 // a10 - coeffs
l32i a6, a2, 8 // a6 - N
movi.n a9, 0
movi.n a8, 4
movi.n a12, 4
// a13 - delay index
fir_loop_len:
// Store to delay line
l32i a11, a2, 4 // a11 - delay line
lsi f0, a3, 0 // f0 = x[i]
addi a3, a3, 4 // x++
ssx f0, a11, a13 // delay[a13] = f0;
addi a13, a13, 4 // a13++
addi a7, a7, 1 // a7++
// verify deley line
blt a7, a6, do_not_reset_a13
movi a13, 0
movi a7, 0
do_not_reset_a13:
// Calc amount for delay line before end
mov a15, a10 // a15 - coeffs
wfr f2, a9 // f2 = 0;
sub a14, a6, a7 // a14 = N-pos
// a11 = &delay[pos]
add a11, a11, a13
loopnez a14, first_fir_loop // pos...N-1
lsxp f1, a15, a8 // f1 = *(coeffs--)
lsxp f0, a11, a12 // load delay f0 = *(delay++)
madd.s f2, f0, f1 // f2 += f0*f1
first_fir_loop:
l32i a11, a2, 4 // a11 - delay line
loopnez a7, second_fir_loop // 0..pos
lsxp f1, a15, a8 // f1 = *(coeffs--)
lsxp f0, a11, a12 // load delay f0 = *(delay++)
madd.s f2, f0, f1 // f2 += f0*f1
second_fir_loop:
// and after end
// Store result
ssi f2, a4, 0
addi a4, a4, 4 // y++ - increment output pointer
// Check loop
addi a5, a5, -1
bnez a5, fir_loop_len
// store state
s32i a7, a2, 12 // pos = a7
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_fir_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,931
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fir/float/dsps_fird_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fir_platform.h"
#if (dsps_fird_f32_ae32_enabled == 1)
#include "dsps_dotprod_f32_m_ae32.S"
// This is FIR filter for ESP32 processor.
.text
.align 4
.global dsps_fird_f32_ae32
.type dsps_fird_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_fird_f32_ae32(fir_f32_t* fir, const float* input, float* output, int len);
dsps_fird_f32_ae32:
// fir - a2
// input - a3
// output - a4
// len - a5
entry a1, 16
// Array increment for floating point data should be 4
l32i a7, a2, 12 // a7 - pos
movi a10, 4
mull a13, a7, a10// a13 - a7*4
l32i a6, a2, 8 // a6 - N
mull a6, a6, a10// a6 = a6*4
l32i a10, a2, 0 // a10 - coeffs
l32i a11, a2, 4 // a11 - delay line
l32i a6, a2, 8 // a6 - N
l32i a12, a2, 16 // a12 - decimation
movi a8, 0 // result = 0;
// a13 - delay index
fird_loop_len:
// Store to delay line
loopnez a12, .fird_load_data // K loops
lsip f0, a3, 4 // f0 = x[i++]
ssx f0, a11, a13 // delay[a13] = f0;
addi a13, a13, 4 // a13++
addi a7, a7, 1 // a7++
// verify deley line
blt a7, a6, do_not_reset_a13
movi a13, 0
movi a7, 0
do_not_reset_a13:
const.s f2, 0
.fird_load_data:
addi a8, a8, 1
// Calc amount for delay line before end
mov a15, a10 // a15 - coeffs
sub a14, a6, a7 // a14 = N-pos
loopnez a14, first_fird_loop // pos...N-1
lsip f1, a15, 4 // a15++
lsx f0, a11, a13 // load delay f0 = delay[pos]
addi a13, a13, 4 // a13++, pos++
madd.s f2, f0, f1 // f2 += f0*f1
first_fird_loop:
movi a13, 0 // load delay line counter to 0
loopnez a7, second_fird_loop // 0..pos
lsip f1, a15, 4 // a15++
lsx f0, a11, a13 // load delay f0 = delay[pos]
addi a13, a13, 4 // a13++, pos++
madd.s f2, f0, f1 // f2 += f0*f1
second_fird_loop:
// and after end
// Store result
ssi f2, a4, 0
addi a4, a4, 4 // y++ - increment output pointer
next_itt_fir32:
// Check loop
addi a5, a5, -1
bnez a5, fird_loop_len
// store state
s32i a7, a2, 12 // pos = a7
mov a2, a8 // return status ESP_OK
retw.n
#endif // dsps_fird_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 4,673
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fir/fixed/dsps_fird_s16_arp4.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fir_platform.h"
#if (dsps_fird_s16_arp4_enabled == 1)
// This is FIR filter for esp32p4 processor.
.text
.align 4
.global dsps_fird_s16_arp4
.global dsps_fird_s16_ansi
.type dsps_fird_s16_arp4,@function
// The function implements the following C code:
// int32_t dsps_fird_s16_arp4(fir_s16_t *fir, const int16_t *input, int16_t *output, int32_t len);
dsps_fird_s16_arp4:
// In case of filter length different then 8*K
lh t2, 8(a0) // t2 - coeffs_len
andi t2, t2, 7
beqz t2, .dsps_fird_s16_arp4_body
j dsps_fird_s16_ansi
.dsps_fird_s16_arp4_body:
add sp,sp,-48
sw s0, 0(sp)
sw s1, 4(sp)
sw s2, 8(sp)
sw s3, 12(sp)
sw s4, 16(sp)
sw s5, 20(sp)
sw s6, 24(sp)
sw s7, 28(sp)
sw s8, 32(sp)
sw s9, 36(sp)
sw s10, 40(sp)
sw s11, 44(sp)
// Enable analigned data access
esp.movx.r.cfg t6
or t6, t6, 2
esp.movx.w.cfg t6
lw t1, 4(a0) // t1 - delay_line
lh t2, 8(a0) // t2 - coeffs_len
lh t3, 10(a0) // t3 - pos
lh t6, 16(a0) // t6 - shift
add t6, t6, -15
neg t6, t6
lw t5, 20(a0) // t5 - rounding_buff
lw s2, 4(a0) // s2 - delay_line* current position
add s2, s2, t3 // s2 = delay_line + pos*2
add s2, s2, t3 //
add s4, t2, t2 // s4 = coeff_len*2
add s0, t1, s4 // s0 - &delay[coeffs_len]
lh a4, 0(t1)
.loop_len:
lh t4, 12(a0) // t4 - decim
.loop_decim_copy:
lh s1, 0(a1) // load input data
add a1, a1, 2
sh s1, 0(s2)
add s2, s2, 2 // preincrement of delay line
bgt s0, s2, .skeep_reset
lw s2, 4(a0) // s2 - delay_line
.skeep_reset:
add t4, t4, -1
bgtz t4, .loop_decim_copy
// s5 - count1 = length - pos
// s6 = count1 >> 3 :
sub t3, s2, t1
srli t3, t3, 1 // t3 = (pos*2)>>1
sub s5, t2, t3
srli s6, s5, 3 // s6 = (coeff_len - pos)>>3
srli s7, t3, 3 // s7 = pos>>3
and s8, t3, 0x07 // s8 = pos&0x07
esp.ld.xacc.ip t5, 0 // load rounding value to accx
lw s10, 0(a0) // s10 - coeffs
esp.vld.128.ip q0, s10, 16 //q0 - coeffs
mv s9, s2 // s9 - pointer to delay line
esp.vld.128.ip q1, s9, 16 // q1 - delay line data
beqz s6, .skip_main_loop1
esp.lp.setup 0, s6, .main_loop1
esp.vmulas.s16.xacc.ld.ip q0, s10, 16, q0, q1 // q0 - coeffs, q1 - data
.main_loop1: esp.vld.128.ip q1, s9, 16 // Load delay line
.skip_main_loop1: nop
add s9, s9, -16
sub s9, s9, s4
beqz s8, .skip_rest_add
esp.vld.128.ip q2, s9, 16
esp.vadd.s16 q1, q2, q1
esp.vmulas.s16.xacc.ld.ip q0, s10, 16, q0, q1 // q0 - coeffs, q1 - data
.skip_rest_add:
esp.vld.128.ip q1, s9, 16
beqz s7, .skip_main_loop3
esp.lp.setup 1, s7, .main_loop3
esp.vmulas.s16.xacc.ld.ip q0, s10, 16, q0, q1 // q0 - coeffs, q1 - data
esp.vld.128.ip q1, s9, 16
.main_loop3: nop
.skip_main_loop3: nop
// Shift and Store result
esp.srs.s.xacc s11, t6 // shift accx register by final_shift amount (a6), save the lower 32bits to a15
sh s11, 0(a2) // store result to output buffer
add a2, a2, 2
add a3, a3, -1
bgtz a3, .loop_len
sh t3, 10(a0)
.fast_exit:
mv a0, a6
lw s0, 0(sp)
lw s1, 4(sp)
lw s2, 8(sp)
lw s3, 12(sp)
lw s4, 16(sp)
lw s5, 20(sp)
lw s6, 24(sp)
lw s7, 28(sp)
lw s8, 32(sp)
lw s9, 36(sp)
lw s10, 40(sp)
lw s11, 44(sp)
add sp,sp,48
ret
#endif //
|
georgevio/IoT-Embedded
| 3,489
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fir/fixed/dsps_fir_s16_m_ae32.S
|
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
.macro fir_s16_ae32_mul x1, x2, count, ID
// This macro calculates fixed point dot product for ((count + 1)*4) int16 samples
// x1 - input array1 register (samples)
// x2 - input array2 register (coefficients) the array is inverted and is being decremented
// count - counter register (for example a7)
// count - (samples_count / 4) - 1
// acc += x1[i + 0]*x2[N - i - 1] + x1[i + 1]*x2[N - i - 2] + x1[i + 2]*x2[N - i - 3] + x1[i + 3]*x2[N - i - 4]; i: 0..count
// acchi, and acclo have to be initialized before
// Result - acchi || acclo
// Modifies:
// m0, m1, m2, m3
// acchi || acclo - must be loaded before (for example 0x3fff to acclo).
/*
* Data schedule. Each line represents instruction and columns represent
* register contents. Last column (MUL) shows the multiplication which
* takes place. Values loaded in the given cycle are shown in square brackets.
*
* m0 m1 m2 m3 MUL
* ----------------- pre-load --------------------------
*[x0 x1] (no MULs in the first 3 instructions)
* x0 x1 [y(N-1) y(N-2)]
* x0 x1 [x2 x3] y(N-1) y(N-2)
* x0 x1 x2 x3 y(N-1) y(N-2) [y(N-3) y(N-4)] x0*y(N-1)
* -------------------- loop ------------------------ (the following 4 instructions are
*[x4 x5] x2 x3 y(N-1) y(N-2) y(N-3) y(N-4) x1*y(N-2) repeated as much as needed)
* x4 x5 x2 x3 [y(N-5) y(M-6)] y(N-3) y(N-4) x2*y(N-3)
* x4 x5 [x6 x7] y(N-5) y(M-6) y(N-3) y(N-4) x3*y(N-4)
* x4 x5 x6 x7 y(N-5) y(M-6) [y(N-7) y(M-8)] x4*y(N-5)
* ------------------- finalize ----------------------
* x4 x5 x6 x7 y(N-5) y(M-6) y(N-7) y(M-8) x5*y(N-6) (nothing is load)
* x4 x5 x6 x7 y(N-5) y(M-6) y(N-7) y(M-8) x6*y(N-7)
* x4 x5 x6 x7 y(N-5) y(M-6) y(N-7) y(M-8) x7*y(N-8)
*/
ldinc m0, \x1
lddec m2, \x2
ldinc m1, \x1
mula.dd.lh.lddec m3, \x2, m0, m2
loopnez \count, .loop_end_\ID
.loop_\ID:
mula.dd.hl.ldinc m0, \x1, m0, m2
mula.dd.lh.lddec m2, \x2, m1, m3
mula.dd.hl.ldinc m1, \x1, m1, m3
mula.dd.lh.lddec m3, \x2, m0, m2
.loop_end_\ID:
mula.dd.hl m0, m2
mula.dd.lh m1, m3
mula.dd.hl m1, m3
.endm // fir_s16_ae32_mul
.macro fir_s16_ae32_full x1, x2, count, full_count, ID
// This macro calculates fixed point dot product for ((count + 1)*4) int16 samples
// x1 - input array1 register (for example a2)
// x2 - input array2 register (for example a3)
// count - counter register (for example a7)
// count - samples_count / 4 - 1
// full_count - samples_count
// acc += x1[i + 0]*x2[N - i - 1] + x1[i + 1]*x2[N - i - 2] + x1[i + 2]*x2[N - i - 3] + x1[i + 3]*x2[N - i - 4]; i: 0..count
// acchi, and acclo have to be initialized before
// Result - acchi || acclo
// Modifies:
// m0, m1, m2, m3
// acchi || acclo - must be loaded before (for example 0x3fff to acclo).
// the main mac16 multiplication loop is skipped for cases with less than 4 samples
blti \full_count, 4, .less_than_4_operands_\ID
fir_s16_ae32_mul \x1, \x2, \count, \ID
.less_than_4_operands_\ID:
bbci \full_count, 1, .mod2chk_\ID
ldinc m0, \x1
lddec m2, \x2
mula.dd.hl m0, m2
mula.dd.lh m0, m2
.mod2chk_\ID:
bbci \full_count, 0, .mod1chk_\ID
ldinc m0, \x1
lddec m2, \x2
mula.dd.lh m0, m2
.mod1chk_\ID:
.endm // fir_s16_ae32_full
|
georgevio/IoT-Embedded
| 6,600
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fir/fixed/dsps_fird_s16_ae32.S
|
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_fir_platform.h"
#if (dsps_fird_s16_ae32_enabled == 1)
#include "dsps_fir_s16_m_ae32.S"
// This is FIR filter for ESP32 processor.
.text
.align 4
.global dsps_fird_s16_ae32
.type dsps_fird_s16_ae32,@function
// The function implements the following C code:
//int32_t dsps_fird_s16_ansi(fir_s16_t *fir, const int16_t *input, int16_t *output, int32_t len)
dsps_fird_s16_ae32:
// Input params Variables
//
// fir - a2 N - a6
// input - a3 pos - a7
// output - a4 rounding_lo - a8
// len - a5 d_pos - a9
// &coeffs[N] - a10
// delay - a11
// decim - a12
// rounding_hi - a13
// final_shift - a14 (shift)
entry a1, 32
l16si a7, a2, 10 // a7 - pos
l16si a6, a2, 8 // a6 - N
l32i a10, a2, 0 // a10 - coeffs
addx2 a10, a6, a10 // a10 - coeffs[N+1]
addi a10, a10, -4 // a10 - coeffs[N]
s32i a10, a1, 0 // save pointer to a1
l32i a11, a2, 4 // a11 - delay line
l16si a12, a2, 12 // a12 - decimation
l16si a9, a2, 14 // a9 - d_pos
l16si a14, a2, 16 // a14 - shift
// prepare rounding value
l32i a15, a2, 20 // get address of rounding array to a15
l32i a8, a15, 0 // a8 = lower 32 bits of the rounding value (acclo)
l32i a13, a15, 4 // a13 = higher 8 bits of the rounding value (acchi), offset 4 (32 bits)
// prepare final_shift value
addi a14, a14, -15 // shift - 15
abs a15, a14
blti a15, 32, _shift_lower_than_32_init // check if lower than 32
// greater than 32 could only be negative shift ((-40 to +40) - 15) -> -55 to +25
addi a14, a14, 32 // if greater than 32, add 32 (SRC is not defined for SAR greater than 32)
_shift_lower_than_32_init:
bltz a14, _shift_negative_init // branch if lower than zero (not including zero)
beqz a14, _shift_negative_init // branch if equal to zero (add zero to the previous statement)
ssl a14 // if positive, set SAR register to left shift value (SAR = 32 - shift)
j _end_of_shift_init
_shift_negative_init: // negative shift
abs a14, a14 // absolute value
ssr a14 // SAR = -shift
// final_shift is saved to SAR register, SAR is not being changed during the execution
_end_of_shift_init:
l16si a14, a2, 16 // a14 - load shift value
addi a14, a14, -15 // shift - 15
s32i a5, a1, 4 // save len to a1, used as the return value
// first delay line load (decim - d_pos) when d_pos is not 0
beqz a9, _fird_loop_len
sub a15, a12, a9 // a15 = decim - d_pos
loopnez a15, ._loop_d_pos
blt a7, a6, reset_fir_pos_d_pos // branch if fir->pos >= fir->N
movi.n a7, 0 // fir->pos = 0
l32i a11, a2, 4 // reset delay line to the beginning
reset_fir_pos_d_pos:
l16si a15, a3, 0 // load 16 bits from input (a3) to a15
addi a7, a7, 1 // fir->pos++
s16i a15, a11, 0 // save 16 bits from a15 to delay line (a11)
addi a3, a3, 2 // increment input pointer
addi a11, a11, 2 // increment delay line pointer
._loop_d_pos:
j .fill_delay_line // skip the first iteration of the delay line filling routine
// outer loop
_fird_loop_len:
loopnez a12, .fill_delay_line
blt a7, a6, reset_fir_pos // branch if fir->pos >= fir->N
movi.n a7, 0 // fir->pos = 0
l32i a11, a2, 4 // reset delay line to the beginning
reset_fir_pos:
l16si a15, a3, 0 // load 16 bits from input (a3) to a15
addi a7, a7, 1 // fir->pos++
s16i a15, a11, 0 // save 16 bits from a15 to delay line (a11)
addi a3, a3, 2 // increment input pointer
addi a11, a11, 2 // increment delay line pointer
.fill_delay_line:
// prepare MAC unit
wsr a8, acclo // acclo = a8
wsr a13, acchi // acchi = a13
addi a11, a11, -4 // preset delay line pointer, samples (array is being incremented)
sub a9, a6, a7 // a9 = full_count = fir->N - fir->pos
// (Count / 4) - 1
srli a15, a9, 2 // a15 = count = full_count /4
addi a10, a10, 4 // preset coeffs pointer, samples (array is being decremented)
addi a15, a15, -1 // count - 1
// x1, x2, count, full_count, ID
fir_s16_ae32_full a11, a10, a15, a9, __LINE__
l32i a10, a2, 0 // load coeffs
l32i a11, a2, 4 // reset delay line to the beginning
addx2 a10, a7, a10 // move coeffs pointer to the end
srli a15, a7, 2 // a15 = count = full_count (fir->pos) / 4
addi a11, a11, -4 // preset delay line pointer, samples (array is being incremented)
addi a15, a15, -1 // count - 1
// x1, x2, count, full_count, ID
fir_s16_ae32_full a11, a10, a15, a7, __LINE__
// SAR already set from the beginning to final_shift value
abs a15, a14 // absolute value of shift
l32i a10, a1, 0 // reset coefficient pointer
blti a15, 32, _shift_lower_than_32
rsr a9, acchi // get only higher 8 bits of the acc register
movi.n a15, 0xFF // higher 8 bits mask
and a9, a9, a15 // apply mask
srl a15, a9
j _shift_set
_shift_lower_than_32:
rsr a9, acchi // get higher 8 bits of the acc register
movi.n a11, 0xFF // higher 8 bits mask
rsr a15, acclo // get lower 32 bits of the acc register
and a9, a9, a11 // apply mask
bltz a14, _shift_negative // branch if lower than zero (if negative)
beqz a14, _shift_negative
src a15, a15, a9 // funnel shift left
j _shift_set
_shift_negative: // negative shift
src a15, a9, a15 // funnel shift right
_shift_set:
l32i a11, a2, 4 // Load initial position of the delay line
s16i a15, a4, 0 // save the shifted value to the output array (a4)
addi a5, a5, -1 // len--
addi a4, a4, 2 // increase pointer of the output array
addx2 a11, a7, a11 // p_delay[fir->pos] - (two times the fir->pos)
// counter
bnez a5, _fird_loop_len // break if a5 == 0
l32i.n a2, a1, 4 // load return value to a2
retw.n
#endif // dsps_fird_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 72,710
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fir/fixed/dsps_fird_s16_aes3.S
|
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_fir_platform.h"
// This is FIR filter for ESP32s3 processor.
.text
.align 4
.global dsps_fird_s16_aes3
.type dsps_fird_s16_aes3,@function
// The function implements the following C code:
// int32_t dsps_fird_s16_aes3(fir_s16_t *fir, const int16_t *input, int16_t *output, int32_t len)
#if (dsps_fird_s16_aes3_enabled == 1)
dsps_fird_s16_aes3:
// Input params Variables
//
// fir - a2 N - a7
// input - a3 coeffs - a8
// output - a4 delay - a9
// len - a5 rounding - a10
// final shift - a11 (div_24 constant)
// fir_pos - a12
// decim - a13
// load inputs
entry a1, 64
l16si a7, a2, 8 // a7 N
l16si a13, a2, 12 // a13 decim
l32i.n a8, a2, 0 // a8 coeffs
l32i.n a9, a2, 4 // a9 delay
l16si a12, a2, 10 // a12 fir_pos
l16si a6, a2, 14 // a6 d_pos
// check decimation and delay line length
movi a15, 0xF // modulo 16 mask
bnone a13, a15, _length_16_check // jump if decim is divisible by 16
srli a14, a15, 1 // modulo 8 mask
bnone a13, a14, _decim_8_dpos_check // jump to start_pos check if decim is divisible by 8
srli a15, a14, 1 // modulo 4 mask
bnone a13, a15, _decim_4_dpos_check // jump to start_pos check if decim is divisible by 4
srli a14, a15, 1 // modulo 2 mask
bnone a13, a14, _decim_2_dpos_check // jump to start_pos check if decim is divisible by 2
j _other_decim // jump to other decimations
// check start_pos and delay line length for the largest decim as decim_16
_length_16_check:
l16si a11, a2, 16 // get shift value
addi a14, a11, -15 // apply 16-bit final shift
neg a11, a14 // negate final_shift
bltz a11, _decim_8_dpos_check // jump if the final shift is to right
bany a7, a15, _decim_8_dpos_check // jump if fir_len (N) is not divisible by 16, but divisible by 8
beqz.n a6, _decim_16_len_16 // jump if start_pos is 0
bnone a6, a15, _decim_16_len_16 // jump to _decim_16_len_16 if start_pos is divisible by 16
j _decim_8_dpos_check
// check start_pos for the largest decim as decim_8
_decim_8_dpos_check:
movi a14, 0x7 // modulo 8 mask
beqz.n a6, _decim_8 // jump to decim_8 if start_pos is 0
bnone a6, a14, _decim_8 // jump to decim_8 if start_pos is divisible by 8
srli a15, a14, 1 // modulo 4 mask
bnone a6, a15, _decim_4 // jump to decim_4 if start_pos is divisible by 4
srli a14, a15, 1 // modulo 2 mask
bnone a6, a14, _decim_2 // jump to decim_2 if start_pos is divisible by 2
j _other_decim // jump to other decim, if start_pos is odd number
// check start_pos for the largest decim as decim_4
_decim_4_dpos_check:
beqz.n a6, _decim_4 // jump to decim_4 if start_pos is 0
bnone a6, a15, _decim_4 // jump to decim_4 if start_pos is divisible by 4
srli a14, a15, 1 // modulo 2 mask
bnone a6, a14, _decim_2 // jump to decim_2 if start_pos is divisible by 2
j _other_decim // jump to other decim, if start_pos is odd number
// check start_pos for the largest decim as decim_2
_decim_2_dpos_check:
beqz.n a6, _decim_2 // jump to decim_2 if start_pos is 0
bnone a6, a14, _decim_2 // jump to decim_2 if start_pos is divisible by 2
j _other_decim // jump to other_decim if srart_pos is odd number
// decimation and fir length divisible by 16, only right final_shift
_decim_16_len_16:
s32i.n a5, a1, 0 // save len/decim to a1, as return value
srli a13, a13, 4 // fir->decim /= 16 (set length of delay line filling loop)
// Prepare final shift value
l32i.n a10, a2, 20 // get address of rounding array to a10
l16si a15, a2, 16 // get shift value (array)
addi.n a11, a15, -15 // final_shift +15
neg a11, a11
// first delay line load ((decim - d_pos) / 16 times) when d_pos is not 0
beqz a6, main_loop_decim_16
slli a14, a13, 4 // decim * 16
sub a15, a14, a6 // a15 = decim - d_pos
srli a15, a15, 4 // a15 / 16
loopnez a15, ._loop_d_pos_decim_16
blt a12, a7, reset_fir_d_pos_decim_16 //if(fir->pos >= fir->N){
movi.n a12, 0 // fir->pos = 0
l32i.n a9, a2, 4 // reset delay line to the beginning
reset_fir_d_pos_decim_16:
ee.vld.128.ip q7, a3, 16 // load from input (a3) to q7, increase a3 pointer
ee.vst.128.ip q7, a9, 16 // save to delay_line (a9) from q7, increase a9 pointer
addi.n a12, a12, 16 // fir->pos++
ee.vld.128.ip q7, a3, 16 // load from input (a3) to q7, increase a3 pointer
ee.vst.128.ip q7, a9, 16 // save to delay_line (a9) from q7, increase a9 pointer
._loop_d_pos_decim_16:
j ._loop_fill_delay_decim_16 // skip the first iteration of the delay line filling routine
main_loop_decim_16:
// fill the delay line by the amount of fir->dec
loopnez a13, ._loop_fill_delay_decim_16
blt a12, a7, reset_fir_pos_decim_16 //if(fir->pos >= fir->N){
movi.n a12, 0 // fir->pos = 0
l32i.n a9, a2, 4 // reset delay line to the beginning
reset_fir_pos_decim_16:
ee.vld.128.ip q7, a3, 16 // load from input (a3) to q7, increase a3 pointer
ee.vst.128.ip q7, a9, 16 // save to delay_line (a9) from q7, increase a9 pointer
addi.n a12, a12, 16 // fir->pos++
ee.vld.128.ip q7, a3, 16 // load from input (a3) to q7, increase a3 pointer
ee.vst.128.ip q7, a9, 16 // save to delay_line (a9) from q7, increase a9 pointer
._loop_fill_delay_decim_16:
ee.ld.accx.ip a10, 0 // load rounding value to accx
sub a15, a7, a12 // loop_len = fir->N - fir->pos
ee.vld.128.ip q0, a8, 16 // Preload
srli a15, a15, 4 // loop_len >> 4 (loop_len / 16)
ee.vld.128.ip q1, a9, 16 // Preload
// Circular buffer loop
loopnez a15, ._loop_end_1st_circular_buff_decim_16
ee.vld.128.ip q2, a8, 16
ee.vmulas.s16.accx.ld.ip q3, a9, 16, q0, q1
ee.vld.128.ip q0, a8, 16
ee.vmulas.s16.accx.ld.ip q1, a9, 16, q2, q3
._loop_end_1st_circular_buff_decim_16:
l32i.n a9, a2, 4 // reset delay to the beginning
srli a15, a12, 4 // loop_len >> 4 (fir->pos / 16)
ee.vld.128.ip q1, a9, 16 // Preload
// Circular buffer loop
loopnez a15, ._loop_end_2nd_circular_buff_decim_16
ee.vld.128.ip q2, a8, 16
ee.vmulas.s16.accx.ld.ip q3, a9, 16, q0, q1
ee.vld.128.ip q0, a8, 16
ee.vmulas.s16.accx.ld.ip q1, a9, 16, q2, q3
._loop_end_2nd_circular_buff_decim_16:
ee.srs.accx a15, a11, 0 // shift accx register by final_shift amount (a11), save the lower 32bits to a15
l32i.n a8, a2, 0 // reset coeffs to the beginning
s16i a15, a4, 0 // save the final acc value to the output
l32i.n a9, a2, 4 // reset delay to the beginning
addi.n a5, a5, -1 // decrement length
addi.n a4, a4, 2 // increase pointer p_output++
addx2 a9, a12, a9 // p_delay[fir->pos] - (two times the fir->pos)
bnez.n a5, main_loop_decim_16
l32i.n a2, a1, 0 // load saved return value from a1 to a2
retw.n
// DECIMATION 2
_decim_2:
s32i.n a5, a1, 0 // save calculated return value to a1
l32i.n a10, a2, 20 // get address of rounding array to a10
// Prepare final shift value
l16si a15, a2, 16 // get shift value
addi.n a15, a15, -15 // final_shift -15
ssl a15 // set SAR register to left shift (even if not used)
neg a11, a15
s32i a11, a1, 4 // save final_shift value to a1
// Set delay line fill loop count
srli a13, a13, 1 // decim = decim / 2
// divide by 24 constant
movi a11, 178956971
// first delay line load ((decim - d_pos) / 2 times) when d_pos is not 0
beqz a6, main_loop_decim_2 // branch if d_pos = 0
slli a14, a13, 1 // a14 = dec * 2
sub a15, a14, a6 // a15 = decim - d_pos
srli a15, a15, 1
loopnez a15, ._loop_d_pos_decim_2
blt a12, a7, reset_fir_d_pos_decim_2 //if(fir->pos >= fir->N){
movi.n a12, 0 // fir->pos = 0
l32i.n a9, a2, 4 // reset delay line to the beginning
reset_fir_d_pos_decim_2:
l32i.n a15, a3, 0 // load 32 bits from input a3 to a15
addi.n a12, a12, 2 // fir->pos++
s32i.n a15, a9, 0 // save 32 bits from a15 to delay line a9
addi.n a3, a3, 4 // Increase pointer of the input array by 4
addi.n a9, a9, 4 // Increase pointer of the delay line by 4
._loop_d_pos_decim_2:
j ._loop_fill_delay_decim_2 // skip the first iteration of the delay line filling routine
main_loop_decim_2:
// Fill the delay line (only decim 2)
loopnez a13, ._loop_fill_delay_decim_2
blt a12, a7, reset_fir_pos_decim_2 //if(fir->pos >= fir->N){
movi.n a12, 0 // fir->pos = 0
l32i.n a9, a2, 4 // reset delay line to the beginning
reset_fir_pos_decim_2:
l32i.n a15, a3, 0 // load 32 bits from input a3 to a15
addi.n a12, a12, 2 // fir->pos++
s32i.n a15, a9, 0 // save 32 bits from a15 to delay line a9
addi.n a3, a3, 4 // Increase pointer of the input array by 4
addi.n a9, a9, 4 // Increase pointer of the delay line by 4
._loop_fill_delay_decim_2:
ee.ld.accx.ip a10, 0 // load rounding value to accx
sub a15, a7, a12 // a15 = loop_len = fir->N - fir->pos
ee.ld.128.usar.ip q0, a9, 16 // Preload from delay
muluh a14, a15, a11 // a14 = loop1_len = loop_len / 24
ee.ld.128.usar.ip q1, a9, 16
movi.n a6, 24 // Move 24 to a6
ee.vld.128.ip q3, a8, 16 // preload from coeffs
mul16s a6, a6, a14 // loop1_len * 24
ee.src.q.ld.ip q2, a9, 16, q0, q1 // preload and shift from delay
sub a6, a15, a6 // loop remiainder = a6 = loop_len - loop1_len *24
loopnez a14, ._loop_end_1st_circular_buff_decim_2
ee.vld.128.ip q4, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2 // Load from delay
ee.vld.128.ip q5, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q1, a9, 16, q1, q4, q2, q0 // Load from delay
ee.vld.128.ip q3, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q2, a9, 16, q2, q5, q0, q1 // Load from delay
._loop_end_1st_circular_buff_decim_2:
beqi a6, 16, _decim_2_1st_equal_to_16 // jump if the remainder is equal to 16
bgei a6, 16, _decim_2_1st_more_equal_to_16 // jump if the remainder is greater or equal to 16
beqi a6, 8, _decim_2_1st_equal_to_8 // jump if the remainder is equal to 8
bgei a6, 8, _decim_2_1st_more_equal_to_8 // jump if the remainder is greater or equal to 8
beqz a6, _decim_2_1st_equal_to_0 // jump if the remainder is equal to 0
bgez a6, _decim_2_1st_more_equal_to_0 // jump if the remainder is greater or equal to 0
_decim_2_1st_equal_to_16:
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q4 ,a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0 ,a9, 16, q0, q3, q1, q2
ee.vmulas.s16.accx q1, q4
j _1st_circular_buff_end_decim_2
_decim_2_1st_more_equal_to_16:
ee.vld.128.ip q4, a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q5, a8, 16
addx2 a6, a7, a9 // move delay pointer to the end, save the pointer to a6
ee.vmulas.s16.accx q1, q4 // MAC
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q2, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q0 ,a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q1, a9, 16, q2, q0 // shift by the amount of SAR_BYTE
ee.vmulas.s16.accx q2, q5
blti a12, 8, _2nd_circular_buff_end_decim_2 // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_decim_2
_decim_2_1st_equal_to_8:
ee.vmulas.s16.accx q0, q3
j _1st_circular_buff_end_decim_2
_decim_2_1st_more_equal_to_8:
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q4 , a8, 16
addx2 a6, a7, a9 // move delay pointer to the end, save the pointer to a6
ee.vmulas.s16.accx q0, q3
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q1, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q2, a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q0, a9, 16, q1, q2 // shift by the amount of SAR_BYTE
ee.vmulas.s16.accx q1, q4
blti a12, 8, _2nd_circular_buff_end_decim_2 // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_decim_2
_decim_2_1st_more_equal_to_0:
l32i.n a9, a2, 4 // reset delay to the beginning
addx2 a6, a7, a9 // move delay pointer to the end, save the pointer to a6
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q0, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q1, a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q2, a9, 16, q0, q1 // shift by amount of SAR_BYTE
ee.vmulas.s16.accx q0, q3
blti a12, 8, _2nd_circular_buff_end_decim_2 // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_decim_2
_decim_2_1st_equal_to_0:
addi a8, a8, -16 // move coeffs pointer back by 16
_1st_circular_buff_end_decim_2:
// SECOND PART OF CIRCULAR BUFFER
l32i.n a9, a2, 4 // reset delay to the beginning
muluh a14, a12, a11 // a14 = loop2_len = fir->pos / 24
movi.n a6, 24 // Move 24 to a6
ee.vld.128.ip q0, a9, 16 // Preload
ee.vld.128.ip q1, a9, 16
ee.src.q.ld.ip q2, a9, 16, q0, q1
mul16s a15, a6, a14 // loop1_len * 24
ee.vld.128.ip q3, a8, 16 // Preload
sub a6, a12, a15 // loop remiainder = a6 = fir->pos - loop1_len *24
loopnez a14, ._loop_end_2nd_circular_buff_decim_2
ee.vld.128.ip q4, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2 // Load from delay
ee.vld.128.ip q5, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q1, a9, 16, q1, q4, q2, q0 // Load from delay
ee.vld.128.ip q3, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q2, a9, 16, q2, q5, q0, q1 // Load from delay
._loop_end_2nd_circular_buff_decim_2:
bgei a6, 16, _decim_2_2nd_more_equal_to_16 // jump if the remainder is greater or equal to 16
bgei a6, 8, _decim_2_2nd_more_equal_to_8 // jump if the remainder is greater or equal to 8
bgez a6, _2nd_circular_buff_end_decim_2 // jump if the remainder is greater or equal to 0
_decim_2_2nd_more_equal_to_16:
ee.vld.128.ip q4, a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2
ee.vmulas.s16.accx q1, q4
j _2nd_circular_buff_end_decim_2
_decim_2_2nd_more_equal_to_8:
ee.vmulas.s16.accx q0, q3
_2nd_circular_buff_end_decim_2:
l32i.n a6, a1, 4 // load final shift value to a6
l32i.n a8, a2, 0 // reset coeffs to the beginning
bgez a6, _shift_right_decim_2
rur.accx_0 a9 // acc low
rur.accx_1 a14 // acc high
addi.n a5, a5, -1 // decrease counter
src a15, a9, a14 // funnel shift left, save 32bits to a15
j _shift_left_decim_2
_shift_right_decim_2:
ee.srs.accx a15, a6, 0 // shift accx register by final_shift amount (a6), save the lower 32bits to a15
addi.n a5, a5, -1 // decrease counter
_shift_left_decim_2:
s16i a15, a4, 0 // save the final acc value to the output
l32i.n a9, a2, 4 // reset delay to the beginning
addi.n a4, a4, 2 // increase pointer p_output++
addx2 a9, a12, a9 // p_delay[fir->pos] - (two times the fir->pos)
bnez.n a5, main_loop_decim_2
l32i.n a2, a1, 0 // load saved return value from a1 to a2
retw.n
// DECIMATION 4
_decim_4:
s32i.n a5, a1, 0 // save calculated return value to a1
l32i.n a10, a2, 20 // get address of rounding array to a10
// Prepare final shift value
l16si a15, a2, 16 // get shift value
addi.n a15, a15, -15 // final_shift -15
ssl a15 // set SAR register to left shift (even if not used)
neg a11, a15
s32i a11, a1, 4 // save final_shift value to a1
// Set delay line fill loop count
srli a13, a13, 2 // decim = decim / 4
// divide by 24 constant
movi a11, 178956971
// first delay line load ((decim - d_pos) / 4 times) when d_pos is not 0
beqz a6, main_loop_decim_4
slli a14, a13, 2 // decim * 4
sub a15, a14, a6 // a15 = decim - d_pos
srli a15, a15, 2
loopnez a15, ._loop_d_pos_decim_4
blt a12, a7, reset_fir_d_pos_decim_4 //if(fir->pos >= fir->N){
movi.n a12, 0 // fir->pos = 0
l32i.n a9, a2, 4 // reset delay line to the beginning
reset_fir_d_pos_decim_4:
ee.vld.l.64.ip q0, a3, 8 // load 64bits from input (a3) to lower half of q0
ee.vst.l.64.ip q0, a9, 8 // store 64bits from lower half of q0 to delay line a9
addi.n a12, a12, 4 // fir->pos++
._loop_d_pos_decim_4:
j ._loop_fill_delay_decim_4 // skip the first iteration of the delay line filling routine
main_loop_decim_4:
// Fill the delay line (only decim 4)
loopnez a13, ._loop_fill_delay_decim_4
blt a12, a7, reset_fir_pos_decim_4 //if(fir->pos >= fir->N){
movi.n a12, 0 // fir->pos = 0
l32i.n a9, a2, 4 // reset delay line to the beginning
reset_fir_pos_decim_4:
ee.vld.l.64.ip q0, a3, 8 // load 64bits from input (a3) to lower half of q0
ee.vst.l.64.ip q0, a9, 8 // store 64bits from lower half of q0 to delay line a9
addi.n a12, a12, 4 // fir->pos++
._loop_fill_delay_decim_4:
ee.ld.accx.ip a10, 0 // load rounding value to accx
sub a15, a7, a12 // a15 = loop_len = fir->N - fir->pos
ee.ld.128.usar.ip q0, a9, 16 // Preload from delay
muluh a14, a15, a11 // a14 = loop1_len = loop_len / 24
ee.ld.128.usar.ip q1, a9, 16
movi.n a6, 24 // Move 24 to a6
ee.vld.128.ip q3, a8, 16 // preload from coeffs
mul16s a6, a6, a14 // loop1_len * 24
ee.src.q.ld.ip q2, a9, 16, q0, q1 // preload and shift from delay
sub a6, a15, a6 // loop remiainder = a6 = loop_len - loop1_len *24
loopnez a14, ._loop_end_1st_circular_buff_decim_4
ee.vld.128.ip q4, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2 // Load from delay
ee.vld.128.ip q5, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q1, a9, 16, q1, q4, q2, q0 // Load from delay
ee.vld.128.ip q3, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q2, a9, 16, q2, q5, q0, q1 // Load from delay
._loop_end_1st_circular_buff_decim_4:
beqi a6, 16, _decim_4_1st_equal_to_16 // jump if the remainder is equal to 16
bgei a6, 16, _decim_4_1st_more_equal_to_16 // jump if the remainder is greater or equal to 16
beqi a6, 8, _decim_4_1st_equal_to_8 // jump if the remainder is equal to 8
bgei a6, 8, _decim_4_1st_more_equal_to_8 // jump if the remainder is greater or equal to 8
beqz a6, _decim_4_1st_equal_to_0 // jump if the remainder is equal to 0
bgez a6, _decim_4_1st_more_equal_to_0 // jump if the remainder is greater or equal to 0
_decim_4_1st_equal_to_16:
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q4 ,a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0 ,a9, 16, q0, q3, q1, q2
ee.vmulas.s16.accx q1, q4
j _1st_circular_buff_end_decim_4
_decim_4_1st_more_equal_to_16:
ee.vld.128.ip q4, a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q5, a8, 16
addx2 a6, a7, a9 // move delay pointer to the end, save the pointer to a6
ee.vmulas.s16.accx q1, q4 // MAC
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q2, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q0 ,a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q1, a9, 16, q2, q0 // shift by the amount of SAR_BYTE
ee.vmulas.s16.accx q2, q5
blti a12, 8, _2nd_circular_buff_end_decim_4 // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_decim_4
_decim_4_1st_equal_to_8:
ee.vmulas.s16.accx q0, q3
j _1st_circular_buff_end_decim_4
_decim_4_1st_more_equal_to_8:
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q4 , a8, 16
addx2 a6, a7, a9 // move delay pointer to the end, save the pointer to a6
ee.vmulas.s16.accx q0, q3
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q1, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q2, a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q0, a9, 16, q1, q2 // shift by the amount of SAR_BYTE
ee.vmulas.s16.accx q1, q4
blti a12, 8, _2nd_circular_buff_end_decim_4 // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_decim_4
_decim_4_1st_more_equal_to_0:
l32i.n a9, a2, 4 // reset delay to the beginning
addx2 a6, a7, a9 // move delay pointer to the end, save pointer to a6
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q0, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q1, a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q2, a9, 16, q0, q1 // shift by amount of SAR_BYTE
ee.vmulas.s16.accx q0, q3
blti a12, 8, _2nd_circular_buff_end_decim_4 // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_decim_4
_decim_4_1st_equal_to_0:
addi a8, a8, -16 // move coeffs pointer back by 16
_1st_circular_buff_end_decim_4:
// SECOND PART OF CIRCULAR BUFFER
l32i.n a9, a2, 4 // reset delay to the beginning
muluh a14, a12, a11 // a14 = loop2_len = fir->pos / 24
movi.n a6, 24 // Move 24 to a6
ee.vld.128.ip q0, a9, 16 // Preload
ee.vld.128.ip q1, a9, 16
ee.src.q.ld.ip q2, a9, 16, q0, q1
mul16s a15, a6, a14 // loop1_len * 24
ee.vld.128.ip q3, a8, 16 // Preload
sub a6, a12, a15 // loop remiainder = a6 = fir->pos - loop1_len *24
loopnez a14, ._loop_end_2nd_circular_buff_decim_4
ee.vld.128.ip q4, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2 // Load from delay
ee.vld.128.ip q5, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q1, a9, 16, q1, q4, q2, q0 // Load from delay
ee.vld.128.ip q3, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q2, a9, 16, q2, q5, q0, q1 // Load from delay
._loop_end_2nd_circular_buff_decim_4:
bgei a6, 16, _decim_4_2nd_more_equal_to_16 // jump if the remainder is greater or equal to 16
bgei a6, 8, _decim_4_2nd_more_equal_to_8 // jump if the remainder is greater or equal to 8
bgez a6, _2nd_circular_buff_end_decim_4 // jump if the remainder is greater or equal to 0
_decim_4_2nd_more_equal_to_16:
ee.vld.128.ip q4, a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2
ee.vmulas.s16.accx q1, q4
j _2nd_circular_buff_end_decim_4
_decim_4_2nd_more_equal_to_8:
ee.vmulas.s16.accx q0, q3
_2nd_circular_buff_end_decim_4:
l32i.n a6, a1, 4 // load final shift value to a6
l32i.n a8, a2, 0 // reset coeffs to the beginning
bgez a6, _shift_right_decim_4
rur.accx_0 a9 // acc low
rur.accx_1 a14 // acc high
addi.n a5, a5, -1 // decrease counter
src a15, a9, a14 // funnel shift left, save 32bits to a15
j _shift_left_decim_4
_shift_right_decim_4:
ee.srs.accx a15, a6, 0 // shift accx register by final_shift amount (a6), save the lower 32bits to a15
addi.n a5, a5, -1 // decrease counter
_shift_left_decim_4:
s16i a15, a4, 0 // save the final acc value to the output
l32i.n a9, a2, 4 // reset delay to the beginning
addi.n a4, a4, 2 // increase pointer p_output++
addx2 a9, a12, a9 // p_delay[fir->pos] - (two times the fir->pos)
bnez.n a5, main_loop_decim_4
l32i.n a2, a1, 0 // load saved return value from a1 to a2
retw.n
// DECIMATION 8
_decim_8:
s32i.n a5, a1, 0 // save len/decim to a1, as return value
l32i.n a10, a2, 20 // get address of rounding array to a10
// Prepare final shift value
l16si a15, a2, 16 // get shift value
addi.n a15, a15, -15 // final_shift -15
ssl a15 // set SAR register to left shift (even if not used)
neg a11, a15
s32i a11, a1, 4 // save final_shift value to a1
// Set delay line fill loop count
srli a13, a13, 3 // decim = decim / 8
// divide by 24 constant
movi a11, 178956971
// first delay line load ((decim - d_pos) / 8 times) when d_pos is not 0
beqz a6, main_loop_decim_8
slli a14, a13, 3 // decim * 8
sub a15, a14, a6 // a15 = decim - d_pos
srli a15, a15, 3 // a15 / 8
loopnez a15, ._loop_d_pos_decim_8
blt a12, a7, reset_fir_d_pos_decim_8 //if(fir->pos >= fir->N){
movi.n a12, 0 // fir->pos = 0
l32i.n a9, a2, 4 // reset delay line to the beginning
reset_fir_d_pos_decim_8:
ee.vld.128.ip q0, a3, 16 // load 64bits from input (a3) to lower half of q0
ee.vst.128.ip q0, a9, 16 // store 64bits from lower half of q0 to delay line a9
addi.n a12, a12, 8 // fir->pos++
._loop_d_pos_decim_8:
j ._loop_fill_delay_decim_8 // skip the first iteration of the delay line filling routine
main_loop_decim_8:
// Fill the delay line (only decim 8)
loopnez a13, ._loop_fill_delay_decim_8
blt a12, a7, reset_fir_pos_decim_8 //if(fir->pos >= fir->N){
movi.n a12, 0 // fir->pos = 0
l32i.n a9, a2, 4 // reset delay line to the beginning
reset_fir_pos_decim_8:
ee.vld.128.ip q0, a3, 16 // load 64bits from input (a3) to lower half of q0
ee.vst.128.ip q0, a9, 16 // store 64bits from lower half of q0 to delay line a9
addi.n a12, a12, 8 // fir->pos++
._loop_fill_delay_decim_8:
ee.ld.accx.ip a10, 0 // load rounding value to accx
sub a15, a7, a12 // a15 = loop_len = fir->N - fir->pos
ee.ld.128.usar.ip q0, a9, 16 // Preload from delay
muluh a14, a15, a11 // a14 = loop1_len = loop_len / 24
ee.ld.128.usar.ip q1, a9, 16
movi.n a6, 24 // Move 24 to a6
ee.vld.128.ip q3, a8, 16 // preload from coeffs
mul16s a6, a6, a14 // loop1_len * 24
ee.src.q.ld.ip q2, a9, 16, q0, q1 // preload and shift from delay
sub a6, a15, a6 // loop remiainder = a6 = loop_len - loop1_len *24
loopnez a14, ._loop_end_1st_circular_buff_decim_8
ee.vld.128.ip q4, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2 // Load from delay
ee.vld.128.ip q5, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q1, a9, 16, q1, q4, q2, q0 // Load from delay
ee.vld.128.ip q3, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q2, a9, 16, q2, q5, q0, q1 // Load from delay
._loop_end_1st_circular_buff_decim_8:
beqi a6, 16, _decim_8_1st_equal_to_16 // jump if the remainder is equal to 16
bgei a6, 16, _decim_8_1st_more_equal_to_16 // jump if the remainder is greater or equal to 16
beqi a6, 8, _decim_8_1st_equal_to_8 // jump if the remainder is equal to 8
bgei a6, 8, _decim_8_1st_more_equal_to_8 // jump if the remainder is greater or equal to 8
beqz a6, _decim_8_1st_equal_to_0 // jump if the remainder is equal to 0
bgez a6, _decim_8_1st_more_equal_to_0 // jump if the remainder is greater or equal to 0
_decim_8_1st_equal_to_16:
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q4 ,a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0 ,a9, 16, q0, q3, q1, q2
ee.vmulas.s16.accx q1, q4
j _1st_circular_buff_end_decim_8
_decim_8_1st_more_equal_to_16:
ee.vld.128.ip q4, a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q5, a8, 16
addx2 a6, a7, a9 // move delay pointer to the end, save the pointer to a6
ee.vmulas.s16.accx q1, q4 // MAC
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q2, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q0 ,a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q1, a9, 16, q2, q0 // shift by the amount of SAR_BYTE
ee.vmulas.s16.accx q2, q5
blti a12, 8, _2nd_circular_buff_end_decim_8 // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_decim_8
_decim_8_1st_equal_to_8:
ee.vmulas.s16.accx q0, q3
j _1st_circular_buff_end_decim_8
_decim_8_1st_more_equal_to_8:
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q4 , a8, 16
addx2 a6, a7, a9 // move delay pointer to the end, save the pointer to a6
ee.vmulas.s16.accx q0, q3
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q1, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q2, a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q0, a9, 16, q1, q2 // shift by the amount of SAR_BYTE
ee.vmulas.s16.accx q1, q4
blti a12, 8, _2nd_circular_buff_end_decim_8 // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_decim_8
_decim_8_1st_more_equal_to_0:
l32i.n a9, a2, 4 // reset delay to the beginning
addx2 a6, a7, a9 // move delay pointer to the end, save pointer to a6
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q0, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q1, a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q2, a9, 16, q0, q1 // shift by amount of SAR_BYTE
ee.vmulas.s16.accx q0, q3
blti a12, 8, _2nd_circular_buff_end_decim_8 // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_decim_8
_decim_8_1st_equal_to_0:
addi a8, a8, -16 // move coeffs pointer back by 16
_1st_circular_buff_end_decim_8:
// SECOND PART OF CIRCULAR BUFFER
rur.accx_0 a15
l32i.n a9, a2, 4 // reset delay to the beginning
muluh a14, a12, a11 // a14 = loop2_len = fir->pos / 24
movi.n a6, 24 // Move 24 to a6
ee.vld.128.ip q0, a9, 16 // Preload
ee.vld.128.ip q1, a9, 16
ee.src.q.ld.ip q2, a9, 16, q0, q1
mul16s a15, a6, a14 // loop1_len * 24
ee.vld.128.ip q3, a8, 16 // Preload
sub a6, a12, a15 // loop remiainder = a6 = fir->pos - loop1_len *24
loopnez a14, ._loop_end_2nd_circular_buff_decim_8
ee.vld.128.ip q4, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2 // Load from delay
ee.vld.128.ip q5, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q1, a9, 16, q1, q4, q2, q0 // Load from delay
ee.vld.128.ip q3, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q2, a9, 16, q2, q5, q0, q1 // Load from delay
._loop_end_2nd_circular_buff_decim_8:
bgei a6, 16, _decim_8_2nd_more_equal_to_16 // jump if the remainder is greater or equal to 16
bgei a6, 8, _decim_8_2nd_more_equal_to_8 // jump if the remainder is greater or equal to 8
bgez a6, _2nd_circular_buff_end_decim_8 // jump if the remainder is greater or equal to 0
_decim_8_2nd_more_equal_to_16:
ee.vld.128.ip q4, a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2
ee.vmulas.s16.accx q1, q4
j _2nd_circular_buff_end_decim_8
_decim_8_2nd_more_equal_to_8:
ee.vmulas.s16.accx q0, q3
_2nd_circular_buff_end_decim_8:
l32i.n a6, a1, 4 // load final shift value to a6
l32i.n a8, a2, 0 // reset coeffs to the beginning
bgez a6, _shift_right_decim_8
rur.accx_0 a9 // acc low
rur.accx_1 a14 // acc high
addi.n a5, a5, -1 // decrease counter
src a15, a9, a14 // funnel shift left, save 32bits to a15
j _shift_left_decim_8
_shift_right_decim_8:
ee.srs.accx a15, a6, 0 // shift accx register by final_shift amount (a6), save the lower 32bits to a15
addi.n a5, a5, -1 // decrease counter
_shift_left_decim_8:
s16i a15, a4, 0 // save the final acc value to the output
l32i.n a9, a2, 4 // reset delay to the beginning
addi.n a4, a4, 2 // increase pointer p_output++
addx2 a9, a12, a9 // p_delay[fir->pos] - (two times the fir->pos)
bnez.n a5, main_loop_decim_8
l32i.n a2, a1, 0 // load saved return value from a1 to a2
retw.n
// OTHER DECIMATIONS
_other_decim:
s32i.n a5, a1, 0 // save calculated return value to a1
l32i.n a10, a2, 20 // get address of rounding array to a10
// Prepare final shift value
l16si a15, a2, 16 // get shift value
addi.n a15, a15, -15 // final_shift -15
ssl a15 // set SAR register to left shift (even if not used)
neg a11, a15
s32i a11, a1, 4 // save final_shift value to a1
// divide by 24 constant
movi a11, 178956971
// first delay line load (decim - d_pos times) when d_pos is not 0
beqz a6, main_loop_other_decim
sub a15, a13, a6 // a15 = decim - d_pos
loopnez a15, ._loop_d_pos_other_decim
blt a12, a7, reset_fir_d_pos_other_decim //if(fir->pos >= fir->N){
movi.n a12, 0 // fir->pos = 0
l32i.n a9, a2, 4 // reset delay line to the beginning
reset_fir_d_pos_other_decim:
l16si a15, a3, 0 // load 16 bits from input a3 to a15
addi.n a12, a12, 1 // fir->pos++
s16i a15, a9, 0 // save 16 bits from a15 to delay line a9
addi.n a3, a3, 2 // Increase pointer of the input array by 2
addi.n a9, a9, 2 // Increase pointer of the delay line by 2
._loop_d_pos_other_decim:
j ._loop_fill_delay_other_decim // skip the first iteration of the delay line filling routine
main_loop_other_decim:
// Fill the delay line (other decims)
loopnez a13, ._loop_fill_delay_other_decim
blt a12, a7, reset_fir_pos_other_decim //if(fir->pos >= fir->N){
movi.n a12, 0 // fir->pos = 0
l32i.n a9, a2, 4 // reset delay line to the beginning
reset_fir_pos_other_decim:
l16si a15, a3, 0 // load 16 bits from input a3 to a15
addi.n a12, a12, 1 // fir->pos++
s16i a15, a9, 0 // save 16 bits from a15 to delay line a9
addi.n a3, a3, 2 // Increase pointer of the input array by 2
addi.n a9, a9, 2 // Increase pointer of the delay line by 2
._loop_fill_delay_other_decim:
ee.ld.accx.ip a10, 0 // load rounding value to accx
sub a15, a7, a12 // a15 = loop_len = fir->N - fir->pos
ee.ld.128.usar.ip q0, a9, 16 // Preload from delay
muluh a14, a15, a11 // a14 = loop1_len = loop_len / 24
ee.ld.128.usar.ip q1, a9, 16
movi.n a6, 24 // Move 24 to a6
ee.vld.128.ip q3, a8, 16 // preload from coeffs
mul16s a6, a6, a14 // loop1_len * 24
ee.src.q.ld.ip q2, a9, 16, q0, q1 // preload and shift from delay
sub a6, a15, a6 // loop remiainder = a6 = loop_len - loop1_len *24
loopnez a14, ._loop_end_1st_circular_buff_other_decim
ee.vld.128.ip q4, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2 // Load from delay
ee.vld.128.ip q5, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q1, a9, 16, q1, q4, q2, q0 // Load from delay
ee.vld.128.ip q3, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q2, a9, 16, q2, q5, q0, q1 // Load from delay
._loop_end_1st_circular_buff_other_decim:
beqi a6, 16, _other_decim_1st_equal_to_16 // jump if the remainder is equal to 16
bgei a6, 16, _other_decim_1st_more_equal_to_16 // jump if the remainder is greater or equal to 16
beqi a6, 8, _other_decim_1st_equal_to_8 // jump if the remainder is equal to 8
bgei a6, 8, _other_decim_1st_more_equal_to_8 // jump if the remainder is greater or equal to 8
beqz a6, _other_decim_1st_equal_to_0 // jump if the remainder is equal to 0
bgez a6, _other_decim_1st_more_equal_to_0 // jump if the remainder is greater or equal to 0
_other_decim_1st_equal_to_16:
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q4 ,a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0 ,a9, 16, q0, q3, q1, q2
ee.vmulas.s16.accx q1, q4
j _1st_circular_buff_end_other_decim
_other_decim_1st_more_equal_to_16:
ee.vld.128.ip q4, a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q5, a8, 16
addx2 a6, a7, a9 // move delay pointer to the end, save the pointer to a6
ee.vmulas.s16.accx q1, q4 // MAC
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q2, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q0 ,a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q1, a9, 16, q2, q0 // shift by the amount of SAR_BYTE
ee.vmulas.s16.accx q2, q5
blti a12, 8, _2nd_circular_buff_end_other_decim // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_other_decim
_other_decim_1st_equal_to_8:
ee.vmulas.s16.accx q0, q3
j _1st_circular_buff_end_other_decim
_other_decim_1st_more_equal_to_8:
l32i.n a9, a2, 4 // reset delay to the beginning
ee.vld.128.ip q4 , a8, 16
addx2 a6, a7, a9 // move delay pointer to the end, save the pointer to a6
ee.vmulas.s16.accx q0, q3
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q1, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q2, a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q0, a9, 16, q1, q2 // shift by the amount of SAR_BYTE
ee.vmulas.s16.accx q1, q4
blti a12, 8, _2nd_circular_buff_end_other_decim // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_other_decim
_other_decim_1st_more_equal_to_0:
l32i.n a9, a2, 4 // reset delay to the beginning
addx2 a6, a7, a9 // move delay pointer to the end, save pointer to a6
addi a15, a6, -16 // move pointer back by 16, save the pointer to a15
ee.vld.128.ip q0, a15, 16 // load 8 words, not modifying the SAR_BYTE, load from a15 (end of the array)
ee.vld.128.ip q1, a9, 16 // load 8 words, not modifying the SAR_BYTE, load from a9 (beginning of the array)
ee.src.q.ld.ip q2, a9, 16, q0, q1 // shift by amount of SAR_BYTE
ee.vmulas.s16.accx q0, q3
blti a12, 8, _2nd_circular_buff_end_other_decim // skip the second circular buffer if fir->pos is lower than 8
j _1st_circular_buff_end_other_decim
_other_decim_1st_equal_to_0:
addi a8, a8, -16 // move coeffs pointer back by 16
_1st_circular_buff_end_other_decim:
// SECOND PART OF CIRCULAR BUFFER
l32i.n a9, a2, 4 // reset delay to the beginning
muluh a14, a12, a11 // a14 = loop2_len = fir->pos / 24
movi.n a6, 24 // Move 24 to a6
ee.vld.128.ip q0, a9, 16 // Preload
ee.vld.128.ip q1, a9, 16
ee.src.q.ld.ip q2, a9, 16, q0, q1
mul16s a15, a6, a14 // loop1_len * 24
ee.vld.128.ip q3, a8, 16 // Preload
sub a6, a12, a15 // loop remiainder = a6 = fir->pos - loop1_len *24
loopnez a14, ._loop_end_2nd_circular_buff_other_decim
ee.vld.128.ip q4, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2 // Load from delay
ee.vld.128.ip q5, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q1, a9, 16, q1, q4, q2, q0 // Load from delay
ee.vld.128.ip q3, a8, 16 // Load from coeffs
ee.vmulas.s16.accx.ld.ip.qup q2, a9, 16, q2, q5, q0, q1 // Load from delay
._loop_end_2nd_circular_buff_other_decim:
bgei a6, 16, _other_decim_2nd_more_equal_to_16 // jump if the remainder is greater or equal to 16
bgei a6, 8, _other_decim_2nd_more_equal_to_8 // jump if the remainder is greater or equal to 8
bgez a6, _2nd_circular_buff_end_other_decim // jump if the remainder is greater or equal to 0
_other_decim_2nd_more_equal_to_16:
ee.vld.128.ip q4, a8, 16
ee.vmulas.s16.accx.ld.ip.qup q0, a9, 16, q0, q3, q1, q2
ee.vmulas.s16.accx q1, q4
j _2nd_circular_buff_end_other_decim
_other_decim_2nd_more_equal_to_8:
ee.vmulas.s16.accx q0, q3
_2nd_circular_buff_end_other_decim:
l32i.n a6, a1, 4 // load final shift value to a6
l32i.n a8, a2, 0 // reset coeffs to the beginning
bgez a6, _shift_right_other_decim
rur.accx_0 a9 // acc low
rur.accx_1 a14 // acc high
addi.n a5, a5, -1 // decrease counter
src a15, a9, a14 // funnel shift left, save 32bits to a15
j _shift_left_other_decim
_shift_right_other_decim:
ee.srs.accx a15, a6, 0 // shift accx register by final_shift amount (a6), save the lower 32bits to a15
addi.n a5, a5, -1 // decrease counter
_shift_left_other_decim:
s16i a15, a4, 0 // save the final acc value to the output
l32i.n a9, a2, 4 // reset delay to the beginning
addi.n a4, a4, 2 // increase pointer p_output++
addx2 a9, a12, a9 // p_delay[fir->pos] - (two times the fir->pos)
bnez.n a5, main_loop_other_decim
l32i.n a2, a1, 0 // load saved return value from a1 to a2
retw.n
#endif // dsps_fird_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 1,818
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/addc/float/dspm_addc_f32_ae32.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_addc_platform.h"
#if (dspm_addc_f32_ae32_enabled == 1)
// This is an add function for sub-matrices for ESP32 processor
.text
.align 4
.global dspm_addc_f32_ae32
.type dspm_addc_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_addc_f32_ansi(const float *input, float *output, float C, int rows, int cols, int padd_in, int padd_out, int step_in, int step_out);
dspm_addc_f32_ae32:
// input - a2
// output - a3
// C - a4
// rows - a5
// cols - a6
// padd_in - a7
// padd_out - a8
// step_in - a9
// step_out - a10
entry a1, 16
l32i.n a8, a1, 16 // padd_out
l32i.n a9, a1, 20 // step_in
l32i.n a10, a1, 24 // step_out
slli a9, a9, 2 // a9 - step_in << 2
slli a10, a10, 2 // a10 - step_out << 2
wfr f0, a4 // a4 - load to the f0
.outer_loop_addc_f32_ae32:
loopnez a6, .loop_addc_f32_ae32
lsxp f1, a2, a9 // load input to f1, increment input (input_ptr+=step_in)
add.s f2, f0, f1 // f2 = f0 + f1
ssxp f2, a3, a10 // save result f2 to output a3, increment output (output_ptr+=step_out)
.loop_addc_f32_ae32:
addx4 a2, a7, a2 // input1_ptr += (padd_in << 2);
addx4 a3, a8, a3 // output_ptr += (padd_out << 2);
addi.n a5, a5, -1 // rows - 1
bnez a5, .outer_loop_addc_f32_ae32
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dspm_add_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,892
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_3x3x1_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_3x3x1_f32_ae32_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_3x3x1_f32_ae32
.type dspm_mult_3x3x1_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mult_3x3x1_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_3x3x1_f32_ae32:
// A - a2
// B - a3
// C - a4
// a5 - 0
// a6 - 3
entry a1, 16
movi a5, 0
movi a6, 3
lsi f13,a3, 0 // B[0]
lsi f14,a3, 4 // B[1]
lsi f15,a3, 8 // B[2]
// addi a2, a2, -12 // To compensate first increment
loopnez a6, loop_mac_3x3x1_end_m_ae32
wfr f0, a5
lsi f2, a2, 0
madd.s f0, f2, f13
lsi f3, a2, 4
madd.s f0, f3, f14
lsi f4, a2, 8
madd.s f0, f4, f15
addi a2, a2, 12
ssi f0, a4, 0
addi a4, a4, 4
loop_mac_3x3x1_end_m_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //
|
georgevio/IoT-Embedded
| 3,043
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_f32_arp4.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_arp4_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_f32_arp4
.global .dspm_mult_f32_arp4_body
.type dspm_mult_f32_arp4,@function
// The function implements the following C code:
// esp_err_t dspm_mult_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_f32_arp4:
// A - a2: a0
// B - a3: a1
// C - a4: a2
// m - a5: a3
// n - a6: a4
// k - a7: a5
// a8:a6 = n*4
// a10:t0 = 4
// a9:a7 - counter loop1: 0..m
// a11:t1 - counter loop2: 0..k
// a12:t2 - A
// a13:t3 - B
// a14:t4
// a15:t5
add sp,sp,-16
// Array increment for floating point data should be 4
.dspm_mult_f32_arp4_body:
slli a6, a4, 2 // Pointer increment for A
slli t5,a5, 2 // Pointer increment for B
li t4, 0 // Innitial state of accumulator f1
li t0, 4 // Increment = 4
li a7, 0 // counter loop1
.dpf_loop1:
li t1, 0 // reset counter for loop2
.dpf_loop2:
// Clear initial state of the result register
// a2 - A
// a3 - B
// a6 - n
// a10 - step == 4 bytes
// a8 - step n*4
mv t2, a0 // load A
slli t3, t1, 2 // loop count to pointer value
add t3, a1, t3 // load A
fmv.w.x fa2,zero // reset fa2
// Calculating dotproduct...
esp.lp.setup 0, a4, .matrix_mul_loop
flw fa0, 0(t2)
add t2, t2, t0
flw fa1, 0(t3)
fmadd.s fa2, fa1, fa0, fa2
.matrix_mul_loop: add t3, t3, t5
fsw fa2, 0(a2)
addi a2, a2, 4 // increment a2 for next time
// check loop 2
addi t1, t1, 1 // Increment loop2 counter
blt t1, a5, .dpf_loop2
// check loop 1
add a0, a0, a6 // Increment A, A = A[i*n]
add a7, a7, 1 // Increment loop1 counter
blt a7, a3, .dpf_loop1
// Exit
mv a0, a6 // return status ESP_OK
add sp,sp,16
ret
#endif //dspm_mult_f32_arp4_enabled
|
georgevio/IoT-Embedded
| 6,777
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_ex_f32_aes3.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_aes3_enabled == 1)
// This is matrix multiplication function for ESP32S3 processor.
.text
.align 4
.global dspm_mult_ex_f32_aes3
.global .dspm_mult_ex_f32_ae32_body
.type dspm_mult_ex_f32_aes3,@function
// The function implements the following C code:
//esp_err_t dspm_mult_ex_f32_ansi(const float* A, const float* B, float* C, int A_rows, int A_cols, int B_cols, int A_padding, int B_padding, int C_padding)
//{
// const int A_step = A_cols + A_padding;
// const int B_step = B_cols + B_padding;
// const int C_step = B_cols + C_padding;
//
// for (int i = 0; i < A_rows; i++) {
// for (int j = 0; j < B_cols; j++) {
// C[i * C_step + j] = A[i * A_step] * B[j];
// for (int s = 1; s < A_cols; s++) {
// C[i * C_step + j] += A[i * A_step + s] * B[s * B_step + j];
// }
// }
// }
// return ESP_OK;
//}
// A - a2
// B - a3
// C - a4
// m - a5
// n - a6
// k - a7
// A_padd = a8
// B_padd = a9
// C_padd = a15
dspm_mult_ex_f32_aes3:
entry a1, 16
l32i.n a8, a1, 16 // A_padding
l32i.n a9, a1, 20 // B_padding
l32i.n a15, a1, 24 // C_padding
// Check if we can use S3 memory model
// Check matrices dimensions and paddings all of them must be divisible by 4
or a12, a5, a6 // a12 = m OR n
or a14, a8, a9 // a14 = A_padd OR B_padd
or a12, a12, a7 // a12 = m OR n OR k
or a14, a14, a15 // a14 = A_padd OR B_padd OR C_padd
or a12, a12, a14 // a12 = m OR n OR k OR A_padd OR B_padd OR C_padd
movi.n a11, 3 // a11 = byte mask
and a12, a12, a11 // a12 = a12 AND 3 (byte mask)
// Check alignment of A B C matrices data pointers
movi.n a11, 15 // a11 = byte mask
or a10, a3, a2 // a10 = A pointer OR B pointer
or a10, a10, a4 // a10 = A pointer OR B pointer OR C pointer
and a10, a10, a11 // a10 = a10 AND 15 (byte mask)
or a12, a12, a10 // a12 = mat_dim OR alignment
beqz a12, .s3_mmult_ex // if zero, jump to s3_mult
// Call Esp32 function
J .dspm_mult_ex_f32_ae32_body
.s3_mmult_ex:
// f0, f1, f2, f3 - multiplication result
// f4, f5, f6, f7 - input for matrix B
// f8, f9, f10,f11- input far matrix A
movi.n a14, 0 // B pointer increment for y loop
add a15, a15, a7 // a15 = k + C_padding
slli a10, a15, 2 // a10 = (K + C_padding) * 4 - step for rows
mov a15, a9 // a15 = B_padd
slli a15, a15, 2 // a15 = B_padd * 4
add a7, a7, a9 // a7 = k + B_padding
slli a12, a7, 2 // a12 = (K + B_padding) * 4 - step for rows
srli a11, a6, 2 // a11 = n / 4
addi.n a11, a11, -1 // a11 = innter loop count (n)
slli a6, a8, 2 // a6 = A_padding *4 = A_pointer step
mov a13, a3 // backup B pointer
mov a7, a4 // backup C pointer
.loop_x_mult_ex:
movi.n a9, 0 // reset loop1 counter
mov a8, a2 // move A matrix back to the beginning
.loop_y_mult_ex:
add a13, a3, a14 // Reload Y pointer to Y11 + A14
EE.LDF.128.IP f11, f10, f9, f8, a8, 16 // Load A values: X11, X12, X13, X14
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y11, Y12, Y13, Y14
mul.s f0, f4, f8 // f0 = X11*Y11
mul.s f1, f5, f8 // f1 = X12*Y11
mul.s f2, f6, f8 // f2 = X13*Y11
mul.s f3, f7, f8 // f3 = X14*Y11
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y21, Y22, Y23, Y24
madd.s f0, f4, f9 // f0 = X11*Y11 + X12*Y21
madd.s f1, f5, f9 // f1 = X11*Y12 + X12*Y22
madd.s f2, f6, f9 // f2 = X11*Y13 + X12*Y23
madd.s f3, f7, f9 // f3 = X11*Y14 + X12*Y24
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y31, Y32, Y33, Y34
madd.s f0, f4, f10 // f0 = X11*Y11 + X12*Y21 + X13*Y31
madd.s f1, f5, f10 // f1 = X11*Y12 + X12*Y22 + X13*Y32
madd.s f2, f6, f10 // f2 = X11*Y13 + X12*Y23 + X13*Y33
madd.s f3, f7, f10 // f3 = X11*Y14 + X12*Y24 + X13*Y34
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y41, Y42, Y43, Y44
madd.s f0, f4, f11 // f0 = X11*Y11 + X12*Y21 + X13*Y31 + X14*Y41
madd.s f1, f5, f11 // f1 = X11*Y12 + X12*Y22 + X13*Y32 + X14*Y42
madd.s f2, f6, f11 // f2 = X11*Y13 + X12*Y23 + X13*Y33 + X14*Y43
madd.s f3, f7, f11 // f3 = X11*Y14 + X12*Y24 + X13*Y34 + X14*Y44
loopnez a11, .iner_loop_mult_ex
EE.LDF.128.IP f11, f10, f9, f8, a8, 16 // Load A values: X15, X16, X17, X18
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y51, Y52, Y53, Y54
madd.s f0, f4, f8 // f0 += X15*Y51
madd.s f1, f5, f8 // f1 += X15*Y52
madd.s f2, f6, f8 // f2 += X15*Y53
madd.s f3, f7, f8 // f3 += X15*Y54
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y61, Y62, Y63, Y64
madd.s f0, f4, f9 // f0 += X16*Y61
madd.s f1, f5, f9 // f1 += X16*Y62
madd.s f2, f6, f9 // f2 += X16*Y63
madd.s f3, f7, f9 // f3 += X16*Y64
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y71, Y72, Y73, Y74
madd.s f0, f4, f10 // f0 =
madd.s f1, f5, f10 // f1 =
madd.s f2, f6, f10 // f2 =
madd.s f3, f7, f10 // f3 =
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y81, Y82, Y83, Y84
madd.s f0, f4, f11 // f0 =
madd.s f1, f5, f11 // f1 =
madd.s f2, f6, f11 // f2 =
madd.s f3, f7, f11 // f3 =
.iner_loop_mult_ex:
EE.STF.128.XP f3, f2, f1, f0, a4, a10 // Store result
addi.n a9, a9, 1 // Increment loop1 counter
add a8, a8, a6 // (increase A pointer by A_padding * 4 times)
blt a9, a5, .loop_y_mult_ex
addi.n a7, a7, 16 // Increase C pinter by 16
mov a4, a7
addi.n a14, a14, 16 // Increase B pointer by 16
addi.n a15, a15, 16 // Increment loop2 counter by 16
blt a15, a12, .loop_x_mult_ex
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //dspm_mult_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 4,782
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_f32_aes3.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_aes3_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_f32_aes3
.global .dspm_mult_f32_ae32_body
.type dspm_mult_f32_aes3,@function
// The function implements the following C code:
// esp_err_t dspm_mult_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_f32_aes3:
entry a1, 16
// A - a2
// B - a3
// C - a4
// m - a5
// n - a6
// k - a7
// Ccheck if we can use S3 memory model:
or a12, a5, a6
or a12, a7, a12
movi.n a11, 3
and a12, a12, a11
movi.n a11, 15
or a10, a3, a2
or a10, a10, a4
and a10, a10, a11
or a12, a12, a10
beqz a12, .s3_mmult
// Call Esp32 function
J .dspm_mult_f32_ae32_body
.s3_mmult:
// f0, f1, f2, f3 - multiplication result
// f4, f5, f6, f7 - input for matrix B
// f8, f9, f10,f11- input far matrix A
movi.n a14, 0
slli a12, a7, 2 // a12 = K*4 - step for rows
slli a10, a7, 2 // a10 = K*4 - step for rows
srli a11, a6, 2 // N count
addi.n a11, a11, -1
movi.n a15, 0
mov a13, a3
mov a7, a4
.loop_x_aes3:
movi.n a9, 0
mov a8, a2 // A matirx
.loop_y_aes3:
add a13, a3, a14 // Reload Y pointer to Y11 + A14
EE.LDF.128.IP f11, f10, f9, f8, a8, 16 // Load A values: X11, X12, X13, X14
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y11, Y12, Y13, Y14
mul.s f0, f4, f8 // f0 = X11*Y11
mul.s f1, f5, f8 // f1 = X12*Y11
mul.s f2, f6, f8 // f2 = X13*Y11
mul.s f3, f7, f8 // f3 = X14*Y11
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y21, Y22, Y23, Y24
madd.s f0, f4, f9 // f0 = X11*Y11 + X12*Y21
madd.s f1, f5, f9 // f1 = X11*Y12 + X12*Y22
madd.s f2, f6, f9 // f2 = X11*Y13 + X12*Y23
madd.s f3, f7, f9 // f3 = X11*Y14 + X12*Y24
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y31, Y32, Y33, Y34
madd.s f0, f4, f10 // f0 = X11*Y11 + X12*Y21 + X13*Y31
madd.s f1, f5, f10 // f1 = X11*Y12 + X12*Y22 + X13*Y32
madd.s f2, f6, f10 // f2 = X11*Y13 + X12*Y23 + X13*Y33
madd.s f3, f7, f10 // f3 = X11*Y14 + X12*Y24 + X13*Y34
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y41, Y42, Y43, Y44
madd.s f0, f4, f11 // f0 = X11*Y11 + X12*Y21 + X13*Y31 + X14*Y41
madd.s f1, f5, f11 // f1 = X11*Y12 + X12*Y22 + X13*Y32 + X14*Y42
madd.s f2, f6, f11 // f2 = X11*Y13 + X12*Y23 + X13*Y33 + X14*Y43
madd.s f3, f7, f11 // f3 = X11*Y14 + X12*Y24 + X13*Y34 + X14*Y44
loopnez a11, .loop_end_m_aes3
EE.LDF.128.IP f11, f10, f9, f8, a8, 16 // Load A values: X15, X16, X17, X18
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y51, Y52, Y53, Y54
madd.s f0, f4, f8 // f0 += X15*Y51
madd.s f1, f5, f8 // f1 += X15*Y52
madd.s f2, f6, f8 // f2 += X15*Y53
madd.s f3, f7, f8 // f3 += X15*Y54
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y61, Y62, Y63, Y64
madd.s f0, f4, f9 // f0 += X16*Y61
madd.s f1, f5, f9 // f1 += X16*Y62
madd.s f2, f6, f9 // f2 += X16*Y63
madd.s f3, f7, f9 // f3 += X16*Y64
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y71, Y72, Y73, Y74
madd.s f0, f4, f10 // f0 =
madd.s f1, f5, f10 // f1 =
madd.s f2, f6, f10 // f2 =
madd.s f3, f7, f10 // f3 =
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y81, Y82, Y83, Y84
madd.s f0, f4, f11 // f0 =
madd.s f1, f5, f11 // f1 =
madd.s f2, f6, f11 // f2 =
madd.s f3, f7, f11 // f3 =
.loop_end_m_aes3:
EE.STF.128.XP f3, f2, f1, f0, a4, a10 // Store result
addi a9, a9, 1 // Increment loop1 counter
blt a9, a5, .loop_y_aes3
addi.n a7, a7, 16
mov a4, a7
addi.n a14, a14, 16 // B shift for 4
addi a15, a15, 16 // Increment loop1 counter
blt a15, a12, .loop_x_aes3
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //dspm_mult_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 2,580
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_ex_f32_ae32.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_ae32_enabled == 1)
#include "dsps_dotprode_f32_m_ae32.S"
// This is matrix multiplication function for ESP32 processor.
.text
.align 4
.global dspm_mult_ex_f32_ae32
.global .dspm_mult_ex_f32_ae32_body
.type dspm_mult_ex_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dspm_mult_ex_f32_ae32(const float *A, const float *B, float *C, int m, int n, int k, int A_padd, int B_padd, int C_padd);
dspm_mult_ex_f32_ae32:
// A - a2
// B - a3
// C - a4
// m - a5
// n - a6
// k - a7
// A_padding - a14
// B_padding - a15
// C_padding - a8
// a10 = 4
// a9 - counter loop1: 0..m
// a11 - counter loop2: 0..k
// a12 - A
// a13 - B
// a4 - C
entry a1, 16
// Array increment for floating point data should be 4
.dspm_mult_ex_f32_ae32_body:
l32i.n a14, a1, 16 // A_padding
l32i.n a15, a1, 20 // B_padding
l32i.n a8, a1, 24 // C_padding
add a14, a14, a6 // A_step = A_padding + A_cols (n)
add a15, a15, a7 // B_step = B_padding + B_cols (k)
slli a15, a15, 2 // Pointer increment for B (B_step * 4)
movi.n a10, 4 // Increment = 4
movi.n a9, 0 // counter loop1
const.s f3, 0 // Innitial state of accumulator, f3 = 0
.mult_ex_loop1:
movi.n a11, 0 // reset counter for loop2
.mult_ex_loop2:
// Clear initial state of the result register
// a2 - A
// a3 - B
// a6 - n
// a10 - step == 4 bytes
mov a12, a2 // load A
addx4 a13, a11, a3 // loop count to pointer value
mov.s f1, f3 // reset f1
// Calculating dotproduct...
//dotprode_f32_ae32( x1 x2 count step1 step2)
dotprode_f32_ae32 a12, a13, a6, a10, a15;
addi.n a11, a11, 1 // Increment loop2 counter
ssip f1, a4, 4 // Store restul from f1 to memory at a4 and increment a4
// check loop 2
blt a11, a7, .mult_ex_loop2
// check loop 1
addx4 a2, a14, a2 // A += (A_step << 2)
addx4 a4, a8, a4 // output += (C_padding << 2)
addi.n a9, a9, 1 // Increment loop1 counter
blt a9, a5, .mult_ex_loop1
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //dspm_mult_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 3,319
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_ex_f32_arp4.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_arp4_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_ex_f32_arp4
.global .dspm_mult_ex_f32_arp4_body
.type dspm_mult_ex_f32_arp4,@function
// The function implements the following C code:
// esp_err_t dspm_mult_f32_ansi(const float *A, const float *B, float *C, int m, int n, int k, int A_padd, int B_padd, int C_padd)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_ex_f32_arp4:
// A - a2: a0
// B - a3: a1
// C - a4: a2
// m - a5: a3
// n - a6: a4
// k - a7: a5
// a8:a6 = n*4
// a10:t0 = 4
// a9:a7 - counter loop1: 0..m
// a11:t1 - counter loop2: 0..k
// a12:t2 - A
// a13:t3 - B
// a14:t4
// a15:t5
add sp,sp,-16
// Array increment for floating point data should be 4
.dspm_mult_ex_f32_arp4_body:
mv t5, a7
add t4, a6, a4 // A_step = A_padding + A_cols (n)
add t5, t5, a5 // B_step = B_padding + B_cols (k)
slli t5, t5, 2 // Pointer increment for B (B_step * 4)
slli t4, t4, 2 // A_step << 2
lw a6, 16(sp) // C_padding from stack
slli a6, a6, 2 // C_step << 2
li a7, 0 // counter loop1
.dpf_loop1:
li t1, 0 // reset counter for loop2
.dpf_loop2:
// Clear initial state of the result register
// a2 - A
// a3 - B
// a6 - n
// a10 - step == 4 bytes
// a8 - step n*4
mv t2, a0 // load A
slli t3, t1, 2 // loop count to pointer value
add t3, a1, t3 // load A
fmv.w.x fa2,zero // reset fa2
// Calculating dotproduct...
esp.lp.setup 0, a4, .matrix_mul_loop
flw fa0, 0(t2)
add t2, t2, 4
flw fa1, 0(t3)
fmadd.s fa2, fa1, fa0, fa2
.matrix_mul_loop: add t3, t3, t5
fsw fa2, 0(a2)
addi a2, a2, 4 // increment a2 for next time
// check loop 2
addi t1, t1, 1 // Increment loop2 counter
blt t1, a5, .dpf_loop2
// check loop 1
add a0, a0, t4 // A += (A_step << 2)
add a2, a2, a6 // output += (C_padding << 2)
add a7, a7, 1 // Increment loop1 counter
blt a7, a3, .dpf_loop1
// Exit
li a0, 0 // return status ESP_OK
add sp,sp,16
ret
#endif //dspm_mult_ex_f32_arp4_enabled
|
georgevio/IoT-Embedded
| 2,126
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_3x3x3_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_3x3x3_f32_ae32_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_3x3x3_f32_ae32
.type dspm_mult_3x3x3_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mult_3x3x1_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_3x3x3_f32_ae32:
// A - a2
// B - a3
// C - a4
// a5 - 0
// a6 - 3 - internal loop for n
// a7 - 3 - external loop for M
entry a1, 16
movi a5, 0
movi a6, 3
movi a7, 3 // loop ccount
m_loop_3x3x3:
mov a12, a2 // A
mov a14, a4 // output pointer
lsi f12, a3, 0 // B[0][0]
lsi f13, a3, 12 // B[1][0]
lsi f14, a3, 24 // B[2][0]
loopnez a6, loop_mac_3x3x3_end_m_ae32
wfr f0, a5
lsi f2, a12, 0
madd.s f0, f2, f12
lsi f3, a12, 4
madd.s f0, f3, f13
lsi f4, a12, 8
madd.s f0, f4, f14
addi a12, a12, 12
ssi f0, a14, 0
addi a14, a14, 12
loop_mac_3x3x3_end_m_ae32:
addi a3, a3, 4 // increment input pointer B
addi a4, a4, 4
addi a7, a7, -1
bnez a7, m_loop_3x3x3
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //
|
georgevio/IoT-Embedded
| 2,678
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_ae32_enabled == 1)
#include "dsps_dotprode_f32_m_ae32.S"
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_f32_ae32
.global .dspm_mult_f32_ae32_body
.type dspm_mult_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mult_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_f32_ae32:
// A - a2
// B - a3
// C - a4
// m - a5
// n - a6
// k - a7
// a8 = n*4
// a10 = 4
// a9 - counter loop1: 0..m
// a11 - counter loop2: 0..k
// a12 - A
// a13 - B
// a4 - C
entry a1, 16
// Array increment for floating point data should be 4
.dspm_mult_f32_ae32_body:
slli a8, a6, 2 // Pointer increment for A
slli a15,a7, 2 // Pointer increment for B
movi.n a14, 0 // Innitial state of accumulator f1
movi.n a10, 4 // Increment = 4
movi.n a9, 0 // counter loop1
.dpf_loop1:
movi.n a11, 0 // reset counter for loop2
.dpf_loop2:
// Clear initial state of the result register
// a2 - A
// a3 - B
// a6 - n
// a10 - step == 4 bytes
// a8 - step n*4
mov a12, a2 // load A
slli a13, a11, 2 // loop count to pointer value
add.n a13, a3, a13 // load A
wfr f1, a14 // reset f1
// Calculating dotproduct...
dotprode_f32_ae32 a12, a13, a6, a10, a15;
ssi f1, a4, 0 // Store result from f1 to memory at a4
addi a4, a4, 4 // increment a4 for next time
// check loop 2
addi a11, a11, 1 // Increment loop2 counter
blt a11, a7, .dpf_loop2
// check loop 1
add.n a2, a2, a8 // Increment A, A = A[i*n]
addi a9, a9, 1 // Increment loop1 counter
blt a9, a5, .dpf_loop1
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //dspm_mult_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,905
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_4x4x1_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_4x4x1_f32_ae32_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_4x4x1_f32_ae32
.type dspm_mult_4x4x1_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mult_3x3x1_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_4x4x1_f32_ae32:
// A - a2
// B - a3
// C - a4
// a5 - 0
// a6 - 3
entry a1, 16
movi a5, 0
movi a6, 4
lsi f12,a3, 0 // B[0]
lsi f13,a3, 4 // B[1]
lsi f14,a3, 8 // B[2]
lsi f15,a3, 12 // B[3]
loopnez a6, loop_mac_4x4x1_end_m_ae32
wfr f0, a5
lsi f2, a2, 0
madd.s f0, f2, f12
lsi f3, a2, 4
madd.s f0, f3, f13
lsi f4, a2, 8
madd.s f0, f4, f14
lsi f5, a2, 12
madd.s f0, f5, f15
addi a2, a2, 16
ssi f0, a4, 0
addi a4, a4, 4
loop_mac_4x4x1_end_m_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //
|
georgevio/IoT-Embedded
| 2,204
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_4x4x4_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_4x4x4_f32_ae32_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_4x4x4_f32_ae32
.type dspm_mult_4x4x4_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mult_3x3x1_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_4x4x4_f32_ae32:
// A - a2
// B - a3
// C - a4
// a5 - 0
// a6 - 4 - internal loop for n
// a7 - 4 - external loop for M
entry a1, 16
movi a5, 0
movi a6, 4
movi a7, 4 // loop ccount
m_loop_4x4x4:
mov a12, a2 // A
mov a14, a4 // output pointer
lsi f12, a3, 0 // B[0][0]
lsi f13, a3, 16 // B[1][0]
lsi f14, a3, 32 // B[2][0]
lsi f15, a3, 48 // B[3][0]
loopnez a6, loop_mac_4x4x4_end_m_ae32
wfr f0, a5
lsi f2, a12, 0
madd.s f0, f2, f12
lsi f3, a12, 4
madd.s f0, f3, f13
lsi f4, a12, 8
madd.s f0, f4, f14
lsi f5, a12, 12
madd.s f0, f5, f15
addi a12, a12, 16
ssi f0, a14, 0
addi a14, a14, 16
loop_mac_4x4x4_end_m_ae32:
addi a3, a3, 4 // increment input pointer B
addi a4, a4, 4
addi a7, a7, -1
bnez a7, m_loop_4x4x4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //
|
georgevio/IoT-Embedded
| 1,366
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/fixed/dspm_mult_s16_m_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro dspm_mult_s16_ae32_MxNxN
// A - a2
// B - a3
// C - a4
// m - a5
// n - a6
// k - a7
// shift - stack (a8)
movi a10, 4 // load 4 as a constant
// Check if n >=4 then acceleration is possible and
blt a6, a10, do_dotproduct
// Here we make operations one by one...
movi.n a2, 0 // return status ESP_OK
retw.n
do_dotproduct:
mov a12, a2
mov a13, a3
srli a9, a6, 2 // a9 - count/4 - 1
addi a9, a9, -1
movi.n a10, 0 // load 0 to the a10 to increment second array
dotprod_s16_ae32_full a12, a13, a9, a10, a6
/* Get accumulator */
ssr a6
rsr a2, acchi
rsr a3, acclo
src a2, a2, a3
s16i a2, a4, 0
movi.n a2, 0
movi.n a2, 0 // return status ESP_OK
retw.n
.endm // dspm_mult_s16_ae32_MxNxN
|
georgevio/IoT-Embedded
| 4,361
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/fixed/dspm_mult_s16_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_s16_ae32_enabled == 1)
#include "dsps_dotprod_s16_m_ae32.S"
#include "dspm_mult_s16_m_ae32_vector.S"
//esp_err_t dspm_mult_s16_ae32(const int16_t* A, const int16_t* B, int16_t* C, int m, int n, int k, int shift);
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_s16_ae32
.global .dspm_mult_s16_ae32_body
.type dspm_mult_s16_ae32,@function
dspm_mult_s16_ae32:
// A - a2
// B - a3
// C - a4
// m - a5 - any > 0
// n - a6 - 1,2,3, any
// k - a7 - 1, any
// shift - stack (a8)
// a14 - n*4 - pointer increment
//
entry a1, 80
// ====== process matrices when k == 1 ============
.dspm_mult_s16_ae32_body:
l32i.n a8, a1, 80 // Load shift to the a8 register
// Prepare and load round value
ssr a8 // store shift to ssa
movi a15, 0x7fff
srl a15, a15
neg a8, a8
addi a8, a8, 15
ssr a8 // store shift to ssa
movi a8, 0 // Clear a8
slli a14, a6, 1 // Pointer increment for n
movi.n a10, 2 // Increment = 2
movi.n a9, 0 // initial counter loop1
movi a12, 1
beq a7, a12, vector_mult
// We have normal path with k > 1
// a2, a3, a4 - A,B,C
// a5 - m
// a6 - n
// a7 - k
// a8 - temp
// a9 - temp
// a10- k counter
// a11- m counter
// a12- B
// a13- A
// a14 - pointer increment for n
// a15 - round value
bbsi a6, 0, even_N_samples
// ---------------- for odd N
srli a6, a6, 1 // counter a6 = a6/2. We have to do it only once
slli a7, a7, 1 // counter a7 = a7*2. We have to do it only once
// loop for M
m_loop_mmult:
movi a10, 0 // reset k loop counter
mov a13, a3 // set pointer to the first column
// loop for K
k_loop_mmult:
addi a12, a2, -4 // every loop the same start position
movi a8, 0
wsr a8, acchi
wsr a15, acclo // initialize acc with shifted round value
loopnez a6, .loop_end_mmult // loop for N
.loop_mmult:
ldinc m3, a12
l16si a8, a13, 0
add a13, a13, a7
mula.ad.ll a8, m3
l16si a8, a13, 0
add a13, a13, a7
mula.ad.lh a8, m3
.loop_end_mmult:
rsr a8, acchi
rsr a9, acclo
src a8, a8, a9
s16i a8, a4, 0
addi a4, a4, 2
// check and increment for K
addi a10, a10, 2
add a13, a3, a10 // we shift collumn
bne a10, a7, k_loop_mmult
// Check and increment for M
add a2, a2, a14 // move to the next raw
addi a5, a5, -1
bnez.n a5, m_loop_mmult
movi.n a2, 0 // return status ESP_OK
retw.n
even_N_samples:
// ---------------- for odd N
slli a7, a7, 1 // counter a7 = a7*2. We have to do it only once
// loop for M
m_loop_mmult_even:
movi a10, 0 // reset k loop counter
mov a13, a3 // set pointer to the first column
// loop for K
k_loop_mmult_even:
mov a12, a2 // every loop the same start position
movi a8, 0
wsr a8, acchi
wsr a15, acclo // initialize acc with shifted round value
loopnez a6, .loop_end_mmult_even // loop for N
.loop_mmult_even:
l16si a9, a12, 0
l16si a8, a13, 0
addi a12, a12, 2
add a13, a13, a7
mula.aa.ll a8, a9
.loop_end_mmult_even:
rsr a8, acchi
rsr a9, acclo
src a8, a8, a9
s16i a8, a4, 0
addi a4, a4, 2
// check and increment for K
addi a10, a10, 2
add a13, a3, a10 // we shift collumn
bne a10, a7, k_loop_mmult_even
// Check and increment for M
add a2, a2, a14 // move to the next raw
addi a5, a5, -1
bnez.n a5, m_loop_mmult_even
movi.n a2, 0 // return status ESP_OK
retw.n
// The path where n > 1
vector_mult:
dspm_mult_s16_m_ae32_vector;
#endif // dspm_mult_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 3,691
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/fixed/dspm_mult_s16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_s16_arp4_enabled == 1)
// This is matrix multipliction function for Risc-V processor core.
.text
.align 4
.global dspm_mult_s16_arp4
.global dspm_mult_s16_ansi
.global .dspm_mult_s16_arp4_body
.type dspm_mult_s16_arp4,@function
// The function implements the following C code:
// esp_err_t dspm_mult_f32_ansi(const int16_t *A, const int16_t *B, int16_t *C, int m, int n, int k, int shift)
// {
// int final_shift = shift - 15;
// for (int i = 0 ; i < m ; i++) {
// for (int j = 0 ; j < k ; j++) {
// // This code also could be used
// //dsps_dotprode_f32_ae32(&A[i*n],&B[j],&C[i*k + j],n,1,n);
// long long acc = 0x7fff >> shift;
// for (int s = 0; s < n ; s++) {
// acc += (int32_t)A[i * n + s] * (int32_t)B[s * k + j];
// }
// if (final_shift > 0) {
// C[i * k + j] = (acc << final_shift);
// } else {
// C[i * k + j] = (acc >> (-final_shift));
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_s16_arp4:
// A - a0
// B - a1
// C - a2
// m - a3
// n - a4
// k - a5
// shift - a6
// a7 - counter loop1: 0..m
// t1 - counter loop2: 0..k
// t0 - counter loop3: 0..n
// x25(s9) - matrix step for input2
// x24(s8) - pointer to current B
// x29(t4) - pointer to initial B
// x30(t5) - pointer to A
// x31(t6) = 2 for increment....
// x26(s10)- final_shift
or t0, a3, a4
or t0, t0, a5
andi t0, t0, 0x7
beqz t0, .dspm_mult_s16_arp4_body
j dspm_mult_s16_ansi
//ret
.dspm_mult_s16_arp4_body:
add sp,sp,-16
sw s8, 4(sp)
sw s9, 8(sp)
sw s10, 12(sp)
mv t0, a4
li a7, 0 // counter loop1
slli x25, a5, 1 // step = step*2
li x31, 2
// final_shift = shift - 15
add x26, a6, -15
.dpf_loop1: // loop for m
li t1, 0 // reset counter for loop2
mv x29, a1
.dpf_loop2: // loop for k
mv x30, a0
mv x24, x29 // load B
// Calculating dotproduct...
esp.zero.qacc // qacc = 0;
esp.vldbc.16.xp q0, x30, x31 // q0 = a[mx..mx]
esp.vld.128.xp q1, x24, x25 // q1 = b[x0..x7],
esp.lp.setup 0, t0, .matrix_mul_loop
esp.vmulas.s16.qacc.ldbc.incp q0,x30, q0,q1
.matrix_mul_loop: esp.vld.128.xp q1,x24,x25
esp.srcmb.s16.qacc q2, x26, 0 // q2 = qacc >> shift
esp.vst.128.ip q2, a2, 16 // save k0..k7
add x29,x29, 16
// check loop 2
addi t1, t1, 8 // Increment loop2 counter
blt t1, a5, .dpf_loop2
add x30, x30, -2
mv a0, x30 //
// check loop 1
add a7, a7, 1 // Increment loop1 counter
blt a7, a3, .dpf_loop1
// Exit
mv a0, a6 // return status ESP_OK
lw s10, 12(sp)
lw s9, 8(sp)
lw s8, 4(sp)
add sp,sp,16
ret
#endif //dspm_mult_s16_arp4_enabled
|
georgevio/IoT-Embedded
| 2,322
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/fixed/dspm_mult_s16_m_ae32_vector.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro dspm_mult_s16_m_ae32_vector
// m - a5 - any > 0
// n - a6 - 1,2,3, any
// k - a7 - 1, any
// Define path for n < 4
movi a7, 4
blt a6, a7, small_process_loop // jump for n < 4
srli a7, a6, 2
addi a7, a7, -1
mmultv_loop1:
wsr a8, acchi
wsr a15, acclo // initialize acc with shifted round value
// Clear initial state of the result register
// a2 - A
// a3 - B
// a4 - C
// a6 - n
// a7 - n/4 - 1
// a8 - 0
// a15- 0x7fff>>shift
mov a12, a2 // load A
mov a13, a3 // Load B
dotprod_s16_ae32_full a12, a13, a7, a6
// check loop 1
/* Get accumulator */
rsr a12, acchi
rsr a13, acclo
src a12, a12, a13
s16i a12, a4, 0
addi a4, a4, 2
add.n a2, a2, a14 // Increment A, A = A[i*n]
addi a9, a9, 1 // Increment loop1 counter
blt a9, a5, mmultv_loop1
movi.n a2, 0 // return status ESP_OK
retw.n
small_process_loop:
wsr a8, acchi
wsr a15, acclo // initialize acc with shifted round value
mov a12, a2 // load A
mov a13, a3 // Load B
addi a12, a12, -4 // To arrange fist pointer
addi a13, a13, -4 // To arrange fist pointer
bbci a6, 1, .mod2chk_short
ldinc m0, a12
ldinc m2, a13
mula.dd.hh m0, m2
mula.dd.ll m0, m2
.mod2chk_short:
bbci a6, 0, .mod1chk_short
ldinc m0, a12
ldinc m2, a13
mula.dd.ll m0, m2
.mod1chk_short:
// check loop 1
/* Get accumulator */
rsr a12, acchi
rsr a13, acclo
src a12, a12, a13
s16i a12, a4, 0
addi a4, a4, 2
add.n a2, a2, a14 // Increment A, A = A[i*n]
addi a9, a9, 1 // Increment loop1 counter
blt a9, a5, small_process_loop
movi.n a2, 0 // return status ESP_OK
retw.n
.endm // dspm_mult_s16_m_ae32_vector
|
georgevio/IoT-Embedded
| 4,887
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mul/fixed/dspm_mult_s16_aes3.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_s16_aes3_enabled == 1)
#include "dsps_dotprod_s16_m_ae32.S"
#include "dspm_mult_s16_m_ae32_vector.S"
//esp_err_t dspm_mult_s16_ae32(const int16_t* A, const int16_t* B, int16_t* C, int m, int n, int k, int shift);
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.literal_position
.literal .LC0_1_38, 32767
.literal .LC1_1_39, 16383
.global dspm_mult_s16_aes3
.global .dspm_mult_s16_ae32_body
.type dspm_mult_s16_aes3,@function
dspm_mult_s16_aes3:
entry a1,80 #
movi.n a10, 7
and a10, a10, a7
beqz a10, .dspm_mult_s16_aes3_body
// Call Esp32 function
J .dspm_mult_s16_ae32_body
.dspm_mult_s16_aes3_body:
mov.n a10,a4 # [0]
mov.n a11,a5 # [1]
l32i a5,a1,80 # [2] id:77 shift+0x0
s32i.n a3,a1,32 # [3] gra_spill_temp_0
bltz a5,.Lt_0_6146 # [4]
#.LBB3_dspm_mult_s16_aes3: # 0x13
l32r a9,.LC0_1_38 # [0]
ssr a5 # [1]
sra a9,a9 # [2]
.LBB23_dspm_mult_s16_aes3: # 0x1c
s16i a9,a1,0 # [0] id:78 round_data_64+0x0
s16i a9,a1,2 # [1] id:78 round_data_64+0x0
s16i a9,a1,4 # [2] id:78 round_data_64+0x0
s16i a9,a1,6 # [3] id:78 round_data_64+0x0
s16i a9,a1,8 # [4] id:78 round_data_64+0x0
s16i a9,a1,10 # [5] id:78 round_data_64+0x0
s16i a9,a1,12 # [6] id:78 round_data_64+0x0
s16i a9,a1,14 # [7] id:78 round_data_64+0x0
blti a11,1,.Lt_0_7426 # [0]
mov.n a13,a2 # [0]
slli a4,a7,1 # [1]
mov.n a12,a1 # [2]
l32i.n a14,a1,32 # [3] gra_spill_temp_0
movi.n a15,15 # [4]
movi.n a8,0 # [5]
slli a9,a6,1 # [6]
s32i.n a9,a1,36 # [7] gra_spill_temp_1
s32i.n a8,a1,44 # [8] gra_spill_temp_3
sub a15,a15,a5 # [9]
addi.n a8,a7,7 # [10]
movgez a8,a7,a7 # [11]
srai a8,a8,3 # [12]
s32i.n a8,a1,40 # [13] gra_spill_temp_2
slli a8,a8,4 # [14]
add.n a14,a14,a8 # [15]
.Lt_0_7938: # 0x5d
l32i.n a8,a1,40 # [0] gra_spill_temp_2
beqz.n a8,.Lt_0_8194 # [2]
l32i.n a7,a1,32 # [0] gra_spill_temp_0
mov.n a2,a13 # [1]
.Lt_0_8706: # 0x65
ee.ldqa.u16.128.ip a12,0 # [0] id:80
ee.vldbc.16.ip q1,a2,2 # [1] id:79
mov.n a3,a7 # [2]
ee.vld.128.xp q0,a3,a4 # [3] id:81
addi a7,a7,16 # [4]
blti a6,1,.Lt_0_8962 # [5]
srai a5,a6,1 # [0]
bbci a6,0,.LBB68_dspm_mult_s16_aes3 # [1]
ee.vmulas.s16.qacc.ldbc.incp q1,a2,q0,q1 # [0] id:82
ee.vld.128.xp q0,a3,a4 # [1] id:83
.LBB68_dspm_mult_s16_aes3: # 0x82
loopgtz a5,.LBB74_dspm_mult_s16_aes3 # [0]
.LBB64_dspm_mult_s16_aes3: # 0x85
ee.vld.128.xp q2,a3,a4 # [0*II+0] id:83
ee.vmulas.s16.qacc.ldbc.incp q1,a2,q0,q1 # [0*II+1] id:82
ee.vld.128.xp q0,a3,a4 # [0*II+2] id:83
ee.vmulas.s16.qacc.ldbc.incp q1,a2,q2,q1 # [0*II+3] id:82
.LBB74_dspm_mult_s16_aes3: # 0x91
.Lt_0_8962: # 0x91
mov.n a2,a13 # [0]
ee.srcmb.s16.qacc q0,a15,1 # [1]
ee.vst.128.ip q0,a10,16 # [2] id:85
bne a7,a14,.Lt_0_8706 # [3]
.Lt_0_8194: # 0x9c
l32i.n a8,a1,36 # [0] gra_spill_temp_1
l32i.n a9,a1,44 # [1] gra_spill_temp_3
add.n a13,a13,a8 # [2]
addi.n a9,a9,1 # [3]
s32i.n a9,a1,44 # [4] gra_spill_temp_3
bne a11,a9,.Lt_0_7938 # [5]
.Lt_0_7426: # 0xa9
movi.n a2,0 # [0]
retw.n # [1]
.Lt_0_6146: # 0xad
l32r a9,.LC1_1_39 # [0]
ssr a5 # [1]
sra a9,a9 # [2]
j .LBB23_dspm_mult_s16_aes3 # [3]
#endif // dspm_mult_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 1,818
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/mulc/float/dspm_mulc_f32_ae32.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_mulc_platform.h"
#if (dspm_mulc_f32_ae32_enabled == 1)
// This is a mul function for sub-matrices for ESP32 processor
.text
.align 4
.global dspm_mulc_f32_ae32
.type dspm_mulc_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mulc_f32_ansi(const float *input, float *output, float C, int rows, int cols, int padd_in, int padd_out, int step_in, int step_out);
dspm_mulc_f32_ae32:
// input - a2
// output - a3
// C - a4
// rows - a5
// cols - a6
// padd_in - a7
// padd_out - a8
// step_in - a9
// step_out - a10
entry a1, 16
l32i.n a8, a1, 16 // padd_out
l32i.n a9, a1, 20 // step_in
l32i.n a10, a1, 24 // step_out
slli a9, a9, 2 // a9 - step_in << 2
slli a10, a10, 2 // a10 - step_out << 2
wfr f0, a4 // a4 - load to the f0
.outer_loop_mulc_f32_ae32:
loopnez a6, .loop_mulc_f32_ae32
lsxp f1, a2, a9 // load input to f1, increment input (input_ptr+=step_in)
mul.s f2, f0, f1 // f2 = f0 * f1
ssxp f2, a3, a10 // save result f2 to output a3, increment output (output_ptr+=step_out)
.loop_mulc_f32_ae32:
addx4 a2, a7, a2 // input1_ptr += (padd_in << 2);
addx4 a3, a8, a3 // output_ptr += (padd_out << 2);
addi.n a5, a5, -1 // rows - 1
bnez a5, .outer_loop_mulc_f32_ae32
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dspm_mulc_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,133
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/sub/float/dspm_sub_f32_ae32.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_sub_platform.h"
#if (dspm_sub_f32_ae32_enabled == 1)
// This is an sub function for sub-matrices for ESP32 processor
.text
.align 4
.global dspm_sub_f32_ae32
.type dspm_sub_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_sub_f32_ansi(const float *input1, const float *input2, float *output, int rows, int cols, int padd1, int padd2, int padd_out, int step1, int step2, int step_out);
dspm_sub_f32_ae32:
// input1 - a2
// input2 - a3
// output - a4
// rows - a5
// cols - a6
// padd1 - a7
// padd2 - a8
// padd_out - a9
// step1 - a10
// step2 - a11
// step_out - a12
entry a1, 16
l32i.n a8, a1, 16 // padd2
l32i.n a9, a1, 20 // padd_out
l32i.n a10, a1, 24 // step1
l32i.n a11, a1, 24 // step2
l32i.n a12, a1, 24 // step_out
slli a10, a10, 2 // a10 - step1 << 2
slli a11, a11, 2 // a11 - step2 << 2
slli a12, a12, 2 // a12 - step_out << 2
.outer_loop_sub_f32_ae32:
loopnez a6, .loop_sub_f32_ae32
lsxp f0, a2, a10 // load input1 to f0, increment input1 (input1_ptr+=step1)
lsxp f1, a3, a11 // load input2 to f1, increment input2 (input2_ptr+=step2)
sub.s f2, f0, f1 // f2 = f0 - f1
ssxp f2, a4, a12 // save result f2 to output a4, increment output (output_ptr+=step_out)
.loop_sub_f32_ae32:
addx4 a3, a8, a3 // input2_ptr += (padd2 << 2);
addx4 a2, a7, a2 // input1_ptr += (padd1 << 2);
addx4 a4, a9, a4 // output_ptr += (padd_out << 2);
addi.n a5, a5, -1 // rows - 1
bnez a5, .outer_loop_sub_f32_ae32
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dspm_sub_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,133
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/matrix/add/float/dspm_add_f32_ae32.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_add_platform.h"
#if (dspm_add_f32_ae32_enabled == 1)
// This is an add function for sub-matrices for ESP32 processor
.text
.align 4
.global dspm_add_f32_ae32
.type dspm_add_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_add_f32_ansi(const float *input1, const float *input2, float *output, int rows, int cols, int padd1, int padd2, int padd_out, int step1, int step2, int step_out);
dspm_add_f32_ae32:
// input1 - a2
// input2 - a3
// output - a4
// rows - a5
// cols - a6
// padd1 - a7
// padd2 - a8
// padd_out - a9
// step1 - a10
// step2 - a11
// step_out - a12
entry a1, 16
l32i.n a8, a1, 16 // padd2
l32i.n a9, a1, 20 // padd_out
l32i.n a10, a1, 24 // step1
l32i.n a11, a1, 24 // step2
l32i.n a12, a1, 24 // step_out
slli a10, a10, 2 // a10 - step1 << 2
slli a11, a11, 2 // a11 - step2 << 2
slli a12, a12, 2 // a12 - step_out << 2
.outer_loop_add_f32_ae32:
loopnez a6, .loop_add_f32_ae32
lsxp f0, a2, a10 // load input1 to f0, increment input1 (input1_ptr+=step1)
lsxp f1, a3, a11 // load input2 to f1, increment input2 (input2_ptr+=step2)
add.s f2, f0, f1 // f2 = f0 + f1
ssxp f2, a4, a12 // save result f2 to output a4, increment output (output_ptr+=step_out)
.loop_add_f32_ae32:
addx4 a3, a8, a3 // input2_ptr += (padd2 << 2);
addx4 a2, a7, a2 // input1_ptr += (padd1 << 2);
addx4 a4, a9, a4 // output_ptr += (padd_out << 2);
addi.n a5, a5, -1 // rows - 1
bnez a5, .outer_loop_add_f32_ae32
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dspm_add_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 5,412
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/support/cplx_gen/dsps_cplx_gen.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_cplx_gen_platform.h"
#if (dsps_cplx_gen_aes3_enbled || dsps_cplx_gen_ae32_enbled)
// This is a Complex signal generator for ESP32 processor.
.text
.align 4
.global dsps_cplx_gen_ae32
.type dsps_cplx_gen_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_cplx_gen_ae32(cplx_sig_t *cplx_gen, void *output, int32_t len);
dsps_cplx_gen_ae32:
// Input params Variables float Variables fixed
//
// cplx_gen - a2 fr - f0 lut - a5
// output - a3 one_const - f1 lut_len - a6
// len - a4 lut_len_f - f2 sin_pos - a7
// ph_f - f3 cos_pos - a8
// sin_pos_f - f4 sin_to_cos - a9
// ph_floor - a10
// modulo - a11
entry a1, 32
l32i a5, a2, 0 // a5 - lut
l32i a6, a2, 4 // a6 - lut_len
lsi f0, a2, 8 // f0 - fr
lsi f3, a2, 12 // f3 - ph_f (phase increment)
const.s f1, 1 // f1 - constant 1
float.s f2, a6, 0 // f2 - lut_len_f
srli a9, a6, 2 // a9 - sin_to_cos = lut_len / 4
addi a11, a6, -1 // a11 - modulo = lut_len - 1
l32i a15, a2, 16 // a15 - d_type
beqz a15, _s16_fixed
// F32 floating point
loopnez a4, ._main_loop_float
floor.s a10, f3, 0 // turncate wiht rounding towards -infinity
// branch if ph_floor is greater than 0
bgez a10, _ph_check_low_float
add.s f3, f3, f1 // f3 = f3 - f1 (ph_f + 1)
floor.s a10, f3, 0 // turncate wiht rounding towards -infinity
_ph_check_low_float:
// branch if ph_ceil is lower than 2 (floored to 1)
blti a10, 1, _ph_check_great_float
sub.s f3, f3, f1 // f3 = f3 - f1 (ph_f - 1)
_ph_check_great_float:
mul.s f4, f3, f2 // sin_pos_f = ph_f * lut_len
trunc.s a7, f4, 0 // truncate sin_pos_f to sin_pos
add a8, a7, a9 // cos_pos (a8) = sin_pos(a7) + sin_to_cos(a9)
and a8, a8, a11 // cos_pos = cos_pos & modulo (lut_len - 1)
slli a8, a8, 2 // set index of the LUT (4 x cos_pos)
slli a7, a7, 2 // set index of the LUT (4 x sin_pos)
lsx f14, a5, a7 // load sin LUT value form *lut
lsx f15, a5, a8 // load cos LUT value form *lut
ssi f15, a3, 0 // save cos LUT value to the output, offset 0
ssi f14, a3, 4 // save sin LUT value to the output, offset 4
add.s f3, f3, f0 // ph_f += fr
addi.n a3, a3, 8 // increase the output pointer (2 x f32)
._main_loop_float:
movi.n a2, 0
retw.n
// Q15 fixed point
_s16_fixed:
loopnez a4, ._main_loop_fixed
floor.s a10, f3, 0 // turncate wiht rounding towards -infinity
// branch if ph_floor is greater than 0
bgez a10, _ph_check_low_fixed
add.s f3, f3, f1 // f3 = f3 - f1 (ph_f + 1)
floor.s a10, f3, 0 // turncate wiht rounding towards -infinity
_ph_check_low_fixed:
// branch if ph_ceil is lower than 2 (floored to 1)
blti a10, 1, _ph_check_great_fixed
sub.s f3, f3, f1 // f3 = f3 - f1 (ph_f - 1)
_ph_check_great_fixed:
mul.s f4, f3, f2 // sin_pos_f = ph_f * lut_len
trunc.s a7, f4, 0 // truncate sin_pos_f to sin_pos
add a8, a7, a9 // cos_pos (a8) = sin_pos(a7) + sin_to_cos(a9)
and a8, a8, a11 // cos_pos = cos_pos & modulo (lut_len - 1)
addx2 a15, a8, a5 // get cos index of the LUT (*lut + 2 x cos_pos)
addx2 a13, a7, a5 // get sin index of the LUT (*lut + 2 x sin_pos)
l16si a14, a15, 0 // load cos LUT value from *lut
l16si a12, a13, 0 // load sin LUT value from *lut
s16i a14, a3, 0 // save cos LUT value to the output (a3), offset 0
s16i a12, a3, 2 // save sin LUT value to the output (a3), offset 2
add.s f3, f3, f0 // ph_f += fr
addi.n a3, a3, 4 // increase the output pointer (2 x s16)
._main_loop_fixed:
movi.n a2, 0
retw.n
#endif // (dsps_cplx_gen_aes3_enbled || dsps_cplx_gen_ae32_enbled)
|
georgevio/IoT-Embedded
| 13,626
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/support/mem/esp32s3/dsps_memset_aes3.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_mem_platform.h"
#if dsps_mem_aes3_enbled
// This is memory access for ESP32S3 processor.
.text
.align 4
.global dsps_memset_aes3
.type dsps_memset_aes3,@function
// The function implements the following C code:
// void *dsps_memset_aes3(void *arr_dest, uint8_t set_val, size_t set_size);
// Input params Variables
//
// arr_dest - a2 loop_len - a5
// set_val - a3 p_arr_dest - a8
// set_size - a4 8_bit_set - a7
// 16_bit_set - a9
// 32_bit_set - a10
// align_mask - a11
/*
esp32s3 optimized memset function works with both, aligned and unaligned data.
arr_dest aligned - _main_loop, 16 bytes in one loop, only aligned data
- Check modulos to finish copying remaining data outside of the cycle
- Modulo 8 - S3 instruction for aligned data, the rest of the modulos are generic
arr_dest unaligned - First, use generic instructions to align the arr_dest data (keep increasing
the arr_dest pointer until the pointer is aligned)
- Once arr_dest is aligned treat the rest of the data as aligned, same as above
if the set_size is less than 16, jump to _less_than_16 label and set data without any s3 instructions or cycles
*/
#define MEMSET_OPTIMIZED 1 // Use optimized memset or ansi memset
#define TIE_ENABLE 0 // Put a dummy TIE instruction to ANSI memset to induce TIE context saving
dsps_memset_aes3:
#if MEMSET_OPTIMIZED
entry a1, 32
mov a8, a2 // a8 - save arr_dest pointer
blti a4, 16, _less_than_16 // set_size shorter than 16
movi.n a7, 0xff // 0xff one-byte mask
movi.n a11, 0xf // 0xf alignment mask
and a7, a7, a3 // mask upper 24 bits of set_val a3
bnez.n a7, _non_zero_constant
ee.zero.q q0 // initialize q0 to zero
movi.n a9, 0 // initialize (16_bit_set) a9 to zero
movi.n a10, 0 // initialize (32_bit_set) a10 to zero
j _q_reg_prepared
_non_zero_constant:
// Fill q register
slli a6, a7, 8 // a6 - (masked)set_val << 8
or a9, a6, a7 // a9 - (masked)set_val << 8 + (masked)set_val
// a9 - 16-bit set
slli a15, a9, 16 // a15 - a9 << 16
or a10, a9, a15 // broadcast 8 bits from set_val a3 to 32 bits
// a10 - 32-bit set
ee.movi.32.q q0, a10, 0 // fill q0 register from a10 by 32 bits
ee.movi.32.q q0, a10, 1
ee.movi.32.q q0, a10, 2
ee.movi.32.q q0, a10, 3
_q_reg_prepared:
// alignment check
and a15, a11, a2 // 0xf (alignment mask) AND arr_dest pointer
beqz a15, _arr_dest_aligned // branch if a15 equals to zero
movi.n a14, 16 // a14 - 16
sub a15, a14, a15 // a15 = 16 - unalignment
sub a4, a4, a15 // len = len - (16 - unalignment)
// keep setting until arr_dest is aligned
// Check modulo 8 of the unalignment, if - then set 8 bytes
bbci a15, 3, _aligning_mod_8_check // branch if 3-rd bit of unalignment a15 is clear
s32i.n a10, a2, 0 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
s32i.n a10, a2, 4 // save 32 bits from a10 to arr_dest a2, offset 4 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 8 bytes
_aligning_mod_8_check:
// Check modulo 4 of the unalignment, if - then set 4 bytes
bbci a15, 2, _aligning_mod_4_check // branch if 2-nd bit unalignment a15 is clear
s32i.n a10, a2, 0 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_aligning_mod_4_check:
// Check modulo 2 of the unalignment, if - then set 2 bytes
bbci a15, 1, _aligning_mod_2_check // branch if 1-st bit unalignment a15 is clear
s16i a9, a2, 0 // save 16 bits from a9 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_aligning_mod_2_check:
// Check modulo 1 of the unalignment, if - then copy 1 byte
bbci a15, 0, _arr_dest_aligned // branch if 0-th bit unalignment a15 is clear
s8i a7, a2, 0 // save 8 bits from a7 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 1 // increment arr_dest pointer by 1 byte
_arr_dest_aligned:
// Calculate main loop_len
srli a5, a4, 4 // a5 - loop_len = set_size / 16
// Main loop
loopnez a5, ._main_loop // 16 bytes in one loop
ee.vst.128.ip q0, a2, 16 // store 16 bytes from q0 to arr_dest a2
._main_loop:
// Check modulo 8 of the set_size, if - then set 8 bytes
bbci a4, 3, _aligned_mod_8_check // branch if 3-rd bit of set_size a4 is clear
ee.vst.l.64.ip q0, a2, 8 // save lower 64 bits from q0 to arr_dest a2, increase arr_dest pointer by 8 bytes
_aligned_mod_8_check:
// Check modulo 4 of the set_size, if - then set 4 bytes
bbci a4, 2, _aligned_mod_4_check // branch if 2-nd bit of set_size a4 is clear
s32i.n a10, a2, 0 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_aligned_mod_4_check:
// Check modulo 2 of the set_size, if - then set 2 bytes
bbci a4, 1, _aligned_mod_2_check // branch if 1-st bit of set_size a4 is clear
s16i a9, a2, 0 // save 16 bits from a9 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_aligned_mod_2_check:
// Check modulo 1 of the set_size, if - then set 1 byte
bbci a4, 0, _aligned_mod_1_check // branch if 0-th bit of set_size a4 is clear
s8i a7, a2, 0 // save 8 bits from a7 to arr_dest a2, offset 0 bytes
_aligned_mod_1_check:
mov a2, a8 // copy the initial arr_dest pointer from a8 to arr_dest a2
retw.n // return
_less_than_16:
// make 16-byte set_val
slli a6, a3, 8 // a6 - a3 (set_val) << 8
or a7, a6, a3 // a7 - a3 (set_val) << 8 + a3 (set_val)
// Check modulo 8 of the set_size, if - then set 8 bytes
bbci a4, 3, _less_than_16_mod_8_check // branch if 3-rd bit of set_size a4 is clear
s16i a7, a2, 0 // save 16 bits from a7 to arr_dest a2, offset 0 bytes
s16i a7, a2, 2 // save 16 bits from a7 to arr_dest a2, offset 2 bytes
s16i a7, a2, 4 // save 16 bits from a7 to arr_dest a2, offset 4 bytes
s16i a7, a2, 6 // save 16 bits from a7 to arr_dest a2, offset 6 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 8 bytes
_less_than_16_mod_8_check:
// Check modulo 4 of the set_size, if - then set 4 bytes
bbci a4, 2, _less_than_16_mod_4_check // branch if 2-nd bit of set_size a4 is clear
s16i a7, a2, 0 // save 16 bits from a7 to arr_dest a2, offset 0 bytes
s16i a7, a2, 2 // save 16 bits from a7 to arr_dest a2, offset 2 bytes
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_less_than_16_mod_4_check:
// Check modulo 2 of the set_size, if - then set 2 bytes
bbci a4, 1, _less_than_16_mod_2_check // branch if 1-st bit of set_size a4 is clear
s16i a7, a2, 0 // save 16 bits from a7 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_less_than_16_mod_2_check:
// Check modulo 1 of the set_size, if - then set 1 byte
bbci a4, 0, _less_than_16_mod_1_check // branch if 0-th bit of set_size a4 is clear
s8i a3, a2, 0 // save 8 bits from a3 to arr_dest a2, offset 0 bytes
_less_than_16_mod_1_check:
mov a2, a8 // copy the initial arr_dest pointer from a8 to arr_dest a2
retw.n // return
#else // MEMSET_OPTIMIZED
// ansi version of the memset (without TIE instructions) for testing purposes
entry a1, 32
mov a8, a2 // a8 - save arr_dest pointer
movi.n a7, 0xff // 0xff one-byte mask
and a7, a7, a3 // mask upper 24 bits of a3
slli a6, a7, 8 // a6 - (masked)set_val << 8
or a9, a6, a7 // a9 - (masked)set_val << 8 + (masked)set_val
// a9 - 16-bit set
slli a15, a9, 16 // a15 - a9 << 16
or a10, a9, a15 // broadcast 8 bits from a3 to 32 bits
srli a5, a4, 4 // a5 - loop_len = arr_len / 16
// Run main loop which sets 16 bytes in one loop run
loopnez a5, ._ansi_loop
s32i.n a10, a2, 0 // save 32 bits from a15 to arr_dest a2
s32i.n a10, a2, 4 // save 32 bits from a14 to arr_dest a2
s32i.n a10, a2, 8 // save 32 bits from a14 to arr_dest a2
s32i.n a10, a2, 12 // save 32 bits from a14 to arr_dest a2
addi.n a2, a2, 16 // increment arr_dest pointer by 8 bytes
._ansi_loop:
// Finish the remaining bytes out of the loop
// Check modulo 8 of the arr_len, if - then set 8 bytes
bbci a4, 3, _mod_8_check // branch if 2-nd bit of arr_len is clear
s32i.n a10, a2, 0 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
s32i.n a10, a2, 4 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 4 bytes
_mod_8_check:
// Check modulo 4 of the arr_len, if - then set 4 bytes
bbci a4, 2, _mod_4_check // branch if 2-nd bit of arr_len is clear
s32i.n a10, a2, 0 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_mod_4_check:
// Check modulo 2 of the arr_len, if - then set 2 bytes
bbci a4, 1, _mod_2_check // branch if 1-st bit of arr_len is clear
s16i a9, a2, 0 // save 16 bits from a7 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_mod_2_check:
// Check modulo 1 of the arr_len, if - then set 1 byte
bbci a4, 0, _mod_1_check // branch if 0-th bit of arr_len is clear
s8i a7, a2, 0 // save 8 bits from a3 to arr_dest a2, offset 0 bytes
_mod_1_check:
// if arr_len is shorter than 16, skip adding TIE instruction, to fix the panic handler before the main_app() loads
blti a4, 16, _less_than_16_1 // set_size shorter than 16, to fix panic handler before main_app() load
#if TIE_ENABLE // put dummy TIE instruction to induce TIE context saving
ee.zero.qacc // initialize q0 to zero
#else // TIE_ENABLE
nop // compensate one cycle, when TIE is disabled to get the same benchmark value
#endif // TIE_ENABLE
_less_than_16_1:
mov a2, a8 // copy the initial arr_dest pointer from a8 to arr_dest a2
retw.n // return
#endif // MEMSET_OPTIMIZED
#endif // dsps_mem_aes3_enbled
|
georgevio/IoT-Embedded
| 20,165
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/support/mem/esp32s3/dsps_memcpy_aes3.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_mem_platform.h"
#if dsps_mem_aes3_enbled
// This is memory access for ESP32S3 processor.
.text
.align 4
.global dsps_memcpy_aes3
.type dsps_memcpy_aes3,@function
// The function implements the following C code:
// void *dsps_memcpy_aes3(void *arr_dest, const void *arr_src, size_t arr_len);
// Input params Variables
//
// arr_dest - a2 loop_len - a5, a6
// arr_src - a3 p_arr_des - a7
// arr_len - a4 div_48 - a8
// align_mask - a9
/*
esp32s3 optimized memcpy function works with both, aligned and unaligned data.
arr_dest aligned --> - _main_loop_aligned, 32 bytes in one run through the cycle, only aligned data
arr_src aligned / - Check modulos to finish copying the remaining data outside of the cycle
- Modulo 8 and 16 - S3 instructions for aligned data, the rest of the modulos are generic
arr_dest aligned ---> - _main_loop_unaligned, 48 bytes of source unaligned data in one run through the cycle,
arr_src unaligned / (the destination must always be aligned)
- Check modulos to finish copying remaining data outside of the cycle
- Modulo 32 and 16 - S3 instructions for unaligned data, the rest of the modulos are generic
arr_dest unaligned -> - First, use generic instructions to align the arr_dest data (keep increasing
arr_src aligned / the arr_dest pointer until the pointer is aligned)
- Once arr_dest is aligned treat the rest of the data as:
either both aligned (if arr_src happens to be aligned after the arr_dest aligning),
or as arr_dest aligned and arr_src unaligned
- Continue as mentioned above
arr_dest unaligned -> - Very same approach as with arr_dest unaligned and arr_src aligned
arr_src unaligned /
if the arr_len is less than 16, jump to _less_than_16 label and copy data without any s3 instructions or cycles
*/
#define MEMCPY_OPTIMIZED 1 // Use optimized memcpy or ANSI memcpy
#define TIE_ENABLE 0 // Put a dummy TIE instruction to the ANSI memcpy to induce TIE context saving
dsps_memcpy_aes3:
#if MEMCPY_OPTIMIZED
// S3 optimized version of the memcpy (with TIE instrucstions)
entry a1, 32
mov a7, a2 // a7 - save arr_dest pointer
blti a4, 16, _less_than_16
// arr_dest alignment check
movi.n a9, 0xf // 0xf alignment mask
and a13, a9, a2 // 0xf AND arr_dest pointer
beqz a13, _arr_dest_aligned
movi.n a14, 16 // a14 - 16
sub a13, a14, a13 // a13 = 16 - unalignment
sub a4, a4, a13 // len = len - (16 - unalignment)
// Aligning the arr_dest
// keep copying until arr_dest is aligned
// Check modulo 8 of the unalignment, if - then copy 8 bytes
bbci a13, 3, _aligning_mod_8_check // branch if 3-rd bit of unalignment a13 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15, offset 0
l32i.n a14, a3, 4 // load 32 bits from arr_src a3 to a14, offset 4
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2, offset 0
s32i.n a14, a2, 4 // save 32 bits from a14 to arr_dest a2, offset 4
addi.n a3, a3, 8 // increment arr_src pointer by 8 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 8 bytes
_aligning_mod_8_check:
// Check modulo 4 of the unalignment, if - then copy 4 bytes
bbci a13, 2, _aligning_mod_4_check // branch if 2-nd bit of unalignment a13 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
addi.n a3, a3, 4 // increment arr_src pointer by 4 bytes
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_aligning_mod_4_check:
// Check modulo 2 of the unalignment, if - then copy 2 bytes
bbci a13, 1, _aligning_mod_2_check // branch if 1-st bit of unalignment a13 is clear
l16ui a15, a3, 0 // load 16 bits from arr_src a3 to a15
addi.n a3, a3, 2 // increment arr_src pointer by 2 bytes
s16i a15, a2, 0 // save 16 bits from a15 to arr_dest a2
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_aligning_mod_2_check:
// Check modulo 1 of the unalignment, if - then copy 1 byte
bbci a13, 0, _arr_dest_aligned // branch if 0-th bit of unalignment a13 is clear
l8ui a15, a3, 0 // load 8 bits from arr_src a3 to a15
addi.n a3, a3, 1 // increment arr_src pointer by 1 byte
s8i a15, a2, 0 // save 8 bits from a15 to arr_dest a2
addi.n a2, a2, 1 // increment arr_dest pointer by 1 byte
_arr_dest_aligned:
// arr_src alignment check
and a15, a9, a3 // 0xf (alignment mask) AND arr_src pointer
beqz a15, _arr_src_aligned
// arr_src unaligned, arr_dest aligned (arr_des either aligned originally or modified to be aligned by the Aligning the arr_des routine)
// Calculate modulo for non-aligned data
movi a8, 89478486 // a8 - div_48 constant
muluh a5, a8, a4 // a5 - loop_len = arr_len / 48
movi a9, 48 // a9 - 48
mul16s a8, a9, a5 // a8 - 48 * loop_len
sub a6, a4, a8 // a6 - loop_len_MOD 48
ee.ld.128.usar.ip q2, a3, 16 // Preload from arr_src
ee.ld.128.usar.ip q3, a3, 16 // Preload from arr_src
// Main loop arr_src unaligned
loopnez a5, ._main_loop_unaligned // 48 bytes in one loop
ee.src.q.ld.ip q4, a3, 16, q2, q3 // preload and shift from arr_src
ee.vst.128.ip q2, a2, 16 // store to aligned arr_dest
ee.src.q.ld.ip q2, a3, 16, q3, q4 // preload and shift from arr_src
ee.vst.128.ip q3, a2, 16 // store to aligned arr_dest
ee.src.q.ld.ip q3, a3, 16, q4, q2 // preload and shift from arr_src
ee.vst.128.ip q4, a2, 16 // store to aligned arr_dest
._main_loop_unaligned:
// Finish the _main_loop_unaligned outside of the loop from Q registers preloads
// Check modulo 32 of the loop_len_MOD, if - then copy 32 bytes
bbci a6, 5, _unaligned_mod_32_check // branch if 5-th bit of loop_len_MOD a6 is clear
ee.src.q.ld.ip q4, a3, 0, q2, q3 // preload and shift from arr_src
ee.vst.128.ip q2, a2, 16 // store to aligned arr_dest
ee.src.q q3, q3, q4 // final shift
ee.vst.128.ip q3, a2, 16 // store to aligned arr_dest
j _follow_unaligned
_unaligned_mod_32_check:
// Check modulo 16 of the loop_len_MOD, if - then copy 16 bytes
bbci a6, 4, _unaligned_mod_16_check // branch if 4-th bit of loop_len_MOD a6 is clear
ee.src.q q2, q2, q3 // final shift
ee.vst.128.ip q2, a2, 16 // store to aligned arr_dest
addi a3, a3, -16 // put arr_src pointer back
j _follow_unaligned
_unaligned_mod_16_check:
addi a3, a3, -32 // put arr_src pointer back
// Finish the _main_loop_unaligned outside of the loop
// Check modulo 8 of the loop_len_MOD, if - then copy 8 bytes
_follow_unaligned:
bbci a6, 3, _unaligned_mod_8_check // branch if 3-rd bit of loop_len_MOD a6 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15, offset 0
l32i.n a14, a3, 4 // load 32 bits from arr_src a3 to a14, offset 4
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2, offset 0
s32i.n a14, a2, 4 // save 32 bits from a14 to arr_dest a2, offset 4
addi.n a3, a3, 8 // increment arr_src pointer by 8 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 8 bytes
_unaligned_mod_8_check:
// Finish the rest of the data, as if the data were aligned, no S3 instructions will be used further after the jump
j _aligned_mod_8_check
// Both arrays (arr_src and arr_dest) aligned
_arr_src_aligned:
// Calculate modulo 32 for aligned data
srli a5, a4, 5 // a5 - loop_len = arr_len / 32
slli a6, a5, 5
sub a6, a4, a6 // a6 - loop_len_MOD 32
// Main loop arr_src aligned
loopnez a5, ._main_loop_aligned // 32 bytes in one loop
ee.vld.128.ip q0, a3, 16 // load 16 bytes from arr_src to q0
ee.vld.128.ip q1, a3, 16 // load 16 bytes from arr_src to q1
ee.vst.128.ip q0, a2, 16 // save 16 bytes to arr_dest from q0
ee.vst.128.ip q1, a2, 16 // save 16 bytes to arr_dest from q1
._main_loop_aligned:
// Modulo 32 check
beqz a6, _aligned_mod_32_check // branch if mod_32 = 0
// finish the end of the array outside of the main loop
// Check modulo 16 of the loop_len_MOD, if - then copy 16 bytes
bbci a6, 4, _aligned_mod_16_check // branch if 4-th bit of loop_len_MOD a6 is clear
ee.vld.128.ip q0, a3, 16 // load 128 bits from arr_src to q0, increase arr_src pointer by 16 bytes
ee.vst.128.ip q0, a2, 16 // save 128 bits to arr_dest from q0, increase arr_dest pointer by 16 bytes
_aligned_mod_16_check:
// Check modulo 8 of the loop_len_MOD, if - then copy 8 bytes
bbci a6, 3, _aligned_mod_8_check // branch if 3-rd bit of loop_len_MOD a6 is clear
ee.vld.l.64.ip q0, a3, 8 // load lower 64 bits from arr_src a3 to q0, increase arr_src pointer by 8 bytes
ee.vst.l.64.ip q0, a2, 8 // save lower 64 bits from q0 to arr_dest a2, increase arr_dest pointer by 8 bytes
_aligned_mod_8_check:
// Check modulo 4 of the loop_len_MOD, if - then copy 4 bytes
bbci a6, 2, _aligned_mod_4_check // branch if 2-nd bit of loop_len_MOD a6 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
addi.n a3, a3, 4 // increment arr_src pointer by 4 bytes
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_aligned_mod_4_check:
// Check modulo 2 of the loop_len_MOD, if - then copy 2 bytes
bbci a6, 1, _aligned_mod_2_check // branch if 1-st bit of loop_len_MOD a6 is clear
l16ui a15, a3, 0 // load 16 bits from arr_src a3 to a15
addi.n a3, a3, 2 // increment arr_src pointer by 2 bytes
s16i a15, a2, 0 // save 16 bits from a15 to arr_dest a2
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_aligned_mod_2_check:
// Check modulo 1 of the loop_len_MOD, if - then copy 1 byte
bbci a6, 0, _aligned_mod_32_check // branch if 0-th bit of loop_len_MOD a6 is clear
l8ui a15, a3, 0 // load 8 bits from arr_src a3 to a15
s8i a15, a2, 0 // save 8 bits from a15 to arr_dest a2
_aligned_mod_32_check:
mov a2, a7 // copy the initial arr_dest pointer from a7 to arr_dest a2
retw.n // return
_less_than_16:
// If the length of the copied array is lower than 16, it is faster not to use esp32s3-optimized functions
// Check modulo 8 of the arr_len, if - then copy 8 bytes
bbci a4, 3, _less_than_16_mod_8_check // branch if 3-rd bit of arr_len a4 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15, offset 0
l32i.n a14, a3, 4 // load 32 bits from arr_src a3 to a14, offset 4
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2, offset 0
s32i.n a14, a2, 4 // save 32 bits from a14 to arr_dest a2, offset 4
addi.n a3, a3, 8 // increment arr_src pointer by 8 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 8 bytes
_less_than_16_mod_8_check:
// Check modulo 4 of the arr_len, if - then copy 4 bytes
bbci a4, 2, _less_than_16_mod_4_check // branch if 2-nd bit of arr_len a4 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
addi.n a3, a3, 4 // increment arr_src pointer by 4 bytes
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_less_than_16_mod_4_check:
// Check modulo 2 of the arr_len, if - then copy 2 bytes
bbci a4, 1, _less_than_16_mod_2_check // branch if 1-st bit of arr_len a4 is clear
l16ui a15, a3, 0 // load 16 bits from arr_src a3 to a15
addi.n a3, a3, 2 // increment arr_src pointer by 2 bytes
s16i a15, a2, 0 // save 16 bits from a15 to arr_dest a2
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_less_than_16_mod_2_check:
// Check modulo 1 of the arr_len, if - then copy 1 byte
bbci a4, 0, _less_than_16_mod_1_check // branch if 0-th bit of arr_len a4 is clear
l8ui a15, a3, 0 // load 8 bits from arr_src a3 to a15
s8i a15, a2, 0 // save 8 bits from a15 to arr_dest a2
_less_than_16_mod_1_check:
mov a2, a7 // copy the initial arr_dest pointer from a7 to arr_dest a2
retw.n // return
#else // MEMCPY_OPTIMIZED
// ansi version of the memcpy (without TIE instructions) for testing purposes
entry a1, 32
mov a7, a2 // a7 - save arr_dest pointer
srli a5, a4, 4 // a5 - loop_len = arr_len / 16
// Run main loop which copies 16 bytes in one loop run
loopnez a5, ._ansi_loop
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
l32i.n a14, a3, 4 // load 32 bits from arr_src a3 to a14
l32i.n a13, a3, 8 // load 32 bits from arr_src a3 to a13
l32i.n a12, a3, 12 // load 32 bits from arr_src a3 to a13
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
s32i.n a14, a2, 4 // save 32 bits from a14 to arr_dest a2
s32i.n a13, a2, 8 // save 32 bits from a13 to arr_dest a2
s32i.n a12, a2, 12 // save 32 bits from a13 to arr_dest a2
addi.n a3, a3, 16 // increment arr_src pointer by 12 bytes
addi.n a2, a2, 16 // increment arr_dest pointer by 12 bytes
._ansi_loop:
// Finish the remaining bytes out of the loop
// Check modulo 8 of the arr_len, if - then copy 8 bytes
bbci a4, 3, _mod_8_check // branch if 2-nd bit of arr_len a4 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
l32i.n a14, a3, 4 // load 32 bits from arr_src a3 to a15
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
s32i.n a14, a2, 4 // save 32 bits from a15 to arr_dest a2
addi.n a3, a3, 8 // increment arr_src pointer by 4 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 4 bytes
_mod_8_check:
// Check modulo 4 of the arr_len, if - then copy 4 bytes
bbci a4, 2, _mod_4_check // branch if 2-nd bit of arr_len a4 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
addi.n a3, a3, 4 // increment arr_src pointer by 4 bytes
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_mod_4_check:
// Check modulo 2 of the arr_len, if - then copy 2 bytes
bbci a4, 1, _mod_2_check // branch if 1-st bit of arr_len a4 is clear
l16ui a15, a3, 0 // load 16 bits from arr_src a3 to a15
addi.n a3, a3, 2 // increment arr_src pointer by 2 bytes
s16i a15, a2, 0 // save 16 bits from a15 to arr_dest a2
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_mod_2_check:
// Check modulo 1 of the arr_len, if - then copy 1 byte
bbci a4, 0, _mod_1_check // branch if 0-th bit of arr_len a4 is clear
l8ui a15, a3, 0 // load 8 bits from arr_src a3 to a15
s8i a15, a2, 0 // save 8 bits from a15 to arr_dest a2
_mod_1_check:
// if arr_len is shorter than 16, skip adding TIE instruction, to fix the panic handler before the main_app() loads
blti a4, 16, _less_than_16_1 // branch, if arr_len a4 is shorter than 16 bytes
#if TIE_ENABLE // put dummy TIE instruction to induce TIE context saving
ee.zero.qacc // initialize q0 to zero (dummy instruction)
#else // TIE_ENABLE
nop // compensate one cycle, when TIE is disabled to get the same benchmark value
#endif // TIE_ENABLE
_less_than_16_1:
mov a2, a7 // copy the initial arr_dest pointer from a7 to arr_dest a2
retw.n // return
#endif // MEMCPY_OPTIMIZED
#endif // dsps_mem_aes3_enbled
|
georgevio/IoT-Embedded
| 2,417
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/iir/biquad/dsps_biquad_f32_aes3.S
|
// Copyright 2025 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad_platform.h"
#if (dsps_biquad_f32_aes3_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_biquad_f32_aes3
.type dsps_biquad_f32_aes3,@function
// The function implements the following C code:
//esp_err_t dsps_biquad_f32_aes3(const float* input, float* output, int len, float* coef, float* w)
// {
// for (int i=0 ; i< len ; i++)
// {
// float d0 = input[i] - coef[3]*w[0] - coef[4]*w[1]; (input[i] - a[1]*w[0] - a[2]*w[1];)
// output[i] = coef[0]*d0 + coef[1]*w[0] + coef[2]*w[1];
// w[1] = w[0];
// w[0] = d0;
// }
// return ESP_OK;
// }
dsps_biquad_f32_aes3:
// input - a2
// output - a3
// len - a4
// coeffs - a5
// w- a6
// f0 - b0
// f1 - b1
// f2 - b2
// f3 - a1
// f4 - a2
// f5 - w0
// f6 - w1
entry a1, 16
// Array increment for floating point data should be 4
lsi f0, a5, 0
lsi f1, a5, 4
lsi f2, a5, 8
lsi f3, a5, 12
lsi f4, a5, 16
neg.s f5, f3 // -a[1]
neg.s f6, f4 // -a[2]
lsi f7, a6, 0 // w[0]
lsi f8, a6, 4 // w[1]
addi a3, a3, -4 // i-- // preset a3
lsi f9, a2, 0 // f9 = x[i]
loopnez a4, .loop_bq_end_m_aes3
madd.s f9, f7, f5 // f9 += -a1*w0
addi a3, a3, 4 // out++;
mul.s f10, f1, f7 // f10 = b1*w0
madd.s f9, f8, f6 // f9 += -a2*w1
madd.s f10, f9, f0 // f10 += b0*d0
addi a2, a2, 4 // in++;
madd.s f10, f2, f8 // f10+= b2*w1, f10 - result
mov.s f8, f7 // w1 = w0
mov.s f7, f9 // w0 = d0
lsi f9, a2, 0 // f9 = x[i]
ssi f10, a3, 0 // y[i] = result
.loop_bq_end_m_aes3:
// Store delay line
ssi f7, a6, 0
ssi f8, a6, 4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_biquad_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 3,677
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/iir/biquad/dsps_biquad_sf32_arp4.S
|
// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad_platform.h"
#if (dsps_biquad_f32_arp4_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_biquad_sf32_arp4
.type dsps_biquad_sf32_arp4,@function
// The function implements the following C code:
//esp_err_t dsps_biquad_f32_arp4(const float* input, float* output, int len, float* coef, float* w)
// {
// for (int i = 0 ; i < len ; i++) {
// float d0 = input[i*2 + 0] - coef[3] * w[0] - coef[4] * w[1];
// output[i*2 + 0] = coef[0] * d0 + coef[1] * w[0] + coef[2] * w[1];
// w[1] = w[0];
// w[0] = d0;
//
// d0 = input[i*2 + 1] - coef[3] * w[2] - coef[4] * w[3];
// output[i*2 + 1] = coef[0] * d0 + coef[1] * w[2] + coef[2] * w[3];
// w[3] = w[2];
// w[2] = d0;
// }
// return ESP_OK;
// }
dsps_biquad_sf32_arp4:
// input - a0
// output - a1
// len - a2
// coeffs - a3
// w- a4
// fa0 - b0
// fa1 - b1
// fa2 - b2
// fa3 - a1
// fa4 - a2
// fa5 - w0
// fa6 - w1
add sp,sp,-16
flw fa0, 0(a3) // coeff[0] : b0
flw fa1, 4(a3) // coeff[1] : b1
flw fa2, 8(a3) // coeff[2] : b2
flw fa3, 12(a3) // coeff[3] : a1
flw fa4, 16(a3) // coeff[4] : a2
fneg.S fa5, fa3 // -a[1]
fneg.S fa6, fa4 // -a[2]
flw ft0, 0(a4) // ft0 - f7 w0
flw ft1, 4(a4) // ft1 - f8 w1
flw ft5, 8(a4) // ft0 - f12 w2
flw ft6, 12(a4) // ft1 - f13 w3
flw ft2, 0(a0) // ft2 - f9 = x[i]
esp.lp.setup 0, a2, .iir_loop_end // label to the last executed instruction
fmadd.S ft2, ft0, fa5, ft2 // ft2 = x[i] - a1*w0
fmul.s ft3, fa1, ft0 // ft3 = w0*b1
fmadd.s ft2, ft1, fa6, ft2 // ft2 += -a2*w1 = d0
fmadd.s ft3, ft2, fa0, ft3 // f10 += b0*d0
addi a0, a0, 4 // in++;
fmadd.s ft3, fa2, ft1, ft3 // f10+= b2*w1, f10 - result
fmv.s ft1, ft0 // w1 = w0
fmv.s ft0, ft2 // w0 = d0
flw ft2, 0(a0)
fsw ft3, 0(a1)
addi a1, a1, 4 // out++;
fmadd.S ft2, ft5, fa5, ft2 // ft2 = x[i] - a1*w0
fmul.s ft3, fa1, ft5 // ft3 = w0*b1
fmadd.s ft2, ft6, fa6, ft2 // ft2 += -a2*w1 = d0
fmadd.s ft3, ft2, fa0, ft3 // f10 += b0*d0
addi a0, a0, 4 // in++;
fmadd.s ft3, fa2, ft6, ft3 // f10+= b2*w1, f10 - result
fmv.s ft6, ft5 // w1 = w0
fmv.s ft5, ft2 // w0 = d0
flw ft2, 0(a0)
fsw ft3, 0(a1)
addi a1, a1, 4 // out++;
.iir_loop_end: nop
fsw ft0, 0(a4) // ft0 - f7
fsw ft1, 4(a4) // ft1 - f8
fsw ft5, 8(a4) // ft5 - f12
fsw ft6, 12(a4) // ft6 - f13
mv a0, a6
add sp,sp,16
ret
#endif // dsps_biquad_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 2,814
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/iir/biquad/dsps_biquad_sf32_ae32.S
|
// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad_platform.h"
#if (dsps_biquad_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_biquad_sf32_ae32
.type dsps_biquad_sf32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_biquad_f32_ae32(const float* input, float* output, int len, float* coef, float* w)
// {
// for (int i=0 ; i< len ; i++)
// {
// float d0 = input[i] - coef[3]*w[0] - coef[4]*w[1]; (input[i] - a[1]*w[0] - a[2]*w[1];)
// output[i] = coef[0]*d0 + coef[1]*w[0] + coef[2]*w[1];
// w[1] = w[0];
// w[0] = d0;
// }
// return ESP_OK;
// }
dsps_biquad_sf32_ae32:
// input - a2
// output - a3
// len - a4
// coeffs - a5
// w- a6
// f0 - b0
// f1 - b1
// f2 - b2
// f3 - a1
// f4 - a2
// f5 - w0
// f6 - w1
entry a1, 16
// Array increment for floating point data should be 4
lsi f0, a5, 0
lsi f1, a5, 4
lsi f2, a5, 8
lsi f3, a5, 12
lsi f4, a5, 16
neg.s f5, f3 // -a[1]
neg.s f6, f4 // -a[2]
lsi f7, a6, 0 // w[0]
lsi f8, a6, 4 // w[1]
lsi f11, a6, 8 // w[0]
lsi f12, a6, 12 // w[1]
//addi a3, a3, -4 // i-- // preset a3
lsip f9, a2, 4 // f9 = x[i]
loopnez a4, .loop_bq_end_m_ae32
madd.s f9, f7, f5 // f9 += -a1*w0
mul.s f10, f1, f7 // f10 = b1*w0
madd.s f9, f8, f6 // f9 += -a2*w1
madd.s f10, f9, f0 // f10 += b0*d0
madd.s f10, f2, f8 // f10+= b2*w1, f10 - result
mov.s f8, f7 // w1 = w0
mov.s f7, f9 // w0 = d0
lsip f9, a2, 4 // f9 = x[i]
ssip f10, a3, 4 // y[i] = result
madd.s f9, f11, f5 // f9 += -a1*w0
mul.s f10, f1, f11 // f10 = b1*w0
madd.s f9, f12, f6 // f9 += -a2*w1
madd.s f10, f9, f0 // f10 += b0*d0
madd.s f10, f2, f12 // f10+= b2*w1, f10 - result
mov.s f12, f11 // w1 = w0
mov.s f11, f9 // w0 = d0
lsip f9, a2, 4 // f9 = x[i]
ssip f10, a3, 4 // y[i] = result
.loop_bq_end_m_ae32:
// Store delay line
ssi f7, a6, 0
ssi f8, a6, 4
ssi f11, a6, 8
ssi f12, a6, 12
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_biquad_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,309
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/iir/biquad/dsps_biquad_f32_ae32.S
|
// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad_platform.h"
#if (dsps_biquad_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_biquad_f32_ae32
.type dsps_biquad_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_biquad_f32_ae32(const float* input, float* output, int len, float* coef, float* w)
// {
// for (int i=0 ; i< len ; i++)
// {
// float d0 = input[i] - coef[3]*w[0] - coef[4]*w[1]; (input[i] - a[1]*w[0] - a[2]*w[1];)
// output[i] = coef[0]*d0 + coef[1]*w[0] + coef[2]*w[1];
// w[1] = w[0];
// w[0] = d0;
// }
// return ESP_OK;
// }
dsps_biquad_f32_ae32:
// input - a2
// output - a3
// len - a4
// coeffs - a5
// w- a6
// f0 - b0
// f1 - b1
// f2 - b2
// f3 - a1
// f4 - a2
// f5 - w0
// f6 - w1
entry a1, 16
// Array increment for floating point data should be 4
lsi f0, a5, 0
lsi f1, a5, 4
lsi f2, a5, 8
lsi f3, a5, 12
lsi f4, a5, 16
neg.s f5, f3 // -a[1]
neg.s f6, f4 // -a[2]
lsi f7, a6, 0 // w[0]
lsi f8, a6, 4 // w[1]
lsip f9, a2, 4 // f9 = x[i]
loopnez a4, .loop_bq_end_m_ae32
madd.s f9, f7, f5 // f9 += -a1*w0
mul.s f10, f1, f7 // f10 = b1*w0
madd.s f9, f8, f6 // f9 += -a2*w1
madd.s f10, f9, f0 // f10 += b0*d0
madd.s f10, f2, f8 // f10+= b2*w1, f10 - result
mov.s f8, f7 // w1 = w0
mov.s f7, f9 // w0 = d0
lsip f9, a2, 4 // f9 = x[i]
ssip f10, a3, 4 // y[i] = result
.loop_bq_end_m_ae32:
// Store delay line
ssi f7, a6, 0
ssi f8, a6, 4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_biquad_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,625
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/iir/biquad/dsps_biquad_f32_arp4.S
|
// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad_platform.h"
#if (dsps_biquad_f32_arp4_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_biquad_f32_arp4
.type dsps_biquad_f32_arp4,@function
// The function implements the following C code:
//esp_err_t dsps_biquad_f32_arp4(const float* input, float* output, int len, float* coef, float* w)
// {
// for (int i=0 ; i< len ; i++)
// {
// float d0 = input[i] - coef[3]*w[0] - coef[4]*w[1]; (input[i] - a[1]*w[0] - a[2]*w[1];)
// output[i] = coef[0]*d0 + coef[1]*w[0] + coef[2]*w[1];
// w[1] = w[0];
// w[0] = d0;
// }
// return ESP_OK;
// }
dsps_biquad_f32_arp4:
// input - a0
// output - a1
// len - a2
// coeffs - a3
// w- a4
// fa0 - b0
// fa1 - b1
// fa2 - b2
// fa3 - a1
// fa4 - a2
// fa5 - w0
// fa6 - w1
add sp,sp,-16
flw fa0, 0(a3)
flw fa1, 4(a3)
flw fa2, 8(a3)
flw fa3, 12(a3)
flw fa4, 16(a3)
fneg.S fa5, fa3 // -a[1]
fneg.S fa6, fa4 // -a[2]
flw ft0, 0(a4) // ft0 - w0
flw ft1, 4(a4) // ft1 - w1
flw ft2, 0(a0) // ft2 - f9 = x[i]
esp.lp.setup 0, a2, .iir_loop_end // label to the last executed instruction
fmadd.S ft2, ft0, fa5, ft2
fmul.s ft3, fa1, ft0
fmadd.s ft2, ft1, fa6, ft2 // f9 += -a2*w1
fmadd.s ft3, ft2, fa0, ft3 // f10 += b0*d0
addi a0, a0, 4 // in++;
fmadd.s ft3, fa2, ft1, ft3 // f10+= b2*w1, f10 - result
fmv.s ft1, ft0 // w1 = w0
fmv.s ft0, ft2 // w0 = d0
flw ft2, 0(a0)
fsw ft3, 0(a1)
addi a1, a1, 4 // out++;
.iir_loop_end: nop
fsw ft0, 0(a4) // ft0 - f7
fsw ft1, 4(a4) // ft1 - f8
mv a0, a6
add sp,sp,16
ret
#endif // dsps_biquad_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 1,699
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/fft/float/dsps_bit_rev_lookup_fc32_aes3.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft2r_platform.h"
#if (dsps_bit_rev_lookup_fc32_ae32_enabled == 1)
#if (dsps_fft2r_fc32_aes3_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dsps_bit_rev_lookup_fc32_aes3
.type dsps_bit_rev_lookup_fc32_aes3,@function
dsps_bit_rev_lookup_fc32_aes3:
//esp_err_t dsps_bit_rev_lookup_fc32_aes3(float *data, int reverse_size, uint16_t *reverse_tab)
entry a1, 16
// data - a2
// reverse_size - a3
// reverse_tab - a4
loopnez a3, .__loop_end_radix2_reorder_lookup_table
l16ui a5, a4, 0 // Load first addr shift
l16ui a6, a4, 2 // Load second addr shift
addi a4, a4, 4 // Table addr update
add.n a5, a5, a2
add.n a6, a6, a2
EE.LDF.64.IP f0, f2, a5, 0
EE.LDF.64.IP f1, f3, a6, 0
EE.STF.64.IP f0, f2, a6, 0
EE.STF.64.IP f1, f3, a5, 0
.__loop_end_radix2_reorder_lookup_table:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_fft2r_fc32_aes3_enabled
#endif // dsps_bit_rev_lookup_fc32_ae32_enabled
|
georgevio/IoT-Embedded
| 3,655
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft2r_fc32_aes3_.S
|
/*
* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileContributor: 2024 f4lcOn @ Libera Chat IRC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_fc32_aes3_enabled == 1)
.text
.align 4
.global dsps_fft2r_fc32_aes3_
.type dsps_fft2r_fc32_aes3_,@function
// The function implements the following C code:
//esp_err_t dsps_fft2r_fc32_ansi(float *data, int N)
//{
// float *w = dsps_fft_w_table_fc32;
//
// int ie, ia, m;
// float re_temp, im_temp;
// float c, s;
// int N2 = N;
// ie = 1;
// for (int N2 = N/2; N2 > 0; N2 >>= 1) {
// ia = 0;
// for (int j = 0; j < ie; j++) {
// c = w[2 * j];
// s = w[2 * j + 1];
// for (int i = 0; i < N2; i++) {
// m = ia + N2;
// re_temp = c * data[2 * m] + s * data[2 * m + 1];
// im_temp = c * data[2 * m + 1] - s * data[2 * m];
// data[2 * m] = data[2 * ia] - re_temp;
// data[2 * m + 1] = data[2 * ia + 1] - im_temp;
// data[2 * ia] = data[2 * ia] + re_temp;
// data[2 * ia + 1] = data[2 * ia + 1] + im_temp;
// ia++;
// }
// ia += N2;
// }
// ie <<= 1;
// }
// return result;
//}
dsps_fft2r_fc32_aes3_:
//esp_err_t dsps_fft2r_fc32_ansi(float *data, int N, float* dsps_fft_w_table_fc32)
entry a1, 16
// Array increment for floating point data should be 4
// data - a2
// N - a3
// dsps_fft_w_table_fc32 - a4
// a6 - k, main loop counter; N2 - for (int N2 = N/2; N2 > 0; N2 >>= 1)
// a7 - ie
// a8 - j
// a10 - (j*2)<<2, or a10 - j<<3
// f0 - c or w[2 * j]
// f1 - s or w[2 * j + 1]
// a11 - ia
// a12 - m
// a13 - ia pointer
// a14 - m pointer
// f6 - re_temp
// f7 - im_temp
srli a6, a3, 1 // a6 = N2 = N/2
movi.n a7, 1 // a7 - ie
.fft2r_l1:
movi.n a8, 0 // a8 - j
movi.n a11,0 // a11 = ia = 0;
.fft2r_l2: // loop for j, a8 - j
addx8 a10, a8, a4 // a8 - shift for cos () -- c = w[2 * j]; -- pointer to cos
ee.ldf.64.ip f1, f0, a10, 0
add.n a12, a11, a6 // a12 = m = ia + N2
addx8 a14, a12, a2 // a14 - pointer for m*2
loopnez a6, .fft2r_l3
ee.ldf.64.ip f5, f4, a14, 0 // data[2 * m], data[2 * m + 1]
mul.s f6, f0, f4 // re_temp = c * data[2 * m]
mul.s f7, f0, f5 // im_temp = c * data[2 * m + 1]
addx8 a13, a11, a2 // a13 - pointer for ia*2
ee.ldf.64.ip f3, f2, a13, 0 // data[2 * ia], data[2 * ia + 1]
madd.s f6, f1, f5 // re_temp += s * data[2 * m + 1];
msub.s f7, f1, f4 // im_temp -= s * data[2 * m];
addi a11, a11, 1 // ia++
add.n a12, a11, a6 // a12 = m = ia + N2
sub.s f8, f2, f6 // = data[2 * ia] - re_temp;
sub.s f9, f3, f7 // = data[2 * ia + 1] - im_temp;
add.s f10, f2, f6 // = data[2 * ia] + re_temp;
add.s f11, f3, f7 // = data[2 * ia + 1] + im_temp;
ee.stf.64.ip f9, f8, a14, 0
addx8 a14, a12, a2 // a14 - pointer for m*2
ee.stf.64.ip f11, f10, a13, 0
.fft2r_l3:
add.n a11, a11, a6
addi.n a8, a8, 1 // j++
bne a8, a7, .fft2r_l2
slli a7, a7, 1 // ie = ie<<1
// main loop: for (int k = N/2; k > 0; k >>= 1)
srli a6, a6, 1 // a6 = a6>>1
bnez a6, .fft2r_l1 // Jump if > 0
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_fft2r_fc32_aes3_enabled
|
georgevio/IoT-Embedded
| 7,652
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft4r_fc32_aes3_.S
|
/*
* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileContributor: 2024 f4lcOn @ Libera Chat IRC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsp_err_codes.h"
#include "dsps_fft4r_platform.h"
#if (dsps_fft4r_fc32_aes3_enabled == 1)
.section .text
.global dsps_fft4r_fc32_aes3_
.global dsps_fft4r_fc32_ae32_
.type dsps_fft4r_fc32_aes3_,@function
.type dsps_fft4r_fc32_ae32_,@function
// The function implements the following C code:
// esp_err_t dsps_fft4r_fc32_ansi_(float *data, int length, float *table, int table_size)
// {
// if (0 == dsps_fft4r_initialized) {
// return ESP_ERR_DSP_UNINITIALIZED;
// }
//
// uint log2N = dsp_power_of_two(length);
// if ((log2N & 0x01) != 0) {
// return ESP_ERR_DSP_INVALID_LENGTH;
// }
// uint log4N = log2N >> 1;
//
// fc32_t bfly[4];
// uint m = 2;
// uint wind_step = table_size / length;
// while (1) { ///radix 4
// if (log4N == 0) {
// break;
// }
// length = length >> 2;
// for (int j = 0; j < m; j += 2) { // j: which FFT of this step
// int start_index = j * (length << 1); // n: n-point FFT
//
// fc32_t *ptrc0 = (fc32_t *)data + start_index;
// fc32_t *ptrc1 = ptrc0 + length;
// fc32_t *ptrc2 = ptrc1 + length;
// fc32_t *ptrc3 = ptrc2 + length;
//
// fc32_t *winc0 = (fc32_t *)table;
// fc32_t *winc1 = winc0;
// fc32_t *winc2 = winc0;
//
// for (int k = 0; k < length; k++) {
// fc32_t in0 = *ptrc0;
// fc32_t in2 = *ptrc2;
// fc32_t in1 = *ptrc1;
// fc32_t in3 = *ptrc3;
//
// bfly[0].re = in0.re + in2.re + in1.re + in3.re;
// bfly[0].im = in0.im + in2.im + in1.im + in3.im;
//
// bfly[1].re = in0.re - in2.re + in1.im - in3.im;
// bfly[1].im = in0.im - in2.im - in1.re + in3.re;
//
// bfly[2].re = in0.re + in2.re - in1.re - in3.re;
// bfly[2].im = in0.im + in2.im - in1.im - in3.im;
//
// bfly[3].re = in0.re - in2.re - in1.im + in3.im;
// bfly[3].im = in0.im - in2.im + in1.re - in3.re;
//
// *ptrc0 = bfly[0];
// ptrc1->re = bfly[1].re * winc0->re + bfly[1].im * winc0->im;
// ptrc1->im = bfly[1].im * winc0->re - bfly[1].re * winc0->im;
// ptrc2->re = bfly[2].re * winc1->re + bfly[2].im * winc1->im;
// ptrc2->im = bfly[2].im * winc1->re - bfly[2].re * winc1->im;
// ptrc3->re = bfly[3].re * winc2->re + bfly[3].im * winc2->im;
// ptrc3->im = bfly[3].im * winc2->re - bfly[3].re * winc2->im;
//
// winc0 += 1 * wind_step;
// winc1 += 2 * wind_step;
// winc2 += 3 * wind_step;
//
// ptrc0++;
// ptrc1++;
// ptrc2++;
// ptrc3++;
// }
// }
// m = m << 2;
// wind_step = wind_step << 2;
// log4N--;
// }
// return ESP_OK;
// }
// esp_err_t dsps_fft4r_fc32_aes3_(data, N, dsps_fft4r_w_table_fc32, dsps_fft4r_w_table_size)
.ret_DSP_INVALID_LENGTH:
movi.n a2, ESP_ERR_DSP_INVALID_LENGTH
retw.n
.align 4
dsps_fft4r_fc32_ae32_: // this is added to make compatibility with libraries that already compiled and use ae32_ function.
dsps_fft4r_fc32_aes3_:
entry a1, 16 # no auto vars on stack
bltui a3, 4, .ret_DSP_INVALID_LENGTH # if N < 4 : return(ESP_ERR_DSP_INVALID_LENGTH)
addi.n a6, a3, -1
and a6, a3, a6
bnez a6, .ret_DSP_INVALID_LENGTH # if N not power of 2 : return(ESP_ERR_DSP_INVALID_LENGTH)
nsau a6, a3 # inline dsp_power_of_two(N)
movi.n a7, 31
xor a6, a6, a7
bbsi a6, 0, .ret_DSP_INVALID_LENGTH # if N not power of 4 : return(ESP_ERR_DSP_INVALID_LENGTH)
srli a7, a6, 1 # log4N = dsp_power_of_two(N) >> 1;
addi.n a6, a6, -1
ssr a6
srl a6, a5 # w_step = table_size >> (dsp_power_of_two(N) - 1)
movi.n a5, 2 # m = 2
.stage:
srli a3, a3, 2 # N >>= 2
movi.n a8, 0 # j = 0
.group:
mov.n a9, a4 # w0 = w
mov.n a10, a4 # w1 = w
mov.n a11, a4 # w2 = w
mul16u a12, a8, a3
slli a12, a12, 1 # start_index = (j * N) << 1
addx8 a12, a12, a2 # p0 = data + (start_index << 1)
addx8 a13, a3, a12 # p1 = p0 + (N << 1)
addx8 a14, a3, a13 # p2 = p1 + (N << 1)
addx8 a15, a3, a14 # p3 = p2 + (N << 1)
loopnez a3, .bf4_loop_end # for (uint k = 0; k < N; k++)
ee.ldf.64.ip f1, f0, a12, 0 # f0 = in0.re = *p0, f1 = in0.im = *(p0 + 1)
ee.ldf.64.ip f3, f2, a14, 0 # f2 = in2.re = *p2, f3 = in2.im = *(p2 + 1)
add.s f5, f1, f3 # f5 = in0.im + in2.im
sub.s f7, f1, f3 # f7 = in0.im - in2.im
add.s f4, f0, f2 # f4 = in0.re + in2.re
sub.s f6, f0, f2 # f6 = in0.re - in2.re
ee.ldf.64.ip f1, f0, a13, 0 # f0 = in1.re = *p1, f1 = in1.im = *(p1 + 1)
ee.ldf.64.ip f3, f2, a15, 0 # f2 = in3.re = *p3, f3 = in3.im = *(p3 + 1)
add.s f9, f1, f3 # f9 = in1.im + in3.im
sub.s f11, f1, f3 # f11 = in1.im - in3.im
lsi f12, a9, 0 # f12 = w0->re
lsi f13, a10, 0 # f13 = w1->re
lsi f14, a11, 0 # f14 = w2->re
add.s f8, f0, f2 # f8 = in1.re + in3.re
sub.s f10, f0, f2 # f10 = in1.re - in3.re
sub.s f1, f5, f9 # f1 = bf2.im = in0.im + in2.im - in1.im - in3.im
add.s f5, f5, f9 # f5 = bf0.im = in0.im + in2.im + in1.im + in3.im
add.s f2, f6, f11 # f2 = bf1.re = in0.re - in2.re + in1.im - in3.im
sub.s f6, f6, f11 # f6 = bf3.re = in0.re - in2.re - in1.im + in3.im
sub.s f0, f4, f8 # f0 = bf2.re = in0.re + in2.re - in1.re - in3.re
add.s f4, f4, f8 # f4 = bf0.re = in0.re + in2.re + in1.re + in3.re
sub.s f3, f7, f10 # f3 = bf1.im = in0.im - in2.im - in1.re + in3.re
add.s f7, f7, f10 # f7 = bf3.im = in0.im - in2.im + in1.re - in3.re
mul.s f10, f6, f14 # f10 = bf3.re * w2->re
ee.stf.64.ip f5, f4, a12, 8 # *p0 = f4 = bf0.re, *(p0 + 1) = f5 = bf0.im, p0 += 2
mul.s f4, f2, f12 # f4 = bf1.re * w0->re
mul.s f11, f7, f14 # f11 = bf3.im * w2->re
mul.s f5, f3, f12 # f5 = bf1.im * w0->re
mul.s f8, f0, f13 # f8 = bf2.re * w1->re
mul.s f9, f1, f13 # f9 = bf2.im * w1->re
lsi f12, a9, 4 # f12 = w0->im
lsi f13, a10, 4 # f13 = w1->im
lsi f14, a11, 4 # f14 = w2->im
msub.s f5, f2, f12 # f5 = bf1.im * w0->re - bf1.re * w0->im
madd.s f4, f3, f12 # f4 = bf1.re * w0->re + bf1.im * w0->im
msub.s f9, f0, f13 # f9 = bf2.im * w1->re - bf2.re * w1->im
madd.s f8, f1, f13 # f8 = bf2.re * w1->re + bf2.im * w1->im
msub.s f11, f6, f14 # f11 = bf3.im * w2->re - bf3.re * w2->im
madd.s f10, f7, f14 # f10 = bf3.re * w2->re + bf3.im * w2->im
addx4 a9, a6, a9 # w0 += w_step
addx8 a10, a6, a10 # w1 += 2 * w_step
addx4 a11, a6, a11
addx8 a11, a6, a11 # w2 += 3 * w_step
ee.stf.64.ip f5, f4, a13, 8 # *p1 = f4, *(p1 + 1) = f5, p1 += 2
ee.stf.64.ip f9, f8, a14, 8 # *p2 = f8, *(p2 + 1) = f9, p2 += 2
ee.stf.64.ip f11, f10, a15, 8 # *p3 = f10, *(p3 + 1) = f11, p3 += 2
.bf4_loop_end:
addi.n a8, a8, 2 # j += 2
bgeu a8, a5, .stage_next # if j >= m
j .group
.stage_next:
slli a5, a5, 2 # m <<= 2
slli a6, a6, 2 # w_step <<= 2
addi.n a7, a7, -1 # log4N--
bnez a7, .stage # if log4N > 0
movi.n a2, DSP_OK # return(DSP_OK)
retw.n
#endif // dsps_fft4r_fc32_aes3_enabled
|
georgevio/IoT-Embedded
| 3,678
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft2r_fc32_ae32_.S
|
/*
* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileContributor: 2024 f4lcOn @ Libera Chat IRC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_fc32_ae32_enabled == 1)
.text
.align 4
.global dsps_fft2r_fc32_ae32_
.type dsps_fft2r_fc32_ae32_,@function
// The function implements the following C code:
//esp_err_t dsps_fft2r_fc32_ansi(float *data, int N)
//{
// float *w = dsps_fft_w_table_fc32;
//
// int ie, ia, m;
// float re_temp, im_temp;
// float c, s;
// int N2 = N;
// ie = 1;
// for (int N2 = N/2; N2 > 0; N2 >>= 1) {
// ia = 0;
// for (int j = 0; j < ie; j++) {
// c = w[2 * j];
// s = w[2 * j + 1];
// for (int i = 0; i < N2; i++) {
// m = ia + N2;
// re_temp = c * data[2 * m] + s * data[2 * m + 1];
// im_temp = c * data[2 * m + 1] - s * data[2 * m];
// data[2 * m] = data[2 * ia] - re_temp;
// data[2 * m + 1] = data[2 * ia + 1] - im_temp;
// data[2 * ia] = data[2 * ia] + re_temp;
// data[2 * ia + 1] = data[2 * ia + 1] + im_temp;
// ia++;
// }
// ia += N2;
// }
// ie <<= 1;
// }
// return result;
//}
dsps_fft2r_fc32_ae32_:
//esp_err_t dsps_fft2r_fc32_ansi(float *data, int N, float* dsps_fft_w_table_fc32)
entry a1, 16
// Array increment for floating point data should be 4
// data - a2
// N - a3
// dsps_fft_w_table_fc32 - a4
// a6 - k, main loop counter; N2 - for (int N2 = N/2; N2 > 0; N2 >>= 1)
// a7 - ie
// a8 - j
// a10 - (j*2)<<2, or a10 - j<<3
// f0 - c or w[2 * j]
// f1 - s or w[2 * j + 1]
// a11 - ia
// a12 - m
// a13 - ia pointer
// a14 - m pointer
// f6 - re_temp
// f7 - im_temp
srli a6, a3, 1 // a6 = N2 = N/2
movi.n a7, 1 // a7 - ie
.fft2r_l1:
movi.n a8, 0 // a8 - j
movi.n a11,0 // a11 = ia = 0;
.fft2r_l2: // loop for j, a8 - j
addx8 a10, a8, a4 // a8 - shift for cos () -- c = w[2 * j]; -- pointer to cos
lsi f0, a10, 0
lsi f1, a10, 4
loopnez a6, .fft2r_l3
add.n a12, a11, a6 // a12 = m = ia + N2
addx8 a14, a12, a2 // a14 - pointer for m*2
addx8 a13, a11, a2 // a13 - pointer for ia*2
lsi f4, a14, 0 // data[2 * m]
mul.s f6, f0, f4 // re_temp = c * data[2 * m]
lsi f5, a14, 4 // data[2 * m + 1]
mul.s f7, f0, f5 // im_temp = c * data[2 * m + 1]
lsi f2, a13, 0 // data[2 * ia]
madd.s f6, f1, f5 // re_temp += s * data[2 * m + 1];
lsi f3, a13, 4 // data[2 * ia + 1]
msub.s f7, f1, f4 // im_temp -= s * data[2 * m];
addi a11, a11, 1 // ia++
sub.s f8, f2, f6 // = data[2 * ia] - re_temp;
add.s f10, f2, f6 // = data[2 * ia] + re_temp;
sub.s f9, f3, f7 // = data[2 * ia + 1] - im_temp;
add.s f11, f3, f7 // = data[2 * ia + 1] + im_temp;
ssi f8, a14, 0
ssi f10, a13, 0
ssi f9, a14, 4
ssi f11, a13, 4
.fft2r_l3:
add.n a11, a11, a6
addi.n a8, a8, 1 // j++
bne a8, a7, .fft2r_l2
slli a7, a7, 1 // ie = ie<<1
// main loop: for (int k = N/2; k > 0; k >>= 1)
srli a6, a6, 1 // a6 = a6>>1
bnez a6, .fft2r_l1 // Jump if > 0
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_fft2r_fc32_ae32_enabled
|
georgevio/IoT-Embedded
| 6,414
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft4r_fc32_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft4r_platform.h"
#if (dsps_fft4r_fc32_arp4_enabled == 1)
// This is matrix multipliction function for esp32p4 processor.
.text
.align 4
.global dsps_fft4r_fc32_arp4_
.type dsps_fft4r_fc32_arp4_,@function
dsps_fft4r_fc32_arp4_:
//esp_err_t dsps_fft4r_fc32_arp4_(float *data, int N, float *table, int wind_step)
// wind_step - a3
// m - t0
// j - t1
add sp,sp,-16
#
srli t6, a1, 1 // t6 = log4N = N/2
li t0, 2 // t0 - m
slli a3, a3, 3 // wind_step = complex step = 8 bytes
.fft2r_l1:
li t1, 0 // t1 - j
srli a1, a1, 2 // a1 = length = length >> 2;
.fft2r_l2: // loop for j, t1 - j
slli t2, a1, 4 // t2 = length << 1 << 3 (8 bytes for one complex sample)
slli t3, a1, 3 // t2 = length << 1 << 3 (8 bytes for one complex sample)
// start_index = j * (length << 1); // n: n-point FFT
mul t2,t2,t1
add a4, a0, t2 // fc32_t *ptrc0
add a5, a4, t3 // fc32_t *ptrc1
add a6, a5, t3 // fc32_t *ptrc2
add a7, a6, t3 // fc32_t *ptrc3
# flw fa0, 0(a4)
# fsw fa0, 0(t3)
# add t3, t3, 4
mv t2, a2 // winc0
mv t3, a2 // winc0
mv t4, a2 // winc0
esp.lp.setup 0, a1, .fft2r_l3 // .fft2r_l3 - label to the last executed instruction
flw fa0, 0(a4) // in0.re
flw fa4, 0(a6) // in2.re
fadd.s ft0, fa0, fa4 // in0.re + in2.re
flw fa1, 4(a4) // in0.im
fsub.s ft1, fa0, fa4 // in0.re - in2.re
flw fa5, 4(a6) // in2.im
fadd.s ft2, fa1, fa5 // in0.im + in2.im
flw fa2, 0(a5) // in1.re
fsub.s ft3, fa1, fa5 // in0.im - in2.im
flw fa6, 0(a7) // in3.re
fadd.s ft4, fa2, fa6 // in1.re + in3.re
flw fa3, 4(a5) // in1.im
fsub.s ft5, fa2, fa6 // in1.re - in3.re
flw fa7, 4(a7) // in3.im
fadd.s ft6, fa3, fa7 // in1.im + in3.im
fsub.s ft7, fa3, fa7 // in1.im - in3.im
# bfly[0].re = ft0 + ft4;
fadd.s fa0, ft0, ft4;
# bfly[0].im = ft2 + ft6;
fadd.s fa1, ft2, ft6;
# bfly[1].re = ft1 + ft7;
fadd.s fa2, ft1, ft7;
# bfly[1].im = ft3 - ft5;
fsub.s fa3, ft3, ft5;
# bfly[2].re = ft0 - ft5;
fsub.s fa4, ft0, ft4;
flw ft0, 0(t2) // winc0->re
# bfly[2].im = ft2 - ft7;
fsub.s fa5, ft2, ft6;
flw ft2, 0(t3) // winc1->re
# bfly[3].re = ft1 - ft6;
fsub.s fa6, ft1, ft7;
flw ft1, 4(t2) // winc0->im
# bfly[3].im = ft3 + ft5;
fadd.s fa7, ft3, ft5;
// *ptrc0 = bfly[0];
fsw fa0, 0(a4) // in0.re
fsw fa1, 4(a4) // in0.im
flw ft3, 4(t3) // winc1->im
// ptrc1->re = bfly[1].re * winc0->re + bfly[1].im * winc0->im;
// ptrc1->im = bfly[1].im * winc0->re - bfly[1].re * winc0->im;
// ptrc2->re = bfly[2].re * winc1->re + bfly[2].im * winc1->im;
fmul.s fa0, fa2, ft0
add t2, t2, a3 // winc0 += 1 * wind_step;
fmul.s fa1, fa3, ft0
fmul.s ft0, fa4, ft2
fmul.s ft2, fa5, ft2
flw ft4, 0(t4) // winc2->re
flw ft5, 4(t4) // winc3->im
fmadd.s fa0, fa3, ft1, fa0
add t3, t3, a3 // winc1 += 2 * wind_step;
fnmsub.s fa1, fa2, ft1, fa1
add t3, t3, a3 //
fmul.s fa2, fa6, ft4
fmul.s fa3, fa7, ft4
add t4, t4, a3 // winc2 += 3 * wind_step;
fmadd.s ft0, fa5, ft3, ft0
add t4, t4, a3 //
fnmsub.s ft2, fa4, ft3, ft2
fmadd.s ft3, fa7, ft5, fa2
add t4, t4, a3 //
fnmsub.s fa3, fa6, ft5, fa3
fsw fa0, 0(a5) // in1.re
add a4, a4, 8
fsw fa1, 4(a5) // in1.im
add a5, a5, 8
fsw ft0, 0(a6) // in2.re
// ptrc2->im = bfly[2].im * winc1->re - bfly[2].re * winc1->im;
fsw ft2, 4(a6) // in2.re
// ptrc3->re = bfly[3].re * winc2->re + bfly[3].im * winc2->im;
add a6, a6, 8
fsw ft3, 0(a7) // in2.re
// ptrc3->im = bfly[3].im * winc2->re - bfly[3].re * winc2->im;
fsw fa3, 4(a7) // in2.re
add a7, a7, 8
// Temp solution
.fft2r_l3: nop
add t1, t1, 2 // j+=2
BNE t1, t0, .fft2r_l2
slli t0, t0, 2 // t0 = m = m<<2
srli t6, t6, 2 // t6 = log4N >>= 2
slli a3, a3, 2 // wind_step = wind_step << 2;
BNEZ t6, .fft2r_l1// Jump if > 0
#
add sp,sp,16
li a0,0
ret
#endif // dsps_fft4r_fc32_arp4_enabled
|
georgevio/IoT-Embedded
| 7,631
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft4r_fc32_ae32_.S
|
/*
* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileContributor: 2024 f4lcOn @ Libera Chat IRC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsp_err_codes.h"
#include "dsps_fft4r_platform.h"
#if (dsps_fft4r_fc32_ae32_enabled == 1)
.section .text # placed in IRAM instead of FLASH .text
.global dsps_fft4r_fc32_ae32_
.type dsps_fft4r_fc32_ae32_,@function
// The function implements the following C code:
// esp_err_t dsps_fft4r_fc32_ansi_(float *data, int length, float *table, int table_size)
// {
// if (0 == dsps_fft4r_initialized) {
// return ESP_ERR_DSP_UNINITIALIZED;
// }
//
// uint log2N = dsp_power_of_two(length);
// if ((log2N & 0x01) != 0) {
// return ESP_ERR_DSP_INVALID_LENGTH;
// }
// uint log4N = log2N >> 1;
//
// fc32_t bfly[4];
// uint m = 2;
// uint wind_step = table_size / length;
// while (1) { ///radix 4
// if (log4N == 0) {
// break;
// }
// length = length >> 2;
// for (int j = 0; j < m; j += 2) { // j: which FFT of this step
// int start_index = j * (length << 1); // n: n-point FFT
//
// fc32_t *ptrc0 = (fc32_t *)data + start_index;
// fc32_t *ptrc1 = ptrc0 + length;
// fc32_t *ptrc2 = ptrc1 + length;
// fc32_t *ptrc3 = ptrc2 + length;
//
// fc32_t *winc0 = (fc32_t *)table;
// fc32_t *winc1 = winc0;
// fc32_t *winc2 = winc0;
//
// for (int k = 0; k < length; k++) {
// fc32_t in0 = *ptrc0;
// fc32_t in2 = *ptrc2;
// fc32_t in1 = *ptrc1;
// fc32_t in3 = *ptrc3;
//
// bfly[0].re = in0.re + in2.re + in1.re + in3.re;
// bfly[0].im = in0.im + in2.im + in1.im + in3.im;
//
// bfly[1].re = in0.re - in2.re + in1.im - in3.im;
// bfly[1].im = in0.im - in2.im - in1.re + in3.re;
//
// bfly[2].re = in0.re + in2.re - in1.re - in3.re;
// bfly[2].im = in0.im + in2.im - in1.im - in3.im;
//
// bfly[3].re = in0.re - in2.re - in1.im + in3.im;
// bfly[3].im = in0.im - in2.im + in1.re - in3.re;
//
// *ptrc0 = bfly[0];
// ptrc1->re = bfly[1].re * winc0->re + bfly[1].im * winc0->im;
// ptrc1->im = bfly[1].im * winc0->re - bfly[1].re * winc0->im;
// ptrc2->re = bfly[2].re * winc1->re + bfly[2].im * winc1->im;
// ptrc2->im = bfly[2].im * winc1->re - bfly[2].re * winc1->im;
// ptrc3->re = bfly[3].re * winc2->re + bfly[3].im * winc2->im;
// ptrc3->im = bfly[3].im * winc2->re - bfly[3].re * winc2->im;
//
// winc0 += 1 * wind_step;
// winc1 += 2 * wind_step;
// winc2 += 3 * wind_step;
//
// ptrc0++;
// ptrc1++;
// ptrc2++;
// ptrc3++;
// }
// }
// m = m << 2;
// wind_step = wind_step << 2;
// log4N--;
// }
// return ESP_OK;
// }
// esp_err_t dsps_fft4r_fc32_ae32_(data, N, dsps_fft4r_w_table_fc32, dsps_fft4r_w_table_size)
.ret_DSP_INVALID_LENGTH:
movi.n a2, ESP_ERR_DSP_INVALID_LENGTH
retw.n
.align 4
dsps_fft4r_fc32_ae32_:
entry a1, 16 # no auto vars on stack
bltui a3, 4, .ret_DSP_INVALID_LENGTH # if N < 4 : return(ESP_ERR_DSP_INVALID_LENGTH)
addi.n a6, a3, -1
and a6, a3, a6
bnez a6, .ret_DSP_INVALID_LENGTH # if N not power of 2 : return(ESP_ERR_DSP_INVALID_LENGTH)
nsau a6, a3 # inline dsp_power_of_two(N)
movi.n a7, 31
xor a6, a6, a7
bbsi a6, 0, .ret_DSP_INVALID_LENGTH # if N not power of 4 : return(ESP_ERR_DSP_INVALID_LENGTH)
srli a7, a6, 1 # log4N = dsp_power_of_two(N) >> 1;
addi.n a6, a6, -1
ssr a6
srl a6, a5 # w_step = table_size >> (dsp_power_of_two(N) - 1)
movi.n a5, 2 # m = 2
.stage:
srli a3, a3, 2 # N >>= 2
movi.n a8, 0 # j = 0
.group:
mov.n a9, a4 # w0 = w
mov.n a10, a4 # w1 = w
mov.n a11, a4 # w2 = w
mul16u a12, a8, a3
slli a12, a12, 1 # start_index = (j * N) << 1
addx8 a12, a12, a2 # p0 = data + (start_index << 1)
addx8 a13, a3, a12 # p1 = p0 + (N << 1)
addx8 a14, a3, a13 # p2 = p1 + (N << 1)
addx8 a15, a3, a14 # p3 = p2 + (N << 1)
loopnez a3, .bf4_loop_end # for (uint k = 0; k < N; k++)
lsi f1, a12, 4 # f1 = in0.im = *(p0 + 1)
lsi f3, a14, 4 # f3 = in2.im = *(p2 + 1)
lsi f0, a12, 0 # f0 = in0.re = *p0
lsi f2, a14, 0 # f2 = in2.re = *p2
add.s f5, f1, f3 # f5 = in0.im + in2.im
sub.s f7, f1, f3 # f7 = in0.im - in2.im
lsi f1, a13, 4 # f1 = in1.im = *(p1 + 1)
lsi f3, a15, 4 # f3 = in3.im = *(p3 + 1)
add.s f4, f0, f2 # f4 = in0.re + in2.re
sub.s f6, f0, f2 # f6 = in0.re - in2.re
add.s f9, f1, f3 # f9 = in1.im + in3.im
sub.s f11, f1, f3 # f11 = in1.im - in3.im
lsi f0, a13, 0 # f0 = in1.re = *p1
lsi f2, a15, 0 # f2 = in3.re = *p3
lsi f12, a9, 0 # f12 = w0->re
lsi f13, a10, 0 # f13 = w1->re
lsi f14, a11, 0 # f14 = w2->re
add.s f8, f0, f2 # f8 = in1.re + in3.re
sub.s f10, f0, f2 # f10 = in1.re - in3.re
sub.s f1, f5, f9 # f1 = bf2.im = in0.im + in2.im - in1.im - in3.im
add.s f5, f5, f9 # f5 = bf0.im = in0.im + in2.im + in1.im + in3.im
add.s f2, f6, f11 # f2 = bf1.re = in0.re - in2.re + in1.im - in3.im
sub.s f6, f6, f11 # f6 = bf3.re = in0.re - in2.re - in1.im + in3.im
sub.s f0, f4, f8 # f0 = bf2.re = in0.re + in2.re - in1.re - in3.re
add.s f4, f4, f8 # f4 = bf0.re = in0.re + in2.re + in1.re + in3.re
sub.s f3, f7, f10 # f3 = bf1.im = in0.im - in2.im - in1.re + in3.re
add.s f7, f7, f10 # f7 = bf3.im = in0.im - in2.im + in1.re - in3.re
ssi f5, a12, 4 # *(p0 + 1) = f5 = bf0.im
ssip f4, a12, 8 # *p0 = f4 = bf0.re , p0 += 2
mul.s f5, f3, f12 # f5 = bf1.im * w0->re
mul.s f4, f2, f12 # f4 = bf1.re * w0->re
mul.s f9, f1, f13 # f9 = bf2.im * w1->re
mul.s f8, f0, f13 # f8 = bf2.re * w1->re
mul.s f11, f7, f14 # f11 = bf3.im * w2->re
mul.s f10, f6, f14 # f10 = bf3.re * w2->re
lsi f12, a9, 4 # f12 = w0->im
lsi f13, a10, 4 # f13 = w1->im
lsi f14, a11, 4 # f14 = w2->im
addx4 a9, a6, a9 # w0 += m
addx8 a10, a6, a10 # w1 += 2 * m
addx4 a11, a6, a11
addx8 a11, a6, a11 # w2 += 3 * m
msub.s f5, f2, f12 # f5 = bf1.im * w0->re - bf1.re * w0->im
madd.s f4, f3, f12 # f4 = bf1.re * w0->re + bf1.im * w0->im
msub.s f9, f0, f13 # f9 = bf2.im * w1->re - bf2.re * w1->im
madd.s f8, f1, f13 # f8 = bf2.re * w1->re + bf2.im * w1->im
msub.s f11, f6, f14 # f11 = bf3.im * w2->re - bf3.re * w2->im
madd.s f10, f7, f14 # f10 = bf3.re * w2->re + bf3.im * w2->im
ssi f5, a13, 4 # *(p1 + 1) = f5
ssip f4, a13, 8 # *p1 = f4, p1 += 2
ssi f9, a14, 4 # *(p2 + 1) = f9
ssip f8, a14, 8 # *p2 = f8, p2 += 2
ssi f11, a15, 4 # *(p3 + 1) = f11
ssip f10, a15, 8 # *p3 = f10, p3 += 2
.bf4_loop_end:
addi.n a8, a8, 2 # j += 2
bgeu a8, a5, .stage_next # if j >= m
j .group
.stage_next:
slli a5, a5, 2 # m <<= 2
slli a6, a6, 2 # w_step <<= 2
addi.n a7, a7, -1 # log4N--
bnez a7, .stage # if log4N > 0
movi.n a2, DSP_OK # return(DSP_OK)
retw.n
#endif // dsps_fft4r_fc32_ae32_enabled
|
georgevio/IoT-Embedded
| 3,118
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft2r_fc32_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_fc32_arp4_enabled == 1)
// This is matrix multipliction function for esp32p4 processor.
.text
.align 4
.global dsps_fft2r_fc32_arp4_
.type dsps_fft2r_fc32_arp4_,@function
dsps_fft2r_fc32_arp4_:
//esp_err_t dsps_fft2r_fc32_arp4_(float *data, int N, float* dsps_fft_w_table_fc32)
add sp,sp,-16
#
srli t6, a1, 1 // a6 = N2 = N/2
li t0, 1 // a7 - ie
.fft2r_l1:
li t1, 0 // a8 - j
li t4, 0 // a11 = ia = 0;
.fft2r_l2: // loop for j, a8 - j
slli t3, t1, 3 // a10 = j<<3 // shift for cos () -- c = w[2 * j];
add t3, t3, a2 // a10 - pointer to cos
flw fa0, 0(t3)
flw fa1, 4(t3)
esp.lp.setup 0, t6, .fft2r_l3 // .fft2r_l3 - label to the last executed instruction
add t5, t4, t6 // a12 = m = ia + N2
slli a4, t5, 3 // a14 - pointer for m*2
slli a3, t4, 3 // a13 - pointer for ia*2
add a4, a4, a0 // pointers to data arrays
add a3, a3, a0 //
flw fa4, 0(a4)
flw fa5, 4(a4)
flw fa2, 0(a3)
flw fa3, 4(a3)
fmul.s ft6, fa0, fa4 // re_temp = c * data[2 * m]
fmul.s ft7, fa0, fa5 // im_temp = c * data[2 * m + 1]
fmadd.s ft6, fa1, fa5, ft6 // re_temp += s * data[2 * m + 1];
fnmsub.s ft7, fa1, fa4, ft7 // im_temp -= s * data[2 * m];
fsub.s ft8, fa2, ft6 // = data[2 * ia] - re_temp;
fsub.s ft9, fa3, ft7 // = data[2 * ia + 1] - im_temp;
fadd.s ft10, fa2, ft6 // = data[2 * ia] + re_temp;
fadd.s ft11, fa3, ft7 // = data[2 * ia + 1] + im_temp;
fsw ft8, 0(a4)
fsw ft9, 4(a4)
fsw ft10, 0(a3)
fsw ft11, 4(a3)
.fft2r_l3: add t4, t4, 1 // ia++
add t4, t4, t6
add t1, t1, 1 // j++
BNE t1, t0, .fft2r_l2
slli t0, t0, 1 // ie = ie<<1
srli t6, t6, 1 // a6 = a6>>1
BNEZ t6, .fft2r_l1// Jump if > 0
#
add sp,sp,16
li a0,0
ret
#endif // dsps_fft2r_fc32_arp4_enabled
|
georgevio/IoT-Embedded
| 6,295
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/fft/fixed/dsps_fft2r_sc16_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_sc16_ae32_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dsps_fft2r_sc16_ae32_
.type dsps_fft2r_sc16_ae32_,@function
.global dsps_fft_w_table_sc16;
//The function implements the following C code:
//esp_err_t dsps_fft2r_sc16_ansi(int16_t *data, int N)
//{
// esp_err_t result = ESP_OK;
// uint32_t *w = (uint32_t*)dsps_fft_w_table_sc16;
// uint32_t *in_data = (uint32_t *)data;
// int ie, ia, m;
// sc16_t temp;
// sc16_t cs;// c - re, s - im
// sc16_t m_data;
// sc16_t a_data;
// ie = 1;
// for (int N2 = N / 2; N2 > 0; N2 >>= 1) {
// ia = 0;
// for (int j = 0; j < ie; j++) {
// cs.data = w[j];
// //c = w[2 * j];
// //s = w[2 * j + 1];
// for (int i = 0; i < N2; i++) {
// m = ia + N2;
// m_data.data = in_data[m];
// a_data.data = in_data[ia];
// sc16_t m1;
// m1.re = xtfixed_bf_1(a_data.re, cs.re, m_data.re, cs.im, m_data.im, 16);//(a_data.re - temp.re + shift_const) >> 1;
// m1.im = xtfixed_bf_2(a_data.im, cs.re, m_data.im, cs.im, m_data.re, 16);//(a_data.im - temp.im + shift_const) >> 1;
// in_data[m] = m1.data;
// sc16_t m2;
// m2.re = xtfixed_bf_3(a_data.re, cs.re, m_data.re, cs.im, m_data.im, 16);//(a_data.re + temp.re + shift_const) >> 1;
// m2.im = xtfixed_bf_4(a_data.im, cs.re, m_data.im, cs.im, m_data.re, 16);//(a_data.im + temp.im + shift_const)>>1;
// in_data[ia] = m2.data;
// ia++;
// }
// ia += N2;
// }
// ie <<= 1;
// }
// return result;
// }
dsps_fft2r_sc16_ae32_:
//esp_err_t dsps_fft2r_sc16_ansi(float *data, int N, float* dsps_fft_w_table_sc16)
entry a1, 16
// Array increment for floating point data should be 4
// data - a2
// N - a3
// dsps_fft_w_table_sc16 - a4 - for now
// a5 - 1, used to initialize acc
// a6 - k, main loop counter; N2 - for (int N2 = N/2; N2 > 0; N2 >>= 1)
// a7 - ie
// a8 - j
// a9 - test
// a10 - (j)<<2, or a10 - j<<2
// a11 - ia
// a12 - m
// a13 - ia pointer
// a14 - m pointer
// a15 - used to shift result
// This instruction are not working. Have to be fixed!!!
// For now theres no solution...
// l32r a4, dsps_fft_w_table_sc16_ae32
// To use ldinc operation we have to prepare a4:
addi a4, a4, -4
addi a9, a2, -4 // prepare input pointer for ldinc operation
ldinc m1, a4 // Load [0x7fff j0] value to the m1
addi a4, a4, -4
// a5 used to load 0x7fff and clear acch/l
movi.n a5, 1 // a5 = 1;
srli a6, a3, 1 // a6 = N2 = N/2
// Load shift register
movi a7, 16
ssr a7
movi a7, 1 // a7 - ie
fft2r_l1:
movi a8, 0 // a8 - j
movi a11,0 // a11 = ia = 0;
fft2r_l2: // loop for j, a8 - j
slli a10, a8, 2 // a10 = j<<2 (4 bytes per address) // shift for cs.data = w[j];
add.n a10, a10, a4 // a10 - pointer to w tables
ldinc m0, a10 // cs.data = w[j];
// here we have m0 and m1
loopnez a6, fft2r_l3
add.n a12, a11, a6 // a12 = m = ia + N2
slli a14, a12, 2 // a14 - pointer for m, m_data.data = in_data[m];
slli a13, a11, 2 // a13 - pointer for ia, a_data.data = in_data[ia];
add.n a14, a14, a9 // pointers to data arrays
add.n a13, a13, a9 // These pointers are -4 from expected values...
ldinc m2, a14 // m_data, a14 += 4; The pointers ready to store data
mul.da.ll m1, a5 // acc = 0x7fff*1
ldinc m3, a13 // ai_data a13 += 4;
// re - l, im - h
muls.dd.ll m0, m2 // acc -= cs.re*m_data.re
mula.dd.ll m1, m3 // acc += 0x7fff*a_data.re
muls.dd.hh m0, m2 // acc -= cs.im*m_data.im
// result in acclo in_data[m].re
rsr a15, acclo
mul.da.ll m1, a5 // acc = 0x7fff*1
sra a15, a15
muls.dd.lh m0, m2 // acc -= cs.re*m_data.im
s16i a15, a14, 0
mula.dd.lh m1, m3 // acc += 0x7fff*a_data.im
mula.dd.hl m0, m2 // acc += cs.im*m_data.re
// result in acclo in_data[m].im
rsr a15, acclo
mul.da.ll m1, a5 // acc = 0x7fff*1
sra a15, a15
mula.dd.ll m0, m2 // acc += cs.re*m_data.re
s16i a15, a14, 2
mula.dd.ll m1, m3 // acc += 0x7fff*a_data.re
mula.dd.hh m0, m2 // acc += cs.im*m_data.im
// result in acclo // in_data[ia].re
rsr a15, acclo
mul.da.ll m1, a5 // acc = 0x7fff*1
sra a15, a15
mula.dd.lh m0, m2 // acc += cs.re*m_data.im
s16i a15, a13, 0
mula.dd.lh m1, m3 // acc += 0x7fff*a_data.im
muls.dd.hl m0, m2 // acc -= cs.im*m_data.re
// result in acclo // in_data[ia].im
rsr a15, acclo
sra a15, a15
s16i a15, a13, 2
// Here we have m0 - w, m2 - m_data, m3 - ai_data,
addi a11, a11, 1// ia++
fft2r_l3:
add a11, a11, a6
addi a8, a8, 1 // j++
BNE a8, a7, fft2r_l2 //
slli a7, a7, 1 // ie = ie<<1
// main loop: for (int k = N/2; k > 0; k >>= 1)
srli a6, a6, 1 // a6 = a6>>1
BNEZ a6, fft2r_l1// Jump if > 0
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_fft2r_sc16_ae32_enabled
|
georgevio/IoT-Embedded
| 4,483
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/fft/fixed/dsps_fft2r_sc16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_sc16_arp4_enabled == 1)
// This is matrix multiplication function for esp32p4 processor.
.text
.align 4
.global dsps_fft2r_sc16_arp4_
.type dsps_fft2r_sc16_arp4_,@function
dsps_fft2r_sc16_arp4_:
//esp_err_t dsps_fft2r_sc16_arp4_(int16_t *data, int N, int16_t *w);
add sp,sp,-16
sw s8, 4(sp)
sw s9, 8(sp)
sw s10, 12(sp)
mv a5, a3
li a4, 16
esp.movx.w.sar a4
li a4, 0x7fff
sw a4, 0(sp)
mv x26, sp
esp.vldbc.16.ip q6, x26, 0
#
srli t6, a1, 1 // t6 = N2 = N/2
li t0, 1 // t0 - ie
li t2, 2 // t2 = 2 : limit for the loop N2 > 2
.fft2r_l1:
li t1, 0 // t1 - j
li t4, 0 // t4 = ia = 0;
mv x26, a2 // x26 - pointer to w
.fft2r_l2: // loop for j, a8 - j
esp.vldbc.32.ip q5, x26, 4
add t5, t4, t6 // t5 = m = ia + N2
slli a4, t5, 2 // a4 - pointer for m
slli a3, t4, 2 // a3 - pointer for ia
add a4, a4, a0 // a4 = &data[m*2]
add a3, a3, a0 // a3 = &data[ia*2]
mv x24, a3
mv x25, a4
add t4, t4, t6 // ia += N2 instead of ia++ for each cycle
srli a7, t6, 2 // a7 = t6>> 2
beqz a7, .fft2r_l3_skeep
esp.lp.setup 0, a7, .fft2r_l3 // main butterfly loop
esp.vld.128.ip q0, x25, 0 // Load data[m .. m + 3]
esp.vld.128.ip q2, x24, 0 // Load data[ia .. ia + 3]
esp.cmul.s16 q1, q5, q0, 2
esp.vmul.s16 q2, q2, q6 // q0 = in_data_ia*0x7fff
esp.cmul.s16 q1, q5, q0, 3
esp.vsub.s16 q3, q2, q1 // input[2 * m] = input[2 * ia] - re_temp;
esp.vadd.s16.st.incp q3, x25, q4, q2, q1
.fft2r_l3: esp.vst.128.ip q4, x24, 16
.fft2r_l3_skeep:
add t4, t4, t6 // ia += N2
add t1, t1, 1 // j++
BNE t1, t0, .fft2r_l2
slli t0, t0, 1 // ie = ie<<1
srli t6, t6, 1 // t6 = N2 = N2>>1
bgt t6, t2, .fft2r_l1// N2 > 2
srli t0, t0, 1 // ie = ie>>1
mv x26, a2 // x26 - pointer to w
mv x24, a0
esp.lp.setup 0, t0, .fft2r_l2_1
esp.vldbc.32.ip q2, x26, 4
esp.vldbc.32.ip q7, x26, 4
esp.vunzip.32 q2, q7
esp.vld.l.64.ip q0, x24, 8
esp.vld.l.64.ip q1, x24, 8
esp.vld.h.64.ip q0, x24, 8
esp.vld.h.64.ip q1, x24, -24
esp.vmul.s16 q0, q0, q6
esp.cmul.s16 q3, q2, q1, 2
esp.cmul.s16 q3, q2, q1, 3
esp.vsub.s16 q4, q0, q3
esp.vadd.s16 q5, q0, q3
esp.vst.l.64.ip q5, x24, 8
esp.vst.l.64.ip q4, x24, 8
esp.vst.h.64.ip q5, x24, 8
.fft2r_l2_1: esp.vst.h.64.ip q4, x24, 8
mv x26, a2 // x26 - pointer to w
mv x24, a0
add t0, t0, -1
esp.lp.setup 0, t0, .fft2r_l2_0
esp.vld.128.ip q0, x24, 16 // q0 = ia
esp.vld.128.ip q1, x24,-16 // q1 = m
esp.vld.128.ip q2, x26, 16
esp.vunzip.32 q0, q1
esp.cmul.s16 q3, q2, q1, 2
esp.vmul.s16 q0, q0, q6
esp.cmul.s16 q3, q2, q1, 3
esp.vsub.s16 q1, q0, q3
esp.vadd.s16 q0, q0, q3
esp.vzip.32 q0, q1
esp.vst.128.ip q0, x24, 16
.fft2r_l2_0: esp.vst.128.ip q1, x24, 16
lw s8, 4(sp)
lw s9, 8(sp)
lw s10, 12(sp)
add sp,sp,16
li a0,0
ret
#endif // dsps_fft2r_sc16_arp4_enabled
|
georgevio/IoT-Embedded
| 5,878
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/fft/fixed/dsps_fft2r_sc16_aes3.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_sc16_aes3_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.literal_position
.literal .LC0_5_39, dsps_fft2r_sc16_initialized
.literal .LC1_5_40, 32767
.literal .LC2_5_41, 458756
.literal .LC3_5_42, 458753
# Program Unit: dsps_fft2r_sc16_aes3_
.type dsps_fft2r_sc16_aes3_, @function
.align 4
.global dsps_fft2r_sc16_aes3_
dsps_fft2r_sc16_aes3_: # 0x4
# q3 = 16
# temp_round = 0
# temp_round_ptr = 4
.LBB1_dsps_fft2r_sc16_aes3_: # 0x4
.frequency 1.000 0.000
entry a1,64 #
mov.n a10,a3 # [0]
.type dsp_is_power_of_two, @function
call8 dsp_is_power_of_two # [1] dsp_is_power_of_two
beqz.n a10,.LBB4_dsps_fft2r_sc16_aes3_ # [0]
l32r a8,.LC0_5_39 # [0]
l8ui a8,a8,0 # [2] id:207 dsps_fft2r_sc16_initialized+0x0
beqz.n a8,.LBB6_dsps_fft2r_sc16_aes3_ # [4]
mov.n a9,a1 # [0]
l32r a8,.LC1_5_40 # [1]
addi.n a6,a3,1 # [2]
movi.n a10,16 # [3]
wsr.sar a10 # [4]
movgez a6,a3,a3 # [5]
s16i a8,a1,0 # [6] temp_round
ee.vldbc.16.ip q6,a9,0 # [7] id:209
srai a6,a6,1 # [8]
bltui a6,3,.Lt_0_13826 # [9]
movi.n a5,1 # [0]
.Lt_0_9218: # 0x33
mov.n a13,a4 # [0]
mov.n a9,a2 # [1]
beqz.n a5,.Lt_0_9474 # [2]
srli a3,a6,2 # [0]
movi.n a14,0 # [1]
slli a15,a6,2 # [2]
add.n a8,a15,a9 # [3]
.Lt_0_9986: # 0x43
ee.vldbc.32.ip q5,a13,4 # [0] id:215
loopnez a3,.LBB54_dsps_fft2r_sc16_aes3_ # [1]
.LBB52_dsps_fft2r_sc16_aes3_: # 0x49
ee.vld.128.ip q0,a8,0 # [0*II+0] id:217
ee.vld.128.ip q2,a9,0 # [0*II+1] id:216
ee.cmul.s16 q1,q5,q0,2 # [0*II+2]
ee.vmul.s16 q2,q2,q6 # [0*II+3]
ee.cmul.s16 q1,q5,q0,3 # [0*II+4]
ee.vsubs.s16 q3,q2,q1 # [0*II+6]
ee.vadds.s16.st.incp q3,a8,q3,q2,q1 # [0*II+7] id:221
ee.vst.128.ip q3,a9,16 # [0*II+8] id:222
.LBB54_dsps_fft2r_sc16_aes3_: # 0x62
addi.n a14,a14,1 # [0]
add.n a9,a9,a15 # [1]
add.n a8,a15,a9 # [2]
bne a14,a5,.Lt_0_9986 # [3]
.Lt_0_9474: # 0x6b
slli a5,a5,1 # [0]
srli a6,a6,1 # [1]
bgeui a6,3,.Lt_0_9218 # [2]
srli a10,a5,1 # [0]
beqz.n a10,.Lt_0_14594 # [1]
mov.n a9,a4 # [0]
mv.qr q4,q1 # [1]
mov.n a8,a2 # [2]
mv.qr q1,q0 # [3]
mv.qr q0,q2 # [4]
loopnez a10,.LBB76_dsps_fft2r_sc16_aes3_ # [5]
.LBB74_dsps_fft2r_sc16_aes3_: # 0x89
ee.vld.l.64.ip q0,a8,8 # [0*II+0] id:225
ee.vldbc.32.ip q2,a9,4 # [0*II+1] id:223
ee.vld.l.64.ip q1,a8,8 # [0*II+2] id:226
ee.vldbc.32.ip q3,a9,4 # [0*II+3] id:224
ee.vld.h.64.ip q0,a8,8 # [0*II+4] id:227
ee.vunzip.32 q2,q3 # [0*II+5]
ee.vld.h.64.ip q1,a8,-24 # [0*II+6] id:228
ee.vmul.s16 q0,q0,q6 # [0*II+7]
ee.cmul.s16 q4,q2,q1,2 # [0*II+8]
ee.cmul.s16 q4,q2,q1,3 # [0*II+9]
ee.vadds.s16 q2,q0,q4 # [0*II+11]
ee.vsubs.s16 q3,q0,q4 # [0*II+12]
ee.vst.l.64.ip q2,a8,8 # [0*II+13] id:232
ee.vst.l.64.ip q3,a8,8 # [0*II+14] id:233
ee.vst.h.64.ip q2,a8,8 # [0*II+15] id:234
ee.vst.h.64.ip q3,a8,8 # [0*II+16] id:235
.LBB76_dsps_fft2r_sc16_aes3_: # 0xb9
.frequency 0.608 0.000
st.qr q4,a1,16 # [0] q3
.Lt_0_11778: # 0xbc
ld.qr q3,a1,16 # [0] q3
slli a10,a5,1 # [1]
srli a10,a10,2 # [2]
loopnez a10,.LBB98_dsps_fft2r_sc16_aes3_ # [3]
.LBB96_dsps_fft2r_sc16_aes3_: # 0xc8
ee.vld.128.ip q0,a2,16 # [0*II+0] id:237
ee.vld.128.ip q1,a2,-16 # [0*II+1] id:238
ee.vld.128.ip q2,a4,16 # [0*II+2] id:236
ee.vunzip.32 q0,q1 # [0*II+3]
ee.cmul.s16 q3,q2,q1,2 # [0*II+4]
ee.vmul.s16 q0,q0,q6 # [0*II+5]
ee.cmul.s16 q3,q2,q1,3 # [0*II+6]
ee.vsubs.s16 q1,q0,q3 # [0*II+8]
ee.vadds.s16 q0,q0,q3 # [0*II+9]
ee.vzip.32 q0,q1 # [0*II+10]
ee.vst.128.ip q0,a2,16 # [0*II+11] id:242
ee.vst.128.ip q1,a2,16 # [0*II+12] id:243
.LBB98_dsps_fft2r_sc16_aes3_: # 0xec
movi.n a2,0 # [0]
retw.n # [1]
.Lt_0_13826: # 0xf0
movi.n a5,1 # [0]
j .Lt_0_11778 # [1]
.LBB6_dsps_fft2r_sc16_aes3_: # 0xf5
l32r a2,.LC2_5_41 # [0]
retw.n # [1]
.LBB4_dsps_fft2r_sc16_aes3_: # 0xfa
l32r a2,.LC3_5_42 # [0]
retw.n # [1]
.Lt_0_14594: # 0xff
st.qr q1,a1,16 # [0] q3
j .Lt_0_11778 # [1]
#endif // dsps_fft2r_sc16_ae32_enabled
|
georgevio/IoT-Embedded
| 1,777
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/addc/float/dsps_addc_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_addc_platform.h"
#if (dsps_addc_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_addc_f32_ae32
.type dsps_addc_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_addc_f32_ansi(const float *input, float *output, int len, float C, int step_in, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// output[i * step_out] = input[i * step_in] + C;
// }
// return ESP_OK;
// }
dsps_addc_f32_ae32:
// input - a2
// output - a3
// len - a4
// C - a5
// step_in - a6
// step_out - a7
entry a1, 16
slli a6, a6, 2 // a6 - step_in<<2
slli a7, a7, 2 // a7 - step_out<<2
wfr f0, a5 // a5 - load to the f0
loopnez a4, loop_end_addc_f32_ae32
lsi f1, a2, 0
add.s f2, f1, f0 // f2 = f1 + f0
add.n a2, a2, a6 // input1_ptr+=step_in;
ssi f2, a3, 0
add.n a3, a3, a7 // output+=step_out;
loop_end_addc_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_addc_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,051
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/mul/float/dsps_mul_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_mul_platform.h"
#if (dsps_mul_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_mul_f32_ae32
.type dsps_mul_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_mul_f32_ansi(const float *input1, const float *input2, float *output, int len, int step1, int step2, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// output[i * step_out] = input1[i * step1] * input2[i * step2];
// }
// return ESP_OK;
// }
dsps_mul_f32_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step1 - a6
// step2 - a7
// step_out - stack (a8)
entry a1, 16
l32i.n a8, a1, 16 // Load step_out to the a8 register
slli a6, a6, 2 // a6 - step1<<2
slli a7, a7, 2 // a7 - step2<<2
slli a8, a8, 2 // a8 - step_out<<2
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
loopnez a5, loop_end_mul_f32_ae32
lsi f1, a3, 0
add.n a3, a3, a7 // input2_ptr+=step2;
mul.s f2, f1, f0 // f2 = f1*f0
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
ssi f2, a4, 0
add.n a4, a4, a8 // input2_ptr+=step2;
loop_end_mul_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mul_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,993
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/mul/fixed/dsps_mul_s16_ae32.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_mul_platform.h"
#if (dsps_mul_s16_ae32_enabled == 1)
.text
.align 4
.global dsps_mul_s16_ae32
.type dsps_mul_s16_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_mul_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_mul_s16_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
// l32i.n a10, a1, 16
// s16i a10, a4, 0
// l32i.n a10, a1, 20
// s16i a10, a4, 2
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
// s16i a10, a4, 0
// s16i a6, a4, 2
// s16i a7, a4, 4
// s16i a5, a4, 6
l16si a11, a2, 0
l16si a8, a3, 0
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_mul_s16_ae32
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
mull a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_mul_s16_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mul_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 2,961
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/mul/fixed/dsps_mul_s8_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_mul_platform.h"
#if (dsps_mul_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_mul_s8_aes3
.type dsps_mul_s8_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_mul_s8_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_mul_s8_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .sub_s8_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .sub_s8_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.sub_s8_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .sub_s8_ae32_mode // jump if != 0
bany a3, a15, .sub_s8_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0xf // modulo 8 mask
bany a5, a15, .sub_s8_ae32_mode // jump if != 0
// Process main function for S3
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 4
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_mul_s8_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vmul.s8.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_mul_s8_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.sub_s8_ae32_mode:
l8ui a11, a2, 0
l8ui a8, a3, 0
mull a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_mul_s8_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l8ui a11, a2, 0
l8ui a8, a3, 0
s8i a9, a4, 0 // store result to the putput
mull a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_mul_s8_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mul_s8_aes3_enabled
|
georgevio/IoT-Embedded
| 3,230
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/mul/fixed/dsps_mul_s16_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_mul_platform.h"
#if (dsps_mul_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_mul_s16_aes3
.type dsps_mul_s16_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_mul_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_mul_s16_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .mul_s16_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .mul_s16_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.mul_s16_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .mul_s16_ae32_mode // jump if != 0
bany a3, a15, .mul_s16_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0x7 // modulo 8 mask
bany a5, a15, .mul_s16_ae32_mode // jump if != 0
// Process main function for S3
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 3
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_mul_s16_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vmul.s16.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_mul_s16_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.mul_s16_ae32_mode:
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
l16si a11, a2, 0
l16si a8, a3, 0
mull a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_mul_s16_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
mull a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_mul_s16_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mul_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 1,777
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/mulc/float/dsps_mulc_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_mulc_platform.h"
#if (dsps_mulc_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_mulc_f32_ae32
.type dsps_mulc_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_mulc_f32_ansi(const float *input, float *output, int len, float C, int step_in, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// output[i * step_out] = input[i * step_in] * C;
// }
// return ESP_OK;
// }
dsps_mulc_f32_ae32:
// input - a2
// output - a3
// len - a4
// C - a5
// step_in - a6
// step_out - a7
entry a1, 16
slli a6, a6, 2 // a6 - step_in<<2
slli a7, a7, 2 // a7 - step_out<<2
wfr f0, a5 // a5 - load to the f0
loopnez a4, loop_end_mulc_f32_ae32
lsi f1, a2, 0
mul.s f2, f1, f0 // f2 = f1 * f0
add.n a2, a2, a6 // input1_ptr+=step_in;
ssi f2, a3, 0
add.n a3, a3, a7 // output+=step_out;
loop_end_mulc_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mulc_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,481
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/mulc/fixed/dsps_mulc_s16_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_mulc_platform.h"
#if (dsps_mulc_s16_ae32_enabled == 1)
.text
.align 4
.global dsps_mulc_s16_ae32
.type dsps_mulc_s16_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_mulc_f32_ansi(const float *input, float *output, int len, float C, int step_in, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input[i * step_in] * (int32_t)C;
// output[i * step_out] = (int16_t)(acc>>15);
// }
// return ESP_OK;
// }
dsps_mulc_s16_ae32:
// input - a2
// output - a3
// len - a4
// C - a5
// step_in - a6
// step_out - a7
entry a1, 16
movi.n a8, 15 // output shift
ssr a8
srli a4, a4, 1 // a4 = a4>>1
slli a6, a6, 2 // a6 - step_in<<3, because we load two inputs per loop
slli a7, a7, 1 // a7 - step_out<<2
addi a6, a6, -4;
addi a2, a2, -4;
ldinc m0, a2
loopnez a4, loop_end_mulc_f32_ae32
add.n a2, a2, a6 // input+=step_input;
mul.DA.LL m0, a5
rsr a8, acchi
rsr a9, acclo
src a8, a8, a9 // Here result in a8
s16i a8, a3, 0 // store result to the putput
// rsr a9, acclo
// s16i a9, a3, 0 // store result to the putput
add.n a3, a3, a7 // output+=step_out;
mul.DA.HL m0, a5
rsr a8, acchi
rsr a9, acclo
ldinc m0, a2 // load next data
src a10, a8, a9 // Here result in a8
s16i a10, a3, 0 // store result to the putput
// // rsr a9, acclo
// // s16i a9, a3, 0 // store result to the putput
add.n a3, a3, a7 // output+=step_out;
loop_end_mulc_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mulc_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 2,053
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/sub/float/dsps_sub_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_sub_platform.h"
#if (dsps_sub_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_sub_f32_ae32
.type dsps_sub_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_sub_f32_ae32(const float *input1, const float *input2, float *output, int len, int step1, int step2, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// output[i * step_out] = input1[i * step1] - input2[i * step2];
// }
// return ESP_OK;
// }
dsps_sub_f32_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step1 - a6
// step2 - a7
// step_out - stack (a8)
entry a1, 16
l32i.n a8, a1, 16 // Load step_out to the a8 register
slli a6, a6, 2 // a6 - step1<<2
slli a7, a7, 2 // a7 - step2<<2
slli a8, a8, 2 // a8 - step_out<<2
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
loopnez a5, loop_end_sub_f32_ae32
lsi f1, a3, 0
add.n a3, a3, a7 // input2_ptr+=step2;
sub.s f2, f0, f1 // f2 = f0 - f1
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
ssi f2, a4, 0
add.n a4, a4, a8 // input2_ptr+=step2;
loop_end_sub_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_sub_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,962
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/sub/fixed/dsps_sub_s8_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_sub_platform.h"
#if (dsps_sub_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_sub_s8_aes3
.type dsps_sub_s8_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_sub_s8_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_sub_s8_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .sub_s8_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .sub_s8_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.sub_s8_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .sub_s8_ae32_mode // jump if != 0
bany a3, a15, .sub_s8_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0xf // modulo 8 mask
bany a5, a15, .sub_s8_ae32_mode // jump if != 0
// Process main function for S3
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 4
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_sub_s8_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vsubs.s8.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_sub_s8_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.sub_s8_ae32_mode:
l8ui a11, a2, 0
l8ui a8, a3, 0
sub a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_sub_s8_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l8ui a11, a2, 0
l8ui a8, a3, 0
s8i a9, a4, 0 // store result to the putput
sub a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_sub_s8_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_sub_s8_aes3_enabled
|
georgevio/IoT-Embedded
| 3,231
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/sub/fixed/dsps_sub_s16_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_sub_platform.h"
#if (dsps_sub_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_sub_s16_aes3
.type dsps_sub_s16_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_sub_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_sub_s16_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .sub_s16_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .sub_s16_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.sub_s16_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .sub_s16_ae32_mode // jump if != 0
bany a3, a15, .sub_s16_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0x7 // modulo 8 mask
bany a5, a15, .sub_s16_ae32_mode // jump if != 0
// Process main function for S3
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 3
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_sub_s16_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vsubs.s16.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_sub_s16_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.sub_s16_ae32_mode:
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
l16si a11, a2, 0
l16si a8, a3, 0
sub a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_sub_s16_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
sub a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_sub_s16_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_sub_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 1,992
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/sub/fixed/dsps_sub_s16_ae32.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_sub_platform.h"
#if (dsps_sub_s16_ae32_enabled == 1)
.text
.align 4
.global dsps_sub_s16_ae32
.type dsps_sub_s16_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_sub_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_sub_s16_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
// l32i.n a10, a1, 16
// s16i a10, a4, 0
// l32i.n a10, a1, 20
// s16i a10, a4, 2
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
// s16i a10, a4, 0
// s16i a6, a4, 2
// s16i a7, a4, 4
// s16i a5, a4, 6
l16si a11, a2, 0
l16si a8, a3, 0
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_sub_s16_ae32
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
sub a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_sub_s16_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_sub_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 2,053
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/add/float/dsps_add_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_add_platform.h"
#if (dsps_add_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_add_f32_ae32
.type dsps_add_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_add_f32_ansi(const float *input1, const float *input2, float *output, int len, int step1, int step2, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// output[i * step_out] = input1[i * step1] + input2[i * step2];
// }
// return ESP_OK;
// }
dsps_add_f32_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step1 - a6
// step2 - a7
// step_out - stack (a8)
entry a1, 16
l32i.n a8, a1, 16 // Load step_out to the a8 register
slli a6, a6, 2 // a6 - step1<<2
slli a7, a7, 2 // a7 - step2<<2
slli a8, a8, 2 // a8 - step_out<<2
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
loopnez a5, loop_end_add_f32_ae32
lsi f1, a3, 0
add.n a3, a3, a7 // input2_ptr+=step2;
add.s f2, f1, f0 // f2 = f1 + f0
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
ssi f2, a4, 0
add.n a4, a4, a8 // input2_ptr+=step2;
loop_end_add_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_add_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 3,232
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/add/fixed/dsps_add_s16_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_add_platform.h"
#if (dsps_add_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_add_s16_aes3
.type dsps_add_s16_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_add_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_add_s16_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .add_s16_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .add_s16_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.add_s16_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .add_s16_ae32_mode // jump if != 0
bany a3, a15, .add_s16_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0x7 // modulo 8 mask
bany a5, a15, .add_s16_ae32_mode // jump if != 0
// Process main function for S3
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 3
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_add_s16_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vadds.s16.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_add_s16_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.add_s16_ae32_mode:
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
l16si a11, a2, 0
l16si a8, a3, 0
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_add_s16_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_add_s16_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_add_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,962
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/add/fixed/dsps_add_s8_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_add_platform.h"
#if (dsps_add_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_add_s8_aes3
.type dsps_add_s8_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_add_s8_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_add_s8_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .add_s8_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .add_s8_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.add_s8_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .add_s8_ae32_mode // jump if != 0
bany a3, a15, .add_s8_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0xf // modulo 8 mask
bany a5, a15, .add_s8_ae32_mode // jump if != 0
// Process main function for S3
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 4
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_add_s8_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vadds.s8.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_add_s8_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.add_s8_ae32_mode:
l8ui a11, a2, 0
l8ui a8, a3, 0
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_add_s8_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l8ui a11, a2, 0
l8ui a8, a3, 0
s8i a9, a4, 0 // store result to the putput
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_add_s8_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_add_s8_aes3_enabled
|
georgevio/IoT-Embedded
| 2,494
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/math/add/fixed/dsps_add_s16_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_add_platform.h"
#if (dsps_add_s16_ae32_enabled == 1)
.text
.align 4
.global dsps_add_s16_ae32
.type dsps_add_s16_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_add_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_add_s16_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
// l32i.n a10, a1, 16
// s16i a10, a4, 0
// l32i.n a10, a1, 20
// s16i a10, a4, 2
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
// s16i a10, a4, 0
// s16i a6, a4, 2
// s16i a7, a4, 4
// s16i a5, a4, 6
l16si a11, a2, 0
l16si a8, a3, 0
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_add_s16_ae32
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_add_s16_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_add_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 2,238
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/conv/float/dsps_corr_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_conv_platform.h"
#if (dsps_corr_f32_ae32_enabled == 1)
#include "dsps_dotprod_f32_m_ae32.S"
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_corr_f32_ae32
.type dsps_corr_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_corr_f32_ansi(const float *Signal, const int siglen, const float *Pattern, const int patlen, float *dest)
//{
// for (size_t n = 0; n < (siglen - patlen); n++) {
// float k_corr = 0;
// for (size_t m = 0; m < patlen; m++) {
// k_corr += Signal[n + m] * Pattern[m];
// }
// dest[n] = k_corr;
// }
// return ESP_OK;
//}
dsps_corr_f32_ae32:
// Signal - a2
// siglen - a3
// Pattern - a4
// patlen - a5
// dest - a6
// a11 - loop length
entry a1, 16
// Array increment for floating point data should be 4
movi.n a8, 4
movi.n a13, 4
sub a11, a3, a5 // a11 = loop length
addi a11, a11, 1
addi a12, a2, 0 // move input pointer to the a12
movi.n a9, 0
movi.n a14, 0
corr_loop:
// Clear initial state of the result register
addi a10, a4, 0 // a10 - pattern
movi.n a9, 0 // clear a9
wfr f1, a9 // clrar f1
// a12 - input1
// a10 - input2
// a5 - length
// a8 - 4, step in arrays
// a9 - 0
dotprod_f32_ae32 a12, a10, a5, a9, a8;
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // y++ - increment output pointer
addi a12, a12, 4 // Signal++
addi a11, a11, -1
bnez a11, corr_loop
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_corr_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 3,715
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/conv/float/dsps_ccorr_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_conv_platform.h"
#if (dsps_ccorr_f32_ae32_enabled == 1)
#include "dsps_conv_f32_m_ae32.S"
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_ccorr_f32_ae32
.type dsps_ccorr_f32_ae32,@function
// The function implements the C code from dsps_ccorr_f32_ansi:
//esp_err_t dsps_ccorr_f32_ansi(const float *Signal, const int siglen, const float *Kernel, const int kernlen, float *corrout);
//
dsps_ccorr_f32_ae32:
// Signal - a2
// siglen - a3
// Kernel - a4
// kernlen - a5
// corrout - a6
//
// a11 - loop length
entry a1, 16
// Array increment for floating point data should be 4
sub a10, a3, a5
bgez a10, dsps_ccorr_positive
addi a10, a2, 0
addi a2, a4, 0
addi a4, a10, 0
addi a10, a3, 0
addi a3, a5, 0
addi a5, a10, 0
dsps_ccorr_positive:
movi.n a8, 4
addi a11, a5, 0 // lkern - loop counter
movi.n a14, 0
addi a9, a14, 1
movi.n a7, 4
movi.n a8, -4
mull a13, a5, a7 // a13 - kernlen*4
add a13, a13, a4 // a13 - Kernel[kernlen]
addi a13, a13, -4 // a13 - Kernel[kernlen - 1]
ccorr_loop1:
// Clear initial state of the result register
addi a10, a13, 0 // a10 - Kernel
addi a12, a2, 0 // a12 - Signal
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[0]
// a10 - kern[n];
// a9 - n+1
// a7 - 4,
// a8 - -4,
conv_f32_ae32 a12, a10, a9, a7, a7, loop1
addi a9, a9, 1 // (n+1)++
addi a13, a13, -4 // kern[n] - a4--
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a11, a11, -1
bnez a11, ccorr_loop1
// a11 - loop counter = siglen - kernlen - 1
addi a9, a2, 4 // sig[1] - sig[kmin]
addi a13, a5, 0
// skip loop if 0
sub a11, a3, a5 // a11 - loop counter
beqz a11, skip_ccorr_loop2
ccorr_loop2:
// Clear initial state of the result register
addi a12, a9, 0 // a12 - Signal[kmin]
addi a10, a4, 0 // a10 - Kernel
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[kmin]
// a10 - kern[0];
// a11 - kernlen
// a7 - 4,
conv_f32_ae32 a12, a10, a13, a7, a7, loop2
addi a9, a9, 4 // in1++
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a11, a11, -1
bnez a11, ccorr_loop2
skip_ccorr_loop2:
// a9 - the same
addi a11, a5, -1
addi a13, a5, -1
ccorr_loop3:
// Clear initial state of the result register
addi a12, a9, 0 // a12 - Signal[kmin]
addi a10, a4, 0 // a10 - Kernel
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[kmin]
// a10 - kern[n - kmin];
// a11 - length
// a7 - 4,
// a8 - -4,
conv_f32_ae32 a12, a10, a11, a7, a7, loop3
addi a9, a9, 4 // n++
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a11, a11, -1
bnez a11, ccorr_loop3
skip_ccorr_loop3:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_ccorr_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,309
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/conv/float/dsps_conv_f32_m_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro conv_f32_ae32 x1 x2 count step1 step2 name
// This macro calculates floating point dot product for count float samples
// x1, x2 - input arrays
// count - amount of samples
// step1 - start step
//,step2 - A register for array step increment. (should be divided by 4)
// f1 - contains initial value
//
// result in f1
//
// Macros body:
// f1 += x1[]*x2[]; i: 0..counter-1
// affected: f0, f1, f2
// Example: conv_f32_ae32 a2 a3 a5 a8 a9
// a8 == 4, step is 4 bytes
// a5 == 32, length of array is 32
//
lsxp f0, \x2, \step2
loopnez \count, loop_mac_end_m_ae32\name
lsxp f2, \x1, \step1
madd.s f1, f2, f0
lsxp f0, \x2, \step2
loop_mac_end_m_ae32\name:
.endm
|
georgevio/IoT-Embedded
| 3,716
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/conv/float/dsps_conv_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_conv_platform.h"
#if (dsps_conv_f32_ae32_enabled == 1)
#include "dsps_conv_f32_m_ae32.S"
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_conv_f32_ae32
.type dsps_conv_f32_ae32,@function
// The function implements the C code from dsps_conv_f32_ansi:
//esp_err_t dsps_conv_f32_ansi(const float *Signal, const int siglen, const float *Kernel, const int kernlen, float *convout);
//
dsps_conv_f32_ae32:
// Signal - a2
// siglen - a3
// Kernel - a4
// kernlen - a5
// convout - a6
//
// a11 - loop length
entry a1, 16
// Array increment for floating point data should be 4
sub a10, a3, a5
bgez a10, dsps_conv_positive
addi a10, a2, 0
addi a2, a4, 0
addi a4, a10, 0
addi a10, a3, 0
addi a3, a5, 0
addi a5, a10, 0
dsps_conv_positive:
movi.n a8, 4
addi a11, a5, 0 // lkern - loop counter
movi.n a14, 0
addi a9, a14, 1
movi.n a7, 4
movi.n a8, -4
conv_loop1:
// Clear initial state of the result register
addi a10, a4, 0 // a10 - Kernel
addi a12, a2, 0 // a12 - Signal
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[0]
// a10 - kern[n];
// a9 - n+1
// a7 - 4,
// a8 - -4,
conv_f32_ae32 a12, a10, a9, a7, a8, loop1
addi a9, a9, 1 // (n+1)++
addi a4, a4, 4 // kern[n] - a4++
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a11, a11, -1
bnez a11, conv_loop1
// a11 - loop counter = siglen - kernlen - 1
addi a9, a2, 0 // sig[1] - sig[kmin]
addi a13, a5, 0
// skip loop if 0
sub a11, a3, a5 // a11 - loop counter
beqz a11, skip_conv_loop2
conv_loop2:
// Clear initial state of the result register
addi a12, a9, 4 // a12 - Signal[kmin]
addi a10, a4, -4 // a10 - Kernel
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[kmin]
// a10 - kern[n - kmin];
// a11 - length
// a7 - 4,
// a8 - -4,
conv_f32_ae32 a12, a10, a13, a7, a8, loop2
addi a9, a9, 4 // (n+1)++
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a11, a11, -1
bnez a11, conv_loop2
skip_conv_loop2:
// sub a11, a3, a5 // a11 - loop counter
// beqz a11, skip_conv_loop3
// a9 - the same
addi a11, a5, -1
addi a13, a5, -1
// beqz a11, skip_conv_loop3
conv_loop3:
// Clear initial state of the result register
addi a12, a9, 4 // a12 - Signal[kmin]
addi a10, a4, -4 // a10 - Kernel
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[kmin]
// a10 - kern[n - kmin];
// a11 - length
// a7 - 4,
// a8 - -4,
conv_f32_ae32 a12, a10, a13, a7, a8, loop3
addi a9, a9, 4 // (n+1)++
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a13, a13, -1
addi a11, a11, -1
bnez a11, conv_loop3
skip_conv_loop3:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_conv_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,926
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprod_f32_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dsps_dotprod_f32_arp4_enabled == 1)
.text
.align 4
.global dsps_dotprod_f32_arp4
.type dsps_dotprod_f32_arp4,@function
// The function implements the following C code:
//esp_err_t dsps_dotprod_f32(const float* src1, const float* src2, float* dest, int len)
//{
// float acc = 0;
// for (int i=0 ; i< len ; i++)
// {
// acc += src1[i]*src2[i];
// }
// *dest = acc;
// return ESP_OK;
//}
dsps_dotprod_f32_arp4:
// src1 - a0
// src2 - a1
// dest - a2
// len - a3
add sp,sp,-16
fmv.w.x fa2,zero
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, 4
add a1, a1, 4
li a4, 2
ble a3, a4, .loop_less_2
// Loop when len > 2
esp.lp.setup 0, a3, .dotprod_loop
fmadd.s fa2, fa0, fa1, fa2
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, 4
.dotprod_loop: add a1, a1, 4
fsw fa2, 0(a2)
add sp,sp,16
li a0,0
ret
// Loop when len <=2
.loop_less_2:
fmadd.s fa2, fa0, fa1, fa2
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, 4
add a1, a1, 4
add a3, a3, -1
bnez a3, .loop_less_2
fsw fa2, 0(a2)
add sp,sp,16
li a0,0
ret
#endif // dotprode_f32_arp4_enabled
|
georgevio/IoT-Embedded
| 1,942
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprode_f32_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dsps_dotprod_f32_arp4_enabled == 1)
.text
.align 4
.global dsps_dotprode_f32_arp4
.type dsps_dotprode_f32_arp4,@function
// The function implements the following C code:
//esp_err_t dsps_dotprode_f32(const float *src1, const float *src2, float *dest, int len, int step1, int step2)
//{
// float acc = 0;
// for (int i = 0 ; i < len ; i++) {
// acc += src1[i * step1] * src2[i * step2];
// }
// *dest = acc;
// return ESP_OK;
//}
dsps_dotprode_f32_arp4:
// src1 - a0
// src2 - a1
// dest - a2
// len - a3
add sp,sp,-16
fmv.w.x fa2,zero
slli a4, a4, 2 // step address increment by 4
slli a5, a5, 2 // step address increment by 4
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, a4
add a1, a1, a5
li a6, 2
ble a3, a6, .loop_less_2
// Loop when len > 2
esp.lp.setup 0, a3, .dotprod_loop
fmadd.s fa2, fa0, fa1, fa2
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, a4
.dotprod_loop: add a1, a1, a5
fsw fa2, 0(a2)
add sp,sp,16
li a0,0
ret
// Loop when len <=2
.loop_less_2:
fmadd.s fa2, fa0, fa1, fa2
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, a4
add a1, a1, a5
add a3, a3, -1
bnez a3, .loop_less_2
fsw fa2, 0(a2)
add sp,sp,16
li a0,0
ret
#endif // dotprode_f32_arp4_enabled
|
georgevio/IoT-Embedded
| 1,732
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprod_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dotprod_f32_ae32_enabled == 1)
#include "dsps_dotprod_f32_m_ae32.S"
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_dotprod_f32_ae32
.global .dsps_dotprod_f32_ae32_body
.type dsps_dotprod_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_dotprod_f32_ae32(const float* src1, const float* src2, float* dest, int len)
//{
// float acc = 0;
// for (int i=0 ; i< len ; i++)
// {
// acc += src1[i]*src2[i];
// }
// *dest = acc;
// return ESP_OK;
//}
dsps_dotprod_f32_ae32:
// src1 - a2
// src2 - a3
// dest - a4
// len - a5
entry a1, 16
.dsps_dotprod_f32_ae32_body:
// Array increment for floating point data should be 4
movi.n a8, 4
// Clear initial state of the result register
movi.n a9, 0
wfr f1, a9
// a2 - input1
// a3 - input2
// a5 - length
// a8 - 4, step in arrays
dotprod_f32_ae32 a2, a3, a5, a9, a8;
ssi f1, a4, 0 // Store result from f1 to memory at a4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dotprode_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,719
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprode_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dotprode_f32_ae32_enabled == 1)
#include "dsps_dotprode_f32_m_ae32.S"
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_dotprode_f32_ae32
.type dsps_dotprode_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_dotprod_f32_ae32(const float* src1, const float* src2, float* dest, int len)
//{
// float acc = 0;
// for (int i=0 ; i< len ; i++)
// {
// acc += src1[i]*src2[i];
// }
// *dest = acc;
// return ESP_OK;
//}
dsps_dotprode_f32_ae32:
// src1 - a2
// src2 - a3
// dest - a4
// len - a5
// step1- a6
// step2- a7
entry a1, 16
// Array increment for floating point data should be 4
slli a6,a6, 2
slli a7,a7, 2
// Clear initial state of the result register
movi.n a9, 0
wfr f1, a9
// a2 - input1
// a3 - input2
// a5 - length
// a6,a7, step in arrays
dotprode_f32_ae32 a2, a3, a5, a6, a7;
ssi f1, a4, 0 // Store result from f1 to memory at a4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //dotprode_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,242
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprod_f32_aes3.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dsps_dotprod_f32_aes3_enabled == 1)
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_dotprod_f32_aes3
.global .dsps_dotprod_f32_ae32_body
.type dsps_dotprod_f32_aes3,@function
// The function implements the following C code:
//esp_err_t dsps_dotprod_f32_ae32(const float* src1, const float* src2, float* dest, int len)
//{
// float acc = 0;
// for (int i=0 ; i< len ; i++)
// {
// acc += src1[i]*src2[i];
// }
// *dest = acc;
// return ESP_OK;
//}
dsps_dotprod_f32_aes3:
// src1 - a2
// src2 - a3
// dest - a4
// len - a5
entry a1, 16
// Check length and align
movi.n a10, 3
and a10, a10, a5
movi.n a9, 15
or a11, a3, a2
and a11, a9, a11
or a10, a10, a11
beqz a10, .dsps_dotprod_f32_aes3_body
// Call Esp32 function
J .dsps_dotprod_f32_ae32_body
.dsps_dotprod_f32_aes3_body:
// Clear initial state of the result register
movi.n a9, 0
wfr f0, a9
wfr f1, a9
wfr f2, a9
wfr f3, a9
// a2 - input1
// a3 - input2
// a5 - length
srli a6, a5, 2 // N count
// lsx f0, a2, a9
loopnez a6, .loop_mac_end_m_ae32
EE.LDF.128.IP f11, f10, f9, f8, a2, 16
EE.LDF.128.IP f7, f6, f5, f4, a3, 16
madd.s f0, f4, f8 // f0 = X11*Y11
madd.s f1, f5, f9 // f1 = X12*Y11
madd.s f2, f6, f10 // f2 = X13*Y11
madd.s f3, f7, f11 // f3 = X14*Y11
.loop_mac_end_m_ae32:
add.s f0, f0, f1
add.s f0, f0, f2
add.s f0, f0, f3
ssi f0, a4, 0 // Store result from f1 to memory at a4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dotprode_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,440
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprod_f32_m_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro dotprod_f32_ae32 x1 x2 count step1 step2
// This macro calculates floating point dot product for count float samples
// x1, x2 - input arrays
// count - amount of samples
// step1 - start step
//,step2 - A register for array step increment. (should be divided by 4)
// f1 - contains initial value
//
// result in f1
//
// Macros body:
// f1 += x1[i*step1]*x2[i*step2]; i: 0..counter-1
// affected: f0, f1, f2
// Example: dotprod_f32_ae32 a2 a3 a5 a8 a9
// a8 == 4, step is 4 bytes
// a5 == 32, length of array is 32
//
// mov \step1, \step2
lsx f0, \x2, \step1
// sub \x1, \x1, \step1 // To compensate first increment
loopnez \count, .loop_mac_end_m_ae32
lsx f2, \x1, \step1
madd.s f1, f2, f0
add.n \step1, \step1, \step2
lsx f0, \x2, \step1
.loop_mac_end_m_ae32:
.endm
|
georgevio/IoT-Embedded
| 1,387
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprode_f32_m_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro dotprode_f32_ae32 x1 x2 count step1 step2
// This macro calculates floating point dot product for count float samples
// x1, x2 - input arrays
// count - amount of samples
// step1,step2 - A register for array step. (should be divided by 4)
// f1 - contains initial value
//
// result in f1
//
// Macros body:
// f1 += x1[i*step1]*x2[i*step2]; i: 0..counter-1
// affected: f0, f1, f2
// Example: dotprod_f32_ae32 a2 a3 a5 a8 a9
// a8 == 4, step is 4 bytes
// a5 == 32, length of array is 32
//
lsi f0, \x2, 0
sub \x1, \x1, \step1 // To compensate first increment
loopnez \count, .loop_mace_end_m_ae32
add.n \x1, \x1, \step1
lsi f2, \x1, 0
madd.s f1, f2, f0
add.n \x2, \x2, \step2
lsi f0, \x2, 0
.loop_mace_end_m_ae32:
.endm
|
georgevio/IoT-Embedded
| 14,933
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_s16_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_53, 458755
# Program Unit: dspi_dotprod_s16_aes3
.type dspi_dotprod_s16_aes3, @function
.align 4
.global dspi_dotprod_s16_aes3
dspi_dotprod_s16_aes3: # 0x4
.LBB1_dspi_dotprod_s16_aes3: # 0x4
entry a1,64 #
l32i.n a10,a2,4 # [0] id:678
l32i.n a11,a2,12 # [1] id:677
mull a8,a10,a5 # [2]
blt a11,a8,.LBB81_dspi_dotprod_s16_aes3 # [4]
l32i.n a12,a2,8 # [0] id:679
l32i.n a9,a2,16 # [1] id:680
mull a13,a12,a6 # [2]
blt a9,a13,.LBB81_dspi_dotprod_s16_aes3 # [4]
l32i.n a15,a3,4 # [0] id:682
l32i.n a14,a3,12 # [1] id:681
mull a13,a15,a5 # [2]
blt a14,a13,.LBB81_dspi_dotprod_s16_aes3 # [4]
l32i.n a8,a3,16 # [0] id:684
l32i.n a9,a3,8 # [1] id:683
s32i.n a9,a1,24 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB81_dspi_dotprod_s16_aes3 # [5]
l32i.n a8,a3,0 # [0] id:685
s32i.n a8,a1,20 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_34050 # [2]
bne a14,a13,.Lt_0_34050 # [0]
bnei a15,1,.Lt_0_34050 # [0]
l32i.n a9,a1,24 # [0] gra_spill_temp_2
beqi a9,1,.Lt_0_18178 # [2]
.Lt_0_34050: # 0x43
.Lt_0_18434: # 0x43
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
.type dspi_dotprod_s16_ansi, @function
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB81_dspi_dotprod_s16_aes3: # 0x56
l32r a2,.LC0_1_53 # [0]
retw.n # [1]
.Lt_0_18178: # 0x5b
addi.n a13,a10,-1 # [0]
bnez a13,.Lt_0_34818 # [1]
addi.n a14,a12,-1 # [0]
bnez a14,.Lt_0_34818 # [1]
extui a15,a5,0,3 # [0]
bnez.n a15,.Lt_0_34818 # [1]
blti a6,4,.Lt_0_34818 # [0]
movi.n a8,32 # [0]
bge a8,a5,.Lt_0_35330 # [1]
extui a9,a5,0,1 # [0]
bnez a9,.LBB28_dspi_dotprod_s16_aes3 # [1]
.Lt_0_35330: # 0x78
.Lt_0_20226: # 0x78
mov.n a3,a6 # [0]
addi a10,a5,-24 # [1]
mull a13,a11,a12 # [2]
l32i.n a15,a1,20 # [3] gra_spill_temp_1
l32i.n a2,a2,0 # [4] id:686
movi.n a14,0 # [5]
wur.sar_byte a14 # [6]
wur.accx_0 a14 # [8]
wur.accx_1 a14 # [9]
ee.vld.128.ip q0,a15,16 # [10] id:690
slli a13,a13,1 # [11]
s32i.n a13,a1,16 # [12] gra_spill_temp_0
beqz a10,.LBB32_dspi_dotprod_s16_aes3 # [13]
.Lt_0_23298: # 0x99
.Lt_0_22786: # 0x99
addi a8,a5,-16 # [0]
beqz a8,.LBB38_dspi_dotprod_s16_aes3 # [1]
.Lt_0_24834: # 0x9f
.Lt_0_24322: # 0x9f
addi a9,a5,-8 # [0]
beqz a9,.LBB44_dspi_dotprod_s16_aes3 # [1]
.Lt_0_26370: # 0xa5
.Lt_0_25858: # 0xa5
addi a10,a5,-32 # [0]
beqz a10,.LBB50_dspi_dotprod_s16_aes3 # [1]
.Lt_0_27906: # 0xab
.Lt_0_27394: # 0xab
addi a11,a5,-64 # [0]
beqz a11,.LBB56_dspi_dotprod_s16_aes3 # [1]
movi.n a12,64 # [0]
bge a12,a5,.Lt_0_30722 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a2,16 # [1] id:762
ee.ld.128.usar.ip q2,a2,16 # [2] id:763
ee.src.q.ld.ip q3,a2,16,q1,q2 # [4] id:764
beqz.n a3,.Lt_0_30722 # [5]
slli a8,a5,1 # [0]
l32i.n a14,a1,16 # [1] gra_spill_temp_0
addi a13,a5,31 # [2]
movgez a13,a5,a5 # [3]
srai a13,a13,5 # [4]
sub a14,a14,a8 # [5]
addi a14,a14,16 # [6]
addi.n a13,a13,-1 # [7]
.Lt_0_31490: # 0xd9
addi.n a12,a12,1 # [0]
movi.n a9,32 # [1]
beqz.n a13,.Lt_0_31746 # [2]
loopnez a13,.LBB221_dspi_dotprod_s16_aes3 # [0]
.LBB219_dspi_dotprod_s16_aes3: # 0xe2
ee.vld.128.ip q5,a15,16 # [0*II+0] id:766
ee.vmulas.s16.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:765
ee.vld.128.ip q0,a15,16 # [0*II+2] id:768
ee.vmulas.s16.accx.ld.ip.qup q1,a2,16,q5,q2,q3,q4 # [0*II+3] id:767
ee.vld.128.ip q5,a15,16 # [0*II+4] id:770
ee.vmulas.s16.accx.ld.ip.qup q2,a2,16,q0,q3,q4,q1 # [0*II+5] id:769
ee.vld.128.ip q0,a15,16 # [0*II+6] id:772
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+7] id:771
.LBB221_dspi_dotprod_s16_aes3: # 0xfe
.Lt_0_31746: # 0xfe
ee.vmulas.s16.accx.ld.ip.qup q5,a2,16,q0,q1,q2,q3 # [0] id:773
movi.n a10,-16 # [1]
ee.vld.128.ip q0,a15,16 # [2] id:774
ee.vld.128.ip q6,a15,16 # [3] id:776
ee.vmulas.s16.accx.ld.xp.qup q7,a2,a14,q0,q2,q3,q5 # [4] id:775
ee.vld.128.ip q4,a15,16 # [5] id:779
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a10,q6,q3,q5,q7 # [6] id:777
ee.ld.128.usar.xp q1,a2,a9 # [7] id:778
ee.vld.128.ip q0,a15,16 # [8] id:781
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q4,q5,q1,q2 # [9] id:780
bne a12,a3,.Lt_0_31490 # [10]
.Lt_0_30722: # 0x122
.Lt_0_30466: # 0x122
rur.accx_0 a9 # [0]
rur.accx_1 a10 # [1]
blti a7,1,.Lt_0_33282 # [2]
movi.n a2,0 # [0]
addi a13,a7,-33 # [1]
addi.n a14,a7,-1 # [2]
ssr a14 # [3]
sra a12,a10 # [4]
src a11,a10,a9 # [5]
movgez a11,a12,a13 # [6]
addi.n a11,a11,1 # [7]
srai a11,a11,1 # [8]
s16i a11,a4,0 # [9] id:787
retw.n # [10]
.Lt_0_34818: # 0x148
.Lt_0_19458: # 0x148
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB32_dspi_dotprod_s16_aes3: # 0x15b
ee.ld.128.usar.ip q1,a2,16 # [0] id:691
ee.ld.128.usar.ip q2,a2,16 # [1] id:692
ee.src.q.ld.ip q3,a2,16,q1,q2 # [3] id:693
beqz.n a6,.Lt_0_23298 # [4]
addi a12,a13,-32 # [0]
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
loopgtz a6,.LBB107_dspi_dotprod_s16_aes3 # [3]
.LBB105_dspi_dotprod_s16_aes3: # 0x170
ee.vld.128.ip q4,a15,16 # [0*II+0] id:695
ee.vmulas.s16.accx.ld.xp.qup q1,a2,a12,q0,q1,q2,q3 # [0*II+1] id:694
ee.vld.128.ip q5,a15,16 # [0*II+2] id:697
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q4,q2,q3,q1 # [0*II+3] id:696
ee.ld.128.usar.xp q1,a2,a10 # [0*II+4] id:698
ee.vld.128.ip q0,a15,16 # [0*II+5] id:700
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q5,q3,q1,q2 # [0*II+6] id:699
.LBB107_dspi_dotprod_s16_aes3: # 0x188
j .Lt_0_23298 # [0]
.LBB38_dspi_dotprod_s16_aes3: # 0x18b
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
srli a3,a6,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:701
ee.ld.128.usar.ip q2,a2,16 # [5] id:702
addi a12,a12,-16 # [7]
ee.src.q.ld.xp q3,a2,a12,q1,q2 # [8] id:703
loopnez a3,.LBB130_dspi_dotprod_s16_aes3 # [9]
.LBB128_dspi_dotprod_s16_aes3: # 0x1a3
ee.vld.128.ip q4,a15,16 # [0*II+0] id:705
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a11,q0,q1,q2,q3 # [0*II+1] id:704
ee.ld.128.usar.xp q1,a2,a10 # [0*II+2] id:706
ee.vld.128.ip q0,a15,16 # [0*II+3] id:708
ee.vmulas.s16.accx.ld.xp.qup q4,a2,a12,q4,q2,q1,q3 # [0*II+4] id:707
ee.vld.128.ip q5,a15,16 # [0*II+5] id:710
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q0,q1,q3,q4 # [0*II+6] id:709
ee.ld.128.usar.xp q1,a2,a10 # [0*II+7] id:711
ee.vld.128.ip q0,a15,16 # [0*II+8] id:713
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a12,q5,q3,q1,q2 # [0*II+9] id:712
.LBB130_dspi_dotprod_s16_aes3: # 0x1c5
j .Lt_0_24834 # [0]
.LBB44_dspi_dotprod_s16_aes3: # 0x1c8
srli a3,a3,2 # [0]
movi.n a10,-16 # [1]
l32i.n a11,a1,16 # [2] gra_spill_temp_0
addi a8,a2,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a8,a10 # [5] id:714
ee.ld.128.usar.xp q1,a8,a11 # [6] id:715
ee.src.q.ld.xp q3,a8,a10,q1,q2 # [8] id:716
ee.ld.128.usar.xp q2,a8,a11 # [9] id:717
loopnez a3,.LBB153_dspi_dotprod_s16_aes3 # [10]
.LBB151_dspi_dotprod_s16_aes3: # 0x1e4
ee.vld.128.ip q4,a15,16 # [0*II+0] id:719
ee.vmulas.s16.accx.ld.xp.qup q3,a8,a10,q0,q1,q2,q3 # [0*II+1] id:718
ee.ld.128.usar.xp q1,a8,a11 # [0*II+2] id:720
ee.vld.128.ip q0,a15,16 # [0*II+3] id:722
ee.vmulas.s16.accx.ld.xp.qup q4,a8,a10,q4,q2,q1,q3 # [0*II+4] id:721
ee.ld.128.usar.xp q3,a8,a11 # [0*II+5] id:723
ee.vld.128.ip q5,a15,16 # [0*II+6] id:725
ee.vmulas.s16.accx.ld.xp.qup q4,a8,a10,q0,q1,q3,q4 # [0*II+7] id:724
ee.ld.128.usar.xp q1,a8,a11 # [0*II+8] id:726
ee.vld.128.ip q0,a15,16 # [0*II+9] id:728
ee.vmulas.s16.accx.ld.xp.qup q3,a8,a10,q5,q3,q1,q4 # [0*II+10] id:727
ee.ld.128.usar.xp q2,a8,a11 # [0*II+11] id:729
.LBB153_dspi_dotprod_s16_aes3: # 0x20c
mov.n a2,a8 # [0]
j .Lt_0_26370 # [1]
.LBB50_dspi_dotprod_s16_aes3: # 0x211
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:730
ee.ld.128.usar.ip q2,a2,16 # [5] id:731
sub a12,a12,a13 # [6]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [8] id:732
addi a12,a12,16 # [9]
loopnez a3,.LBB176_dspi_dotprod_s16_aes3 # [10]
.LBB174_dspi_dotprod_s16_aes3: # 0x22c
ee.vld.128.ip q5,a15,16 # [0*II+0] id:734
ee.vmulas.s16.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:733
ee.vld.128.ip q1,a15,16 # [0*II+2] id:736
ee.vmulas.s16.accx.ld.xp.qup q0,a2,a12,q5,q2,q3,q4 # [0*II+3] id:735
ee.vld.128.ip q5,a15,16 # [0*II+4] id:739
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q1,q3,q4,q0 # [0*II+5] id:737
ee.ld.128.usar.xp q1,a2,a10 # [0*II+6] id:738
ee.vld.128.ip q0,a15,16 # [0*II+7] id:741
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+8] id:740
.LBB176_dspi_dotprod_s16_aes3: # 0x24b
j .Lt_0_27906 # [0]
.LBB56_dspi_dotprod_s16_aes3: # 0x24e
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:742
ee.ld.128.usar.ip q2,a2,16 # [5] id:743
sub a12,a12,a13 # [7]
addi a12,a12,16 # [8]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [9] id:744
loopnez a3,.LBB198_dspi_dotprod_s16_aes3 # [10]
.LBB196_dspi_dotprod_s16_aes3: # 0x269
ee.vld.128.ip q4,a15,16 # [0*II+0] id:746
ee.vmulas.s16.accx.ld.ip.qup q1,a2,16,q0,q1,q2,q3 # [0*II+1] id:745
ee.vld.128.ip q0,a15,16 # [0*II+2] id:748
ee.vmulas.s16.accx.ld.ip.qup q4,a2,16,q4,q2,q3,q1 # [0*II+3] id:747
ee.vld.128.ip q5,a15,16 # [0*II+4] id:750
ee.vmulas.s16.accx.ld.ip.qup q0,a2,16,q0,q3,q1,q4 # [0*II+5] id:749
ee.vld.128.ip q6,a15,16 # [0*II+6] id:752
ee.vmulas.s16.accx.ld.ip.qup q1,a2,16,q5,q1,q4,q0 # [0*II+7] id:751
ee.vld.128.ip q5,a15,16 # [0*II+8] id:754
ee.vmulas.s16.accx.ld.ip.qup q4,a2,16,q6,q4,q0,q1 # [0*II+9] id:753
ee.vld.128.ip q6,a15,16 # [0*II+10] id:756
ee.vmulas.s16.accx.ld.xp.qup q0,a2,a12,q5,q0,q1,q4 # [0*II+11] id:755
ee.vld.128.ip q5,a15,16 # [0*II+12] id:759
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q6,q1,q4,q0 # [0*II+13] id:757
ee.ld.128.usar.xp q1,a2,a10 # [0*II+14] id:758
ee.vld.128.ip q0,a15,16 # [0*II+15] id:761
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+16] id:760
.LBB198_dspi_dotprod_s16_aes3: # 0x2a4
j .Lt_0_30722 # [0]
.Lt_0_33282: # 0x2a7
movi.n a2,0 # [0]
sext a14,a9,15 # [1]
s16i a14,a4,0 # [2] id:788
retw.n # [3]
.LBB28_dspi_dotprod_s16_aes3: # 0x2b1
mov.n a15,a7 # [0]
mov.n a14,a6 # [1]
mov.n a13,a5 # [2]
mov.n a12,a4 # [3]
mov.n a11,a3 # [4]
mov.n a10,a2 # [5]
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,649
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_s8_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_s8_arp4
.global dspi_dotprod_s8_ansi
.type dspi_dotprod_s8_arp4,@function
// esp_err_t dspi_dotprod_s8_arp4(image2d_t *in_image, image2d_t *filter, int16_t *out_value, int count_x, int count_y, int shift);
dspi_dotprod_s8_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 15
or t1, t1, t2
beqz t1, .dspi_dotprod_s8_arp4_body
j dspi_dotprod_s8_ansi
.dspi_dotprod_s8_arp4_body:
add sp, sp, -16
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
srli t6, a3, 4 // t5 = len/16
addi a6, a5, -1
li t4, 1
sll t4, t4, a6
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q0, t4, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q1, t5, 16 // q1 - f_data
.loop_count_x: esp.vmulas.s8.xacc.ld.ip q0, t4, 16, q0, q1 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.s.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 2,718
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_u16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_u16_arp4
.global dspi_dotprod_u16_ansi
.type dspi_dotprod_u16_arp4,@function
// esp_err_t dspi_dotprod_u16_arp4(image2d_t *in_image, image2d_t *filter, uint16_t *out_value, int count_x, int count_y, int shift);
dspi_dotprod_u16_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 7
or t1, t1, t2
beqz t1, .dspi_dotprod_u16_arp4_body
j dspi_dotprod_u16_ansi
.dspi_dotprod_u16_arp4_body:
add sp, sp, -16
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
slli t2, t2, 1 // i_step = i_step<<1
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
slli t3, t3, 1 // f_step = f_step<<1
srli t6, a3, 3 // t5 = len/8
addi a6, a5, -1
li t4, 1
sll t4, t4, a6
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q0, t4, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q1, t5, 16 // q1 - f_data
.loop_count_x: esp.vmulas.u16.xacc.ld.ip q0, t4, 16, q0, q1 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.u.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 3,555
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dsps_dotprod_s16_m_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro dotprod_s16_ae32 x1, x2, count
// This macro calculates fixed point dot product for ((count + 1)*4) int16 samples
// x1 - input array1 register (for example a2)
// x2 - input array2 register (for example a3)
// count - counter register (for example a7)
// count - samples_count / 4 - 1
// acc += x1[i + 0]*x2[i + 0] + x1[i + 1]*x2[i + 1] + x1[i + 2]*x2[i + 2] + x1[i + 3]*x2[i + 3]; i: 0..count
// acchi, and acclo have to be initialize before
// Result - acchi || acclo
// Modifies:
// m0, m1, m2, m3
// acchi || acclo - must be loaded before (for example 0x3fff to acclo).
/*
* Data schedule. Each line represents instruction, columns represent
* register contents. Last column (MUL) shows the multiplication which
* takes place. Values loaded in the given cycle are shown in square brackets.
*
* m0 m1 m2 m3 MUL
* --------- pre-load ------------
*[x0 x1] (no MULs in the first 3 instructions)
* x0 x1 [y0 y1]
* x0 x1 [x2 x3] y0 y1
* x0 x1 x2 x3 y0 y1 [y2 y3] x0*y0
* ---------- loop -------------- (the following 4 instructions are
*[x4 x5] x2 x3 y0 y1 y2 y3 x1*y1 repeated as much as needed)
* x4 x5 x2 x3 [y4 y5] y2 y3 x2*y2
* x4 x5 [x6 x7] y4 y5 y2 y3 x3*y3
* x4 x5 x6 x7 y4 y5 [y6 y7] x4*y4
* --------- finalize ------------
* x4 x5 x6 x7 y4 y5 y6 y7 x5*y5 (nothing is load)
* x4 x5 x6 x7 y4 y5 y6 y7 x6*y6
* x4 x5 x6 x7 y4 y5 y6 y7 x7*y7
*/
addi \x1, \x1, -4 // To arrange fist pointer
addi \x2, \x2, -4 // To arrange fist pointer
//lddec m0, \x1
//lddec m2, \x2 // To arrange fist pointer
ldinc m0, \x1
ldinc m2, \x2
ldinc m1, \x1
mula.dd.ll.ldinc m3, \x2, m0, m2
loopnez \count, .loop_end
.loop:
mula.dd.hh.ldinc m0, \x1, m0, m2
mula.dd.ll.ldinc m2, \x2, m1, m3
mula.dd.hh.ldinc m1, \x1, m1, m3
mula.dd.ll.ldinc m3, \x2, m0, m2
.loop_end:
mula.dd.hh m0, m2
mula.dd.ll m1, m3
mula.dd.hh m1, m3
.endm // dotprod_s16_ae32
.macro dotprod_s16_ae32_full x1, x2, count, full_count
// This macro calculates fixed point dot product for ((count + 1)*4) int16 samples
// x1 - input array1 register (for example a2)
// x2 - input array2 register (for example a3)
// count - counter register (for example a7)
// count - samples_count / 4 - 1
// full_count - samples_count
// acc += x1[i + 0]*x2[i + 0] + x1[i + 1]*x2[i + 1] + x1[i + 2]*x2[i + 2] + x1[i + 3]*x2[i + 3]; i: 0..count
// acchi, and acclo have to be initialize before
// Result - acchi || acclo
// Modifies:
// m0, m1, m2, m3
// acchi || acclo - must be loaded before (for example 0x3fff to acclo).
dotprod_s16_ae32 \x1, \x2, \count
bbci \full_count, 1, .mod2chk
ldinc m0, \x1
ldinc m2, \x2
mula.dd.hh m0, m2
mula.dd.ll m0, m2
.mod2chk:
bbci \full_count, 0, .mod1chk
ldinc m0, \x1
ldinc m2, \x2
mula.dd.ll m0, m2
.mod1chk:
.endm // dotprod_s16_ae32_full
|
georgevio/IoT-Embedded
| 14,880
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_s8_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_52, 458755
# Program Unit: dspi_dotprod_s8_aes3
.type dspi_dotprod_s8_aes3, @function
.align 4
.global dspi_dotprod_s8_aes3
dspi_dotprod_s8_aes3: # 0x4
.LBB1_dspi_dotprod_s8_aes3: # 0x4
entry a1,48 #
l32i.n a10,a2,4 # [0] id:668
l32i.n a11,a2,12 # [1] id:667
mull a8,a10,a5 # [2]
blt a11,a8,.LBB78_dspi_dotprod_s8_aes3 # [4]
l32i.n a12,a2,8 # [0] id:669
l32i.n a9,a2,16 # [1] id:670
mull a13,a12,a6 # [2]
blt a9,a13,.LBB78_dspi_dotprod_s8_aes3 # [4]
l32i.n a15,a3,4 # [0] id:672
l32i.n a14,a3,12 # [1] id:671
mull a13,a15,a5 # [2]
blt a14,a13,.LBB78_dspi_dotprod_s8_aes3 # [4]
l32i.n a8,a3,16 # [0] id:674
l32i.n a9,a3,8 # [1] id:673
s32i.n a9,a1,8 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB78_dspi_dotprod_s8_aes3 # [5]
l32i.n a8,a3,0 # [0] id:675
s32i.n a8,a1,4 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_33026 # [2]
bne a14,a13,.Lt_0_33026 # [0]
bnei a15,1,.Lt_0_33026 # [0]
l32i.n a13,a1,8 # [0] gra_spill_temp_2
beqi a13,1,.Lt_0_17666 # [2]
.Lt_0_33026: # 0x43
.Lt_0_17922: # 0x43
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
.type dspi_dotprod_s8_ansi, @function
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB78_dspi_dotprod_s8_aes3: # 0x56
l32r a2,.LC0_1_52 # [0]
retw.n # [1]
.Lt_0_17666: # 0x5b
addi.n a14,a10,-1 # [0]
bnez a14,.Lt_0_33794 # [1]
addi.n a15,a12,-1 # [0]
bnez a15,.Lt_0_33794 # [1]
extui a8,a5,0,4 # [0]
bnez.n a8,.Lt_0_33794 # [1]
blti a6,4,.Lt_0_33794 # [0]
movi.n a9,64 # [0]
bge a9,a5,.Lt_0_34306 # [1]
extui a10,a5,0,1 # [0]
bnez a10,.LBB28_dspi_dotprod_s8_aes3 # [1]
.Lt_0_34306: # 0x78
.Lt_0_19714: # 0x78
mov.n a3,a6 # [0]
addi a13,a5,-48 # [1]
movi.n a14,0 # [2]
mull a15,a11,a12 # [3]
l32i.n a2,a2,0 # [4] id:676
s32i.n a15,a1,0 # [6] gra_spill_temp_0
wur.accx_0 a14 # [7]
l32i.n a15,a1,4 # [8] gra_spill_temp_1
wur.accx_1 a14 # [9]
ee.vld.128.ip q0,a15,16 # [10] id:679
beqz a13,.LBB32_dspi_dotprod_s8_aes3 # [11]
.Lt_0_22786: # 0x93
.Lt_0_22274: # 0x93
addi a8,a5,-32 # [0]
beqz a8,.LBB38_dspi_dotprod_s8_aes3 # [1]
.Lt_0_24322: # 0x99
.Lt_0_23810: # 0x99
addi a9,a5,-16 # [0]
beqz a9,.LBB44_dspi_dotprod_s8_aes3 # [1]
.Lt_0_25858: # 0x9f
.Lt_0_25346: # 0x9f
addi a10,a5,-64 # [0]
beqz a10,.LBB50_dspi_dotprod_s8_aes3 # [1]
.Lt_0_27394: # 0xa5
.Lt_0_26882: # 0xa5
addi a11,a5,-128 # [0]
beqz a11,.LBB56_dspi_dotprod_s8_aes3 # [1]
movi a12,128 # [0]
bge a12,a5,.Lt_0_30210 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a2,16 # [1] id:751
ee.ld.128.usar.ip q2,a2,16 # [2] id:752
ee.src.q.ld.ip q3,a2,16,q1,q2 # [4] id:753
beqz.n a3,.Lt_0_30210 # [5]
l32i.n a14,a1,0 # [0] gra_spill_temp_0
addi a13,a5,63 # [1]
movgez a13,a5,a5 # [2]
srai a13,a13,6 # [3]
sub a14,a14,a5 # [4]
addi a14,a14,16 # [5]
addi.n a13,a13,-1 # [6]
.Lt_0_30978: # 0xd1
addi.n a12,a12,1 # [0]
movi.n a8,32 # [1]
movi.n a9,-16 # [2]
beqz.n a13,.Lt_0_31234 # [3]
loopnez a13,.LBB218_dspi_dotprod_s8_aes3 # [0]
.LBB216_dspi_dotprod_s8_aes3: # 0xdc
ee.vld.128.ip q5,a15,16 # [0*II+0] id:755
ee.vmulas.s8.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:754
ee.vld.128.ip q0,a15,16 # [0*II+2] id:757
ee.vmulas.s8.accx.ld.ip.qup q1,a2,16,q5,q2,q3,q4 # [0*II+3] id:756
ee.vld.128.ip q5,a15,16 # [0*II+4] id:759
ee.vmulas.s8.accx.ld.ip.qup q2,a2,16,q0,q3,q4,q1 # [0*II+5] id:758
ee.vld.128.ip q0,a15,16 # [0*II+6] id:761
ee.vmulas.s8.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+7] id:760
.LBB218_dspi_dotprod_s8_aes3: # 0xf8
.Lt_0_31234: # 0xf8
ee.vmulas.s8.accx.ld.ip.qup q5,a2,16,q0,q1,q2,q3 # [0] id:762
ee.vld.128.ip q0,a15,16 # [1] id:763
ee.vld.128.ip q6,a15,16 # [2] id:765
ee.vmulas.s8.accx.ld.xp.qup q7,a2,a14,q0,q2,q3,q5 # [3] id:764
ee.vld.128.ip q4,a15,16 # [4] id:768
ee.vmulas.s8.accx.ld.xp.qup q2,a2,a9,q6,q3,q5,q7 # [5] id:766
ee.ld.128.usar.xp q1,a2,a8 # [6] id:767
ee.vld.128.ip q0,a15,16 # [7] id:770
ee.vmulas.s8.accx.ld.ip.qup q3,a2,16,q4,q5,q1,q2 # [8] id:769
bne a12,a3,.Lt_0_30978 # [9]
.Lt_0_30210: # 0x11a
.Lt_0_29954: # 0x11a
movi.n a2,0 # [0]
rur.accx_0 a10 # [1]
addi.n a12,a7,-1 # [2]
movi.n a11,1 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:772
retw.n # [10]
.Lt_0_33794: # 0x136
.Lt_0_18946: # 0x136
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
#.LBB25_dspi_dotprod_s8_aes3: # 0x145
mov.n a2,a10 # [0]
retw.n # [1]
.LBB32_dspi_dotprod_s8_aes3: # 0x149
ee.ld.128.usar.ip q1,a2,16 # [0] id:680
ee.ld.128.usar.ip q2,a2,16 # [1] id:681
ee.src.q.ld.ip q3,a2,16,q1,q2 # [3] id:682
beqz.n a6,.Lt_0_22786 # [4]
movi.n a10,32 # [0]
l32i.n a12,a1,0 # [1] gra_spill_temp_0
movi.n a11,-16 # [2]
addi a12,a12,-32 # [3]
loopgtz a6,.LBB104_dspi_dotprod_s8_aes3 # [4]
.LBB102_dspi_dotprod_s8_aes3: # 0x160
ee.vld.128.ip q4,a15,16 # [0*II+0] id:684
ee.vmulas.s8.accx.ld.xp.qup q1,a2,a12,q0,q1,q2,q3 # [0*II+1] id:683
ee.vld.128.ip q5,a15,16 # [0*II+2] id:686
ee.vmulas.s8.accx.ld.xp.qup q2,a2,a11,q4,q2,q3,q1 # [0*II+3] id:685
ee.ld.128.usar.xp q1,a2,a10 # [0*II+4] id:687
ee.vld.128.ip q0,a15,16 # [0*II+5] id:689
ee.vmulas.s8.accx.ld.ip.qup q3,a2,16,q5,q3,q1,q2 # [0*II+6] id:688
.LBB104_dspi_dotprod_s8_aes3: # 0x178
j .Lt_0_22786 # [0]
.LBB38_dspi_dotprod_s8_aes3: # 0x17b
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
srli a3,a6,1 # [2]
l32i.n a12,a1,0 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:690
ee.ld.128.usar.ip q2,a2,16 # [5] id:691
addi a12,a12,-16 # [7]
ee.src.q.ld.xp q3,a2,a12,q1,q2 # [8] id:692
loopnez a3,.LBB127_dspi_dotprod_s8_aes3 # [9]
.LBB125_dspi_dotprod_s8_aes3: # 0x193
ee.vld.128.ip q4,a15,16 # [0*II+0] id:694
ee.vmulas.s8.accx.ld.xp.qup q3,a2,a11,q0,q1,q2,q3 # [0*II+1] id:693
ee.ld.128.usar.xp q1,a2,a10 # [0*II+2] id:695
ee.vld.128.ip q0,a15,16 # [0*II+3] id:697
ee.vmulas.s8.accx.ld.xp.qup q4,a2,a12,q4,q2,q1,q3 # [0*II+4] id:696
ee.vld.128.ip q5,a15,16 # [0*II+5] id:699
ee.vmulas.s8.accx.ld.xp.qup q2,a2,a11,q0,q1,q3,q4 # [0*II+6] id:698
ee.ld.128.usar.xp q1,a2,a10 # [0*II+7] id:700
ee.vld.128.ip q0,a15,16 # [0*II+8] id:702
ee.vmulas.s8.accx.ld.xp.qup q3,a2,a12,q5,q3,q1,q2 # [0*II+9] id:701
.LBB127_dspi_dotprod_s8_aes3: # 0x1b5
j .Lt_0_24322 # [0]
.LBB44_dspi_dotprod_s8_aes3: # 0x1b8
srli a3,a3,2 # [0]
movi.n a10,-16 # [1]
l32i.n a11,a1,0 # [2] gra_spill_temp_0
addi a8,a2,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a8,a10 # [5] id:703
ee.ld.128.usar.xp q1,a8,a11 # [6] id:704
ee.src.q.ld.xp q3,a8,a10,q1,q2 # [8] id:705
ee.ld.128.usar.xp q2,a8,a11 # [9] id:706
loopnez a3,.LBB150_dspi_dotprod_s8_aes3 # [10]
.LBB148_dspi_dotprod_s8_aes3: # 0x1d4
ee.vld.128.ip q4,a15,16 # [0*II+0] id:708
ee.vmulas.s8.accx.ld.xp.qup q3,a8,a10,q0,q1,q2,q3 # [0*II+1] id:707
ee.ld.128.usar.xp q1,a8,a11 # [0*II+2] id:709
ee.vld.128.ip q0,a15,16 # [0*II+3] id:711
ee.vmulas.s8.accx.ld.xp.qup q4,a8,a10,q4,q2,q1,q3 # [0*II+4] id:710
ee.ld.128.usar.xp q3,a8,a11 # [0*II+5] id:712
ee.vld.128.ip q5,a15,16 # [0*II+6] id:714
ee.vmulas.s8.accx.ld.xp.qup q4,a8,a10,q0,q1,q3,q4 # [0*II+7] id:713
ee.ld.128.usar.xp q1,a8,a11 # [0*II+8] id:715
ee.vld.128.ip q0,a15,16 # [0*II+9] id:717
ee.vmulas.s8.accx.ld.xp.qup q3,a8,a10,q5,q3,q1,q4 # [0*II+10] id:716
ee.ld.128.usar.xp q2,a8,a11 # [0*II+11] id:718
.LBB150_dspi_dotprod_s8_aes3: # 0x1fc
mov.n a2,a8 # [0]
j .Lt_0_25858 # [1]
.LBB50_dspi_dotprod_s8_aes3: # 0x201
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i.n a12,a1,0 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [3] id:719
ee.ld.128.usar.ip q2,a2,16 # [4] id:720
sub a12,a12,a5 # [5]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [7] id:721
addi a12,a12,16 # [8]
loopnez a3,.LBB173_dspi_dotprod_s8_aes3 # [9]
.LBB171_dspi_dotprod_s8_aes3: # 0x219
ee.vld.128.ip q5,a15,16 # [0*II+0] id:723
ee.vmulas.s8.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:722
ee.vld.128.ip q1,a15,16 # [0*II+2] id:725
ee.vmulas.s8.accx.ld.xp.qup q0,a2,a12,q5,q2,q3,q4 # [0*II+3] id:724
ee.vld.128.ip q5,a15,16 # [0*II+4] id:728
ee.vmulas.s8.accx.ld.xp.qup q2,a2,a11,q1,q3,q4,q0 # [0*II+5] id:726
ee.ld.128.usar.xp q1,a2,a10 # [0*II+6] id:727
ee.vld.128.ip q0,a15,16 # [0*II+7] id:730
ee.vmulas.s8.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+8] id:729
.LBB173_dspi_dotprod_s8_aes3: # 0x238
j .Lt_0_27394 # [0]
.LBB56_dspi_dotprod_s8_aes3: # 0x23b
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i.n a12,a1,0 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [3] id:731
ee.ld.128.usar.ip q2,a2,16 # [4] id:732
sub a12,a12,a5 # [6]
addi a12,a12,16 # [7]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [8] id:733
loopnez a3,.LBB195_dspi_dotprod_s8_aes3 # [9]
.LBB193_dspi_dotprod_s8_aes3: # 0x253
ee.vld.128.ip q4,a15,16 # [0*II+0] id:735
ee.vmulas.s8.accx.ld.ip.qup q1,a2,16,q0,q1,q2,q3 # [0*II+1] id:734
ee.vld.128.ip q0,a15,16 # [0*II+2] id:737
ee.vmulas.s8.accx.ld.ip.qup q4,a2,16,q4,q2,q3,q1 # [0*II+3] id:736
ee.vld.128.ip q5,a15,16 # [0*II+4] id:739
ee.vmulas.s8.accx.ld.ip.qup q0,a2,16,q0,q3,q1,q4 # [0*II+5] id:738
ee.vld.128.ip q6,a15,16 # [0*II+6] id:741
ee.vmulas.s8.accx.ld.ip.qup q1,a2,16,q5,q1,q4,q0 # [0*II+7] id:740
ee.vld.128.ip q5,a15,16 # [0*II+8] id:743
ee.vmulas.s8.accx.ld.ip.qup q4,a2,16,q6,q4,q0,q1 # [0*II+9] id:742
ee.vld.128.ip q6,a15,16 # [0*II+10] id:745
ee.vmulas.s8.accx.ld.xp.qup q0,a2,a12,q5,q0,q1,q4 # [0*II+11] id:744
ee.vld.128.ip q5,a15,16 # [0*II+12] id:748
ee.vmulas.s8.accx.ld.xp.qup q2,a2,a11,q6,q1,q4,q0 # [0*II+13] id:746
ee.ld.128.usar.xp q1,a2,a10 # [0*II+14] id:747
ee.vld.128.ip q0,a15,16 # [0*II+15] id:750
ee.vmulas.s8.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+16] id:749
.LBB195_dspi_dotprod_s8_aes3: # 0x28e
movi.n a2,0 # [0]
movi.n a11,1 # [1]
addi.n a12,a7,-1 # [2]
rur.accx_0 a10 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:772
retw.n # [10]
.LBB28_dspi_dotprod_s8_aes3: # 0x2aa
mov.n a15,a7 # [0]
mov.n a14,a6 # [1]
mov.n a13,a5 # [2]
mov.n a12,a4 # [3]
mov.n a11,a3 # [4]
mov.n a10,a2 # [5]
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
#.LBB29_dspi_dotprod_s8_aes3: # 0x2b9
mov.n a2,a10 # [0]
retw.n # [1]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 17,637
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_u16_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_61, 458755
# Program Unit: dspi_dotprod_off_u16_aes3
.type dspi_dotprod_off_u16_aes3, @function
.align 4
.global dspi_dotprod_off_u16_aes3
dspi_dotprod_off_u16_aes3: # 0x4
.LBB1_dspi_dotprod_off_u16_aes3: # 0x4
entry a1,144 #
l32i.n a10,a2,4 # [0] id:760
l32i.n a12,a2,12 # [1] id:759
mull a8,a10,a5 # [2]
blt a12,a8,.LBB89_dspi_dotprod_off_u16_aes3 # [4]
l32i.n a13,a2,8 # [0] id:761
l32i.n a9,a2,16 # [1] id:762
mull a11,a13,a6 # [2]
blt a9,a11,.LBB89_dspi_dotprod_off_u16_aes3 # [4]
l32i.n a15,a3,4 # [0] id:764
l32i.n a14,a3,12 # [1] id:763
mull a11,a15,a5 # [2]
blt a14,a11,.LBB89_dspi_dotprod_off_u16_aes3 # [4]
l32i.n a8,a3,16 # [0] id:766
l32i.n a9,a3,8 # [1] id:765
s32i a9,a1,104 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB89_dspi_dotprod_off_u16_aes3 # [5]
l32i.n a8,a3,0 # [0] id:767
s32i a8,a1,100 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_36354 # [2]
bne a14,a11,.Lt_0_36354 # [0]
bnei a15,1,.Lt_0_36354 # [0]
l32i a9,a1,104 # [0] gra_spill_temp_2
beqi a9,1,.Lt_0_19458 # [2]
.Lt_0_36354: # 0x46
.Lt_0_19714: # 0x46
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16ui a8,a1,144 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:876
.type dspi_dotprod_off_u16_ansi, @function
call8 dspi_dotprod_off_u16_ansi # [8] dspi_dotprod_off_u16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB89_dspi_dotprod_off_u16_aes3: # 0x5e
l32r a2,.LC0_1_61 # [0]
retw.n # [1]
.Lt_0_19458: # 0x63
addi.n a9,a10,-1 # [0]
bnez a9,.Lt_0_37122 # [1]
addi.n a10,a13,-1 # [0]
bnez a10,.Lt_0_37122 # [1]
extui a11,a5,0,3 # [0]
bnez.n a11,.Lt_0_37122 # [1]
blti a6,4,.Lt_0_37122 # [0]
movi.n a14,32 # [0]
blt a14,a5,.LBB27_dspi_dotprod_off_u16_aes3 # [1]
.Lt_0_37634: # 0x7a
.Lt_0_21506: # 0x7a
l16ui a9,a1,144 # [0] id:768 offset+0x0
addi a8,a1,16 # [1] temp_offset
l32i.n a15,a2,0 # [2] id:769
mull a10,a12,a13 # [3]
l32i a2,a1,100 # [4] gra_spill_temp_1
slli a10,a10,1 # [5]
s32i a10,a1,96 # [6] gra_spill_temp_0
movi.n a10,2 # [7]
# loop-count fixed at 2
loop a10,.LBB143_dspi_dotprod_off_u16_aes3 # [8]
.LBB138_dspi_dotprod_off_u16_aes3: # 0x93
s16i a9,a8,0 # [0*II+0] id:770 temp_offset+0x0
s16i a9,a8,2 # [0*II+1] id:770 temp_offset+0x0
s16i a9,a8,4 # [0*II+2] id:770 temp_offset+0x0
s16i a9,a8,6 # [0*II+3] id:770 temp_offset+0x0
s16i a9,a8,8 # [0*II+4] id:770 temp_offset+0x0
s16i a9,a8,10 # [0*II+5] id:770 temp_offset+0x0
s16i a9,a8,12 # [0*II+6] id:770 temp_offset+0x0
s16i a9,a8,14 # [0*II+7] id:770 temp_offset+0x0
addi a8,a8,16 # [0*II+8]
.LBB143_dspi_dotprod_off_u16_aes3: # 0xae
mov.n a3,a6 # [0]
addi a11,a5,-24 # [1]
addi a12,a1,24 # [3] temp_offset+8
movi.n a13,0 # [4]
wur.sar_byte a13 # [5]
wur.accx_0 a13 # [6]
wur.accx_1 a13 # [7]
ee.vld.128.ip q6,a12,0 # [8] id:771
s32i.n a12,a1,48 # [9] offset_data_ptr
beqz a11,.LBB34_dspi_dotprod_off_u16_aes3 # [10]
l32i a2,a1,100 # [0] gra_spill_temp_1
ee.vld.128.ip q0,a2,16 # [2] id:787
st.qr q0,a1,64 # [3] q0
.Lt_0_25090: # 0xd1
addi a14,a5,-16 # [0]
beqz a14,.LBB43_dspi_dotprod_off_u16_aes3 # [1]
.Lt_0_27138: # 0xd7
.Lt_0_26626: # 0xd7
addi a8,a5,-8 # [0]
beqz a8,.LBB50_dspi_dotprod_off_u16_aes3 # [1]
.Lt_0_28674: # 0xdd
.Lt_0_28162: # 0xdd
addi a9,a5,-32 # [0]
beqz a9,.LBB57_dspi_dotprod_off_u16_aes3 # [1]
.Lt_0_30210: # 0xe3
.Lt_0_29698: # 0xe3
addi a10,a5,-64 # [0]
beqz a10,.LBB64_dspi_dotprod_off_u16_aes3 # [1]
movi.n a11,64 # [0]
bge a11,a5,.Lt_0_33026 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a15,16 # [1] id:849
ee.ld.128.usar.ip q2,a15,16 # [2] id:850
ee.src.q.ld.ip q3,a15,16,q1,q2 # [4] id:851
beqz.n a3,.Lt_0_33026 # [5]
ld.qr q0,a1,64 # [0] q0
slli a8,a5,1 # [1]
l32i a14,a1,96 # [2] gra_spill_temp_0
addi a13,a5,31 # [3]
movgez a13,a5,a5 # [4]
srai a13,a13,5 # [5]
sub a14,a14,a8 # [6]
addi a14,a14,16 # [7]
addi.n a13,a13,-1 # [8]
.Lt_0_33794: # 0x115
beqz.n a13,.Lt_0_34050 # [0]
loopnez a13,.LBB280_dspi_dotprod_off_u16_aes3 # [0]
.LBB278_dspi_dotprod_off_u16_aes3: # 0x11a
ee.vmulas.u16.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:852
ee.vmulas.u16.accx.ld.ip q1,a2,16,q1,q6 # [0*II+1] id:853
ee.vmulas.u16.accx.ld.ip.qup q1,a15,16,q1,q2,q3,q0 # [0*II+3] id:854
ee.vmulas.u16.accx.ld.ip q4,a2,16,q2,q6 # [0*II+4] id:855
ee.vmulas.u16.accx.ld.ip.qup q2,a15,16,q4,q3,q0,q1 # [0*II+6] id:856
ee.vmulas.u16.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:857
ee.vmulas.u16.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+9] id:858
ee.vmulas.u16.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:859
.LBB280_dspi_dotprod_off_u16_aes3: # 0x13a
.Lt_0_34050: # 0x13a
ee.vmulas.u16.accx.ld.ip.qup q4,a15,16,q0,q1,q2,q3 # [0] id:860
ee.vmulas.u16.accx.ld.ip q1,a2,16,q1,q6 # [1] id:861
movi.n a9,32 # [2]
ee.vmulas.u16.accx.ld.xp.qup q0,a15,a14,q1,q2,q3,q4 # [3] id:862
ee.vmulas.u16.accx.ld.ip q7,a2,16,q2,q6 # [4] id:863
movi.n a10,-16 # [5]
ee.vmulas.u16.accx.ld.xp.qup q2,a15,a10,q7,q3,q4,q0 # [6] id:864
ee.vmulas.u16.accx.ld.ip q5,a2,16,q3,q6 # [7] id:866
ee.ld.128.usar.xp q1,a15,a9 # [8] id:865
addi.n a12,a12,1 # [9]
ee.vmulas.u16.accx.ld.ip.qup q3,a15,16,q5,q4,q1,q2 # [10] id:867
ee.vmulas.u16.accx.ld.ip q0,a2,16,q4,q6 # [11] id:868
bne a12,a3,.Lt_0_33794 # [12]
.Lt_0_33026: # 0x166
.Lt_0_32770: # 0x166
rur.accx_0 a9 # [0]
rur.accx_1 a10 # [1]
blti a7,1,.Lt_0_35586 # [2]
movi.n a2,0 # [0]
addi a13,a7,-33 # [1]
addi.n a14,a7,-1 # [2]
ssr a14 # [3]
sra a12,a10 # [4]
src a11,a10,a9 # [5]
movgez a11,a12,a13 # [6]
addi.n a11,a11,1 # [7]
srli a11,a11,1 # [8]
s16i a11,a4,0 # [9] id:874
retw.n # [10]
.Lt_0_37122: # 0x18c
.Lt_0_20738: # 0x18c
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16ui a8,a1,144 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:877
call8 dspi_dotprod_off_u16_ansi # [8] dspi_dotprod_off_u16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB27_dspi_dotprod_off_u16_aes3: # 0x1a4
extui a9,a5,0,1 # [0]
beqz a9,.Lt_0_37634 # [1]
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16ui a8,a1,144 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:878
call8 dspi_dotprod_off_u16_ansi # [8] dspi_dotprod_off_u16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB34_dspi_dotprod_off_u16_aes3: # 0x1c2
ee.ld.128.usar.ip q0,a15,16 # [0] id:776
ee.ld.128.usar.ip q2,a15,16 # [1] id:777
ee.src.q.ld.ip q3,a15,16,q0,q2 # [3] id:778
beqz.n a6,.Lt_0_25090 # [4]
movi.n a10,32 # [0]
l32i a12,a1,96 # [1] gra_spill_temp_0
movi.n a11,-16 # [2]
addi a12,a12,-32 # [3]
loopgtz a6,.LBB166_dspi_dotprod_off_u16_aes3 # [4]
.LBB164_dspi_dotprod_off_u16_aes3: # 0x1da
ee.vmulas.u16.accx.ld.ip q1,a2,16,q0,q6 # [0*II+0] id:779
ee.vmulas.u16.accx.ld.xp.qup q1,a15,a12,q1,q0,q2,q3 # [0*II+2] id:780
ee.vmulas.u16.accx.ld.ip q0,a2,16,q2,q6 # [0*II+3] id:781
ee.vmulas.u16.accx.ld.xp.qup q2,a15,a11,q0,q2,q3,q1 # [0*II+5] id:782
ee.vmulas.u16.accx.ld.ip q1,a2,16,q3,q6 # [0*II+6] id:784
ee.ld.128.usar.xp q0,a15,a10 # [0*II+7] id:783
ee.vmulas.u16.accx.ld.ip.qup q3,a15,16,q1,q3,q0,q2 # [0*II+9] id:785
.LBB166_dspi_dotprod_off_u16_aes3: # 0x1f5
st.qr q1,a1,64 # [0] q0
j .Lt_0_25090 # [1]
.LBB43_dspi_dotprod_off_u16_aes3: # 0x1fb
srli a3,a6,1 # [0]
l32i a12,a1,96 # [1] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [2] id:788
ee.ld.128.usar.ip q2,a15,16 # [3] id:789
addi a12,a12,-16 # [5]
ee.src.q.ld.xp q3,a15,a12,q1,q2 # [6] id:790
beqz.n a3,.Lt_0_27138 # [7]
ld.qr q0,a1,64 # [0] q0
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
loopnez a3,.LBB189_dspi_dotprod_off_u16_aes3 # [3]
.LBB187_dspi_dotprod_off_u16_aes3: # 0x219
ee.vmulas.u16.accx.ld.xp.qup q0,a15,a11,q0,q1,q2,q3 # [0*II+0] id:791
ee.vmulas.u16.accx.ld.ip q3,a2,16,q1,q6 # [0*II+1] id:792
ee.ld.128.usar.xp q1,a15,a10 # [0*II+2] id:793
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a12,q3,q2,q1,q0 # [0*II+4] id:794
ee.vmulas.u16.accx.ld.ip q4,a2,16,q2,q6 # [0*II+5] id:795
ee.vmulas.u16.accx.ld.xp.qup q2,a15,a11,q4,q1,q0,q3 # [0*II+7] id:796
ee.vmulas.u16.accx.ld.ip q3,a2,16,q1,q6 # [0*II+8] id:797
ee.ld.128.usar.xp q1,a15,a10 # [0*II+9] id:798
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a12,q3,q0,q1,q2 # [0*II+11] id:799
ee.vmulas.u16.accx.ld.ip q0,a2,16,q0,q6 # [0*II+12] id:800
.LBB189_dspi_dotprod_off_u16_aes3: # 0x23f
st.qr q0,a1,64 # [0] q0
j .Lt_0_27138 # [1]
.LBB50_dspi_dotprod_off_u16_aes3: # 0x245
srli a3,a3,2 # [0]
movi.n a13,-16 # [1]
l32i a11,a1,96 # [2] gra_spill_temp_0
addi a15,a15,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a15,a13 # [5] id:801
ee.ld.128.usar.xp q1,a15,a11 # [6] id:802
ee.src.q.ld.xp q3,a15,a13,q1,q2 # [8] id:803
ee.ld.128.usar.xp q2,a15,a11 # [9] id:804
beqz.n a3,.Lt_0_28674 # [10]
ld.qr q0,a1,64 # [0] q0
movi.n a10,-16 # [1]
loopnez a3,.LBB212_dspi_dotprod_off_u16_aes3 # [2]
.LBB210_dspi_dotprod_off_u16_aes3: # 0x269
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a10,q0,q1,q2,q3 # [0*II+0] id:805
ee.vmulas.u16.accx.ld.ip q0,a2,16,q1,q6 # [0*II+1] id:806
ee.ld.128.usar.xp q1,a15,a11 # [0*II+2] id:807
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a10,q0,q2,q1,q3 # [0*II+4] id:808
ee.vmulas.u16.accx.ld.ip q0,a2,16,q2,q6 # [0*II+5] id:809
ee.ld.128.usar.xp q4,a15,a11 # [0*II+6] id:810
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a10,q0,q1,q4,q3 # [0*II+8] id:811
ee.vmulas.u16.accx.ld.ip q0,a2,16,q1,q6 # [0*II+9] id:812
ee.ld.128.usar.xp q1,a15,a11 # [0*II+10] id:813
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a10,q0,q4,q1,q3 # [0*II+12] id:814
ee.vmulas.u16.accx.ld.ip q0,a2,16,q4,q6 # [0*II+13] id:815
ee.ld.128.usar.xp q2,a15,a11 # [0*II+14] id:816
.LBB212_dspi_dotprod_off_u16_aes3: # 0x295
st.qr q0,a1,64 # [0] q0
j .Lt_0_28674 # [1]
.LBB57_dspi_dotprod_off_u16_aes3: # 0x29b
ee.ld.128.usar.ip q1,a15,16 # [0] id:817
ee.ld.128.usar.ip q2,a15,16 # [1] id:818
ee.src.q.ld.ip q3,a15,16,q1,q2 # [3] id:819
beqz.n a3,.Lt_0_30210 # [4]
ld.qr q0,a1,64 # [0] q0
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
l32i a12,a1,96 # [3] gra_spill_temp_0
slli a13,a5,1 # [4]
sub a12,a12,a13 # [5]
addi a12,a12,16 # [6]
loopnez a3,.LBB235_dspi_dotprod_off_u16_aes3 # [7]
.LBB233_dspi_dotprod_off_u16_aes3: # 0x2bc
ee.vmulas.u16.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:820
ee.vmulas.u16.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:821
ee.vmulas.u16.accx.ld.xp.qup q4,a15,a12,q4,q2,q3,q0 # [0*II+3] id:822
ee.vmulas.u16.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:823
ee.vmulas.u16.accx.ld.xp.qup q2,a15,a11,q1,q3,q0,q4 # [0*II+6] id:824
ee.vmulas.u16.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:826
ee.ld.128.usar.xp q1,a15,a10 # [0*II+8] id:825
ee.vmulas.u16.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+10] id:827
ee.vmulas.u16.accx.ld.ip q0,a2,16,q0,q6 # [0*II+11] id:828
.LBB235_dspi_dotprod_off_u16_aes3: # 0x2df
st.qr q0,a1,64 # [0] q0
j .Lt_0_30210 # [1]
.LBB64_dspi_dotprod_off_u16_aes3: # 0x2e5
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i a12,a1,96 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [4] id:829
ee.ld.128.usar.ip q2,a15,16 # [5] id:830
sub a12,a12,a13 # [7]
addi a12,a12,16 # [8]
ld.qr q0,a1,64 # [9] q0
ee.src.q.ld.ip q3,a15,16,q1,q2 # [10] id:831
mov.n a8,a15 # [11]
loopnez a3,.LBB257_dspi_dotprod_off_u16_aes3 # [12]
.LBB255_dspi_dotprod_off_u16_aes3: # 0x306
ee.vmulas.u16.accx.ld.ip.qup q0,a8,16,q0,q1,q2,q3 # [0*II+0] id:832
ee.vmulas.u16.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:833
ee.vmulas.u16.accx.ld.ip.qup q4,a8,16,q4,q2,q3,q0 # [0*II+3] id:834
ee.vmulas.u16.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:835
ee.vmulas.u16.accx.ld.ip.qup q1,a8,16,q1,q3,q0,q4 # [0*II+6] id:836
ee.vmulas.u16.accx.ld.ip q5,a2,16,q3,q6 # [0*II+7] id:837
ee.vmulas.u16.accx.ld.ip.qup q5,a8,16,q5,q0,q4,q1 # [0*II+9] id:838
ee.vmulas.u16.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:839
ee.vmulas.u16.accx.ld.ip.qup q0,a8,16,q0,q4,q1,q5 # [0*II+12] id:840
ee.vmulas.u16.accx.ld.ip q4,a2,16,q4,q6 # [0*II+13] id:841
ee.vmulas.u16.accx.ld.xp.qup q4,a8,a12,q4,q1,q5,q0 # [0*II+15] id:842
ee.vmulas.u16.accx.ld.ip q1,a2,16,q1,q6 # [0*II+16] id:843
ee.vmulas.u16.accx.ld.xp.qup q2,a8,a11,q1,q5,q0,q4 # [0*II+18] id:844
ee.vmulas.u16.accx.ld.ip q4,a2,16,q5,q6 # [0*II+19] id:846
ee.ld.128.usar.xp q1,a8,a10 # [0*II+20] id:845
ee.vmulas.u16.accx.ld.ip.qup q3,a8,16,q4,q0,q1,q2 # [0*II+22] id:847
ee.vmulas.u16.accx.ld.ip q0,a2,16,q0,q6 # [0*II+23] id:848
.LBB257_dspi_dotprod_off_u16_aes3: # 0x349
j .Lt_0_33026 # [0]
.Lt_0_35586: # 0x34c
movi.n a2,0 # [0]
sext a14,a9,15 # [1]
s16i a14,a4,0 # [2] id:875
retw.n # [3]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,928
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_s16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_off_s16_arp4
.global dspi_dotprod_off_s16_ansi
.type dspi_dotprod_off_s16_arp4,@function
// esp_err_t dspi_dotprod_off_s16_arp4(image2d_t *in_image, image2d_t *filter, int16_t *out_value, int count_x, int count_y, int shift, int16_t offset);
dspi_dotprod_off_s16_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// offset - a6
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// current i_data - t4
// current f_data - t5
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 7
or t1, t1, t2
beqz t1, .dspi_dotprod_off_s16_arp4_body
j dspi_dotprod_off_s16_ansi
.dspi_dotprod_off_s16_arp4_body:
add sp, sp, -16
sw a6, 0(sp)
mv t6, sp
esp.vldbc.16.ip q2, t6, 0
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
slli t2, t2, 1 // i_step = i_step<<1
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
slli t3, t3, 1 // f_step = f_step<<1
srli t6, a3, 3 // t5 = len/8
addi a7, a5, -1
li t4, 1
sll t4, t4, a7
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q1, t5, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q0, t4, 16 // q1 - f_data
esp.vadd.s16 q3, q2, q1
.loop_count_x: esp.vmulas.s16.xacc.ld.ip q1, t5, 16, q0, q3 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.s.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 17,039
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_u8_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_57, 458755
# Program Unit: dspi_dotprod_off_u8_aes3
.type dspi_dotprod_off_u8_aes3, @function
.align 4
.global dspi_dotprod_off_u8_aes3
dspi_dotprod_off_u8_aes3: # 0x4
.LBB1_dspi_dotprod_off_u8_aes3: # 0x4
entry a1,112 #
l32i.n a10,a2,4 # [0] id:745
l32i.n a12,a2,12 # [1] id:744
mull a8,a10,a5 # [2]
blt a12,a8,.LBB86_dspi_dotprod_off_u8_aes3 # [4]
l32i.n a13,a2,8 # [0] id:746
l32i.n a9,a2,16 # [1] id:747
mull a11,a13,a6 # [2]
blt a9,a11,.LBB86_dspi_dotprod_off_u8_aes3 # [4]
l32i.n a15,a3,4 # [0] id:749
l32i.n a14,a3,12 # [1] id:748
mull a11,a15,a5 # [2]
blt a14,a11,.LBB86_dspi_dotprod_off_u8_aes3 # [4]
l32i.n a8,a3,16 # [0] id:751
l32i.n a9,a3,8 # [1] id:750
s32i a9,a1,72 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB86_dspi_dotprod_off_u8_aes3 # [5]
l32i.n a8,a3,0 # [0] id:752
s32i a8,a1,68 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_35330 # [2]
bne a14,a11,.Lt_0_35330 # [0]
bnei a15,1,.Lt_0_35330 # [0]
l32i a11,a1,72 # [0] gra_spill_temp_2
beqi a11,1,.Lt_0_18946 # [2]
.Lt_0_35330: # 0x46
.Lt_0_19202: # 0x46
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
.type dspi_dotprod_u8_ansi, @function
call8 dspi_dotprod_u8_ansi # [6] dspi_dotprod_u8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB86_dspi_dotprod_off_u8_aes3: # 0x59
l32r a2,.LC0_1_57 # [0]
retw.n # [1]
.Lt_0_18946: # 0x5e
addi.n a14,a10,-1 # [0]
bnez a14,.Lt_0_36098 # [1]
addi.n a15,a13,-1 # [0]
bnez a15,.Lt_0_36098 # [1]
extui a8,a5,0,4 # [0]
bnez.n a8,.Lt_0_36098 # [1]
blti a6,4,.Lt_0_36098 # [0]
movi.n a9,64 # [0]
blt a9,a5,.LBB27_dspi_dotprod_off_u8_aes3 # [1]
.Lt_0_36610: # 0x75
.Lt_0_20994: # 0x75
l8ui a9,a1,112 # [0] id:754 offset+0x0
mov.n a8,a1 # [1]
l32i.n a15,a2,0 # [2] id:753
mull a10,a12,a13 # [3]
l32i a2,a1,68 # [4] gra_spill_temp_1
s32i a10,a1,64 # [5] gra_spill_temp_0
movi.n a10,4 # [6]
# loop-count fixed at 4
loop a10,.LBB140_dspi_dotprod_off_u8_aes3 # [7]
.LBB135_dspi_dotprod_off_u8_aes3: # 0x8a
s8i a9,a8,0 # [0*II+0] id:755 temp_offset+0x0
s8i a9,a8,1 # [0*II+1] id:755 temp_offset+0x0
s8i a9,a8,2 # [0*II+2] id:755 temp_offset+0x0
s8i a9,a8,3 # [0*II+3] id:755 temp_offset+0x0
s8i a9,a8,4 # [0*II+4] id:755 temp_offset+0x0
s8i a9,a8,5 # [0*II+5] id:755 temp_offset+0x0
s8i a9,a8,6 # [0*II+6] id:755 temp_offset+0x0
s8i a9,a8,7 # [0*II+7] id:755 temp_offset+0x0
addi.n a8,a8,8 # [0*II+8]
.LBB140_dspi_dotprod_off_u8_aes3: # 0xa4
mov.n a3,a6 # [0]
addi a11,a5,-48 # [1]
addi.n a12,a1,8 # [3] temp_offset+8
movi.n a13,0 # [4]
wur.accx_0 a13 # [5]
wur.accx_1 a13 # [6]
ee.vld.128.ip q6,a12,0 # [7] id:756
s32i.n a12,a1,32 # [8] offset_data_ptr
beqz a11,.LBB34_dspi_dotprod_off_u8_aes3 # [9]
l32i a2,a1,68 # [0] gra_spill_temp_1
ee.vld.128.ip q0,a2,16 # [2] id:771
st.qr q0,a1,48 # [3] q0
.Lt_0_24578: # 0xc3
addi a14,a5,-32 # [0]
beqz a14,.LBB43_dspi_dotprod_off_u8_aes3 # [1]
.Lt_0_26626: # 0xc9
.Lt_0_26114: # 0xc9
addi a8,a5,-16 # [0]
beqz a8,.LBB50_dspi_dotprod_off_u8_aes3 # [1]
.Lt_0_28162: # 0xcf
.Lt_0_27650: # 0xcf
addi a9,a5,-64 # [0]
beqz a9,.LBB57_dspi_dotprod_off_u8_aes3 # [1]
.Lt_0_29698: # 0xd5
.Lt_0_29186: # 0xd5
addi a10,a5,-128 # [0]
beqz a10,.LBB64_dspi_dotprod_off_u8_aes3 # [1]
movi a11,128 # [0]
bge a11,a5,.Lt_0_32514 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a15,16 # [1] id:833
ee.ld.128.usar.ip q2,a15,16 # [2] id:834
ee.src.q.ld.ip q3,a15,16,q1,q2 # [4] id:835
beqz.n a3,.Lt_0_32514 # [5]
ld.qr q0,a1,48 # [0] q0
l32i a14,a1,64 # [1] gra_spill_temp_0
addi a13,a5,31 # [2]
movgez a13,a5,a5 # [3]
srai a13,a13,5 # [4]
sub a14,a14,a5 # [5]
addi a14,a14,16 # [6]
addi.n a13,a13,-1 # [7]
.Lt_0_33282: # 0x105
beqz.n a13,.Lt_0_33538 # [0]
loopnez a13,.LBB277_dspi_dotprod_off_u8_aes3 # [0]
.LBB275_dspi_dotprod_off_u8_aes3: # 0x10a
ee.vmulas.u8.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:836
ee.vmulas.u8.accx.ld.ip q1,a2,16,q1,q6 # [0*II+1] id:837
ee.vmulas.u8.accx.ld.ip.qup q1,a15,16,q1,q2,q3,q0 # [0*II+3] id:838
ee.vmulas.u8.accx.ld.ip q4,a2,16,q2,q6 # [0*II+4] id:839
ee.vmulas.u8.accx.ld.ip.qup q2,a15,16,q4,q3,q0,q1 # [0*II+6] id:840
ee.vmulas.u8.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:841
ee.vmulas.u8.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+9] id:842
ee.vmulas.u8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:843
.LBB277_dspi_dotprod_off_u8_aes3: # 0x12a
.Lt_0_33538: # 0x12a
ee.vmulas.u8.accx.ld.ip.qup q4,a15,16,q0,q1,q2,q3 # [0] id:844
ee.vmulas.u8.accx.ld.ip q1,a2,16,q1,q6 # [1] id:845
movi.n a8,32 # [2]
ee.vmulas.u8.accx.ld.xp.qup q0,a15,a14,q1,q2,q3,q4 # [3] id:846
ee.vmulas.u8.accx.ld.ip q7,a2,16,q2,q6 # [4] id:847
movi.n a9,-16 # [5]
ee.vmulas.u8.accx.ld.xp.qup q2,a15,a9,q7,q3,q4,q0 # [6] id:848
ee.vmulas.u8.accx.ld.ip q5,a2,16,q3,q6 # [7] id:850
ee.ld.128.usar.xp q1,a15,a8 # [8] id:849
addi.n a12,a12,1 # [9]
ee.vmulas.u8.accx.ld.ip.qup q3,a15,16,q5,q4,q1,q2 # [10] id:851
ee.vmulas.u8.accx.ld.ip q0,a2,16,q4,q6 # [11] id:852
bne a12,a3,.Lt_0_33282 # [12]
.Lt_0_32514: # 0x156
.Lt_0_32258: # 0x156
movi.n a2,0 # [0]
rur.accx_0 a10 # [1]
addi.n a12,a7,-1 # [2]
movi.n a11,1 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:854
retw.n # [10]
.Lt_0_36098: # 0x172
.Lt_0_20226: # 0x172
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_u8_ansi # [6] dspi_dotprod_u8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB27_dspi_dotprod_off_u8_aes3: # 0x185
extui a14,a5,0,1 # [0]
beqz a14,.Lt_0_36610 # [1]
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_u8_ansi # [6] dspi_dotprod_u8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB34_dspi_dotprod_off_u8_aes3: # 0x19e
ee.ld.128.usar.ip q0,a15,16 # [0] id:760
ee.ld.128.usar.ip q2,a15,16 # [1] id:761
ee.src.q.ld.ip q3,a15,16,q0,q2 # [3] id:762
beqz.n a6,.Lt_0_24578 # [4]
movi.n a10,32 # [0]
l32i a12,a1,64 # [1] gra_spill_temp_0
movi.n a11,-16 # [2]
addi a12,a12,-32 # [3]
loopgtz a6,.LBB163_dspi_dotprod_off_u8_aes3 # [4]
.LBB161_dspi_dotprod_off_u8_aes3: # 0x1b6
ee.vmulas.u8.accx.ld.ip q1,a2,16,q0,q6 # [0*II+0] id:763
ee.vmulas.u8.accx.ld.xp.qup q1,a15,a12,q1,q0,q2,q3 # [0*II+2] id:764
ee.vmulas.u8.accx.ld.ip q0,a2,16,q2,q6 # [0*II+3] id:765
ee.vmulas.u8.accx.ld.xp.qup q2,a15,a11,q0,q2,q3,q1 # [0*II+5] id:766
ee.vmulas.u8.accx.ld.ip q1,a2,16,q3,q6 # [0*II+6] id:768
ee.ld.128.usar.xp q0,a15,a10 # [0*II+7] id:767
ee.vmulas.u8.accx.ld.ip.qup q3,a15,16,q1,q3,q0,q2 # [0*II+9] id:769
.LBB163_dspi_dotprod_off_u8_aes3: # 0x1d1
st.qr q1,a1,48 # [0] q0
j .Lt_0_24578 # [1]
.LBB43_dspi_dotprod_off_u8_aes3: # 0x1d7
srli a3,a6,1 # [0]
l32i a12,a1,64 # [1] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [2] id:772
ee.ld.128.usar.ip q2,a15,16 # [3] id:773
addi a12,a12,-16 # [5]
ee.src.q.ld.xp q3,a15,a12,q1,q2 # [6] id:774
beqz.n a3,.Lt_0_26626 # [7]
ld.qr q0,a1,48 # [0] q0
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
loopnez a3,.LBB186_dspi_dotprod_off_u8_aes3 # [3]
.LBB184_dspi_dotprod_off_u8_aes3: # 0x1f5
ee.vmulas.u8.accx.ld.xp.qup q0,a15,a11,q0,q1,q2,q3 # [0*II+0] id:775
ee.vmulas.u8.accx.ld.ip q3,a2,16,q1,q6 # [0*II+1] id:776
ee.ld.128.usar.xp q1,a15,a10 # [0*II+2] id:777
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a12,q3,q2,q1,q0 # [0*II+4] id:778
ee.vmulas.u8.accx.ld.ip q4,a2,16,q2,q6 # [0*II+5] id:779
ee.vmulas.u8.accx.ld.xp.qup q2,a15,a11,q4,q1,q0,q3 # [0*II+7] id:780
ee.vmulas.u8.accx.ld.ip q3,a2,16,q1,q6 # [0*II+8] id:781
ee.ld.128.usar.xp q1,a15,a10 # [0*II+9] id:782
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a12,q3,q0,q1,q2 # [0*II+11] id:783
ee.vmulas.u8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+12] id:784
.LBB186_dspi_dotprod_off_u8_aes3: # 0x21b
st.qr q0,a1,48 # [0] q0
j .Lt_0_26626 # [1]
.LBB50_dspi_dotprod_off_u8_aes3: # 0x221
srli a3,a3,2 # [0]
movi.n a13,-16 # [1]
l32i a11,a1,64 # [2] gra_spill_temp_0
addi a15,a15,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a15,a13 # [5] id:785
ee.ld.128.usar.xp q1,a15,a11 # [6] id:786
ee.src.q.ld.xp q3,a15,a13,q1,q2 # [8] id:787
ee.ld.128.usar.xp q2,a15,a11 # [9] id:788
beqz.n a3,.Lt_0_28162 # [10]
ld.qr q0,a1,48 # [0] q0
movi.n a10,-16 # [1]
loopnez a3,.LBB209_dspi_dotprod_off_u8_aes3 # [2]
.LBB207_dspi_dotprod_off_u8_aes3: # 0x245
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a10,q0,q1,q2,q3 # [0*II+0] id:789
ee.vmulas.u8.accx.ld.ip q0,a2,16,q1,q6 # [0*II+1] id:790
ee.ld.128.usar.xp q1,a15,a11 # [0*II+2] id:791
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a10,q0,q2,q1,q3 # [0*II+4] id:792
ee.vmulas.u8.accx.ld.ip q0,a2,16,q2,q6 # [0*II+5] id:793
ee.ld.128.usar.xp q4,a15,a11 # [0*II+6] id:794
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a10,q0,q1,q4,q3 # [0*II+8] id:795
ee.vmulas.u8.accx.ld.ip q0,a2,16,q1,q6 # [0*II+9] id:796
ee.ld.128.usar.xp q1,a15,a11 # [0*II+10] id:797
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a10,q0,q4,q1,q3 # [0*II+12] id:798
ee.vmulas.u8.accx.ld.ip q0,a2,16,q4,q6 # [0*II+13] id:799
ee.ld.128.usar.xp q2,a15,a11 # [0*II+14] id:800
.LBB209_dspi_dotprod_off_u8_aes3: # 0x271
st.qr q0,a1,48 # [0] q0
j .Lt_0_28162 # [1]
.LBB57_dspi_dotprod_off_u8_aes3: # 0x277
ee.ld.128.usar.ip q1,a15,16 # [0] id:801
ee.ld.128.usar.ip q2,a15,16 # [1] id:802
ee.src.q.ld.ip q3,a15,16,q1,q2 # [3] id:803
beqz.n a3,.Lt_0_29698 # [4]
ld.qr q0,a1,48 # [0] q0
movi.n a10,32 # [1]
l32i a12,a1,64 # [2] gra_spill_temp_0
movi.n a11,-16 # [3]
sub a12,a12,a5 # [4]
addi a12,a12,16 # [5]
loopnez a3,.LBB232_dspi_dotprod_off_u8_aes3 # [6]
.LBB230_dspi_dotprod_off_u8_aes3: # 0x295
ee.vmulas.u8.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:804
ee.vmulas.u8.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:805
ee.vmulas.u8.accx.ld.xp.qup q4,a15,a12,q4,q2,q3,q0 # [0*II+3] id:806
ee.vmulas.u8.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:807
ee.vmulas.u8.accx.ld.xp.qup q2,a15,a11,q1,q3,q0,q4 # [0*II+6] id:808
ee.vmulas.u8.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:809
ee.ld.128.usar.xp q1,a15,a10 # [0*II+8] id:810
ee.vmulas.u8.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+10] id:811
ee.vmulas.u8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+11] id:812
.LBB232_dspi_dotprod_off_u8_aes3: # 0x2b8
st.qr q0,a1,48 # [0] q0
j .Lt_0_29698 # [1]
.LBB64_dspi_dotprod_off_u8_aes3: # 0x2be
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i a12,a1,64 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [3] id:813
ee.ld.128.usar.ip q2,a15,16 # [4] id:814
sub a12,a12,a5 # [6]
addi a12,a12,16 # [7]
ld.qr q0,a1,48 # [8] q0
ee.src.q.ld.ip q3,a15,16,q1,q2 # [9] id:815
mov.n a8,a15 # [10]
loopnez a3,.LBB254_dspi_dotprod_off_u8_aes3 # [11]
.LBB252_dspi_dotprod_off_u8_aes3: # 0x2dc
ee.vmulas.u8.accx.ld.ip.qup q0,a8,16,q0,q1,q2,q3 # [0*II+0] id:816
ee.vmulas.u8.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:817
ee.vmulas.u8.accx.ld.ip.qup q4,a8,16,q4,q2,q3,q0 # [0*II+3] id:818
ee.vmulas.u8.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:819
ee.vmulas.u8.accx.ld.ip.qup q1,a8,16,q1,q3,q0,q4 # [0*II+6] id:820
ee.vmulas.u8.accx.ld.ip q5,a2,16,q3,q6 # [0*II+7] id:821
ee.vmulas.u8.accx.ld.ip.qup q5,a8,16,q5,q0,q4,q1 # [0*II+9] id:822
ee.vmulas.u8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:823
ee.vmulas.u8.accx.ld.ip.qup q0,a8,16,q0,q4,q1,q5 # [0*II+12] id:824
ee.vmulas.u8.accx.ld.ip q4,a2,16,q4,q6 # [0*II+13] id:825
ee.vmulas.u8.accx.ld.xp.qup q4,a8,a12,q4,q1,q5,q0 # [0*II+15] id:826
ee.vmulas.u8.accx.ld.ip q1,a2,16,q1,q6 # [0*II+16] id:827
ee.vmulas.u8.accx.ld.xp.qup q2,a8,a11,q1,q5,q0,q4 # [0*II+18] id:828
ee.vmulas.u8.accx.ld.ip q4,a2,16,q5,q6 # [0*II+19] id:829
ee.ld.128.usar.xp q1,a8,a10 # [0*II+20] id:830
ee.vmulas.u8.accx.ld.ip.qup q3,a8,16,q4,q0,q1,q2 # [0*II+22] id:831
ee.vmulas.u8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+23] id:832
.LBB254_dspi_dotprod_off_u8_aes3: # 0x31f
movi.n a2,0 # [0]
movi.n a11,1 # [1]
addi.n a12,a7,-1 # [2]
rur.accx_0 a10 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:854
retw.n # [10]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 16,956
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_s16_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_61, 458755
# Program Unit: dspi_dotprod_off_s16_aes3
.type dspi_dotprod_off_s16_aes3, @function
.align 4
.global dspi_dotprod_off_s16_aes3
dspi_dotprod_off_s16_aes3: # 0x4
.LBB1_dspi_dotprod_off_s16_aes3: # 0x4
entry a1,128 #
l32i.n a10,a2,4 # [0] id:760
l32i.n a12,a2,12 # [1] id:759
mull a8,a10,a5 # [2]
blt a12,a8,.LBB83_dspi_dotprod_off_s16_aes3 # [4]
l32i.n a13,a2,8 # [0] id:761
l32i.n a9,a2,16 # [1] id:762
mull a11,a13,a6 # [2]
blt a9,a11,.LBB83_dspi_dotprod_off_s16_aes3 # [4]
l32i.n a15,a3,4 # [0] id:764
l32i.n a14,a3,12 # [1] id:763
mull a11,a15,a5 # [2]
blt a14,a11,.LBB83_dspi_dotprod_off_s16_aes3 # [4]
l32i.n a8,a3,16 # [0] id:766
l32i.n a9,a3,8 # [1] id:765
s32i a9,a1,88 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB83_dspi_dotprod_off_s16_aes3 # [5]
l32i.n a8,a3,0 # [0] id:767
s32i a8,a1,84 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_36354 # [2]
bne a14,a11,.Lt_0_36354 # [0]
bnei a15,1,.Lt_0_36354 # [0]
l32i a9,a1,88 # [0] gra_spill_temp_2
beqi a9,1,.Lt_0_19458 # [2]
.Lt_0_36354: # 0x46
.Lt_0_19714: # 0x46
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16si a8,a1,128 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:875
.type dspi_dotprod_off_s16_ansi, @function
call8 dspi_dotprod_off_s16_ansi # [8] dspi_dotprod_off_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB83_dspi_dotprod_off_s16_aes3: # 0x5e
l32r a2,.LC0_1_61 # [0]
retw.n # [1]
.Lt_0_19458: # 0x63
addi.n a9,a10,-1 # [0]
bnez a9,.Lt_0_37122 # [1]
addi.n a10,a13,-1 # [0]
bnez a10,.Lt_0_37122 # [1]
extui a11,a5,0,3 # [0]
bnez.n a11,.Lt_0_37122 # [1]
blti a6,4,.Lt_0_37122 # [0]
movi.n a14,32 # [0]
blt a14,a5,.LBB27_dspi_dotprod_off_s16_aes3 # [1]
.Lt_0_37634: # 0x7a
.Lt_0_21506: # 0x7a
l32i a15,a1,84 # [0] gra_spill_temp_1
l32i.n a2,a2,0 # [1] id:769
l16si a9,a1,128 # [2] id:768 offset+0x0
mull a10,a12,a13 # [3]
addi a8,a1,16 # [4] temp_offset
slli a10,a10,1 # [5]
s32i a10,a1,80 # [6] gra_spill_temp_0
movi.n a10,2 # [7]
# loop-count fixed at 2
loop a10,.LBB137_dspi_dotprod_off_s16_aes3 # [8]
.LBB132_dspi_dotprod_off_s16_aes3: # 0x93
s16i a9,a8,0 # [0*II+0] id:770 temp_offset+0x0
s16i a9,a8,2 # [0*II+1] id:770 temp_offset+0x0
s16i a9,a8,4 # [0*II+2] id:770 temp_offset+0x0
s16i a9,a8,6 # [0*II+3] id:770 temp_offset+0x0
s16i a9,a8,8 # [0*II+4] id:770 temp_offset+0x0
s16i a9,a8,10 # [0*II+5] id:770 temp_offset+0x0
s16i a9,a8,12 # [0*II+6] id:770 temp_offset+0x0
s16i a9,a8,14 # [0*II+7] id:770 temp_offset+0x0
addi a8,a8,16 # [0*II+8]
.LBB137_dspi_dotprod_off_s16_aes3: # 0xae
mov.n a3,a6 # [0]
addi a11,a5,-24 # [1]
addi a12,a1,24 # [3] temp_offset+8
movi.n a13,0 # [4]
wur.sar_byte a13 # [5]
wur.accx_0 a13 # [6]
wur.accx_1 a13 # [7]
ee.vld.128.ip q6,a12,0 # [8] id:771
s32i.n a12,a1,48 # [9] offset_data_ptr
beqz a11,.LBB34_dspi_dotprod_off_s16_aes3 # [10]
.Lt_0_25602: # 0xc8
.Lt_0_25090: # 0xc8
ee.vld.128.ip q0,a15,16 # [0] id:786
addi a14,a5,-16 # [1]
beqz a14,.LBB40_dspi_dotprod_off_s16_aes3 # [2]
.Lt_0_27138: # 0xd1
.Lt_0_26626: # 0xd1
addi a8,a5,-8 # [0]
beqz a8,.LBB46_dspi_dotprod_off_s16_aes3 # [1]
.Lt_0_28674: # 0xd7
.Lt_0_28162: # 0xd7
addi a9,a5,-32 # [0]
beqz a9,.LBB52_dspi_dotprod_off_s16_aes3 # [1]
.Lt_0_30210: # 0xdd
.Lt_0_29698: # 0xdd
addi a10,a5,-64 # [0]
beqz a10,.LBB58_dspi_dotprod_off_s16_aes3 # [1]
movi.n a11,64 # [0]
bge a11,a5,.Lt_0_33026 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a2,16 # [1] id:848
ee.ld.128.usar.ip q2,a2,16 # [2] id:849
ee.src.q.ld.ip q3,a2,16,q1,q2 # [4] id:850
beqz.n a3,.Lt_0_33026 # [5]
slli a8,a5,1 # [0]
l32i a14,a1,80 # [1] gra_spill_temp_0
addi a13,a5,31 # [2]
movgez a13,a5,a5 # [3]
srai a13,a13,5 # [4]
sub a14,a14,a8 # [5]
addi a14,a14,16 # [6]
addi.n a13,a13,-1 # [7]
.Lt_0_33794: # 0x10c
beqz.n a13,.Lt_0_34050 # [0]
loopnez a13,.LBB273_dspi_dotprod_off_s16_aes3 # [0]
.LBB271_dspi_dotprod_off_s16_aes3: # 0x111
ee.vmulas.s16.accx.ld.ip.qup q0,a2,16,q0,q1,q2,q3 # [0*II+0] id:851
ee.vmulas.s16.accx.ld.ip q1,a15,16,q1,q6 # [0*II+1] id:852
ee.vmulas.s16.accx.ld.ip.qup q1,a2,16,q1,q2,q3,q0 # [0*II+3] id:853
ee.vmulas.s16.accx.ld.ip q4,a15,16,q2,q6 # [0*II+4] id:854
ee.vmulas.s16.accx.ld.ip.qup q2,a2,16,q4,q3,q0,q1 # [0*II+6] id:855
ee.vmulas.s16.accx.ld.ip q4,a15,16,q3,q6 # [0*II+7] id:856
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q4,q0,q1,q2 # [0*II+9] id:857
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [0*II+10] id:858
.LBB273_dspi_dotprod_off_s16_aes3: # 0x131
.Lt_0_34050: # 0x131
ee.vmulas.s16.accx.ld.ip.qup q0,a2,16,q0,q1,q2,q3 # [0] id:859
ee.vmulas.s16.accx.ld.ip q1,a15,16,q1,q6 # [1] id:860
movi.n a9,32 # [2]
ee.vmulas.s16.accx.ld.xp.qup q7,a2,a14,q1,q2,q3,q0 # [3] id:861
ee.vmulas.s16.accx.ld.ip q5,a15,16,q2,q6 # [4] id:862
movi.n a10,-16 # [5]
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a10,q5,q3,q0,q7 # [6] id:863
ee.vmulas.s16.accx.ld.ip q4,a15,16,q3,q6 # [7] id:865
ee.ld.128.usar.xp q1,a2,a9 # [8] id:864
addi.n a12,a12,1 # [9]
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q4,q0,q1,q2 # [10] id:866
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [11] id:867
bne a12,a3,.Lt_0_33794 # [12]
.Lt_0_33026: # 0x15d
.Lt_0_32770: # 0x15d
rur.accx_0 a9 # [0]
rur.accx_1 a10 # [1]
blti a7,1,.Lt_0_35586 # [2]
movi.n a2,0 # [0]
addi a13,a7,-33 # [1]
addi.n a14,a7,-1 # [2]
ssr a14 # [3]
sra a12,a10 # [4]
src a11,a10,a9 # [5]
movgez a11,a12,a13 # [6]
addi.n a11,a11,1 # [7]
srai a11,a11,1 # [8]
s16i a11,a4,0 # [9] id:873
retw.n # [10]
.Lt_0_37122: # 0x183
.Lt_0_20738: # 0x183
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16si a8,a1,128 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:876
call8 dspi_dotprod_off_s16_ansi # [8] dspi_dotprod_off_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB27_dspi_dotprod_off_s16_aes3: # 0x19b
extui a9,a5,0,1 # [0]
beqz a9,.Lt_0_37634 # [1]
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16si a8,a1,128 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:877
call8 dspi_dotprod_off_s16_ansi # [8] dspi_dotprod_off_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB34_dspi_dotprod_off_s16_aes3: # 0x1b9
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i a12,a1,80 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q0,a2,16 # [3] id:776
ee.ld.128.usar.ip q2,a2,16 # [4] id:777
addi a12,a12,-32 # [5]
ee.src.q.ld.ip q3,a2,16,q0,q2 # [6] id:778
loopgtz a6,.LBB159_dspi_dotprod_off_s16_aes3 # [7]
.LBB157_dspi_dotprod_off_s16_aes3: # 0x1cf
ee.vmulas.s16.accx.ld.ip q1,a15,16,q0,q6 # [0*II+0] id:779
ee.vmulas.s16.accx.ld.xp.qup q1,a2,a12,q1,q0,q2,q3 # [0*II+2] id:780
ee.vmulas.s16.accx.ld.ip q0,a15,16,q2,q6 # [0*II+3] id:781
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q0,q2,q3,q1 # [0*II+5] id:782
ee.vmulas.s16.accx.ld.ip q1,a15,16,q3,q6 # [0*II+6] id:784
ee.ld.128.usar.xp q0,a2,a10 # [0*II+7] id:783
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q1,q3,q0,q2 # [0*II+9] id:785
.LBB159_dspi_dotprod_off_s16_aes3: # 0x1ea
j .Lt_0_25602 # [0]
.LBB40_dspi_dotprod_off_s16_aes3: # 0x1ed
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
srli a3,a6,1 # [2]
l32i a12,a1,80 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:787
ee.ld.128.usar.ip q2,a2,16 # [5] id:788
addi a12,a12,-16 # [7]
ee.src.q.ld.xp q3,a2,a12,q1,q2 # [8] id:789
loopnez a3,.LBB182_dspi_dotprod_off_s16_aes3 # [9]
.LBB180_dspi_dotprod_off_s16_aes3: # 0x206
ee.vmulas.s16.accx.ld.xp.qup q0,a2,a11,q0,q1,q2,q3 # [0*II+0] id:790
ee.vmulas.s16.accx.ld.ip q3,a15,16,q1,q6 # [0*II+1] id:791
ee.ld.128.usar.xp q1,a2,a10 # [0*II+2] id:792
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a12,q3,q2,q1,q0 # [0*II+4] id:793
ee.vmulas.s16.accx.ld.ip q4,a15,16,q2,q6 # [0*II+5] id:794
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q4,q1,q0,q3 # [0*II+7] id:795
ee.vmulas.s16.accx.ld.ip q3,a15,16,q1,q6 # [0*II+8] id:796
ee.ld.128.usar.xp q1,a2,a10 # [0*II+9] id:797
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a12,q3,q0,q1,q2 # [0*II+11] id:798
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [0*II+12] id:799
.LBB182_dspi_dotprod_off_s16_aes3: # 0x22c
j .Lt_0_27138 # [0]
.LBB46_dspi_dotprod_off_s16_aes3: # 0x22f
movi.n a10,-16 # [0]
l32i a11,a1,80 # [1] gra_spill_temp_0
addi a8,a2,16 # [2]
addi a11,a11,16 # [3]
ee.ld.128.usar.xp q2,a8,a10 # [4] id:800
ee.ld.128.usar.xp q1,a8,a11 # [5] id:801
ee.src.q.ld.xp q3,a8,a10,q1,q2 # [7] id:802
ee.ld.128.usar.xp q2,a8,a11 # [8] id:803
srli a3,a3,2 # [9]
mov.n a2,a8 # [10]
loopnez a3,.LBB205_dspi_dotprod_off_s16_aes3 # [11]
.LBB203_dspi_dotprod_off_s16_aes3: # 0x24e
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a10,q0,q1,q2,q3 # [0*II+0] id:804
ee.vmulas.s16.accx.ld.ip q0,a15,16,q1,q6 # [0*II+1] id:805
ee.ld.128.usar.xp q1,a2,a11 # [0*II+2] id:806
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a10,q0,q2,q1,q3 # [0*II+4] id:807
ee.vmulas.s16.accx.ld.ip q0,a15,16,q2,q6 # [0*II+5] id:808
ee.ld.128.usar.xp q4,a2,a11 # [0*II+6] id:809
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a10,q0,q1,q4,q3 # [0*II+8] id:810
ee.vmulas.s16.accx.ld.ip q0,a15,16,q1,q6 # [0*II+9] id:811
ee.ld.128.usar.xp q1,a2,a11 # [0*II+10] id:812
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a10,q0,q4,q1,q3 # [0*II+12] id:813
ee.vmulas.s16.accx.ld.ip q0,a15,16,q4,q6 # [0*II+13] id:814
ee.ld.128.usar.xp q2,a2,a11 # [0*II+14] id:815
.LBB205_dspi_dotprod_off_s16_aes3: # 0x27a
j .Lt_0_28674 # [0]
.LBB52_dspi_dotprod_off_s16_aes3: # 0x27d
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i a12,a1,80 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:816
ee.ld.128.usar.ip q2,a2,16 # [5] id:817
sub a12,a12,a13 # [6]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [8] id:818
addi a12,a12,16 # [9]
loopnez a3,.LBB228_dspi_dotprod_off_s16_aes3 # [10]
.LBB226_dspi_dotprod_off_s16_aes3: # 0x299
ee.vmulas.s16.accx.ld.ip.qup q0,a2,16,q0,q1,q2,q3 # [0*II+0] id:819
ee.vmulas.s16.accx.ld.ip q4,a15,16,q1,q6 # [0*II+1] id:820
ee.vmulas.s16.accx.ld.xp.qup q4,a2,a12,q4,q2,q3,q0 # [0*II+3] id:821
ee.vmulas.s16.accx.ld.ip q1,a15,16,q2,q6 # [0*II+4] id:822
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q1,q3,q0,q4 # [0*II+6] id:823
ee.vmulas.s16.accx.ld.ip q4,a15,16,q3,q6 # [0*II+7] id:825
ee.ld.128.usar.xp q1,a2,a10 # [0*II+8] id:824
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q4,q0,q1,q2 # [0*II+10] id:826
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [0*II+11] id:827
.LBB228_dspi_dotprod_off_s16_aes3: # 0x2bc
j .Lt_0_30210 # [0]
.LBB58_dspi_dotprod_off_s16_aes3: # 0x2bf
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i a12,a1,80 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:828
ee.ld.128.usar.ip q2,a2,16 # [5] id:829
sub a12,a12,a13 # [7]
addi a12,a12,16 # [8]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [9] id:830
mov.n a8,a2 # [10]
loopnez a3,.LBB250_dspi_dotprod_off_s16_aes3 # [11]
.LBB248_dspi_dotprod_off_s16_aes3: # 0x2dd
ee.vmulas.s16.accx.ld.ip.qup q0,a8,16,q0,q1,q2,q3 # [0*II+0] id:831
ee.vmulas.s16.accx.ld.ip q4,a15,16,q1,q6 # [0*II+1] id:832
ee.vmulas.s16.accx.ld.ip.qup q4,a8,16,q4,q2,q3,q0 # [0*II+3] id:833
ee.vmulas.s16.accx.ld.ip q1,a15,16,q2,q6 # [0*II+4] id:834
ee.vmulas.s16.accx.ld.ip.qup q1,a8,16,q1,q3,q0,q4 # [0*II+6] id:835
ee.vmulas.s16.accx.ld.ip q5,a15,16,q3,q6 # [0*II+7] id:836
ee.vmulas.s16.accx.ld.ip.qup q5,a8,16,q5,q0,q4,q1 # [0*II+9] id:837
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [0*II+10] id:838
ee.vmulas.s16.accx.ld.ip.qup q0,a8,16,q0,q4,q1,q5 # [0*II+12] id:839
ee.vmulas.s16.accx.ld.ip q4,a15,16,q4,q6 # [0*II+13] id:840
ee.vmulas.s16.accx.ld.xp.qup q4,a8,a12,q4,q1,q5,q0 # [0*II+15] id:841
ee.vmulas.s16.accx.ld.ip q1,a15,16,q1,q6 # [0*II+16] id:842
ee.vmulas.s16.accx.ld.xp.qup q2,a8,a11,q1,q5,q0,q4 # [0*II+18] id:843
ee.vmulas.s16.accx.ld.ip q4,a15,16,q5,q6 # [0*II+19] id:845
ee.ld.128.usar.xp q1,a8,a10 # [0*II+20] id:844
ee.vmulas.s16.accx.ld.ip.qup q3,a8,16,q4,q0,q1,q2 # [0*II+22] id:846
ee.vmulas.s16.accx.ld.ip q0,a15,16,q0,q6 # [0*II+23] id:847
.LBB250_dspi_dotprod_off_s16_aes3: # 0x320
j .Lt_0_33026 # [0]
.Lt_0_35586: # 0x323
movi.n a2,0 # [0]
sext a14,a9,15 # [1]
s16i a14,a4,0 # [2] id:874
retw.n # [3]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,626
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_u8_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_u8_arp4
.global dspi_dotprod_u8_ansi
.type dspi_dotprod_u8_arp4,@function
// esp_err_t dspi_dotprod_u8_arp4(image2d_t *in_image, image2d_t *filter, uint8_t *out_value, int count_x, int count_y, int shift);
dspi_dotprod_u8_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 15
or t1, t1, t2
beqz t1, .dspi_dotprod_u8_arp4_body
j dspi_dotprod_u8_ansi
.dspi_dotprod_u8_arp4_body:
add sp, sp, -16
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
srli t6, a3, 4 // t5 = len/16
addi a6, a5, -1
li t4, 1
sll t4, t4, a6
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q0, t4, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q1, t5, 16 // q1 - f_data
.loop_count_x: esp.vmulas.u8.xacc.ld.ip q0, t4, 16, q0, q1 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.u.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 2,851
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_s8_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_off_s8_arp4
.global dspi_dotprod_off_s8_ansi
.type dspi_dotprod_off_s8_arp4,@function
// esp_err_t dspi_dotprod_off_s8_arp4(image2d_t *in_image, image2d_t *filter, int16_t *out_value, int count_x, int count_y, int shift, int8_t offset);
dspi_dotprod_off_s8_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// offset - a6
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 15
or t1, t1, t2
beqz t1, .dspi_dotprod_off_s8_arp4_body
j dspi_dotprod_off_s8_ansi
.dspi_dotprod_off_s8_arp4_body:
add sp, sp, -16
sw a6, 0(sp)
mv t6, sp
esp.vldbc.8.ip q2, t6, 0
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
srli t6, a3, 4 // t5 = len/16
addi a7, a5, -1
li t4, 1
sll t4, t4, a7
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q1, t5, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q0, t4, 16 // q1 - f_data
esp.vadd.s8 q3, q2, q1
.loop_count_x: esp.vmulas.s8.xacc.ld.ip q1, t5, 16, q0, q3 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.s.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 2,713
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_s16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_s16_arp4
.global dspi_dotprod_s16_ansi
.type dspi_dotprod_s16_arp4,@function
// esp_err_t dspi_dotprod_s16_arp4(image2d_t *in_image, image2d_t *filter, int16_t *out_value, int count_x, int count_y, int shift);
dspi_dotprod_s16_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 7
or t1, t1, t2
beqz t1, .dspi_dotprod_s16_arp4_body
j dspi_dotprod_s16_ansi
.dspi_dotprod_s16_arp4_body:
add sp, sp, -16
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
slli t2, t2, 1 // i_step = i_step<<1
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
slli t3, t3, 1 // f_step = f_step<<1
srli t6, a3, 3 // t5 = len/8
addi a6, a5, -1
li t4, 1
sll t4, t4, a6
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q0, t4, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q1, t5, 16 // q1 - f_data
.loop_count_x: esp.vmulas.s16.xacc.ld.ip q0, t4, 16, q0, q1 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.s.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 1,893
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dsps_dotprod_s16_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dsps_dotprod_s16_ae32_enabled == 1)
#include "dsps_dotprod_s16_m_ae32.S"
#include "dsp_err_codes.h"
.text
.align 4
.global dsps_dotprod_s16_ae32
.type dsps_dotprod_s16_ae32,@function
//esp_err_t dsps_dotprod_s16_ae32(const int16_t* src1, const int16_t* src2, int16_t* dest, int len, int8_t shift);
dsps_dotprod_s16_ae32:
// src1 - a2
// src2 - a3
// dest - a4
// len - a5
// shift - a6
entry a1, 16
// Check minimum length
movi a8, 4
blt a5, a8, dsps_dotprod_s16_ae32_error
// Clear accumulator
movi a8, 0
wsr a8, acchi
// Prepare and load round value
movi a8, 0x7fff
ssr a6
srl a8, a8
wsr a8, acclo // initialize acc with shifted round value
// Compensate for pre-increment
// Right shift to 16 bits
// RS = -shift + 15
neg a6, a6
addi a6, a6, 15
/* number of loop iterations (see below):
* a7 = count / 4 - 1
*/
srli a7, a5, 2
addi a7, a7, -1
movi.n a10, 0 // load 0 to the a10 to increment second array
dotprod_s16_ae32_full a2, a3, a7, a5
/* Get accumulator */
ssr a6
rsr a2, acchi
rsr a3, acclo
src a2, a2, a3
s16i a2, a4, 0
movi.n a2, 0
retw.n
dsps_dotprod_s16_ae32_error:
movi.n a2, ESP_ERR_DSP_INVALID_LENGTH
retw.n
#endif // dsps_dotprod_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 14,668
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_u16_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_55, 458755
# Program Unit: dspi_dotprod_u16_aes3
.type dspi_dotprod_u16_aes3, @function
.align 4
.global dspi_dotprod_u16_aes3
dspi_dotprod_u16_aes3: # 0x4
.LBB1_dspi_dotprod_u16_aes3: # 0x4
entry a1,64 #
l32i.n a10,a2,4 # [0] id:681
l32i.n a11,a2,12 # [1] id:680
mull a8,a10,a5 # [2]
blt a11,a8,.LBB81_dspi_dotprod_u16_aes3 # [4]
l32i.n a12,a2,8 # [0] id:682
l32i.n a9,a2,16 # [1] id:683
mull a13,a12,a6 # [2]
blt a9,a13,.LBB81_dspi_dotprod_u16_aes3 # [4]
l32i.n a15,a3,4 # [0] id:685
l32i.n a14,a3,12 # [1] id:684
mull a13,a15,a5 # [2]
blt a14,a13,.LBB81_dspi_dotprod_u16_aes3 # [4]
l32i.n a8,a3,16 # [0] id:687
l32i.n a9,a3,8 # [1] id:686
s32i.n a9,a1,24 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB81_dspi_dotprod_u16_aes3 # [5]
l32i.n a8,a3,0 # [0] id:688
s32i.n a8,a1,20 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_34050 # [2]
bne a14,a13,.Lt_0_34050 # [0]
bnei a15,1,.Lt_0_34050 # [0]
l32i.n a9,a1,24 # [0] gra_spill_temp_2
beqi a9,1,.Lt_0_18178 # [2]
.Lt_0_34050: # 0x43
.Lt_0_18434: # 0x43
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
.type dspi_dotprod_s16_ansi, @function
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB81_dspi_dotprod_u16_aes3: # 0x56
l32r a2,.LC0_1_55 # [0]
retw.n # [1]
.Lt_0_18178: # 0x5b
addi.n a13,a10,-1 # [0]
bnez a13,.Lt_0_34818 # [1]
addi.n a14,a12,-1 # [0]
bnez a14,.Lt_0_34818 # [1]
extui a15,a5,0,3 # [0]
bnez.n a15,.Lt_0_34818 # [1]
blti a6,4,.Lt_0_34818 # [0]
movi.n a8,32 # [0]
bge a8,a5,.Lt_0_35330 # [1]
extui a9,a5,0,1 # [0]
bnez a9,.LBB28_dspi_dotprod_u16_aes3 # [1]
.Lt_0_35330: # 0x78
.Lt_0_20226: # 0x78
mov.n a3,a6 # [0]
addi a10,a5,-24 # [1]
mull a13,a11,a12 # [2]
l32i.n a15,a1,20 # [3] gra_spill_temp_1
l32i.n a2,a2,0 # [4] id:689
movi.n a14,0 # [5]
wur.sar_byte a14 # [6]
wur.accx_0 a14 # [8]
wur.accx_1 a14 # [9]
ee.vld.128.ip q0,a15,16 # [10] id:693
slli a13,a13,1 # [11]
s32i.n a13,a1,16 # [12] gra_spill_temp_0
beqz a10,.LBB32_dspi_dotprod_u16_aes3 # [13]
.Lt_0_23298: # 0x99
.Lt_0_22786: # 0x99
addi a8,a5,-16 # [0]
beqz a8,.LBB38_dspi_dotprod_u16_aes3 # [1]
.Lt_0_24834: # 0x9f
.Lt_0_24322: # 0x9f
addi a9,a5,-8 # [0]
beqz a9,.LBB44_dspi_dotprod_u16_aes3 # [1]
.Lt_0_26370: # 0xa5
.Lt_0_25858: # 0xa5
addi a10,a5,-32 # [0]
beqz a10,.LBB50_dspi_dotprod_u16_aes3 # [1]
.Lt_0_27906: # 0xab
.Lt_0_27394: # 0xab
addi a11,a5,-64 # [0]
beqz a11,.LBB56_dspi_dotprod_u16_aes3 # [1]
movi.n a12,64 # [0]
bge a12,a5,.Lt_0_30722 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a2,16 # [1] id:765
ee.ld.128.usar.ip q2,a2,16 # [2] id:766
ee.src.q.ld.ip q3,a2,16,q1,q2 # [4] id:767
beqz.n a3,.Lt_0_30722 # [5]
slli a8,a5,1 # [0]
l32i.n a14,a1,16 # [1] gra_spill_temp_0
addi a13,a5,31 # [2]
movgez a13,a5,a5 # [3]
srai a13,a13,5 # [4]
sub a14,a14,a8 # [5]
addi a14,a14,16 # [6]
addi.n a13,a13,-1 # [7]
.Lt_0_31490: # 0xd9
addi.n a12,a12,1 # [0]
movi.n a9,32 # [1]
beqz.n a13,.Lt_0_31746 # [2]
loopnez a13,.LBB221_dspi_dotprod_u16_aes3 # [0]
.LBB219_dspi_dotprod_u16_aes3: # 0xe2
ee.vld.128.ip q5,a15,16 # [0*II+0] id:769
ee.vmulas.u16.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:768
ee.vld.128.ip q0,a15,16 # [0*II+2] id:771
ee.vmulas.u16.accx.ld.ip.qup q1,a2,16,q5,q2,q3,q4 # [0*II+3] id:770
ee.vld.128.ip q5,a15,16 # [0*II+4] id:773
ee.vmulas.u16.accx.ld.ip.qup q2,a2,16,q0,q3,q4,q1 # [0*II+5] id:772
ee.vld.128.ip q0,a15,16 # [0*II+6] id:775
ee.vmulas.u16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+7] id:774
.LBB221_dspi_dotprod_u16_aes3: # 0xfe
.Lt_0_31746: # 0xfe
ee.vmulas.u16.accx.ld.ip.qup q5,a2,16,q0,q1,q2,q3 # [0] id:776
movi.n a10,-16 # [1]
ee.vld.128.ip q0,a15,16 # [2] id:777
ee.vld.128.ip q6,a15,16 # [3] id:779
ee.vmulas.u16.accx.ld.xp.qup q7,a2,a14,q0,q2,q3,q5 # [4] id:778
ee.vld.128.ip q4,a15,16 # [5] id:782
ee.vmulas.u16.accx.ld.xp.qup q2,a2,a10,q6,q3,q5,q7 # [6] id:780
ee.ld.128.usar.xp q1,a2,a9 # [7] id:781
ee.vld.128.ip q0,a15,16 # [8] id:784
ee.vmulas.u16.accx.ld.ip.qup q3,a2,16,q4,q5,q1,q2 # [9] id:783
bne a12,a3,.Lt_0_31490 # [10]
.Lt_0_30722: # 0x122
.Lt_0_30466: # 0x122
rur.accx_0 a9 # [0]
rur.accx_1 a10 # [1]
blti a7,1,.Lt_0_33282 # [2]
movi.n a2,0 # [0]
addi a13,a7,-33 # [1]
addi.n a14,a7,-1 # [2]
ssr a14 # [3]
sra a12,a10 # [4]
src a11,a10,a9 # [5]
movgez a11,a12,a13 # [6]
addi.n a11,a11,1 # [7]
srli a11,a11,1 # [8]
s16i a11,a4,0 # [9] id:790
retw.n # [10]
.Lt_0_34818: # 0x148
.Lt_0_19458: # 0x148
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB32_dspi_dotprod_u16_aes3: # 0x15b
ee.ld.128.usar.ip q1,a2,16 # [0] id:694
ee.ld.128.usar.ip q2,a2,16 # [1] id:695
ee.src.q.ld.ip q3,a2,16,q1,q2 # [3] id:696
beqz.n a6,.Lt_0_23298 # [4]
addi a12,a13,-32 # [0]
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
loopgtz a6,.LBB107_dspi_dotprod_u16_aes3 # [3]
.LBB105_dspi_dotprod_u16_aes3: # 0x170
ee.vld.128.ip q4,a15,16 # [0*II+0] id:698
ee.vmulas.u16.accx.ld.xp.qup q1,a2,a12,q0,q1,q2,q3 # [0*II+1] id:697
ee.vld.128.ip q5,a15,16 # [0*II+2] id:700
ee.vmulas.u16.accx.ld.xp.qup q2,a2,a11,q4,q2,q3,q1 # [0*II+3] id:699
ee.ld.128.usar.xp q1,a2,a10 # [0*II+4] id:701
ee.vld.128.ip q0,a15,16 # [0*II+5] id:703
ee.vmulas.u16.accx.ld.ip.qup q3,a2,16,q5,q3,q1,q2 # [0*II+6] id:702
.LBB107_dspi_dotprod_u16_aes3: # 0x188
j .Lt_0_23298 # [0]
.LBB38_dspi_dotprod_u16_aes3: # 0x18b
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
srli a3,a6,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:704
ee.ld.128.usar.ip q2,a2,16 # [5] id:705
addi a12,a12,-16 # [7]
ee.src.q.ld.xp q3,a2,a12,q1,q2 # [8] id:706
loopnez a3,.LBB130_dspi_dotprod_u16_aes3 # [9]
.LBB128_dspi_dotprod_u16_aes3: # 0x1a3
ee.vld.128.ip q4,a15,16 # [0*II+0] id:708
ee.vmulas.u16.accx.ld.xp.qup q3,a2,a11,q0,q1,q2,q3 # [0*II+1] id:707
ee.ld.128.usar.xp q1,a2,a10 # [0*II+2] id:709
ee.vld.128.ip q0,a15,16 # [0*II+3] id:711
ee.vmulas.u16.accx.ld.xp.qup q4,a2,a12,q4,q2,q1,q3 # [0*II+4] id:710
ee.vld.128.ip q5,a15,16 # [0*II+5] id:713
ee.vmulas.u16.accx.ld.xp.qup q2,a2,a11,q0,q1,q3,q4 # [0*II+6] id:712
ee.ld.128.usar.xp q1,a2,a10 # [0*II+7] id:714
ee.vld.128.ip q0,a15,16 # [0*II+8] id:716
ee.vmulas.u16.accx.ld.xp.qup q3,a2,a12,q5,q3,q1,q2 # [0*II+9] id:715
.LBB130_dspi_dotprod_u16_aes3: # 0x1c5
j .Lt_0_24834 # [0]
.LBB44_dspi_dotprod_u16_aes3: # 0x1c8
srli a3,a3,2 # [0]
movi.n a10,-16 # [1]
l32i.n a11,a1,16 # [2] gra_spill_temp_0
addi a8,a2,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a8,a10 # [5] id:717
ee.ld.128.usar.xp q1,a8,a11 # [6] id:718
ee.src.q.ld.xp q3,a8,a10,q1,q2 # [8] id:719
ee.ld.128.usar.xp q2,a8,a11 # [9] id:720
loopnez a3,.LBB153_dspi_dotprod_u16_aes3 # [10]
.LBB151_dspi_dotprod_u16_aes3: # 0x1e4
ee.vld.128.ip q4,a15,16 # [0*II+0] id:722
ee.vmulas.u16.accx.ld.xp.qup q3,a8,a10,q0,q1,q2,q3 # [0*II+1] id:721
ee.ld.128.usar.xp q1,a8,a11 # [0*II+2] id:723
ee.vld.128.ip q0,a15,16 # [0*II+3] id:725
ee.vmulas.u16.accx.ld.xp.qup q4,a8,a10,q4,q2,q1,q3 # [0*II+4] id:724
ee.ld.128.usar.xp q3,a8,a11 # [0*II+5] id:726
ee.vld.128.ip q5,a15,16 # [0*II+6] id:728
ee.vmulas.u16.accx.ld.xp.qup q4,a8,a10,q0,q1,q3,q4 # [0*II+7] id:727
ee.ld.128.usar.xp q1,a8,a11 # [0*II+8] id:729
ee.vld.128.ip q0,a15,16 # [0*II+9] id:731
ee.vmulas.u16.accx.ld.xp.qup q3,a8,a10,q5,q3,q1,q4 # [0*II+10] id:730
ee.ld.128.usar.xp q2,a8,a11 # [0*II+11] id:732
.LBB153_dspi_dotprod_u16_aes3: # 0x20c
mov.n a2,a8 # [0]
j .Lt_0_26370 # [1]
.LBB50_dspi_dotprod_u16_aes3: # 0x211
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:733
ee.ld.128.usar.ip q2,a2,16 # [5] id:734
sub a12,a12,a13 # [6]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [8] id:735
addi a12,a12,16 # [9]
loopnez a3,.LBB176_dspi_dotprod_u16_aes3 # [10]
.LBB174_dspi_dotprod_u16_aes3: # 0x22c
ee.vld.128.ip q5,a15,16 # [0*II+0] id:737
ee.vmulas.u16.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:736
ee.vld.128.ip q1,a15,16 # [0*II+2] id:739
ee.vmulas.u16.accx.ld.xp.qup q0,a2,a12,q5,q2,q3,q4 # [0*II+3] id:738
ee.vld.128.ip q5,a15,16 # [0*II+4] id:742
ee.vmulas.u16.accx.ld.xp.qup q2,a2,a11,q1,q3,q4,q0 # [0*II+5] id:740
ee.ld.128.usar.xp q1,a2,a10 # [0*II+6] id:741
ee.vld.128.ip q0,a15,16 # [0*II+7] id:744
ee.vmulas.u16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+8] id:743
.LBB176_dspi_dotprod_u16_aes3: # 0x24b
j .Lt_0_27906 # [0]
.LBB56_dspi_dotprod_u16_aes3: # 0x24e
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:745
ee.ld.128.usar.ip q2,a2,16 # [5] id:746
sub a12,a12,a13 # [7]
addi a12,a12,16 # [8]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [9] id:747
loopnez a3,.LBB198_dspi_dotprod_u16_aes3 # [10]
.LBB196_dspi_dotprod_u16_aes3: # 0x269
ee.vld.128.ip q4,a15,16 # [0*II+0] id:749
ee.vmulas.u16.accx.ld.ip.qup q1,a2,16,q0,q1,q2,q3 # [0*II+1] id:748
ee.vld.128.ip q0,a15,16 # [0*II+2] id:751
ee.vmulas.u16.accx.ld.ip.qup q4,a2,16,q4,q2,q3,q1 # [0*II+3] id:750
ee.vld.128.ip q5,a15,16 # [0*II+4] id:753
ee.vmulas.u16.accx.ld.ip.qup q0,a2,16,q0,q3,q1,q4 # [0*II+5] id:752
ee.vld.128.ip q6,a15,16 # [0*II+6] id:755
ee.vmulas.u16.accx.ld.ip.qup q1,a2,16,q5,q1,q4,q0 # [0*II+7] id:754
ee.vld.128.ip q5,a15,16 # [0*II+8] id:757
ee.vmulas.u16.accx.ld.ip.qup q4,a2,16,q6,q4,q0,q1 # [0*II+9] id:756
ee.vld.128.ip q6,a15,16 # [0*II+10] id:759
ee.vmulas.u16.accx.ld.xp.qup q0,a2,a12,q5,q0,q1,q4 # [0*II+11] id:758
ee.vld.128.ip q5,a15,16 # [0*II+12] id:762
ee.vmulas.u16.accx.ld.xp.qup q2,a2,a11,q6,q1,q4,q0 # [0*II+13] id:760
ee.ld.128.usar.xp q1,a2,a10 # [0*II+14] id:761
ee.vld.128.ip q0,a15,16 # [0*II+15] id:764
ee.vmulas.u16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+16] id:763
.LBB198_dspi_dotprod_u16_aes3: # 0x2a4
j .Lt_0_30722 # [0]
.Lt_0_33282: # 0x2a7
movi.n a2,0 # [0]
sext a14,a9,15 # [1]
s16i a14,a4,0 # [2] id:791
retw.n # [3]
.LBB28_dspi_dotprod_u16_aes3: # 0x2b1
mov.n a15,a7 # [0]
mov.n a14,a6 # [1]
mov.n a13,a5 # [2]
mov.n a12,a4 # [3]
mov.n a11,a3 # [4]
mov.n a10,a2 # [5]
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,937
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_u16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_off_u16_arp4
.global dspi_dotprod_off_u16_ansi
.type dspi_dotprod_off_u16_arp4,@function
// esp_err_t dspi_dotprod_off_u16_arp4(image2d_t *in_image, image2d_t *filter, int16_t *out_value, int count_x, int count_y, int shift, unt16_t offset);
dspi_dotprod_off_u16_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// offset - a6
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 7
or t1, t1, t2
beqz t1, .dspi_dotprod_off_u16_arp4_body
j dspi_dotprod_off_u16_ansi
.dspi_dotprod_off_u16_arp4_body:
add sp, sp, -16
sw a6, 0(sp)
mv t6, sp
esp.vldbc.16.ip q2, t6, 0
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
slli t2, t2, 1 // i_step = i_step<<1
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
slli t3, t3, 1 // f_step = f_step<<1
srli t6, a3, 3 // t5 = len/8
addi a7, a5, -1
li t4, 1
sll t4, t4, a7
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q1, t5, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q0, t4, 16 // q1 - f_data
esp.vadd.u16 q3, q2, q1
.loop_count_x: esp.vmulas.u16.xacc.ld.ip q1, t5, 16, q0, q3 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.u.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 17,082
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_s8_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_57, 458755
# Program Unit: dspi_dotprod_off_s8_aes3
.type dspi_dotprod_off_s8_aes3, @function
.align 4
.global dspi_dotprod_off_s8_aes3
dspi_dotprod_off_s8_aes3: # 0x4
.LBB1_dspi_dotprod_off_s8_aes3: # 0x4
entry a1,112 #
l32i.n a10,a2,4 # [0] id:745
l32i.n a12,a2,12 # [1] id:744
mull a8,a10,a5 # [2]
blt a12,a8,.LBB86_dspi_dotprod_off_s8_aes3 # [4]
l32i.n a13,a2,8 # [0] id:746
l32i.n a9,a2,16 # [1] id:747
mull a11,a13,a6 # [2]
blt a9,a11,.LBB86_dspi_dotprod_off_s8_aes3 # [4]
l32i.n a15,a3,4 # [0] id:749
l32i.n a14,a3,12 # [1] id:748
mull a11,a15,a5 # [2]
blt a14,a11,.LBB86_dspi_dotprod_off_s8_aes3 # [4]
l32i.n a8,a3,16 # [0] id:751
l32i.n a9,a3,8 # [1] id:750
s32i a9,a1,72 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB86_dspi_dotprod_off_s8_aes3 # [5]
l32i.n a8,a3,0 # [0] id:752
s32i a8,a1,68 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_35330 # [2]
bne a14,a11,.Lt_0_35330 # [0]
bnei a15,1,.Lt_0_35330 # [0]
l32i a11,a1,72 # [0] gra_spill_temp_2
beqi a11,1,.Lt_0_18946 # [2]
.Lt_0_35330: # 0x46
.Lt_0_19202: # 0x46
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
.type dspi_dotprod_s8_ansi, @function
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB86_dspi_dotprod_off_s8_aes3: # 0x59
l32r a2,.LC0_1_57 # [0]
retw.n # [1]
.Lt_0_18946: # 0x5e
addi.n a14,a10,-1 # [0]
bnez a14,.Lt_0_36098 # [1]
addi.n a15,a13,-1 # [0]
bnez a15,.Lt_0_36098 # [1]
extui a8,a5,0,4 # [0]
bnez.n a8,.Lt_0_36098 # [1]
blti a6,4,.Lt_0_36098 # [0]
movi.n a9,64 # [0]
blt a9,a5,.LBB27_dspi_dotprod_off_s8_aes3 # [1]
.Lt_0_36610: # 0x75
.Lt_0_20994: # 0x75
mov.n a8,a1 # [0]
l8ui a9,a1,112 # [1] id:754 offset+0x0
l32i.n a15,a2,0 # [2] id:753
mull a10,a12,a13 # [3]
l32i a2,a1,68 # [4] gra_spill_temp_1
s32i a10,a1,64 # [5] gra_spill_temp_0
sext a9,a9,7 # [6]
movi.n a10,4 # [7]
# loop-count fixed at 4
loop a10,.LBB140_dspi_dotprod_off_s8_aes3 # [8]
.LBB135_dspi_dotprod_off_s8_aes3: # 0x8d
s8i a9,a8,0 # [0*II+0] id:755 temp_offset+0x0
s8i a9,a8,1 # [0*II+1] id:755 temp_offset+0x0
s8i a9,a8,2 # [0*II+2] id:755 temp_offset+0x0
s8i a9,a8,3 # [0*II+3] id:755 temp_offset+0x0
s8i a9,a8,4 # [0*II+4] id:755 temp_offset+0x0
s8i a9,a8,5 # [0*II+5] id:755 temp_offset+0x0
s8i a9,a8,6 # [0*II+6] id:755 temp_offset+0x0
s8i a9,a8,7 # [0*II+7] id:755 temp_offset+0x0
addi.n a8,a8,8 # [0*II+8]
.LBB140_dspi_dotprod_off_s8_aes3: # 0xa7
mov.n a3,a6 # [0]
addi a11,a5,-48 # [1]
addi.n a12,a1,8 # [3] temp_offset+8
movi.n a13,0 # [4]
wur.accx_0 a13 # [5]
wur.accx_1 a13 # [6]
ee.vld.128.ip q6,a12,0 # [7] id:756
s32i.n a12,a1,32 # [8] offset_data_ptr
beqz a11,.LBB34_dspi_dotprod_off_s8_aes3 # [9]
l32i a2,a1,68 # [0] gra_spill_temp_1
ee.vld.128.ip q0,a2,16 # [2] id:771
st.qr q0,a1,48 # [3] q0
.Lt_0_24578: # 0xc6
addi a14,a5,-32 # [0]
beqz a14,.LBB43_dspi_dotprod_off_s8_aes3 # [1]
.Lt_0_26626: # 0xcc
.Lt_0_26114: # 0xcc
addi a8,a5,-16 # [0]
beqz a8,.LBB50_dspi_dotprod_off_s8_aes3 # [1]
.Lt_0_28162: # 0xd2
.Lt_0_27650: # 0xd2
addi a9,a5,-64 # [0]
beqz a9,.LBB57_dspi_dotprod_off_s8_aes3 # [1]
.Lt_0_29698: # 0xd8
.Lt_0_29186: # 0xd8
addi a10,a5,-128 # [0]
beqz a10,.LBB64_dspi_dotprod_off_s8_aes3 # [1]
movi a11,128 # [0]
bge a11,a5,.Lt_0_32514 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a15,16 # [1] id:833
ee.ld.128.usar.ip q2,a15,16 # [2] id:834
ee.src.q.ld.ip q3,a15,16,q1,q2 # [4] id:835
beqz.n a3,.Lt_0_32514 # [5]
ld.qr q0,a1,48 # [0] q0
l32i a14,a1,64 # [1] gra_spill_temp_0
addi a13,a5,31 # [2]
movgez a13,a5,a5 # [3]
srai a13,a13,5 # [4]
sub a14,a14,a5 # [5]
addi a14,a14,16 # [6]
addi.n a13,a13,-1 # [7]
.Lt_0_33282: # 0x108
beqz.n a13,.Lt_0_33538 # [0]
loopnez a13,.LBB277_dspi_dotprod_off_s8_aes3 # [0]
.LBB275_dspi_dotprod_off_s8_aes3: # 0x10d
ee.vmulas.s8.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:836
ee.vmulas.s8.accx.ld.ip q1,a2,16,q1,q6 # [0*II+1] id:837
ee.vmulas.s8.accx.ld.ip.qup q1,a15,16,q1,q2,q3,q0 # [0*II+3] id:838
ee.vmulas.s8.accx.ld.ip q4,a2,16,q2,q6 # [0*II+4] id:839
ee.vmulas.s8.accx.ld.ip.qup q2,a15,16,q4,q3,q0,q1 # [0*II+6] id:840
ee.vmulas.s8.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:841
ee.vmulas.s8.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+9] id:842
ee.vmulas.s8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:843
.LBB277_dspi_dotprod_off_s8_aes3: # 0x12d
.Lt_0_33538: # 0x12d
ee.vmulas.s8.accx.ld.ip.qup q4,a15,16,q0,q1,q2,q3 # [0] id:844
ee.vmulas.s8.accx.ld.ip q1,a2,16,q1,q6 # [1] id:845
movi.n a8,32 # [2]
ee.vmulas.s8.accx.ld.xp.qup q0,a15,a14,q1,q2,q3,q4 # [3] id:846
ee.vmulas.s8.accx.ld.ip q7,a2,16,q2,q6 # [4] id:847
movi.n a9,-16 # [5]
ee.vmulas.s8.accx.ld.xp.qup q2,a15,a9,q7,q3,q4,q0 # [6] id:848
ee.vmulas.s8.accx.ld.ip q5,a2,16,q3,q6 # [7] id:850
ee.ld.128.usar.xp q1,a15,a8 # [8] id:849
addi.n a12,a12,1 # [9]
ee.vmulas.s8.accx.ld.ip.qup q3,a15,16,q5,q4,q1,q2 # [10] id:851
ee.vmulas.s8.accx.ld.ip q0,a2,16,q4,q6 # [11] id:852
bne a12,a3,.Lt_0_33282 # [12]
.Lt_0_32514: # 0x159
.Lt_0_32258: # 0x159
movi.n a2,0 # [0]
rur.accx_0 a10 # [1]
addi.n a12,a7,-1 # [2]
movi.n a11,1 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:854
retw.n # [10]
.Lt_0_36098: # 0x175
.Lt_0_20226: # 0x175
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB27_dspi_dotprod_off_s8_aes3: # 0x188
extui a14,a5,0,1 # [0]
beqz a14,.Lt_0_36610 # [1]
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB34_dspi_dotprod_off_s8_aes3: # 0x1a1
ee.ld.128.usar.ip q0,a15,16 # [0] id:760
ee.ld.128.usar.ip q2,a15,16 # [1] id:761
ee.src.q.ld.ip q3,a15,16,q0,q2 # [3] id:762
beqz.n a6,.Lt_0_24578 # [4]
movi.n a10,32 # [0]
l32i a12,a1,64 # [1] gra_spill_temp_0
movi.n a11,-16 # [2]
addi a12,a12,-32 # [3]
loopgtz a6,.LBB163_dspi_dotprod_off_s8_aes3 # [4]
.LBB161_dspi_dotprod_off_s8_aes3: # 0x1b9
ee.vmulas.s8.accx.ld.ip q1,a2,16,q0,q6 # [0*II+0] id:763
ee.vmulas.s8.accx.ld.xp.qup q1,a15,a12,q1,q0,q2,q3 # [0*II+2] id:764
ee.vmulas.s8.accx.ld.ip q0,a2,16,q2,q6 # [0*II+3] id:765
ee.vmulas.s8.accx.ld.xp.qup q2,a15,a11,q0,q2,q3,q1 # [0*II+5] id:766
ee.vmulas.s8.accx.ld.ip q1,a2,16,q3,q6 # [0*II+6] id:768
ee.ld.128.usar.xp q0,a15,a10 # [0*II+7] id:767
ee.vmulas.s8.accx.ld.ip.qup q3,a15,16,q1,q3,q0,q2 # [0*II+9] id:769
.LBB163_dspi_dotprod_off_s8_aes3: # 0x1d4
st.qr q1,a1,48 # [0] q0
j .Lt_0_24578 # [1]
.LBB43_dspi_dotprod_off_s8_aes3: # 0x1da
srli a3,a6,1 # [0]
l32i a12,a1,64 # [1] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [2] id:772
ee.ld.128.usar.ip q2,a15,16 # [3] id:773
addi a12,a12,-16 # [5]
ee.src.q.ld.xp q3,a15,a12,q1,q2 # [6] id:774
beqz.n a3,.Lt_0_26626 # [7]
ld.qr q0,a1,48 # [0] q0
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
loopnez a3,.LBB186_dspi_dotprod_off_s8_aes3 # [3]
.LBB184_dspi_dotprod_off_s8_aes3: # 0x1f8
ee.vmulas.s8.accx.ld.xp.qup q0,a15,a11,q0,q1,q2,q3 # [0*II+0] id:775
ee.vmulas.s8.accx.ld.ip q3,a2,16,q1,q6 # [0*II+1] id:776
ee.ld.128.usar.xp q1,a15,a10 # [0*II+2] id:777
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a12,q3,q2,q1,q0 # [0*II+4] id:778
ee.vmulas.s8.accx.ld.ip q4,a2,16,q2,q6 # [0*II+5] id:779
ee.vmulas.s8.accx.ld.xp.qup q2,a15,a11,q4,q1,q0,q3 # [0*II+7] id:780
ee.vmulas.s8.accx.ld.ip q3,a2,16,q1,q6 # [0*II+8] id:781
ee.ld.128.usar.xp q1,a15,a10 # [0*II+9] id:782
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a12,q3,q0,q1,q2 # [0*II+11] id:783
ee.vmulas.s8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+12] id:784
.LBB186_dspi_dotprod_off_s8_aes3: # 0x21e
st.qr q0,a1,48 # [0] q0
j .Lt_0_26626 # [1]
.LBB50_dspi_dotprod_off_s8_aes3: # 0x224
srli a3,a3,2 # [0]
movi.n a13,-16 # [1]
l32i a11,a1,64 # [2] gra_spill_temp_0
addi a15,a15,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a15,a13 # [5] id:785
ee.ld.128.usar.xp q1,a15,a11 # [6] id:786
ee.src.q.ld.xp q3,a15,a13,q1,q2 # [8] id:787
ee.ld.128.usar.xp q2,a15,a11 # [9] id:788
beqz.n a3,.Lt_0_28162 # [10]
ld.qr q0,a1,48 # [0] q0
movi.n a10,-16 # [1]
loopnez a3,.LBB209_dspi_dotprod_off_s8_aes3 # [2]
.LBB207_dspi_dotprod_off_s8_aes3: # 0x248
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a10,q0,q1,q2,q3 # [0*II+0] id:789
ee.vmulas.s8.accx.ld.ip q0,a2,16,q1,q6 # [0*II+1] id:790
ee.ld.128.usar.xp q1,a15,a11 # [0*II+2] id:791
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a10,q0,q2,q1,q3 # [0*II+4] id:792
ee.vmulas.s8.accx.ld.ip q0,a2,16,q2,q6 # [0*II+5] id:793
ee.ld.128.usar.xp q4,a15,a11 # [0*II+6] id:794
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a10,q0,q1,q4,q3 # [0*II+8] id:795
ee.vmulas.s8.accx.ld.ip q0,a2,16,q1,q6 # [0*II+9] id:796
ee.ld.128.usar.xp q1,a15,a11 # [0*II+10] id:797
ee.vmulas.s8.accx.ld.xp.qup q3,a15,a10,q0,q4,q1,q3 # [0*II+12] id:798
ee.vmulas.s8.accx.ld.ip q0,a2,16,q4,q6 # [0*II+13] id:799
ee.ld.128.usar.xp q2,a15,a11 # [0*II+14] id:800
.LBB209_dspi_dotprod_off_s8_aes3: # 0x274
st.qr q0,a1,48 # [0] q0
j .Lt_0_28162 # [1]
.LBB57_dspi_dotprod_off_s8_aes3: # 0x27a
ee.ld.128.usar.ip q1,a15,16 # [0] id:801
ee.ld.128.usar.ip q2,a15,16 # [1] id:802
ee.src.q.ld.ip q3,a15,16,q1,q2 # [3] id:803
beqz.n a3,.Lt_0_29698 # [4]
ld.qr q0,a1,48 # [0] q0
movi.n a10,32 # [1]
l32i a12,a1,64 # [2] gra_spill_temp_0
movi.n a11,-16 # [3]
sub a12,a12,a5 # [4]
addi a12,a12,16 # [5]
loopnez a3,.LBB232_dspi_dotprod_off_s8_aes3 # [6]
.LBB230_dspi_dotprod_off_s8_aes3: # 0x298
ee.vmulas.s8.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:804
ee.vmulas.s8.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:805
ee.vmulas.s8.accx.ld.xp.qup q4,a15,a12,q4,q2,q3,q0 # [0*II+3] id:806
ee.vmulas.s8.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:807
ee.vmulas.s8.accx.ld.xp.qup q2,a15,a11,q1,q3,q0,q4 # [0*II+6] id:808
ee.vmulas.s8.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:809
ee.ld.128.usar.xp q1,a15,a10 # [0*II+8] id:810
ee.vmulas.s8.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+10] id:811
ee.vmulas.s8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+11] id:812
.LBB232_dspi_dotprod_off_s8_aes3: # 0x2bb
st.qr q0,a1,48 # [0] q0
j .Lt_0_29698 # [1]
.LBB64_dspi_dotprod_off_s8_aes3: # 0x2c1
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i a12,a1,64 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [3] id:813
ee.ld.128.usar.ip q2,a15,16 # [4] id:814
sub a12,a12,a5 # [6]
addi a12,a12,16 # [7]
ld.qr q0,a1,48 # [8] q0
ee.src.q.ld.ip q3,a15,16,q1,q2 # [9] id:815
mov.n a8,a15 # [10]
loopnez a3,.LBB254_dspi_dotprod_off_s8_aes3 # [11]
.LBB252_dspi_dotprod_off_s8_aes3: # 0x2df
ee.vmulas.s8.accx.ld.ip.qup q0,a8,16,q0,q1,q2,q3 # [0*II+0] id:816
ee.vmulas.s8.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:817
ee.vmulas.s8.accx.ld.ip.qup q4,a8,16,q4,q2,q3,q0 # [0*II+3] id:818
ee.vmulas.s8.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:819
ee.vmulas.s8.accx.ld.ip.qup q1,a8,16,q1,q3,q0,q4 # [0*II+6] id:820
ee.vmulas.s8.accx.ld.ip q5,a2,16,q3,q6 # [0*II+7] id:821
ee.vmulas.s8.accx.ld.ip.qup q5,a8,16,q5,q0,q4,q1 # [0*II+9] id:822
ee.vmulas.s8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:823
ee.vmulas.s8.accx.ld.ip.qup q0,a8,16,q0,q4,q1,q5 # [0*II+12] id:824
ee.vmulas.s8.accx.ld.ip q4,a2,16,q4,q6 # [0*II+13] id:825
ee.vmulas.s8.accx.ld.xp.qup q4,a8,a12,q4,q1,q5,q0 # [0*II+15] id:826
ee.vmulas.s8.accx.ld.ip q1,a2,16,q1,q6 # [0*II+16] id:827
ee.vmulas.s8.accx.ld.xp.qup q2,a8,a11,q1,q5,q0,q4 # [0*II+18] id:828
ee.vmulas.s8.accx.ld.ip q4,a2,16,q5,q6 # [0*II+19] id:829
ee.ld.128.usar.xp q1,a8,a10 # [0*II+20] id:830
ee.vmulas.s8.accx.ld.ip.qup q3,a8,16,q4,q0,q1,q2 # [0*II+22] id:831
ee.vmulas.s8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+23] id:832
.LBB254_dspi_dotprod_off_s8_aes3: # 0x322
movi.n a2,0 # [0]
movi.n a11,1 # [1]
addi.n a12,a7,-1 # [2]
rur.accx_0 a10 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:854
retw.n # [10]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,214
|
esp-idf/esp32-cam-webPage-faceDetect/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dsps_dotprod_s16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dsps_dotprod_s16_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dsps_dotprod_s16_arp4
.global dsps_dotprod_s16_ansi
.type dsps_dotprod_s16_arp4,@function
//esp_err_t dsps_dotprod_s16_arp4(const int16_t* src1, const int16_t* src2, int16_t* dest, int len, int8_t shift);
dsps_dotprod_s16_arp4:
// src1 - a0
// src2 - a1
// dest - a2
// len - a3
// shift - a4
andi a5, a3, 7
beqz a5, .dsps_dotprod_s16_arp4_body
j dsps_dotprod_s16_ansi
.dsps_dotprod_s16_arp4_body:
add sp,sp,-16
// Enable analigned data access
esp.movx.r.cfg t6
or t6, t6, 2
esp.movx.w.cfg t6
add t6, a4, -15
neg t6, t6 // t6 - real_shift
li t3, 0x7fff
srl t3, t3, a4
esp.zero.xacc
esp.movx.w.xacc.l t3
mv t3, a0
mv t4, a1
esp.vld.128.ip q0, t3, 16 //q0 - src1
srli t5, a3, 3 // t5 = len>>3
# esp.lp.setup 0, t5, .main_loop
# esp.vld.128.ip q1, t4, 16 // q1 - src1
# .main_loop: esp.vmulas.s16.xacc.ld.ip q0, t3, 16, q0, q1 // q0 - src2
.main_loop:
esp.vld.128.ip q1, t4, 16 // q1 - src1
esp.vmulas.s16.xacc.ld.ip q0, t3, 16, q0, q1 // q0 - src2
add t5, t5, -1
bgtz t5, .main_loop
esp.srs.s.xacc t5, t6 // shift accx register by final_shift amount (a6), save the lower 32bits to a15
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dsps_dotprod_s16_ae32_enabled
|
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