repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
212
| content
stringlengths 590
5.01M
|
|---|---|---|---|
genetel200/u-boot
| 1,257
|
arch/arm/cpu/armv7/smccc-call.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015, Linaro Limited
*/
#include <linux/linkage.h>
#include <asm/opcodes-sec.h>
#include <asm/opcodes-virt.h>
#ifdef CONFIG_EFI_LOADER
.section .text.efi_runtime
#endif
#define UNWIND(x...)
/*
* Wrap c macros in asm macros to delay expansion until after the
* SMCCC asm macro is expanded.
*/
.macro SMCCC_SMC
__SMC(0)
.endm
.macro SMCCC_HVC
__HVC(0)
.endm
.macro SMCCC instr
UNWIND( .fnstart)
mov r12, sp
push {r4-r7}
UNWIND( .save {r4-r7})
ldm r12, {r4-r7}
\instr
pop {r4-r7}
ldr r12, [sp, #(4 * 4)]
stm r12, {r0-r3}
bx lr
UNWIND( .fnend)
.endm
/*
* void smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
* unsigned long a3, unsigned long a4, unsigned long a5,
* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
* struct arm_smccc_quirk *quirk)
*/
ENTRY(__arm_smccc_smc)
SMCCC SMCCC_SMC
ENDPROC(__arm_smccc_smc)
/*
* void smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
* unsigned long a3, unsigned long a4, unsigned long a5,
* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
* struct arm_smccc_quirk *quirk)
*/
ENTRY(__arm_smccc_hvc)
SMCCC SMCCC_HVC
ENDPROC(__arm_smccc_hvc)
|
genetel200/u-boot
| 9,096
|
arch/arm/cpu/armv7/psci.S
|
/*
* Copyright (C) 2013,2014 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
#include <asm/psci.h>
.pushsection ._secure.text, "ax"
.arch_extension sec
.align 5
.globl _psci_vectors
_psci_vectors:
b default_psci_vector @ reset
b default_psci_vector @ undef
b _smc_psci @ smc
b default_psci_vector @ pabort
b default_psci_vector @ dabort
b default_psci_vector @ hyp
b default_psci_vector @ irq
b psci_fiq_enter @ fiq
ENTRY(psci_fiq_enter)
movs pc, lr
ENDPROC(psci_fiq_enter)
.weak psci_fiq_enter
ENTRY(default_psci_vector)
movs pc, lr
ENDPROC(default_psci_vector)
.weak default_psci_vector
ENTRY(psci_version)
ENTRY(psci_cpu_suspend)
ENTRY(psci_cpu_off)
ENTRY(psci_cpu_on)
ENTRY(psci_affinity_info)
ENTRY(psci_migrate)
ENTRY(psci_migrate_info_type)
ENTRY(psci_migrate_info_up_cpu)
ENTRY(psci_system_off)
ENTRY(psci_system_reset)
ENTRY(psci_features)
ENTRY(psci_cpu_freeze)
ENTRY(psci_cpu_default_suspend)
ENTRY(psci_node_hw_state)
ENTRY(psci_system_suspend)
ENTRY(psci_set_suspend_mode)
ENTRY(psi_stat_residency)
ENTRY(psci_stat_count)
mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
mov pc, lr
ENDPROC(psci_stat_count)
ENDPROC(psi_stat_residency)
ENDPROC(psci_set_suspend_mode)
ENDPROC(psci_system_suspend)
ENDPROC(psci_node_hw_state)
ENDPROC(psci_cpu_default_suspend)
ENDPROC(psci_cpu_freeze)
ENDPROC(psci_features)
ENDPROC(psci_system_reset)
ENDPROC(psci_system_off)
ENDPROC(psci_migrate_info_up_cpu)
ENDPROC(psci_migrate_info_type)
ENDPROC(psci_migrate)
ENDPROC(psci_affinity_info)
ENDPROC(psci_cpu_on)
ENDPROC(psci_cpu_off)
ENDPROC(psci_cpu_suspend)
ENDPROC(psci_version)
.weak psci_version
.weak psci_cpu_suspend
.weak psci_cpu_off
.weak psci_cpu_on
.weak psci_affinity_info
.weak psci_migrate
.weak psci_migrate_info_type
.weak psci_migrate_info_up_cpu
.weak psci_system_off
.weak psci_system_reset
.weak psci_features
.weak psci_cpu_freeze
.weak psci_cpu_default_suspend
.weak psci_node_hw_state
.weak psci_system_suspend
.weak psci_set_suspend_mode
.weak psi_stat_residency
.weak psci_stat_count
_psci_table:
.word ARM_PSCI_FN_CPU_SUSPEND
.word psci_cpu_suspend
.word ARM_PSCI_FN_CPU_OFF
.word psci_cpu_off
.word ARM_PSCI_FN_CPU_ON
.word psci_cpu_on
.word ARM_PSCI_FN_MIGRATE
.word psci_migrate
.word ARM_PSCI_0_2_FN_PSCI_VERSION
.word psci_version
.word ARM_PSCI_0_2_FN_CPU_SUSPEND
.word psci_cpu_suspend
.word ARM_PSCI_0_2_FN_CPU_OFF
.word psci_cpu_off
.word ARM_PSCI_0_2_FN_CPU_ON
.word psci_cpu_on
.word ARM_PSCI_0_2_FN_AFFINITY_INFO
.word psci_affinity_info
.word ARM_PSCI_0_2_FN_MIGRATE
.word psci_migrate
.word ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE
.word psci_migrate_info_type
.word ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU
.word psci_migrate_info_up_cpu
.word ARM_PSCI_0_2_FN_SYSTEM_OFF
.word psci_system_off
.word ARM_PSCI_0_2_FN_SYSTEM_RESET
.word psci_system_reset
.word ARM_PSCI_1_0_FN_PSCI_FEATURES
.word psci_features
.word ARM_PSCI_1_0_FN_CPU_FREEZE
.word psci_cpu_freeze
.word ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
.word psci_cpu_default_suspend
.word ARM_PSCI_1_0_FN_NODE_HW_STATE
.word psci_node_hw_state
.word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
.word psci_system_suspend
.word ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
.word psci_set_suspend_mode
.word ARM_PSCI_1_0_FN_STAT_RESIDENCY
.word psi_stat_residency
.word ARM_PSCI_1_0_FN_STAT_COUNT
.word psci_stat_count
.word 0
.word 0
_smc_psci:
push {r4-r7,lr}
@ Switch to secure
mrc p15, 0, r7, c1, c1, 0
bic r4, r7, #1
mcr p15, 0, r4, c1, c1, 0
isb
adr r4, _psci_table
1: ldr r5, [r4] @ Load PSCI function ID
ldr r6, [r4, #4] @ Load target PC
cmp r5, #0 @ If reach the end, bail out
moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid)
beq 2f
cmp r0, r5 @ If not matching, try next entry
addne r4, r4, #8
bne 1b
blx r6 @ Execute PSCI function
@ Switch back to non-secure
2: mcr p15, 0, r7, c1, c1, 0
pop {r4-r7, lr}
movs pc, lr @ Return to the kernel
@ Requires dense and single-cluster CPU ID space
ENTRY(psci_get_cpu_id)
mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
and r0, r0, #0xff /* return CPU ID in cluster */
bx lr
ENDPROC(psci_get_cpu_id)
.weak psci_get_cpu_id
/* Imported from Linux kernel */
ENTRY(psci_v7_flush_dcache_all)
stmfd sp!, {r4-r5, r7, r9-r11, lr}
dmb @ ensure ordering with previous memory accesses
mrc p15, 1, r0, c0, c0, 1 @ read clidr
ands r3, r0, #0x7000000 @ extract loc from clidr
mov r3, r3, lsr #23 @ left align loc bit field
beq finished @ if loc is 0, then no need to clean
mov r10, #0 @ start clean at cache level 0
flush_levels:
add r2, r10, r10, lsr #1 @ work out 3x current cache level
mov r1, r0, lsr r2 @ extract cache type bits from clidr
and r1, r1, #7 @ mask of the bits for current cache only
cmp r1, #2 @ see what cache we have at this level
blt skip @ skip if no cache, or just i-cache
mrs r9, cpsr @ make cssr&csidr read atomic
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
isb @ isb to sych the new cssr&csidr
mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
msr cpsr_c, r9
and r2, r1, #7 @ extract the length of the cache lines
add r2, r2, #4 @ add 4 (line length offset)
ldr r4, =0x3ff
ands r4, r4, r1, lsr #3 @ find maximum number on the way size
clz r5, r4 @ find bit position of way size increment
ldr r7, =0x7fff
ands r7, r7, r1, lsr #13 @ extract max number of the index size
loop1:
mov r9, r7 @ create working copy of max index
loop2:
orr r11, r10, r4, lsl r5 @ factor way and cache number into r11
orr r11, r11, r9, lsl r2 @ factor index number into r11
mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
subs r9, r9, #1 @ decrement the index
bge loop2
subs r4, r4, #1 @ decrement the way
bge loop1
skip:
add r10, r10, #2 @ increment cache number
cmp r3, r10
bgt flush_levels
finished:
mov r10, #0 @ swith back to cache level 0
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
dsb st
isb
ldmfd sp!, {r4-r5, r7, r9-r11, lr}
bx lr
ENDPROC(psci_v7_flush_dcache_all)
ENTRY(psci_disable_smp)
mrc p15, 0, r0, c1, c0, 1 @ ACTLR
bic r0, r0, #(1 << 6) @ Clear SMP bit
mcr p15, 0, r0, c1, c0, 1 @ ACTLR
isb
dsb
bx lr
ENDPROC(psci_disable_smp)
.weak psci_disable_smp
ENTRY(psci_enable_smp)
mrc p15, 0, r0, c1, c0, 1 @ ACTLR
orr r0, r0, #(1 << 6) @ Set SMP bit
mcr p15, 0, r0, c1, c0, 1 @ ACTLR
isb
bx lr
ENDPROC(psci_enable_smp)
.weak psci_enable_smp
ENTRY(psci_cpu_off_common)
push {lr}
bl psci_v7_flush_dcache_all
clrex @ Why???
mrc p15, 0, r0, c1, c0, 0 @ SCTLR
bic r0, r0, #(1 << 2) @ Clear C bit
mcr p15, 0, r0, c1, c0, 0 @ SCTLR
isb
dsb
bl psci_v7_flush_dcache_all
clrex @ Why???
bl psci_disable_smp
pop {lr}
bx lr
ENDPROC(psci_cpu_off_common)
@ The stacks are allocated in reverse order, i.e.
@ the stack for CPU0 has the highest memory address.
@
@ -------------------- __secure_stack_end
@ | CPU0 target PC |
@ |------------------|
@ | |
@ | CPU0 stack |
@ | |
@ |------------------| __secure_stack_end - 1KB
@ | . |
@ | . |
@ | . |
@ | . |
@ -------------------- __secure_stack_start
@
@ This expects CPU ID in r0 and returns stack top in r0
LENTRY(psci_get_cpu_stack_top)
@ stack top = __secure_stack_end - (cpuid << ARM_PSCI_STACK_SHIFT)
ldr r3, =__secure_stack_end
sub r0, r3, r0, LSL #ARM_PSCI_STACK_SHIFT
sub r0, r0, #4 @ Save space for target PC
bx lr
ENDPROC(psci_get_cpu_stack_top)
@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in
@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across
@ this function.
ENTRY(psci_stack_setup)
mov r6, lr
mov r7, r0
bl psci_get_cpu_id @ CPU ID => r0
bl psci_get_cpu_stack_top @ stack top => r0
mov sp, r0
mov r0, r7
bx r6
ENDPROC(psci_stack_setup)
ENTRY(psci_arch_init)
mov pc, lr
ENDPROC(psci_arch_init)
.weak psci_arch_init
ENTRY(psci_arch_cpu_entry)
mov pc, lr
ENDPROC(psci_arch_cpu_entry)
.weak psci_arch_cpu_entry
ENTRY(psci_cpu_entry)
bl psci_enable_smp
bl _nonsec_init
bl psci_stack_setup
bl psci_arch_cpu_entry
bl psci_get_cpu_id @ CPU ID => r0
mov r2, r0 @ CPU ID => r2
bl psci_get_context_id @ context id => r0
mov r1, r0 @ context id => r1
mov r0, r2 @ CPU ID => r0
bl psci_get_target_pc @ target PC => r0
b _do_nonsec_entry
ENDPROC(psci_cpu_entry)
.popsection
|
genetel200/u-boot
| 2,808
|
arch/arm/cpu/arm926ejs/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Texas Instruments
*
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
*/
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
bx lr
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
/*
* flush D cache before disabling it
*/
mov r0, #0
flush_dcache:
mrc p15, 0, r15, c7, c10, 3
bne flush_dcache
mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
/*
* disable MMU and D cache
* enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
#else
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
#ifndef CONFIG_SYS_ICACHE_OFF
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Go setup Memory and board specific bits prior to relocation.
*/
mov r4, lr /* perserve link reg across call */
bl lowlevel_init /* go setup pll,mux,memory */
mov lr, r4 /* restore link */
#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
genetel200/u-boot
| 2,525
|
arch/arm/cpu/sa1100/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for SA1100 CPU
*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
*/
#include <asm-offsets.h>
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
/* Interrupt-Controller base address */
IC_BASE: .word 0x90050000
#define ICMR 0x04
/* Reset-Controller */
RST_BASE: .word 0x90030000
#define RSRR 0x00
#define RCSR 0x04
/* PWR */
PWR_BASE: .word 0x90020000
#define PSPR 0x08
#define PPCR 0x14
cpuspeed: .word CONFIG_SYS_CPUSPEED
cpu_init_crit:
/*
* mask all IRQs
*/
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
/* set clock speed */
ldr r0, PWR_BASE
ldr r1, cpuspeed
str r1, [r0, #PPCR]
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
* find a lowlevel_init.S in your board directory.
*/
mov ip, lr
bl lowlevel_init
mov lr, ip
#endif
/*
* disable MMU stuff and enable I-cache
*/
mrc p15,0,r0,c1,c0
bic r0, r0, #0x00002000 @ clear bit 13 (X)
bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
orr r0, r0, #0x00000002 @ set bit 1 (A) Align
mcr p15,0,r0,c1,c0
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
mov pc, lr
|
genetel200/u-boot
| 10,486
|
arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Low-level initialization for EP93xx
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
* Copyright (C) 2013
* Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
*
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
* Copyright (C) 2006 Cirrus Logic Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#include <config.h>
#include <asm/arch-ep93xx/ep93xx.h>
/*
/* Configure the SDRAM based on the supplied settings.
*
* Input: r0 - SDRAM DEVCFG register
* r2 - configuration for SDRAM chips
* Output: none
* Modifies: r3, r4
*/
ep93xx_sdram_config:
/* Program the SDRAM device configuration register. */
ldr r3, =SDRAM_BASE
#ifdef CONFIG_EDB93XX_SDCS0
str r0, [r3, #SDRAM_OFF_DEVCFG0]
#endif
#ifdef CONFIG_EDB93XX_SDCS1
str r0, [r3, #SDRAM_OFF_DEVCFG1]
#endif
#ifdef CONFIG_EDB93XX_SDCS2
str r0, [r3, #SDRAM_OFF_DEVCFG2]
#endif
#ifdef CONFIG_EDB93XX_SDCS3
str r0, [r3, #SDRAM_OFF_DEVCFG3]
#endif
/* Set the Initialize and MRS bits (issue continuous NOP commands
* (INIT & MRS set))
*/
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Delay for 200us. */
mov r4, #0x3000
delay1:
subs r4, r4, #1
bne delay1
/* Clear the MRS bit to issue a precharge all. */
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Temporarily set the refresh timer to 0x10. Make it really low so
* that refresh cycles are generated.
*/
ldr r4, =0x10
str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
/* Delay for at least 80 SDRAM clock cycles. */
mov r4, #80
delay2:
subs r4, r4, #1
bne delay2
/* Set the refresh timer to the fastest required for any device
* that might be used. Set 9.6 ms refresh time.
*/
ldr r4, =0x01e0
str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
/* Select mode register update mode. */
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Program the mode register on the SDRAM by performing fake read */
ldr r4, [r2]
/* Select normal operating mode. */
ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Return to the caller. */
mov pc, lr
/*
* Test to see if the SDRAM has been configured in a usable mode.
*
* Input: r0 - Test address of SDRAM
* Output: r0 - 0 -- Test OK, -1 -- Failed
* Modifies: r0-r5
*/
ep93xx_sdram_test:
/* Load the test patterns to be written to SDRAM. */
ldr r1, =0xf00dface
ldr r2, =0xdeadbeef
ldr r3, =0x08675309
ldr r4, =0xdeafc0ed
/* Store the test patterns to SDRAM. */
stmia r0, {r1-r4}
/* Load the test patterns from SDRAM one at a time and compare them
* to the actual pattern.
*/
ldr r5, [r0]
cmp r5, r1
ldreq r5, [r0, #0x0004]
cmpeq r5, r2
ldreq r5, [r0, #0x0008]
cmpeq r5, r3
ldreq r5, [r0, #0x000c]
cmpeq r5, r4
/* Return -1 if a mismatch was encountered, 0 otherwise. */
mvnne r0, #0xffffffff
moveq r0, #0x00000000
/* Return to the caller. */
mov pc, lr
/*
* Determine the size of the SDRAM. Use data=address for the scan.
*
* Input: r0 - Start SDRAM address
* Return: r0 - Single block size
* r1 - Valid block mask
* r2 - Total block count
* Modifies: r0-r5
*/
ep93xx_sdram_size:
/* Store zero at offset zero. */
str r0, [r0]
/* Start checking for an alias at 1MB into SDRAM. */
ldr r1, =0x00100000
/* Store the offset at the current offset. */
check_block_size:
str r1, [r0, r1]
/* Read back from zero. */
ldr r2, [r0]
/* Stop searching of an alias was found. */
cmp r1, r2
beq found_block_size
/* Advance to the next power of two boundary. */
mov r1, r1, lsl #1
/* Loop back if the size has not reached 256MB. */
cmp r1, #0x10000000
bne check_block_size
/* A full 256MB of memory was found, so return it now. */
ldr r0, =0x10000000
ldr r1, =0x00000000
ldr r2, =0x00000001
mov pc, lr
/* An alias was found. See if the first block is 128MB in size. */
found_block_size:
cmp r1, #0x08000000
/* The first block is 128MB, so there is no further memory. Return it
* now.
*/
ldreq r0, =0x08000000
ldreq r1, =0x00000000
ldreq r2, =0x00000001
moveq pc, lr
/* Save the block size, set the block address bits to zero, and
* initialize the block count to one.
*/
mov r3, r1
ldr r4, =0x00000000
ldr r5, =0x00000001
/* Look for additional blocks of memory by searching for non-aliases. */
find_blocks:
/* Store zero back to address zero. It may be overwritten. */
str r0, [r0]
/* Advance to the next power of two boundary. */
mov r1, r1, lsl #1
/* Store the offset at the current offset. */
str r1, [r0, r1]
/* Read back from zero. */
ldr r2, [r0]
/* See if a non-alias was found. */
cmp r1, r2
/* If a non-alias was found, then or in the block address bit and
* multiply the block count by two (since there are two unique
* blocks, one with this bit zero and one with it one).
*/
orrne r4, r4, r1
movne r5, r5, lsl #1
/* Continue searching if there are more address bits to check. */
cmp r1, #0x08000000
bne find_blocks
/* Return the block size, address mask, and count. */
mov r0, r3
mov r1, r4
mov r2, r5
/* Return to the caller. */
mov pc, lr
.globl lowlevel_init
lowlevel_init:
mov r6, lr
/* Make sure caches are off and invalidated. */
ldr r0, =0x00000000
mcr p15, 0, r0, c1, c0, 0
nop
nop
nop
nop
nop
/* Turn off the green LED and turn on the red LED. If the red LED
* is left on for too long, the external reset circuit described
* by application note AN258 will cause the system to reset.
*/
ldr r1, =EP93XX_LED_DATA
ldr r0, [r1]
bic r0, r0, #EP93XX_LED_GREEN_ON
orr r0, r0, #EP93XX_LED_RED_ON
str r0, [r1]
/* Undo the silly static memory controller programming performed
* by the boot rom.
*/
ldr r0, =SMC_BASE
/* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
ldr r1, =0x0000fbe0
/* Reset EP93XX_OFF_SMCBCR0 */
ldr r2, [r0]
orr r2, r2, r1
str r2, [r0]
ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR1]
ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR2]
ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR3]
ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR6]
ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR7]
/* Set the PLL1 and processor clock. */
ldr r0, =SYSCON_BASE
#ifdef CONFIG_EDB9301
/* 332MHz, giving a 166MHz processor clock. */
ldr r1, = 0x02b49907
#else
#ifdef CONFIG_EDB93XX_INDUSTRIAL
/* 384MHz, giving a 196MHz processor clock. */
ldr r1, =0x02a4bb38
#else
/* 400MHz, giving a 200MHz processor clock. */
ldr r1, =0x02a4e39e
#endif
#endif
str r1, [r0, #SYSCON_OFF_CLKSET1]
nop
nop
nop
nop
nop
/* Need to make sure that SDRAM is configured correctly before
* coping the code into it.
*/
#ifdef CONFIG_EDB93XX_SDCS0
mov r11, #SDRAM_DEVCFG0_BASE
#endif
#ifdef CONFIG_EDB93XX_SDCS1
mov r11, #SDRAM_DEVCFG1_BASE
#endif
#ifdef CONFIG_EDB93XX_SDCS2
mov r11, #SDRAM_DEVCFG2_BASE
#endif
#ifdef CONFIG_EDB93XX_SDCS3
ldr r0, =SYSCON_BASE
ldr r0, [r0, #SYSCON_OFF_SYSCFG]
ands r0, r0, #SYSCON_SYSCFG_LASDO
moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
movne r11, #SDRAM_DEVCFG3_ASD1_BASE
#endif
/* See Table 13-5 in EP93xx datasheet for more info about DRAM
* register mapping */
/* Try a 32-bit wide configuration of SDRAM. */
ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
/* Set burst count: 4 and CAS: 2
* Burst mode [A11:A10]; CAS [A16:A14]
*/
orr r2, r11, #0x00008800
bl ep93xx_sdram_config
/* Test the SDRAM. */
mov r0, r11
bl ep93xx_sdram_test
cmp r0, #0x00000000
beq ep93xx_sdram_done
/* Try a 16-bit wide configuration of SDRAM. */
ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
/* Set burst count: 8, CAS: 2, sequential burst
* Accoring to Table 13-3 for 16bit operations mapping must be shifted.
* Burst mode [A10:A9]; CAS [A15:A13]
*/
orr r2, r11, #0x00004600
bl ep93xx_sdram_config
/* Test the SDRAM. */
mov r0, r11
bl ep93xx_sdram_test
cmp r0, #0x00000000
beq ep93xx_sdram_done
/* Turn off the red LED. */
ldr r0, =EP93XX_LED_DATA
ldr r1, [r0]
bic r1, r1, #EP93XX_LED_RED_ON
str r1, [r0]
/* There is no SDRAM so flash the green LED. */
flash_green:
orr r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00010000
flash_green_delay_1:
subs r2, r2, #1
bne flash_green_delay_1
bic r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00010000
flash_green_delay_2:
subs r2, r2, #1
bne flash_green_delay_2
orr r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00010000
flash_green_delay_3:
subs r2, r2, #1
bne flash_green_delay_3
bic r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00050000
flash_green_delay_4:
subs r2, r2, #1
bne flash_green_delay_4
b flash_green
ep93xx_sdram_done:
ldr r1, =EP93XX_LED_DATA
ldr r0, [r1]
bic r0, r0, #EP93XX_LED_RED_ON
str r0, [r1]
/* Determine the size of the SDRAM. */
mov r0, r11
bl ep93xx_sdram_size
/* Save the SDRAM characteristics. */
mov r8, r0
mov r9, r1
mov r10, r2
/* Compute total memory size into r1 */
mul r1, r8, r10
#ifdef CONFIG_EDB93XX_SDCS0
ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
#endif
#ifdef CONFIG_EDB93XX_SDCS1
ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
#endif
#ifdef CONFIG_EDB93XX_SDCS2
ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
#endif
#ifdef CONFIG_EDB93XX_SDCS3
ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
#endif
/* Consider small DRAM size as:
* < 32Mb for 32bit bus
* < 64Mb for 16bit bus
*/
tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
moveq r1, r1, lsr #1
cmp r1, #0x02000000
#if defined(CONFIG_EDB9301)
/* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
movlt r1, #0x03f0
movge r1, #0x01e0
#else
/* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
movlt r1, #0x0600
movge r1, #0x2f0
#endif
str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
/* Save the memory configuration information. */
orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
stmia r0, {r8-r11}
mov lr, r6
mov pc, lr
|
genetel200/u-boot
| 12,413
|
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014-2015 Freescale Semiconductor
* Copyright 2019 NXP
*
* Extracted from armv8/start.S
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/macro.h>
#include <asm/arch-fsl-layerscape/soc.h>
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
#ifdef CONFIG_FSL_LSCH3
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#endif
#include <asm/u-boot.h>
/* Get GIC offset
* For LS1043a rev1.0, GIC base address align with 4k.
* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
* is set, GIC base address align with 4K, or else align
* with 64k.
* output:
* x0: the base address of GICD
* x1: the base address of GICC
*/
ENTRY(get_gic_offset)
ldr x0, =GICD_BASE
#ifdef CONFIG_GICV2
ldr x1, =GICC_BASE
#endif
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
ldr x2, =DCFG_CCSR_SVR
ldr w2, [x2]
rev w2, w2
lsr w3, w2, #16
ldr w4, =SVR_DEV(SVR_LS1043A)
cmp w3, w4
b.ne 1f
ands w2, w2, #0xff
cmp w2, #REV1_0
b.eq 1f
ldr x2, =SCFG_GIC400_ALIGN
ldr w2, [x2]
rev w2, w2
tbnz w2, #GIC_ADDR_BIT, 1f
ldr x0, =GICD_BASE_64K
#ifdef CONFIG_GICV2
ldr x1, =GICC_BASE_64K
#endif
1:
#endif
ret
ENDPROC(get_gic_offset)
ENTRY(smp_kick_all_cpus)
/* Kick secondary cpus up by SGI 0 interrupt */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
mov x29, lr /* Save LR */
bl get_gic_offset
bl gic_kick_secondary_cpus
mov lr, x29 /* Restore LR */
#endif
ret
ENDPROC(smp_kick_all_cpus)
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
/* unmask SError and abort */
msr daifclr, #4
/* Set HCR_EL2[AMO] so SError @EL2 is taken */
mrs x0, hcr_el2
orr x0, x0, #0x20 /* AMO */
msr hcr_el2, x0
isb
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
1:
#if defined (CONFIG_SYS_FSL_HAS_CCN504)
/* Set Wuo bit for RN-I 20 */
#ifdef CONFIG_ARCH_LS2080A
ldr x0, =CCI_AUX_CONTROL_BASE(20)
ldr x1, =0x00000010
bl ccn504_set_aux
/*
* Set forced-order mode in RNI-6, RNI-20
* This is required for performance optimization on LS2088A
* LS2080A family does not support setting forced-order mode,
* so skip this operation for LS2080A family
*/
bl get_svr
lsr w0, w0, #16
ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq 1f
ldr x0, =CCI_AUX_CONTROL_BASE(6)
ldr x1, =0x00000020
bl ccn504_set_aux
ldr x0, =CCI_AUX_CONTROL_BASE(20)
ldr x1, =0x00000020
bl ccn504_set_aux
1:
#endif
/* Add fully-coherent masters to DVM domain */
ldr x0, =CCI_MN_BASE
ldr x1, =CCI_MN_RNF_NODEID_LIST
ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
bl ccn504_add_masters_to_dvm
/* Set all RN-I ports to QoS of 15 */
ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
ldr x1, =0x00FF000C
bl ccn504_set_qos
ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
ldr x1, =0x00FF000C
bl ccn504_set_qos
#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef SMMU_BASE
/* Set the SMMU page size in the sACR register */
ldr x1, =SMMU_BASE
ldr w0, [x1, #0x10]
orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
str w0, [x1, #0x10]
#endif
/* Initialize GIC Secure Bank Status */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
bl get_gic_offset
bl gic_init_secure
1:
#ifdef CONFIG_GICV3
ldr x0, =GICR_BASE
bl gic_init_secure_percpu
#elif defined(CONFIG_GICV2)
bl get_gic_offset
bl gic_init_secure_percpu
#endif
#endif
100:
branch_if_master x0, x1, 2f
#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
ldr x0, =secondary_boot_func
blr x0
#endif
2:
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
1:
#ifdef CONFIG_FSL_TZPC_BP147
/* Set Non Secure access for all devices protected via TZPC */
ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
str w0, [x1]
isb
dsb sy
#endif
#ifdef CONFIG_FSL_TZASC_400
/*
* LS2080 and its personalities does not support TZASC
* So skip TZASC related operations
*/
bl get_svr
lsr w0, w0, #16
ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq 1f
/* Set TZASC so that:
* a. We use only Region0 whose global secure write/read is EN
* b. We use only Region0 whose NSAID write/read is EN
*
* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
* placeholders.
*/
.macro tzasc_prog, xreg
mov x12, TZASC1_BASE
mov x16, #0x10000
mul x14, \xreg, x16
add x14, x14,x12
mov x1, #0x8
add x1, x1, x14
ldr w0, [x1] /* Filter 0 Gate Keeper Register */
orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
str w0, [x1]
mov x1, #0x110
add x1, x1, x14
ldr w0, [x1] /* Region-0 Attributes Register */
orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
str w0, [x1]
mov x1, #0x114
add x1, x1, x14
ldr w0, [x1] /* Region-0 Access Register */
mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
str w0, [x1]
.endm
#ifdef CONFIG_FSL_TZASC_1
mov x13, #0
tzasc_prog x13
#endif
#ifdef CONFIG_FSL_TZASC_2
mov x13, #1
tzasc_prog x13
#endif
isb
dsb sy
#endif
100:
1:
#ifdef CONFIG_ARCH_LS1046A
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
1:
/* Initialize the L2 RAM latency */
mrs x1, S3_1_c11_c0_2
mov x0, #0x1C7
/* Clear L2 Tag RAM latency and L2 Data RAM latency */
bic x1, x1, x0
/* Set L2 data ram latency bits [2:0] */
orr x1, x1, #0x2
/* set L2 tag ram latency bits [8:6] */
orr x1, x1, #0x80
msr S3_1_c11_c0_2, x1
isb
100:
#endif
#if !defined(CONFIG_TFABOOT) && \
(defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD))
bl fsl_ocram_init
#endif
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
ENTRY(fsl_ocram_init)
mov x28, lr /* Save LR */
bl fsl_clear_ocram
bl fsl_ocram_clear_ecc_err
mov lr, x28 /* Restore LR */
ret
ENDPROC(fsl_ocram_init)
ENTRY(fsl_clear_ocram)
/* Clear OCRAM */
ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
mov x2, #0
clear_loop:
str x2, [x0]
add x0, x0, #8
cmp x0, x1
b.lo clear_loop
ret
ENDPROC(fsl_clear_ocram)
ENTRY(fsl_ocram_clear_ecc_err)
/* OCRAM1/2 ECC status bit */
mov w1, #0x60
ldr x0, =DCSR_DCFG_SBEESR2
str w1, [x0]
ldr x0, =DCSR_DCFG_MBEESR2
str w1, [x0]
ret
ENDPROC(fsl_ocram_init)
#endif
#ifdef CONFIG_FSL_LSCH3
.globl get_svr
get_svr:
ldr x1, =FSL_LSCH3_SVR
ldr w0, [x1]
ret
#endif
#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508)
hnf_pstate_poll:
/* x0 has the desired status, return only if operation succeed
* clobber x1, x2, x6
*/
mov x1, x0
mov w6, #8 /* HN-F node count */
mov x0, #0x18
movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
1:
ldr x2, [x0]
cmp x2, x1 /* check status */
b.eq 2f
b 1b
2:
add x0, x0, #0x10000 /* move to next node */
subs w6, w6, #1
cbnz w6, 1b
ret
hnf_set_pstate:
/* x0 has the desired state, clobber x1, x2, x6 */
mov x1, x0
/* power state to SFONLY */
mov w6, #8 /* HN-F node count */
mov x0, #0x10
movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
1: /* set pstate to sfonly */
ldr x2, [x0]
and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
orr x2, x2, x1
str x2, [x0]
add x0, x0, #0x10000 /* move to next node */
subs w6, w6, #1
cbnz w6, 1b
ret
ENTRY(__asm_flush_l3_dcache)
/*
* Return status in x0
* success 0
*/
mov x29, lr
dsb sy
mov x0, #0x1 /* HNFPSTAT_SFONLY */
bl hnf_set_pstate
mov x0, #0x4 /* SFONLY status */
bl hnf_pstate_poll
dsb sy
mov x0, #0x3 /* HNFPSTAT_FAM */
bl hnf_set_pstate
mov x0, #0xc /* FAM status */
bl hnf_pstate_poll
mov x0, #0
mov lr, x29
ret
ENDPROC(__asm_flush_l3_dcache)
#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */
.ltorg
/* Using 64 bit alignment since the spin table is accessed as data */
.align 4
.global secondary_boot_code
/* Secondary Boot Code starts here */
secondary_boot_code:
.global __spin_table
__spin_table:
.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
.align 2
ENTRY(secondary_boot_func)
/*
* MPIDR_EL1 Fields:
* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
* MPIDR[7:2] = AFF0_RES
* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
* MPIDR[23:16] = AFF2_CLUSTERID
* MPIDR[24] = MT
* MPIDR[29:25] = RES0
* MPIDR[30] = U
* MPIDR[31] = ME
* MPIDR[39:32] = AFF3
*
* Linear Processor ID (LPID) calculation from MPIDR_EL1:
* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
* until AFF2_CLUSTERID and AFF3 have non-zero values)
*
* LPID = MPIDR[15:8] | MPIDR[1:0]
*/
mrs x0, mpidr_el1
ubfm x1, x0, #8, #15
ubfm x2, x0, #0, #1
orr x10, x2, x1, lsl #2 /* x10 has LPID */
ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
/*
* offset of the spin table element for this core from start of spin
* table (each elem is padded to 64 bytes)
*/
lsl x1, x10, #6
ldr x0, =__spin_table
/* physical address of this cpus spin table element */
add x11, x1, x0
ldr x0, =__real_cntfrq
ldr x0, [x0]
msr cntfrq_el0, x0 /* set with real frequency */
str x9, [x11, #16] /* LPID */
mov x4, #1
str x4, [x11, #8] /* STATUS */
dsb sy
#if defined(CONFIG_GICV3)
gic_wait_for_interrupt_m x0
#elif defined(CONFIG_GICV2)
bl get_gic_offset
mov x0, x1
gic_wait_for_interrupt_m x0, w1
#endif
slave_cpu:
wfe
ldr x0, [x11]
cbz x0, slave_cpu
#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
mrs x1, sctlr_el2
#else
mrs x1, sctlr_el1
#endif
tbz x1, #25, cpu_is_le
rev x0, x0 /* BE to LE conversion */
cpu_is_le:
ldr x5, [x11, #24]
cbz x5, 1f
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
adr x4, secondary_switch_to_el1
ldr x5, =ES_TO_AARCH64
#else
ldr x4, [x11]
ldr x5, =ES_TO_AARCH32
#endif
bl secondary_switch_to_el2
1:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
adr x4, secondary_switch_to_el1
#else
ldr x4, [x11]
#endif
ldr x5, =ES_TO_AARCH64
bl secondary_switch_to_el2
ENDPROC(secondary_boot_func)
ENTRY(secondary_switch_to_el2)
switch_el x6, 1f, 0f, 0f
0: ret
1: armv8_switch_to_el2_m x4, x5, x6
ENDPROC(secondary_switch_to_el2)
ENTRY(secondary_switch_to_el1)
mrs x0, mpidr_el1
ubfm x1, x0, #8, #15
ubfm x2, x0, #0, #1
orr x10, x2, x1, lsl #2 /* x10 has LPID */
lsl x1, x10, #6
ldr x0, =__spin_table
/* physical address of this cpus spin table element */
add x11, x1, x0
ldr x4, [x11]
ldr x5, [x11, #24]
cbz x5, 2f
ldr x5, =ES_TO_AARCH32
bl switch_to_el1
2: ldr x5, =ES_TO_AARCH64
switch_to_el1:
switch_el x6, 0f, 1f, 0f
0: ret
1: armv8_switch_to_el1_m x4, x5, x6
ENDPROC(secondary_switch_to_el1)
/* Ensure that the literals used by the secondary boot code are
* assembled within it (this is required so that we can protect
* this area with a single memreserve region
*/
.ltorg
/* 64 bit alignment for elements accessed as data */
.align 4
.global __real_cntfrq
__real_cntfrq:
.quad COUNTER_FREQUENCY
.globl __secondary_boot_code_size
.type __secondary_boot_code_size, %object
/* Secondary Boot Code ends here */
__secondary_boot_code_size:
.quad .-secondary_boot_code
#endif
|
genetel200/u-boot
| 5,253
|
arch/arm/cpu/armv7/ls102xa/psci.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Author: Wang Dongsheng <dongsheng.wang@freescale.com>
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/armv7.h>
#include <asm/arch-armv7/generictimer.h>
#include <asm/psci.h>
#define RCPM_TWAITSR 0x04C
#define SCFG_CORE0_SFT_RST 0x130
#define SCFG_CORESRENCR 0x204
#define DCFG_CCSR_RSTCR 0x0B0
#define DCFG_CCSR_RSTCR_RESET_REQ 0x2
#define DCFG_CCSR_BRR 0x0E4
#define DCFG_CCSR_SCRATCHRW1 0x200
#define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0
#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
#define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
#define PSCI_FN_CPU_ON_FEATURE_MASK 0x0
#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
#define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK 0x0
.pushsection ._secure.text, "ax"
.arch_extension sec
.align 5
#define ONE_MS (COUNTER_FREQUENCY / 1000)
#define RESET_WAIT (30 * ONE_MS)
.globl psci_version
psci_version:
movw r0, #0
movt r0, #1
bx lr
_ls102x_psci_supported_table:
.word ARM_PSCI_0_2_FN_PSCI_VERSION
.word PSCI_FN_PSCI_VERSION_FEATURE_MASK
.word ARM_PSCI_0_2_FN_CPU_SUSPEND
.word PSCI_FN_CPU_SUSPEND_FEATURE_MASK
.word ARM_PSCI_0_2_FN_CPU_OFF
.word PSCI_FN_CPU_OFF_FEATURE_MASK
.word ARM_PSCI_0_2_FN_CPU_ON
.word PSCI_FN_CPU_ON_FEATURE_MASK
.word ARM_PSCI_0_2_FN_AFFINITY_INFO
.word PSCI_FN_AFFINITY_INFO_FEATURE_MASK
.word ARM_PSCI_0_2_FN_SYSTEM_OFF
.word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
.word ARM_PSCI_0_2_FN_SYSTEM_RESET
.word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
.word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
.word PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
.word 0
.word ARM_PSCI_RET_NI
.globl psci_features
psci_features:
adr r2, _ls102x_psci_supported_table
1: ldr r3, [r2]
cmp r3, #0
beq out_psci_features
cmp r1, r3
addne r2, r2, #8
bne 1b
out_psci_features:
ldr r0, [r2, #4]
bx lr
@ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
@ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
@ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
@ ARM_PSCI_RET_INVAL,suppose caller saves r4 before calling
LENTRY(psci_check_target_cpu_id)
@ Get the real CPU number
and r4, r1, #0xff
mov r0, #ARM_PSCI_RET_INVAL
@ Bit[31:24], bits must be zero.
tst r1, #0xff000000
bxne lr
@ Affinity level 2 - Cluster: only one cluster in LS1021xa.
tst r1, #0xff0000
bxne lr
@ Affinity level 1 - Processors: should be in 0xf00 format.
lsr r1, r1, #8
teq r1, #0xf
bxne lr
@ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
cmp r4, #2
bxge lr
mov r0, #ARM_PSCI_RET_SUCCESS
bx lr
ENDPROC(psci_check_target_cpu_id)
@ r1 = target CPU
@ r2 = target PC
.globl psci_cpu_on
psci_cpu_on:
push {r4, r5, r6, lr}
@ Clear and Get the correct CPU number
@ r1 = 0xf01
bl psci_check_target_cpu_id
cmp r0, #ARM_PSCI_RET_INVAL
beq out_psci_cpu_on
mov r0, r4
mov r1, r2
mov r2, r3
bl psci_save
mov r1, r4
@ Get DCFG base address
movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
@ Detect target CPU state
ldr r2, [r4, #DCFG_CCSR_BRR]
rev r2, r2
lsr r2, r2, r1
ands r2, r2, #1
beq holdoff_release
@ Reset target CPU
@ Get SCFG base address
movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
@ Enable CORE Soft Reset
movw r5, #0
movt r5, #(1 << 15)
rev r5, r5
str r5, [r0, #SCFG_CORESRENCR]
@ Get CPUx offset register
mov r6, #0x4
mul r6, r6, r1
add r2, r0, r6
@ Do reset on target CPU
movw r5, #0
movt r5, #(1 << 15)
rev r5, r5
str r5, [r2, #SCFG_CORE0_SFT_RST]
@ Wait target CPU up
timer_wait r2, RESET_WAIT
@ Disable CORE soft reset
mov r5, #0
str r5, [r0, #SCFG_CORESRENCR]
holdoff_release:
@ Release on target CPU
ldr r2, [r4, #DCFG_CCSR_BRR]
mov r6, #1
lsl r6, r6, r1 @ 32 bytes per CPU
rev r6, r6
orr r2, r2, r6
str r2, [r4, #DCFG_CCSR_BRR]
@ Set secondary boot entry
ldr r6, =psci_cpu_entry
rev r6, r6
str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
isb
dsb
@ Return
mov r0, #ARM_PSCI_RET_SUCCESS
out_psci_cpu_on:
pop {r4, r5, r6, lr}
bx lr
.globl psci_cpu_off
psci_cpu_off:
bl psci_cpu_off_common
1: wfi
b 1b
.globl psci_affinity_info
psci_affinity_info:
push {lr}
mov r0, #ARM_PSCI_RET_INVAL
@ Verify Affinity level
cmp r2, #0
bne out_affinity_info
bl psci_check_target_cpu_id
cmp r0, #ARM_PSCI_RET_INVAL
beq out_affinity_info
mov r1, r4
@ Get RCPM base address
movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
mov r0, #PSCI_AFFINITY_LEVEL_ON
@ Detect target CPU state
ldr r2, [r4, #RCPM_TWAITSR]
rev r2, r2
lsr r2, r2, r1
ands r2, r2, #1
beq out_affinity_info
mov r0, #PSCI_AFFINITY_LEVEL_OFF
out_affinity_info:
pop {pc}
.globl psci_system_reset
psci_system_reset:
@ Get DCFG base address
movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
rev r2, r2
str r2, [r1, #DCFG_CCSR_RSTCR]
1: wfi
b 1b
.globl psci_system_suspend
psci_system_suspend:
push {lr}
bl ls1_system_suspend
pop {pc}
.popsection
|
genetel200/u-boot
| 1,892
|
arch/arm/cpu/arm926ejs/mx27/relocate.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX27-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
/*
* The i.MX27 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM. Therefore, vectors cannot be changed at all.
*
* However, these ROM-based vectors actually just perform indirect
* calls through pointers located in RAM at SoC-specific addresses,
* as follows:
*
* Offset Exception Use by ROM code
* 0x00000000 reset indirect branch to [0x00000014]
* 0x00000004 undefined instruction indirect branch to [0xfffffef0]
* 0x00000008 software interrupt indirect branch to [0xfffffef4]
* 0x0000000c prefetch abort indirect branch to [0xfffffef8]
* 0x00000010 data abort indirect branch to [0xfffffefc]
* 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000
* 0x00000018 IRQ indirect branch to [0xffffff00]
* 0x0000001c FIQ indirect branch to [0xffffff04]
*
* In order to initialize exceptions on i.MX27, we must copy U-Boot's
* indirect (not exception!) vector table into 0xfffffef0..0xffffff04
* taking care not to copy vectors number 5 (reserved exception).
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
ldr r1, =32 /* size of vector table */
add r0, r0, r1 /* skip to indirect table */
ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */
ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */
stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */
bx lr
ENDPROC(relocate_vectors)
|
genetel200/u-boot
| 2,810
|
arch/arm/cpu/arm926ejs/mxs/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Texas Instruments
*
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Groger <mag@sysgo.de>
* Copyright (c) 2002 Alex Zupke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
*
* Change to support call back into iMX28 bootrom
* Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*/
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl reset
reset:
/*
* If the CPU is configured in "Wait JTAG connection mode", the stack
* pointer is not configured and is zero. This will cause crash when
* trying to push data onto stack right below here. Load the SP and make
* it point to the end of OCRAM if the SP is zero.
*/
cmp sp, #0x00000000
ldreq sp, =CONFIG_SYS_INIT_SP_ADDR
/*
* Store all registers on old stack pointer, this will allow us later to
* return to the BootROM and let the BootROM load U-Boot into RAM.
*
* WARNING: Register r0 and r1 are used by the BootROM to pass data
* to the called code. Register r0 will contain arbitrary
* data that are set in the BootStream. In case this code
* was started with CALL instruction, register r1 will contain
* pointer to the return value this function can then set.
* The code below MUST NOT CHANGE register r0 and r1 !
*/
push {r0-r12,r14}
/* Save control register c1 */
mrc p15, 0, r2, c1, c0, 0
push {r2}
/* Set the cpu to SVC32 mode and store old CPSR register content. */
mrs r2, cpsr
push {r2}
bic r2, r2, #0x1f
orr r2, r2, #0xd3
msr cpsr, r2
bl board_init_ll
/* Restore BootROM's CPU mode (especially FIQ). */
pop {r2}
msr cpsr,r2
/*
* Restore c1 register. Especially set exception vector location
* back to BootROM space which is required by bootrom for USB boot.
*/
pop {r2}
mcr p15, 0, r2, c1, c0, 0
pop {r0-r12,r14}
/*
* In case this code was started by the CALL instruction, the register
* r0 is examined by the BootROM after this code returns. The value in
* r0 must be set to 0 to indicate successful return.
*/
mov r0, #0
bx lr
|
genetel200/u-boot
| 1,963
|
arch/arm/cpu/arm926ejs/spear/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Texas Instruments
*
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
*/
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* Below are the critical initializations already taken place in BootROM.
* So, these are not taken care in Xloader
* 1. Relocation to RAM
* 2. Initializing stacks
*
*************************************************************************
*/
.globl reset
reset:
/*
* Xloader has to return back to BootROM in a few cases.
* eg. Ethernet boot, UART boot, USB boot
* Saving registers for returning back
*/
stmdb sp!, {r0-r12,r14}
bl cpu_init_crit
/*
* Clearing bss area is not done in Xloader.
* BSS area lies in the DDR location which is not yet initialized
* bss is assumed to be uninitialized.
*/
ldmia sp!, {r0-r12,pc}
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* enable instruction cache
*/
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
/*
* Go setup Memory and board specific bits prior to relocation.
*/
stmdb sp!, {lr}
bl _main /* _main will call board_init_f */
ldmia sp!, {pc}
|
genetel200/u-boot
| 2,744
|
arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2006
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*/
#include <config.h>
/*
* platform specific initializations are already done in Xloader
* Initializations already done include
* DDR, PLLs, IP's clock enable and reset release etc
*/
.globl lowlevel_init
lowlevel_init:
mov pc, lr
/* void setfreq(unsigned int device, unsigned int frequency) */
.global setfreq
setfreq:
stmfd sp!,{r14}
stmfd sp!,{r0-r12}
mov r8,sp
ldr sp,SRAM_STACK_V
/* Saving the function arguements for later use */
mov r4,r0
mov r5,r1
/* Putting DDR into self refresh */
ldr r0,DDR_07_V
ldr r1,[r0]
ldr r2,DDR_ACTIVE_V
bic r1, r1, r2
str r1,[r0]
ldr r0,DDR_57_V
ldr r1,[r0]
ldr r2,CYCLES_MASK_V
bic r1, r1, r2
ldr r2,REFRESH_CYCLES_V
orr r1, r1, r2, lsl #16
str r1,[r0]
ldr r0,DDR_07_V
ldr r1,[r0]
ldr r2,SREFRESH_MASK_V
orr r1, r1, r2
str r1,[r0]
/* flush pipeline */
b flush
.align 5
flush:
/* Delay to ensure self refresh mode */
ldr r0,SREFRESH_DELAY_V
delay:
sub r0,r0,#1
cmp r0,#0
bne delay
/* Putting system in slow mode */
ldr r0,SCCTRL_V
mov r1,#2
str r1,[r0]
/* Changing PLL(1/2) frequency */
mov r0,r4
mov r1,r5
cmp r4,#0
beq pll1_freq
/* Change PLL2 (DDR frequency) */
ldr r6,PLL2_FREQ_V
ldr r7,PLL2_CNTL_V
b pll2_freq
pll1_freq:
/* Change PLL1 (CPU frequency) */
ldr r6,PLL1_FREQ_V
ldr r7,PLL1_CNTL_V
pll2_freq:
mov r0,r6
ldr r1,[r0]
ldr r2,PLLFREQ_MASK_V
bic r1,r1,r2
mov r2,r5,lsr#1
orr r1,r1,r2,lsl#24
str r1,[r0]
mov r0,r7
ldr r1,P1C0A_V
str r1,[r0]
ldr r1,P1C0E_V
str r1,[r0]
ldr r1,P1C06_V
str r1,[r0]
ldr r1,P1C0E_V
str r1,[r0]
lock:
ldr r1,[r0]
and r1,r1,#1
cmp r1,#0
beq lock
/* Putting system back to normal mode */
ldr r0,SCCTRL_V
mov r1,#4
str r1,[r0]
/* Putting DDR back to normal */
ldr r0,DDR_07_V
ldr r1,[R0]
ldr r2,SREFRESH_MASK_V
bic r1, r1, r2
str r1,[r0]
ldr r2,DDR_ACTIVE_V
orr r1, r1, r2
str r1,[r0]
/* Delay to ensure self refresh mode */
ldr r0,SREFRESH_DELAY_V
1:
sub r0,r0,#1
cmp r0,#0
bne 1b
mov sp,r8
/* Resuming back to code */
ldmia sp!,{r0-r12}
ldmia sp!,{pc}
SCCTRL_V:
.word 0xfca00000
PLL1_FREQ_V:
.word 0xfca8000C
PLL1_CNTL_V:
.word 0xfca80008
PLL2_FREQ_V:
.word 0xfca80018
PLL2_CNTL_V:
.word 0xfca80014
PLLFREQ_MASK_V:
.word 0xff000000
P1C0A_V:
.word 0x1C0A
P1C0E_V:
.word 0x1C0E
P1C06_V:
.word 0x1C06
SREFRESH_DELAY_V:
.word 0x9999
SRAM_STACK_V:
.word 0xD2800600
DDR_07_V:
.word 0xfc60001c
DDR_ACTIVE_V:
.word 0x01000000
DDR_57_V:
.word 0xfc6000e4
CYCLES_MASK_V:
.word 0xffff0000
REFRESH_CYCLES_V:
.word 0xf0f0
SREFRESH_MASK_V:
.word 0x00010000
.global setfreq_sz
setfreq_sz:
.word setfreq_sz - setfreq
|
genetel200/u-boot
| 3,020
|
arch/arc/lib/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/arcregs.h>
ENTRY(_start)
/* Setup interrupt vector base that matches "__text_start" */
sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
; Disable/enable I-cache according to configuration
lr r5, [ARC_BCR_IC_BUILD]
breq r5, 0, 1f ; I$ doesn't exist
lr r5, [ARC_AUX_IC_CTRL]
#ifndef CONFIG_SYS_ICACHE_OFF
bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
#else
bset r5, r5, 0 ; I$ exists, but is not used
#endif
sr r5, [ARC_AUX_IC_CTRL]
mov r5, 1
sr r5, [ARC_AUX_IC_IVIC]
; As per ARC HS databook (see chapter 5.3.3.2)
; it is required to add 3 NOPs after each write to IC_IVIC.
nop
nop
nop
1:
; Disable/enable D-cache according to configuration
lr r5, [ARC_BCR_DC_BUILD]
breq r5, 0, 1f ; D$ doesn't exist
lr r5, [ARC_AUX_DC_CTRL]
bclr r5, r5, 6 ; Invalidate (discard w/o wback)
#ifndef CONFIG_SYS_DCACHE_OFF
bclr r5, r5, 0 ; Enable (+Inv)
#else
bset r5, r5, 0 ; Disable (+Inv)
#endif
sr r5, [ARC_AUX_DC_CTRL]
mov r5, 1
sr r5, [ARC_AUX_DC_IVDC]
1:
#ifdef CONFIG_ISA_ARCV2
; Disable System-Level Cache (SLC)
lr r5, [ARC_BCR_SLC]
breq r5, 0, 1f ; SLC doesn't exist
lr r5, [ARC_AUX_SLC_CTRL]
bclr r5, r5, 6 ; Invalidate (discard w/o wback)
bclr r5, r5, 0 ; Enable (+Inv)
sr r5, [ARC_AUX_SLC_CTRL]
1:
#endif
#ifdef __ARC_UNALIGNED__
/*
* Enable handling of unaligned access in the CPU as by default
* this HW feature is disabled while GCC starting from 8.1.0
* unconditionally uses it for ARC HS cores.
*/
flag 1 << STATUS_AD_BIT
#endif
/* Establish C runtime stack and frame */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %fp, %sp
/* Allocate reserved area from current top of stack */
mov %r0, %sp
bl board_init_f_alloc_reserve
/* Set stack below reserved area, adjust frame pointer accordingly */
mov %sp, %r0
mov %fp, %sp
/* Initialize reserved area - note: r0 already contains address */
bl board_init_f_init_reserve
#ifdef CONFIG_DEBUG_UART
/* Earliest point to set up early debug uart */
bl debug_uart_init
#endif
/* Zero the one and only argument of "board_init_f" */
mov_s %r0, 0
bl board_init_f
/* We only get here if relocation is disabled by GD_FLG_SKIP_RELOC */
/* Make sure we don't lose GD overwritten by zero new GD */
mov %r0, %r25
mov %r1, 0
bl board_init_r
ENDPROC(_start)
/*
* void board_init_f_r_trampoline(stack-pointer address)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r0 = new stack-pointer
*/
ENTRY(board_init_f_r_trampoline)
/* Set up the stack- and frame-pointers */
mov %sp, %r0
mov %fp, %sp
/* Update position of intterupt vector table */
lr %r0, [ARC_AUX_INTR_VEC_BASE]
ld %r1, [%r25, GD_RELOC_OFF]
add %r0, %r0, %r1
sr %r0, [ARC_AUX_INTR_VEC_BASE]
/* Re-enter U-Boot by calling board_init_f_r */
j board_init_f_r
ENDPROC(board_init_f_r_trampoline)
|
genetel200/u-boot
| 2,919
|
arch/arc/lib/ints_low.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
*/
#include <linux/linkage.h>
/*
* Note on the LD/ST addressing modes with address register write-back
*
* LD.a same as LD.aw
*
* LD.a reg1, [reg2, x] => Pre Incr
* Eff Addr for load = [reg2 + x]
*
* LD.ab reg1, [reg2, x] => Post Incr
* Eff Addr for load = [reg2]
*/
.macro PUSH reg
st.a \reg, [%sp, -4]
.endm
.macro PUSHAX aux
lr %r9, [\aux]
PUSH %r9
.endm
.macro SAVE_R1_TO_R24
PUSH %r1
PUSH %r2
PUSH %r3
PUSH %r4
PUSH %r5
PUSH %r6
PUSH %r7
PUSH %r8
PUSH %r9
PUSH %r10
PUSH %r11
PUSH %r12
PUSH %r13
PUSH %r14
PUSH %r15
PUSH %r16
PUSH %r17
PUSH %r18
PUSH %r19
PUSH %r20
PUSH %r21
PUSH %r22
PUSH %r23
PUSH %r24
.endm
.macro SAVE_ALL_SYS
/* saving %r0 to reg->r0 in advance since we read %ecr into it */
st %r0, [%sp, -8]
lr %r0, [%ecr] /* all stack addressing is manual so far */
st %r0, [%sp]
st %sp, [%sp, -4]
/* now move %sp to reg->r0 position so we can do "push" automatically */
sub %sp, %sp, 8
SAVE_R1_TO_R24
PUSH %r25
PUSH %gp
PUSH %fp
PUSH %blink
PUSHAX %eret
PUSHAX %erstatus
PUSH %lp_count
PUSHAX %lp_end
PUSHAX %lp_start
PUSHAX %erbta
.endm
.macro SAVE_EXCEPTION_SOURCE
#ifdef CONFIG_MMU
/* If MMU exists exception faulting address is loaded in EFA reg */
lr %r0, [%efa]
#else
/* Otherwise in ERET (exception return) reg */
lr %r0, [%eret]
#endif
.endm
ENTRY(memory_error)
SAVE_ALL_SYS
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_memory_error
ENDPROC(memory_error)
ENTRY(instruction_error)
SAVE_ALL_SYS
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_instruction_error
ENDPROC(instruction_error)
ENTRY(interrupt_handler)
/* Todo - save and restore CPU context when interrupts will be in use */
bl do_interrupt_handler
rtie
ENDPROC(interrupt_handler)
ENTRY(EV_MachineCheck)
SAVE_ALL_SYS
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_machine_check_fault
ENDPROC(EV_MachineCheck)
ENTRY(EV_TLBMissI)
SAVE_ALL_SYS
mov %r0, %sp
j do_itlb_miss
ENDPROC(EV_TLBMissI)
ENTRY(EV_TLBMissD)
SAVE_ALL_SYS
mov %r0, %sp
j do_dtlb_miss
ENDPROC(EV_TLBMissD)
ENTRY(EV_TLBProtV)
SAVE_ALL_SYS
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_tlb_prot_violation
ENDPROC(EV_TLBProtV)
ENTRY(EV_PrivilegeV)
SAVE_ALL_SYS
mov %r0, %sp
j do_privilege_violation
ENDPROC(EV_PrivilegeV)
ENTRY(EV_Trap)
SAVE_ALL_SYS
mov %r0, %sp
j do_trap
ENDPROC(EV_Trap)
ENTRY(EV_Extension)
SAVE_ALL_SYS
mov %r0, %sp
j do_extension
ENDPROC(EV_Extension)
#ifdef CONFIG_ISA_ARCV2
ENTRY(EV_SWI)
SAVE_ALL_SYS
mov %r0, %sp
j do_swi
ENDPROC(EV_SWI)
ENTRY(EV_DivZero)
SAVE_ALL_SYS
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_divzero
ENDPROC(EV_DivZero)
ENTRY(EV_DCError)
SAVE_ALL_SYS
mov %r0, %sp
j do_dcerror
ENDPROC(EV_DCError)
ENTRY(EV_Maligned)
SAVE_ALL_SYS
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_maligned
ENDPROC(EV_Maligned)
#endif
|
genetel200/u-boot
| 5,541
|
arch/arc/lib/_millicodethunk.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 1995, 1997, 2007-2013 Free Software Foundation, Inc.
*/
/* ANSI concatenation macros. */
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a ## b
/* Use the right prefix for global labels. */
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
#ifndef WORKING_ASSEMBLER
#define abs_l abs
#define asl_l asl
#define mov_l mov
#endif
#define FUNC(X) .type SYM(X),@function
#define HIDDEN_FUNC(X) FUNC(X)` .hidden X
#define ENDFUNC0(X) .Lfe_##X: .size X,.Lfe_##X-X
#define ENDFUNC(X) ENDFUNC0(X)
.section .text
.align 4
.global SYM(__st_r13_to_r15)
.global SYM(__st_r13_to_r16)
.global SYM(__st_r13_to_r17)
.global SYM(__st_r13_to_r18)
.global SYM(__st_r13_to_r19)
.global SYM(__st_r13_to_r20)
.global SYM(__st_r13_to_r21)
.global SYM(__st_r13_to_r22)
.global SYM(__st_r13_to_r23)
.global SYM(__st_r13_to_r24)
.global SYM(__st_r13_to_r25)
HIDDEN_FUNC(__st_r13_to_r15)
HIDDEN_FUNC(__st_r13_to_r16)
HIDDEN_FUNC(__st_r13_to_r17)
HIDDEN_FUNC(__st_r13_to_r18)
HIDDEN_FUNC(__st_r13_to_r19)
HIDDEN_FUNC(__st_r13_to_r20)
HIDDEN_FUNC(__st_r13_to_r21)
HIDDEN_FUNC(__st_r13_to_r22)
HIDDEN_FUNC(__st_r13_to_r23)
HIDDEN_FUNC(__st_r13_to_r24)
HIDDEN_FUNC(__st_r13_to_r25)
.align 4
SYM(__st_r13_to_r25):
st r25, [sp,48]
SYM(__st_r13_to_r24):
st r24, [sp,44]
SYM(__st_r13_to_r23):
st r23, [sp,40]
SYM(__st_r13_to_r22):
st r22, [sp,36]
SYM(__st_r13_to_r21):
st r21, [sp,32]
SYM(__st_r13_to_r20):
st r20, [sp,28]
SYM(__st_r13_to_r19):
st r19, [sp,24]
SYM(__st_r13_to_r18):
st r18, [sp,20]
SYM(__st_r13_to_r17):
st r17, [sp,16]
SYM(__st_r13_to_r16):
st r16, [sp,12]
SYM(__st_r13_to_r15):
#ifdef __ARC700__
st r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
#else
st_s r15, [sp,8]
#endif
st_s r14, [sp,4]
j_s.d [%blink]
st_s r13, [sp,0]
ENDFUNC(__st_r13_to_r15)
ENDFUNC(__st_r13_to_r16)
ENDFUNC(__st_r13_to_r17)
ENDFUNC(__st_r13_to_r18)
ENDFUNC(__st_r13_to_r19)
ENDFUNC(__st_r13_to_r20)
ENDFUNC(__st_r13_to_r21)
ENDFUNC(__st_r13_to_r22)
ENDFUNC(__st_r13_to_r23)
ENDFUNC(__st_r13_to_r24)
ENDFUNC(__st_r13_to_r25)
.section .text
.align 4
; ==================================
; the loads
.global SYM(__ld_r13_to_r15)
.global SYM(__ld_r13_to_r16)
.global SYM(__ld_r13_to_r17)
.global SYM(__ld_r13_to_r18)
.global SYM(__ld_r13_to_r19)
.global SYM(__ld_r13_to_r20)
.global SYM(__ld_r13_to_r21)
.global SYM(__ld_r13_to_r22)
.global SYM(__ld_r13_to_r23)
.global SYM(__ld_r13_to_r24)
.global SYM(__ld_r13_to_r25)
HIDDEN_FUNC(__ld_r13_to_r15)
HIDDEN_FUNC(__ld_r13_to_r16)
HIDDEN_FUNC(__ld_r13_to_r17)
HIDDEN_FUNC(__ld_r13_to_r18)
HIDDEN_FUNC(__ld_r13_to_r19)
HIDDEN_FUNC(__ld_r13_to_r20)
HIDDEN_FUNC(__ld_r13_to_r21)
HIDDEN_FUNC(__ld_r13_to_r22)
HIDDEN_FUNC(__ld_r13_to_r23)
HIDDEN_FUNC(__ld_r13_to_r24)
HIDDEN_FUNC(__ld_r13_to_r25)
SYM(__ld_r13_to_r25):
ld r25, [sp,48]
SYM(__ld_r13_to_r24):
ld r24, [sp,44]
SYM(__ld_r13_to_r23):
ld r23, [sp,40]
SYM(__ld_r13_to_r22):
ld r22, [sp,36]
SYM(__ld_r13_to_r21):
ld r21, [sp,32]
SYM(__ld_r13_to_r20):
ld r20, [sp,28]
SYM(__ld_r13_to_r19):
ld r19, [sp,24]
SYM(__ld_r13_to_r18):
ld r18, [sp,20]
SYM(__ld_r13_to_r17):
ld r17, [sp,16]
SYM(__ld_r13_to_r16):
ld r16, [sp,12]
SYM(__ld_r13_to_r15):
#ifdef __ARC700__
ld r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
#else
ld_s r15, [sp,8]
#endif
ld_s r14, [sp,4]
j_s.d [%blink]
ld_s r13, [sp,0]
ENDFUNC(__ld_r13_to_r15)
ENDFUNC(__ld_r13_to_r16)
ENDFUNC(__ld_r13_to_r17)
ENDFUNC(__ld_r13_to_r18)
ENDFUNC(__ld_r13_to_r19)
ENDFUNC(__ld_r13_to_r20)
ENDFUNC(__ld_r13_to_r21)
ENDFUNC(__ld_r13_to_r22)
ENDFUNC(__ld_r13_to_r23)
ENDFUNC(__ld_r13_to_r24)
ENDFUNC(__ld_r13_to_r25)
.global SYM(__ld_r13_to_r14_ret)
.global SYM(__ld_r13_to_r15_ret)
.global SYM(__ld_r13_to_r16_ret)
.global SYM(__ld_r13_to_r17_ret)
.global SYM(__ld_r13_to_r18_ret)
.global SYM(__ld_r13_to_r19_ret)
.global SYM(__ld_r13_to_r20_ret)
.global SYM(__ld_r13_to_r21_ret)
.global SYM(__ld_r13_to_r22_ret)
.global SYM(__ld_r13_to_r23_ret)
.global SYM(__ld_r13_to_r24_ret)
.global SYM(__ld_r13_to_r25_ret)
HIDDEN_FUNC(__ld_r13_to_r14_ret)
HIDDEN_FUNC(__ld_r13_to_r15_ret)
HIDDEN_FUNC(__ld_r13_to_r16_ret)
HIDDEN_FUNC(__ld_r13_to_r17_ret)
HIDDEN_FUNC(__ld_r13_to_r18_ret)
HIDDEN_FUNC(__ld_r13_to_r19_ret)
HIDDEN_FUNC(__ld_r13_to_r20_ret)
HIDDEN_FUNC(__ld_r13_to_r21_ret)
HIDDEN_FUNC(__ld_r13_to_r22_ret)
HIDDEN_FUNC(__ld_r13_to_r23_ret)
HIDDEN_FUNC(__ld_r13_to_r24_ret)
HIDDEN_FUNC(__ld_r13_to_r25_ret)
.section .text
.align 4
SYM(__ld_r13_to_r25_ret):
ld r25, [sp,48]
SYM(__ld_r13_to_r24_ret):
ld r24, [sp,44]
SYM(__ld_r13_to_r23_ret):
ld r23, [sp,40]
SYM(__ld_r13_to_r22_ret):
ld r22, [sp,36]
SYM(__ld_r13_to_r21_ret):
ld r21, [sp,32]
SYM(__ld_r13_to_r20_ret):
ld r20, [sp,28]
SYM(__ld_r13_to_r19_ret):
ld r19, [sp,24]
SYM(__ld_r13_to_r18_ret):
ld r18, [sp,20]
SYM(__ld_r13_to_r17_ret):
ld r17, [sp,16]
SYM(__ld_r13_to_r16_ret):
ld r16, [sp,12]
SYM(__ld_r13_to_r15_ret):
ld r15, [sp,8]
SYM(__ld_r13_to_r14_ret):
ld blink,[sp,r12]
ld_s r14, [sp,4]
ld.ab r13, [sp,r12]
j_s.d [%blink]
add_s sp,sp,4
ENDFUNC(__ld_r13_to_r14_ret)
ENDFUNC(__ld_r13_to_r15_ret)
ENDFUNC(__ld_r13_to_r16_ret)
ENDFUNC(__ld_r13_to_r17_ret)
ENDFUNC(__ld_r13_to_r18_ret)
ENDFUNC(__ld_r13_to_r19_ret)
ENDFUNC(__ld_r13_to_r20_ret)
ENDFUNC(__ld_r13_to_r21_ret)
ENDFUNC(__ld_r13_to_r22_ret)
ENDFUNC(__ld_r13_to_r23_ret)
ENDFUNC(__ld_r13_to_r24_ret)
ENDFUNC(__ld_r13_to_r25_ret)
|
genetel200/u-boot
| 1,067
|
arch/arc/cpu/arcv2/ivt.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
*/
.section .ivt, "a",@progbits
.align 4
/* Critical system events */
.word _start /* 0x00 - Reset */
.word memory_error /* 0x01 - Memory Error */
.word instruction_error /* 0x02 - Instruction Error */
/* Exceptions */
.word EV_MachineCheck /* 0x03 - Fatal Machine check */
.word EV_TLBMissI /* 0x04 - Intruction TLB miss */
.word EV_TLBMissD /* 0x05 - Data TLB miss */
.word EV_TLBProtV /* 0x06 - Protection Violation or Misaligned Access */
.word EV_PrivilegeV /* 0x07 - Privilege Violation */
.word EV_SWI /* 0x08 - Software Interrupt */
.word EV_Trap /* 0x09 - Trap */
.word EV_Extension /* 0x0A - Extension Intruction Exception */
.word EV_DivZero /* 0x0B - Division by Zero */
.word EV_DCError /* 0x0C - Data cache consistency error */
.word EV_Maligned /* 0x0D - Misaligned data access */
.word 0 /* 0x0E - Unused */
.word 0 /* 0x0F - Unused */
/* Device interrupts */
.rept 240
.word interrupt_handler /* 0x10 - 0xFF */
.endr
|
genetel200/u-boot
| 6,657
|
arch/x86/lib/bios_asm.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* From coreboot x86_asm.S, cleaned up substantially
*
* Copyright (C) 2009-2010 coresystems GmbH
*/
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include "bios.h"
#define SEG(segment) $segment * X86_GDT_ENTRY_SIZE
/*
* This is the interrupt handler stub code. It gets copied to the IDT and
* to some fixed addresses in the F segment. Before the code can used,
* it gets patched up by the C function copying it: byte 3 (the $0 in
* movb $0, %al) is overwritten with the interrupt numbers.
*/
.code16
.globl __idt_handler
__idt_handler:
pushal
movb $0, %al /* This instruction gets modified */
ljmp $0, $__interrupt_handler_16bit
.globl __idt_handler_size
__idt_handler_size:
.long . - __idt_handler
.macro setup_registers
/* initial register values */
movl 44(%ebp), %eax
movl %eax, __registers + 0 /* eax */
movl 48(%ebp), %eax
movl %eax, __registers + 4 /* ebx */
movl 52(%ebp), %eax
movl %eax, __registers + 8 /* ecx */
movl 56(%ebp), %eax
movl %eax, __registers + 12 /* edx */
movl 60(%ebp), %eax
movl %eax, __registers + 16 /* esi */
movl 64(%ebp), %eax
movl %eax, __registers + 20 /* edi */
.endm
.macro enter_real_mode
/* Activate the right segment descriptor real mode. */
ljmp SEG(X86_GDT_ENTRY_16BIT_CS), $PTR_TO_REAL_MODE(1f)
1:
.code16
/*
* Load the segment registers with properly configured segment
* descriptors. They will retain these configurations (limits,
* writability, etc.) once protected mode is turned off.
*/
mov SEG(X86_GDT_ENTRY_16BIT_DS), %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %fs
mov %ax, %gs
mov %ax, %ss
/* Turn off protection */
movl %cr0, %eax
andl $~X86_CR0_PE, %eax
movl %eax, %cr0
/* Now really going into real mode */
ljmp $0, $PTR_TO_REAL_MODE(1f)
1:
/*
* Set up a stack: Put the stack at the end of page zero. That way
* we can easily share it between real and protected, since the
* 16-bit ESP at segment 0 will work for any case.
*/
mov $0x0, %ax
mov %ax, %ss
/* Load 16 bit IDT */
xor %ax, %ax
mov %ax, %ds
lidt __realmode_idt
.endm
.macro prepare_for_irom
movl $0x1000, %eax
movl %eax, %esp
/* Initialise registers for option rom lcall */
movl __registers + 0, %eax
movl __registers + 4, %ebx
movl __registers + 8, %ecx
movl __registers + 12, %edx
movl __registers + 16, %esi
movl __registers + 20, %edi
/* Set all segments to 0x0000, ds to 0x0040 */
push %ax
xor %ax, %ax
mov %ax, %es
mov %ax, %fs
mov %ax, %gs
mov SEG(X86_GDT_ENTRY_16BIT_FLAT_DS), %ax
mov %ax, %ds
pop %ax
.endm
.macro enter_protected_mode
/* Go back to protected mode */
movl %cr0, %eax
orl $X86_CR0_PE, %eax
movl %eax, %cr0
/* Now that we are in protected mode jump to a 32 bit code segment */
data32 ljmp SEG(X86_GDT_ENTRY_32BIT_CS), $PTR_TO_REAL_MODE(1f)
1:
.code32
mov SEG(X86_GDT_ENTRY_32BIT_DS), %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %gs
mov %ax, %ss
mov SEG(X86_GDT_ENTRY_32BIT_FS), %ax
mov %ax, %fs
/* restore proper idt */
lidt idt_ptr
.endm
/*
* In order to be independent of U-Boot's position in RAM we relocate a part
* of the code to the first megabyte of RAM, so the CPU can use it in
* real-mode. This code lives at asm_realmode_code.
*/
.globl asm_realmode_code
asm_realmode_code:
/* Realmode IDT pointer structure. */
__realmode_idt = PTR_TO_REAL_MODE(.)
.word 1023 /* 16 bit limit */
.long 0 /* 24 bit base */
.word 0
/* Preserve old stack */
__stack = PTR_TO_REAL_MODE(.)
.long 0
/* Register store for realmode_call and realmode_interrupt */
__registers = PTR_TO_REAL_MODE(.)
.long 0 /* 0 - EAX */
.long 0 /* 4 - EBX */
.long 0 /* 8 - ECX */
.long 0 /* 12 - EDX */
.long 0 /* 16 - ESI */
.long 0 /* 20 - EDI */
/* 256 byte buffer, used by int10 */
.globl asm_realmode_buffer
asm_realmode_buffer:
.skip 256
.code32
.globl asm_realmode_call
asm_realmode_call:
/* save all registers to the stack */
pusha
pushf
movl %esp, __stack
movl %esp, %ebp
/*
* This function is called with regparm=0 and we have to skip the
* 36 bytes from pushf+pusha. Hence start at 40.
* Set up our call instruction.
*/
movl 40(%ebp), %eax
mov %ax, __lcall_instr + 1
andl $0xffff0000, %eax
shrl $4, %eax
mov %ax, __lcall_instr + 3
wbinvd
setup_registers
enter_real_mode
prepare_for_irom
__lcall_instr = PTR_TO_REAL_MODE(.)
.byte 0x9a
.word 0x0000, 0x0000
enter_protected_mode
/* restore stack pointer, eflags and register values and exit */
movl __stack, %esp
popf
popa
ret
.globl __realmode_interrupt
__realmode_interrupt:
/* save all registers to the stack and store the stack pointer */
pusha
pushf
movl %esp, __stack
movl %esp, %ebp
/*
* This function is called with regparm=0 and we have to skip the
* 36 bytes from pushf+pusha. Hence start at 40.
* Prepare interrupt calling code.
*/
movl 40(%ebp), %eax
movb %al, __intXX_instr + 1 /* intno */
setup_registers
enter_real_mode
prepare_for_irom
__intXX_instr = PTR_TO_REAL_MODE(.)
.byte 0xcd, 0x00 /* This becomes intXX */
enter_protected_mode
/* restore stack pointer, eflags and register values and exit */
movl __stack, %esp
popf
popa
ret
/*
* This is the 16-bit interrupt entry point called by the IDT stub code.
*
* Before this code code is called, %eax is pushed to the stack, and the
* interrupt number is loaded into %al. On return this function cleans up
* for its caller.
*/
.code16
__interrupt_handler_16bit = PTR_TO_REAL_MODE(.)
push %ds
push %es
push %fs
push %gs
/* Save real mode SS */
movw %ss, %cs:__realmode_ss
/* Clear DF to not break ABI assumptions */
cld
/*
* Clean up the interrupt number. We could do this in the stub, but
* it would cost two more bytes per stub entry.
*/
andl $0xff, %eax
pushl %eax /* ... and make it the first parameter */
enter_protected_mode
/*
* Now we are in protected mode. We need compute the right ESP based
* on saved real mode SS otherwise interrupt_handler() won't get
* correct parameters from the stack.
*/
movzwl %cs:__realmode_ss, %ecx
shll $4, %ecx
addl %ecx, %esp
/* Call the C interrupt handler */
movl $interrupt_handler, %eax
call *%eax
/* Restore real mode ESP based on saved SS */
movzwl %cs:__realmode_ss, %ecx
shll $4, %ecx
subl %ecx, %esp
enter_real_mode
/* Restore real mode SS */
movw %cs:__realmode_ss, %ss
/*
* Restore all registers, including those manipulated by the C
* handler
*/
popl %eax
pop %gs
pop %fs
pop %es
pop %ds
popal
iret
__realmode_ss = PTR_TO_REAL_MODE(.)
.word 0
.globl asm_realmode_code_size
asm_realmode_code_size:
.long . - asm_realmode_code
|
genetel200/u-boot
| 1,040
|
arch/x86/lib/crt0_ia32_efi.S
|
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* crt0-efi-ia32.S - x86 EFI startup code.
*
* Copyright (C) 1999 Hewlett-Packard Co.
* Contributed by David Mosberger <davidm@hpl.hp.com>.
* All rights reserved.
*/
.text
.align 4
.globl _start
_start:
pushl %ebp
movl %esp,%ebp
pushl 12(%ebp) # copy "image" argument
pushl 8(%ebp) # copy "systab" argument
call 0f
0: popl %eax
movl %eax,%ebx
addl $image_base-0b,%eax # %eax = ldbase
addl $_DYNAMIC-0b,%ebx # %ebx = _DYNAMIC
pushl %ebx # pass _DYNAMIC as second argument
pushl %eax # pass ldbase as first argument
call _relocate
popl %ebx
popl %ebx
testl %eax,%eax
jne .exit
call efi_main # call app with "image" and "systab" argument
.exit: leave
ret
/*
* hand-craft a dummy .reloc section so EFI knows it's a relocatable
* executable:
*/
.data
dummy: .long 0
#define IMAGE_REL_ABSOLUTE 0
.section .reloc
.long dummy /* Page RVA */
.long 10 /* Block Size (2*4+2) */
.word (IMAGE_REL_ABSOLUTE << 12) + 0 /* reloc for dummy */
|
genetel200/u-boot
| 7,033
|
arch/x86/cpu/start.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* U-Boot - x86 Startup Code
*
* (C) Copyright 2008-2011
* Graeme Russ, <graeme.russ@gmail.com>
*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
*/
#include <config.h>
#include <asm/global_data.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <generated/generic-asm-offsets.h>
#include <generated/asm-offsets.h>
#include <linux/linkage.h>
.section .text.start
.code32
.globl _start
.type _start, @function
.globl _x86boot_start
_x86boot_start:
/*
* This is the fail-safe 32-bit bootstrap entry point.
*
* This code is used when booting from another boot loader like
* coreboot or EFI. So we repeat some of the same init found in
* start16.
*/
cli
cld
/* Turn off cache (this might require a 486-class CPU) */
movl %cr0, %eax
orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
wbinvd
/* Tell 32-bit code it is being entered from an in-RAM copy */
movl $GD_FLG_WARM_BOOT, %ebx
/*
* Zero the BIST (Built-In Self Test) value since we don't have it.
* It must be 0 or the previous loader would have reported an error.
*/
movl $0, %ebp
jmp 1f
/* Add a way for tools to discover the _start entry point */
.align 4
.long 0x12345678
_start:
/*
* This is the 32-bit cold-reset entry point, coming from start16.
* Set %ebx to GD_FLG_COLD_BOOT to indicate this.
*/
movl $GD_FLG_COLD_BOOT, %ebx
/* Save BIST */
movl %eax, %ebp
1:
/* Save table pointer */
movl %ecx, %esi
#ifdef CONFIG_X86_LOAD_FROM_32_BIT
lgdt gdt_ptr2
#endif
/* Load the segement registers to match the GDT loaded in start16.S */
movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax
movw %ax, %fs
movw %ax, %ds
movw %ax, %gs
movw %ax, %es
movw %ax, %ss
/* Clear the interrupt vectors */
lidt blank_idt_ptr
/*
* Critical early platform init - generally not used, we prefer init
* to happen later when we have a console, in case something goes
* wrong.
*/
jmp early_board_init
.globl early_board_init_ret
early_board_init_ret:
post_code(POST_START)
/* Initialise Cache-As-RAM */
jmp car_init
.globl car_init_ret
car_init_ret:
#ifndef CONFIG_HAVE_FSP
/*
* We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
* or fully initialised SDRAM - we really don't care which)
* starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack
* and early malloc() area. The MRC requires some space at the top.
*
* Stack grows down from top of CAR. We have:
*
* top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE
* MRC area
* global_data with x86 global descriptor table
* early malloc area
* stack
* bottom-> CONFIG_SYS_CAR_ADDR
*/
movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp
#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
#endif
#else
/*
* U-Boot enters here twice. For the first time it comes from
* car_init_done() with esp points to a temporary stack and esi
* set to zero. For the second time it comes from fsp_init_done()
* with esi holding the HOB list address returned by the FSP.
*/
#endif
/* Set up global data */
mov %esp, %eax
call board_init_f_alloc_reserve
mov %eax, %esp
call board_init_f_init_reserve
#ifdef CONFIG_DEBUG_UART
call debug_uart_init
#endif
/* Get address of global_data */
mov %fs:0, %edx
#ifdef CONFIG_HAVE_FSP
/* Store the HOB list if we have one */
test %esi, %esi
jz skip_hob
movl %esi, GD_HOB_LIST(%edx)
/*
* After fsp_init() returns, the stack has already been switched to a
* place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
* Enlarge the size of malloc() pool before relocation since we have
* plenty of memory now.
*/
subl $CONFIG_FSP_SYS_MALLOC_F_LEN, %esp
movl %esp, GD_MALLOC_BASE(%edx)
skip_hob:
#else
/* Store table pointer */
movl %esi, GD_TABLE(%edx)
#endif
/* Store BIST */
movl %ebp, GD_BIST(%edx)
/* Set parameter to board_init_f() to boot flags */
post_code(POST_START_DONE)
xorl %eax, %eax
/* Enter, U-Boot! */
call board_init_f
/* indicate (lack of) progress */
movw $0x85, %ax
jmp die
.globl board_init_f_r_trampoline
.type board_init_f_r_trampoline, @function
board_init_f_r_trampoline:
/*
* SDRAM has been initialised, U-Boot code has been copied into
* RAM, BSS has been cleared and relocation adjustments have been
* made. It is now time to jump into the in-RAM copy of U-Boot
*
* %eax = Address of top of new stack
*/
/* Stack grows down from top of SDRAM */
movl %eax, %esp
/* See if we need to disable CAR */
call car_uninit
/* Re-enter U-Boot by calling board_init_f_r() */
call board_init_f_r
die:
hlt
jmp die
hlt
WEAK(car_uninit)
ret
ENDPROC(car_uninit)
blank_idt_ptr:
.word 0 /* limit */
.long 0 /* base */
.p2align 2 /* force 4-byte alignment */
/* Add a multiboot header so U-Boot can be loaded by GRUB2 */
multiboot_header:
/* magic */
.long 0x1badb002
/* flags */
.long (1 << 16)
/* checksum */
.long -0x1BADB002 - (1 << 16)
/* header addr */
.long multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE
/* load addr */
.long CONFIG_SYS_TEXT_BASE
/* load end addr */
.long 0
/* bss end addr */
.long 0
/* entry addr */
.long CONFIG_SYS_TEXT_BASE
#ifdef CONFIG_X86_LOAD_FROM_32_BIT
/*
* The following Global Descriptor Table is just enough to get us into
* 'Flat Protected Mode' - It will be discarded as soon as the final
* GDT is setup in a safe location in RAM
*/
gdt_ptr2:
.word 0x1f /* limit (31 bytes = 4 GDT entries - 1) */
.long gdt_rom2 /* base */
/* Some CPUs are picky about GDT alignment... */
.align 16
.globl gdt_rom2
gdt_rom2:
/*
* The GDT table ...
*
* Selector Type
* 0x00 NULL
* 0x08 Unused
* 0x10 32bit code
* 0x18 32bit data/stack
*/
/* The NULL Desciptor - Mandatory */
.word 0x0000 /* limit_low */
.word 0x0000 /* base_low */
.byte 0x00 /* base_middle */
.byte 0x00 /* access */
.byte 0x00 /* flags + limit_high */
.byte 0x00 /* base_high */
/* Unused Desciptor - (matches Linux) */
.word 0x0000 /* limit_low */
.word 0x0000 /* base_low */
.byte 0x00 /* base_middle */
.byte 0x00 /* access */
.byte 0x00 /* flags + limit_high */
.byte 0x00 /* base_high */
/*
* The Code Segment Descriptor:
* - Base = 0x00000000
* - Size = 4GB
* - Access = Present, Ring 0, Exec (Code), Readable
* - Flags = 4kB Granularity, 32-bit
*/
.word 0xffff /* limit_low */
.word 0x0000 /* base_low */
.byte 0x00 /* base_middle */
.byte 0x9b /* access */
.byte 0xcf /* flags + limit_high */
.byte 0x00 /* base_high */
/*
* The Data Segment Descriptor:
* - Base = 0x00000000
* - Size = 4GB
* - Access = Present, Ring 0, Non-Exec (Data), Writable
* - Flags = 4kB Granularity, 32-bit
*/
.word 0xffff /* limit_low */
.word 0x0000 /* base_low */
.byte 0x00 /* base_middle */
.byte 0x93 /* access */
.byte 0xcf /* flags + limit_high */
.byte 0x00 /* base_high */
#endif
|
genetel200/u-boot
| 1,240
|
arch/x86/cpu/call32.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*/
#include <asm/global_data.h>
#include <asm/msr-index.h>
#include <asm/processor-flags.h>
/*
* rdi - 32-bit code segment selector
* rsi - target address
* rdx - table address (0 if none)
*/
.code64
.globl cpu_call32
cpu_call32:
cli
/* Save table pointer */
mov %edx, %ebx
/*
* Debugging option, this outputs characters to the console UART
* mov $0x3f8,%edx
* mov $'a',%al
* out %al,(%dx)
*/
pushf
push %rdi /* 32-bit code segment */
lea compat(%rip), %rax
push %rax
.byte 0x48 /* REX prefix to force 64-bit far return */
retf
.code32
compat:
/*
* We are now in compatibility mode with a default operand size of
* 32 bits. First disable paging.
*/
movl %cr0, %eax
andl $~X86_CR0_PG, %eax
movl %eax, %cr0
/* Invalidate TLB */
xorl %eax, %eax
movl %eax, %cr3
/* Disable Long mode in EFER (Extended Feature Enable Register) */
movl $MSR_EFER, %ecx
rdmsr
btr $_EFER_LME, %eax
wrmsr
/* Set up table pointer for _x86boot_start */
mov %ebx, %ecx
/* Jump to the required target */
pushl %edi /* 32-bit code segment */
pushl %esi /* 32-bit target address */
retf
|
genetel200/u-boot
| 4,514
|
arch/x86/cpu/sipi_vector.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015 Google, Inc
*
* Taken from coreboot file of the same name
*/
/*
* The SIPI vector is responsible for initializing the APs in the sytem. It
* loads microcode, sets up MSRs, and enables caching before calling into
* C code
*/
#include <asm/global_data.h>
#include <asm/msr-index.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/sipi.h>
#define CODE_SEG (X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE)
#define DATA_SEG (X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE)
/*
* First we have the 16-bit section. Every AP process starts here.
* The simple task is to load U-Boot's Global Descriptor Table (GDT) to allow
* U-Boot's 32-bit code to become visible, then jump to ap_start.
*
* Note that this code is copied to RAM below 1MB in mp_init.c, and runs from
* there, but the 32-bit code (ap_start and onwards) is part of U-Boot and
* is therefore relocated to the top of RAM with other U-Boot code. This
* means that for the 16-bit code we must write relocatable code, but for the
* rest, we can do what we like.
*/
.text
.code16
.globl ap_start16
ap_start16:
cli
xorl %eax, %eax
movl %eax, %cr3 /* Invalidate TLB */
/* setup the data segment */
movw %cs, %ax
movw %ax, %ds
/* Use an address relative to the data segment for the GDT */
movl $gdtaddr, %ebx
subl $ap_start16, %ebx
data32 lgdt (%ebx)
movl %cr0, %eax
andl $(~(X86_CR0_PG | X86_CR0_AM | X86_CR0_WP | X86_CR0_NE | \
X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)), %eax
orl $(X86_CR0_NW | X86_CR0_CD | X86_CR0_PE), %eax
movl %eax, %cr0
movl $ap_start_jmp, %eax
subl $ap_start16, %eax
movw %ax, %bp
/* Jump to ap_start within U-Boot */
data32 cs ljmp *(%bp)
.align 4
.globl sipi_params_16bit
sipi_params_16bit:
/* 48-bit far pointer */
ap_start_jmp:
.long 0 /* offset set to ap_start by U-Boot */
.word CODE_SEG /* segment */
.word 0 /* padding */
gdtaddr:
.word 0 /* limit */
.long 0 /* table */
.word 0 /* unused */
.globl ap_start16_code_end
ap_start16_code_end:
/*
* Set up the special 'fs' segment for global_data. Then jump to ap_continue
* to set up the AP.
*/
.globl ap_start
ap_start:
.code32
movw $DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movw %ax, %gs
movw $(X86_GDT_ENTRY_32BIT_FS * X86_GDT_ENTRY_SIZE), %ax
movw %ax, %fs
/* Load the Interrupt descriptor table */
mov idt_ptr, %ebx
lidt (%ebx)
/* Obtain cpu number */
movl ap_count, %eax
1:
movl %eax, %ecx
inc %ecx
lock cmpxchg %ecx, ap_count
jnz 1b
/* Setup stacks for each CPU */
movl stack_size, %eax
mul %ecx
movl stack_top, %edx
subl %eax, %edx
mov %edx, %esp
/* Save cpu number */
mov %ecx, %esi
/* Determine if one should check microcode versions */
mov microcode_ptr, %edi
test %edi, %edi
jz microcode_done /* Bypass if no microde exists */
/* Get the Microcode version */
mov $1, %eax
cpuid
mov $MSR_IA32_UCODE_REV, %ecx
rdmsr
/* If something already loaded skip loading again */
test %edx, %edx
jnz microcode_done
/* Determine if parallel microcode loading is allowed */
cmp $0xffffffff, microcode_lock
je load_microcode
/* Protect microcode loading */
lock_microcode:
lock bts $0, microcode_lock
jc lock_microcode
load_microcode:
/* Load new microcode */
mov $MSR_IA32_UCODE_WRITE, %ecx
xor %edx, %edx
mov %edi, %eax
/*
* The microcode pointer is passed in pointing to the header. Adjust
* pointer to reflect the payload (header size is 48 bytes)
*/
add $UCODE_HEADER_LEN, %eax
pusha
wrmsr
popa
/* Unconditionally unlock microcode loading */
cmp $0xffffffff, microcode_lock
je microcode_done
xor %eax, %eax
mov %eax, microcode_lock
microcode_done:
/*
* Load MSRs. Each entry in the table consists of:
* 0: index,
* 4: value[31:0]
* 8: value[63:32]
* See struct saved_msr in mp_init.c.
*/
mov msr_table_ptr, %edi
mov msr_count, %ebx
test %ebx, %ebx
jz 1f
load_msr:
mov (%edi), %ecx
mov 4(%edi), %eax
mov 8(%edi), %edx
wrmsr
add $12, %edi
dec %ebx
jnz load_msr
1:
/* Enable caching */
mov %cr0, %eax
andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
mov %eax, %cr0
/* c_handler(cpu_num) */
movl %esi, %eax /* cpu_num */
mov c_handler, %esi
call *%esi
/* This matches struct sipi_param */
.align 4
.globl sipi_params
sipi_params:
idt_ptr:
.long 0
stack_top:
.long 0
stack_size:
.long 0
microcode_lock:
.long 0
microcode_ptr:
.long 0
msr_table_ptr:
.long 0
msr_count:
.long 0
c_handler:
.long 0
ap_count:
.long 0
|
genetel200/u-boot
| 3,004
|
arch/x86/cpu/start16.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* U-Boot - x86 Startup Code
*
* (C) Copyright 2008-2011
* Graeme Russ, <graeme.russ@gmail.com>
*
* (C) Copyright 2002,2003
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
*/
#include <asm/global_data.h>
#include <asm/processor-flags.h>
#define BOOT_SEG 0xffff0000 /* linear segment of boot code */
#define a32 .byte 0x67;
#define o32 .byte 0x66;
.section .start16, "ax"
.code16
.globl start16
start16:
/* Save BIST */
movl %eax, %ecx
/* Set the Cold Boot / Hard Reset flag */
movl $GD_FLG_COLD_BOOT, %ebx
xorl %eax, %eax
movl %eax, %cr3 /* Invalidate TLB */
/* Turn off cache (this might require a 486-class CPU) */
movl %cr0, %eax
orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
wbinvd
/* load the temporary Global Descriptor Table */
o32 cs lidt idt_ptr
o32 cs lgdt gdt_ptr
/* Now, we enter protected mode */
movl %cr0, %eax
orl $X86_CR0_PE, %eax
movl %eax, %cr0
/* Flush the prefetch queue */
jmp ff
ff:
/* Finally restore BIST and jump to the 32-bit initialization code */
movw $code32start, %ax
movw %ax, %bp
movl %ecx, %eax
o32 cs ljmp *(%bp)
/* 48-bit far pointer */
code32start:
.long _start /* offset */
.word 0x10 /* segment */
idt_ptr:
.word 0 /* limit */
.long 0 /* base */
/*
* The following Global Descriptor Table is just enough to get us into
* 'Flat Protected Mode' - It will be discarded as soon as the final
* GDT is setup in a safe location in RAM
*/
gdt_ptr:
.word 0x1f /* limit (31 bytes = 4 GDT entries - 1) */
.long BOOT_SEG + gdt_rom /* base */
/* Some CPUs are picky about GDT alignment... */
.align 16
.globl gdt_rom
gdt_rom:
/*
* The GDT table ...
*
* Selector Type
* 0x00 NULL
* 0x08 Unused
* 0x10 32bit code
* 0x18 32bit data/stack
*/
/* The NULL Desciptor - Mandatory */
.word 0x0000 /* limit_low */
.word 0x0000 /* base_low */
.byte 0x00 /* base_middle */
.byte 0x00 /* access */
.byte 0x00 /* flags + limit_high */
.byte 0x00 /* base_high */
/* Unused Desciptor - (matches Linux) */
.word 0x0000 /* limit_low */
.word 0x0000 /* base_low */
.byte 0x00 /* base_middle */
.byte 0x00 /* access */
.byte 0x00 /* flags + limit_high */
.byte 0x00 /* base_high */
/*
* The Code Segment Descriptor:
* - Base = 0x00000000
* - Size = 4GB
* - Access = Present, Ring 0, Exec (Code), Readable
* - Flags = 4kB Granularity, 32-bit
*/
.word 0xffff /* limit_low */
.word 0x0000 /* base_low */
.byte 0x00 /* base_middle */
.byte 0x9b /* access */
.byte 0xcf /* flags + limit_high */
.byte 0x00 /* base_high */
/*
* The Data Segment Descriptor:
* - Base = 0x00000000
* - Size = 4GB
* - Access = Present, Ring 0, Non-Exec (Data), Writable
* - Flags = 4kB Granularity, 32-bit
*/
.word 0xffff /* limit_low */
.word 0x0000 /* base_low */
.byte 0x00 /* base_middle */
.byte 0x93 /* access */
.byte 0xcf /* flags + limit_high */
.byte 0x00 /* base_high */
|
genetel200/u-boot
| 1,665
|
arch/x86/cpu/wakeup.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
*
* From coreboot src/arch/x86/wakeup.S
*/
#include <asm/acpi_s3.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#define RELOCATED(x) ((x) - __wakeup + WAKEUP_BASE)
#define CODE_SEG (X86_GDT_ENTRY_16BIT_CS * X86_GDT_ENTRY_SIZE)
#define DATA_SEG (X86_GDT_ENTRY_16BIT_DS * X86_GDT_ENTRY_SIZE)
.code32
.globl __wakeup
__wakeup:
/* First prepare the jmp to the resume vector */
mov 0x4(%esp), %eax /* vector */
/* last 4 bits of linear addr are taken as offset */
andw $0x0f, %ax
movw %ax, (__wakeup_offset)
mov 0x4(%esp), %eax
/* the rest is taken as segment */
shr $4, %eax
movw %ax, (__wakeup_segment)
/* Activate the right segment descriptor real mode */
ljmp $CODE_SEG, $RELOCATED(1f)
1:
/* 16 bit code from here on... */
.code16
/*
* Load the segment registers w/ properly configured segment
* descriptors. They will retain these configurations (limits,
* writability, etc.) once protected mode is turned off.
*/
mov $DATA_SEG, %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %fs
mov %ax, %gs
mov %ax, %ss
/* Turn off protection */
movl %cr0, %eax
andl $~X86_CR0_PE, %eax
movl %eax, %cr0
/* Now really going into real mode */
ljmp $0, $RELOCATED(1f)
1:
movw $0x0, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movw %ax, %fs
movw %ax, %gs
/*
* This is a FAR JMP to the OS waking vector.
* The C code changes the address to be correct.
*/
.byte 0xea
__wakeup_offset = RELOCATED(.)
.word 0x0000
__wakeup_segment = RELOCATED(.)
.word 0x0000
.globl __wakeup_size
__wakeup_size:
.long . - __wakeup
|
genetel200/u-boot
| 2,531
|
arch/x86/lib/fsp/fsp_car.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*/
#include <config.h>
#include <asm/post.h>
.globl car_init
car_init:
/*
* Note: ebp holds the BIST value (built-in self test) so far, but ebp
* will be destroyed through the FSP call, thus we have to test the
* BIST value here before we call into FSP.
*/
test %ebp, %ebp
jz car_init_start
post_code(POST_BIST_FAILURE)
jmp die
car_init_start:
post_code(POST_CAR_START)
lea find_fsp_header_romstack, %esp
jmp find_fsp_header
find_fsp_header_ret:
/* EAX points to FSP_INFO_HEADER */
mov %eax, %ebp
/* sanity test */
cmp $CONFIG_FSP_ADDR, %eax
jb die
/* calculate TempRamInitEntry address */
mov 0x30(%ebp), %eax
add 0x1c(%ebp), %eax
/* call FSP TempRamInitEntry to setup temporary stack */
lea temp_ram_init_romstack, %esp
jmp *%eax
temp_ram_init_ret:
addl $4, %esp
cmp $0, %eax
jnz car_init_fail
post_code(POST_CAR_CPU_CACHE)
/*
* The FSP TempRamInit initializes the ecx and edx registers to
* point to a temporary but writable memory range (Cache-As-RAM).
* ecx: the start of this temporary memory range,
* edx: the end of this range.
*/
/* stack grows down from top of CAR */
movl %edx, %esp
subl $4, %esp
xor %esi, %esi
jmp car_init_done
.global fsp_init_done
fsp_init_done:
/*
* We come here from fsp_continue() with eax pointing to the HOB list.
* Save eax to esi temporarily.
*/
movl %eax, %esi
car_init_done:
/*
* Re-initialize the ebp (BIST) to zero, as we already reach here
* which means we passed BIST testing before.
*/
xorl %ebp, %ebp
jmp car_init_ret
car_init_fail:
post_code(POST_CAR_FAILURE)
die:
hlt
jmp die
hlt
/*
* The function call before CAR initialization is tricky. It cannot
* be called using the 'call' instruction but only the 'jmp' with
* the help of a handcrafted stack in the ROM. The stack needs to
* contain the function return address as well as the parameters.
*/
.balign 4
find_fsp_header_romstack:
.long find_fsp_header_ret
.balign 4
temp_ram_init_romstack:
.long temp_ram_init_ret
.long temp_ram_init_params
temp_ram_init_params:
_dt_ucode_base_size:
/* These next two fields are filled in by ifdtool */
.globl ucode_base
ucode_base: /* Declared in microcode.h */
.long 0 /* microcode base */
.globl ucode_size
ucode_size: /* Declared in microcode.h */
.long 0 /* microcode size */
.long CONFIG_SYS_MONITOR_BASE /* code region base */
.long CONFIG_SYS_MONITOR_LEN /* code region size */
|
genetel200/u-boot
| 2,245
|
arch/x86/cpu/i386/call64.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014 Google, Inc
* Copyright (C) 1991, 1992, 1993 Linus Torvalds
*
* Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
*/
#include <asm/global_data.h>
#include <asm/msr-index.h>
#include <asm/processor-flags.h>
.code32
.globl cpu_call64
cpu_call64:
/*
* cpu_call64(ulong pgtable, ulong setup_base, ulong target)
*
* eax - pgtable
* edx - setup_base
* ecx - target
*/
cli
push %ecx /* arg2 = target */
push %edx /* arg1 = setup_base */
mov %eax, %ebx
/* Load new GDT with the 64bit segments using 32bit descriptor */
leal gdt, %eax
movl %eax, gdt+2
lgdt gdt
/* Enable PAE mode */
movl $(X86_CR4_PAE), %eax
movl %eax, %cr4
/* Enable the boot page tables */
leal (%ebx), %eax
movl %eax, %cr3
/* Enable Long mode in EFER (Extended Feature Enable Register) */
movl $MSR_EFER, %ecx
rdmsr
btsl $_EFER_LME, %eax
wrmsr
/* After gdt is loaded */
xorl %eax, %eax
lldt %ax
movl $0x20, %eax
ltr %ax
/*
* Setup for the jump to 64bit mode
*
* When the jump is performed we will be in long mode but
* in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
* (and in turn EFER.LMA = 1). To jump into 64bit mode we use
* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
* We place all of the values on our mini stack so lret can
* used to perform that far jump. See the gdt below.
*/
pop %esi /* setup_base */
pushl $0x10
leal lret_target, %eax
pushl %eax
/* Enter paged protected Mode, activating Long Mode */
movl $(X86_CR0_PG | X86_CR0_PE), %eax
movl %eax, %cr0
/* Jump from 32bit compatibility mode into 64bit mode. */
lret
code64:
lret_target:
pop %eax /* target */
mov %eax, %eax /* Clear bits 63:32 */
jmp *%eax /* Jump to the 64-bit target */
.globl call64_stub_size
call64_stub_size:
.long . - cpu_call64
.data
.align 16
.globl gdt64
gdt64:
gdt:
.word gdt_end - gdt - 1
.long gdt /* Fixed up by code above */
.word 0
.quad 0x0000000000000000 /* NULL descriptor */
.quad 0x00af9a000000ffff /* __KERNEL_CS */
.quad 0x00cf92000000ffff /* __KERNEL_DS */
.quad 0x0080890000000000 /* TS descriptor */
.quad 0x0000000000000000 /* TS continued */
gdt_end:
|
genetel200/u-boot
| 1,139
|
arch/x86/cpu/i386/setjmp.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Written by H. Peter Anvin <hpa@zytor.com>
* Brought in from Linux v4.4 and modified for U-Boot
* From Linux arch/um/sys-i386/setjmp.S
*/
#define _REGPARM
/*
* The jmp_buf is assumed to contain the following, in order:
* %ebx
* %esp
* %ebp
* %esi
* %edi
* <return address>
*/
.text
.align 4
.globl setjmp
.type setjmp, @function
setjmp:
#ifdef _REGPARM
movl %eax, %edx
#else
movl 4(%esp), %edx
#endif
popl %ecx /* Return address, and adjust the stack */
xorl %eax, %eax /* Return value */
movl %ebx, (%edx)
movl %esp, 4(%edx) /* Post-return %esp! */
pushl %ecx /* Make the call/return stack happy */
movl %ebp, 8(%edx)
movl %esi, 12(%edx)
movl %edi, 16(%edx)
movl %ecx, 20(%edx) /* Return address */
ret
/* Provide function size if needed */
.size setjmp, .-setjmp
.align 4
.globl longjmp
.type longjmp, @function
longjmp:
#ifdef _REGPARM
xchgl %eax, %edx
#else
movl 4(%esp), %edx /* jmp_ptr address */
#endif
movl (%edx), %ebx
movl 4(%edx), %esp
movl 8(%edx), %ebp
movl 12(%edx), %esi
movl 16(%edx), %edi
jmp *20(%edx)
.size longjmp, .-longjmp
|
genetel200/u-boot
| 5,618
|
arch/x86/cpu/intel_common/car.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 Google, Inc
*
* From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
*/
#include <common.h>
#include <asm/microcode.h>
#include <asm/msr-index.h>
#include <asm/mtrr.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
/* Cache 4GB - MRC_SIZE_KB for MRC */
#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define NOEVICTMOD_MSR 0x2e0
/*
* Note: ebp must not be touched in this code as it holds the BIST
* value (built-in self test). We preserve this value until it can
* be written to global_data when CAR is ready for use.
*/
.globl car_init
car_init:
post_code(POST_CAR_START)
/* Send INIT IPI to all excluding ourself */
movl $0x000C4500, %eax
movl $0xFEE00300, %esi
movl %eax, (%esi)
/* TODO: Load microcode later - the 'no eviction' mode breaks this */
movl $MSR_IA32_UCODE_WRITE, %ecx
xorl %edx, %edx
movl $_dt_ucode_base_size, %eax
movl (%eax), %eax
addl $UCODE_HEADER_LEN, %eax
wrmsr
post_code(POST_CAR_SIPI)
/* Zero out all fixed range and variable range MTRRs */
movl $mtrr_table, %esi
movl $((mtrr_table_end - mtrr_table) / 2), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
movw (%esi), %bx
movzx %bx, %ecx
wrmsr
add $2, %esi
dec %edi
jnz clear_mtrrs
post_code(POST_CAR_MTRR)
/* Configure the default memory type to uncacheable */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $(~0x00000cff), %eax
wrmsr
post_code(POST_CAR_UNCACHEABLE)
/* Set Cache-as-RAM base address */
movl $(MTRR_PHYS_BASE_MSR(0)), %ecx
movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
post_code(POST_CAR_BASE_ADDRESS)
/* Set Cache-as-RAM mask */
movl $(MTRR_PHYS_MASK_MSR(0)), %ecx
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
post_code(POST_CAR_MASK)
/* Enable MTRR */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0) */
movl %cr0, %eax
andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
invd
movl %eax, %cr0
/* enable the 'no eviction' mode */
movl $NOEVICTMOD_MSR, %ecx
rdmsr
orl $1, %eax
andl $~2, %eax
wrmsr
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE / 4), %ecx
xorl %eax, %eax
rep stosl
/* enable the 'no eviction run' state */
movl $NOEVICTMOD_MSR, %ecx
rdmsr
orl $3, %eax
wrmsr
post_code(POST_CAR_FILL)
/* Enable Cache-as-RAM mode by disabling cache */
movl %cr0, %eax
orl $X86_CR0_CD, %eax
movl %eax, %cr0
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE_MSR(1), %ecx
xorl %edx, %edx
movl $car_init_ret, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
movl $MTRR_PHYS_MASK_MSR(1), %ecx
movl $CPU_PHYSMASK_HI, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
post_code(POST_CAR_ROM_CACHE)
#ifdef CONFIG_CACHE_MRC_BIN
/* Enable caching for ram init code to run faster */
movl $MTRR_PHYS_BASE_MSR(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
movl $MTRR_PHYS_MASK_MSR(2), %ecx
movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif
post_code(POST_CAR_MRC_CACHE)
/* Enable cache */
movl %cr0, %eax
andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
movl %eax, %cr0
post_code(POST_CAR_CPU_CACHE)
/* All CPUs need to be in Wait for SIPI state */
wait_for_sipi:
movl (%esi), %eax
bt $12, %eax
jc wait_for_sipi
/* return */
jmp car_init_ret
.globl car_uninit
car_uninit:
/* Disable cache */
movl %cr0, %eax
orl $X86_CR0_CD, %eax
movl %eax, %cr0
/* Disable MTRRs */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $(~MTRR_DEF_TYPE_EN), %eax
wrmsr
/* Disable the no-eviction run state */
movl $NOEVICTMOD_MSR, %ecx
rdmsr
andl $~2, %eax
wrmsr
invd
/* Disable the no-eviction mode */
rdmsr
andl $~1, %eax
wrmsr
#ifdef CONFIG_CACHE_MRC_BIN
/* Clear the MTRR that was used to cache MRC */
xorl %eax, %eax
xorl %edx, %edx
movl $MTRR_PHYS_BASE_MSR(2), %ecx
wrmsr
movl $MTRR_PHYS_MASK_MSR(2), %ecx
wrmsr
#endif
/* Enable MTRRs */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
invd
ret
mtrr_table:
/* Fixed MTRRs */
.word 0x250, 0x258, 0x259
.word 0x268, 0x269, 0x26A
.word 0x26B, 0x26C, 0x26D
.word 0x26E, 0x26F
/* Variable MTRRs */
.word 0x200, 0x201, 0x202, 0x203
.word 0x204, 0x205, 0x206, 0x207
.word 0x208, 0x209, 0x20A, 0x20B
.word 0x20C, 0x20D, 0x20E, 0x20F
.word 0x210, 0x211, 0x212, 0x213
mtrr_table_end:
.align 4
_dt_ucode_base_size:
/* These next two fields are filled in by ifdtool */
.globl ucode_base
ucode_base: /* Declared in microcode.h */
.long 0 /* microcode base */
.globl ucode_size
ucode_size: /* Declared in microcode.h */
.long 0 /* microcode size */
|
genetel200/u-boot
| 2,247
|
arch/x86/cpu/quark/car.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*/
#include <config.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/arch/quark.h>
#include <asm/arch/msg_port.h>
.globl car_init
car_init:
post_code(POST_CAR_START)
/*
* Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
* initialized by hardware. eSRAM is the ideal place to be used
* for Cache-As-RAM (CAR) before system memory is available.
*
* Relocate this eSRAM to a suitable location in the physical
* memory map and enable it.
*/
/* Host Memory Bound Register P03h:R08h */
mov $((MSG_PORT_HOST_BRIDGE << 16) | (HM_BOUND << 8)), %eax
mov $(DRAM_BASE + DRAM_MAX_SIZE + ESRAM_SIZE), %edx
lea 1f, %esp
jmp msg_port_write
1:
/* eSRAM Block Page Control Register P05h:R82h */
mov $((MSG_PORT_MEM_MGR << 16) | (ESRAM_BLK_CTRL << 8)), %eax
mov $(ESRAM_BLOCK_MODE | (CONFIG_ESRAM_BASE >> 24)), %edx
lea 2f, %esp
jmp msg_port_write
2:
post_code(POST_CAR_CPU_CACHE)
jmp car_init_ret
msg_port_read:
/*
* Parameter:
* eax[23:16] - Message Port ID
* eax[15:08] - Register Address
*
* Return Value:
* eax - Message Port Register value
*
* Return Address: esp
*/
or $((MSG_OP_READ << 24) | MSG_BYTE_ENABLE), %eax
mov %eax, %ebx
/* Write MCR B0:D0:F0:RD0 */
mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax
mov $PCI_REG_ADDR, %dx
out %eax, %dx
mov $PCI_REG_DATA, %dx
mov %ebx, %eax
out %eax, %dx
/* Read MDR B0:D0:F0:RD4 */
mov $(PCI_CFG_EN | MSG_DATA_REG), %eax
mov $PCI_REG_ADDR, %dx
out %eax, %dx
mov $PCI_REG_DATA, %dx
in %dx, %eax
jmp *%esp
msg_port_write:
/*
* Parameter:
* eax[23:16] - Message Port ID
* eax[15:08] - Register Address
* edx - Message Port Register value to write
*
* Return Address: esp
*/
or $((MSG_OP_WRITE << 24) | MSG_BYTE_ENABLE), %eax
mov %eax, %esi
mov %edx, %edi
/* Write MDR B0:D0:F0:RD4 */
mov $(PCI_CFG_EN | MSG_DATA_REG), %eax
mov $PCI_REG_ADDR, %dx
out %eax, %dx
mov $PCI_REG_DATA, %dx
mov %edi, %eax
out %eax, %dx
/* Write MCR B0:D0:F0:RD0 */
mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax
mov $PCI_REG_ADDR, %dx
out %eax, %dx
mov $PCI_REG_DATA, %dx
mov %esi, %eax
out %eax, %dx
jmp *%esp
|
genetel200/u-boot
| 4,834
|
post/lib_powerpc/asm.S
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
*/
#include <config.h>
#include <post.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#if CONFIG_POST & CONFIG_SYS_POST_CPU
/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
.global cpu_post_exec_02
cpu_post_exec_02:
isync
mflr r0
stwu r0, -4(r1)
subi r1, r1, 104
stmw r6, 0(r1)
mtlr r3
mr r3, r4
mr r4, r5
blrl
lmw r6, 0(r1)
addi r1, r1, 104
lwz r0, 0(r1)
addi r1, r1, 4
mtlr r0
blr
/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */
.global cpu_post_exec_04
cpu_post_exec_04:
isync
mflr r0
stwu r0, -4(r1)
subi r1, r1, 96
stmw r8, 0(r1)
mtlr r3
mr r3, r4
mr r4, r5
mr r5, r6
mtxer r7
blrl
lmw r8, 0(r1)
addi r1, r1, 96
lwz r0, 0(r1)
addi r1, r1, 4
mtlr r0
blr
/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */
.global cpu_post_exec_12
cpu_post_exec_12:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
mtlr r3
mr r3, r5
mr r4, r6
blrl
lwz r4, 0(r1)
stw r3, 0(r4)
lwz r0, 4(r1)
addi r1, r1, 8
mtlr r0
blr
/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */
.global cpu_post_exec_11
cpu_post_exec_11:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
mtlr r3
mr r3, r5
blrl
lwz r4, 0(r1)
stw r3, 0(r4)
lwz r0, 4(r1)
addi r1, r1, 8
mtlr r0
blr
/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */
.global cpu_post_exec_21
cpu_post_exec_21:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
stwu r5, -4(r1)
li r0, 0
mtxer r0
lwz r0, 0(r4)
mtcr r0
mtlr r3
mr r3, r6
blrl
mfcr r0
lwz r4, 4(r1)
stw r0, 0(r4)
lwz r4, 0(r1)
stw r3, 0(r4)
lwz r0, 8(r1)
addi r1, r1, 12
mtlr r0
blr
/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
ulong op2); */
.global cpu_post_exec_22
cpu_post_exec_22:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
stwu r5, -4(r1)
li r0, 0
mtxer r0
lwz r0, 0(r4)
mtcr r0
mtlr r3
mr r3, r6
mr r4, r7
blrl
mfcr r0
lwz r4, 4(r1)
stw r0, 0(r4)
lwz r4, 0(r1)
stw r3, 0(r4)
lwz r0, 8(r1)
addi r1, r1, 12
mtlr r0
blr
/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */
.global cpu_post_exec_12w
cpu_post_exec_12w:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
mtlr r3
lwz r3, 0(r4)
mr r4, r5
mr r5, r6
blrl
lwz r4, 0(r1)
stw r3, 0(r4)
lwz r0, 4(r1)
addi r1, r1, 8
mtlr r0
blr
/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */
.global cpu_post_exec_11w
cpu_post_exec_11w:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
mtlr r3
lwz r3, 0(r4)
mr r4, r5
blrl
lwz r4, 0(r1)
stw r3, 0(r4)
lwz r0, 4(r1)
addi r1, r1, 8
mtlr r0
blr
/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */
.global cpu_post_exec_22w
cpu_post_exec_22w:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
stwu r6, -4(r1)
mtlr r3
lwz r3, 0(r4)
mr r4, r5
blrl
lwz r4, 4(r1)
stw r3, 0(r4)
lwz r4, 0(r1)
stw r5, 0(r4)
lwz r0, 8(r1)
addi r1, r1, 12
mtlr r0
blr
/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */
.global cpu_post_exec_21w
cpu_post_exec_21w:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
stwu r5, -4(r1)
mtlr r3
lwz r3, 0(r4)
blrl
lwz r5, 4(r1)
stw r3, 0(r5)
lwz r5, 0(r1)
stw r4, 0(r5)
lwz r0, 8(r1)
addi r1, r1, 12
mtlr r0
blr
/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */
.global cpu_post_exec_21x
cpu_post_exec_21x:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
stwu r5, -4(r1)
mtlr r3
mr r3, r6
blrl
lwz r5, 4(r1)
stw r3, 0(r5)
lwz r5, 0(r1)
stw r4, 0(r5)
lwz r0, 8(r1)
addi r1, r1, 12
mtlr r0
blr
/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
ulong cr); */
.global cpu_post_exec_31
cpu_post_exec_31:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
stwu r5, -4(r1)
stwu r6, -4(r1)
mtlr r3
lwz r3, 0(r4)
lwz r4, 0(r5)
mr r6, r7
mfcr r7
blrl
mtcr r7
lwz r7, 8(r1)
stw r3, 0(r7)
lwz r7, 4(r1)
stw r4, 0(r7)
lwz r7, 0(r1)
stw r5, 0(r7)
lwz r0, 12(r1)
addi r1, r1, 16
mtlr r0
blr
/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */
.global cpu_post_complex_1_asm
cpu_post_complex_1_asm:
li r9,0
cmpw r9,r7
bge cpu_post_complex_1_done
mtctr r7
cpu_post_complex_1_loop:
mullw r0,r3,r4
subf r0,r5,r0
divw r0,r0,r6
add r9,r9,r0
bdnz cpu_post_complex_1_loop
cpu_post_complex_1_done:
mr r3,r9
blr
/* int cpu_post_complex_2_asm (int x, int n); */
.global cpu_post_complex_2_asm
cpu_post_complex_2_asm:
mr. r0,r4
mtctr r0
mr r0,r3
li r3,1
li r4,1
blelr
cpu_post_complex_2_loop:
mullw r3,r3,r0
add r3,r3,r4
bdnz cpu_post_complex_2_loop
blr
#endif
|
geobitus/m328p_sin_pwm
| 1,384
|
reg_init.s
|
void reg_init()
{
asm(
"cli \n"
"in r24, 0x34 \n"
"andi r24, 0xF7 \n"
"out 0x34, r24 \n"
"ldi r30, 0x60 \n"
"ldi r31, 0x00 \n"
"ld r24, Z \n"
"ori r24, 0x18 \n"
"st Z, r24 \n"
"st Z, r1 \n"
"in r24, 0x04 \n"
"ori r24, 0x26 \n"
"out 0x04, r24 \n"
"in r24, 0x05 \n"
"ori r24, 0x06 \n"
"out 0x05, r24 \n"
"ldi r30, 0x6F \n"
"ldi r31, 0x00 \n"
"st Z, r1 \n"
"ldi r26, 0x81 \n"
"ldi r27, 0x00 \n"
"st X, r1 \n"
"ldi r28, 0x80 \n"
"ldi r29, 0x00 \n"
"st Y, r1 \n"
"ld r24, Y \n"
"ori r24, 0xC2 \n"
"st Y, r24 \n"
"ld r24, X \n"
"ori r24, 0x19 \n"
"st X, r24 \n"
"ld r24, Z \n"
"ori r24, 0x01 \n"
"st Z, r24 \n"
"cbi 0x0a, 2 \n"
"cbi 0x0b, 2 \n"
"ldi r30, 0x6E \n"
"ldi r31, 0x00 \n"
"ld r24, Z \n"
"andi r24, 0xFE \n"
"st Z, r24 \n"
"ldi r30, 0x69 \n"
"ldi r31, 0x00 \n"
"ld r24, Z \n"
"ori r24, 0x03 \n"
"st Z, r24 \n"
"sbi 0x1d, 0 \n"
"lds r24, 0x0151 \n"
"lds r25, 0x0152 \n"
"sts 0x0087, r25 \n"
"sts 0x0086, r24 \n"
"sei ");
}
|
georgevio/IoT-Embedded
| 1,818
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/addc/float/dspm_addc_f32_ae32.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_addc_platform.h"
#if (dspm_addc_f32_ae32_enabled == 1)
// This is an add function for sub-matrices for ESP32 processor
.text
.align 4
.global dspm_addc_f32_ae32
.type dspm_addc_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_addc_f32_ansi(const float *input, float *output, float C, int rows, int cols, int padd_in, int padd_out, int step_in, int step_out);
dspm_addc_f32_ae32:
// input - a2
// output - a3
// C - a4
// rows - a5
// cols - a6
// padd_in - a7
// padd_out - a8
// step_in - a9
// step_out - a10
entry a1, 16
l32i.n a8, a1, 16 // padd_out
l32i.n a9, a1, 20 // step_in
l32i.n a10, a1, 24 // step_out
slli a9, a9, 2 // a9 - step_in << 2
slli a10, a10, 2 // a10 - step_out << 2
wfr f0, a4 // a4 - load to the f0
.outer_loop_addc_f32_ae32:
loopnez a6, .loop_addc_f32_ae32
lsxp f1, a2, a9 // load input to f1, increment input (input_ptr+=step_in)
add.s f2, f0, f1 // f2 = f0 + f1
ssxp f2, a3, a10 // save result f2 to output a3, increment output (output_ptr+=step_out)
.loop_addc_f32_ae32:
addx4 a2, a7, a2 // input1_ptr += (padd_in << 2);
addx4 a3, a8, a3 // output_ptr += (padd_out << 2);
addi.n a5, a5, -1 // rows - 1
bnez a5, .outer_loop_addc_f32_ae32
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dspm_add_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,892
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_3x3x1_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_3x3x1_f32_ae32_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_3x3x1_f32_ae32
.type dspm_mult_3x3x1_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mult_3x3x1_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_3x3x1_f32_ae32:
// A - a2
// B - a3
// C - a4
// a5 - 0
// a6 - 3
entry a1, 16
movi a5, 0
movi a6, 3
lsi f13,a3, 0 // B[0]
lsi f14,a3, 4 // B[1]
lsi f15,a3, 8 // B[2]
// addi a2, a2, -12 // To compensate first increment
loopnez a6, loop_mac_3x3x1_end_m_ae32
wfr f0, a5
lsi f2, a2, 0
madd.s f0, f2, f13
lsi f3, a2, 4
madd.s f0, f3, f14
lsi f4, a2, 8
madd.s f0, f4, f15
addi a2, a2, 12
ssi f0, a4, 0
addi a4, a4, 4
loop_mac_3x3x1_end_m_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //
|
georgevio/IoT-Embedded
| 3,043
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_f32_arp4.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_arp4_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_f32_arp4
.global .dspm_mult_f32_arp4_body
.type dspm_mult_f32_arp4,@function
// The function implements the following C code:
// esp_err_t dspm_mult_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_f32_arp4:
// A - a2: a0
// B - a3: a1
// C - a4: a2
// m - a5: a3
// n - a6: a4
// k - a7: a5
// a8:a6 = n*4
// a10:t0 = 4
// a9:a7 - counter loop1: 0..m
// a11:t1 - counter loop2: 0..k
// a12:t2 - A
// a13:t3 - B
// a14:t4
// a15:t5
add sp,sp,-16
// Array increment for floating point data should be 4
.dspm_mult_f32_arp4_body:
slli a6, a4, 2 // Pointer increment for A
slli t5,a5, 2 // Pointer increment for B
li t4, 0 // Innitial state of accumulator f1
li t0, 4 // Increment = 4
li a7, 0 // counter loop1
.dpf_loop1:
li t1, 0 // reset counter for loop2
.dpf_loop2:
// Clear initial state of the result register
// a2 - A
// a3 - B
// a6 - n
// a10 - step == 4 bytes
// a8 - step n*4
mv t2, a0 // load A
slli t3, t1, 2 // loop count to pointer value
add t3, a1, t3 // load A
fmv.w.x fa2,zero // reset fa2
// Calculating dotproduct...
esp.lp.setup 0, a4, .matrix_mul_loop
flw fa0, 0(t2)
add t2, t2, t0
flw fa1, 0(t3)
fmadd.s fa2, fa1, fa0, fa2
.matrix_mul_loop: add t3, t3, t5
fsw fa2, 0(a2)
addi a2, a2, 4 // increment a2 for next time
// check loop 2
addi t1, t1, 1 // Increment loop2 counter
blt t1, a5, .dpf_loop2
// check loop 1
add a0, a0, a6 // Increment A, A = A[i*n]
add a7, a7, 1 // Increment loop1 counter
blt a7, a3, .dpf_loop1
// Exit
mv a0, a6 // return status ESP_OK
add sp,sp,16
ret
#endif //dspm_mult_f32_arp4_enabled
|
georgevio/IoT-Embedded
| 6,777
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_ex_f32_aes3.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_aes3_enabled == 1)
// This is matrix multiplication function for ESP32S3 processor.
.text
.align 4
.global dspm_mult_ex_f32_aes3
.global .dspm_mult_ex_f32_ae32_body
.type dspm_mult_ex_f32_aes3,@function
// The function implements the following C code:
//esp_err_t dspm_mult_ex_f32_ansi(const float* A, const float* B, float* C, int A_rows, int A_cols, int B_cols, int A_padding, int B_padding, int C_padding)
//{
// const int A_step = A_cols + A_padding;
// const int B_step = B_cols + B_padding;
// const int C_step = B_cols + C_padding;
//
// for (int i = 0; i < A_rows; i++) {
// for (int j = 0; j < B_cols; j++) {
// C[i * C_step + j] = A[i * A_step] * B[j];
// for (int s = 1; s < A_cols; s++) {
// C[i * C_step + j] += A[i * A_step + s] * B[s * B_step + j];
// }
// }
// }
// return ESP_OK;
//}
// A - a2
// B - a3
// C - a4
// m - a5
// n - a6
// k - a7
// A_padd = a8
// B_padd = a9
// C_padd = a15
dspm_mult_ex_f32_aes3:
entry a1, 16
l32i.n a8, a1, 16 // A_padding
l32i.n a9, a1, 20 // B_padding
l32i.n a15, a1, 24 // C_padding
// Check if we can use S3 memory model
// Check matrices dimensions and paddings all of them must be divisible by 4
or a12, a5, a6 // a12 = m OR n
or a14, a8, a9 // a14 = A_padd OR B_padd
or a12, a12, a7 // a12 = m OR n OR k
or a14, a14, a15 // a14 = A_padd OR B_padd OR C_padd
or a12, a12, a14 // a12 = m OR n OR k OR A_padd OR B_padd OR C_padd
movi.n a11, 3 // a11 = byte mask
and a12, a12, a11 // a12 = a12 AND 3 (byte mask)
// Check alignment of A B C matrices data pointers
movi.n a11, 15 // a11 = byte mask
or a10, a3, a2 // a10 = A pointer OR B pointer
or a10, a10, a4 // a10 = A pointer OR B pointer OR C pointer
and a10, a10, a11 // a10 = a10 AND 15 (byte mask)
or a12, a12, a10 // a12 = mat_dim OR alignment
beqz a12, .s3_mmult_ex // if zero, jump to s3_mult
// Call Esp32 function
J .dspm_mult_ex_f32_ae32_body
.s3_mmult_ex:
// f0, f1, f2, f3 - multiplication result
// f4, f5, f6, f7 - input for matrix B
// f8, f9, f10,f11- input far matrix A
movi.n a14, 0 // B pointer increment for y loop
add a15, a15, a7 // a15 = k + C_padding
slli a10, a15, 2 // a10 = (K + C_padding) * 4 - step for rows
mov a15, a9 // a15 = B_padd
slli a15, a15, 2 // a15 = B_padd * 4
add a7, a7, a9 // a7 = k + B_padding
slli a12, a7, 2 // a12 = (K + B_padding) * 4 - step for rows
srli a11, a6, 2 // a11 = n / 4
addi.n a11, a11, -1 // a11 = innter loop count (n)
slli a6, a8, 2 // a6 = A_padding *4 = A_pointer step
mov a13, a3 // backup B pointer
mov a7, a4 // backup C pointer
.loop_x_mult_ex:
movi.n a9, 0 // reset loop1 counter
mov a8, a2 // move A matrix back to the beginning
.loop_y_mult_ex:
add a13, a3, a14 // Reload Y pointer to Y11 + A14
EE.LDF.128.IP f11, f10, f9, f8, a8, 16 // Load A values: X11, X12, X13, X14
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y11, Y12, Y13, Y14
mul.s f0, f4, f8 // f0 = X11*Y11
mul.s f1, f5, f8 // f1 = X12*Y11
mul.s f2, f6, f8 // f2 = X13*Y11
mul.s f3, f7, f8 // f3 = X14*Y11
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y21, Y22, Y23, Y24
madd.s f0, f4, f9 // f0 = X11*Y11 + X12*Y21
madd.s f1, f5, f9 // f1 = X11*Y12 + X12*Y22
madd.s f2, f6, f9 // f2 = X11*Y13 + X12*Y23
madd.s f3, f7, f9 // f3 = X11*Y14 + X12*Y24
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y31, Y32, Y33, Y34
madd.s f0, f4, f10 // f0 = X11*Y11 + X12*Y21 + X13*Y31
madd.s f1, f5, f10 // f1 = X11*Y12 + X12*Y22 + X13*Y32
madd.s f2, f6, f10 // f2 = X11*Y13 + X12*Y23 + X13*Y33
madd.s f3, f7, f10 // f3 = X11*Y14 + X12*Y24 + X13*Y34
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y41, Y42, Y43, Y44
madd.s f0, f4, f11 // f0 = X11*Y11 + X12*Y21 + X13*Y31 + X14*Y41
madd.s f1, f5, f11 // f1 = X11*Y12 + X12*Y22 + X13*Y32 + X14*Y42
madd.s f2, f6, f11 // f2 = X11*Y13 + X12*Y23 + X13*Y33 + X14*Y43
madd.s f3, f7, f11 // f3 = X11*Y14 + X12*Y24 + X13*Y34 + X14*Y44
loopnez a11, .iner_loop_mult_ex
EE.LDF.128.IP f11, f10, f9, f8, a8, 16 // Load A values: X15, X16, X17, X18
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y51, Y52, Y53, Y54
madd.s f0, f4, f8 // f0 += X15*Y51
madd.s f1, f5, f8 // f1 += X15*Y52
madd.s f2, f6, f8 // f2 += X15*Y53
madd.s f3, f7, f8 // f3 += X15*Y54
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y61, Y62, Y63, Y64
madd.s f0, f4, f9 // f0 += X16*Y61
madd.s f1, f5, f9 // f1 += X16*Y62
madd.s f2, f6, f9 // f2 += X16*Y63
madd.s f3, f7, f9 // f3 += X16*Y64
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y71, Y72, Y73, Y74
madd.s f0, f4, f10 // f0 =
madd.s f1, f5, f10 // f1 =
madd.s f2, f6, f10 // f2 =
madd.s f3, f7, f10 // f3 =
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y81, Y82, Y83, Y84
madd.s f0, f4, f11 // f0 =
madd.s f1, f5, f11 // f1 =
madd.s f2, f6, f11 // f2 =
madd.s f3, f7, f11 // f3 =
.iner_loop_mult_ex:
EE.STF.128.XP f3, f2, f1, f0, a4, a10 // Store result
addi.n a9, a9, 1 // Increment loop1 counter
add a8, a8, a6 // (increase A pointer by A_padding * 4 times)
blt a9, a5, .loop_y_mult_ex
addi.n a7, a7, 16 // Increase C pinter by 16
mov a4, a7
addi.n a14, a14, 16 // Increase B pointer by 16
addi.n a15, a15, 16 // Increment loop2 counter by 16
blt a15, a12, .loop_x_mult_ex
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //dspm_mult_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 4,782
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_f32_aes3.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_aes3_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_f32_aes3
.global .dspm_mult_f32_ae32_body
.type dspm_mult_f32_aes3,@function
// The function implements the following C code:
// esp_err_t dspm_mult_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_f32_aes3:
entry a1, 16
// A - a2
// B - a3
// C - a4
// m - a5
// n - a6
// k - a7
// Ccheck if we can use S3 memory model:
or a12, a5, a6
or a12, a7, a12
movi.n a11, 3
and a12, a12, a11
movi.n a11, 15
or a10, a3, a2
or a10, a10, a4
and a10, a10, a11
or a12, a12, a10
beqz a12, .s3_mmult
// Call Esp32 function
J .dspm_mult_f32_ae32_body
.s3_mmult:
// f0, f1, f2, f3 - multiplication result
// f4, f5, f6, f7 - input for matrix B
// f8, f9, f10,f11- input far matrix A
movi.n a14, 0
slli a12, a7, 2 // a12 = K*4 - step for rows
slli a10, a7, 2 // a10 = K*4 - step for rows
srli a11, a6, 2 // N count
addi.n a11, a11, -1
movi.n a15, 0
mov a13, a3
mov a7, a4
.loop_x_aes3:
movi.n a9, 0
mov a8, a2 // A matirx
.loop_y_aes3:
add a13, a3, a14 // Reload Y pointer to Y11 + A14
EE.LDF.128.IP f11, f10, f9, f8, a8, 16 // Load A values: X11, X12, X13, X14
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y11, Y12, Y13, Y14
mul.s f0, f4, f8 // f0 = X11*Y11
mul.s f1, f5, f8 // f1 = X12*Y11
mul.s f2, f6, f8 // f2 = X13*Y11
mul.s f3, f7, f8 // f3 = X14*Y11
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y21, Y22, Y23, Y24
madd.s f0, f4, f9 // f0 = X11*Y11 + X12*Y21
madd.s f1, f5, f9 // f1 = X11*Y12 + X12*Y22
madd.s f2, f6, f9 // f2 = X11*Y13 + X12*Y23
madd.s f3, f7, f9 // f3 = X11*Y14 + X12*Y24
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y31, Y32, Y33, Y34
madd.s f0, f4, f10 // f0 = X11*Y11 + X12*Y21 + X13*Y31
madd.s f1, f5, f10 // f1 = X11*Y12 + X12*Y22 + X13*Y32
madd.s f2, f6, f10 // f2 = X11*Y13 + X12*Y23 + X13*Y33
madd.s f3, f7, f10 // f3 = X11*Y14 + X12*Y24 + X13*Y34
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y41, Y42, Y43, Y44
madd.s f0, f4, f11 // f0 = X11*Y11 + X12*Y21 + X13*Y31 + X14*Y41
madd.s f1, f5, f11 // f1 = X11*Y12 + X12*Y22 + X13*Y32 + X14*Y42
madd.s f2, f6, f11 // f2 = X11*Y13 + X12*Y23 + X13*Y33 + X14*Y43
madd.s f3, f7, f11 // f3 = X11*Y14 + X12*Y24 + X13*Y34 + X14*Y44
loopnez a11, .loop_end_m_aes3
EE.LDF.128.IP f11, f10, f9, f8, a8, 16 // Load A values: X15, X16, X17, X18
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y51, Y52, Y53, Y54
madd.s f0, f4, f8 // f0 += X15*Y51
madd.s f1, f5, f8 // f1 += X15*Y52
madd.s f2, f6, f8 // f2 += X15*Y53
madd.s f3, f7, f8 // f3 += X15*Y54
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y61, Y62, Y63, Y64
madd.s f0, f4, f9 // f0 += X16*Y61
madd.s f1, f5, f9 // f1 += X16*Y62
madd.s f2, f6, f9 // f2 += X16*Y63
madd.s f3, f7, f9 // f3 += X16*Y64
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y71, Y72, Y73, Y74
madd.s f0, f4, f10 // f0 =
madd.s f1, f5, f10 // f1 =
madd.s f2, f6, f10 // f2 =
madd.s f3, f7, f10 // f3 =
EE.LDF.128.XP f7, f6, f5, f4, a13, a12 // Load B value: Y81, Y82, Y83, Y84
madd.s f0, f4, f11 // f0 =
madd.s f1, f5, f11 // f1 =
madd.s f2, f6, f11 // f2 =
madd.s f3, f7, f11 // f3 =
.loop_end_m_aes3:
EE.STF.128.XP f3, f2, f1, f0, a4, a10 // Store result
addi a9, a9, 1 // Increment loop1 counter
blt a9, a5, .loop_y_aes3
addi.n a7, a7, 16
mov a4, a7
addi.n a14, a14, 16 // B shift for 4
addi a15, a15, 16 // Increment loop1 counter
blt a15, a12, .loop_x_aes3
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //dspm_mult_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 2,580
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_ex_f32_ae32.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_ae32_enabled == 1)
#include "dsps_dotprode_f32_m_ae32.S"
// This is matrix multiplication function for ESP32 processor.
.text
.align 4
.global dspm_mult_ex_f32_ae32
.global .dspm_mult_ex_f32_ae32_body
.type dspm_mult_ex_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dspm_mult_ex_f32_ae32(const float *A, const float *B, float *C, int m, int n, int k, int A_padd, int B_padd, int C_padd);
dspm_mult_ex_f32_ae32:
// A - a2
// B - a3
// C - a4
// m - a5
// n - a6
// k - a7
// A_padding - a14
// B_padding - a15
// C_padding - a8
// a10 = 4
// a9 - counter loop1: 0..m
// a11 - counter loop2: 0..k
// a12 - A
// a13 - B
// a4 - C
entry a1, 16
// Array increment for floating point data should be 4
.dspm_mult_ex_f32_ae32_body:
l32i.n a14, a1, 16 // A_padding
l32i.n a15, a1, 20 // B_padding
l32i.n a8, a1, 24 // C_padding
add a14, a14, a6 // A_step = A_padding + A_cols (n)
add a15, a15, a7 // B_step = B_padding + B_cols (k)
slli a15, a15, 2 // Pointer increment for B (B_step * 4)
movi.n a10, 4 // Increment = 4
movi.n a9, 0 // counter loop1
const.s f3, 0 // Innitial state of accumulator, f3 = 0
.mult_ex_loop1:
movi.n a11, 0 // reset counter for loop2
.mult_ex_loop2:
// Clear initial state of the result register
// a2 - A
// a3 - B
// a6 - n
// a10 - step == 4 bytes
mov a12, a2 // load A
addx4 a13, a11, a3 // loop count to pointer value
mov.s f1, f3 // reset f1
// Calculating dotproduct...
//dotprode_f32_ae32( x1 x2 count step1 step2)
dotprode_f32_ae32 a12, a13, a6, a10, a15;
addi.n a11, a11, 1 // Increment loop2 counter
ssip f1, a4, 4 // Store restul from f1 to memory at a4 and increment a4
// check loop 2
blt a11, a7, .mult_ex_loop2
// check loop 1
addx4 a2, a14, a2 // A += (A_step << 2)
addx4 a4, a8, a4 // output += (C_padding << 2)
addi.n a9, a9, 1 // Increment loop1 counter
blt a9, a5, .mult_ex_loop1
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //dspm_mult_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 3,319
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_ex_f32_arp4.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_arp4_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_ex_f32_arp4
.global .dspm_mult_ex_f32_arp4_body
.type dspm_mult_ex_f32_arp4,@function
// The function implements the following C code:
// esp_err_t dspm_mult_f32_ansi(const float *A, const float *B, float *C, int m, int n, int k, int A_padd, int B_padd, int C_padd)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_ex_f32_arp4:
// A - a2: a0
// B - a3: a1
// C - a4: a2
// m - a5: a3
// n - a6: a4
// k - a7: a5
// a8:a6 = n*4
// a10:t0 = 4
// a9:a7 - counter loop1: 0..m
// a11:t1 - counter loop2: 0..k
// a12:t2 - A
// a13:t3 - B
// a14:t4
// a15:t5
add sp,sp,-16
// Array increment for floating point data should be 4
.dspm_mult_ex_f32_arp4_body:
mv t5, a7
add t4, a6, a4 // A_step = A_padding + A_cols (n)
add t5, t5, a5 // B_step = B_padding + B_cols (k)
slli t5, t5, 2 // Pointer increment for B (B_step * 4)
slli t4, t4, 2 // A_step << 2
lw a6, 16(sp) // C_padding from stack
slli a6, a6, 2 // C_step << 2
li a7, 0 // counter loop1
.dpf_loop1:
li t1, 0 // reset counter for loop2
.dpf_loop2:
// Clear initial state of the result register
// a2 - A
// a3 - B
// a6 - n
// a10 - step == 4 bytes
// a8 - step n*4
mv t2, a0 // load A
slli t3, t1, 2 // loop count to pointer value
add t3, a1, t3 // load A
fmv.w.x fa2,zero // reset fa2
// Calculating dotproduct...
esp.lp.setup 0, a4, .matrix_mul_loop
flw fa0, 0(t2)
add t2, t2, 4
flw fa1, 0(t3)
fmadd.s fa2, fa1, fa0, fa2
.matrix_mul_loop: add t3, t3, t5
fsw fa2, 0(a2)
addi a2, a2, 4 // increment a2 for next time
// check loop 2
addi t1, t1, 1 // Increment loop2 counter
blt t1, a5, .dpf_loop2
// check loop 1
add a0, a0, t4 // A += (A_step << 2)
add a2, a2, a6 // output += (C_padding << 2)
add a7, a7, 1 // Increment loop1 counter
blt a7, a3, .dpf_loop1
// Exit
li a0, 0 // return status ESP_OK
add sp,sp,16
ret
#endif //dspm_mult_ex_f32_arp4_enabled
|
georgevio/IoT-Embedded
| 2,126
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_3x3x3_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_3x3x3_f32_ae32_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_3x3x3_f32_ae32
.type dspm_mult_3x3x3_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mult_3x3x1_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_3x3x3_f32_ae32:
// A - a2
// B - a3
// C - a4
// a5 - 0
// a6 - 3 - internal loop for n
// a7 - 3 - external loop for M
entry a1, 16
movi a5, 0
movi a6, 3
movi a7, 3 // loop ccount
m_loop_3x3x3:
mov a12, a2 // A
mov a14, a4 // output pointer
lsi f12, a3, 0 // B[0][0]
lsi f13, a3, 12 // B[1][0]
lsi f14, a3, 24 // B[2][0]
loopnez a6, loop_mac_3x3x3_end_m_ae32
wfr f0, a5
lsi f2, a12, 0
madd.s f0, f2, f12
lsi f3, a12, 4
madd.s f0, f3, f13
lsi f4, a12, 8
madd.s f0, f4, f14
addi a12, a12, 12
ssi f0, a14, 0
addi a14, a14, 12
loop_mac_3x3x3_end_m_ae32:
addi a3, a3, 4 // increment input pointer B
addi a4, a4, 4
addi a7, a7, -1
bnez a7, m_loop_3x3x3
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //
|
georgevio/IoT-Embedded
| 2,678
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_f32_ae32_enabled == 1)
#include "dsps_dotprode_f32_m_ae32.S"
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_f32_ae32
.global .dspm_mult_f32_ae32_body
.type dspm_mult_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mult_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_f32_ae32:
// A - a2
// B - a3
// C - a4
// m - a5
// n - a6
// k - a7
// a8 = n*4
// a10 = 4
// a9 - counter loop1: 0..m
// a11 - counter loop2: 0..k
// a12 - A
// a13 - B
// a4 - C
entry a1, 16
// Array increment for floating point data should be 4
.dspm_mult_f32_ae32_body:
slli a8, a6, 2 // Pointer increment for A
slli a15,a7, 2 // Pointer increment for B
movi.n a14, 0 // Innitial state of accumulator f1
movi.n a10, 4 // Increment = 4
movi.n a9, 0 // counter loop1
.dpf_loop1:
movi.n a11, 0 // reset counter for loop2
.dpf_loop2:
// Clear initial state of the result register
// a2 - A
// a3 - B
// a6 - n
// a10 - step == 4 bytes
// a8 - step n*4
mov a12, a2 // load A
slli a13, a11, 2 // loop count to pointer value
add.n a13, a3, a13 // load A
wfr f1, a14 // reset f1
// Calculating dotproduct...
dotprode_f32_ae32 a12, a13, a6, a10, a15;
ssi f1, a4, 0 // Store result from f1 to memory at a4
addi a4, a4, 4 // increment a4 for next time
// check loop 2
addi a11, a11, 1 // Increment loop2 counter
blt a11, a7, .dpf_loop2
// check loop 1
add.n a2, a2, a8 // Increment A, A = A[i*n]
addi a9, a9, 1 // Increment loop1 counter
blt a9, a5, .dpf_loop1
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //dspm_mult_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,905
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_4x4x1_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_4x4x1_f32_ae32_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_4x4x1_f32_ae32
.type dspm_mult_4x4x1_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mult_3x3x1_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_4x4x1_f32_ae32:
// A - a2
// B - a3
// C - a4
// a5 - 0
// a6 - 3
entry a1, 16
movi a5, 0
movi a6, 4
lsi f12,a3, 0 // B[0]
lsi f13,a3, 4 // B[1]
lsi f14,a3, 8 // B[2]
lsi f15,a3, 12 // B[3]
loopnez a6, loop_mac_4x4x1_end_m_ae32
wfr f0, a5
lsi f2, a2, 0
madd.s f0, f2, f12
lsi f3, a2, 4
madd.s f0, f3, f13
lsi f4, a2, 8
madd.s f0, f4, f14
lsi f5, a2, 12
madd.s f0, f5, f15
addi a2, a2, 16
ssi f0, a4, 0
addi a4, a4, 4
loop_mac_4x4x1_end_m_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //
|
georgevio/IoT-Embedded
| 2,204
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/float/dspm_mult_4x4x4_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_4x4x4_f32_ae32_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_4x4x4_f32_ae32
.type dspm_mult_4x4x4_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mult_3x3x1_f32_ansi(const float* A, const float* B, float* C, int m, int n, int k)
// {
// for (int i=0 ; i< m ; i++)
// {
// for (int j=0 ; j< k ; j++)
// {
// C[i*k + j] = A[i*n]*B[j];
// for (int s=1; s< n ; s++)
// {
// C[i*k + j] += A[i*n + s]*B[s*k + j];
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_4x4x4_f32_ae32:
// A - a2
// B - a3
// C - a4
// a5 - 0
// a6 - 4 - internal loop for n
// a7 - 4 - external loop for M
entry a1, 16
movi a5, 0
movi a6, 4
movi a7, 4 // loop ccount
m_loop_4x4x4:
mov a12, a2 // A
mov a14, a4 // output pointer
lsi f12, a3, 0 // B[0][0]
lsi f13, a3, 16 // B[1][0]
lsi f14, a3, 32 // B[2][0]
lsi f15, a3, 48 // B[3][0]
loopnez a6, loop_mac_4x4x4_end_m_ae32
wfr f0, a5
lsi f2, a12, 0
madd.s f0, f2, f12
lsi f3, a12, 4
madd.s f0, f3, f13
lsi f4, a12, 8
madd.s f0, f4, f14
lsi f5, a12, 12
madd.s f0, f5, f15
addi a12, a12, 16
ssi f0, a14, 0
addi a14, a14, 16
loop_mac_4x4x4_end_m_ae32:
addi a3, a3, 4 // increment input pointer B
addi a4, a4, 4
addi a7, a7, -1
bnez a7, m_loop_4x4x4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //
|
georgevio/IoT-Embedded
| 1,366
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/fixed/dspm_mult_s16_m_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro dspm_mult_s16_ae32_MxNxN
// A - a2
// B - a3
// C - a4
// m - a5
// n - a6
// k - a7
// shift - stack (a8)
movi a10, 4 // load 4 as a constant
// Check if n >=4 then acceleration is possible and
blt a6, a10, do_dotproduct
// Here we make operations one by one...
movi.n a2, 0 // return status ESP_OK
retw.n
do_dotproduct:
mov a12, a2
mov a13, a3
srli a9, a6, 2 // a9 - count/4 - 1
addi a9, a9, -1
movi.n a10, 0 // load 0 to the a10 to increment second array
dotprod_s16_ae32_full a12, a13, a9, a10, a6
/* Get accumulator */
ssr a6
rsr a2, acchi
rsr a3, acclo
src a2, a2, a3
s16i a2, a4, 0
movi.n a2, 0
movi.n a2, 0 // return status ESP_OK
retw.n
.endm // dspm_mult_s16_ae32_MxNxN
|
georgevio/IoT-Embedded
| 4,361
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/fixed/dspm_mult_s16_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_s16_ae32_enabled == 1)
#include "dsps_dotprod_s16_m_ae32.S"
#include "dspm_mult_s16_m_ae32_vector.S"
//esp_err_t dspm_mult_s16_ae32(const int16_t* A, const int16_t* B, int16_t* C, int m, int n, int k, int shift);
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dspm_mult_s16_ae32
.global .dspm_mult_s16_ae32_body
.type dspm_mult_s16_ae32,@function
dspm_mult_s16_ae32:
// A - a2
// B - a3
// C - a4
// m - a5 - any > 0
// n - a6 - 1,2,3, any
// k - a7 - 1, any
// shift - stack (a8)
// a14 - n*4 - pointer increment
//
entry a1, 80
// ====== process matrices when k == 1 ============
.dspm_mult_s16_ae32_body:
l32i.n a8, a1, 80 // Load shift to the a8 register
// Prepare and load round value
ssr a8 // store shift to ssa
movi a15, 0x7fff
srl a15, a15
neg a8, a8
addi a8, a8, 15
ssr a8 // store shift to ssa
movi a8, 0 // Clear a8
slli a14, a6, 1 // Pointer increment for n
movi.n a10, 2 // Increment = 2
movi.n a9, 0 // initial counter loop1
movi a12, 1
beq a7, a12, vector_mult
// We have normal path with k > 1
// a2, a3, a4 - A,B,C
// a5 - m
// a6 - n
// a7 - k
// a8 - temp
// a9 - temp
// a10- k counter
// a11- m counter
// a12- B
// a13- A
// a14 - pointer increment for n
// a15 - round value
bbsi a6, 0, even_N_samples
// ---------------- for odd N
srli a6, a6, 1 // counter a6 = a6/2. We have to do it only once
slli a7, a7, 1 // counter a7 = a7*2. We have to do it only once
// loop for M
m_loop_mmult:
movi a10, 0 // reset k loop counter
mov a13, a3 // set pointer to the first column
// loop for K
k_loop_mmult:
addi a12, a2, -4 // every loop the same start position
movi a8, 0
wsr a8, acchi
wsr a15, acclo // initialize acc with shifted round value
loopnez a6, .loop_end_mmult // loop for N
.loop_mmult:
ldinc m3, a12
l16si a8, a13, 0
add a13, a13, a7
mula.ad.ll a8, m3
l16si a8, a13, 0
add a13, a13, a7
mula.ad.lh a8, m3
.loop_end_mmult:
rsr a8, acchi
rsr a9, acclo
src a8, a8, a9
s16i a8, a4, 0
addi a4, a4, 2
// check and increment for K
addi a10, a10, 2
add a13, a3, a10 // we shift collumn
bne a10, a7, k_loop_mmult
// Check and increment for M
add a2, a2, a14 // move to the next raw
addi a5, a5, -1
bnez.n a5, m_loop_mmult
movi.n a2, 0 // return status ESP_OK
retw.n
even_N_samples:
// ---------------- for odd N
slli a7, a7, 1 // counter a7 = a7*2. We have to do it only once
// loop for M
m_loop_mmult_even:
movi a10, 0 // reset k loop counter
mov a13, a3 // set pointer to the first column
// loop for K
k_loop_mmult_even:
mov a12, a2 // every loop the same start position
movi a8, 0
wsr a8, acchi
wsr a15, acclo // initialize acc with shifted round value
loopnez a6, .loop_end_mmult_even // loop for N
.loop_mmult_even:
l16si a9, a12, 0
l16si a8, a13, 0
addi a12, a12, 2
add a13, a13, a7
mula.aa.ll a8, a9
.loop_end_mmult_even:
rsr a8, acchi
rsr a9, acclo
src a8, a8, a9
s16i a8, a4, 0
addi a4, a4, 2
// check and increment for K
addi a10, a10, 2
add a13, a3, a10 // we shift collumn
bne a10, a7, k_loop_mmult_even
// Check and increment for M
add a2, a2, a14 // move to the next raw
addi a5, a5, -1
bnez.n a5, m_loop_mmult_even
movi.n a2, 0 // return status ESP_OK
retw.n
// The path where n > 1
vector_mult:
dspm_mult_s16_m_ae32_vector;
#endif // dspm_mult_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 3,691
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/fixed/dspm_mult_s16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_s16_arp4_enabled == 1)
// This is matrix multipliction function for Risc-V processor core.
.text
.align 4
.global dspm_mult_s16_arp4
.global dspm_mult_s16_ansi
.global .dspm_mult_s16_arp4_body
.type dspm_mult_s16_arp4,@function
// The function implements the following C code:
// esp_err_t dspm_mult_f32_ansi(const int16_t *A, const int16_t *B, int16_t *C, int m, int n, int k, int shift)
// {
// int final_shift = shift - 15;
// for (int i = 0 ; i < m ; i++) {
// for (int j = 0 ; j < k ; j++) {
// // This code also could be used
// //dsps_dotprode_f32_ae32(&A[i*n],&B[j],&C[i*k + j],n,1,n);
// long long acc = 0x7fff >> shift;
// for (int s = 0; s < n ; s++) {
// acc += (int32_t)A[i * n + s] * (int32_t)B[s * k + j];
// }
// if (final_shift > 0) {
// C[i * k + j] = (acc << final_shift);
// } else {
// C[i * k + j] = (acc >> (-final_shift));
// }
// }
// }
// return ESP_OK;
// }
dspm_mult_s16_arp4:
// A - a0
// B - a1
// C - a2
// m - a3
// n - a4
// k - a5
// shift - a6
// a7 - counter loop1: 0..m
// t1 - counter loop2: 0..k
// t0 - counter loop3: 0..n
// x25(s9) - matrix step for input2
// x24(s8) - pointer to current B
// x29(t4) - pointer to initial B
// x30(t5) - pointer to A
// x31(t6) = 2 for increment....
// x26(s10)- final_shift
or t0, a3, a4
or t0, t0, a5
andi t0, t0, 0x7
beqz t0, .dspm_mult_s16_arp4_body
j dspm_mult_s16_ansi
//ret
.dspm_mult_s16_arp4_body:
add sp,sp,-16
sw s8, 4(sp)
sw s9, 8(sp)
sw s10, 12(sp)
mv t0, a4
li a7, 0 // counter loop1
slli x25, a5, 1 // step = step*2
li x31, 2
// final_shift = shift - 15
add x26, a6, -15
.dpf_loop1: // loop for m
li t1, 0 // reset counter for loop2
mv x29, a1
.dpf_loop2: // loop for k
mv x30, a0
mv x24, x29 // load B
// Calculating dotproduct...
esp.zero.qacc // qacc = 0;
esp.vldbc.16.xp q0, x30, x31 // q0 = a[mx..mx]
esp.vld.128.xp q1, x24, x25 // q1 = b[x0..x7],
esp.lp.setup 0, t0, .matrix_mul_loop
esp.vmulas.s16.qacc.ldbc.incp q0,x30, q0,q1
.matrix_mul_loop: esp.vld.128.xp q1,x24,x25
esp.srcmb.s16.qacc q2, x26, 0 // q2 = qacc >> shift
esp.vst.128.ip q2, a2, 16 // save k0..k7
add x29,x29, 16
// check loop 2
addi t1, t1, 8 // Increment loop2 counter
blt t1, a5, .dpf_loop2
add x30, x30, -2
mv a0, x30 //
// check loop 1
add a7, a7, 1 // Increment loop1 counter
blt a7, a3, .dpf_loop1
// Exit
mv a0, a6 // return status ESP_OK
lw s10, 12(sp)
lw s9, 8(sp)
lw s8, 4(sp)
add sp,sp,16
ret
#endif //dspm_mult_s16_arp4_enabled
|
georgevio/IoT-Embedded
| 2,322
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/fixed/dspm_mult_s16_m_ae32_vector.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro dspm_mult_s16_m_ae32_vector
// m - a5 - any > 0
// n - a6 - 1,2,3, any
// k - a7 - 1, any
// Define path for n < 4
movi a7, 4
blt a6, a7, small_process_loop // jump for n < 4
srli a7, a6, 2
addi a7, a7, -1
mmultv_loop1:
wsr a8, acchi
wsr a15, acclo // initialize acc with shifted round value
// Clear initial state of the result register
// a2 - A
// a3 - B
// a4 - C
// a6 - n
// a7 - n/4 - 1
// a8 - 0
// a15- 0x7fff>>shift
mov a12, a2 // load A
mov a13, a3 // Load B
dotprod_s16_ae32_full a12, a13, a7, a6
// check loop 1
/* Get accumulator */
rsr a12, acchi
rsr a13, acclo
src a12, a12, a13
s16i a12, a4, 0
addi a4, a4, 2
add.n a2, a2, a14 // Increment A, A = A[i*n]
addi a9, a9, 1 // Increment loop1 counter
blt a9, a5, mmultv_loop1
movi.n a2, 0 // return status ESP_OK
retw.n
small_process_loop:
wsr a8, acchi
wsr a15, acclo // initialize acc with shifted round value
mov a12, a2 // load A
mov a13, a3 // Load B
addi a12, a12, -4 // To arrange fist pointer
addi a13, a13, -4 // To arrange fist pointer
bbci a6, 1, .mod2chk_short
ldinc m0, a12
ldinc m2, a13
mula.dd.hh m0, m2
mula.dd.ll m0, m2
.mod2chk_short:
bbci a6, 0, .mod1chk_short
ldinc m0, a12
ldinc m2, a13
mula.dd.ll m0, m2
.mod1chk_short:
// check loop 1
/* Get accumulator */
rsr a12, acchi
rsr a13, acclo
src a12, a12, a13
s16i a12, a4, 0
addi a4, a4, 2
add.n a2, a2, a14 // Increment A, A = A[i*n]
addi a9, a9, 1 // Increment loop1 counter
blt a9, a5, small_process_loop
movi.n a2, 0 // return status ESP_OK
retw.n
.endm // dspm_mult_s16_m_ae32_vector
|
georgevio/IoT-Embedded
| 4,887
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mul/fixed/dspm_mult_s16_aes3.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspm_mult_platform.h"
#if (dspm_mult_s16_aes3_enabled == 1)
#include "dsps_dotprod_s16_m_ae32.S"
#include "dspm_mult_s16_m_ae32_vector.S"
//esp_err_t dspm_mult_s16_ae32(const int16_t* A, const int16_t* B, int16_t* C, int m, int n, int k, int shift);
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.literal_position
.literal .LC0_1_38, 32767
.literal .LC1_1_39, 16383
.global dspm_mult_s16_aes3
.global .dspm_mult_s16_ae32_body
.type dspm_mult_s16_aes3,@function
dspm_mult_s16_aes3:
entry a1,80 #
movi.n a10, 7
and a10, a10, a7
beqz a10, .dspm_mult_s16_aes3_body
// Call Esp32 function
J .dspm_mult_s16_ae32_body
.dspm_mult_s16_aes3_body:
mov.n a10,a4 # [0]
mov.n a11,a5 # [1]
l32i a5,a1,80 # [2] id:77 shift+0x0
s32i.n a3,a1,32 # [3] gra_spill_temp_0
bltz a5,.Lt_0_6146 # [4]
#.LBB3_dspm_mult_s16_aes3: # 0x13
l32r a9,.LC0_1_38 # [0]
ssr a5 # [1]
sra a9,a9 # [2]
.LBB23_dspm_mult_s16_aes3: # 0x1c
s16i a9,a1,0 # [0] id:78 round_data_64+0x0
s16i a9,a1,2 # [1] id:78 round_data_64+0x0
s16i a9,a1,4 # [2] id:78 round_data_64+0x0
s16i a9,a1,6 # [3] id:78 round_data_64+0x0
s16i a9,a1,8 # [4] id:78 round_data_64+0x0
s16i a9,a1,10 # [5] id:78 round_data_64+0x0
s16i a9,a1,12 # [6] id:78 round_data_64+0x0
s16i a9,a1,14 # [7] id:78 round_data_64+0x0
blti a11,1,.Lt_0_7426 # [0]
mov.n a13,a2 # [0]
slli a4,a7,1 # [1]
mov.n a12,a1 # [2]
l32i.n a14,a1,32 # [3] gra_spill_temp_0
movi.n a15,15 # [4]
movi.n a8,0 # [5]
slli a9,a6,1 # [6]
s32i.n a9,a1,36 # [7] gra_spill_temp_1
s32i.n a8,a1,44 # [8] gra_spill_temp_3
sub a15,a15,a5 # [9]
addi.n a8,a7,7 # [10]
movgez a8,a7,a7 # [11]
srai a8,a8,3 # [12]
s32i.n a8,a1,40 # [13] gra_spill_temp_2
slli a8,a8,4 # [14]
add.n a14,a14,a8 # [15]
.Lt_0_7938: # 0x5d
l32i.n a8,a1,40 # [0] gra_spill_temp_2
beqz.n a8,.Lt_0_8194 # [2]
l32i.n a7,a1,32 # [0] gra_spill_temp_0
mov.n a2,a13 # [1]
.Lt_0_8706: # 0x65
ee.ldqa.u16.128.ip a12,0 # [0] id:80
ee.vldbc.16.ip q1,a2,2 # [1] id:79
mov.n a3,a7 # [2]
ee.vld.128.xp q0,a3,a4 # [3] id:81
addi a7,a7,16 # [4]
blti a6,1,.Lt_0_8962 # [5]
srai a5,a6,1 # [0]
bbci a6,0,.LBB68_dspm_mult_s16_aes3 # [1]
ee.vmulas.s16.qacc.ldbc.incp q1,a2,q0,q1 # [0] id:82
ee.vld.128.xp q0,a3,a4 # [1] id:83
.LBB68_dspm_mult_s16_aes3: # 0x82
loopgtz a5,.LBB74_dspm_mult_s16_aes3 # [0]
.LBB64_dspm_mult_s16_aes3: # 0x85
ee.vld.128.xp q2,a3,a4 # [0*II+0] id:83
ee.vmulas.s16.qacc.ldbc.incp q1,a2,q0,q1 # [0*II+1] id:82
ee.vld.128.xp q0,a3,a4 # [0*II+2] id:83
ee.vmulas.s16.qacc.ldbc.incp q1,a2,q2,q1 # [0*II+3] id:82
.LBB74_dspm_mult_s16_aes3: # 0x91
.Lt_0_8962: # 0x91
mov.n a2,a13 # [0]
ee.srcmb.s16.qacc q0,a15,1 # [1]
ee.vst.128.ip q0,a10,16 # [2] id:85
bne a7,a14,.Lt_0_8706 # [3]
.Lt_0_8194: # 0x9c
l32i.n a8,a1,36 # [0] gra_spill_temp_1
l32i.n a9,a1,44 # [1] gra_spill_temp_3
add.n a13,a13,a8 # [2]
addi.n a9,a9,1 # [3]
s32i.n a9,a1,44 # [4] gra_spill_temp_3
bne a11,a9,.Lt_0_7938 # [5]
.Lt_0_7426: # 0xa9
movi.n a2,0 # [0]
retw.n # [1]
.Lt_0_6146: # 0xad
l32r a9,.LC1_1_39 # [0]
ssr a5 # [1]
sra a9,a9 # [2]
j .LBB23_dspm_mult_s16_aes3 # [3]
#endif // dspm_mult_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 1,818
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/mulc/float/dspm_mulc_f32_ae32.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_mulc_platform.h"
#if (dspm_mulc_f32_ae32_enabled == 1)
// This is a mul function for sub-matrices for ESP32 processor
.text
.align 4
.global dspm_mulc_f32_ae32
.type dspm_mulc_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_mulc_f32_ansi(const float *input, float *output, float C, int rows, int cols, int padd_in, int padd_out, int step_in, int step_out);
dspm_mulc_f32_ae32:
// input - a2
// output - a3
// C - a4
// rows - a5
// cols - a6
// padd_in - a7
// padd_out - a8
// step_in - a9
// step_out - a10
entry a1, 16
l32i.n a8, a1, 16 // padd_out
l32i.n a9, a1, 20 // step_in
l32i.n a10, a1, 24 // step_out
slli a9, a9, 2 // a9 - step_in << 2
slli a10, a10, 2 // a10 - step_out << 2
wfr f0, a4 // a4 - load to the f0
.outer_loop_mulc_f32_ae32:
loopnez a6, .loop_mulc_f32_ae32
lsxp f1, a2, a9 // load input to f1, increment input (input_ptr+=step_in)
mul.s f2, f0, f1 // f2 = f0 * f1
ssxp f2, a3, a10 // save result f2 to output a3, increment output (output_ptr+=step_out)
.loop_mulc_f32_ae32:
addx4 a2, a7, a2 // input1_ptr += (padd_in << 2);
addx4 a3, a8, a3 // output_ptr += (padd_out << 2);
addi.n a5, a5, -1 // rows - 1
bnez a5, .outer_loop_mulc_f32_ae32
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dspm_mulc_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,133
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/sub/float/dspm_sub_f32_ae32.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_sub_platform.h"
#if (dspm_sub_f32_ae32_enabled == 1)
// This is an sub function for sub-matrices for ESP32 processor
.text
.align 4
.global dspm_sub_f32_ae32
.type dspm_sub_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_sub_f32_ansi(const float *input1, const float *input2, float *output, int rows, int cols, int padd1, int padd2, int padd_out, int step1, int step2, int step_out);
dspm_sub_f32_ae32:
// input1 - a2
// input2 - a3
// output - a4
// rows - a5
// cols - a6
// padd1 - a7
// padd2 - a8
// padd_out - a9
// step1 - a10
// step2 - a11
// step_out - a12
entry a1, 16
l32i.n a8, a1, 16 // padd2
l32i.n a9, a1, 20 // padd_out
l32i.n a10, a1, 24 // step1
l32i.n a11, a1, 24 // step2
l32i.n a12, a1, 24 // step_out
slli a10, a10, 2 // a10 - step1 << 2
slli a11, a11, 2 // a11 - step2 << 2
slli a12, a12, 2 // a12 - step_out << 2
.outer_loop_sub_f32_ae32:
loopnez a6, .loop_sub_f32_ae32
lsxp f0, a2, a10 // load input1 to f0, increment input1 (input1_ptr+=step1)
lsxp f1, a3, a11 // load input2 to f1, increment input2 (input2_ptr+=step2)
sub.s f2, f0, f1 // f2 = f0 - f1
ssxp f2, a4, a12 // save result f2 to output a4, increment output (output_ptr+=step_out)
.loop_sub_f32_ae32:
addx4 a3, a8, a3 // input2_ptr += (padd2 << 2);
addx4 a2, a7, a2 // input1_ptr += (padd1 << 2);
addx4 a4, a9, a4 // output_ptr += (padd_out << 2);
addi.n a5, a5, -1 // rows - 1
bnez a5, .outer_loop_sub_f32_ae32
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dspm_sub_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,133
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/matrix/add/float/dspm_add_f32_ae32.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dspm_add_platform.h"
#if (dspm_add_f32_ae32_enabled == 1)
// This is an add function for sub-matrices for ESP32 processor
.text
.align 4
.global dspm_add_f32_ae32
.type dspm_add_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dspm_add_f32_ansi(const float *input1, const float *input2, float *output, int rows, int cols, int padd1, int padd2, int padd_out, int step1, int step2, int step_out);
dspm_add_f32_ae32:
// input1 - a2
// input2 - a3
// output - a4
// rows - a5
// cols - a6
// padd1 - a7
// padd2 - a8
// padd_out - a9
// step1 - a10
// step2 - a11
// step_out - a12
entry a1, 16
l32i.n a8, a1, 16 // padd2
l32i.n a9, a1, 20 // padd_out
l32i.n a10, a1, 24 // step1
l32i.n a11, a1, 24 // step2
l32i.n a12, a1, 24 // step_out
slli a10, a10, 2 // a10 - step1 << 2
slli a11, a11, 2 // a11 - step2 << 2
slli a12, a12, 2 // a12 - step_out << 2
.outer_loop_add_f32_ae32:
loopnez a6, .loop_add_f32_ae32
lsxp f0, a2, a10 // load input1 to f0, increment input1 (input1_ptr+=step1)
lsxp f1, a3, a11 // load input2 to f1, increment input2 (input2_ptr+=step2)
add.s f2, f0, f1 // f2 = f0 + f1
ssxp f2, a4, a12 // save result f2 to output a4, increment output (output_ptr+=step_out)
.loop_add_f32_ae32:
addx4 a3, a8, a3 // input2_ptr += (padd2 << 2);
addx4 a2, a7, a2 // input1_ptr += (padd1 << 2);
addx4 a4, a9, a4 // output_ptr += (padd_out << 2);
addi.n a5, a5, -1 // rows - 1
bnez a5, .outer_loop_add_f32_ae32
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dspm_add_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 5,412
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/support/cplx_gen/dsps_cplx_gen.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_cplx_gen_platform.h"
#if (dsps_cplx_gen_aes3_enbled || dsps_cplx_gen_ae32_enbled)
// This is a Complex signal generator for ESP32 processor.
.text
.align 4
.global dsps_cplx_gen_ae32
.type dsps_cplx_gen_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_cplx_gen_ae32(cplx_sig_t *cplx_gen, void *output, int32_t len);
dsps_cplx_gen_ae32:
// Input params Variables float Variables fixed
//
// cplx_gen - a2 fr - f0 lut - a5
// output - a3 one_const - f1 lut_len - a6
// len - a4 lut_len_f - f2 sin_pos - a7
// ph_f - f3 cos_pos - a8
// sin_pos_f - f4 sin_to_cos - a9
// ph_floor - a10
// modulo - a11
entry a1, 32
l32i a5, a2, 0 // a5 - lut
l32i a6, a2, 4 // a6 - lut_len
lsi f0, a2, 8 // f0 - fr
lsi f3, a2, 12 // f3 - ph_f (phase increment)
const.s f1, 1 // f1 - constant 1
float.s f2, a6, 0 // f2 - lut_len_f
srli a9, a6, 2 // a9 - sin_to_cos = lut_len / 4
addi a11, a6, -1 // a11 - modulo = lut_len - 1
l32i a15, a2, 16 // a15 - d_type
beqz a15, _s16_fixed
// F32 floating point
loopnez a4, ._main_loop_float
floor.s a10, f3, 0 // turncate wiht rounding towards -infinity
// branch if ph_floor is greater than 0
bgez a10, _ph_check_low_float
add.s f3, f3, f1 // f3 = f3 - f1 (ph_f + 1)
floor.s a10, f3, 0 // turncate wiht rounding towards -infinity
_ph_check_low_float:
// branch if ph_ceil is lower than 2 (floored to 1)
blti a10, 1, _ph_check_great_float
sub.s f3, f3, f1 // f3 = f3 - f1 (ph_f - 1)
_ph_check_great_float:
mul.s f4, f3, f2 // sin_pos_f = ph_f * lut_len
trunc.s a7, f4, 0 // truncate sin_pos_f to sin_pos
add a8, a7, a9 // cos_pos (a8) = sin_pos(a7) + sin_to_cos(a9)
and a8, a8, a11 // cos_pos = cos_pos & modulo (lut_len - 1)
slli a8, a8, 2 // set index of the LUT (4 x cos_pos)
slli a7, a7, 2 // set index of the LUT (4 x sin_pos)
lsx f14, a5, a7 // load sin LUT value form *lut
lsx f15, a5, a8 // load cos LUT value form *lut
ssi f15, a3, 0 // save cos LUT value to the output, offset 0
ssi f14, a3, 4 // save sin LUT value to the output, offset 4
add.s f3, f3, f0 // ph_f += fr
addi.n a3, a3, 8 // increase the output pointer (2 x f32)
._main_loop_float:
movi.n a2, 0
retw.n
// Q15 fixed point
_s16_fixed:
loopnez a4, ._main_loop_fixed
floor.s a10, f3, 0 // turncate wiht rounding towards -infinity
// branch if ph_floor is greater than 0
bgez a10, _ph_check_low_fixed
add.s f3, f3, f1 // f3 = f3 - f1 (ph_f + 1)
floor.s a10, f3, 0 // turncate wiht rounding towards -infinity
_ph_check_low_fixed:
// branch if ph_ceil is lower than 2 (floored to 1)
blti a10, 1, _ph_check_great_fixed
sub.s f3, f3, f1 // f3 = f3 - f1 (ph_f - 1)
_ph_check_great_fixed:
mul.s f4, f3, f2 // sin_pos_f = ph_f * lut_len
trunc.s a7, f4, 0 // truncate sin_pos_f to sin_pos
add a8, a7, a9 // cos_pos (a8) = sin_pos(a7) + sin_to_cos(a9)
and a8, a8, a11 // cos_pos = cos_pos & modulo (lut_len - 1)
addx2 a15, a8, a5 // get cos index of the LUT (*lut + 2 x cos_pos)
addx2 a13, a7, a5 // get sin index of the LUT (*lut + 2 x sin_pos)
l16si a14, a15, 0 // load cos LUT value from *lut
l16si a12, a13, 0 // load sin LUT value from *lut
s16i a14, a3, 0 // save cos LUT value to the output (a3), offset 0
s16i a12, a3, 2 // save sin LUT value to the output (a3), offset 2
add.s f3, f3, f0 // ph_f += fr
addi.n a3, a3, 4 // increase the output pointer (2 x s16)
._main_loop_fixed:
movi.n a2, 0
retw.n
#endif // (dsps_cplx_gen_aes3_enbled || dsps_cplx_gen_ae32_enbled)
|
georgevio/IoT-Embedded
| 13,626
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/support/mem/esp32s3/dsps_memset_aes3.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_mem_platform.h"
#if dsps_mem_aes3_enbled
// This is memory access for ESP32S3 processor.
.text
.align 4
.global dsps_memset_aes3
.type dsps_memset_aes3,@function
// The function implements the following C code:
// void *dsps_memset_aes3(void *arr_dest, uint8_t set_val, size_t set_size);
// Input params Variables
//
// arr_dest - a2 loop_len - a5
// set_val - a3 p_arr_dest - a8
// set_size - a4 8_bit_set - a7
// 16_bit_set - a9
// 32_bit_set - a10
// align_mask - a11
/*
esp32s3 optimized memset function works with both, aligned and unaligned data.
arr_dest aligned - _main_loop, 16 bytes in one loop, only aligned data
- Check modulos to finish copying remaining data outside of the cycle
- Modulo 8 - S3 instruction for aligned data, the rest of the modulos are generic
arr_dest unaligned - First, use generic instructions to align the arr_dest data (keep increasing
the arr_dest pointer until the pointer is aligned)
- Once arr_dest is aligned treat the rest of the data as aligned, same as above
if the set_size is less than 16, jump to _less_than_16 label and set data without any s3 instructions or cycles
*/
#define MEMSET_OPTIMIZED 1 // Use optimized memset or ansi memset
#define TIE_ENABLE 0 // Put a dummy TIE instruction to ANSI memset to induce TIE context saving
dsps_memset_aes3:
#if MEMSET_OPTIMIZED
entry a1, 32
mov a8, a2 // a8 - save arr_dest pointer
blti a4, 16, _less_than_16 // set_size shorter than 16
movi.n a7, 0xff // 0xff one-byte mask
movi.n a11, 0xf // 0xf alignment mask
and a7, a7, a3 // mask upper 24 bits of set_val a3
bnez.n a7, _non_zero_constant
ee.zero.q q0 // initialize q0 to zero
movi.n a9, 0 // initialize (16_bit_set) a9 to zero
movi.n a10, 0 // initialize (32_bit_set) a10 to zero
j _q_reg_prepared
_non_zero_constant:
// Fill q register
slli a6, a7, 8 // a6 - (masked)set_val << 8
or a9, a6, a7 // a9 - (masked)set_val << 8 + (masked)set_val
// a9 - 16-bit set
slli a15, a9, 16 // a15 - a9 << 16
or a10, a9, a15 // broadcast 8 bits from set_val a3 to 32 bits
// a10 - 32-bit set
ee.movi.32.q q0, a10, 0 // fill q0 register from a10 by 32 bits
ee.movi.32.q q0, a10, 1
ee.movi.32.q q0, a10, 2
ee.movi.32.q q0, a10, 3
_q_reg_prepared:
// alignment check
and a15, a11, a2 // 0xf (alignment mask) AND arr_dest pointer
beqz a15, _arr_dest_aligned // branch if a15 equals to zero
movi.n a14, 16 // a14 - 16
sub a15, a14, a15 // a15 = 16 - unalignment
sub a4, a4, a15 // len = len - (16 - unalignment)
// keep setting until arr_dest is aligned
// Check modulo 8 of the unalignment, if - then set 8 bytes
bbci a15, 3, _aligning_mod_8_check // branch if 3-rd bit of unalignment a15 is clear
s32i.n a10, a2, 0 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
s32i.n a10, a2, 4 // save 32 bits from a10 to arr_dest a2, offset 4 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 8 bytes
_aligning_mod_8_check:
// Check modulo 4 of the unalignment, if - then set 4 bytes
bbci a15, 2, _aligning_mod_4_check // branch if 2-nd bit unalignment a15 is clear
s32i.n a10, a2, 0 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_aligning_mod_4_check:
// Check modulo 2 of the unalignment, if - then set 2 bytes
bbci a15, 1, _aligning_mod_2_check // branch if 1-st bit unalignment a15 is clear
s16i a9, a2, 0 // save 16 bits from a9 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_aligning_mod_2_check:
// Check modulo 1 of the unalignment, if - then copy 1 byte
bbci a15, 0, _arr_dest_aligned // branch if 0-th bit unalignment a15 is clear
s8i a7, a2, 0 // save 8 bits from a7 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 1 // increment arr_dest pointer by 1 byte
_arr_dest_aligned:
// Calculate main loop_len
srli a5, a4, 4 // a5 - loop_len = set_size / 16
// Main loop
loopnez a5, ._main_loop // 16 bytes in one loop
ee.vst.128.ip q0, a2, 16 // store 16 bytes from q0 to arr_dest a2
._main_loop:
// Check modulo 8 of the set_size, if - then set 8 bytes
bbci a4, 3, _aligned_mod_8_check // branch if 3-rd bit of set_size a4 is clear
ee.vst.l.64.ip q0, a2, 8 // save lower 64 bits from q0 to arr_dest a2, increase arr_dest pointer by 8 bytes
_aligned_mod_8_check:
// Check modulo 4 of the set_size, if - then set 4 bytes
bbci a4, 2, _aligned_mod_4_check // branch if 2-nd bit of set_size a4 is clear
s32i.n a10, a2, 0 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_aligned_mod_4_check:
// Check modulo 2 of the set_size, if - then set 2 bytes
bbci a4, 1, _aligned_mod_2_check // branch if 1-st bit of set_size a4 is clear
s16i a9, a2, 0 // save 16 bits from a9 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_aligned_mod_2_check:
// Check modulo 1 of the set_size, if - then set 1 byte
bbci a4, 0, _aligned_mod_1_check // branch if 0-th bit of set_size a4 is clear
s8i a7, a2, 0 // save 8 bits from a7 to arr_dest a2, offset 0 bytes
_aligned_mod_1_check:
mov a2, a8 // copy the initial arr_dest pointer from a8 to arr_dest a2
retw.n // return
_less_than_16:
// make 16-byte set_val
slli a6, a3, 8 // a6 - a3 (set_val) << 8
or a7, a6, a3 // a7 - a3 (set_val) << 8 + a3 (set_val)
// Check modulo 8 of the set_size, if - then set 8 bytes
bbci a4, 3, _less_than_16_mod_8_check // branch if 3-rd bit of set_size a4 is clear
s16i a7, a2, 0 // save 16 bits from a7 to arr_dest a2, offset 0 bytes
s16i a7, a2, 2 // save 16 bits from a7 to arr_dest a2, offset 2 bytes
s16i a7, a2, 4 // save 16 bits from a7 to arr_dest a2, offset 4 bytes
s16i a7, a2, 6 // save 16 bits from a7 to arr_dest a2, offset 6 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 8 bytes
_less_than_16_mod_8_check:
// Check modulo 4 of the set_size, if - then set 4 bytes
bbci a4, 2, _less_than_16_mod_4_check // branch if 2-nd bit of set_size a4 is clear
s16i a7, a2, 0 // save 16 bits from a7 to arr_dest a2, offset 0 bytes
s16i a7, a2, 2 // save 16 bits from a7 to arr_dest a2, offset 2 bytes
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_less_than_16_mod_4_check:
// Check modulo 2 of the set_size, if - then set 2 bytes
bbci a4, 1, _less_than_16_mod_2_check // branch if 1-st bit of set_size a4 is clear
s16i a7, a2, 0 // save 16 bits from a7 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_less_than_16_mod_2_check:
// Check modulo 1 of the set_size, if - then set 1 byte
bbci a4, 0, _less_than_16_mod_1_check // branch if 0-th bit of set_size a4 is clear
s8i a3, a2, 0 // save 8 bits from a3 to arr_dest a2, offset 0 bytes
_less_than_16_mod_1_check:
mov a2, a8 // copy the initial arr_dest pointer from a8 to arr_dest a2
retw.n // return
#else // MEMSET_OPTIMIZED
// ansi version of the memset (without TIE instructions) for testing purposes
entry a1, 32
mov a8, a2 // a8 - save arr_dest pointer
movi.n a7, 0xff // 0xff one-byte mask
and a7, a7, a3 // mask upper 24 bits of a3
slli a6, a7, 8 // a6 - (masked)set_val << 8
or a9, a6, a7 // a9 - (masked)set_val << 8 + (masked)set_val
// a9 - 16-bit set
slli a15, a9, 16 // a15 - a9 << 16
or a10, a9, a15 // broadcast 8 bits from a3 to 32 bits
srli a5, a4, 4 // a5 - loop_len = arr_len / 16
// Run main loop which sets 16 bytes in one loop run
loopnez a5, ._ansi_loop
s32i.n a10, a2, 0 // save 32 bits from a15 to arr_dest a2
s32i.n a10, a2, 4 // save 32 bits from a14 to arr_dest a2
s32i.n a10, a2, 8 // save 32 bits from a14 to arr_dest a2
s32i.n a10, a2, 12 // save 32 bits from a14 to arr_dest a2
addi.n a2, a2, 16 // increment arr_dest pointer by 8 bytes
._ansi_loop:
// Finish the remaining bytes out of the loop
// Check modulo 8 of the arr_len, if - then set 8 bytes
bbci a4, 3, _mod_8_check // branch if 2-nd bit of arr_len is clear
s32i.n a10, a2, 0 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
s32i.n a10, a2, 4 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 4 bytes
_mod_8_check:
// Check modulo 4 of the arr_len, if - then set 4 bytes
bbci a4, 2, _mod_4_check // branch if 2-nd bit of arr_len is clear
s32i.n a10, a2, 0 // save 32 bits from a10 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_mod_4_check:
// Check modulo 2 of the arr_len, if - then set 2 bytes
bbci a4, 1, _mod_2_check // branch if 1-st bit of arr_len is clear
s16i a9, a2, 0 // save 16 bits from a7 to arr_dest a2, offset 0 bytes
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_mod_2_check:
// Check modulo 1 of the arr_len, if - then set 1 byte
bbci a4, 0, _mod_1_check // branch if 0-th bit of arr_len is clear
s8i a7, a2, 0 // save 8 bits from a3 to arr_dest a2, offset 0 bytes
_mod_1_check:
// if arr_len is shorter than 16, skip adding TIE instruction, to fix the panic handler before the main_app() loads
blti a4, 16, _less_than_16_1 // set_size shorter than 16, to fix panic handler before main_app() load
#if TIE_ENABLE // put dummy TIE instruction to induce TIE context saving
ee.zero.qacc // initialize q0 to zero
#else // TIE_ENABLE
nop // compensate one cycle, when TIE is disabled to get the same benchmark value
#endif // TIE_ENABLE
_less_than_16_1:
mov a2, a8 // copy the initial arr_dest pointer from a8 to arr_dest a2
retw.n // return
#endif // MEMSET_OPTIMIZED
#endif // dsps_mem_aes3_enbled
|
georgevio/IoT-Embedded
| 20,165
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/support/mem/esp32s3/dsps_memcpy_aes3.S
|
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_mem_platform.h"
#if dsps_mem_aes3_enbled
// This is memory access for ESP32S3 processor.
.text
.align 4
.global dsps_memcpy_aes3
.type dsps_memcpy_aes3,@function
// The function implements the following C code:
// void *dsps_memcpy_aes3(void *arr_dest, const void *arr_src, size_t arr_len);
// Input params Variables
//
// arr_dest - a2 loop_len - a5, a6
// arr_src - a3 p_arr_des - a7
// arr_len - a4 div_48 - a8
// align_mask - a9
/*
esp32s3 optimized memcpy function works with both, aligned and unaligned data.
arr_dest aligned --> - _main_loop_aligned, 32 bytes in one run through the cycle, only aligned data
arr_src aligned / - Check modulos to finish copying the remaining data outside of the cycle
- Modulo 8 and 16 - S3 instructions for aligned data, the rest of the modulos are generic
arr_dest aligned ---> - _main_loop_unaligned, 48 bytes of source unaligned data in one run through the cycle,
arr_src unaligned / (the destination must always be aligned)
- Check modulos to finish copying remaining data outside of the cycle
- Modulo 32 and 16 - S3 instructions for unaligned data, the rest of the modulos are generic
arr_dest unaligned -> - First, use generic instructions to align the arr_dest data (keep increasing
arr_src aligned / the arr_dest pointer until the pointer is aligned)
- Once arr_dest is aligned treat the rest of the data as:
either both aligned (if arr_src happens to be aligned after the arr_dest aligning),
or as arr_dest aligned and arr_src unaligned
- Continue as mentioned above
arr_dest unaligned -> - Very same approach as with arr_dest unaligned and arr_src aligned
arr_src unaligned /
if the arr_len is less than 16, jump to _less_than_16 label and copy data without any s3 instructions or cycles
*/
#define MEMCPY_OPTIMIZED 1 // Use optimized memcpy or ANSI memcpy
#define TIE_ENABLE 0 // Put a dummy TIE instruction to the ANSI memcpy to induce TIE context saving
dsps_memcpy_aes3:
#if MEMCPY_OPTIMIZED
// S3 optimized version of the memcpy (with TIE instrucstions)
entry a1, 32
mov a7, a2 // a7 - save arr_dest pointer
blti a4, 16, _less_than_16
// arr_dest alignment check
movi.n a9, 0xf // 0xf alignment mask
and a13, a9, a2 // 0xf AND arr_dest pointer
beqz a13, _arr_dest_aligned
movi.n a14, 16 // a14 - 16
sub a13, a14, a13 // a13 = 16 - unalignment
sub a4, a4, a13 // len = len - (16 - unalignment)
// Aligning the arr_dest
// keep copying until arr_dest is aligned
// Check modulo 8 of the unalignment, if - then copy 8 bytes
bbci a13, 3, _aligning_mod_8_check // branch if 3-rd bit of unalignment a13 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15, offset 0
l32i.n a14, a3, 4 // load 32 bits from arr_src a3 to a14, offset 4
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2, offset 0
s32i.n a14, a2, 4 // save 32 bits from a14 to arr_dest a2, offset 4
addi.n a3, a3, 8 // increment arr_src pointer by 8 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 8 bytes
_aligning_mod_8_check:
// Check modulo 4 of the unalignment, if - then copy 4 bytes
bbci a13, 2, _aligning_mod_4_check // branch if 2-nd bit of unalignment a13 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
addi.n a3, a3, 4 // increment arr_src pointer by 4 bytes
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_aligning_mod_4_check:
// Check modulo 2 of the unalignment, if - then copy 2 bytes
bbci a13, 1, _aligning_mod_2_check // branch if 1-st bit of unalignment a13 is clear
l16ui a15, a3, 0 // load 16 bits from arr_src a3 to a15
addi.n a3, a3, 2 // increment arr_src pointer by 2 bytes
s16i a15, a2, 0 // save 16 bits from a15 to arr_dest a2
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_aligning_mod_2_check:
// Check modulo 1 of the unalignment, if - then copy 1 byte
bbci a13, 0, _arr_dest_aligned // branch if 0-th bit of unalignment a13 is clear
l8ui a15, a3, 0 // load 8 bits from arr_src a3 to a15
addi.n a3, a3, 1 // increment arr_src pointer by 1 byte
s8i a15, a2, 0 // save 8 bits from a15 to arr_dest a2
addi.n a2, a2, 1 // increment arr_dest pointer by 1 byte
_arr_dest_aligned:
// arr_src alignment check
and a15, a9, a3 // 0xf (alignment mask) AND arr_src pointer
beqz a15, _arr_src_aligned
// arr_src unaligned, arr_dest aligned (arr_des either aligned originally or modified to be aligned by the Aligning the arr_des routine)
// Calculate modulo for non-aligned data
movi a8, 89478486 // a8 - div_48 constant
muluh a5, a8, a4 // a5 - loop_len = arr_len / 48
movi a9, 48 // a9 - 48
mul16s a8, a9, a5 // a8 - 48 * loop_len
sub a6, a4, a8 // a6 - loop_len_MOD 48
ee.ld.128.usar.ip q2, a3, 16 // Preload from arr_src
ee.ld.128.usar.ip q3, a3, 16 // Preload from arr_src
// Main loop arr_src unaligned
loopnez a5, ._main_loop_unaligned // 48 bytes in one loop
ee.src.q.ld.ip q4, a3, 16, q2, q3 // preload and shift from arr_src
ee.vst.128.ip q2, a2, 16 // store to aligned arr_dest
ee.src.q.ld.ip q2, a3, 16, q3, q4 // preload and shift from arr_src
ee.vst.128.ip q3, a2, 16 // store to aligned arr_dest
ee.src.q.ld.ip q3, a3, 16, q4, q2 // preload and shift from arr_src
ee.vst.128.ip q4, a2, 16 // store to aligned arr_dest
._main_loop_unaligned:
// Finish the _main_loop_unaligned outside of the loop from Q registers preloads
// Check modulo 32 of the loop_len_MOD, if - then copy 32 bytes
bbci a6, 5, _unaligned_mod_32_check // branch if 5-th bit of loop_len_MOD a6 is clear
ee.src.q.ld.ip q4, a3, 0, q2, q3 // preload and shift from arr_src
ee.vst.128.ip q2, a2, 16 // store to aligned arr_dest
ee.src.q q3, q3, q4 // final shift
ee.vst.128.ip q3, a2, 16 // store to aligned arr_dest
j _follow_unaligned
_unaligned_mod_32_check:
// Check modulo 16 of the loop_len_MOD, if - then copy 16 bytes
bbci a6, 4, _unaligned_mod_16_check // branch if 4-th bit of loop_len_MOD a6 is clear
ee.src.q q2, q2, q3 // final shift
ee.vst.128.ip q2, a2, 16 // store to aligned arr_dest
addi a3, a3, -16 // put arr_src pointer back
j _follow_unaligned
_unaligned_mod_16_check:
addi a3, a3, -32 // put arr_src pointer back
// Finish the _main_loop_unaligned outside of the loop
// Check modulo 8 of the loop_len_MOD, if - then copy 8 bytes
_follow_unaligned:
bbci a6, 3, _unaligned_mod_8_check // branch if 3-rd bit of loop_len_MOD a6 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15, offset 0
l32i.n a14, a3, 4 // load 32 bits from arr_src a3 to a14, offset 4
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2, offset 0
s32i.n a14, a2, 4 // save 32 bits from a14 to arr_dest a2, offset 4
addi.n a3, a3, 8 // increment arr_src pointer by 8 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 8 bytes
_unaligned_mod_8_check:
// Finish the rest of the data, as if the data were aligned, no S3 instructions will be used further after the jump
j _aligned_mod_8_check
// Both arrays (arr_src and arr_dest) aligned
_arr_src_aligned:
// Calculate modulo 32 for aligned data
srli a5, a4, 5 // a5 - loop_len = arr_len / 32
slli a6, a5, 5
sub a6, a4, a6 // a6 - loop_len_MOD 32
// Main loop arr_src aligned
loopnez a5, ._main_loop_aligned // 32 bytes in one loop
ee.vld.128.ip q0, a3, 16 // load 16 bytes from arr_src to q0
ee.vld.128.ip q1, a3, 16 // load 16 bytes from arr_src to q1
ee.vst.128.ip q0, a2, 16 // save 16 bytes to arr_dest from q0
ee.vst.128.ip q1, a2, 16 // save 16 bytes to arr_dest from q1
._main_loop_aligned:
// Modulo 32 check
beqz a6, _aligned_mod_32_check // branch if mod_32 = 0
// finish the end of the array outside of the main loop
// Check modulo 16 of the loop_len_MOD, if - then copy 16 bytes
bbci a6, 4, _aligned_mod_16_check // branch if 4-th bit of loop_len_MOD a6 is clear
ee.vld.128.ip q0, a3, 16 // load 128 bits from arr_src to q0, increase arr_src pointer by 16 bytes
ee.vst.128.ip q0, a2, 16 // save 128 bits to arr_dest from q0, increase arr_dest pointer by 16 bytes
_aligned_mod_16_check:
// Check modulo 8 of the loop_len_MOD, if - then copy 8 bytes
bbci a6, 3, _aligned_mod_8_check // branch if 3-rd bit of loop_len_MOD a6 is clear
ee.vld.l.64.ip q0, a3, 8 // load lower 64 bits from arr_src a3 to q0, increase arr_src pointer by 8 bytes
ee.vst.l.64.ip q0, a2, 8 // save lower 64 bits from q0 to arr_dest a2, increase arr_dest pointer by 8 bytes
_aligned_mod_8_check:
// Check modulo 4 of the loop_len_MOD, if - then copy 4 bytes
bbci a6, 2, _aligned_mod_4_check // branch if 2-nd bit of loop_len_MOD a6 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
addi.n a3, a3, 4 // increment arr_src pointer by 4 bytes
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_aligned_mod_4_check:
// Check modulo 2 of the loop_len_MOD, if - then copy 2 bytes
bbci a6, 1, _aligned_mod_2_check // branch if 1-st bit of loop_len_MOD a6 is clear
l16ui a15, a3, 0 // load 16 bits from arr_src a3 to a15
addi.n a3, a3, 2 // increment arr_src pointer by 2 bytes
s16i a15, a2, 0 // save 16 bits from a15 to arr_dest a2
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_aligned_mod_2_check:
// Check modulo 1 of the loop_len_MOD, if - then copy 1 byte
bbci a6, 0, _aligned_mod_32_check // branch if 0-th bit of loop_len_MOD a6 is clear
l8ui a15, a3, 0 // load 8 bits from arr_src a3 to a15
s8i a15, a2, 0 // save 8 bits from a15 to arr_dest a2
_aligned_mod_32_check:
mov a2, a7 // copy the initial arr_dest pointer from a7 to arr_dest a2
retw.n // return
_less_than_16:
// If the length of the copied array is lower than 16, it is faster not to use esp32s3-optimized functions
// Check modulo 8 of the arr_len, if - then copy 8 bytes
bbci a4, 3, _less_than_16_mod_8_check // branch if 3-rd bit of arr_len a4 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15, offset 0
l32i.n a14, a3, 4 // load 32 bits from arr_src a3 to a14, offset 4
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2, offset 0
s32i.n a14, a2, 4 // save 32 bits from a14 to arr_dest a2, offset 4
addi.n a3, a3, 8 // increment arr_src pointer by 8 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 8 bytes
_less_than_16_mod_8_check:
// Check modulo 4 of the arr_len, if - then copy 4 bytes
bbci a4, 2, _less_than_16_mod_4_check // branch if 2-nd bit of arr_len a4 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
addi.n a3, a3, 4 // increment arr_src pointer by 4 bytes
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_less_than_16_mod_4_check:
// Check modulo 2 of the arr_len, if - then copy 2 bytes
bbci a4, 1, _less_than_16_mod_2_check // branch if 1-st bit of arr_len a4 is clear
l16ui a15, a3, 0 // load 16 bits from arr_src a3 to a15
addi.n a3, a3, 2 // increment arr_src pointer by 2 bytes
s16i a15, a2, 0 // save 16 bits from a15 to arr_dest a2
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_less_than_16_mod_2_check:
// Check modulo 1 of the arr_len, if - then copy 1 byte
bbci a4, 0, _less_than_16_mod_1_check // branch if 0-th bit of arr_len a4 is clear
l8ui a15, a3, 0 // load 8 bits from arr_src a3 to a15
s8i a15, a2, 0 // save 8 bits from a15 to arr_dest a2
_less_than_16_mod_1_check:
mov a2, a7 // copy the initial arr_dest pointer from a7 to arr_dest a2
retw.n // return
#else // MEMCPY_OPTIMIZED
// ansi version of the memcpy (without TIE instructions) for testing purposes
entry a1, 32
mov a7, a2 // a7 - save arr_dest pointer
srli a5, a4, 4 // a5 - loop_len = arr_len / 16
// Run main loop which copies 16 bytes in one loop run
loopnez a5, ._ansi_loop
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
l32i.n a14, a3, 4 // load 32 bits from arr_src a3 to a14
l32i.n a13, a3, 8 // load 32 bits from arr_src a3 to a13
l32i.n a12, a3, 12 // load 32 bits from arr_src a3 to a13
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
s32i.n a14, a2, 4 // save 32 bits from a14 to arr_dest a2
s32i.n a13, a2, 8 // save 32 bits from a13 to arr_dest a2
s32i.n a12, a2, 12 // save 32 bits from a13 to arr_dest a2
addi.n a3, a3, 16 // increment arr_src pointer by 12 bytes
addi.n a2, a2, 16 // increment arr_dest pointer by 12 bytes
._ansi_loop:
// Finish the remaining bytes out of the loop
// Check modulo 8 of the arr_len, if - then copy 8 bytes
bbci a4, 3, _mod_8_check // branch if 2-nd bit of arr_len a4 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
l32i.n a14, a3, 4 // load 32 bits from arr_src a3 to a15
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
s32i.n a14, a2, 4 // save 32 bits from a15 to arr_dest a2
addi.n a3, a3, 8 // increment arr_src pointer by 4 bytes
addi.n a2, a2, 8 // increment arr_dest pointer by 4 bytes
_mod_8_check:
// Check modulo 4 of the arr_len, if - then copy 4 bytes
bbci a4, 2, _mod_4_check // branch if 2-nd bit of arr_len a4 is clear
l32i.n a15, a3, 0 // load 32 bits from arr_src a3 to a15
addi.n a3, a3, 4 // increment arr_src pointer by 4 bytes
s32i.n a15, a2, 0 // save 32 bits from a15 to arr_dest a2
addi.n a2, a2, 4 // increment arr_dest pointer by 4 bytes
_mod_4_check:
// Check modulo 2 of the arr_len, if - then copy 2 bytes
bbci a4, 1, _mod_2_check // branch if 1-st bit of arr_len a4 is clear
l16ui a15, a3, 0 // load 16 bits from arr_src a3 to a15
addi.n a3, a3, 2 // increment arr_src pointer by 2 bytes
s16i a15, a2, 0 // save 16 bits from a15 to arr_dest a2
addi.n a2, a2, 2 // increment arr_dest pointer by 2 bytes
_mod_2_check:
// Check modulo 1 of the arr_len, if - then copy 1 byte
bbci a4, 0, _mod_1_check // branch if 0-th bit of arr_len a4 is clear
l8ui a15, a3, 0 // load 8 bits from arr_src a3 to a15
s8i a15, a2, 0 // save 8 bits from a15 to arr_dest a2
_mod_1_check:
// if arr_len is shorter than 16, skip adding TIE instruction, to fix the panic handler before the main_app() loads
blti a4, 16, _less_than_16_1 // branch, if arr_len a4 is shorter than 16 bytes
#if TIE_ENABLE // put dummy TIE instruction to induce TIE context saving
ee.zero.qacc // initialize q0 to zero (dummy instruction)
#else // TIE_ENABLE
nop // compensate one cycle, when TIE is disabled to get the same benchmark value
#endif // TIE_ENABLE
_less_than_16_1:
mov a2, a7 // copy the initial arr_dest pointer from a7 to arr_dest a2
retw.n // return
#endif // MEMCPY_OPTIMIZED
#endif // dsps_mem_aes3_enbled
|
georgevio/IoT-Embedded
| 2,417
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/iir/biquad/dsps_biquad_f32_aes3.S
|
// Copyright 2025 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad_platform.h"
#if (dsps_biquad_f32_aes3_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_biquad_f32_aes3
.type dsps_biquad_f32_aes3,@function
// The function implements the following C code:
//esp_err_t dsps_biquad_f32_aes3(const float* input, float* output, int len, float* coef, float* w)
// {
// for (int i=0 ; i< len ; i++)
// {
// float d0 = input[i] - coef[3]*w[0] - coef[4]*w[1]; (input[i] - a[1]*w[0] - a[2]*w[1];)
// output[i] = coef[0]*d0 + coef[1]*w[0] + coef[2]*w[1];
// w[1] = w[0];
// w[0] = d0;
// }
// return ESP_OK;
// }
dsps_biquad_f32_aes3:
// input - a2
// output - a3
// len - a4
// coeffs - a5
// w- a6
// f0 - b0
// f1 - b1
// f2 - b2
// f3 - a1
// f4 - a2
// f5 - w0
// f6 - w1
entry a1, 16
// Array increment for floating point data should be 4
lsi f0, a5, 0
lsi f1, a5, 4
lsi f2, a5, 8
lsi f3, a5, 12
lsi f4, a5, 16
neg.s f5, f3 // -a[1]
neg.s f6, f4 // -a[2]
lsi f7, a6, 0 // w[0]
lsi f8, a6, 4 // w[1]
addi a3, a3, -4 // i-- // preset a3
lsi f9, a2, 0 // f9 = x[i]
loopnez a4, .loop_bq_end_m_aes3
madd.s f9, f7, f5 // f9 += -a1*w0
addi a3, a3, 4 // out++;
mul.s f10, f1, f7 // f10 = b1*w0
madd.s f9, f8, f6 // f9 += -a2*w1
madd.s f10, f9, f0 // f10 += b0*d0
addi a2, a2, 4 // in++;
madd.s f10, f2, f8 // f10+= b2*w1, f10 - result
mov.s f8, f7 // w1 = w0
mov.s f7, f9 // w0 = d0
lsi f9, a2, 0 // f9 = x[i]
ssi f10, a3, 0 // y[i] = result
.loop_bq_end_m_aes3:
// Store delay line
ssi f7, a6, 0
ssi f8, a6, 4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_biquad_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 3,677
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/iir/biquad/dsps_biquad_sf32_arp4.S
|
// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad_platform.h"
#if (dsps_biquad_f32_arp4_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_biquad_sf32_arp4
.type dsps_biquad_sf32_arp4,@function
// The function implements the following C code:
//esp_err_t dsps_biquad_f32_arp4(const float* input, float* output, int len, float* coef, float* w)
// {
// for (int i = 0 ; i < len ; i++) {
// float d0 = input[i*2 + 0] - coef[3] * w[0] - coef[4] * w[1];
// output[i*2 + 0] = coef[0] * d0 + coef[1] * w[0] + coef[2] * w[1];
// w[1] = w[0];
// w[0] = d0;
//
// d0 = input[i*2 + 1] - coef[3] * w[2] - coef[4] * w[3];
// output[i*2 + 1] = coef[0] * d0 + coef[1] * w[2] + coef[2] * w[3];
// w[3] = w[2];
// w[2] = d0;
// }
// return ESP_OK;
// }
dsps_biquad_sf32_arp4:
// input - a0
// output - a1
// len - a2
// coeffs - a3
// w- a4
// fa0 - b0
// fa1 - b1
// fa2 - b2
// fa3 - a1
// fa4 - a2
// fa5 - w0
// fa6 - w1
add sp,sp,-16
flw fa0, 0(a3) // coeff[0] : b0
flw fa1, 4(a3) // coeff[1] : b1
flw fa2, 8(a3) // coeff[2] : b2
flw fa3, 12(a3) // coeff[3] : a1
flw fa4, 16(a3) // coeff[4] : a2
fneg.S fa5, fa3 // -a[1]
fneg.S fa6, fa4 // -a[2]
flw ft0, 0(a4) // ft0 - f7 w0
flw ft1, 4(a4) // ft1 - f8 w1
flw ft5, 8(a4) // ft0 - f12 w2
flw ft6, 12(a4) // ft1 - f13 w3
flw ft2, 0(a0) // ft2 - f9 = x[i]
esp.lp.setup 0, a2, .iir_loop_end // label to the last executed instruction
fmadd.S ft2, ft0, fa5, ft2 // ft2 = x[i] - a1*w0
fmul.s ft3, fa1, ft0 // ft3 = w0*b1
fmadd.s ft2, ft1, fa6, ft2 // ft2 += -a2*w1 = d0
fmadd.s ft3, ft2, fa0, ft3 // f10 += b0*d0
addi a0, a0, 4 // in++;
fmadd.s ft3, fa2, ft1, ft3 // f10+= b2*w1, f10 - result
fmv.s ft1, ft0 // w1 = w0
fmv.s ft0, ft2 // w0 = d0
flw ft2, 0(a0)
fsw ft3, 0(a1)
addi a1, a1, 4 // out++;
fmadd.S ft2, ft5, fa5, ft2 // ft2 = x[i] - a1*w0
fmul.s ft3, fa1, ft5 // ft3 = w0*b1
fmadd.s ft2, ft6, fa6, ft2 // ft2 += -a2*w1 = d0
fmadd.s ft3, ft2, fa0, ft3 // f10 += b0*d0
addi a0, a0, 4 // in++;
fmadd.s ft3, fa2, ft6, ft3 // f10+= b2*w1, f10 - result
fmv.s ft6, ft5 // w1 = w0
fmv.s ft5, ft2 // w0 = d0
flw ft2, 0(a0)
fsw ft3, 0(a1)
addi a1, a1, 4 // out++;
.iir_loop_end: nop
fsw ft0, 0(a4) // ft0 - f7
fsw ft1, 4(a4) // ft1 - f8
fsw ft5, 8(a4) // ft5 - f12
fsw ft6, 12(a4) // ft6 - f13
mv a0, a6
add sp,sp,16
ret
#endif // dsps_biquad_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 2,814
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/iir/biquad/dsps_biquad_sf32_ae32.S
|
// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad_platform.h"
#if (dsps_biquad_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_biquad_sf32_ae32
.type dsps_biquad_sf32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_biquad_f32_ae32(const float* input, float* output, int len, float* coef, float* w)
// {
// for (int i=0 ; i< len ; i++)
// {
// float d0 = input[i] - coef[3]*w[0] - coef[4]*w[1]; (input[i] - a[1]*w[0] - a[2]*w[1];)
// output[i] = coef[0]*d0 + coef[1]*w[0] + coef[2]*w[1];
// w[1] = w[0];
// w[0] = d0;
// }
// return ESP_OK;
// }
dsps_biquad_sf32_ae32:
// input - a2
// output - a3
// len - a4
// coeffs - a5
// w- a6
// f0 - b0
// f1 - b1
// f2 - b2
// f3 - a1
// f4 - a2
// f5 - w0
// f6 - w1
entry a1, 16
// Array increment for floating point data should be 4
lsi f0, a5, 0
lsi f1, a5, 4
lsi f2, a5, 8
lsi f3, a5, 12
lsi f4, a5, 16
neg.s f5, f3 // -a[1]
neg.s f6, f4 // -a[2]
lsi f7, a6, 0 // w[0]
lsi f8, a6, 4 // w[1]
lsi f11, a6, 8 // w[0]
lsi f12, a6, 12 // w[1]
//addi a3, a3, -4 // i-- // preset a3
lsip f9, a2, 4 // f9 = x[i]
loopnez a4, .loop_bq_end_m_ae32
madd.s f9, f7, f5 // f9 += -a1*w0
mul.s f10, f1, f7 // f10 = b1*w0
madd.s f9, f8, f6 // f9 += -a2*w1
madd.s f10, f9, f0 // f10 += b0*d0
madd.s f10, f2, f8 // f10+= b2*w1, f10 - result
mov.s f8, f7 // w1 = w0
mov.s f7, f9 // w0 = d0
lsip f9, a2, 4 // f9 = x[i]
ssip f10, a3, 4 // y[i] = result
madd.s f9, f11, f5 // f9 += -a1*w0
mul.s f10, f1, f11 // f10 = b1*w0
madd.s f9, f12, f6 // f9 += -a2*w1
madd.s f10, f9, f0 // f10 += b0*d0
madd.s f10, f2, f12 // f10+= b2*w1, f10 - result
mov.s f12, f11 // w1 = w0
mov.s f11, f9 // w0 = d0
lsip f9, a2, 4 // f9 = x[i]
ssip f10, a3, 4 // y[i] = result
.loop_bq_end_m_ae32:
// Store delay line
ssi f7, a6, 0
ssi f8, a6, 4
ssi f11, a6, 8
ssi f12, a6, 12
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_biquad_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,309
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/iir/biquad/dsps_biquad_f32_ae32.S
|
// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad_platform.h"
#if (dsps_biquad_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_biquad_f32_ae32
.type dsps_biquad_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_biquad_f32_ae32(const float* input, float* output, int len, float* coef, float* w)
// {
// for (int i=0 ; i< len ; i++)
// {
// float d0 = input[i] - coef[3]*w[0] - coef[4]*w[1]; (input[i] - a[1]*w[0] - a[2]*w[1];)
// output[i] = coef[0]*d0 + coef[1]*w[0] + coef[2]*w[1];
// w[1] = w[0];
// w[0] = d0;
// }
// return ESP_OK;
// }
dsps_biquad_f32_ae32:
// input - a2
// output - a3
// len - a4
// coeffs - a5
// w- a6
// f0 - b0
// f1 - b1
// f2 - b2
// f3 - a1
// f4 - a2
// f5 - w0
// f6 - w1
entry a1, 16
// Array increment for floating point data should be 4
lsi f0, a5, 0
lsi f1, a5, 4
lsi f2, a5, 8
lsi f3, a5, 12
lsi f4, a5, 16
neg.s f5, f3 // -a[1]
neg.s f6, f4 // -a[2]
lsi f7, a6, 0 // w[0]
lsi f8, a6, 4 // w[1]
lsip f9, a2, 4 // f9 = x[i]
loopnez a4, .loop_bq_end_m_ae32
madd.s f9, f7, f5 // f9 += -a1*w0
mul.s f10, f1, f7 // f10 = b1*w0
madd.s f9, f8, f6 // f9 += -a2*w1
madd.s f10, f9, f0 // f10 += b0*d0
madd.s f10, f2, f8 // f10+= b2*w1, f10 - result
mov.s f8, f7 // w1 = w0
mov.s f7, f9 // w0 = d0
lsip f9, a2, 4 // f9 = x[i]
ssip f10, a3, 4 // y[i] = result
.loop_bq_end_m_ae32:
// Store delay line
ssi f7, a6, 0
ssi f8, a6, 4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_biquad_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,625
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/iir/biquad/dsps_biquad_f32_arp4.S
|
// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad_platform.h"
#if (dsps_biquad_f32_arp4_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_biquad_f32_arp4
.type dsps_biquad_f32_arp4,@function
// The function implements the following C code:
//esp_err_t dsps_biquad_f32_arp4(const float* input, float* output, int len, float* coef, float* w)
// {
// for (int i=0 ; i< len ; i++)
// {
// float d0 = input[i] - coef[3]*w[0] - coef[4]*w[1]; (input[i] - a[1]*w[0] - a[2]*w[1];)
// output[i] = coef[0]*d0 + coef[1]*w[0] + coef[2]*w[1];
// w[1] = w[0];
// w[0] = d0;
// }
// return ESP_OK;
// }
dsps_biquad_f32_arp4:
// input - a0
// output - a1
// len - a2
// coeffs - a3
// w- a4
// fa0 - b0
// fa1 - b1
// fa2 - b2
// fa3 - a1
// fa4 - a2
// fa5 - w0
// fa6 - w1
add sp,sp,-16
flw fa0, 0(a3)
flw fa1, 4(a3)
flw fa2, 8(a3)
flw fa3, 12(a3)
flw fa4, 16(a3)
fneg.S fa5, fa3 // -a[1]
fneg.S fa6, fa4 // -a[2]
flw ft0, 0(a4) // ft0 - w0
flw ft1, 4(a4) // ft1 - w1
flw ft2, 0(a0) // ft2 - f9 = x[i]
esp.lp.setup 0, a2, .iir_loop_end // label to the last executed instruction
fmadd.S ft2, ft0, fa5, ft2
fmul.s ft3, fa1, ft0
fmadd.s ft2, ft1, fa6, ft2 // f9 += -a2*w1
fmadd.s ft3, ft2, fa0, ft3 // f10 += b0*d0
addi a0, a0, 4 // in++;
fmadd.s ft3, fa2, ft1, ft3 // f10+= b2*w1, f10 - result
fmv.s ft1, ft0 // w1 = w0
fmv.s ft0, ft2 // w0 = d0
flw ft2, 0(a0)
fsw ft3, 0(a1)
addi a1, a1, 4 // out++;
.iir_loop_end: nop
fsw ft0, 0(a4) // ft0 - f7
fsw ft1, 4(a4) // ft1 - f8
mv a0, a6
add sp,sp,16
ret
#endif // dsps_biquad_f32_aes3_enabled
|
georgevio/IoT-Embedded
| 1,699
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fft/float/dsps_bit_rev_lookup_fc32_aes3.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft2r_platform.h"
#if (dsps_bit_rev_lookup_fc32_ae32_enabled == 1)
#if (dsps_fft2r_fc32_aes3_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dsps_bit_rev_lookup_fc32_aes3
.type dsps_bit_rev_lookup_fc32_aes3,@function
dsps_bit_rev_lookup_fc32_aes3:
//esp_err_t dsps_bit_rev_lookup_fc32_aes3(float *data, int reverse_size, uint16_t *reverse_tab)
entry a1, 16
// data - a2
// reverse_size - a3
// reverse_tab - a4
loopnez a3, .__loop_end_radix2_reorder_lookup_table
l16ui a5, a4, 0 // Load first addr shift
l16ui a6, a4, 2 // Load second addr shift
addi a4, a4, 4 // Table addr update
add.n a5, a5, a2
add.n a6, a6, a2
EE.LDF.64.IP f0, f2, a5, 0
EE.LDF.64.IP f1, f3, a6, 0
EE.STF.64.IP f0, f2, a6, 0
EE.STF.64.IP f1, f3, a5, 0
.__loop_end_radix2_reorder_lookup_table:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_fft2r_fc32_aes3_enabled
#endif // dsps_bit_rev_lookup_fc32_ae32_enabled
|
georgevio/IoT-Embedded
| 3,655
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft2r_fc32_aes3_.S
|
/*
* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileContributor: 2024 f4lcOn @ Libera Chat IRC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_fc32_aes3_enabled == 1)
.text
.align 4
.global dsps_fft2r_fc32_aes3_
.type dsps_fft2r_fc32_aes3_,@function
// The function implements the following C code:
//esp_err_t dsps_fft2r_fc32_ansi(float *data, int N)
//{
// float *w = dsps_fft_w_table_fc32;
//
// int ie, ia, m;
// float re_temp, im_temp;
// float c, s;
// int N2 = N;
// ie = 1;
// for (int N2 = N/2; N2 > 0; N2 >>= 1) {
// ia = 0;
// for (int j = 0; j < ie; j++) {
// c = w[2 * j];
// s = w[2 * j + 1];
// for (int i = 0; i < N2; i++) {
// m = ia + N2;
// re_temp = c * data[2 * m] + s * data[2 * m + 1];
// im_temp = c * data[2 * m + 1] - s * data[2 * m];
// data[2 * m] = data[2 * ia] - re_temp;
// data[2 * m + 1] = data[2 * ia + 1] - im_temp;
// data[2 * ia] = data[2 * ia] + re_temp;
// data[2 * ia + 1] = data[2 * ia + 1] + im_temp;
// ia++;
// }
// ia += N2;
// }
// ie <<= 1;
// }
// return result;
//}
dsps_fft2r_fc32_aes3_:
//esp_err_t dsps_fft2r_fc32_ansi(float *data, int N, float* dsps_fft_w_table_fc32)
entry a1, 16
// Array increment for floating point data should be 4
// data - a2
// N - a3
// dsps_fft_w_table_fc32 - a4
// a6 - k, main loop counter; N2 - for (int N2 = N/2; N2 > 0; N2 >>= 1)
// a7 - ie
// a8 - j
// a10 - (j*2)<<2, or a10 - j<<3
// f0 - c or w[2 * j]
// f1 - s or w[2 * j + 1]
// a11 - ia
// a12 - m
// a13 - ia pointer
// a14 - m pointer
// f6 - re_temp
// f7 - im_temp
srli a6, a3, 1 // a6 = N2 = N/2
movi.n a7, 1 // a7 - ie
.fft2r_l1:
movi.n a8, 0 // a8 - j
movi.n a11,0 // a11 = ia = 0;
.fft2r_l2: // loop for j, a8 - j
addx8 a10, a8, a4 // a8 - shift for cos () -- c = w[2 * j]; -- pointer to cos
ee.ldf.64.ip f1, f0, a10, 0
add.n a12, a11, a6 // a12 = m = ia + N2
addx8 a14, a12, a2 // a14 - pointer for m*2
loopnez a6, .fft2r_l3
ee.ldf.64.ip f5, f4, a14, 0 // data[2 * m], data[2 * m + 1]
mul.s f6, f0, f4 // re_temp = c * data[2 * m]
mul.s f7, f0, f5 // im_temp = c * data[2 * m + 1]
addx8 a13, a11, a2 // a13 - pointer for ia*2
ee.ldf.64.ip f3, f2, a13, 0 // data[2 * ia], data[2 * ia + 1]
madd.s f6, f1, f5 // re_temp += s * data[2 * m + 1];
msub.s f7, f1, f4 // im_temp -= s * data[2 * m];
addi a11, a11, 1 // ia++
add.n a12, a11, a6 // a12 = m = ia + N2
sub.s f8, f2, f6 // = data[2 * ia] - re_temp;
sub.s f9, f3, f7 // = data[2 * ia + 1] - im_temp;
add.s f10, f2, f6 // = data[2 * ia] + re_temp;
add.s f11, f3, f7 // = data[2 * ia + 1] + im_temp;
ee.stf.64.ip f9, f8, a14, 0
addx8 a14, a12, a2 // a14 - pointer for m*2
ee.stf.64.ip f11, f10, a13, 0
.fft2r_l3:
add.n a11, a11, a6
addi.n a8, a8, 1 // j++
bne a8, a7, .fft2r_l2
slli a7, a7, 1 // ie = ie<<1
// main loop: for (int k = N/2; k > 0; k >>= 1)
srli a6, a6, 1 // a6 = a6>>1
bnez a6, .fft2r_l1 // Jump if > 0
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_fft2r_fc32_aes3_enabled
|
georgevio/IoT-Embedded
| 7,652
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft4r_fc32_aes3_.S
|
/*
* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileContributor: 2024 f4lcOn @ Libera Chat IRC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsp_err_codes.h"
#include "dsps_fft4r_platform.h"
#if (dsps_fft4r_fc32_aes3_enabled == 1)
.section .text
.global dsps_fft4r_fc32_aes3_
.global dsps_fft4r_fc32_ae32_
.type dsps_fft4r_fc32_aes3_,@function
.type dsps_fft4r_fc32_ae32_,@function
// The function implements the following C code:
// esp_err_t dsps_fft4r_fc32_ansi_(float *data, int length, float *table, int table_size)
// {
// if (0 == dsps_fft4r_initialized) {
// return ESP_ERR_DSP_UNINITIALIZED;
// }
//
// uint log2N = dsp_power_of_two(length);
// if ((log2N & 0x01) != 0) {
// return ESP_ERR_DSP_INVALID_LENGTH;
// }
// uint log4N = log2N >> 1;
//
// fc32_t bfly[4];
// uint m = 2;
// uint wind_step = table_size / length;
// while (1) { ///radix 4
// if (log4N == 0) {
// break;
// }
// length = length >> 2;
// for (int j = 0; j < m; j += 2) { // j: which FFT of this step
// int start_index = j * (length << 1); // n: n-point FFT
//
// fc32_t *ptrc0 = (fc32_t *)data + start_index;
// fc32_t *ptrc1 = ptrc0 + length;
// fc32_t *ptrc2 = ptrc1 + length;
// fc32_t *ptrc3 = ptrc2 + length;
//
// fc32_t *winc0 = (fc32_t *)table;
// fc32_t *winc1 = winc0;
// fc32_t *winc2 = winc0;
//
// for (int k = 0; k < length; k++) {
// fc32_t in0 = *ptrc0;
// fc32_t in2 = *ptrc2;
// fc32_t in1 = *ptrc1;
// fc32_t in3 = *ptrc3;
//
// bfly[0].re = in0.re + in2.re + in1.re + in3.re;
// bfly[0].im = in0.im + in2.im + in1.im + in3.im;
//
// bfly[1].re = in0.re - in2.re + in1.im - in3.im;
// bfly[1].im = in0.im - in2.im - in1.re + in3.re;
//
// bfly[2].re = in0.re + in2.re - in1.re - in3.re;
// bfly[2].im = in0.im + in2.im - in1.im - in3.im;
//
// bfly[3].re = in0.re - in2.re - in1.im + in3.im;
// bfly[3].im = in0.im - in2.im + in1.re - in3.re;
//
// *ptrc0 = bfly[0];
// ptrc1->re = bfly[1].re * winc0->re + bfly[1].im * winc0->im;
// ptrc1->im = bfly[1].im * winc0->re - bfly[1].re * winc0->im;
// ptrc2->re = bfly[2].re * winc1->re + bfly[2].im * winc1->im;
// ptrc2->im = bfly[2].im * winc1->re - bfly[2].re * winc1->im;
// ptrc3->re = bfly[3].re * winc2->re + bfly[3].im * winc2->im;
// ptrc3->im = bfly[3].im * winc2->re - bfly[3].re * winc2->im;
//
// winc0 += 1 * wind_step;
// winc1 += 2 * wind_step;
// winc2 += 3 * wind_step;
//
// ptrc0++;
// ptrc1++;
// ptrc2++;
// ptrc3++;
// }
// }
// m = m << 2;
// wind_step = wind_step << 2;
// log4N--;
// }
// return ESP_OK;
// }
// esp_err_t dsps_fft4r_fc32_aes3_(data, N, dsps_fft4r_w_table_fc32, dsps_fft4r_w_table_size)
.ret_DSP_INVALID_LENGTH:
movi.n a2, ESP_ERR_DSP_INVALID_LENGTH
retw.n
.align 4
dsps_fft4r_fc32_ae32_: // this is added to make compatibility with libraries that already compiled and use ae32_ function.
dsps_fft4r_fc32_aes3_:
entry a1, 16 # no auto vars on stack
bltui a3, 4, .ret_DSP_INVALID_LENGTH # if N < 4 : return(ESP_ERR_DSP_INVALID_LENGTH)
addi.n a6, a3, -1
and a6, a3, a6
bnez a6, .ret_DSP_INVALID_LENGTH # if N not power of 2 : return(ESP_ERR_DSP_INVALID_LENGTH)
nsau a6, a3 # inline dsp_power_of_two(N)
movi.n a7, 31
xor a6, a6, a7
bbsi a6, 0, .ret_DSP_INVALID_LENGTH # if N not power of 4 : return(ESP_ERR_DSP_INVALID_LENGTH)
srli a7, a6, 1 # log4N = dsp_power_of_two(N) >> 1;
addi.n a6, a6, -1
ssr a6
srl a6, a5 # w_step = table_size >> (dsp_power_of_two(N) - 1)
movi.n a5, 2 # m = 2
.stage:
srli a3, a3, 2 # N >>= 2
movi.n a8, 0 # j = 0
.group:
mov.n a9, a4 # w0 = w
mov.n a10, a4 # w1 = w
mov.n a11, a4 # w2 = w
mul16u a12, a8, a3
slli a12, a12, 1 # start_index = (j * N) << 1
addx8 a12, a12, a2 # p0 = data + (start_index << 1)
addx8 a13, a3, a12 # p1 = p0 + (N << 1)
addx8 a14, a3, a13 # p2 = p1 + (N << 1)
addx8 a15, a3, a14 # p3 = p2 + (N << 1)
loopnez a3, .bf4_loop_end # for (uint k = 0; k < N; k++)
ee.ldf.64.ip f1, f0, a12, 0 # f0 = in0.re = *p0, f1 = in0.im = *(p0 + 1)
ee.ldf.64.ip f3, f2, a14, 0 # f2 = in2.re = *p2, f3 = in2.im = *(p2 + 1)
add.s f5, f1, f3 # f5 = in0.im + in2.im
sub.s f7, f1, f3 # f7 = in0.im - in2.im
add.s f4, f0, f2 # f4 = in0.re + in2.re
sub.s f6, f0, f2 # f6 = in0.re - in2.re
ee.ldf.64.ip f1, f0, a13, 0 # f0 = in1.re = *p1, f1 = in1.im = *(p1 + 1)
ee.ldf.64.ip f3, f2, a15, 0 # f2 = in3.re = *p3, f3 = in3.im = *(p3 + 1)
add.s f9, f1, f3 # f9 = in1.im + in3.im
sub.s f11, f1, f3 # f11 = in1.im - in3.im
lsi f12, a9, 0 # f12 = w0->re
lsi f13, a10, 0 # f13 = w1->re
lsi f14, a11, 0 # f14 = w2->re
add.s f8, f0, f2 # f8 = in1.re + in3.re
sub.s f10, f0, f2 # f10 = in1.re - in3.re
sub.s f1, f5, f9 # f1 = bf2.im = in0.im + in2.im - in1.im - in3.im
add.s f5, f5, f9 # f5 = bf0.im = in0.im + in2.im + in1.im + in3.im
add.s f2, f6, f11 # f2 = bf1.re = in0.re - in2.re + in1.im - in3.im
sub.s f6, f6, f11 # f6 = bf3.re = in0.re - in2.re - in1.im + in3.im
sub.s f0, f4, f8 # f0 = bf2.re = in0.re + in2.re - in1.re - in3.re
add.s f4, f4, f8 # f4 = bf0.re = in0.re + in2.re + in1.re + in3.re
sub.s f3, f7, f10 # f3 = bf1.im = in0.im - in2.im - in1.re + in3.re
add.s f7, f7, f10 # f7 = bf3.im = in0.im - in2.im + in1.re - in3.re
mul.s f10, f6, f14 # f10 = bf3.re * w2->re
ee.stf.64.ip f5, f4, a12, 8 # *p0 = f4 = bf0.re, *(p0 + 1) = f5 = bf0.im, p0 += 2
mul.s f4, f2, f12 # f4 = bf1.re * w0->re
mul.s f11, f7, f14 # f11 = bf3.im * w2->re
mul.s f5, f3, f12 # f5 = bf1.im * w0->re
mul.s f8, f0, f13 # f8 = bf2.re * w1->re
mul.s f9, f1, f13 # f9 = bf2.im * w1->re
lsi f12, a9, 4 # f12 = w0->im
lsi f13, a10, 4 # f13 = w1->im
lsi f14, a11, 4 # f14 = w2->im
msub.s f5, f2, f12 # f5 = bf1.im * w0->re - bf1.re * w0->im
madd.s f4, f3, f12 # f4 = bf1.re * w0->re + bf1.im * w0->im
msub.s f9, f0, f13 # f9 = bf2.im * w1->re - bf2.re * w1->im
madd.s f8, f1, f13 # f8 = bf2.re * w1->re + bf2.im * w1->im
msub.s f11, f6, f14 # f11 = bf3.im * w2->re - bf3.re * w2->im
madd.s f10, f7, f14 # f10 = bf3.re * w2->re + bf3.im * w2->im
addx4 a9, a6, a9 # w0 += w_step
addx8 a10, a6, a10 # w1 += 2 * w_step
addx4 a11, a6, a11
addx8 a11, a6, a11 # w2 += 3 * w_step
ee.stf.64.ip f5, f4, a13, 8 # *p1 = f4, *(p1 + 1) = f5, p1 += 2
ee.stf.64.ip f9, f8, a14, 8 # *p2 = f8, *(p2 + 1) = f9, p2 += 2
ee.stf.64.ip f11, f10, a15, 8 # *p3 = f10, *(p3 + 1) = f11, p3 += 2
.bf4_loop_end:
addi.n a8, a8, 2 # j += 2
bgeu a8, a5, .stage_next # if j >= m
j .group
.stage_next:
slli a5, a5, 2 # m <<= 2
slli a6, a6, 2 # w_step <<= 2
addi.n a7, a7, -1 # log4N--
bnez a7, .stage # if log4N > 0
movi.n a2, DSP_OK # return(DSP_OK)
retw.n
#endif // dsps_fft4r_fc32_aes3_enabled
|
georgevio/IoT-Embedded
| 3,678
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft2r_fc32_ae32_.S
|
/*
* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileContributor: 2024 f4lcOn @ Libera Chat IRC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_fc32_ae32_enabled == 1)
.text
.align 4
.global dsps_fft2r_fc32_ae32_
.type dsps_fft2r_fc32_ae32_,@function
// The function implements the following C code:
//esp_err_t dsps_fft2r_fc32_ansi(float *data, int N)
//{
// float *w = dsps_fft_w_table_fc32;
//
// int ie, ia, m;
// float re_temp, im_temp;
// float c, s;
// int N2 = N;
// ie = 1;
// for (int N2 = N/2; N2 > 0; N2 >>= 1) {
// ia = 0;
// for (int j = 0; j < ie; j++) {
// c = w[2 * j];
// s = w[2 * j + 1];
// for (int i = 0; i < N2; i++) {
// m = ia + N2;
// re_temp = c * data[2 * m] + s * data[2 * m + 1];
// im_temp = c * data[2 * m + 1] - s * data[2 * m];
// data[2 * m] = data[2 * ia] - re_temp;
// data[2 * m + 1] = data[2 * ia + 1] - im_temp;
// data[2 * ia] = data[2 * ia] + re_temp;
// data[2 * ia + 1] = data[2 * ia + 1] + im_temp;
// ia++;
// }
// ia += N2;
// }
// ie <<= 1;
// }
// return result;
//}
dsps_fft2r_fc32_ae32_:
//esp_err_t dsps_fft2r_fc32_ansi(float *data, int N, float* dsps_fft_w_table_fc32)
entry a1, 16
// Array increment for floating point data should be 4
// data - a2
// N - a3
// dsps_fft_w_table_fc32 - a4
// a6 - k, main loop counter; N2 - for (int N2 = N/2; N2 > 0; N2 >>= 1)
// a7 - ie
// a8 - j
// a10 - (j*2)<<2, or a10 - j<<3
// f0 - c or w[2 * j]
// f1 - s or w[2 * j + 1]
// a11 - ia
// a12 - m
// a13 - ia pointer
// a14 - m pointer
// f6 - re_temp
// f7 - im_temp
srli a6, a3, 1 // a6 = N2 = N/2
movi.n a7, 1 // a7 - ie
.fft2r_l1:
movi.n a8, 0 // a8 - j
movi.n a11,0 // a11 = ia = 0;
.fft2r_l2: // loop for j, a8 - j
addx8 a10, a8, a4 // a8 - shift for cos () -- c = w[2 * j]; -- pointer to cos
lsi f0, a10, 0
lsi f1, a10, 4
loopnez a6, .fft2r_l3
add.n a12, a11, a6 // a12 = m = ia + N2
addx8 a14, a12, a2 // a14 - pointer for m*2
addx8 a13, a11, a2 // a13 - pointer for ia*2
lsi f4, a14, 0 // data[2 * m]
mul.s f6, f0, f4 // re_temp = c * data[2 * m]
lsi f5, a14, 4 // data[2 * m + 1]
mul.s f7, f0, f5 // im_temp = c * data[2 * m + 1]
lsi f2, a13, 0 // data[2 * ia]
madd.s f6, f1, f5 // re_temp += s * data[2 * m + 1];
lsi f3, a13, 4 // data[2 * ia + 1]
msub.s f7, f1, f4 // im_temp -= s * data[2 * m];
addi a11, a11, 1 // ia++
sub.s f8, f2, f6 // = data[2 * ia] - re_temp;
add.s f10, f2, f6 // = data[2 * ia] + re_temp;
sub.s f9, f3, f7 // = data[2 * ia + 1] - im_temp;
add.s f11, f3, f7 // = data[2 * ia + 1] + im_temp;
ssi f8, a14, 0
ssi f10, a13, 0
ssi f9, a14, 4
ssi f11, a13, 4
.fft2r_l3:
add.n a11, a11, a6
addi.n a8, a8, 1 // j++
bne a8, a7, .fft2r_l2
slli a7, a7, 1 // ie = ie<<1
// main loop: for (int k = N/2; k > 0; k >>= 1)
srli a6, a6, 1 // a6 = a6>>1
bnez a6, .fft2r_l1 // Jump if > 0
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_fft2r_fc32_ae32_enabled
|
georgevio/IoT-Embedded
| 6,414
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft4r_fc32_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft4r_platform.h"
#if (dsps_fft4r_fc32_arp4_enabled == 1)
// This is matrix multipliction function for esp32p4 processor.
.text
.align 4
.global dsps_fft4r_fc32_arp4_
.type dsps_fft4r_fc32_arp4_,@function
dsps_fft4r_fc32_arp4_:
//esp_err_t dsps_fft4r_fc32_arp4_(float *data, int N, float *table, int wind_step)
// wind_step - a3
// m - t0
// j - t1
add sp,sp,-16
#
srli t6, a1, 1 // t6 = log4N = N/2
li t0, 2 // t0 - m
slli a3, a3, 3 // wind_step = complex step = 8 bytes
.fft2r_l1:
li t1, 0 // t1 - j
srli a1, a1, 2 // a1 = length = length >> 2;
.fft2r_l2: // loop for j, t1 - j
slli t2, a1, 4 // t2 = length << 1 << 3 (8 bytes for one complex sample)
slli t3, a1, 3 // t2 = length << 1 << 3 (8 bytes for one complex sample)
// start_index = j * (length << 1); // n: n-point FFT
mul t2,t2,t1
add a4, a0, t2 // fc32_t *ptrc0
add a5, a4, t3 // fc32_t *ptrc1
add a6, a5, t3 // fc32_t *ptrc2
add a7, a6, t3 // fc32_t *ptrc3
# flw fa0, 0(a4)
# fsw fa0, 0(t3)
# add t3, t3, 4
mv t2, a2 // winc0
mv t3, a2 // winc0
mv t4, a2 // winc0
esp.lp.setup 0, a1, .fft2r_l3 // .fft2r_l3 - label to the last executed instruction
flw fa0, 0(a4) // in0.re
flw fa4, 0(a6) // in2.re
fadd.s ft0, fa0, fa4 // in0.re + in2.re
flw fa1, 4(a4) // in0.im
fsub.s ft1, fa0, fa4 // in0.re - in2.re
flw fa5, 4(a6) // in2.im
fadd.s ft2, fa1, fa5 // in0.im + in2.im
flw fa2, 0(a5) // in1.re
fsub.s ft3, fa1, fa5 // in0.im - in2.im
flw fa6, 0(a7) // in3.re
fadd.s ft4, fa2, fa6 // in1.re + in3.re
flw fa3, 4(a5) // in1.im
fsub.s ft5, fa2, fa6 // in1.re - in3.re
flw fa7, 4(a7) // in3.im
fadd.s ft6, fa3, fa7 // in1.im + in3.im
fsub.s ft7, fa3, fa7 // in1.im - in3.im
# bfly[0].re = ft0 + ft4;
fadd.s fa0, ft0, ft4;
# bfly[0].im = ft2 + ft6;
fadd.s fa1, ft2, ft6;
# bfly[1].re = ft1 + ft7;
fadd.s fa2, ft1, ft7;
# bfly[1].im = ft3 - ft5;
fsub.s fa3, ft3, ft5;
# bfly[2].re = ft0 - ft5;
fsub.s fa4, ft0, ft4;
flw ft0, 0(t2) // winc0->re
# bfly[2].im = ft2 - ft7;
fsub.s fa5, ft2, ft6;
flw ft2, 0(t3) // winc1->re
# bfly[3].re = ft1 - ft6;
fsub.s fa6, ft1, ft7;
flw ft1, 4(t2) // winc0->im
# bfly[3].im = ft3 + ft5;
fadd.s fa7, ft3, ft5;
// *ptrc0 = bfly[0];
fsw fa0, 0(a4) // in0.re
fsw fa1, 4(a4) // in0.im
flw ft3, 4(t3) // winc1->im
// ptrc1->re = bfly[1].re * winc0->re + bfly[1].im * winc0->im;
// ptrc1->im = bfly[1].im * winc0->re - bfly[1].re * winc0->im;
// ptrc2->re = bfly[2].re * winc1->re + bfly[2].im * winc1->im;
fmul.s fa0, fa2, ft0
add t2, t2, a3 // winc0 += 1 * wind_step;
fmul.s fa1, fa3, ft0
fmul.s ft0, fa4, ft2
fmul.s ft2, fa5, ft2
flw ft4, 0(t4) // winc2->re
flw ft5, 4(t4) // winc3->im
fmadd.s fa0, fa3, ft1, fa0
add t3, t3, a3 // winc1 += 2 * wind_step;
fnmsub.s fa1, fa2, ft1, fa1
add t3, t3, a3 //
fmul.s fa2, fa6, ft4
fmul.s fa3, fa7, ft4
add t4, t4, a3 // winc2 += 3 * wind_step;
fmadd.s ft0, fa5, ft3, ft0
add t4, t4, a3 //
fnmsub.s ft2, fa4, ft3, ft2
fmadd.s ft3, fa7, ft5, fa2
add t4, t4, a3 //
fnmsub.s fa3, fa6, ft5, fa3
fsw fa0, 0(a5) // in1.re
add a4, a4, 8
fsw fa1, 4(a5) // in1.im
add a5, a5, 8
fsw ft0, 0(a6) // in2.re
// ptrc2->im = bfly[2].im * winc1->re - bfly[2].re * winc1->im;
fsw ft2, 4(a6) // in2.re
// ptrc3->re = bfly[3].re * winc2->re + bfly[3].im * winc2->im;
add a6, a6, 8
fsw ft3, 0(a7) // in2.re
// ptrc3->im = bfly[3].im * winc2->re - bfly[3].re * winc2->im;
fsw fa3, 4(a7) // in2.re
add a7, a7, 8
// Temp solution
.fft2r_l3: nop
add t1, t1, 2 // j+=2
BNE t1, t0, .fft2r_l2
slli t0, t0, 2 // t0 = m = m<<2
srli t6, t6, 2 // t6 = log4N >>= 2
slli a3, a3, 2 // wind_step = wind_step << 2;
BNEZ t6, .fft2r_l1// Jump if > 0
#
add sp,sp,16
li a0,0
ret
#endif // dsps_fft4r_fc32_arp4_enabled
|
georgevio/IoT-Embedded
| 7,631
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft4r_fc32_ae32_.S
|
/*
* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileContributor: 2024 f4lcOn @ Libera Chat IRC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsp_err_codes.h"
#include "dsps_fft4r_platform.h"
#if (dsps_fft4r_fc32_ae32_enabled == 1)
.section .text # placed in IRAM instead of FLASH .text
.global dsps_fft4r_fc32_ae32_
.type dsps_fft4r_fc32_ae32_,@function
// The function implements the following C code:
// esp_err_t dsps_fft4r_fc32_ansi_(float *data, int length, float *table, int table_size)
// {
// if (0 == dsps_fft4r_initialized) {
// return ESP_ERR_DSP_UNINITIALIZED;
// }
//
// uint log2N = dsp_power_of_two(length);
// if ((log2N & 0x01) != 0) {
// return ESP_ERR_DSP_INVALID_LENGTH;
// }
// uint log4N = log2N >> 1;
//
// fc32_t bfly[4];
// uint m = 2;
// uint wind_step = table_size / length;
// while (1) { ///radix 4
// if (log4N == 0) {
// break;
// }
// length = length >> 2;
// for (int j = 0; j < m; j += 2) { // j: which FFT of this step
// int start_index = j * (length << 1); // n: n-point FFT
//
// fc32_t *ptrc0 = (fc32_t *)data + start_index;
// fc32_t *ptrc1 = ptrc0 + length;
// fc32_t *ptrc2 = ptrc1 + length;
// fc32_t *ptrc3 = ptrc2 + length;
//
// fc32_t *winc0 = (fc32_t *)table;
// fc32_t *winc1 = winc0;
// fc32_t *winc2 = winc0;
//
// for (int k = 0; k < length; k++) {
// fc32_t in0 = *ptrc0;
// fc32_t in2 = *ptrc2;
// fc32_t in1 = *ptrc1;
// fc32_t in3 = *ptrc3;
//
// bfly[0].re = in0.re + in2.re + in1.re + in3.re;
// bfly[0].im = in0.im + in2.im + in1.im + in3.im;
//
// bfly[1].re = in0.re - in2.re + in1.im - in3.im;
// bfly[1].im = in0.im - in2.im - in1.re + in3.re;
//
// bfly[2].re = in0.re + in2.re - in1.re - in3.re;
// bfly[2].im = in0.im + in2.im - in1.im - in3.im;
//
// bfly[3].re = in0.re - in2.re - in1.im + in3.im;
// bfly[3].im = in0.im - in2.im + in1.re - in3.re;
//
// *ptrc0 = bfly[0];
// ptrc1->re = bfly[1].re * winc0->re + bfly[1].im * winc0->im;
// ptrc1->im = bfly[1].im * winc0->re - bfly[1].re * winc0->im;
// ptrc2->re = bfly[2].re * winc1->re + bfly[2].im * winc1->im;
// ptrc2->im = bfly[2].im * winc1->re - bfly[2].re * winc1->im;
// ptrc3->re = bfly[3].re * winc2->re + bfly[3].im * winc2->im;
// ptrc3->im = bfly[3].im * winc2->re - bfly[3].re * winc2->im;
//
// winc0 += 1 * wind_step;
// winc1 += 2 * wind_step;
// winc2 += 3 * wind_step;
//
// ptrc0++;
// ptrc1++;
// ptrc2++;
// ptrc3++;
// }
// }
// m = m << 2;
// wind_step = wind_step << 2;
// log4N--;
// }
// return ESP_OK;
// }
// esp_err_t dsps_fft4r_fc32_ae32_(data, N, dsps_fft4r_w_table_fc32, dsps_fft4r_w_table_size)
.ret_DSP_INVALID_LENGTH:
movi.n a2, ESP_ERR_DSP_INVALID_LENGTH
retw.n
.align 4
dsps_fft4r_fc32_ae32_:
entry a1, 16 # no auto vars on stack
bltui a3, 4, .ret_DSP_INVALID_LENGTH # if N < 4 : return(ESP_ERR_DSP_INVALID_LENGTH)
addi.n a6, a3, -1
and a6, a3, a6
bnez a6, .ret_DSP_INVALID_LENGTH # if N not power of 2 : return(ESP_ERR_DSP_INVALID_LENGTH)
nsau a6, a3 # inline dsp_power_of_two(N)
movi.n a7, 31
xor a6, a6, a7
bbsi a6, 0, .ret_DSP_INVALID_LENGTH # if N not power of 4 : return(ESP_ERR_DSP_INVALID_LENGTH)
srli a7, a6, 1 # log4N = dsp_power_of_two(N) >> 1;
addi.n a6, a6, -1
ssr a6
srl a6, a5 # w_step = table_size >> (dsp_power_of_two(N) - 1)
movi.n a5, 2 # m = 2
.stage:
srli a3, a3, 2 # N >>= 2
movi.n a8, 0 # j = 0
.group:
mov.n a9, a4 # w0 = w
mov.n a10, a4 # w1 = w
mov.n a11, a4 # w2 = w
mul16u a12, a8, a3
slli a12, a12, 1 # start_index = (j * N) << 1
addx8 a12, a12, a2 # p0 = data + (start_index << 1)
addx8 a13, a3, a12 # p1 = p0 + (N << 1)
addx8 a14, a3, a13 # p2 = p1 + (N << 1)
addx8 a15, a3, a14 # p3 = p2 + (N << 1)
loopnez a3, .bf4_loop_end # for (uint k = 0; k < N; k++)
lsi f1, a12, 4 # f1 = in0.im = *(p0 + 1)
lsi f3, a14, 4 # f3 = in2.im = *(p2 + 1)
lsi f0, a12, 0 # f0 = in0.re = *p0
lsi f2, a14, 0 # f2 = in2.re = *p2
add.s f5, f1, f3 # f5 = in0.im + in2.im
sub.s f7, f1, f3 # f7 = in0.im - in2.im
lsi f1, a13, 4 # f1 = in1.im = *(p1 + 1)
lsi f3, a15, 4 # f3 = in3.im = *(p3 + 1)
add.s f4, f0, f2 # f4 = in0.re + in2.re
sub.s f6, f0, f2 # f6 = in0.re - in2.re
add.s f9, f1, f3 # f9 = in1.im + in3.im
sub.s f11, f1, f3 # f11 = in1.im - in3.im
lsi f0, a13, 0 # f0 = in1.re = *p1
lsi f2, a15, 0 # f2 = in3.re = *p3
lsi f12, a9, 0 # f12 = w0->re
lsi f13, a10, 0 # f13 = w1->re
lsi f14, a11, 0 # f14 = w2->re
add.s f8, f0, f2 # f8 = in1.re + in3.re
sub.s f10, f0, f2 # f10 = in1.re - in3.re
sub.s f1, f5, f9 # f1 = bf2.im = in0.im + in2.im - in1.im - in3.im
add.s f5, f5, f9 # f5 = bf0.im = in0.im + in2.im + in1.im + in3.im
add.s f2, f6, f11 # f2 = bf1.re = in0.re - in2.re + in1.im - in3.im
sub.s f6, f6, f11 # f6 = bf3.re = in0.re - in2.re - in1.im + in3.im
sub.s f0, f4, f8 # f0 = bf2.re = in0.re + in2.re - in1.re - in3.re
add.s f4, f4, f8 # f4 = bf0.re = in0.re + in2.re + in1.re + in3.re
sub.s f3, f7, f10 # f3 = bf1.im = in0.im - in2.im - in1.re + in3.re
add.s f7, f7, f10 # f7 = bf3.im = in0.im - in2.im + in1.re - in3.re
ssi f5, a12, 4 # *(p0 + 1) = f5 = bf0.im
ssip f4, a12, 8 # *p0 = f4 = bf0.re , p0 += 2
mul.s f5, f3, f12 # f5 = bf1.im * w0->re
mul.s f4, f2, f12 # f4 = bf1.re * w0->re
mul.s f9, f1, f13 # f9 = bf2.im * w1->re
mul.s f8, f0, f13 # f8 = bf2.re * w1->re
mul.s f11, f7, f14 # f11 = bf3.im * w2->re
mul.s f10, f6, f14 # f10 = bf3.re * w2->re
lsi f12, a9, 4 # f12 = w0->im
lsi f13, a10, 4 # f13 = w1->im
lsi f14, a11, 4 # f14 = w2->im
addx4 a9, a6, a9 # w0 += m
addx8 a10, a6, a10 # w1 += 2 * m
addx4 a11, a6, a11
addx8 a11, a6, a11 # w2 += 3 * m
msub.s f5, f2, f12 # f5 = bf1.im * w0->re - bf1.re * w0->im
madd.s f4, f3, f12 # f4 = bf1.re * w0->re + bf1.im * w0->im
msub.s f9, f0, f13 # f9 = bf2.im * w1->re - bf2.re * w1->im
madd.s f8, f1, f13 # f8 = bf2.re * w1->re + bf2.im * w1->im
msub.s f11, f6, f14 # f11 = bf3.im * w2->re - bf3.re * w2->im
madd.s f10, f7, f14 # f10 = bf3.re * w2->re + bf3.im * w2->im
ssi f5, a13, 4 # *(p1 + 1) = f5
ssip f4, a13, 8 # *p1 = f4, p1 += 2
ssi f9, a14, 4 # *(p2 + 1) = f9
ssip f8, a14, 8 # *p2 = f8, p2 += 2
ssi f11, a15, 4 # *(p3 + 1) = f11
ssip f10, a15, 8 # *p3 = f10, p3 += 2
.bf4_loop_end:
addi.n a8, a8, 2 # j += 2
bgeu a8, a5, .stage_next # if j >= m
j .group
.stage_next:
slli a5, a5, 2 # m <<= 2
slli a6, a6, 2 # w_step <<= 2
addi.n a7, a7, -1 # log4N--
bnez a7, .stage # if log4N > 0
movi.n a2, DSP_OK # return(DSP_OK)
retw.n
#endif // dsps_fft4r_fc32_ae32_enabled
|
georgevio/IoT-Embedded
| 3,118
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fft/float/dsps_fft2r_fc32_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_fc32_arp4_enabled == 1)
// This is matrix multipliction function for esp32p4 processor.
.text
.align 4
.global dsps_fft2r_fc32_arp4_
.type dsps_fft2r_fc32_arp4_,@function
dsps_fft2r_fc32_arp4_:
//esp_err_t dsps_fft2r_fc32_arp4_(float *data, int N, float* dsps_fft_w_table_fc32)
add sp,sp,-16
#
srli t6, a1, 1 // a6 = N2 = N/2
li t0, 1 // a7 - ie
.fft2r_l1:
li t1, 0 // a8 - j
li t4, 0 // a11 = ia = 0;
.fft2r_l2: // loop for j, a8 - j
slli t3, t1, 3 // a10 = j<<3 // shift for cos () -- c = w[2 * j];
add t3, t3, a2 // a10 - pointer to cos
flw fa0, 0(t3)
flw fa1, 4(t3)
esp.lp.setup 0, t6, .fft2r_l3 // .fft2r_l3 - label to the last executed instruction
add t5, t4, t6 // a12 = m = ia + N2
slli a4, t5, 3 // a14 - pointer for m*2
slli a3, t4, 3 // a13 - pointer for ia*2
add a4, a4, a0 // pointers to data arrays
add a3, a3, a0 //
flw fa4, 0(a4)
flw fa5, 4(a4)
flw fa2, 0(a3)
flw fa3, 4(a3)
fmul.s ft6, fa0, fa4 // re_temp = c * data[2 * m]
fmul.s ft7, fa0, fa5 // im_temp = c * data[2 * m + 1]
fmadd.s ft6, fa1, fa5, ft6 // re_temp += s * data[2 * m + 1];
fnmsub.s ft7, fa1, fa4, ft7 // im_temp -= s * data[2 * m];
fsub.s ft8, fa2, ft6 // = data[2 * ia] - re_temp;
fsub.s ft9, fa3, ft7 // = data[2 * ia + 1] - im_temp;
fadd.s ft10, fa2, ft6 // = data[2 * ia] + re_temp;
fadd.s ft11, fa3, ft7 // = data[2 * ia + 1] + im_temp;
fsw ft8, 0(a4)
fsw ft9, 4(a4)
fsw ft10, 0(a3)
fsw ft11, 4(a3)
.fft2r_l3: add t4, t4, 1 // ia++
add t4, t4, t6
add t1, t1, 1 // j++
BNE t1, t0, .fft2r_l2
slli t0, t0, 1 // ie = ie<<1
srli t6, t6, 1 // a6 = a6>>1
BNEZ t6, .fft2r_l1// Jump if > 0
#
add sp,sp,16
li a0,0
ret
#endif // dsps_fft2r_fc32_arp4_enabled
|
georgevio/IoT-Embedded
| 6,295
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fft/fixed/dsps_fft2r_sc16_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_sc16_ae32_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.global dsps_fft2r_sc16_ae32_
.type dsps_fft2r_sc16_ae32_,@function
.global dsps_fft_w_table_sc16;
//The function implements the following C code:
//esp_err_t dsps_fft2r_sc16_ansi(int16_t *data, int N)
//{
// esp_err_t result = ESP_OK;
// uint32_t *w = (uint32_t*)dsps_fft_w_table_sc16;
// uint32_t *in_data = (uint32_t *)data;
// int ie, ia, m;
// sc16_t temp;
// sc16_t cs;// c - re, s - im
// sc16_t m_data;
// sc16_t a_data;
// ie = 1;
// for (int N2 = N / 2; N2 > 0; N2 >>= 1) {
// ia = 0;
// for (int j = 0; j < ie; j++) {
// cs.data = w[j];
// //c = w[2 * j];
// //s = w[2 * j + 1];
// for (int i = 0; i < N2; i++) {
// m = ia + N2;
// m_data.data = in_data[m];
// a_data.data = in_data[ia];
// sc16_t m1;
// m1.re = xtfixed_bf_1(a_data.re, cs.re, m_data.re, cs.im, m_data.im, 16);//(a_data.re - temp.re + shift_const) >> 1;
// m1.im = xtfixed_bf_2(a_data.im, cs.re, m_data.im, cs.im, m_data.re, 16);//(a_data.im - temp.im + shift_const) >> 1;
// in_data[m] = m1.data;
// sc16_t m2;
// m2.re = xtfixed_bf_3(a_data.re, cs.re, m_data.re, cs.im, m_data.im, 16);//(a_data.re + temp.re + shift_const) >> 1;
// m2.im = xtfixed_bf_4(a_data.im, cs.re, m_data.im, cs.im, m_data.re, 16);//(a_data.im + temp.im + shift_const)>>1;
// in_data[ia] = m2.data;
// ia++;
// }
// ia += N2;
// }
// ie <<= 1;
// }
// return result;
// }
dsps_fft2r_sc16_ae32_:
//esp_err_t dsps_fft2r_sc16_ansi(float *data, int N, float* dsps_fft_w_table_sc16)
entry a1, 16
// Array increment for floating point data should be 4
// data - a2
// N - a3
// dsps_fft_w_table_sc16 - a4 - for now
// a5 - 1, used to initialize acc
// a6 - k, main loop counter; N2 - for (int N2 = N/2; N2 > 0; N2 >>= 1)
// a7 - ie
// a8 - j
// a9 - test
// a10 - (j)<<2, or a10 - j<<2
// a11 - ia
// a12 - m
// a13 - ia pointer
// a14 - m pointer
// a15 - used to shift result
// This instruction are not working. Have to be fixed!!!
// For now theres no solution...
// l32r a4, dsps_fft_w_table_sc16_ae32
// To use ldinc operation we have to prepare a4:
addi a4, a4, -4
addi a9, a2, -4 // prepare input pointer for ldinc operation
ldinc m1, a4 // Load [0x7fff j0] value to the m1
addi a4, a4, -4
// a5 used to load 0x7fff and clear acch/l
movi.n a5, 1 // a5 = 1;
srli a6, a3, 1 // a6 = N2 = N/2
// Load shift register
movi a7, 16
ssr a7
movi a7, 1 // a7 - ie
fft2r_l1:
movi a8, 0 // a8 - j
movi a11,0 // a11 = ia = 0;
fft2r_l2: // loop for j, a8 - j
slli a10, a8, 2 // a10 = j<<2 (4 bytes per address) // shift for cs.data = w[j];
add.n a10, a10, a4 // a10 - pointer to w tables
ldinc m0, a10 // cs.data = w[j];
// here we have m0 and m1
loopnez a6, fft2r_l3
add.n a12, a11, a6 // a12 = m = ia + N2
slli a14, a12, 2 // a14 - pointer for m, m_data.data = in_data[m];
slli a13, a11, 2 // a13 - pointer for ia, a_data.data = in_data[ia];
add.n a14, a14, a9 // pointers to data arrays
add.n a13, a13, a9 // These pointers are -4 from expected values...
ldinc m2, a14 // m_data, a14 += 4; The pointers ready to store data
mul.da.ll m1, a5 // acc = 0x7fff*1
ldinc m3, a13 // ai_data a13 += 4;
// re - l, im - h
muls.dd.ll m0, m2 // acc -= cs.re*m_data.re
mula.dd.ll m1, m3 // acc += 0x7fff*a_data.re
muls.dd.hh m0, m2 // acc -= cs.im*m_data.im
// result in acclo in_data[m].re
rsr a15, acclo
mul.da.ll m1, a5 // acc = 0x7fff*1
sra a15, a15
muls.dd.lh m0, m2 // acc -= cs.re*m_data.im
s16i a15, a14, 0
mula.dd.lh m1, m3 // acc += 0x7fff*a_data.im
mula.dd.hl m0, m2 // acc += cs.im*m_data.re
// result in acclo in_data[m].im
rsr a15, acclo
mul.da.ll m1, a5 // acc = 0x7fff*1
sra a15, a15
mula.dd.ll m0, m2 // acc += cs.re*m_data.re
s16i a15, a14, 2
mula.dd.ll m1, m3 // acc += 0x7fff*a_data.re
mula.dd.hh m0, m2 // acc += cs.im*m_data.im
// result in acclo // in_data[ia].re
rsr a15, acclo
mul.da.ll m1, a5 // acc = 0x7fff*1
sra a15, a15
mula.dd.lh m0, m2 // acc += cs.re*m_data.im
s16i a15, a13, 0
mula.dd.lh m1, m3 // acc += 0x7fff*a_data.im
muls.dd.hl m0, m2 // acc -= cs.im*m_data.re
// result in acclo // in_data[ia].im
rsr a15, acclo
sra a15, a15
s16i a15, a13, 2
// Here we have m0 - w, m2 - m_data, m3 - ai_data,
addi a11, a11, 1// ia++
fft2r_l3:
add a11, a11, a6
addi a8, a8, 1 // j++
BNE a8, a7, fft2r_l2 //
slli a7, a7, 1 // ie = ie<<1
// main loop: for (int k = N/2; k > 0; k >>= 1)
srli a6, a6, 1 // a6 = a6>>1
BNEZ a6, fft2r_l1// Jump if > 0
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_fft2r_sc16_ae32_enabled
|
georgevio/IoT-Embedded
| 4,483
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fft/fixed/dsps_fft2r_sc16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_sc16_arp4_enabled == 1)
// This is matrix multiplication function for esp32p4 processor.
.text
.align 4
.global dsps_fft2r_sc16_arp4_
.type dsps_fft2r_sc16_arp4_,@function
dsps_fft2r_sc16_arp4_:
//esp_err_t dsps_fft2r_sc16_arp4_(int16_t *data, int N, int16_t *w);
add sp,sp,-16
sw s8, 4(sp)
sw s9, 8(sp)
sw s10, 12(sp)
mv a5, a3
li a4, 16
esp.movx.w.sar a4
li a4, 0x7fff
sw a4, 0(sp)
mv x26, sp
esp.vldbc.16.ip q6, x26, 0
#
srli t6, a1, 1 // t6 = N2 = N/2
li t0, 1 // t0 - ie
li t2, 2 // t2 = 2 : limit for the loop N2 > 2
.fft2r_l1:
li t1, 0 // t1 - j
li t4, 0 // t4 = ia = 0;
mv x26, a2 // x26 - pointer to w
.fft2r_l2: // loop for j, a8 - j
esp.vldbc.32.ip q5, x26, 4
add t5, t4, t6 // t5 = m = ia + N2
slli a4, t5, 2 // a4 - pointer for m
slli a3, t4, 2 // a3 - pointer for ia
add a4, a4, a0 // a4 = &data[m*2]
add a3, a3, a0 // a3 = &data[ia*2]
mv x24, a3
mv x25, a4
add t4, t4, t6 // ia += N2 instead of ia++ for each cycle
srli a7, t6, 2 // a7 = t6>> 2
beqz a7, .fft2r_l3_skeep
esp.lp.setup 0, a7, .fft2r_l3 // main butterfly loop
esp.vld.128.ip q0, x25, 0 // Load data[m .. m + 3]
esp.vld.128.ip q2, x24, 0 // Load data[ia .. ia + 3]
esp.cmul.s16 q1, q5, q0, 2
esp.vmul.s16 q2, q2, q6 // q0 = in_data_ia*0x7fff
esp.cmul.s16 q1, q5, q0, 3
esp.vsub.s16 q3, q2, q1 // input[2 * m] = input[2 * ia] - re_temp;
esp.vadd.s16.st.incp q3, x25, q4, q2, q1
.fft2r_l3: esp.vst.128.ip q4, x24, 16
.fft2r_l3_skeep:
add t4, t4, t6 // ia += N2
add t1, t1, 1 // j++
BNE t1, t0, .fft2r_l2
slli t0, t0, 1 // ie = ie<<1
srli t6, t6, 1 // t6 = N2 = N2>>1
bgt t6, t2, .fft2r_l1// N2 > 2
srli t0, t0, 1 // ie = ie>>1
mv x26, a2 // x26 - pointer to w
mv x24, a0
esp.lp.setup 0, t0, .fft2r_l2_1
esp.vldbc.32.ip q2, x26, 4
esp.vldbc.32.ip q7, x26, 4
esp.vunzip.32 q2, q7
esp.vld.l.64.ip q0, x24, 8
esp.vld.l.64.ip q1, x24, 8
esp.vld.h.64.ip q0, x24, 8
esp.vld.h.64.ip q1, x24, -24
esp.vmul.s16 q0, q0, q6
esp.cmul.s16 q3, q2, q1, 2
esp.cmul.s16 q3, q2, q1, 3
esp.vsub.s16 q4, q0, q3
esp.vadd.s16 q5, q0, q3
esp.vst.l.64.ip q5, x24, 8
esp.vst.l.64.ip q4, x24, 8
esp.vst.h.64.ip q5, x24, 8
.fft2r_l2_1: esp.vst.h.64.ip q4, x24, 8
mv x26, a2 // x26 - pointer to w
mv x24, a0
add t0, t0, -1
esp.lp.setup 0, t0, .fft2r_l2_0
esp.vld.128.ip q0, x24, 16 // q0 = ia
esp.vld.128.ip q1, x24,-16 // q1 = m
esp.vld.128.ip q2, x26, 16
esp.vunzip.32 q0, q1
esp.cmul.s16 q3, q2, q1, 2
esp.vmul.s16 q0, q0, q6
esp.cmul.s16 q3, q2, q1, 3
esp.vsub.s16 q1, q0, q3
esp.vadd.s16 q0, q0, q3
esp.vzip.32 q0, q1
esp.vst.128.ip q0, x24, 16
.fft2r_l2_0: esp.vst.128.ip q1, x24, 16
lw s8, 4(sp)
lw s9, 8(sp)
lw s10, 12(sp)
add sp,sp,16
li a0,0
ret
#endif // dsps_fft2r_sc16_arp4_enabled
|
georgevio/IoT-Embedded
| 5,878
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/fft/fixed/dsps_fft2r_sc16_aes3.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_fft2r_platform.h"
#if (dsps_fft2r_sc16_aes3_enabled == 1)
// This is matrix multipliction function for ESP32 processor.
.text
.align 4
.literal_position
.literal .LC0_5_39, dsps_fft2r_sc16_initialized
.literal .LC1_5_40, 32767
.literal .LC2_5_41, 458756
.literal .LC3_5_42, 458753
# Program Unit: dsps_fft2r_sc16_aes3_
.type dsps_fft2r_sc16_aes3_, @function
.align 4
.global dsps_fft2r_sc16_aes3_
dsps_fft2r_sc16_aes3_: # 0x4
# q3 = 16
# temp_round = 0
# temp_round_ptr = 4
.LBB1_dsps_fft2r_sc16_aes3_: # 0x4
.frequency 1.000 0.000
entry a1,64 #
mov.n a10,a3 # [0]
.type dsp_is_power_of_two, @function
call8 dsp_is_power_of_two # [1] dsp_is_power_of_two
beqz.n a10,.LBB4_dsps_fft2r_sc16_aes3_ # [0]
l32r a8,.LC0_5_39 # [0]
l8ui a8,a8,0 # [2] id:207 dsps_fft2r_sc16_initialized+0x0
beqz.n a8,.LBB6_dsps_fft2r_sc16_aes3_ # [4]
mov.n a9,a1 # [0]
l32r a8,.LC1_5_40 # [1]
addi.n a6,a3,1 # [2]
movi.n a10,16 # [3]
wsr.sar a10 # [4]
movgez a6,a3,a3 # [5]
s16i a8,a1,0 # [6] temp_round
ee.vldbc.16.ip q6,a9,0 # [7] id:209
srai a6,a6,1 # [8]
bltui a6,3,.Lt_0_13826 # [9]
movi.n a5,1 # [0]
.Lt_0_9218: # 0x33
mov.n a13,a4 # [0]
mov.n a9,a2 # [1]
beqz.n a5,.Lt_0_9474 # [2]
srli a3,a6,2 # [0]
movi.n a14,0 # [1]
slli a15,a6,2 # [2]
add.n a8,a15,a9 # [3]
.Lt_0_9986: # 0x43
ee.vldbc.32.ip q5,a13,4 # [0] id:215
loopnez a3,.LBB54_dsps_fft2r_sc16_aes3_ # [1]
.LBB52_dsps_fft2r_sc16_aes3_: # 0x49
ee.vld.128.ip q0,a8,0 # [0*II+0] id:217
ee.vld.128.ip q2,a9,0 # [0*II+1] id:216
ee.cmul.s16 q1,q5,q0,2 # [0*II+2]
ee.vmul.s16 q2,q2,q6 # [0*II+3]
ee.cmul.s16 q1,q5,q0,3 # [0*II+4]
ee.vsubs.s16 q3,q2,q1 # [0*II+6]
ee.vadds.s16.st.incp q3,a8,q3,q2,q1 # [0*II+7] id:221
ee.vst.128.ip q3,a9,16 # [0*II+8] id:222
.LBB54_dsps_fft2r_sc16_aes3_: # 0x62
addi.n a14,a14,1 # [0]
add.n a9,a9,a15 # [1]
add.n a8,a15,a9 # [2]
bne a14,a5,.Lt_0_9986 # [3]
.Lt_0_9474: # 0x6b
slli a5,a5,1 # [0]
srli a6,a6,1 # [1]
bgeui a6,3,.Lt_0_9218 # [2]
srli a10,a5,1 # [0]
beqz.n a10,.Lt_0_14594 # [1]
mov.n a9,a4 # [0]
mv.qr q4,q1 # [1]
mov.n a8,a2 # [2]
mv.qr q1,q0 # [3]
mv.qr q0,q2 # [4]
loopnez a10,.LBB76_dsps_fft2r_sc16_aes3_ # [5]
.LBB74_dsps_fft2r_sc16_aes3_: # 0x89
ee.vld.l.64.ip q0,a8,8 # [0*II+0] id:225
ee.vldbc.32.ip q2,a9,4 # [0*II+1] id:223
ee.vld.l.64.ip q1,a8,8 # [0*II+2] id:226
ee.vldbc.32.ip q3,a9,4 # [0*II+3] id:224
ee.vld.h.64.ip q0,a8,8 # [0*II+4] id:227
ee.vunzip.32 q2,q3 # [0*II+5]
ee.vld.h.64.ip q1,a8,-24 # [0*II+6] id:228
ee.vmul.s16 q0,q0,q6 # [0*II+7]
ee.cmul.s16 q4,q2,q1,2 # [0*II+8]
ee.cmul.s16 q4,q2,q1,3 # [0*II+9]
ee.vadds.s16 q2,q0,q4 # [0*II+11]
ee.vsubs.s16 q3,q0,q4 # [0*II+12]
ee.vst.l.64.ip q2,a8,8 # [0*II+13] id:232
ee.vst.l.64.ip q3,a8,8 # [0*II+14] id:233
ee.vst.h.64.ip q2,a8,8 # [0*II+15] id:234
ee.vst.h.64.ip q3,a8,8 # [0*II+16] id:235
.LBB76_dsps_fft2r_sc16_aes3_: # 0xb9
.frequency 0.608 0.000
st.qr q4,a1,16 # [0] q3
.Lt_0_11778: # 0xbc
ld.qr q3,a1,16 # [0] q3
slli a10,a5,1 # [1]
srli a10,a10,2 # [2]
loopnez a10,.LBB98_dsps_fft2r_sc16_aes3_ # [3]
.LBB96_dsps_fft2r_sc16_aes3_: # 0xc8
ee.vld.128.ip q0,a2,16 # [0*II+0] id:237
ee.vld.128.ip q1,a2,-16 # [0*II+1] id:238
ee.vld.128.ip q2,a4,16 # [0*II+2] id:236
ee.vunzip.32 q0,q1 # [0*II+3]
ee.cmul.s16 q3,q2,q1,2 # [0*II+4]
ee.vmul.s16 q0,q0,q6 # [0*II+5]
ee.cmul.s16 q3,q2,q1,3 # [0*II+6]
ee.vsubs.s16 q1,q0,q3 # [0*II+8]
ee.vadds.s16 q0,q0,q3 # [0*II+9]
ee.vzip.32 q0,q1 # [0*II+10]
ee.vst.128.ip q0,a2,16 # [0*II+11] id:242
ee.vst.128.ip q1,a2,16 # [0*II+12] id:243
.LBB98_dsps_fft2r_sc16_aes3_: # 0xec
movi.n a2,0 # [0]
retw.n # [1]
.Lt_0_13826: # 0xf0
movi.n a5,1 # [0]
j .Lt_0_11778 # [1]
.LBB6_dsps_fft2r_sc16_aes3_: # 0xf5
l32r a2,.LC2_5_41 # [0]
retw.n # [1]
.LBB4_dsps_fft2r_sc16_aes3_: # 0xfa
l32r a2,.LC3_5_42 # [0]
retw.n # [1]
.Lt_0_14594: # 0xff
st.qr q1,a1,16 # [0] q3
j .Lt_0_11778 # [1]
#endif // dsps_fft2r_sc16_ae32_enabled
|
georgevio/IoT-Embedded
| 1,777
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/addc/float/dsps_addc_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_addc_platform.h"
#if (dsps_addc_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_addc_f32_ae32
.type dsps_addc_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_addc_f32_ansi(const float *input, float *output, int len, float C, int step_in, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// output[i * step_out] = input[i * step_in] + C;
// }
// return ESP_OK;
// }
dsps_addc_f32_ae32:
// input - a2
// output - a3
// len - a4
// C - a5
// step_in - a6
// step_out - a7
entry a1, 16
slli a6, a6, 2 // a6 - step_in<<2
slli a7, a7, 2 // a7 - step_out<<2
wfr f0, a5 // a5 - load to the f0
loopnez a4, loop_end_addc_f32_ae32
lsi f1, a2, 0
add.s f2, f1, f0 // f2 = f1 + f0
add.n a2, a2, a6 // input1_ptr+=step_in;
ssi f2, a3, 0
add.n a3, a3, a7 // output+=step_out;
loop_end_addc_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_addc_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,051
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/mul/float/dsps_mul_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_mul_platform.h"
#if (dsps_mul_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_mul_f32_ae32
.type dsps_mul_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_mul_f32_ansi(const float *input1, const float *input2, float *output, int len, int step1, int step2, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// output[i * step_out] = input1[i * step1] * input2[i * step2];
// }
// return ESP_OK;
// }
dsps_mul_f32_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step1 - a6
// step2 - a7
// step_out - stack (a8)
entry a1, 16
l32i.n a8, a1, 16 // Load step_out to the a8 register
slli a6, a6, 2 // a6 - step1<<2
slli a7, a7, 2 // a7 - step2<<2
slli a8, a8, 2 // a8 - step_out<<2
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
loopnez a5, loop_end_mul_f32_ae32
lsi f1, a3, 0
add.n a3, a3, a7 // input2_ptr+=step2;
mul.s f2, f1, f0 // f2 = f1*f0
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
ssi f2, a4, 0
add.n a4, a4, a8 // input2_ptr+=step2;
loop_end_mul_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mul_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,993
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/mul/fixed/dsps_mul_s16_ae32.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_mul_platform.h"
#if (dsps_mul_s16_ae32_enabled == 1)
.text
.align 4
.global dsps_mul_s16_ae32
.type dsps_mul_s16_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_mul_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_mul_s16_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
// l32i.n a10, a1, 16
// s16i a10, a4, 0
// l32i.n a10, a1, 20
// s16i a10, a4, 2
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
// s16i a10, a4, 0
// s16i a6, a4, 2
// s16i a7, a4, 4
// s16i a5, a4, 6
l16si a11, a2, 0
l16si a8, a3, 0
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_mul_s16_ae32
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
mull a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_mul_s16_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mul_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 2,961
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/mul/fixed/dsps_mul_s8_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_mul_platform.h"
#if (dsps_mul_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_mul_s8_aes3
.type dsps_mul_s8_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_mul_s8_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_mul_s8_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .sub_s8_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .sub_s8_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.sub_s8_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .sub_s8_ae32_mode // jump if != 0
bany a3, a15, .sub_s8_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0xf // modulo 8 mask
bany a5, a15, .sub_s8_ae32_mode // jump if != 0
// Process main function for S3
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 4
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_mul_s8_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vmul.s8.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_mul_s8_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.sub_s8_ae32_mode:
l8ui a11, a2, 0
l8ui a8, a3, 0
mull a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_mul_s8_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l8ui a11, a2, 0
l8ui a8, a3, 0
s8i a9, a4, 0 // store result to the putput
mull a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_mul_s8_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mul_s8_aes3_enabled
|
georgevio/IoT-Embedded
| 3,230
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/mul/fixed/dsps_mul_s16_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_mul_platform.h"
#if (dsps_mul_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_mul_s16_aes3
.type dsps_mul_s16_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_mul_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_mul_s16_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .mul_s16_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .mul_s16_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.mul_s16_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .mul_s16_ae32_mode // jump if != 0
bany a3, a15, .mul_s16_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0x7 // modulo 8 mask
bany a5, a15, .mul_s16_ae32_mode // jump if != 0
// Process main function for S3
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 3
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_mul_s16_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vmul.s16.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_mul_s16_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.mul_s16_ae32_mode:
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
l16si a11, a2, 0
l16si a8, a3, 0
mull a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_mul_s16_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
mull a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_mul_s16_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mul_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 1,777
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/mulc/float/dsps_mulc_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_mulc_platform.h"
#if (dsps_mulc_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_mulc_f32_ae32
.type dsps_mulc_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_mulc_f32_ansi(const float *input, float *output, int len, float C, int step_in, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// output[i * step_out] = input[i * step_in] * C;
// }
// return ESP_OK;
// }
dsps_mulc_f32_ae32:
// input - a2
// output - a3
// len - a4
// C - a5
// step_in - a6
// step_out - a7
entry a1, 16
slli a6, a6, 2 // a6 - step_in<<2
slli a7, a7, 2 // a7 - step_out<<2
wfr f0, a5 // a5 - load to the f0
loopnez a4, loop_end_mulc_f32_ae32
lsi f1, a2, 0
mul.s f2, f1, f0 // f2 = f1 * f0
add.n a2, a2, a6 // input1_ptr+=step_in;
ssi f2, a3, 0
add.n a3, a3, a7 // output+=step_out;
loop_end_mulc_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mulc_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,481
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/mulc/fixed/dsps_mulc_s16_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_mulc_platform.h"
#if (dsps_mulc_s16_ae32_enabled == 1)
.text
.align 4
.global dsps_mulc_s16_ae32
.type dsps_mulc_s16_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_mulc_f32_ansi(const float *input, float *output, int len, float C, int step_in, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input[i * step_in] * (int32_t)C;
// output[i * step_out] = (int16_t)(acc>>15);
// }
// return ESP_OK;
// }
dsps_mulc_s16_ae32:
// input - a2
// output - a3
// len - a4
// C - a5
// step_in - a6
// step_out - a7
entry a1, 16
movi.n a8, 15 // output shift
ssr a8
srli a4, a4, 1 // a4 = a4>>1
slli a6, a6, 2 // a6 - step_in<<3, because we load two inputs per loop
slli a7, a7, 1 // a7 - step_out<<2
addi a6, a6, -4;
addi a2, a2, -4;
ldinc m0, a2
loopnez a4, loop_end_mulc_f32_ae32
add.n a2, a2, a6 // input+=step_input;
mul.DA.LL m0, a5
rsr a8, acchi
rsr a9, acclo
src a8, a8, a9 // Here result in a8
s16i a8, a3, 0 // store result to the putput
// rsr a9, acclo
// s16i a9, a3, 0 // store result to the putput
add.n a3, a3, a7 // output+=step_out;
mul.DA.HL m0, a5
rsr a8, acchi
rsr a9, acclo
ldinc m0, a2 // load next data
src a10, a8, a9 // Here result in a8
s16i a10, a3, 0 // store result to the putput
// // rsr a9, acclo
// // s16i a9, a3, 0 // store result to the putput
add.n a3, a3, a7 // output+=step_out;
loop_end_mulc_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_mulc_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 2,053
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/sub/float/dsps_sub_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_sub_platform.h"
#if (dsps_sub_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_sub_f32_ae32
.type dsps_sub_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_sub_f32_ae32(const float *input1, const float *input2, float *output, int len, int step1, int step2, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// output[i * step_out] = input1[i * step1] - input2[i * step2];
// }
// return ESP_OK;
// }
dsps_sub_f32_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step1 - a6
// step2 - a7
// step_out - stack (a8)
entry a1, 16
l32i.n a8, a1, 16 // Load step_out to the a8 register
slli a6, a6, 2 // a6 - step1<<2
slli a7, a7, 2 // a7 - step2<<2
slli a8, a8, 2 // a8 - step_out<<2
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
loopnez a5, loop_end_sub_f32_ae32
lsi f1, a3, 0
add.n a3, a3, a7 // input2_ptr+=step2;
sub.s f2, f0, f1 // f2 = f0 - f1
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
ssi f2, a4, 0
add.n a4, a4, a8 // input2_ptr+=step2;
loop_end_sub_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_sub_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,962
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/sub/fixed/dsps_sub_s8_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_sub_platform.h"
#if (dsps_sub_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_sub_s8_aes3
.type dsps_sub_s8_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_sub_s8_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_sub_s8_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .sub_s8_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .sub_s8_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.sub_s8_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .sub_s8_ae32_mode // jump if != 0
bany a3, a15, .sub_s8_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0xf // modulo 8 mask
bany a5, a15, .sub_s8_ae32_mode // jump if != 0
// Process main function for S3
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 4
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_sub_s8_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vsubs.s8.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_sub_s8_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.sub_s8_ae32_mode:
l8ui a11, a2, 0
l8ui a8, a3, 0
sub a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_sub_s8_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l8ui a11, a2, 0
l8ui a8, a3, 0
s8i a9, a4, 0 // store result to the putput
sub a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_sub_s8_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_sub_s8_aes3_enabled
|
georgevio/IoT-Embedded
| 3,231
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/sub/fixed/dsps_sub_s16_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_sub_platform.h"
#if (dsps_sub_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_sub_s16_aes3
.type dsps_sub_s16_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_sub_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_sub_s16_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .sub_s16_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .sub_s16_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.sub_s16_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .sub_s16_ae32_mode // jump if != 0
bany a3, a15, .sub_s16_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0x7 // modulo 8 mask
bany a5, a15, .sub_s16_ae32_mode // jump if != 0
// Process main function for S3
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 3
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_sub_s16_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vsubs.s16.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_sub_s16_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.sub_s16_ae32_mode:
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
l16si a11, a2, 0
l16si a8, a3, 0
sub a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_sub_s16_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
sub a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_sub_s16_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_sub_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 1,992
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/sub/fixed/dsps_sub_s16_ae32.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_sub_platform.h"
#if (dsps_sub_s16_ae32_enabled == 1)
.text
.align 4
.global dsps_sub_s16_ae32
.type dsps_sub_s16_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_sub_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_sub_s16_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
// l32i.n a10, a1, 16
// s16i a10, a4, 0
// l32i.n a10, a1, 20
// s16i a10, a4, 2
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
// s16i a10, a4, 0
// s16i a6, a4, 2
// s16i a7, a4, 4
// s16i a5, a4, 6
l16si a11, a2, 0
l16si a8, a3, 0
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_sub_s16_ae32
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
sub a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_sub_s16_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_sub_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 2,053
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/add/float/dsps_add_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_add_platform.h"
#if (dsps_add_f32_ae32_enabled == 1)
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_add_f32_ae32
.type dsps_add_f32_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_add_f32_ansi(const float *input1, const float *input2, float *output, int len, int step1, int step2, int step_out)
// {
// for (int i = 0 ; i < len ; i++) {
// output[i * step_out] = input1[i * step1] + input2[i * step2];
// }
// return ESP_OK;
// }
dsps_add_f32_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step1 - a6
// step2 - a7
// step_out - stack (a8)
entry a1, 16
l32i.n a8, a1, 16 // Load step_out to the a8 register
slli a6, a6, 2 // a6 - step1<<2
slli a7, a7, 2 // a7 - step2<<2
slli a8, a8, 2 // a8 - step_out<<2
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
loopnez a5, loop_end_add_f32_ae32
lsi f1, a3, 0
add.n a3, a3, a7 // input2_ptr+=step2;
add.s f2, f1, f0 // f2 = f1 + f0
lsi f0, a2, 0
add.n a2, a2, a6 // input1_ptr+=step1;
ssi f2, a4, 0
add.n a4, a4, a8 // input2_ptr+=step2;
loop_end_add_f32_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_add_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 3,232
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/add/fixed/dsps_add_s16_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_add_platform.h"
#if (dsps_add_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_add_s16_aes3
.type dsps_add_s16_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_add_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_add_s16_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .add_s16_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .add_s16_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.add_s16_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .add_s16_ae32_mode // jump if != 0
bany a3, a15, .add_s16_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0x7 // modulo 8 mask
bany a5, a15, .add_s16_ae32_mode // jump if != 0
// Process main function for S3
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 3
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_add_s16_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vadds.s16.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_add_s16_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.add_s16_ae32_mode:
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
l16si a11, a2, 0
l16si a8, a3, 0
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_add_s16_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_add_s16_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_add_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,962
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/add/fixed/dsps_add_s8_aes3.S
|
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dsps_add_platform.h"
#if (dsps_add_s16_aes3_enabled == 1)
.text
.align 4
.global dsps_add_s8_aes3
.type dsps_add_s8_aes3,@function
// The function implements the following C code:
// esp_err_t dsps_add_s8_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_add_s8_aes3:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
// Check if any of steps is not 0
addi a15, a6, -1
bnez a15, .add_s8_ae32_mode // Branch if step !=0
addi a15, a7, -1
bnez a15, .add_s8_ae32_mode // Branch if step !=0
addi a15, a10, -1
bnez a15,.add_s8_ae32_mode // Branch if step !=0
// Check addresses
movi a15, 0xF // modulo 16 mask
bany a2, a15, .add_s8_ae32_mode // jump if != 0
bany a3, a15, .add_s8_ae32_mode // jump if != 0
// Check length (should be divided to 8)
movi a15, 0xf // modulo 8 mask
bany a5, a15, .add_s8_ae32_mode // jump if != 0
// Process main function for S3
wsr.sar a9 // load sar register
// Preload q1 from a3
//ee.vld.128.ip q1, a3, 16
srli a5, a5, 4
ee.vld.128.ip q0, a2, 16
loopnez a5, .loop_end_add_s8_aes3_main
ee.vld.128.ip q1, a3, 16
ee.vadds.s8.ld.incp q0, a2, q4, q0, q1
ee.vst.128.ip q4, a4, 16
.loop_end_add_s8_aes3_main:
// Exit for Esp32s3 mode
movi.n a2, 0 // return status ESP_OK
retw.n
.add_s8_ae32_mode:
l8ui a11, a2, 0
l8ui a8, a3, 0
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_add_s8_aes3
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l8ui a11, a2, 0
l8ui a8, a3, 0
s8i a9, a4, 0 // store result to the putput
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_add_s8_aes3:
// Exit for Esp32 mode
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_add_s8_aes3_enabled
|
georgevio/IoT-Embedded
| 2,494
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/math/add/fixed/dsps_add_s16_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_add_platform.h"
#if (dsps_add_s16_ae32_enabled == 1)
.text
.align 4
.global dsps_add_s16_ae32
.type dsps_add_s16_ae32,@function
// The function implements the following C code:
// esp_err_t dsps_add_s16_ansi(const int16_t *input1, const int16_t *input2, int16_t *output, int len, int step1, int step2, int step_out, int shift)
// {
// for (int i = 0 ; i < len ; i++) {
// int32_t acc = (int32_t)input1[i * step1] + (int32_t)input2[i * step2];
// output[i * step_out] = acc >> shift;
// }
// return ESP_OK;
// }
dsps_add_s16_ae32:
// input1 - a2
// input2 - a3
// output - a4
// len - a5
// step_in1 - a6
// step_in2 - a7
// step_out - stack (a10)
// shift - stack (a9)
entry a1, 16
// l32i.n a10, a1, 16
// s16i a10, a4, 0
// l32i.n a10, a1, 20
// s16i a10, a4, 2
l32i.n a10, a1, 16 // Load step_out to the a10 register
l32i.n a9, a1, 20 // Load shift to the a9 register
ssr a9 // sar = a9
slli a6, a6, 1 // a6 - step_in<<1
slli a7, a7, 1 // a7 - step_in<<1
slli a10, a10, 1 // a8 - step_out<<1
// s16i a10, a4, 0
// s16i a6, a4, 2
// s16i a7, a4, 4
// s16i a5, a4, 6
l16si a11, a2, 0
l16si a8, a3, 0
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
loopnez a5, .loop_end_add_s16_ae32
add.n a2, a2, a6 // input1+=step_in1;
add.n a3, a3, a7 // input2+=step_in2;
l16si a11, a2, 0
l16si a8, a3, 0
s16i a9, a4, 0 // store result to the putput
add a8, a11, a8
srl a9, a8 // a8 = a8>>sar
add.n a4, a4, a10 // output+=step_out;
.loop_end_add_s16_ae32:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_add_s16_ae32_enabled
|
georgevio/IoT-Embedded
| 2,238
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/conv/float/dsps_corr_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_conv_platform.h"
#if (dsps_corr_f32_ae32_enabled == 1)
#include "dsps_dotprod_f32_m_ae32.S"
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_corr_f32_ae32
.type dsps_corr_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_corr_f32_ansi(const float *Signal, const int siglen, const float *Pattern, const int patlen, float *dest)
//{
// for (size_t n = 0; n < (siglen - patlen); n++) {
// float k_corr = 0;
// for (size_t m = 0; m < patlen; m++) {
// k_corr += Signal[n + m] * Pattern[m];
// }
// dest[n] = k_corr;
// }
// return ESP_OK;
//}
dsps_corr_f32_ae32:
// Signal - a2
// siglen - a3
// Pattern - a4
// patlen - a5
// dest - a6
// a11 - loop length
entry a1, 16
// Array increment for floating point data should be 4
movi.n a8, 4
movi.n a13, 4
sub a11, a3, a5 // a11 = loop length
addi a11, a11, 1
addi a12, a2, 0 // move input pointer to the a12
movi.n a9, 0
movi.n a14, 0
corr_loop:
// Clear initial state of the result register
addi a10, a4, 0 // a10 - pattern
movi.n a9, 0 // clear a9
wfr f1, a9 // clrar f1
// a12 - input1
// a10 - input2
// a5 - length
// a8 - 4, step in arrays
// a9 - 0
dotprod_f32_ae32 a12, a10, a5, a9, a8;
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // y++ - increment output pointer
addi a12, a12, 4 // Signal++
addi a11, a11, -1
bnez a11, corr_loop
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_corr_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 3,715
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/conv/float/dsps_ccorr_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_conv_platform.h"
#if (dsps_ccorr_f32_ae32_enabled == 1)
#include "dsps_conv_f32_m_ae32.S"
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_ccorr_f32_ae32
.type dsps_ccorr_f32_ae32,@function
// The function implements the C code from dsps_ccorr_f32_ansi:
//esp_err_t dsps_ccorr_f32_ansi(const float *Signal, const int siglen, const float *Kernel, const int kernlen, float *corrout);
//
dsps_ccorr_f32_ae32:
// Signal - a2
// siglen - a3
// Kernel - a4
// kernlen - a5
// corrout - a6
//
// a11 - loop length
entry a1, 16
// Array increment for floating point data should be 4
sub a10, a3, a5
bgez a10, dsps_ccorr_positive
addi a10, a2, 0
addi a2, a4, 0
addi a4, a10, 0
addi a10, a3, 0
addi a3, a5, 0
addi a5, a10, 0
dsps_ccorr_positive:
movi.n a8, 4
addi a11, a5, 0 // lkern - loop counter
movi.n a14, 0
addi a9, a14, 1
movi.n a7, 4
movi.n a8, -4
mull a13, a5, a7 // a13 - kernlen*4
add a13, a13, a4 // a13 - Kernel[kernlen]
addi a13, a13, -4 // a13 - Kernel[kernlen - 1]
ccorr_loop1:
// Clear initial state of the result register
addi a10, a13, 0 // a10 - Kernel
addi a12, a2, 0 // a12 - Signal
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[0]
// a10 - kern[n];
// a9 - n+1
// a7 - 4,
// a8 - -4,
conv_f32_ae32 a12, a10, a9, a7, a7, loop1
addi a9, a9, 1 // (n+1)++
addi a13, a13, -4 // kern[n] - a4--
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a11, a11, -1
bnez a11, ccorr_loop1
// a11 - loop counter = siglen - kernlen - 1
addi a9, a2, 4 // sig[1] - sig[kmin]
addi a13, a5, 0
// skip loop if 0
sub a11, a3, a5 // a11 - loop counter
beqz a11, skip_ccorr_loop2
ccorr_loop2:
// Clear initial state of the result register
addi a12, a9, 0 // a12 - Signal[kmin]
addi a10, a4, 0 // a10 - Kernel
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[kmin]
// a10 - kern[0];
// a11 - kernlen
// a7 - 4,
conv_f32_ae32 a12, a10, a13, a7, a7, loop2
addi a9, a9, 4 // in1++
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a11, a11, -1
bnez a11, ccorr_loop2
skip_ccorr_loop2:
// a9 - the same
addi a11, a5, -1
addi a13, a5, -1
ccorr_loop3:
// Clear initial state of the result register
addi a12, a9, 0 // a12 - Signal[kmin]
addi a10, a4, 0 // a10 - Kernel
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[kmin]
// a10 - kern[n - kmin];
// a11 - length
// a7 - 4,
// a8 - -4,
conv_f32_ae32 a12, a10, a11, a7, a7, loop3
addi a9, a9, 4 // n++
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a11, a11, -1
bnez a11, ccorr_loop3
skip_ccorr_loop3:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_ccorr_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,309
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/conv/float/dsps_conv_f32_m_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro conv_f32_ae32 x1 x2 count step1 step2 name
// This macro calculates floating point dot product for count float samples
// x1, x2 - input arrays
// count - amount of samples
// step1 - start step
//,step2 - A register for array step increment. (should be divided by 4)
// f1 - contains initial value
//
// result in f1
//
// Macros body:
// f1 += x1[]*x2[]; i: 0..counter-1
// affected: f0, f1, f2
// Example: conv_f32_ae32 a2 a3 a5 a8 a9
// a8 == 4, step is 4 bytes
// a5 == 32, length of array is 32
//
lsxp f0, \x2, \step2
loopnez \count, loop_mac_end_m_ae32\name
lsxp f2, \x1, \step1
madd.s f1, f2, f0
lsxp f0, \x2, \step2
loop_mac_end_m_ae32\name:
.endm
|
georgevio/IoT-Embedded
| 3,716
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/conv/float/dsps_conv_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_conv_platform.h"
#if (dsps_conv_f32_ae32_enabled == 1)
#include "dsps_conv_f32_m_ae32.S"
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_conv_f32_ae32
.type dsps_conv_f32_ae32,@function
// The function implements the C code from dsps_conv_f32_ansi:
//esp_err_t dsps_conv_f32_ansi(const float *Signal, const int siglen, const float *Kernel, const int kernlen, float *convout);
//
dsps_conv_f32_ae32:
// Signal - a2
// siglen - a3
// Kernel - a4
// kernlen - a5
// convout - a6
//
// a11 - loop length
entry a1, 16
// Array increment for floating point data should be 4
sub a10, a3, a5
bgez a10, dsps_conv_positive
addi a10, a2, 0
addi a2, a4, 0
addi a4, a10, 0
addi a10, a3, 0
addi a3, a5, 0
addi a5, a10, 0
dsps_conv_positive:
movi.n a8, 4
addi a11, a5, 0 // lkern - loop counter
movi.n a14, 0
addi a9, a14, 1
movi.n a7, 4
movi.n a8, -4
conv_loop1:
// Clear initial state of the result register
addi a10, a4, 0 // a10 - Kernel
addi a12, a2, 0 // a12 - Signal
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[0]
// a10 - kern[n];
// a9 - n+1
// a7 - 4,
// a8 - -4,
conv_f32_ae32 a12, a10, a9, a7, a8, loop1
addi a9, a9, 1 // (n+1)++
addi a4, a4, 4 // kern[n] - a4++
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a11, a11, -1
bnez a11, conv_loop1
// a11 - loop counter = siglen - kernlen - 1
addi a9, a2, 0 // sig[1] - sig[kmin]
addi a13, a5, 0
// skip loop if 0
sub a11, a3, a5 // a11 - loop counter
beqz a11, skip_conv_loop2
conv_loop2:
// Clear initial state of the result register
addi a12, a9, 4 // a12 - Signal[kmin]
addi a10, a4, -4 // a10 - Kernel
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[kmin]
// a10 - kern[n - kmin];
// a11 - length
// a7 - 4,
// a8 - -4,
conv_f32_ae32 a12, a10, a13, a7, a8, loop2
addi a9, a9, 4 // (n+1)++
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a11, a11, -1
bnez a11, conv_loop2
skip_conv_loop2:
// sub a11, a3, a5 // a11 - loop counter
// beqz a11, skip_conv_loop3
// a9 - the same
addi a11, a5, -1
addi a13, a5, -1
// beqz a11, skip_conv_loop3
conv_loop3:
// Clear initial state of the result register
addi a12, a9, 4 // a12 - Signal[kmin]
addi a10, a4, -4 // a10 - Kernel
wfr f1, a14 // clear output: convout[n] = 0;
// a12 - sig[kmin]
// a10 - kern[n - kmin];
// a11 - length
// a7 - 4,
// a8 - -4,
conv_f32_ae32 a12, a10, a13, a7, a8, loop3
addi a9, a9, 4 // (n+1)++
ssi f1, a6, 0 // Store result from f1 to memory at a6
addi a6, a6, 4 // convout++ - increment output pointer
addi a13, a13, -1
addi a11, a11, -1
bnez a11, conv_loop3
skip_conv_loop3:
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dsps_conv_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,926
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprod_f32_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dsps_dotprod_f32_arp4_enabled == 1)
.text
.align 4
.global dsps_dotprod_f32_arp4
.type dsps_dotprod_f32_arp4,@function
// The function implements the following C code:
//esp_err_t dsps_dotprod_f32(const float* src1, const float* src2, float* dest, int len)
//{
// float acc = 0;
// for (int i=0 ; i< len ; i++)
// {
// acc += src1[i]*src2[i];
// }
// *dest = acc;
// return ESP_OK;
//}
dsps_dotprod_f32_arp4:
// src1 - a0
// src2 - a1
// dest - a2
// len - a3
add sp,sp,-16
fmv.w.x fa2,zero
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, 4
add a1, a1, 4
li a4, 2
ble a3, a4, .loop_less_2
// Loop when len > 2
esp.lp.setup 0, a3, .dotprod_loop
fmadd.s fa2, fa0, fa1, fa2
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, 4
.dotprod_loop: add a1, a1, 4
fsw fa2, 0(a2)
add sp,sp,16
li a0,0
ret
// Loop when len <=2
.loop_less_2:
fmadd.s fa2, fa0, fa1, fa2
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, 4
add a1, a1, 4
add a3, a3, -1
bnez a3, .loop_less_2
fsw fa2, 0(a2)
add sp,sp,16
li a0,0
ret
#endif // dotprode_f32_arp4_enabled
|
georgevio/IoT-Embedded
| 1,942
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprode_f32_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dsps_dotprod_f32_arp4_enabled == 1)
.text
.align 4
.global dsps_dotprode_f32_arp4
.type dsps_dotprode_f32_arp4,@function
// The function implements the following C code:
//esp_err_t dsps_dotprode_f32(const float *src1, const float *src2, float *dest, int len, int step1, int step2)
//{
// float acc = 0;
// for (int i = 0 ; i < len ; i++) {
// acc += src1[i * step1] * src2[i * step2];
// }
// *dest = acc;
// return ESP_OK;
//}
dsps_dotprode_f32_arp4:
// src1 - a0
// src2 - a1
// dest - a2
// len - a3
add sp,sp,-16
fmv.w.x fa2,zero
slli a4, a4, 2 // step address increment by 4
slli a5, a5, 2 // step address increment by 4
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, a4
add a1, a1, a5
li a6, 2
ble a3, a6, .loop_less_2
// Loop when len > 2
esp.lp.setup 0, a3, .dotprod_loop
fmadd.s fa2, fa0, fa1, fa2
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, a4
.dotprod_loop: add a1, a1, a5
fsw fa2, 0(a2)
add sp,sp,16
li a0,0
ret
// Loop when len <=2
.loop_less_2:
fmadd.s fa2, fa0, fa1, fa2
flw fa0, 0(a0)
flw fa1, 0(a1)
add a0, a0, a4
add a1, a1, a5
add a3, a3, -1
bnez a3, .loop_less_2
fsw fa2, 0(a2)
add sp,sp,16
li a0,0
ret
#endif // dotprode_f32_arp4_enabled
|
georgevio/IoT-Embedded
| 1,732
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprod_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dotprod_f32_ae32_enabled == 1)
#include "dsps_dotprod_f32_m_ae32.S"
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_dotprod_f32_ae32
.global .dsps_dotprod_f32_ae32_body
.type dsps_dotprod_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_dotprod_f32_ae32(const float* src1, const float* src2, float* dest, int len)
//{
// float acc = 0;
// for (int i=0 ; i< len ; i++)
// {
// acc += src1[i]*src2[i];
// }
// *dest = acc;
// return ESP_OK;
//}
dsps_dotprod_f32_ae32:
// src1 - a2
// src2 - a3
// dest - a4
// len - a5
entry a1, 16
.dsps_dotprod_f32_ae32_body:
// Array increment for floating point data should be 4
movi.n a8, 4
// Clear initial state of the result register
movi.n a9, 0
wfr f1, a9
// a2 - input1
// a3 - input2
// a5 - length
// a8 - 4, step in arrays
dotprod_f32_ae32 a2, a3, a5, a9, a8;
ssi f1, a4, 0 // Store result from f1 to memory at a4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dotprode_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,719
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprode_f32_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dotprode_f32_ae32_enabled == 1)
#include "dsps_dotprode_f32_m_ae32.S"
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_dotprode_f32_ae32
.type dsps_dotprode_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_dotprod_f32_ae32(const float* src1, const float* src2, float* dest, int len)
//{
// float acc = 0;
// for (int i=0 ; i< len ; i++)
// {
// acc += src1[i]*src2[i];
// }
// *dest = acc;
// return ESP_OK;
//}
dsps_dotprode_f32_ae32:
// src1 - a2
// src2 - a3
// dest - a4
// len - a5
// step1- a6
// step2- a7
entry a1, 16
// Array increment for floating point data should be 4
slli a6,a6, 2
slli a7,a7, 2
// Clear initial state of the result register
movi.n a9, 0
wfr f1, a9
// a2 - input1
// a3 - input2
// a5 - length
// a6,a7, step in arrays
dotprode_f32_ae32 a2, a3, a5, a6, a7;
ssi f1, a4, 0 // Store result from f1 to memory at a4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif //dotprode_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 2,242
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprod_f32_aes3.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_dotprod_platform.h"
#if (dsps_dotprod_f32_aes3_enabled == 1)
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_dotprod_f32_aes3
.global .dsps_dotprod_f32_ae32_body
.type dsps_dotprod_f32_aes3,@function
// The function implements the following C code:
//esp_err_t dsps_dotprod_f32_ae32(const float* src1, const float* src2, float* dest, int len)
//{
// float acc = 0;
// for (int i=0 ; i< len ; i++)
// {
// acc += src1[i]*src2[i];
// }
// *dest = acc;
// return ESP_OK;
//}
dsps_dotprod_f32_aes3:
// src1 - a2
// src2 - a3
// dest - a4
// len - a5
entry a1, 16
// Check length and align
movi.n a10, 3
and a10, a10, a5
movi.n a9, 15
or a11, a3, a2
and a11, a9, a11
or a10, a10, a11
beqz a10, .dsps_dotprod_f32_aes3_body
// Call Esp32 function
J .dsps_dotprod_f32_ae32_body
.dsps_dotprod_f32_aes3_body:
// Clear initial state of the result register
movi.n a9, 0
wfr f0, a9
wfr f1, a9
wfr f2, a9
wfr f3, a9
// a2 - input1
// a3 - input2
// a5 - length
srli a6, a5, 2 // N count
// lsx f0, a2, a9
loopnez a6, .loop_mac_end_m_ae32
EE.LDF.128.IP f11, f10, f9, f8, a2, 16
EE.LDF.128.IP f7, f6, f5, f4, a3, 16
madd.s f0, f4, f8 // f0 = X11*Y11
madd.s f1, f5, f9 // f1 = X12*Y11
madd.s f2, f6, f10 // f2 = X13*Y11
madd.s f3, f7, f11 // f3 = X14*Y11
.loop_mac_end_m_ae32:
add.s f0, f0, f1
add.s f0, f0, f2
add.s f0, f0, f3
ssi f0, a4, 0 // Store result from f1 to memory at a4
movi.n a2, 0 // return status ESP_OK
retw.n
#endif // dotprode_f32_ae32_enabled
|
georgevio/IoT-Embedded
| 1,440
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprod_f32_m_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro dotprod_f32_ae32 x1 x2 count step1 step2
// This macro calculates floating point dot product for count float samples
// x1, x2 - input arrays
// count - amount of samples
// step1 - start step
//,step2 - A register for array step increment. (should be divided by 4)
// f1 - contains initial value
//
// result in f1
//
// Macros body:
// f1 += x1[i*step1]*x2[i*step2]; i: 0..counter-1
// affected: f0, f1, f2
// Example: dotprod_f32_ae32 a2 a3 a5 a8 a9
// a8 == 4, step is 4 bytes
// a5 == 32, length of array is 32
//
// mov \step1, \step2
lsx f0, \x2, \step1
// sub \x1, \x1, \step1 // To compensate first increment
loopnez \count, .loop_mac_end_m_ae32
lsx f2, \x1, \step1
madd.s f1, f2, f0
add.n \step1, \step1, \step2
lsx f0, \x2, \step1
.loop_mac_end_m_ae32:
.endm
|
georgevio/IoT-Embedded
| 1,387
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/float/dsps_dotprode_f32_m_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro dotprode_f32_ae32 x1 x2 count step1 step2
// This macro calculates floating point dot product for count float samples
// x1, x2 - input arrays
// count - amount of samples
// step1,step2 - A register for array step. (should be divided by 4)
// f1 - contains initial value
//
// result in f1
//
// Macros body:
// f1 += x1[i*step1]*x2[i*step2]; i: 0..counter-1
// affected: f0, f1, f2
// Example: dotprod_f32_ae32 a2 a3 a5 a8 a9
// a8 == 4, step is 4 bytes
// a5 == 32, length of array is 32
//
lsi f0, \x2, 0
sub \x1, \x1, \step1 // To compensate first increment
loopnez \count, .loop_mace_end_m_ae32
add.n \x1, \x1, \step1
lsi f2, \x1, 0
madd.s f1, f2, f0
add.n \x2, \x2, \step2
lsi f0, \x2, 0
.loop_mace_end_m_ae32:
.endm
|
georgevio/IoT-Embedded
| 14,933
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_s16_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_53, 458755
# Program Unit: dspi_dotprod_s16_aes3
.type dspi_dotprod_s16_aes3, @function
.align 4
.global dspi_dotprod_s16_aes3
dspi_dotprod_s16_aes3: # 0x4
.LBB1_dspi_dotprod_s16_aes3: # 0x4
entry a1,64 #
l32i.n a10,a2,4 # [0] id:678
l32i.n a11,a2,12 # [1] id:677
mull a8,a10,a5 # [2]
blt a11,a8,.LBB81_dspi_dotprod_s16_aes3 # [4]
l32i.n a12,a2,8 # [0] id:679
l32i.n a9,a2,16 # [1] id:680
mull a13,a12,a6 # [2]
blt a9,a13,.LBB81_dspi_dotprod_s16_aes3 # [4]
l32i.n a15,a3,4 # [0] id:682
l32i.n a14,a3,12 # [1] id:681
mull a13,a15,a5 # [2]
blt a14,a13,.LBB81_dspi_dotprod_s16_aes3 # [4]
l32i.n a8,a3,16 # [0] id:684
l32i.n a9,a3,8 # [1] id:683
s32i.n a9,a1,24 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB81_dspi_dotprod_s16_aes3 # [5]
l32i.n a8,a3,0 # [0] id:685
s32i.n a8,a1,20 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_34050 # [2]
bne a14,a13,.Lt_0_34050 # [0]
bnei a15,1,.Lt_0_34050 # [0]
l32i.n a9,a1,24 # [0] gra_spill_temp_2
beqi a9,1,.Lt_0_18178 # [2]
.Lt_0_34050: # 0x43
.Lt_0_18434: # 0x43
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
.type dspi_dotprod_s16_ansi, @function
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB81_dspi_dotprod_s16_aes3: # 0x56
l32r a2,.LC0_1_53 # [0]
retw.n # [1]
.Lt_0_18178: # 0x5b
addi.n a13,a10,-1 # [0]
bnez a13,.Lt_0_34818 # [1]
addi.n a14,a12,-1 # [0]
bnez a14,.Lt_0_34818 # [1]
extui a15,a5,0,3 # [0]
bnez.n a15,.Lt_0_34818 # [1]
blti a6,4,.Lt_0_34818 # [0]
movi.n a8,32 # [0]
bge a8,a5,.Lt_0_35330 # [1]
extui a9,a5,0,1 # [0]
bnez a9,.LBB28_dspi_dotprod_s16_aes3 # [1]
.Lt_0_35330: # 0x78
.Lt_0_20226: # 0x78
mov.n a3,a6 # [0]
addi a10,a5,-24 # [1]
mull a13,a11,a12 # [2]
l32i.n a15,a1,20 # [3] gra_spill_temp_1
l32i.n a2,a2,0 # [4] id:686
movi.n a14,0 # [5]
wur.sar_byte a14 # [6]
wur.accx_0 a14 # [8]
wur.accx_1 a14 # [9]
ee.vld.128.ip q0,a15,16 # [10] id:690
slli a13,a13,1 # [11]
s32i.n a13,a1,16 # [12] gra_spill_temp_0
beqz a10,.LBB32_dspi_dotprod_s16_aes3 # [13]
.Lt_0_23298: # 0x99
.Lt_0_22786: # 0x99
addi a8,a5,-16 # [0]
beqz a8,.LBB38_dspi_dotprod_s16_aes3 # [1]
.Lt_0_24834: # 0x9f
.Lt_0_24322: # 0x9f
addi a9,a5,-8 # [0]
beqz a9,.LBB44_dspi_dotprod_s16_aes3 # [1]
.Lt_0_26370: # 0xa5
.Lt_0_25858: # 0xa5
addi a10,a5,-32 # [0]
beqz a10,.LBB50_dspi_dotprod_s16_aes3 # [1]
.Lt_0_27906: # 0xab
.Lt_0_27394: # 0xab
addi a11,a5,-64 # [0]
beqz a11,.LBB56_dspi_dotprod_s16_aes3 # [1]
movi.n a12,64 # [0]
bge a12,a5,.Lt_0_30722 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a2,16 # [1] id:762
ee.ld.128.usar.ip q2,a2,16 # [2] id:763
ee.src.q.ld.ip q3,a2,16,q1,q2 # [4] id:764
beqz.n a3,.Lt_0_30722 # [5]
slli a8,a5,1 # [0]
l32i.n a14,a1,16 # [1] gra_spill_temp_0
addi a13,a5,31 # [2]
movgez a13,a5,a5 # [3]
srai a13,a13,5 # [4]
sub a14,a14,a8 # [5]
addi a14,a14,16 # [6]
addi.n a13,a13,-1 # [7]
.Lt_0_31490: # 0xd9
addi.n a12,a12,1 # [0]
movi.n a9,32 # [1]
beqz.n a13,.Lt_0_31746 # [2]
loopnez a13,.LBB221_dspi_dotprod_s16_aes3 # [0]
.LBB219_dspi_dotprod_s16_aes3: # 0xe2
ee.vld.128.ip q5,a15,16 # [0*II+0] id:766
ee.vmulas.s16.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:765
ee.vld.128.ip q0,a15,16 # [0*II+2] id:768
ee.vmulas.s16.accx.ld.ip.qup q1,a2,16,q5,q2,q3,q4 # [0*II+3] id:767
ee.vld.128.ip q5,a15,16 # [0*II+4] id:770
ee.vmulas.s16.accx.ld.ip.qup q2,a2,16,q0,q3,q4,q1 # [0*II+5] id:769
ee.vld.128.ip q0,a15,16 # [0*II+6] id:772
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+7] id:771
.LBB221_dspi_dotprod_s16_aes3: # 0xfe
.Lt_0_31746: # 0xfe
ee.vmulas.s16.accx.ld.ip.qup q5,a2,16,q0,q1,q2,q3 # [0] id:773
movi.n a10,-16 # [1]
ee.vld.128.ip q0,a15,16 # [2] id:774
ee.vld.128.ip q6,a15,16 # [3] id:776
ee.vmulas.s16.accx.ld.xp.qup q7,a2,a14,q0,q2,q3,q5 # [4] id:775
ee.vld.128.ip q4,a15,16 # [5] id:779
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a10,q6,q3,q5,q7 # [6] id:777
ee.ld.128.usar.xp q1,a2,a9 # [7] id:778
ee.vld.128.ip q0,a15,16 # [8] id:781
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q4,q5,q1,q2 # [9] id:780
bne a12,a3,.Lt_0_31490 # [10]
.Lt_0_30722: # 0x122
.Lt_0_30466: # 0x122
rur.accx_0 a9 # [0]
rur.accx_1 a10 # [1]
blti a7,1,.Lt_0_33282 # [2]
movi.n a2,0 # [0]
addi a13,a7,-33 # [1]
addi.n a14,a7,-1 # [2]
ssr a14 # [3]
sra a12,a10 # [4]
src a11,a10,a9 # [5]
movgez a11,a12,a13 # [6]
addi.n a11,a11,1 # [7]
srai a11,a11,1 # [8]
s16i a11,a4,0 # [9] id:787
retw.n # [10]
.Lt_0_34818: # 0x148
.Lt_0_19458: # 0x148
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB32_dspi_dotprod_s16_aes3: # 0x15b
ee.ld.128.usar.ip q1,a2,16 # [0] id:691
ee.ld.128.usar.ip q2,a2,16 # [1] id:692
ee.src.q.ld.ip q3,a2,16,q1,q2 # [3] id:693
beqz.n a6,.Lt_0_23298 # [4]
addi a12,a13,-32 # [0]
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
loopgtz a6,.LBB107_dspi_dotprod_s16_aes3 # [3]
.LBB105_dspi_dotprod_s16_aes3: # 0x170
ee.vld.128.ip q4,a15,16 # [0*II+0] id:695
ee.vmulas.s16.accx.ld.xp.qup q1,a2,a12,q0,q1,q2,q3 # [0*II+1] id:694
ee.vld.128.ip q5,a15,16 # [0*II+2] id:697
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q4,q2,q3,q1 # [0*II+3] id:696
ee.ld.128.usar.xp q1,a2,a10 # [0*II+4] id:698
ee.vld.128.ip q0,a15,16 # [0*II+5] id:700
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q5,q3,q1,q2 # [0*II+6] id:699
.LBB107_dspi_dotprod_s16_aes3: # 0x188
j .Lt_0_23298 # [0]
.LBB38_dspi_dotprod_s16_aes3: # 0x18b
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
srli a3,a6,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:701
ee.ld.128.usar.ip q2,a2,16 # [5] id:702
addi a12,a12,-16 # [7]
ee.src.q.ld.xp q3,a2,a12,q1,q2 # [8] id:703
loopnez a3,.LBB130_dspi_dotprod_s16_aes3 # [9]
.LBB128_dspi_dotprod_s16_aes3: # 0x1a3
ee.vld.128.ip q4,a15,16 # [0*II+0] id:705
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a11,q0,q1,q2,q3 # [0*II+1] id:704
ee.ld.128.usar.xp q1,a2,a10 # [0*II+2] id:706
ee.vld.128.ip q0,a15,16 # [0*II+3] id:708
ee.vmulas.s16.accx.ld.xp.qup q4,a2,a12,q4,q2,q1,q3 # [0*II+4] id:707
ee.vld.128.ip q5,a15,16 # [0*II+5] id:710
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q0,q1,q3,q4 # [0*II+6] id:709
ee.ld.128.usar.xp q1,a2,a10 # [0*II+7] id:711
ee.vld.128.ip q0,a15,16 # [0*II+8] id:713
ee.vmulas.s16.accx.ld.xp.qup q3,a2,a12,q5,q3,q1,q2 # [0*II+9] id:712
.LBB130_dspi_dotprod_s16_aes3: # 0x1c5
j .Lt_0_24834 # [0]
.LBB44_dspi_dotprod_s16_aes3: # 0x1c8
srli a3,a3,2 # [0]
movi.n a10,-16 # [1]
l32i.n a11,a1,16 # [2] gra_spill_temp_0
addi a8,a2,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a8,a10 # [5] id:714
ee.ld.128.usar.xp q1,a8,a11 # [6] id:715
ee.src.q.ld.xp q3,a8,a10,q1,q2 # [8] id:716
ee.ld.128.usar.xp q2,a8,a11 # [9] id:717
loopnez a3,.LBB153_dspi_dotprod_s16_aes3 # [10]
.LBB151_dspi_dotprod_s16_aes3: # 0x1e4
ee.vld.128.ip q4,a15,16 # [0*II+0] id:719
ee.vmulas.s16.accx.ld.xp.qup q3,a8,a10,q0,q1,q2,q3 # [0*II+1] id:718
ee.ld.128.usar.xp q1,a8,a11 # [0*II+2] id:720
ee.vld.128.ip q0,a15,16 # [0*II+3] id:722
ee.vmulas.s16.accx.ld.xp.qup q4,a8,a10,q4,q2,q1,q3 # [0*II+4] id:721
ee.ld.128.usar.xp q3,a8,a11 # [0*II+5] id:723
ee.vld.128.ip q5,a15,16 # [0*II+6] id:725
ee.vmulas.s16.accx.ld.xp.qup q4,a8,a10,q0,q1,q3,q4 # [0*II+7] id:724
ee.ld.128.usar.xp q1,a8,a11 # [0*II+8] id:726
ee.vld.128.ip q0,a15,16 # [0*II+9] id:728
ee.vmulas.s16.accx.ld.xp.qup q3,a8,a10,q5,q3,q1,q4 # [0*II+10] id:727
ee.ld.128.usar.xp q2,a8,a11 # [0*II+11] id:729
.LBB153_dspi_dotprod_s16_aes3: # 0x20c
mov.n a2,a8 # [0]
j .Lt_0_26370 # [1]
.LBB50_dspi_dotprod_s16_aes3: # 0x211
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:730
ee.ld.128.usar.ip q2,a2,16 # [5] id:731
sub a12,a12,a13 # [6]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [8] id:732
addi a12,a12,16 # [9]
loopnez a3,.LBB176_dspi_dotprod_s16_aes3 # [10]
.LBB174_dspi_dotprod_s16_aes3: # 0x22c
ee.vld.128.ip q5,a15,16 # [0*II+0] id:734
ee.vmulas.s16.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:733
ee.vld.128.ip q1,a15,16 # [0*II+2] id:736
ee.vmulas.s16.accx.ld.xp.qup q0,a2,a12,q5,q2,q3,q4 # [0*II+3] id:735
ee.vld.128.ip q5,a15,16 # [0*II+4] id:739
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q1,q3,q4,q0 # [0*II+5] id:737
ee.ld.128.usar.xp q1,a2,a10 # [0*II+6] id:738
ee.vld.128.ip q0,a15,16 # [0*II+7] id:741
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+8] id:740
.LBB176_dspi_dotprod_s16_aes3: # 0x24b
j .Lt_0_27906 # [0]
.LBB56_dspi_dotprod_s16_aes3: # 0x24e
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i.n a12,a1,16 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:742
ee.ld.128.usar.ip q2,a2,16 # [5] id:743
sub a12,a12,a13 # [7]
addi a12,a12,16 # [8]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [9] id:744
loopnez a3,.LBB198_dspi_dotprod_s16_aes3 # [10]
.LBB196_dspi_dotprod_s16_aes3: # 0x269
ee.vld.128.ip q4,a15,16 # [0*II+0] id:746
ee.vmulas.s16.accx.ld.ip.qup q1,a2,16,q0,q1,q2,q3 # [0*II+1] id:745
ee.vld.128.ip q0,a15,16 # [0*II+2] id:748
ee.vmulas.s16.accx.ld.ip.qup q4,a2,16,q4,q2,q3,q1 # [0*II+3] id:747
ee.vld.128.ip q5,a15,16 # [0*II+4] id:750
ee.vmulas.s16.accx.ld.ip.qup q0,a2,16,q0,q3,q1,q4 # [0*II+5] id:749
ee.vld.128.ip q6,a15,16 # [0*II+6] id:752
ee.vmulas.s16.accx.ld.ip.qup q1,a2,16,q5,q1,q4,q0 # [0*II+7] id:751
ee.vld.128.ip q5,a15,16 # [0*II+8] id:754
ee.vmulas.s16.accx.ld.ip.qup q4,a2,16,q6,q4,q0,q1 # [0*II+9] id:753
ee.vld.128.ip q6,a15,16 # [0*II+10] id:756
ee.vmulas.s16.accx.ld.xp.qup q0,a2,a12,q5,q0,q1,q4 # [0*II+11] id:755
ee.vld.128.ip q5,a15,16 # [0*II+12] id:759
ee.vmulas.s16.accx.ld.xp.qup q2,a2,a11,q6,q1,q4,q0 # [0*II+13] id:757
ee.ld.128.usar.xp q1,a2,a10 # [0*II+14] id:758
ee.vld.128.ip q0,a15,16 # [0*II+15] id:761
ee.vmulas.s16.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+16] id:760
.LBB198_dspi_dotprod_s16_aes3: # 0x2a4
j .Lt_0_30722 # [0]
.Lt_0_33282: # 0x2a7
movi.n a2,0 # [0]
sext a14,a9,15 # [1]
s16i a14,a4,0 # [2] id:788
retw.n # [3]
.LBB28_dspi_dotprod_s16_aes3: # 0x2b1
mov.n a15,a7 # [0]
mov.n a14,a6 # [1]
mov.n a13,a5 # [2]
mov.n a12,a4 # [3]
mov.n a11,a3 # [4]
mov.n a10,a2 # [5]
call8 dspi_dotprod_s16_ansi # [6] dspi_dotprod_s16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,649
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_s8_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_s8_arp4
.global dspi_dotprod_s8_ansi
.type dspi_dotprod_s8_arp4,@function
// esp_err_t dspi_dotprod_s8_arp4(image2d_t *in_image, image2d_t *filter, int16_t *out_value, int count_x, int count_y, int shift);
dspi_dotprod_s8_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 15
or t1, t1, t2
beqz t1, .dspi_dotprod_s8_arp4_body
j dspi_dotprod_s8_ansi
.dspi_dotprod_s8_arp4_body:
add sp, sp, -16
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
srli t6, a3, 4 // t5 = len/16
addi a6, a5, -1
li t4, 1
sll t4, t4, a6
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q0, t4, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q1, t5, 16 // q1 - f_data
.loop_count_x: esp.vmulas.s8.xacc.ld.ip q0, t4, 16, q0, q1 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.s.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 2,718
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_u16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_u16_arp4
.global dspi_dotprod_u16_ansi
.type dspi_dotprod_u16_arp4,@function
// esp_err_t dspi_dotprod_u16_arp4(image2d_t *in_image, image2d_t *filter, uint16_t *out_value, int count_x, int count_y, int shift);
dspi_dotprod_u16_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// t4 - current i_data
// t5 - current f_data
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 7
or t1, t1, t2
beqz t1, .dspi_dotprod_u16_arp4_body
j dspi_dotprod_u16_ansi
.dspi_dotprod_u16_arp4_body:
add sp, sp, -16
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
slli t2, t2, 1 // i_step = i_step<<1
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
slli t3, t3, 1 // f_step = f_step<<1
srli t6, a3, 3 // t5 = len/8
addi a6, a5, -1
li t4, 1
sll t4, t4, a6
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q0, t4, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q1, t5, 16 // q1 - f_data
.loop_count_x: esp.vmulas.u16.xacc.ld.ip q0, t4, 16, q0, q1 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.u.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 3,555
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dsps_dotprod_s16_m_ae32.S
|
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro dotprod_s16_ae32 x1, x2, count
// This macro calculates fixed point dot product for ((count + 1)*4) int16 samples
// x1 - input array1 register (for example a2)
// x2 - input array2 register (for example a3)
// count - counter register (for example a7)
// count - samples_count / 4 - 1
// acc += x1[i + 0]*x2[i + 0] + x1[i + 1]*x2[i + 1] + x1[i + 2]*x2[i + 2] + x1[i + 3]*x2[i + 3]; i: 0..count
// acchi, and acclo have to be initialize before
// Result - acchi || acclo
// Modifies:
// m0, m1, m2, m3
// acchi || acclo - must be loaded before (for example 0x3fff to acclo).
/*
* Data schedule. Each line represents instruction, columns represent
* register contents. Last column (MUL) shows the multiplication which
* takes place. Values loaded in the given cycle are shown in square brackets.
*
* m0 m1 m2 m3 MUL
* --------- pre-load ------------
*[x0 x1] (no MULs in the first 3 instructions)
* x0 x1 [y0 y1]
* x0 x1 [x2 x3] y0 y1
* x0 x1 x2 x3 y0 y1 [y2 y3] x0*y0
* ---------- loop -------------- (the following 4 instructions are
*[x4 x5] x2 x3 y0 y1 y2 y3 x1*y1 repeated as much as needed)
* x4 x5 x2 x3 [y4 y5] y2 y3 x2*y2
* x4 x5 [x6 x7] y4 y5 y2 y3 x3*y3
* x4 x5 x6 x7 y4 y5 [y6 y7] x4*y4
* --------- finalize ------------
* x4 x5 x6 x7 y4 y5 y6 y7 x5*y5 (nothing is load)
* x4 x5 x6 x7 y4 y5 y6 y7 x6*y6
* x4 x5 x6 x7 y4 y5 y6 y7 x7*y7
*/
addi \x1, \x1, -4 // To arrange fist pointer
addi \x2, \x2, -4 // To arrange fist pointer
//lddec m0, \x1
//lddec m2, \x2 // To arrange fist pointer
ldinc m0, \x1
ldinc m2, \x2
ldinc m1, \x1
mula.dd.ll.ldinc m3, \x2, m0, m2
loopnez \count, .loop_end
.loop:
mula.dd.hh.ldinc m0, \x1, m0, m2
mula.dd.ll.ldinc m2, \x2, m1, m3
mula.dd.hh.ldinc m1, \x1, m1, m3
mula.dd.ll.ldinc m3, \x2, m0, m2
.loop_end:
mula.dd.hh m0, m2
mula.dd.ll m1, m3
mula.dd.hh m1, m3
.endm // dotprod_s16_ae32
.macro dotprod_s16_ae32_full x1, x2, count, full_count
// This macro calculates fixed point dot product for ((count + 1)*4) int16 samples
// x1 - input array1 register (for example a2)
// x2 - input array2 register (for example a3)
// count - counter register (for example a7)
// count - samples_count / 4 - 1
// full_count - samples_count
// acc += x1[i + 0]*x2[i + 0] + x1[i + 1]*x2[i + 1] + x1[i + 2]*x2[i + 2] + x1[i + 3]*x2[i + 3]; i: 0..count
// acchi, and acclo have to be initialize before
// Result - acchi || acclo
// Modifies:
// m0, m1, m2, m3
// acchi || acclo - must be loaded before (for example 0x3fff to acclo).
dotprod_s16_ae32 \x1, \x2, \count
bbci \full_count, 1, .mod2chk
ldinc m0, \x1
ldinc m2, \x2
mula.dd.hh m0, m2
mula.dd.ll m0, m2
.mod2chk:
bbci \full_count, 0, .mod1chk
ldinc m0, \x1
ldinc m2, \x2
mula.dd.ll m0, m2
.mod1chk:
.endm // dotprod_s16_ae32_full
|
georgevio/IoT-Embedded
| 14,880
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_s8_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_52, 458755
# Program Unit: dspi_dotprod_s8_aes3
.type dspi_dotprod_s8_aes3, @function
.align 4
.global dspi_dotprod_s8_aes3
dspi_dotprod_s8_aes3: # 0x4
.LBB1_dspi_dotprod_s8_aes3: # 0x4
entry a1,48 #
l32i.n a10,a2,4 # [0] id:668
l32i.n a11,a2,12 # [1] id:667
mull a8,a10,a5 # [2]
blt a11,a8,.LBB78_dspi_dotprod_s8_aes3 # [4]
l32i.n a12,a2,8 # [0] id:669
l32i.n a9,a2,16 # [1] id:670
mull a13,a12,a6 # [2]
blt a9,a13,.LBB78_dspi_dotprod_s8_aes3 # [4]
l32i.n a15,a3,4 # [0] id:672
l32i.n a14,a3,12 # [1] id:671
mull a13,a15,a5 # [2]
blt a14,a13,.LBB78_dspi_dotprod_s8_aes3 # [4]
l32i.n a8,a3,16 # [0] id:674
l32i.n a9,a3,8 # [1] id:673
s32i.n a9,a1,8 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB78_dspi_dotprod_s8_aes3 # [5]
l32i.n a8,a3,0 # [0] id:675
s32i.n a8,a1,4 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_33026 # [2]
bne a14,a13,.Lt_0_33026 # [0]
bnei a15,1,.Lt_0_33026 # [0]
l32i.n a13,a1,8 # [0] gra_spill_temp_2
beqi a13,1,.Lt_0_17666 # [2]
.Lt_0_33026: # 0x43
.Lt_0_17922: # 0x43
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
.type dspi_dotprod_s8_ansi, @function
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB78_dspi_dotprod_s8_aes3: # 0x56
l32r a2,.LC0_1_52 # [0]
retw.n # [1]
.Lt_0_17666: # 0x5b
addi.n a14,a10,-1 # [0]
bnez a14,.Lt_0_33794 # [1]
addi.n a15,a12,-1 # [0]
bnez a15,.Lt_0_33794 # [1]
extui a8,a5,0,4 # [0]
bnez.n a8,.Lt_0_33794 # [1]
blti a6,4,.Lt_0_33794 # [0]
movi.n a9,64 # [0]
bge a9,a5,.Lt_0_34306 # [1]
extui a10,a5,0,1 # [0]
bnez a10,.LBB28_dspi_dotprod_s8_aes3 # [1]
.Lt_0_34306: # 0x78
.Lt_0_19714: # 0x78
mov.n a3,a6 # [0]
addi a13,a5,-48 # [1]
movi.n a14,0 # [2]
mull a15,a11,a12 # [3]
l32i.n a2,a2,0 # [4] id:676
s32i.n a15,a1,0 # [6] gra_spill_temp_0
wur.accx_0 a14 # [7]
l32i.n a15,a1,4 # [8] gra_spill_temp_1
wur.accx_1 a14 # [9]
ee.vld.128.ip q0,a15,16 # [10] id:679
beqz a13,.LBB32_dspi_dotprod_s8_aes3 # [11]
.Lt_0_22786: # 0x93
.Lt_0_22274: # 0x93
addi a8,a5,-32 # [0]
beqz a8,.LBB38_dspi_dotprod_s8_aes3 # [1]
.Lt_0_24322: # 0x99
.Lt_0_23810: # 0x99
addi a9,a5,-16 # [0]
beqz a9,.LBB44_dspi_dotprod_s8_aes3 # [1]
.Lt_0_25858: # 0x9f
.Lt_0_25346: # 0x9f
addi a10,a5,-64 # [0]
beqz a10,.LBB50_dspi_dotprod_s8_aes3 # [1]
.Lt_0_27394: # 0xa5
.Lt_0_26882: # 0xa5
addi a11,a5,-128 # [0]
beqz a11,.LBB56_dspi_dotprod_s8_aes3 # [1]
movi a12,128 # [0]
bge a12,a5,.Lt_0_30210 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a2,16 # [1] id:751
ee.ld.128.usar.ip q2,a2,16 # [2] id:752
ee.src.q.ld.ip q3,a2,16,q1,q2 # [4] id:753
beqz.n a3,.Lt_0_30210 # [5]
l32i.n a14,a1,0 # [0] gra_spill_temp_0
addi a13,a5,63 # [1]
movgez a13,a5,a5 # [2]
srai a13,a13,6 # [3]
sub a14,a14,a5 # [4]
addi a14,a14,16 # [5]
addi.n a13,a13,-1 # [6]
.Lt_0_30978: # 0xd1
addi.n a12,a12,1 # [0]
movi.n a8,32 # [1]
movi.n a9,-16 # [2]
beqz.n a13,.Lt_0_31234 # [3]
loopnez a13,.LBB218_dspi_dotprod_s8_aes3 # [0]
.LBB216_dspi_dotprod_s8_aes3: # 0xdc
ee.vld.128.ip q5,a15,16 # [0*II+0] id:755
ee.vmulas.s8.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:754
ee.vld.128.ip q0,a15,16 # [0*II+2] id:757
ee.vmulas.s8.accx.ld.ip.qup q1,a2,16,q5,q2,q3,q4 # [0*II+3] id:756
ee.vld.128.ip q5,a15,16 # [0*II+4] id:759
ee.vmulas.s8.accx.ld.ip.qup q2,a2,16,q0,q3,q4,q1 # [0*II+5] id:758
ee.vld.128.ip q0,a15,16 # [0*II+6] id:761
ee.vmulas.s8.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+7] id:760
.LBB218_dspi_dotprod_s8_aes3: # 0xf8
.Lt_0_31234: # 0xf8
ee.vmulas.s8.accx.ld.ip.qup q5,a2,16,q0,q1,q2,q3 # [0] id:762
ee.vld.128.ip q0,a15,16 # [1] id:763
ee.vld.128.ip q6,a15,16 # [2] id:765
ee.vmulas.s8.accx.ld.xp.qup q7,a2,a14,q0,q2,q3,q5 # [3] id:764
ee.vld.128.ip q4,a15,16 # [4] id:768
ee.vmulas.s8.accx.ld.xp.qup q2,a2,a9,q6,q3,q5,q7 # [5] id:766
ee.ld.128.usar.xp q1,a2,a8 # [6] id:767
ee.vld.128.ip q0,a15,16 # [7] id:770
ee.vmulas.s8.accx.ld.ip.qup q3,a2,16,q4,q5,q1,q2 # [8] id:769
bne a12,a3,.Lt_0_30978 # [9]
.Lt_0_30210: # 0x11a
.Lt_0_29954: # 0x11a
movi.n a2,0 # [0]
rur.accx_0 a10 # [1]
addi.n a12,a7,-1 # [2]
movi.n a11,1 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:772
retw.n # [10]
.Lt_0_33794: # 0x136
.Lt_0_18946: # 0x136
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
#.LBB25_dspi_dotprod_s8_aes3: # 0x145
mov.n a2,a10 # [0]
retw.n # [1]
.LBB32_dspi_dotprod_s8_aes3: # 0x149
ee.ld.128.usar.ip q1,a2,16 # [0] id:680
ee.ld.128.usar.ip q2,a2,16 # [1] id:681
ee.src.q.ld.ip q3,a2,16,q1,q2 # [3] id:682
beqz.n a6,.Lt_0_22786 # [4]
movi.n a10,32 # [0]
l32i.n a12,a1,0 # [1] gra_spill_temp_0
movi.n a11,-16 # [2]
addi a12,a12,-32 # [3]
loopgtz a6,.LBB104_dspi_dotprod_s8_aes3 # [4]
.LBB102_dspi_dotprod_s8_aes3: # 0x160
ee.vld.128.ip q4,a15,16 # [0*II+0] id:684
ee.vmulas.s8.accx.ld.xp.qup q1,a2,a12,q0,q1,q2,q3 # [0*II+1] id:683
ee.vld.128.ip q5,a15,16 # [0*II+2] id:686
ee.vmulas.s8.accx.ld.xp.qup q2,a2,a11,q4,q2,q3,q1 # [0*II+3] id:685
ee.ld.128.usar.xp q1,a2,a10 # [0*II+4] id:687
ee.vld.128.ip q0,a15,16 # [0*II+5] id:689
ee.vmulas.s8.accx.ld.ip.qup q3,a2,16,q5,q3,q1,q2 # [0*II+6] id:688
.LBB104_dspi_dotprod_s8_aes3: # 0x178
j .Lt_0_22786 # [0]
.LBB38_dspi_dotprod_s8_aes3: # 0x17b
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
srli a3,a6,1 # [2]
l32i.n a12,a1,0 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [4] id:690
ee.ld.128.usar.ip q2,a2,16 # [5] id:691
addi a12,a12,-16 # [7]
ee.src.q.ld.xp q3,a2,a12,q1,q2 # [8] id:692
loopnez a3,.LBB127_dspi_dotprod_s8_aes3 # [9]
.LBB125_dspi_dotprod_s8_aes3: # 0x193
ee.vld.128.ip q4,a15,16 # [0*II+0] id:694
ee.vmulas.s8.accx.ld.xp.qup q3,a2,a11,q0,q1,q2,q3 # [0*II+1] id:693
ee.ld.128.usar.xp q1,a2,a10 # [0*II+2] id:695
ee.vld.128.ip q0,a15,16 # [0*II+3] id:697
ee.vmulas.s8.accx.ld.xp.qup q4,a2,a12,q4,q2,q1,q3 # [0*II+4] id:696
ee.vld.128.ip q5,a15,16 # [0*II+5] id:699
ee.vmulas.s8.accx.ld.xp.qup q2,a2,a11,q0,q1,q3,q4 # [0*II+6] id:698
ee.ld.128.usar.xp q1,a2,a10 # [0*II+7] id:700
ee.vld.128.ip q0,a15,16 # [0*II+8] id:702
ee.vmulas.s8.accx.ld.xp.qup q3,a2,a12,q5,q3,q1,q2 # [0*II+9] id:701
.LBB127_dspi_dotprod_s8_aes3: # 0x1b5
j .Lt_0_24322 # [0]
.LBB44_dspi_dotprod_s8_aes3: # 0x1b8
srli a3,a3,2 # [0]
movi.n a10,-16 # [1]
l32i.n a11,a1,0 # [2] gra_spill_temp_0
addi a8,a2,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a8,a10 # [5] id:703
ee.ld.128.usar.xp q1,a8,a11 # [6] id:704
ee.src.q.ld.xp q3,a8,a10,q1,q2 # [8] id:705
ee.ld.128.usar.xp q2,a8,a11 # [9] id:706
loopnez a3,.LBB150_dspi_dotprod_s8_aes3 # [10]
.LBB148_dspi_dotprod_s8_aes3: # 0x1d4
ee.vld.128.ip q4,a15,16 # [0*II+0] id:708
ee.vmulas.s8.accx.ld.xp.qup q3,a8,a10,q0,q1,q2,q3 # [0*II+1] id:707
ee.ld.128.usar.xp q1,a8,a11 # [0*II+2] id:709
ee.vld.128.ip q0,a15,16 # [0*II+3] id:711
ee.vmulas.s8.accx.ld.xp.qup q4,a8,a10,q4,q2,q1,q3 # [0*II+4] id:710
ee.ld.128.usar.xp q3,a8,a11 # [0*II+5] id:712
ee.vld.128.ip q5,a15,16 # [0*II+6] id:714
ee.vmulas.s8.accx.ld.xp.qup q4,a8,a10,q0,q1,q3,q4 # [0*II+7] id:713
ee.ld.128.usar.xp q1,a8,a11 # [0*II+8] id:715
ee.vld.128.ip q0,a15,16 # [0*II+9] id:717
ee.vmulas.s8.accx.ld.xp.qup q3,a8,a10,q5,q3,q1,q4 # [0*II+10] id:716
ee.ld.128.usar.xp q2,a8,a11 # [0*II+11] id:718
.LBB150_dspi_dotprod_s8_aes3: # 0x1fc
mov.n a2,a8 # [0]
j .Lt_0_25858 # [1]
.LBB50_dspi_dotprod_s8_aes3: # 0x201
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i.n a12,a1,0 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [3] id:719
ee.ld.128.usar.ip q2,a2,16 # [4] id:720
sub a12,a12,a5 # [5]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [7] id:721
addi a12,a12,16 # [8]
loopnez a3,.LBB173_dspi_dotprod_s8_aes3 # [9]
.LBB171_dspi_dotprod_s8_aes3: # 0x219
ee.vld.128.ip q5,a15,16 # [0*II+0] id:723
ee.vmulas.s8.accx.ld.ip.qup q4,a2,16,q0,q1,q2,q3 # [0*II+1] id:722
ee.vld.128.ip q1,a15,16 # [0*II+2] id:725
ee.vmulas.s8.accx.ld.xp.qup q0,a2,a12,q5,q2,q3,q4 # [0*II+3] id:724
ee.vld.128.ip q5,a15,16 # [0*II+4] id:728
ee.vmulas.s8.accx.ld.xp.qup q2,a2,a11,q1,q3,q4,q0 # [0*II+5] id:726
ee.ld.128.usar.xp q1,a2,a10 # [0*II+6] id:727
ee.vld.128.ip q0,a15,16 # [0*II+7] id:730
ee.vmulas.s8.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+8] id:729
.LBB173_dspi_dotprod_s8_aes3: # 0x238
j .Lt_0_27394 # [0]
.LBB56_dspi_dotprod_s8_aes3: # 0x23b
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i.n a12,a1,0 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q1,a2,16 # [3] id:731
ee.ld.128.usar.ip q2,a2,16 # [4] id:732
sub a12,a12,a5 # [6]
addi a12,a12,16 # [7]
ee.src.q.ld.ip q3,a2,16,q1,q2 # [8] id:733
loopnez a3,.LBB195_dspi_dotprod_s8_aes3 # [9]
.LBB193_dspi_dotprod_s8_aes3: # 0x253
ee.vld.128.ip q4,a15,16 # [0*II+0] id:735
ee.vmulas.s8.accx.ld.ip.qup q1,a2,16,q0,q1,q2,q3 # [0*II+1] id:734
ee.vld.128.ip q0,a15,16 # [0*II+2] id:737
ee.vmulas.s8.accx.ld.ip.qup q4,a2,16,q4,q2,q3,q1 # [0*II+3] id:736
ee.vld.128.ip q5,a15,16 # [0*II+4] id:739
ee.vmulas.s8.accx.ld.ip.qup q0,a2,16,q0,q3,q1,q4 # [0*II+5] id:738
ee.vld.128.ip q6,a15,16 # [0*II+6] id:741
ee.vmulas.s8.accx.ld.ip.qup q1,a2,16,q5,q1,q4,q0 # [0*II+7] id:740
ee.vld.128.ip q5,a15,16 # [0*II+8] id:743
ee.vmulas.s8.accx.ld.ip.qup q4,a2,16,q6,q4,q0,q1 # [0*II+9] id:742
ee.vld.128.ip q6,a15,16 # [0*II+10] id:745
ee.vmulas.s8.accx.ld.xp.qup q0,a2,a12,q5,q0,q1,q4 # [0*II+11] id:744
ee.vld.128.ip q5,a15,16 # [0*II+12] id:748
ee.vmulas.s8.accx.ld.xp.qup q2,a2,a11,q6,q1,q4,q0 # [0*II+13] id:746
ee.ld.128.usar.xp q1,a2,a10 # [0*II+14] id:747
ee.vld.128.ip q0,a15,16 # [0*II+15] id:750
ee.vmulas.s8.accx.ld.ip.qup q3,a2,16,q5,q4,q1,q2 # [0*II+16] id:749
.LBB195_dspi_dotprod_s8_aes3: # 0x28e
movi.n a2,0 # [0]
movi.n a11,1 # [1]
addi.n a12,a7,-1 # [2]
rur.accx_0 a10 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:772
retw.n # [10]
.LBB28_dspi_dotprod_s8_aes3: # 0x2aa
mov.n a15,a7 # [0]
mov.n a14,a6 # [1]
mov.n a13,a5 # [2]
mov.n a12,a4 # [3]
mov.n a11,a3 # [4]
mov.n a10,a2 # [5]
call8 dspi_dotprod_s8_ansi # [6] dspi_dotprod_s8_ansi
#.LBB29_dspi_dotprod_s8_aes3: # 0x2b9
mov.n a2,a10 # [0]
retw.n # [1]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 17,637
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_u16_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_61, 458755
# Program Unit: dspi_dotprod_off_u16_aes3
.type dspi_dotprod_off_u16_aes3, @function
.align 4
.global dspi_dotprod_off_u16_aes3
dspi_dotprod_off_u16_aes3: # 0x4
.LBB1_dspi_dotprod_off_u16_aes3: # 0x4
entry a1,144 #
l32i.n a10,a2,4 # [0] id:760
l32i.n a12,a2,12 # [1] id:759
mull a8,a10,a5 # [2]
blt a12,a8,.LBB89_dspi_dotprod_off_u16_aes3 # [4]
l32i.n a13,a2,8 # [0] id:761
l32i.n a9,a2,16 # [1] id:762
mull a11,a13,a6 # [2]
blt a9,a11,.LBB89_dspi_dotprod_off_u16_aes3 # [4]
l32i.n a15,a3,4 # [0] id:764
l32i.n a14,a3,12 # [1] id:763
mull a11,a15,a5 # [2]
blt a14,a11,.LBB89_dspi_dotprod_off_u16_aes3 # [4]
l32i.n a8,a3,16 # [0] id:766
l32i.n a9,a3,8 # [1] id:765
s32i a9,a1,104 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB89_dspi_dotprod_off_u16_aes3 # [5]
l32i.n a8,a3,0 # [0] id:767
s32i a8,a1,100 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_36354 # [2]
bne a14,a11,.Lt_0_36354 # [0]
bnei a15,1,.Lt_0_36354 # [0]
l32i a9,a1,104 # [0] gra_spill_temp_2
beqi a9,1,.Lt_0_19458 # [2]
.Lt_0_36354: # 0x46
.Lt_0_19714: # 0x46
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16ui a8,a1,144 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:876
.type dspi_dotprod_off_u16_ansi, @function
call8 dspi_dotprod_off_u16_ansi # [8] dspi_dotprod_off_u16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB89_dspi_dotprod_off_u16_aes3: # 0x5e
l32r a2,.LC0_1_61 # [0]
retw.n # [1]
.Lt_0_19458: # 0x63
addi.n a9,a10,-1 # [0]
bnez a9,.Lt_0_37122 # [1]
addi.n a10,a13,-1 # [0]
bnez a10,.Lt_0_37122 # [1]
extui a11,a5,0,3 # [0]
bnez.n a11,.Lt_0_37122 # [1]
blti a6,4,.Lt_0_37122 # [0]
movi.n a14,32 # [0]
blt a14,a5,.LBB27_dspi_dotprod_off_u16_aes3 # [1]
.Lt_0_37634: # 0x7a
.Lt_0_21506: # 0x7a
l16ui a9,a1,144 # [0] id:768 offset+0x0
addi a8,a1,16 # [1] temp_offset
l32i.n a15,a2,0 # [2] id:769
mull a10,a12,a13 # [3]
l32i a2,a1,100 # [4] gra_spill_temp_1
slli a10,a10,1 # [5]
s32i a10,a1,96 # [6] gra_spill_temp_0
movi.n a10,2 # [7]
# loop-count fixed at 2
loop a10,.LBB143_dspi_dotprod_off_u16_aes3 # [8]
.LBB138_dspi_dotprod_off_u16_aes3: # 0x93
s16i a9,a8,0 # [0*II+0] id:770 temp_offset+0x0
s16i a9,a8,2 # [0*II+1] id:770 temp_offset+0x0
s16i a9,a8,4 # [0*II+2] id:770 temp_offset+0x0
s16i a9,a8,6 # [0*II+3] id:770 temp_offset+0x0
s16i a9,a8,8 # [0*II+4] id:770 temp_offset+0x0
s16i a9,a8,10 # [0*II+5] id:770 temp_offset+0x0
s16i a9,a8,12 # [0*II+6] id:770 temp_offset+0x0
s16i a9,a8,14 # [0*II+7] id:770 temp_offset+0x0
addi a8,a8,16 # [0*II+8]
.LBB143_dspi_dotprod_off_u16_aes3: # 0xae
mov.n a3,a6 # [0]
addi a11,a5,-24 # [1]
addi a12,a1,24 # [3] temp_offset+8
movi.n a13,0 # [4]
wur.sar_byte a13 # [5]
wur.accx_0 a13 # [6]
wur.accx_1 a13 # [7]
ee.vld.128.ip q6,a12,0 # [8] id:771
s32i.n a12,a1,48 # [9] offset_data_ptr
beqz a11,.LBB34_dspi_dotprod_off_u16_aes3 # [10]
l32i a2,a1,100 # [0] gra_spill_temp_1
ee.vld.128.ip q0,a2,16 # [2] id:787
st.qr q0,a1,64 # [3] q0
.Lt_0_25090: # 0xd1
addi a14,a5,-16 # [0]
beqz a14,.LBB43_dspi_dotprod_off_u16_aes3 # [1]
.Lt_0_27138: # 0xd7
.Lt_0_26626: # 0xd7
addi a8,a5,-8 # [0]
beqz a8,.LBB50_dspi_dotprod_off_u16_aes3 # [1]
.Lt_0_28674: # 0xdd
.Lt_0_28162: # 0xdd
addi a9,a5,-32 # [0]
beqz a9,.LBB57_dspi_dotprod_off_u16_aes3 # [1]
.Lt_0_30210: # 0xe3
.Lt_0_29698: # 0xe3
addi a10,a5,-64 # [0]
beqz a10,.LBB64_dspi_dotprod_off_u16_aes3 # [1]
movi.n a11,64 # [0]
bge a11,a5,.Lt_0_33026 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a15,16 # [1] id:849
ee.ld.128.usar.ip q2,a15,16 # [2] id:850
ee.src.q.ld.ip q3,a15,16,q1,q2 # [4] id:851
beqz.n a3,.Lt_0_33026 # [5]
ld.qr q0,a1,64 # [0] q0
slli a8,a5,1 # [1]
l32i a14,a1,96 # [2] gra_spill_temp_0
addi a13,a5,31 # [3]
movgez a13,a5,a5 # [4]
srai a13,a13,5 # [5]
sub a14,a14,a8 # [6]
addi a14,a14,16 # [7]
addi.n a13,a13,-1 # [8]
.Lt_0_33794: # 0x115
beqz.n a13,.Lt_0_34050 # [0]
loopnez a13,.LBB280_dspi_dotprod_off_u16_aes3 # [0]
.LBB278_dspi_dotprod_off_u16_aes3: # 0x11a
ee.vmulas.u16.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:852
ee.vmulas.u16.accx.ld.ip q1,a2,16,q1,q6 # [0*II+1] id:853
ee.vmulas.u16.accx.ld.ip.qup q1,a15,16,q1,q2,q3,q0 # [0*II+3] id:854
ee.vmulas.u16.accx.ld.ip q4,a2,16,q2,q6 # [0*II+4] id:855
ee.vmulas.u16.accx.ld.ip.qup q2,a15,16,q4,q3,q0,q1 # [0*II+6] id:856
ee.vmulas.u16.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:857
ee.vmulas.u16.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+9] id:858
ee.vmulas.u16.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:859
.LBB280_dspi_dotprod_off_u16_aes3: # 0x13a
.Lt_0_34050: # 0x13a
ee.vmulas.u16.accx.ld.ip.qup q4,a15,16,q0,q1,q2,q3 # [0] id:860
ee.vmulas.u16.accx.ld.ip q1,a2,16,q1,q6 # [1] id:861
movi.n a9,32 # [2]
ee.vmulas.u16.accx.ld.xp.qup q0,a15,a14,q1,q2,q3,q4 # [3] id:862
ee.vmulas.u16.accx.ld.ip q7,a2,16,q2,q6 # [4] id:863
movi.n a10,-16 # [5]
ee.vmulas.u16.accx.ld.xp.qup q2,a15,a10,q7,q3,q4,q0 # [6] id:864
ee.vmulas.u16.accx.ld.ip q5,a2,16,q3,q6 # [7] id:866
ee.ld.128.usar.xp q1,a15,a9 # [8] id:865
addi.n a12,a12,1 # [9]
ee.vmulas.u16.accx.ld.ip.qup q3,a15,16,q5,q4,q1,q2 # [10] id:867
ee.vmulas.u16.accx.ld.ip q0,a2,16,q4,q6 # [11] id:868
bne a12,a3,.Lt_0_33794 # [12]
.Lt_0_33026: # 0x166
.Lt_0_32770: # 0x166
rur.accx_0 a9 # [0]
rur.accx_1 a10 # [1]
blti a7,1,.Lt_0_35586 # [2]
movi.n a2,0 # [0]
addi a13,a7,-33 # [1]
addi.n a14,a7,-1 # [2]
ssr a14 # [3]
sra a12,a10 # [4]
src a11,a10,a9 # [5]
movgez a11,a12,a13 # [6]
addi.n a11,a11,1 # [7]
srli a11,a11,1 # [8]
s16i a11,a4,0 # [9] id:874
retw.n # [10]
.Lt_0_37122: # 0x18c
.Lt_0_20738: # 0x18c
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16ui a8,a1,144 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:877
call8 dspi_dotprod_off_u16_ansi # [8] dspi_dotprod_off_u16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB27_dspi_dotprod_off_u16_aes3: # 0x1a4
extui a9,a5,0,1 # [0]
beqz a9,.Lt_0_37634 # [1]
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
l16ui a8,a1,144 # [6] id:768 offset+0x0
s32i.n a8,a1,0 # [7] id:878
call8 dspi_dotprod_off_u16_ansi # [8] dspi_dotprod_off_u16_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB34_dspi_dotprod_off_u16_aes3: # 0x1c2
ee.ld.128.usar.ip q0,a15,16 # [0] id:776
ee.ld.128.usar.ip q2,a15,16 # [1] id:777
ee.src.q.ld.ip q3,a15,16,q0,q2 # [3] id:778
beqz.n a6,.Lt_0_25090 # [4]
movi.n a10,32 # [0]
l32i a12,a1,96 # [1] gra_spill_temp_0
movi.n a11,-16 # [2]
addi a12,a12,-32 # [3]
loopgtz a6,.LBB166_dspi_dotprod_off_u16_aes3 # [4]
.LBB164_dspi_dotprod_off_u16_aes3: # 0x1da
ee.vmulas.u16.accx.ld.ip q1,a2,16,q0,q6 # [0*II+0] id:779
ee.vmulas.u16.accx.ld.xp.qup q1,a15,a12,q1,q0,q2,q3 # [0*II+2] id:780
ee.vmulas.u16.accx.ld.ip q0,a2,16,q2,q6 # [0*II+3] id:781
ee.vmulas.u16.accx.ld.xp.qup q2,a15,a11,q0,q2,q3,q1 # [0*II+5] id:782
ee.vmulas.u16.accx.ld.ip q1,a2,16,q3,q6 # [0*II+6] id:784
ee.ld.128.usar.xp q0,a15,a10 # [0*II+7] id:783
ee.vmulas.u16.accx.ld.ip.qup q3,a15,16,q1,q3,q0,q2 # [0*II+9] id:785
.LBB166_dspi_dotprod_off_u16_aes3: # 0x1f5
st.qr q1,a1,64 # [0] q0
j .Lt_0_25090 # [1]
.LBB43_dspi_dotprod_off_u16_aes3: # 0x1fb
srli a3,a6,1 # [0]
l32i a12,a1,96 # [1] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [2] id:788
ee.ld.128.usar.ip q2,a15,16 # [3] id:789
addi a12,a12,-16 # [5]
ee.src.q.ld.xp q3,a15,a12,q1,q2 # [6] id:790
beqz.n a3,.Lt_0_27138 # [7]
ld.qr q0,a1,64 # [0] q0
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
loopnez a3,.LBB189_dspi_dotprod_off_u16_aes3 # [3]
.LBB187_dspi_dotprod_off_u16_aes3: # 0x219
ee.vmulas.u16.accx.ld.xp.qup q0,a15,a11,q0,q1,q2,q3 # [0*II+0] id:791
ee.vmulas.u16.accx.ld.ip q3,a2,16,q1,q6 # [0*II+1] id:792
ee.ld.128.usar.xp q1,a15,a10 # [0*II+2] id:793
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a12,q3,q2,q1,q0 # [0*II+4] id:794
ee.vmulas.u16.accx.ld.ip q4,a2,16,q2,q6 # [0*II+5] id:795
ee.vmulas.u16.accx.ld.xp.qup q2,a15,a11,q4,q1,q0,q3 # [0*II+7] id:796
ee.vmulas.u16.accx.ld.ip q3,a2,16,q1,q6 # [0*II+8] id:797
ee.ld.128.usar.xp q1,a15,a10 # [0*II+9] id:798
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a12,q3,q0,q1,q2 # [0*II+11] id:799
ee.vmulas.u16.accx.ld.ip q0,a2,16,q0,q6 # [0*II+12] id:800
.LBB189_dspi_dotprod_off_u16_aes3: # 0x23f
st.qr q0,a1,64 # [0] q0
j .Lt_0_27138 # [1]
.LBB50_dspi_dotprod_off_u16_aes3: # 0x245
srli a3,a3,2 # [0]
movi.n a13,-16 # [1]
l32i a11,a1,96 # [2] gra_spill_temp_0
addi a15,a15,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a15,a13 # [5] id:801
ee.ld.128.usar.xp q1,a15,a11 # [6] id:802
ee.src.q.ld.xp q3,a15,a13,q1,q2 # [8] id:803
ee.ld.128.usar.xp q2,a15,a11 # [9] id:804
beqz.n a3,.Lt_0_28674 # [10]
ld.qr q0,a1,64 # [0] q0
movi.n a10,-16 # [1]
loopnez a3,.LBB212_dspi_dotprod_off_u16_aes3 # [2]
.LBB210_dspi_dotprod_off_u16_aes3: # 0x269
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a10,q0,q1,q2,q3 # [0*II+0] id:805
ee.vmulas.u16.accx.ld.ip q0,a2,16,q1,q6 # [0*II+1] id:806
ee.ld.128.usar.xp q1,a15,a11 # [0*II+2] id:807
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a10,q0,q2,q1,q3 # [0*II+4] id:808
ee.vmulas.u16.accx.ld.ip q0,a2,16,q2,q6 # [0*II+5] id:809
ee.ld.128.usar.xp q4,a15,a11 # [0*II+6] id:810
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a10,q0,q1,q4,q3 # [0*II+8] id:811
ee.vmulas.u16.accx.ld.ip q0,a2,16,q1,q6 # [0*II+9] id:812
ee.ld.128.usar.xp q1,a15,a11 # [0*II+10] id:813
ee.vmulas.u16.accx.ld.xp.qup q3,a15,a10,q0,q4,q1,q3 # [0*II+12] id:814
ee.vmulas.u16.accx.ld.ip q0,a2,16,q4,q6 # [0*II+13] id:815
ee.ld.128.usar.xp q2,a15,a11 # [0*II+14] id:816
.LBB212_dspi_dotprod_off_u16_aes3: # 0x295
st.qr q0,a1,64 # [0] q0
j .Lt_0_28674 # [1]
.LBB57_dspi_dotprod_off_u16_aes3: # 0x29b
ee.ld.128.usar.ip q1,a15,16 # [0] id:817
ee.ld.128.usar.ip q2,a15,16 # [1] id:818
ee.src.q.ld.ip q3,a15,16,q1,q2 # [3] id:819
beqz.n a3,.Lt_0_30210 # [4]
ld.qr q0,a1,64 # [0] q0
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
l32i a12,a1,96 # [3] gra_spill_temp_0
slli a13,a5,1 # [4]
sub a12,a12,a13 # [5]
addi a12,a12,16 # [6]
loopnez a3,.LBB235_dspi_dotprod_off_u16_aes3 # [7]
.LBB233_dspi_dotprod_off_u16_aes3: # 0x2bc
ee.vmulas.u16.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:820
ee.vmulas.u16.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:821
ee.vmulas.u16.accx.ld.xp.qup q4,a15,a12,q4,q2,q3,q0 # [0*II+3] id:822
ee.vmulas.u16.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:823
ee.vmulas.u16.accx.ld.xp.qup q2,a15,a11,q1,q3,q0,q4 # [0*II+6] id:824
ee.vmulas.u16.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:826
ee.ld.128.usar.xp q1,a15,a10 # [0*II+8] id:825
ee.vmulas.u16.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+10] id:827
ee.vmulas.u16.accx.ld.ip q0,a2,16,q0,q6 # [0*II+11] id:828
.LBB235_dspi_dotprod_off_u16_aes3: # 0x2df
st.qr q0,a1,64 # [0] q0
j .Lt_0_30210 # [1]
.LBB64_dspi_dotprod_off_u16_aes3: # 0x2e5
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
slli a13,a5,1 # [2]
l32i a12,a1,96 # [3] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [4] id:829
ee.ld.128.usar.ip q2,a15,16 # [5] id:830
sub a12,a12,a13 # [7]
addi a12,a12,16 # [8]
ld.qr q0,a1,64 # [9] q0
ee.src.q.ld.ip q3,a15,16,q1,q2 # [10] id:831
mov.n a8,a15 # [11]
loopnez a3,.LBB257_dspi_dotprod_off_u16_aes3 # [12]
.LBB255_dspi_dotprod_off_u16_aes3: # 0x306
ee.vmulas.u16.accx.ld.ip.qup q0,a8,16,q0,q1,q2,q3 # [0*II+0] id:832
ee.vmulas.u16.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:833
ee.vmulas.u16.accx.ld.ip.qup q4,a8,16,q4,q2,q3,q0 # [0*II+3] id:834
ee.vmulas.u16.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:835
ee.vmulas.u16.accx.ld.ip.qup q1,a8,16,q1,q3,q0,q4 # [0*II+6] id:836
ee.vmulas.u16.accx.ld.ip q5,a2,16,q3,q6 # [0*II+7] id:837
ee.vmulas.u16.accx.ld.ip.qup q5,a8,16,q5,q0,q4,q1 # [0*II+9] id:838
ee.vmulas.u16.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:839
ee.vmulas.u16.accx.ld.ip.qup q0,a8,16,q0,q4,q1,q5 # [0*II+12] id:840
ee.vmulas.u16.accx.ld.ip q4,a2,16,q4,q6 # [0*II+13] id:841
ee.vmulas.u16.accx.ld.xp.qup q4,a8,a12,q4,q1,q5,q0 # [0*II+15] id:842
ee.vmulas.u16.accx.ld.ip q1,a2,16,q1,q6 # [0*II+16] id:843
ee.vmulas.u16.accx.ld.xp.qup q2,a8,a11,q1,q5,q0,q4 # [0*II+18] id:844
ee.vmulas.u16.accx.ld.ip q4,a2,16,q5,q6 # [0*II+19] id:846
ee.ld.128.usar.xp q1,a8,a10 # [0*II+20] id:845
ee.vmulas.u16.accx.ld.ip.qup q3,a8,16,q4,q0,q1,q2 # [0*II+22] id:847
ee.vmulas.u16.accx.ld.ip q0,a2,16,q0,q6 # [0*II+23] id:848
.LBB257_dspi_dotprod_off_u16_aes3: # 0x349
j .Lt_0_33026 # [0]
.Lt_0_35586: # 0x34c
movi.n a2,0 # [0]
sext a14,a9,15 # [1]
s16i a14,a4,0 # [2] id:875
retw.n # [3]
#endif // dsps_dotprod_s16_aes3_enabled
|
georgevio/IoT-Embedded
| 2,928
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_s16_arp4.S
|
// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_arp4_enabled == 1)
#include "dsp_err_codes.h"
.text
.align 4
.global dspi_dotprod_off_s16_arp4
.global dspi_dotprod_off_s16_ansi
.type dspi_dotprod_off_s16_arp4,@function
// esp_err_t dspi_dotprod_off_s16_arp4(image2d_t *in_image, image2d_t *filter, int16_t *out_value, int count_x, int count_y, int shift, int16_t offset);
dspi_dotprod_off_s16_arp4:
// in_image - a0
// filter - a1
// out_value - a2
// count_x - a3
// count_y - a4
// shift - a5
// offset - a6
// i_data - t0
// f_data - t1
// i_step - t2
// f_step - t3
// current i_data - t4
// current f_data - t5
lw t1, 4(a0) // load in_image->step_x
lw t2, 4(a1) // load filter->step_x
or t1, t1, t2
addi t1, t1, -1 // should be 0 now
andi t2, a3, 7
or t1, t1, t2
beqz t1, .dspi_dotprod_off_s16_arp4_body
j dspi_dotprod_off_s16_ansi
.dspi_dotprod_off_s16_arp4_body:
add sp, sp, -16
sw a6, 0(sp)
mv t6, sp
esp.vldbc.16.ip q2, t6, 0
lw t0, 0(a0) // i_data
lw t1, 0(a1) // f_data
lw t2, 8(a0) // step_y
lw t4, 12(a0) // stride_x
mul t2, t4, t2
slli t2, t2, 1 // i_step = i_step<<1
lw t3, 8(a1) // step_y
lw t5, 12(a1) // stride_x
mul t3, t5, t3
slli t3, t3, 1 // f_step = f_step<<1
srli t6, a3, 3 // t5 = len/8
addi a7, a5, -1
li t4, 1
sll t4, t4, a7
esp.zero.xacc
esp.movx.w.xacc.l t4
.loop_count_y:
mv t4, t0
mv t5, t1
esp.vld.128.ip q1, t5, 16 // q0 - i_data
esp.lp.setup 0, t6, .loop_count_x
esp.vld.128.ip q0, t4, 16 // q1 - f_data
esp.vadd.s16 q3, q2, q1
.loop_count_x: esp.vmulas.s16.xacc.ld.ip q1, t5, 16, q0, q3 // q0 - i_data
add t0, t0, t2
add t1, t1, t3
add a4,a4, -1
bgtz a4, .loop_count_y
esp.srs.s.xacc t5, a5 // shift accx register by final_shift amount (a5), save the lower 32bits to t5
sh t5, 0(a2) // store result to output buffer
li a0,0
add sp,sp,16
ret
#endif // dspi_dotprod_arp4_enabled
|
georgevio/IoT-Embedded
| 17,039
|
esp-idf/esp32-cam-webPage/managed_components/espressif__esp-dsp/modules/dotprod/fixed/dspi_dotprod_off_u8_aes3.S
|
// Copyright 2018-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dspi_dotprod_platform.h"
#if (dspi_dotprod_aes3_enabled == 1)
.text
.align 4
.literal .LC0_1_57, 458755
# Program Unit: dspi_dotprod_off_u8_aes3
.type dspi_dotprod_off_u8_aes3, @function
.align 4
.global dspi_dotprod_off_u8_aes3
dspi_dotprod_off_u8_aes3: # 0x4
.LBB1_dspi_dotprod_off_u8_aes3: # 0x4
entry a1,112 #
l32i.n a10,a2,4 # [0] id:745
l32i.n a12,a2,12 # [1] id:744
mull a8,a10,a5 # [2]
blt a12,a8,.LBB86_dspi_dotprod_off_u8_aes3 # [4]
l32i.n a13,a2,8 # [0] id:746
l32i.n a9,a2,16 # [1] id:747
mull a11,a13,a6 # [2]
blt a9,a11,.LBB86_dspi_dotprod_off_u8_aes3 # [4]
l32i.n a15,a3,4 # [0] id:749
l32i.n a14,a3,12 # [1] id:748
mull a11,a15,a5 # [2]
blt a14,a11,.LBB86_dspi_dotprod_off_u8_aes3 # [4]
l32i.n a8,a3,16 # [0] id:751
l32i.n a9,a3,8 # [1] id:750
s32i a9,a1,72 # [2] gra_spill_temp_2
mull a9,a9,a6 # [3]
blt a8,a9,.LBB86_dspi_dotprod_off_u8_aes3 # [5]
l32i.n a8,a3,0 # [0] id:752
s32i a8,a1,68 # [1] gra_spill_temp_1
bbsi a8,0,.Lt_0_35330 # [2]
bne a14,a11,.Lt_0_35330 # [0]
bnei a15,1,.Lt_0_35330 # [0]
l32i a11,a1,72 # [0] gra_spill_temp_2
beqi a11,1,.Lt_0_18946 # [2]
.Lt_0_35330: # 0x46
.Lt_0_19202: # 0x46
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
.type dspi_dotprod_u8_ansi, @function
call8 dspi_dotprod_u8_ansi # [6] dspi_dotprod_u8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB86_dspi_dotprod_off_u8_aes3: # 0x59
l32r a2,.LC0_1_57 # [0]
retw.n # [1]
.Lt_0_18946: # 0x5e
addi.n a14,a10,-1 # [0]
bnez a14,.Lt_0_36098 # [1]
addi.n a15,a13,-1 # [0]
bnez a15,.Lt_0_36098 # [1]
extui a8,a5,0,4 # [0]
bnez.n a8,.Lt_0_36098 # [1]
blti a6,4,.Lt_0_36098 # [0]
movi.n a9,64 # [0]
blt a9,a5,.LBB27_dspi_dotprod_off_u8_aes3 # [1]
.Lt_0_36610: # 0x75
.Lt_0_20994: # 0x75
l8ui a9,a1,112 # [0] id:754 offset+0x0
mov.n a8,a1 # [1]
l32i.n a15,a2,0 # [2] id:753
mull a10,a12,a13 # [3]
l32i a2,a1,68 # [4] gra_spill_temp_1
s32i a10,a1,64 # [5] gra_spill_temp_0
movi.n a10,4 # [6]
# loop-count fixed at 4
loop a10,.LBB140_dspi_dotprod_off_u8_aes3 # [7]
.LBB135_dspi_dotprod_off_u8_aes3: # 0x8a
s8i a9,a8,0 # [0*II+0] id:755 temp_offset+0x0
s8i a9,a8,1 # [0*II+1] id:755 temp_offset+0x0
s8i a9,a8,2 # [0*II+2] id:755 temp_offset+0x0
s8i a9,a8,3 # [0*II+3] id:755 temp_offset+0x0
s8i a9,a8,4 # [0*II+4] id:755 temp_offset+0x0
s8i a9,a8,5 # [0*II+5] id:755 temp_offset+0x0
s8i a9,a8,6 # [0*II+6] id:755 temp_offset+0x0
s8i a9,a8,7 # [0*II+7] id:755 temp_offset+0x0
addi.n a8,a8,8 # [0*II+8]
.LBB140_dspi_dotprod_off_u8_aes3: # 0xa4
mov.n a3,a6 # [0]
addi a11,a5,-48 # [1]
addi.n a12,a1,8 # [3] temp_offset+8
movi.n a13,0 # [4]
wur.accx_0 a13 # [5]
wur.accx_1 a13 # [6]
ee.vld.128.ip q6,a12,0 # [7] id:756
s32i.n a12,a1,32 # [8] offset_data_ptr
beqz a11,.LBB34_dspi_dotprod_off_u8_aes3 # [9]
l32i a2,a1,68 # [0] gra_spill_temp_1
ee.vld.128.ip q0,a2,16 # [2] id:771
st.qr q0,a1,48 # [3] q0
.Lt_0_24578: # 0xc3
addi a14,a5,-32 # [0]
beqz a14,.LBB43_dspi_dotprod_off_u8_aes3 # [1]
.Lt_0_26626: # 0xc9
.Lt_0_26114: # 0xc9
addi a8,a5,-16 # [0]
beqz a8,.LBB50_dspi_dotprod_off_u8_aes3 # [1]
.Lt_0_28162: # 0xcf
.Lt_0_27650: # 0xcf
addi a9,a5,-64 # [0]
beqz a9,.LBB57_dspi_dotprod_off_u8_aes3 # [1]
.Lt_0_29698: # 0xd5
.Lt_0_29186: # 0xd5
addi a10,a5,-128 # [0]
beqz a10,.LBB64_dspi_dotprod_off_u8_aes3 # [1]
movi a11,128 # [0]
bge a11,a5,.Lt_0_32514 # [1]
movi.n a12,0 # [0]
ee.ld.128.usar.ip q1,a15,16 # [1] id:833
ee.ld.128.usar.ip q2,a15,16 # [2] id:834
ee.src.q.ld.ip q3,a15,16,q1,q2 # [4] id:835
beqz.n a3,.Lt_0_32514 # [5]
ld.qr q0,a1,48 # [0] q0
l32i a14,a1,64 # [1] gra_spill_temp_0
addi a13,a5,31 # [2]
movgez a13,a5,a5 # [3]
srai a13,a13,5 # [4]
sub a14,a14,a5 # [5]
addi a14,a14,16 # [6]
addi.n a13,a13,-1 # [7]
.Lt_0_33282: # 0x105
beqz.n a13,.Lt_0_33538 # [0]
loopnez a13,.LBB277_dspi_dotprod_off_u8_aes3 # [0]
.LBB275_dspi_dotprod_off_u8_aes3: # 0x10a
ee.vmulas.u8.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:836
ee.vmulas.u8.accx.ld.ip q1,a2,16,q1,q6 # [0*II+1] id:837
ee.vmulas.u8.accx.ld.ip.qup q1,a15,16,q1,q2,q3,q0 # [0*II+3] id:838
ee.vmulas.u8.accx.ld.ip q4,a2,16,q2,q6 # [0*II+4] id:839
ee.vmulas.u8.accx.ld.ip.qup q2,a15,16,q4,q3,q0,q1 # [0*II+6] id:840
ee.vmulas.u8.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:841
ee.vmulas.u8.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+9] id:842
ee.vmulas.u8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:843
.LBB277_dspi_dotprod_off_u8_aes3: # 0x12a
.Lt_0_33538: # 0x12a
ee.vmulas.u8.accx.ld.ip.qup q4,a15,16,q0,q1,q2,q3 # [0] id:844
ee.vmulas.u8.accx.ld.ip q1,a2,16,q1,q6 # [1] id:845
movi.n a8,32 # [2]
ee.vmulas.u8.accx.ld.xp.qup q0,a15,a14,q1,q2,q3,q4 # [3] id:846
ee.vmulas.u8.accx.ld.ip q7,a2,16,q2,q6 # [4] id:847
movi.n a9,-16 # [5]
ee.vmulas.u8.accx.ld.xp.qup q2,a15,a9,q7,q3,q4,q0 # [6] id:848
ee.vmulas.u8.accx.ld.ip q5,a2,16,q3,q6 # [7] id:850
ee.ld.128.usar.xp q1,a15,a8 # [8] id:849
addi.n a12,a12,1 # [9]
ee.vmulas.u8.accx.ld.ip.qup q3,a15,16,q5,q4,q1,q2 # [10] id:851
ee.vmulas.u8.accx.ld.ip q0,a2,16,q4,q6 # [11] id:852
bne a12,a3,.Lt_0_33282 # [12]
.Lt_0_32514: # 0x156
.Lt_0_32258: # 0x156
movi.n a2,0 # [0]
rur.accx_0 a10 # [1]
addi.n a12,a7,-1 # [2]
movi.n a11,1 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:854
retw.n # [10]
.Lt_0_36098: # 0x172
.Lt_0_20226: # 0x172
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_u8_ansi # [6] dspi_dotprod_u8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB27_dspi_dotprod_off_u8_aes3: # 0x185
extui a14,a5,0,1 # [0]
beqz a14,.Lt_0_36610 # [1]
mov.n a10,a2 # [0]
mov.n a11,a3 # [1]
mov.n a12,a4 # [2]
mov.n a13,a5 # [3]
mov.n a14,a6 # [4]
mov.n a15,a7 # [5]
call8 dspi_dotprod_u8_ansi # [6] dspi_dotprod_u8_ansi
mov.n a2,a10 # [0]
retw.n # [1]
.LBB34_dspi_dotprod_off_u8_aes3: # 0x19e
ee.ld.128.usar.ip q0,a15,16 # [0] id:760
ee.ld.128.usar.ip q2,a15,16 # [1] id:761
ee.src.q.ld.ip q3,a15,16,q0,q2 # [3] id:762
beqz.n a6,.Lt_0_24578 # [4]
movi.n a10,32 # [0]
l32i a12,a1,64 # [1] gra_spill_temp_0
movi.n a11,-16 # [2]
addi a12,a12,-32 # [3]
loopgtz a6,.LBB163_dspi_dotprod_off_u8_aes3 # [4]
.LBB161_dspi_dotprod_off_u8_aes3: # 0x1b6
ee.vmulas.u8.accx.ld.ip q1,a2,16,q0,q6 # [0*II+0] id:763
ee.vmulas.u8.accx.ld.xp.qup q1,a15,a12,q1,q0,q2,q3 # [0*II+2] id:764
ee.vmulas.u8.accx.ld.ip q0,a2,16,q2,q6 # [0*II+3] id:765
ee.vmulas.u8.accx.ld.xp.qup q2,a15,a11,q0,q2,q3,q1 # [0*II+5] id:766
ee.vmulas.u8.accx.ld.ip q1,a2,16,q3,q6 # [0*II+6] id:768
ee.ld.128.usar.xp q0,a15,a10 # [0*II+7] id:767
ee.vmulas.u8.accx.ld.ip.qup q3,a15,16,q1,q3,q0,q2 # [0*II+9] id:769
.LBB163_dspi_dotprod_off_u8_aes3: # 0x1d1
st.qr q1,a1,48 # [0] q0
j .Lt_0_24578 # [1]
.LBB43_dspi_dotprod_off_u8_aes3: # 0x1d7
srli a3,a6,1 # [0]
l32i a12,a1,64 # [1] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [2] id:772
ee.ld.128.usar.ip q2,a15,16 # [3] id:773
addi a12,a12,-16 # [5]
ee.src.q.ld.xp q3,a15,a12,q1,q2 # [6] id:774
beqz.n a3,.Lt_0_26626 # [7]
ld.qr q0,a1,48 # [0] q0
movi.n a10,32 # [1]
movi.n a11,-16 # [2]
loopnez a3,.LBB186_dspi_dotprod_off_u8_aes3 # [3]
.LBB184_dspi_dotprod_off_u8_aes3: # 0x1f5
ee.vmulas.u8.accx.ld.xp.qup q0,a15,a11,q0,q1,q2,q3 # [0*II+0] id:775
ee.vmulas.u8.accx.ld.ip q3,a2,16,q1,q6 # [0*II+1] id:776
ee.ld.128.usar.xp q1,a15,a10 # [0*II+2] id:777
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a12,q3,q2,q1,q0 # [0*II+4] id:778
ee.vmulas.u8.accx.ld.ip q4,a2,16,q2,q6 # [0*II+5] id:779
ee.vmulas.u8.accx.ld.xp.qup q2,a15,a11,q4,q1,q0,q3 # [0*II+7] id:780
ee.vmulas.u8.accx.ld.ip q3,a2,16,q1,q6 # [0*II+8] id:781
ee.ld.128.usar.xp q1,a15,a10 # [0*II+9] id:782
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a12,q3,q0,q1,q2 # [0*II+11] id:783
ee.vmulas.u8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+12] id:784
.LBB186_dspi_dotprod_off_u8_aes3: # 0x21b
st.qr q0,a1,48 # [0] q0
j .Lt_0_26626 # [1]
.LBB50_dspi_dotprod_off_u8_aes3: # 0x221
srli a3,a3,2 # [0]
movi.n a13,-16 # [1]
l32i a11,a1,64 # [2] gra_spill_temp_0
addi a15,a15,16 # [3]
addi a11,a11,16 # [4]
ee.ld.128.usar.xp q2,a15,a13 # [5] id:785
ee.ld.128.usar.xp q1,a15,a11 # [6] id:786
ee.src.q.ld.xp q3,a15,a13,q1,q2 # [8] id:787
ee.ld.128.usar.xp q2,a15,a11 # [9] id:788
beqz.n a3,.Lt_0_28162 # [10]
ld.qr q0,a1,48 # [0] q0
movi.n a10,-16 # [1]
loopnez a3,.LBB209_dspi_dotprod_off_u8_aes3 # [2]
.LBB207_dspi_dotprod_off_u8_aes3: # 0x245
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a10,q0,q1,q2,q3 # [0*II+0] id:789
ee.vmulas.u8.accx.ld.ip q0,a2,16,q1,q6 # [0*II+1] id:790
ee.ld.128.usar.xp q1,a15,a11 # [0*II+2] id:791
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a10,q0,q2,q1,q3 # [0*II+4] id:792
ee.vmulas.u8.accx.ld.ip q0,a2,16,q2,q6 # [0*II+5] id:793
ee.ld.128.usar.xp q4,a15,a11 # [0*II+6] id:794
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a10,q0,q1,q4,q3 # [0*II+8] id:795
ee.vmulas.u8.accx.ld.ip q0,a2,16,q1,q6 # [0*II+9] id:796
ee.ld.128.usar.xp q1,a15,a11 # [0*II+10] id:797
ee.vmulas.u8.accx.ld.xp.qup q3,a15,a10,q0,q4,q1,q3 # [0*II+12] id:798
ee.vmulas.u8.accx.ld.ip q0,a2,16,q4,q6 # [0*II+13] id:799
ee.ld.128.usar.xp q2,a15,a11 # [0*II+14] id:800
.LBB209_dspi_dotprod_off_u8_aes3: # 0x271
st.qr q0,a1,48 # [0] q0
j .Lt_0_28162 # [1]
.LBB57_dspi_dotprod_off_u8_aes3: # 0x277
ee.ld.128.usar.ip q1,a15,16 # [0] id:801
ee.ld.128.usar.ip q2,a15,16 # [1] id:802
ee.src.q.ld.ip q3,a15,16,q1,q2 # [3] id:803
beqz.n a3,.Lt_0_29698 # [4]
ld.qr q0,a1,48 # [0] q0
movi.n a10,32 # [1]
l32i a12,a1,64 # [2] gra_spill_temp_0
movi.n a11,-16 # [3]
sub a12,a12,a5 # [4]
addi a12,a12,16 # [5]
loopnez a3,.LBB232_dspi_dotprod_off_u8_aes3 # [6]
.LBB230_dspi_dotprod_off_u8_aes3: # 0x295
ee.vmulas.u8.accx.ld.ip.qup q0,a15,16,q0,q1,q2,q3 # [0*II+0] id:804
ee.vmulas.u8.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:805
ee.vmulas.u8.accx.ld.xp.qup q4,a15,a12,q4,q2,q3,q0 # [0*II+3] id:806
ee.vmulas.u8.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:807
ee.vmulas.u8.accx.ld.xp.qup q2,a15,a11,q1,q3,q0,q4 # [0*II+6] id:808
ee.vmulas.u8.accx.ld.ip q4,a2,16,q3,q6 # [0*II+7] id:809
ee.ld.128.usar.xp q1,a15,a10 # [0*II+8] id:810
ee.vmulas.u8.accx.ld.ip.qup q3,a15,16,q4,q0,q1,q2 # [0*II+10] id:811
ee.vmulas.u8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+11] id:812
.LBB232_dspi_dotprod_off_u8_aes3: # 0x2b8
st.qr q0,a1,48 # [0] q0
j .Lt_0_29698 # [1]
.LBB64_dspi_dotprod_off_u8_aes3: # 0x2be
movi.n a10,32 # [0]
movi.n a11,-16 # [1]
l32i a12,a1,64 # [2] gra_spill_temp_0
ee.ld.128.usar.ip q1,a15,16 # [3] id:813
ee.ld.128.usar.ip q2,a15,16 # [4] id:814
sub a12,a12,a5 # [6]
addi a12,a12,16 # [7]
ld.qr q0,a1,48 # [8] q0
ee.src.q.ld.ip q3,a15,16,q1,q2 # [9] id:815
mov.n a8,a15 # [10]
loopnez a3,.LBB254_dspi_dotprod_off_u8_aes3 # [11]
.LBB252_dspi_dotprod_off_u8_aes3: # 0x2dc
ee.vmulas.u8.accx.ld.ip.qup q0,a8,16,q0,q1,q2,q3 # [0*II+0] id:816
ee.vmulas.u8.accx.ld.ip q4,a2,16,q1,q6 # [0*II+1] id:817
ee.vmulas.u8.accx.ld.ip.qup q4,a8,16,q4,q2,q3,q0 # [0*II+3] id:818
ee.vmulas.u8.accx.ld.ip q1,a2,16,q2,q6 # [0*II+4] id:819
ee.vmulas.u8.accx.ld.ip.qup q1,a8,16,q1,q3,q0,q4 # [0*II+6] id:820
ee.vmulas.u8.accx.ld.ip q5,a2,16,q3,q6 # [0*II+7] id:821
ee.vmulas.u8.accx.ld.ip.qup q5,a8,16,q5,q0,q4,q1 # [0*II+9] id:822
ee.vmulas.u8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+10] id:823
ee.vmulas.u8.accx.ld.ip.qup q0,a8,16,q0,q4,q1,q5 # [0*II+12] id:824
ee.vmulas.u8.accx.ld.ip q4,a2,16,q4,q6 # [0*II+13] id:825
ee.vmulas.u8.accx.ld.xp.qup q4,a8,a12,q4,q1,q5,q0 # [0*II+15] id:826
ee.vmulas.u8.accx.ld.ip q1,a2,16,q1,q6 # [0*II+16] id:827
ee.vmulas.u8.accx.ld.xp.qup q2,a8,a11,q1,q5,q0,q4 # [0*II+18] id:828
ee.vmulas.u8.accx.ld.ip q4,a2,16,q5,q6 # [0*II+19] id:829
ee.ld.128.usar.xp q1,a8,a10 # [0*II+20] id:830
ee.vmulas.u8.accx.ld.ip.qup q3,a8,16,q4,q0,q1,q2 # [0*II+22] id:831
ee.vmulas.u8.accx.ld.ip q0,a2,16,q0,q6 # [0*II+23] id:832
.LBB254_dspi_dotprod_off_u8_aes3: # 0x31f
movi.n a2,0 # [0]
movi.n a11,1 # [1]
addi.n a12,a7,-1 # [2]
rur.accx_0 a10 # [3]
ssl a12 # [4]
sll a11,a11 # [5]
ssr a7 # [6]
add.n a10,a10,a11 # [7]
sra a10,a10 # [8]
s8i a10,a4,0 # [9] id:854
retw.n # [10]
#endif // dsps_dotprod_s16_aes3_enabled
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