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stsp/binutils-ia16
| 2,963
|
sim/testsuite/bfin/c_loopsetup_nested_prelc.s
|
//Original:/testcases/core/c_loopsetup_nested_prelc/c_loopsetup_nested_prelc.dsp
// Spec Reference: loopsetup nested preload lc0 lc1
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x12;
R3 = 0x14;
R4 = 0x18;
R5 = 0x16;
R6 = 0x16;
R7 = 0x18;
LC0 = R0;
LC1 = R1;
LSETUP ( start1 , end1 ) LC0;
start1: R0 += 1;
R1 += -2;
LSETUP ( start2 , end2 ) LC1;
start2: R4 += 4;
end2: R5 += -5;
R3 += 1;
end1: R2 += 3;
R3 += 4;
LC0 = R7;
LC1 = R6;
LSETUP ( start3 , end3 ) LC0;
start3: R6 += 6;
LSETUP ( start4 , end4 ) LC1;
start4: R0 += 1;
R1 += -2;
end4: R2 += 3;
R3 += 4;
end3: R7 += -7;
R3 += 1;
CHECKREG r0, 0x00000037;
CHECKREG r1, 0xFFFFFFAC;
CHECKREG r2, 0x000000A8;
CHECKREG r3, 0x0000007E;
CHECKREG r4, 0x00000068;
CHECKREG r5, 0xFFFFFFB2;
CHECKREG r6, 0x000000A6;
CHECKREG r7, 0xFFFFFF70;
R0 = 0x05;
R1 = 0x10;
R2 = 0x08;
R3 = 0x0C;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LC0 = R2;
LC1 = R3;
LSETUP ( start5 , end5 ) LC0;
start5: R4 += 1;
LSETUP ( start6 , end6 ) LC1;
start6: R6 += 4;
end6: R7 += -5;
R3 += 6;
end5: R5 += -2;
R3 += 3;
CHECKREG r0, 0x00000005;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000008;
CHECKREG r3, 0x0000003F;
CHECKREG r4, 0x00000048;
CHECKREG r5, 0x00000040;
CHECKREG r6, 0x000000AC;
CHECKREG r7, 0x00000011;
LSETUP ( start7 , end7 ) LC0;
start7: R4 += 4;
end7: R5 += -5;
R3 += 6;
CHECKREG r0, 0x00000005;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000008;
CHECKREG r3, 0x00000045;
CHECKREG r4, 0x0000004C;
CHECKREG r5, 0x0000003B;
CHECKREG r6, 0x000000AC;
CHECKREG r7, 0x00000011;
P1 = 12;
P2 = 14;
P3 = 16;
P4 = 18;
P5 = 12;
SP = 14;
FP = 16;
R0 = 0x05;
R1 = 0x10;
R2 = 0x14;
R3 = 0x18;
R4 = 0x16;
R5 = 0x04;
R6 = 0x30;
R7 = 0x30;
LC0 = R5;
LC1 = R4;
LSETUP ( start11 , end11 ) LC0;
start11: R0 += 1;
R1 += -1;
LSETUP ( start15 , end15 ) LC1;
start15: R4 += 1;
end15: R5 += -1;
R3 += 1;
end11: R2 += 1;
R3 += 1;
LSETUP ( start13 , end13 ) LC0 = P5;
start13: R6 += 1;
LSETUP ( start12 , end12 ) LC1 = P2;
start12: R4 += 1;
end12: R5 += -1;
R3 += 1;
end13: R7 += -1;
R3 += 1;
CHECKREG r0, 0x00000009;
CHECKREG r1, 0x0000000C;
CHECKREG r2, 0x00000018;
CHECKREG r3, 0x0000002A;
CHECKREG r4, 0x000000D7;
CHECKREG r5, 0xFFFFFF43;
CHECKREG r6, 0x0000003C;
CHECKREG r7, 0x00000024;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x14;
R7 = 0x08;
P4 = 6;
FP = 8;
LC0 = R6;
LC1 = R7;
LSETUP ( start14 , end14 ) LC0 = P4;
start14: R0 += 1;
R1 += -1;
LSETUP ( start16 , end16 ) LC1;
start16: R6 += 1;
end16: R7 += -1;
R3 += 1;
LSETUP ( start17 , end17 ) LC1 = FP >> 1;
start17: R4 += 1;
end17: R5 += -1;
R3 += 1;
end14: R2 += 1;
R3 += 1;
CHECKREG r0, 0x0000000B;
CHECKREG r1, 0x0000000A;
CHECKREG r2, 0x00000026;
CHECKREG r3, 0x0000003D;
CHECKREG r4, 0x00000058;
CHECKREG r5, 0x00000038;
CHECKREG r6, 0x00000021;
CHECKREG r7, 0xFFFFFFFB;
pass
|
stsp/binutils-ia16
| 1,114
|
sim/testsuite/bfin/cec-system-call.S
|
# Blackfin testcase for returning to the right place while bouncing between
# multiple CEC levels (like in a Linux system call)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
# This test keeps P5 as the base of the EVT table
.macro set_evt lvl:req, sym:req
loadsym R1, \sym;
[P5 + 4 * \lvl\()] = R1;
.endm
start
# First mark all EVTs as fails (they shouldn't be activated)
imm32 P5, EVT0;
P1 = P5;
loadsym R1, fail_lvl
imm32 P2, 16
LSETUP (1f, 1f) LC0 = P2;
1: [P1++] = R1;
# The OS exception handler
set_evt 3, _evx;
# The OS system call handler
set_evt 15, _evt15;
# Lower ourselves to userspace
loadsym R1, _user;
loadsym R2, _next_user;
RETI = R1;
R7 = -1;
sti R7;
RTI;
_user:
EXCPT 0;
_next_user:
dbg_pass
_evx:
# RETX should be pointing to the right place
R1 = RETX;
CC = R1 == R2;
IF !CC JUMP fail_lvl;
# Lower ourselves to the system call handler
RAISE 15;
RTX;
_evt15:
# RETI should be pointing to the right place
R1 = RETI;
CC = R1 == R2;
IF !CC JUMP fail_lvl;
# Return to userspace now
RTI;
fail_lvl:
dbg_fail
|
stsp/binutils-ia16
| 5,610
|
sim/testsuite/bfin/c_ccflag_dr_dr_uu.s
|
//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr_uu/c_ccflag_dr_dr_uu.dsp
// Spec Reference: ccflags dr-dr_uu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00110022;
imm32 r1, 0x00110022;
imm32 r2, 0x00330044;
imm32 r3, 0x00550066;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
imm32 r7, 0x00000000;
ASTAT = R7;
R4 = ASTAT;
// positive dreg-1 EQUAL to positive dreg-2
CC = R0 == R1;
R5 = ASTAT;
CC = R0 < R1 (IU);
R6 = ASTAT;
CC = R0 <= R1 (IU);
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00001025;
CHECKREG r6, 0x00001005;
CHECKREG r7, 0x00001025;
CC = R0 < R1 (IU);
R4 = ASTAT;
CC = R0 <= R1 (IU);
R5 = ASTAT;
CHECKREG r4, 0x00001005;
CHECKREG r5, 0x00001025;
// positive dreg-1 GREATER than positive dreg-2
CC = R3 == R2;
R5 = ASTAT;
CC = R3 < R2 (IU);
R6 = ASTAT;
CC = R3 <= R2 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00001004;
CHECKREG r6, 0x00001004;
CHECKREG r7, 0x00001004;
CC = R3 < R2 (IU);
R4 = ASTAT;
CC = R3 <= R2 (IU);
R5 = ASTAT;
CHECKREG r4, 0x00001004;
CHECKREG r5, 0x00001004;
// positive dreg-1 LESS than positive dreg-2
CC = R2 == R3;
R5 = ASTAT;
CC = R2 < R3 (IU);
R6 = ASTAT;
CC = R2 <= R3 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
CC = R2 < R3 (IU);
R4 = ASTAT;
CC = R2 <= R3 (IU);
R5 = ASTAT;
CHECKREG r4, 0x00000022;
CHECKREG r5, 0x00000022;
imm32 r0, 0x01230123;
imm32 r1, 0x81230123;
imm32 r2, 0x04560456;
imm32 r3, 0x87890789;
// operate on negative number
R7 = 0;
ASTAT = R7;
R4 = ASTAT;
// positive dreg-1 GREATER than negative dreg-2
CC = R0 == R1;
R5 = ASTAT;
CC = R0 < R1 (IU);
R6 = ASTAT;
CC = R0 <= R1 (IU);
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
// negative dreg-1 LESS than POSITIVE dreg-2 small
CC = R3 == R2;
R5 = ASTAT;
CC = R3 < R2 (IU);
R6 = ASTAT;
CC = R3 <= R2 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00001006;
CHECKREG r6, 0x00001004;
CHECKREG r7, 0x00001004;
// negative dreg-1 GREATER than negative dreg-2
CC = R1 == R3;
R5 = ASTAT;
CC = R1 < R3 (IU);
R6 = ASTAT;
CC = R1 <= R3 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
// negative dreg-1 LESS than negative dreg-2
CC = R3 == R1;
R5 = ASTAT;
CC = R3 < R1 (IU);
R6 = ASTAT;
CC = R3 <= R1 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00001004;
CHECKREG r6, 0x00001004;
CHECKREG r7, 0x00001004;
imm32 r0, 0x80230123;
imm32 r1, 0x00230123;
imm32 r2, 0x80560056;
imm32 r3, 0x00890089;
// operate on negative number
R7 = 0;
ASTAT = R7;
R4 = ASTAT;
// negative dreg-1 LESS than POSITIVE dreg-2
CC = R2 == R3;
R5 = ASTAT;
CC = R2 < R3 (IU);
R6 = ASTAT;
CC = R2 <= R3 (IU);
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00001006; // overflow and carry but not negative
CHECKREG r6, 0x00001004; // cc overflow, carry and negative
CHECKREG r7, 0x00001004;
imm32 r4, 0x44444444;
imm32 r5, 0x55555555;
imm32 r6, 0x66666666;
imm32 r7, 0x77777777;
imm32 r0, 0x00000000;
imm32 r1, 0x11111111;
imm32 r2, 0x22222222;
imm32 r3, 0x33333333;
ASTAT = R0;
R3 = ASTAT;
NOP;
CHECKREG r3, 0x00000000;
// positive dreg-1 EQUAL to positive dreg-2
CC = R4 == R5;
R0 = ASTAT;
CC = R4 < R5 (IU);
R1 = ASTAT;
CC = R4 <= R5 (IU);
R2 = ASTAT;
CC = R4 < R5 (IU);
R3 = ASTAT;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000022;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CC = R4 <= R5 (IU);
R0 = ASTAT;
NOP;
CHECKREG r0, 0x00000022;
// positive dreg-1 GREATER than positive dreg-2
CC = R7 == R6;
R0 = ASTAT;
CC = R7 < R6 (IU);
R1 = ASTAT;
CC = R7 <= R6 (IU);
R2 = ASTAT;
CC = R7 < R6 (IU);
R3 = ASTAT;
CHECKREG r0, 0x00001004;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001004;
CC = R7 <= R6 (IU);
R0 = ASTAT;
NOP;
CHECKREG r0, 0x00001004;
// positive dreg-1 LESS than positive dreg-2
CC = R6 == R7;
R0 = ASTAT;
CC = R6 < R7 (IU);
R1 = ASTAT;
CC = R6 <= R7 (IU);
R2 = ASTAT;
CC = R6 < R7 (IU);
R3 = ASTAT;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000022;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CC = R6 <= R7 (IU);
R0 = ASTAT;
NOP;
CHECKREG r0, 0x00000022;
imm32 r4, 0x01230123;
imm32 r5, 0x81230123;
imm32 r6, 0x04560456;
imm32 r7, 0x87890789;
// operate on negative number
R0 = 0;
ASTAT = R0;
R3 = ASTAT;
CHECKREG r3, 0x00000000;
// positive dreg-1 GREATER than negative dreg-2
CC = R4 == R5;
R1 = ASTAT;
CC = R4 < R5 (IU);
R2 = ASTAT;
CC = R4 <= R5 (IU);
R3 = ASTAT;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
// negative dreg-1 LESS than POSITIVE dreg-2 small
CC = R7 == R6;
R0 = ASTAT;
CC = R7 < R6 (IU);
R1 = ASTAT;
CC = R7 <= R6 (IU);
R2 = ASTAT;
CHECKREG r0, 0x00001006;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
// negative dreg-1 GREATER than negative dreg-2
CC = R5 == R7;
R0 = ASTAT;
CC = R5 < R7 (IU);
R1 = ASTAT;
CC = R5 <= R7 (IU);
R2 = ASTAT;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000022;
CHECKREG r2, 0x00000022;
// negative dreg-1 LESS than negative dreg-2
CC = R7 == R5;
R1 = ASTAT;
CC = R7 < R5 (IU);
R2 = ASTAT;
CC = R7 <= R5 (IU);
R3 = ASTAT;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001004;
imm32 r4, 0x80230123;
imm32 r5, 0x00230123;
imm32 r6, 0x80560056;
imm32 r7, 0x00890089;
// operate on negative number
R3 = 0;
ASTAT = R3;
R0 = ASTAT;
// negative dreg-1 LESS than POSITIVE dreg-2
CC = R6 == R7;
R1 = ASTAT;
CC = R6 < R7 (IU);
R2 = ASTAT;
CC = R6 <= R7 (IU);
R3 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00001006; // overflow and carry but not negative
CHECKREG r2, 0x00001004; // cc overflow, carry and negative
CHECKREG r3, 0x00001004;
pass;
|
stsp/binutils-ia16
| 3,814
|
sim/testsuite/bfin/c_dsp32mac_dr_a1a0.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0/c_dsp32mac_dr_a1a0.dsp
// Spec Reference: dsp32mac dr_a1a0
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0;
ASTAT = R0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xb2bcfec7;
imm32 r2, 0xc1348679;
imm32 r3, 0xd0049007;
imm32 r4, 0xefbc5569;
imm32 r5, 0xcd35560b;
imm32 r6, 0xe00c807d;
imm32 r7, 0xf78e9008;
A1 = A0 = 0;
R6.H = (A1 += R0.L * R0.L), R6.L = (A0 = R0.L * R0.L);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 += R2.L * R3.L), R1.L = (A0 -= R2.H * R3.L);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 -= R4.L * R5.L), R2.L = (A0 += R4.H * R5.H);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 += R0.L * R7.L), R3.L = (A0 += R0.L * R7.H);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0x13545ABD;
CHECKREG r1, 0x7FFF0964;
CHECKREG r2, 0x71380FD8;
CHECKREG r3, 0x21D909DC;
CHECKREG r4, 0x21D8C27A;
CHECKREG r5, 0x09DB89BE;
CHECKREG r6, 0x40534053;
CHECKREG r7, 0xF78E9008;
CHECKREG p1, 0x4052DF12;
CHECKREG p2, 0x4052DF12;
CHECKREG p3, 0xAAA259B0;
CHECKREG p4, 0x0963CE3A;
CHECKREG p5, 0x713876AA;
CHECKREG fp, 0x0FD82A12;
imm32 r0, 0x13545abd;
imm32 r1, 0x22bcfec7;
imm32 r2, 0x43348679;
imm32 r3, 0x50049007;
imm32 r4, 0x6fbc5569;
imm32 r5, 0x7d35560b;
imm32 r6, 0x800c807d;
imm32 r7, 0xf98e9008;
A1 = A0 = 0;
R0.H = (A1 += R1.L * R0.H), R0.L = (A0 = R1.L * R0.L);
P1 = A1.w;
P2 = A0.w;
R6.H = (A1 += R2.L * R2.H), R6.L = (A0 -= R2.H * R2.L);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 -= R4.L * R5.H), R2.L = (A0 += R4.H * R5.H);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 += R3.L * R7.H), R3.L = (A0 -= R3.L * R7.H);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0xFFD1FF22;
CHECKREG r1, 0x22BCFEC7;
CHECKREG r2, 0x80007FFF;
CHECKREG r3, 0x80007FFF;
CHECKREG r4, 0x721A320A;
CHECKREG r5, 0xA6989CC2;
CHECKREG r6, 0xC0033EF0;
CHECKREG r7, 0xF98E9008;
CHECKREG p1, 0xFFD0BC98;
CHECKREG p2, 0xFF221DD6;
CHECKREG p3, 0xC002B3C0;
CHECKREG p4, 0x3EF026AE;
CHECKREG p5, 0x6C76CC46;
CHECKREG fp, 0xAC3C0286;
imm32 r0, 0x13545abd;
imm32 r1, 0x42bcfec7;
imm32 r2, 0x51348679;
imm32 r3, 0x60049007;
imm32 r4, 0x7fbc5569;
imm32 r5, 0x8d35560b;
imm32 r6, 0x900c807d;
imm32 r7, 0xa78e9008;
A1 = A0 = 0;
R0.H = (A1 -= R1.H * R0.L), R0.L = (A0 = R1.L * R0.L);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 += R2.H * R3.L), R1.L = (A0 -= R2.H * R3.L);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 = R4.H * R5.L), R2.L = (A0 += R4.H * R5.H);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 -= R6.H * R7.L), R3.L = (A0 += R6.L * R7.H);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0xD0B1FF22;
CHECKREG r1, 0x89A8462B;
CHECKREG r2, 0x55DDD39D;
CHECKREG r3, 0xF3EF2BB9;
CHECKREG r4, 0xF3EEC968;
CHECKREG r5, 0x2BB8C982;
CHECKREG r6, 0x900C807D;
CHECKREG r7, 0xA78E9008;
CHECKREG p1, 0xD0B14668;
CHECKREG p2, 0xFF221DD6;
CHECKREG p3, 0x89A83740;
CHECKREG p4, 0x462B2CFE;
CHECKREG p5, 0x55DD4A28;
CHECKREG fp, 0xD39D28D6;
imm32 r0, 0x03545abd;
imm32 r1, 0xb3bcfec7;
imm32 r2, 0x24348679;
imm32 r3, 0x60049007;
imm32 r4, 0x7fbc5569;
imm32 r5, 0x9d35560b;
imm32 r6, 0xa00c807d;
imm32 r7, 0x078e9008;
A1 = A0 = 0;
R0.H = (A1 += R1.H * R0.H), R0.L = (A0 -= R1.L * R0.L);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 -= R2.H * R3.H), R1.L = (A0 = R2.H * R3.L);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 = R4.H * R5.H), R2.L = (A0 += R4.H * R5.H);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 += R6.H * R7.H), R3.L = (A0 -= R6.L * R7.H);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0xFE0400DE;
CHECKREG r1, 0xE2DCE054;
CHECKREG r2, 0x9D698000;
CHECKREG r3, 0x97C08545;
CHECKREG r4, 0x97BFB128;
CHECKREG r5, 0x85449604;
CHECKREG r6, 0xA00C807D;
CHECKREG r7, 0x078E9008;
CHECKREG p1, 0xFE045B60;
CHECKREG p2, 0x00DDE22A;
CHECKREG p3, 0xE2DC39C0;
CHECKREG p4, 0xE0547AD8;
CHECKREG p5, 0x9D697BD8;
CHECKREG fp, 0x7DBDF6B0;
pass
|
stsp/binutils-ia16
| 1,626
|
sim/testsuite/bfin/c_cc_flag_ccmv_depend.S
|
//Original:/proj/frio/dv/testcases/core/c_cc_flag_ccmv_depend/c_cc_flag_ccmv_depend.dsp
// Spec Reference: ccflag followed by ccmv (# stalls)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00740088;
imm32 r5, 0x609950aa;
imm32 r6, 0x20bb06cc;
imm32 r7, 0xd90e108f;
imm32 p1, 0x1401101f;
imm32 p2, 0x3204108e;
imm32 fp, 0xd93f1084;
imm32 p4, 0xeb04106f;
imm32 p5, 0xa90e5089;
CC = R7; // cc2dreg
IF CC R0 = R3; // ccmov
R6 = R0 + R4;
CC = ! CC; // cc2dreg
IF CC R1 = P1; // ccmov
CC = R5 < R1; // ccflag
R1 = ASTAT;
IF !CC R2 = R5; // ccmov
CC = R2 == R3; // ccflag
IF CC P1 = R4; // ccmov
CC = ! CC;
CC = R7 < R5;
IF CC P2 = P5; // ccmov
CC = P5 == 3;
IF CC FP = R2; // ccmov
R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair
CC = A0 == A1;
IF !CC R3 = R6; // ccmov
R7 = R3 + R2;
A0 += A1 (W32); // dsp32alu a0 + a1
CC = A0 < A1;
IF CC R4 = P4; // ccmov
R6 = R4;
R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac
CC = A0 <= A1;
IF CC R5 = P5; // ccmov
A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac
CC = A0 <= A1;
IF CC P5 = R6; // ccmov
CHECKREG r0, 0x07300007;
CHECKREG r1, (_AC0|_AC0_COPY);
CHECKREG r2, 0x00766960;
CHECKREG r3, 0x07A4008F;
CHECKREG r4, 0xEB04106F;
CHECKREG r5, 0xA90E5089;
CHECKREG r6, 0xEB04106F;
CHECKREG r7, 0x075D69EF;
CHECKREG p1, 0x1401101F;
CHECKREG p2, 0xA90E5089;
CHECKREG fp, 0xD93F1084;
CHECKREG p4, 0xEB04106F;
CHECKREG p5, 0xA90E5089;
pass
|
stsp/binutils-ia16
| 2,025
|
sim/testsuite/bfin/c_ldimmhalf_lzhi_dr.s
|
//Original:/testcases/core/c_ldimmhalf_lzhi_dr/c_ldimmhalf_lzhi_dr.dsp
// Spec Reference: ldimmhalf lz & hi dreg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0 = 0x0001 (Z);
R0.H = 0x0000;
R1 = 0x0003 (Z);
R1.H = 0x0002;
R2 = 0x0005 (Z);
R2.H = 0x0004;
R3 = 0x0007 (Z);
R3.H = 0x0006;
R4 = 0x0009 (Z);
R4.H = 0x0008;
R5 = 0x000b (Z);
R5.H = 0x000a;
R6 = 0x000d (Z);
R6.H = 0x000c;
R7 = 0x000f (Z);
R7.H = 0x000e;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00020003;
CHECKREG r2, 0x00040005;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0x00080009;
CHECKREG r5, 0x000a000b;
CHECKREG r6, 0x000c000d;
CHECKREG r7, 0x000e000f;
R0 = 0x0010 (Z);
R0.H = 0x0000;
R1 = 0x0030 (Z);
R1.H = 0x0020;
R2 = 0x0050 (Z);
R2.H = 0x0040;
R3 = 0x0070 (Z);
R3.H = 0x0060;
R4 = 0x0090 (Z);
R4.H = 0x0080;
R5 = 0x00b0 (Z);
R5.H = 0x00a0;
R6 = 0x00d0 (Z);
R6.H = 0x00c0;
R7 = 0x00f0 (Z);
R7.H = 0x00e0;
CHECKREG r0, 0x00000010;
CHECKREG r1, 0x00200030;
CHECKREG r2, 0x00400050;
CHECKREG r3, 0x00600070;
CHECKREG r4, 0x00800090;
CHECKREG r5, 0x00a000b0;
CHECKREG r6, 0x00c000d0;
CHECKREG r7, 0x00e000f0;
R0 = 0x0100 (Z);
R0.H = 0x0000;
R1 = 0x0300 (Z);
R1.H = 0x0200;
R2 = 0x0500 (Z);
R2.H = 0x0400;
R3 = 0x0700 (Z);
R3.H = 0x0600;
R4 = 0x0900 (Z);
R4.H = 0x0800;
R5 = 0x0b00 (Z);
R5.H = 0x0a00;
R6 = 0x0d00 (Z);
R6.H = 0x0c00;
R7 = 0x0f00 (Z);
R7.H = 0x0e00;
CHECKREG r0, 0x00000100;
CHECKREG r1, 0x02000300;
CHECKREG r2, 0x04000500;
CHECKREG r3, 0x06000700;
CHECKREG r4, 0x08000900;
CHECKREG r5, 0x0a000b00;
CHECKREG r6, 0x0c000d00;
CHECKREG r7, 0x0e000f00;
R0 = 0x1000 (Z);
R0.H = 0x0000;
R1 = 0x3000 (Z);
R1.H = 0x2000;
R2 = 0x5000 (Z);
R2.H = 0x4000;
R3 = 0x7000 (Z);
R3.H = 0x6000;
R4 = 0x9000 (Z);
R4.H = 0x8000;
R5 = 0xb000 (Z);
R5.H = 0xa000;
R6 = 0xd000 (Z);
R6.H = 0xc000;
R7 = 0xf000 (Z);
R7.H = 0xe000;
CHECKREG r0, 0x00001000;
CHECKREG r1, 0x20003000;
CHECKREG r2, 0x40005000;
CHECKREG r3, 0x60007000;
CHECKREG r4, 0x80009000;
CHECKREG r5, 0xa000b000;
CHECKREG r6, 0xc000d000;
CHECKREG r7, 0xe000f000;
pass
|
stsp/binutils-ia16
| 2,290
|
sim/testsuite/bfin/c_ccmv_ncc_dr_dr.s
|
//Original:/testcases/core/c_ccmv_ncc_dr_dr/c_ccmv_ncc_dr_dr.dsp
// Spec Reference: ccmv !cc dreg = dreg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x808d2301;
imm32 r1, 0x90021053;
imm32 r2, 0x21041405;
imm32 r3, 0x60261507;
imm32 r4, 0x50447609;
imm32 r5, 0xdfe5500b;
imm32 r6, 0x2a0c660d;
imm32 r7, 0xd90e1b8f;
IF !CC R0 = R0;
IF !CC R1 = R3;
IF !CC R2 = R5;
IF !CC R3 = R2;
CC = ! CC;
IF !CC R4 = R6;
IF !CC R5 = R1;
IF !CC R6 = R7;
CC = ! CC;
IF !CC R7 = R4;
CHECKREG r0, 0x808D2301;
CHECKREG r1, 0x60261507;
CHECKREG r2, 0xDFE5500B;
CHECKREG r3, 0xDFE5500B;
CHECKREG r4, 0x50447609;
CHECKREG r5, 0xDFE5500B;
CHECKREG r6, 0x2A0C660D;
CHECKREG r7, 0x50447609;
imm32 r0, 0x308d2301;
imm32 r1, 0xd4023053;
imm32 r2, 0x2f041405;
imm32 r3, 0x60f61507;
imm32 r4, 0xd0487f09;
imm32 r5, 0x300b900b;
imm32 r6, 0x2a0cd60d;
imm32 r7, 0xd90e189f;
IF !CC R4 = R3;
IF !CC R5 = R7;
IF !CC R6 = R1;
IF !CC R7 = R2;
CC = ! CC;
IF !CC R0 = R6;
IF !CC R1 = R5;
IF !CC R2 = R4;
CC = ! CC;
IF !CC R3 = R0;
CHECKREG r0, 0x308D2301;
CHECKREG r1, 0xD4023053;
CHECKREG r2, 0x2F041405;
CHECKREG r3, 0x308D2301;
CHECKREG r4, 0x60F61507;
CHECKREG r5, 0xD90E189F;
CHECKREG r6, 0xD4023053;
CHECKREG r7, 0x2F041405;
imm32 r0, 0x708d2301;
imm32 r1, 0xd8021053;
imm32 r2, 0x2f041405;
imm32 r3, 0x65b61507;
imm32 r4, 0x59487609;
imm32 r5, 0x3005900b;
imm32 r6, 0x2abc660d;
imm32 r7, 0xd90e108f;
IF !CC R0 = R2;
IF !CC R1 = R3;
CC = ! CC;
IF !CC R2 = R5;
IF !CC R3 = R7;
CC = ! CC;
IF !CC R4 = R1;
IF !CC R5 = R4;
IF !CC R6 = R7;
IF !CC R7 = R6;
CHECKREG r0, 0x2F041405;
CHECKREG r1, 0x65B61507;
CHECKREG r2, 0x2F041405;
CHECKREG r3, 0x65B61507;
CHECKREG r4, 0x65B61507;
CHECKREG r5, 0x65B61507;
CHECKREG r6, 0xD90E108F;
CHECKREG r7, 0xD90E108F;
imm32 r0, 0xc08d2301;
imm32 r1, 0xdb021053;
imm32 r2, 0x2f041405;
imm32 r3, 0x64b61507;
imm32 r4, 0x50487609;
imm32 r5, 0x30f5900b;
imm32 r6, 0x2a4c660d;
imm32 r7, 0x895e108f;
IF !CC R4 = R3;
IF !CC R5 = R7;
CC = ! CC;
IF !CC R6 = R2;
IF !CC R7 = R6;
CC = ! CC;
IF !CC R0 = R1;
IF !CC R1 = R2;
IF !CC R2 = R0;
IF !CC R3 = R4;
CHECKREG r0, 0xDB021053;
CHECKREG r1, 0x2F041405;
CHECKREG r2, 0xDB021053;
CHECKREG r3, 0x64B61507;
CHECKREG r4, 0x64B61507;
CHECKREG r5, 0x895E108F;
CHECKREG r6, 0x2A4C660D;
CHECKREG r7, 0x895E108F;
pass
|
stsp/binutils-ia16
| 1,478
|
sim/testsuite/bfin/c_pushpopmultiple_preg.s
|
//Original:/testcases/core/c_pushpopmultiple_preg/c_pushpopmultiple_preg.dsp
// Spec Reference: pushpopmultiple preg
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
P1 = 0xa1 (X);
P2 = 0xa2 (X);
P3 = 0xa3 (X);
P4 = 0xa4 (X);
P5 = 0xa5 (X);
[ -- SP ] = ( P5:1 );
P1 = 0;
P2 = 0;
P3 = 0;
P4 = 0;
P5 = 0;
( P5:1 ) = [ SP ++ ];
CHECKREG p1, 0x000000a1;
CHECKREG p2, 0x000000a2;
CHECKREG p3, 0x000000a3;
CHECKREG p4, 0x000000a4;
CHECKREG p5, 0x000000a5;
P2 = 0xb2 (X);
P3 = 0xb3 (X);
P4 = 0xb4 (X);
P5 = 0xb5 (X);
[ -- SP ] = ( P5:2 );
P2 = 0;
P3 = 0;
P4 = 0;
P5 = 0;
( P5:2 ) = [ SP ++ ];
CHECKREG p1, 0x000000a1;
CHECKREG p2, 0x000000b2;
CHECKREG p3, 0x000000b3;
CHECKREG p4, 0x000000b4;
CHECKREG p5, 0x000000b5;
P3 = 0xc3 (X);
P4 = 0xc4 (X);
P5 = 0xc5 (X);
[ -- SP ] = ( P5:3 );
P3 = 0;
P4 = 0;
P5 = 0;
( P5:3 ) = [ SP ++ ];
CHECKREG p1, 0x000000a1;
CHECKREG p2, 0x000000b2;
CHECKREG p3, 0x000000c3;
CHECKREG p4, 0x000000c4;
CHECKREG p5, 0x000000c5;
P4 = 0xd4 (X);
P5 = 0xd5 (X);
[ -- SP ] = ( P5:4 );
P4 = 0;
P5 = 0;
( P5:4 ) = [ SP ++ ];
CHECKREG p1, 0x000000a1;
CHECKREG p2, 0x000000b2;
CHECKREG p3, 0x000000c3;
CHECKREG p4, 0x000000d4;
CHECKREG p5, 0x000000d5;
P5 = 0xe5 (X);
[ -- SP ] = ( P5:5 );
P5 = 0;
( P5:5 ) = [ SP ++ ];
CHECKREG p1, 0x000000a1;
CHECKREG p2, 0x000000b2;
CHECKREG p3, 0x000000c3;
CHECKREG p4, 0x000000d4;
CHECKREG p5, 0x000000e5;
pass
|
stsp/binutils-ia16
| 4,247
|
sim/testsuite/bfin/c_multi_issue_dsp_ldst_1.s
|
//Original:/testcases/core/c_multi_issue_dsp_ldst_1/c_multi_issue_dsp_ldst_1.dsp
// Spec Reference: dsp32mac and 2 load/store
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
loadsym I0, DATA0;
loadsym I1, DATA1;
loadsym P1, DATA0;
loadsym P2, DATA1;
// test the default (signed fraction : left )
imm32 r0, 0x12345678;
imm32 r1, 0x33456789;
imm32 r2, 0x5556789a;
imm32 r3, 0x75678912;
imm32 r4, 0x86789123;
imm32 r5, 0xa7891234;
imm32 r6, 0xc1234567;
imm32 r7, 0xf1234567;
A1 = R0.L * R1.L, A0 = R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ];
A1 += R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ I0 ++ ] || R3 = [ I1 ++ ];
A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = [ P1 ++ ] || [ I1 ++ ] = R5;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x000A0000;
CHECKREG r1, 0x00F00100;
CHECKREG r2, 0x000B0001;
CHECKREG r3, 0x00E00101;
CHECKREG r4, 0x000A0000;
CHECKREG r5, 0xA7891234;
CHECKREG r6, 0x92793486;
CHECKREG r7, 0xDD2F9BAA;
imm32 r0, 0x12245618;
imm32 r1, 0x23256719;
imm32 r2, 0x3426781a;
imm32 r3, 0x45278912;
imm32 r4, 0x56289113;
imm32 r5, 0x67291214;
imm32 r6, 0xa1234517;
imm32 r7, 0xc1234517;
A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = [ P1 ++ ] || [ I0 ++ ] = R6;
A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ P2 ++ ] || [ I1 ++ ] = R3;
A1 += R4.H * R6.H, A0 -= R4.H * R6.L || [ P2 ++ ] = R5 || R7 = [ I1 ++ ];
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x12245618;
CHECKREG r1, 0x23256719;
CHECKREG r2, 0x00F00100;
CHECKREG r3, 0x45278912;
CHECKREG r4, 0x000B0001;
CHECKREG r5, 0x67291214;
CHECKREG r6, 0x8634CCA2;
CHECKREG r7, 0xB4E7420A;
imm32 r0, 0x15245648;
imm32 r1, 0x25256749;
imm32 r2, 0x3526784a;
imm32 r3, 0x45278942;
imm32 r4, 0x55389143;
imm32 r5, 0x65391244;
imm32 r6, 0xa5334547;
imm32 r7, 0xc5334547;
A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = [ P1 ++ ] || [ I1 -- ] = R3;
A1 += R2.H * R3.H, A0 += R2.L * R3.H || NOP || [ I0 ++ ] = R2;
A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = [ P2 -- ] || R6 = [ I0 -- ];
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x15245648;
CHECKREG r1, 0x25256749;
CHECKREG r2, 0xA1234517;
CHECKREG r3, 0xA7891234;
CHECKREG r4, 0x55389143;
CHECKREG r5, 0x65391244;
CHECKREG r6, 0xFD508A74;
CHECKREG r7, 0x0C2925C0;
imm32 r1, 0x02450789;
imm32 r2, 0x0356089a;
imm32 r3, 0x04670912;
imm32 r4, 0x05780123;
imm32 r5, 0x06890234;
imm32 r6, 0x07230567;
imm32 r7, 0x00230567;
R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R0 = [ I1 ++ ] || [ I0 -- ] = R2;
R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = [ P1 ] || [ I0 -- ] = R3;
R5 = R4 +|+ R2, R0 = R4 -|- R2 (CO) || NOP || [ I0 ++ ] = R5;
CHECKREG r0, 0xFA99FFDD;
CHECKREG r1, 0x0B8A0E79;
CHECKREG r2, 0x0AA32DD7;
CHECKREG r3, 0x04670912;
CHECKREG r4, 0x0A802870;
CHECKREG r5, 0x15235647;
CHECKREG r6, 0x0356089A;
CHECKREG r7, 0x00230567;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.dd 0x000f0005
.dd 0x00100006
.dd 0x00200007
.dd 0x00300008
.dd 0x00400009
.dd 0x0050000a
.dd 0x0060000b
.dd 0x0070000c
.dd 0x0080000d
.dd 0x0090000e
.dd 0x0100000f
.dd 0x02000010
.dd 0x03000011
.dd 0x04000012
.dd 0x05000013
.dd 0x06000014
.dd 0x001a0000
.dd 0x001b0001
.dd 0x001c0002
.dd 0x001d0003
.dd 0x00010004
.dd 0x00010005
.dd 0x02100006
.dd 0x02200007
.dd 0x02300008
.dd 0x02200009
.dd 0x0250000a
.dd 0x0260000b
.dd 0x0270000c
.dd 0x0280000d
.dd 0x0290000e
.dd 0x2100000f
.dd 0x22000010
.dd 0x22000011
.dd 0x24000012
.dd 0x25000013
.dd 0x26000014
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
.dd 0x00b00104
.dd 0x00a00105
.dd 0x00900106
.dd 0x00800107
.dd 0x00100108
.dd 0x00200109
.dd 0x0030010a
.dd 0x0040010b
.dd 0x0050011c
.dd 0x0060010d
.dd 0x0070010e
.dd 0x0080010f
.dd 0x00900110
.dd 0x01000111
.dd 0x02000112
.dd 0x03000113
.dd 0x04000114
.dd 0x05000115
.dd 0x03f00100
.dd 0x03e00101
.dd 0x03d00102
.dd 0x03c00103
.dd 0x03b00104
.dd 0x03a00105
.dd 0x03900106
.dd 0x03800107
.dd 0x03100108
.dd 0x03200109
.dd 0x0330010a
.dd 0x0330010b
.dd 0x0350011c
.dd 0x0360010d
.dd 0x0370010e
.dd 0x0380010f
.dd 0x03900110
.dd 0x31000111
.dd 0x32000112
.dd 0x33000113
.dd 0x34000114
|
stsp/binutils-ia16
| 4,130
|
sim/testsuite/bfin/c_alu2op_conv_b.s
|
//Original:/testcases/core/c_alu2op_conv_b/c_alu2op_conv_b.dsp
// Spec Reference: alu2op convert b
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = R0.B (Z);
R1 = R0.B (Z);
R2 = R0.B (Z);
R3 = R0.B (Z);
R4 = R0.B (Z);
R5 = R0.B (Z);
R6 = R0.B (Z);
R7 = R0.B (Z);
CHECKREG r0, 0x000000BC;
CHECKREG r1, 0x000000BC;
CHECKREG r2, 0x000000BC;
CHECKREG r3, 0x000000BC;
CHECKREG r4, 0x000000BC;
CHECKREG r5, 0x000000BC;
CHECKREG r6, 0x000000BC;
CHECKREG r7, 0x000000BC;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R0 = R1.B (Z);
R2 = R1.B (Z);
R3 = R1.B (Z);
R4 = R1.B (Z);
R5 = R1.B (Z);
R6 = R1.B (Z);
R7 = R1.B (Z);
R1 = R1.B (Z);
CHECKREG r0, 0x00000059;
CHECKREG r1, 0x00000059;
CHECKREG r2, 0x00000059;
CHECKREG r3, 0x00000059;
CHECKREG r4, 0x00000059;
CHECKREG r5, 0x00000059;
CHECKREG r6, 0x00000059;
CHECKREG r7, 0x00000059;
imm32 r0, 0x10789abc;
imm32 r1, 0x11345678;
imm32 r2, 0x93156789;
imm32 r3, 0xd451789a;
imm32 r4, 0x856719ab;
imm32 r5, 0x267891bc;
imm32 r6, 0xa789ab1d;
imm32 r7, 0x989ab1de;
R0 = R2.B (Z);
R1 = R2.B (Z);
R3 = R2.B (Z);
R4 = R2.B (Z);
R5 = R2.B (Z);
R6 = R2.B (Z);
R7 = R2.B (Z);
R2 = R2.B (Z);
CHECKREG r0, 0x00000089;
CHECKREG r1, 0x00000089;
CHECKREG r2, 0x00000089;
CHECKREG r3, 0x00000089;
CHECKREG r4, 0x00000089;
CHECKREG r5, 0x00000089;
CHECKREG r6, 0x00000089;
CHECKREG r7, 0x00000089;
imm32 r0, 0x21230002;
imm32 r1, 0x02374659;
imm32 r2, 0x93256789;
imm32 r3, 0xa952789a;
imm32 r4, 0xb59729ab;
imm32 r5, 0xc67992bc;
imm32 r6, 0xd7899b2d;
imm32 r7, 0xe89ab9d2;
R0 = R3.B (Z);
R1 = R3.B (Z);
R2 = R3.B (Z);
R4 = R3.B (Z);
R5 = R3.B (Z);
R6 = R3.B (Z);
R7 = R3.B (Z);
R3 = R3.B (Z);
CHECKREG r0, 0x0000009A;
CHECKREG r1, 0x0000009A;
CHECKREG r2, 0x0000009A;
CHECKREG r3, 0x0000009A;
CHECKREG r4, 0x0000009A;
CHECKREG r5, 0x0000009A;
CHECKREG r6, 0x0000009A;
CHECKREG r7, 0x0000009A;
imm32 r0, 0xa0789abc;
imm32 r1, 0x1a345678;
imm32 r2, 0x23a56789;
imm32 r3, 0x645a789a;
imm32 r4, 0x8667a9ab;
imm32 r5, 0x96689abc;
imm32 r6, 0xa787abad;
imm32 r7, 0xb89a7cda;
R0 = R4.B (Z);
R1 = R4.B (Z);
R2 = R4.B (Z);
R3 = R4.B (Z);
R4 = R4.B (Z);
R5 = R4.B (Z);
R6 = R4.B (Z);
R7 = R4.B (Z);
CHECKREG r0, 0x000000AB;
CHECKREG r1, 0x000000AB;
CHECKREG r2, 0x000000AB;
CHECKREG r3, 0x000000AB;
CHECKREG r4, 0x000000AB;
CHECKREG r5, 0x000000AB;
CHECKREG r6, 0x000000AB;
CHECKREG r7, 0x000000AB;
imm32 r0, 0xf1230002;
imm32 r1, 0x0f374659;
imm32 r2, 0x93f56789;
imm32 r3, 0xa45f789a;
imm32 r4, 0xb567f9ab;
imm32 r5, 0xc6789fbc;
imm32 r6, 0xd789abfd;
imm32 r7, 0xe89abcdf;
R0 = R5.B (Z);
R1 = R5.B (Z);
R2 = R5.B (Z);
R3 = R5.B (Z);
R4 = R5.B (Z);
R6 = R5.B (Z);
R7 = R5.B (Z);
R5 = R5.B (Z);
CHECKREG r0, 0x000000BC;
CHECKREG r1, 0x000000BC;
CHECKREG r2, 0x000000BC;
CHECKREG r3, 0x000000BC;
CHECKREG r4, 0x000000BC;
CHECKREG r5, 0x000000BC;
CHECKREG r6, 0x000000BC;
CHECKREG r7, 0x000000BC;
imm32 r0, 0xe0789abc;
imm32 r1, 0xe2345678;
imm32 r2, 0x2e456789;
imm32 r3, 0x34e6789a;
imm32 r4, 0x856e89ab;
imm32 r5, 0x9678eabc;
imm32 r6, 0xa789aecd;
imm32 r7, 0xb89abcee;
R0 = R6.B (Z);
R1 = R6.B (Z);
R2 = R6.B (Z);
R3 = R6.B (Z);
R4 = R6.B (Z);
R5 = R6.B (Z);
R7 = R6.B (Z);
R6 = R6.B (Z);
CHECKREG r0, 0x000000CD;
CHECKREG r1, 0x000000CD;
CHECKREG r2, 0x000000CD;
CHECKREG r3, 0x000000CD;
CHECKREG r4, 0x000000CD;
CHECKREG r5, 0x000000CD;
CHECKREG r6, 0x000000CD;
CHECKREG r7, 0x000000CD;
imm32 r0, 0x012300f5;
imm32 r1, 0x80374659;
imm32 r2, 0x98456589;
imm32 r3, 0xa486589a;
imm32 r4, 0xb56589ab;
imm32 r5, 0xc6588abc;
imm32 r6, 0xd589a8cd;
imm32 r7, 0x589abc88;
R0 = R7.B (Z);
R1 = R7.B (Z);
R2 = R7.B (Z);
R3 = R7.B (Z);
R4 = R7.B (Z);
R5 = R7.B (Z);
R6 = R7.B (Z);
R7 = R7.B (Z);
CHECKREG r0, 0x00000088;
CHECKREG r1, 0x00000088;
CHECKREG r2, 0x00000088;
CHECKREG r3, 0x00000088;
CHECKREG r4, 0x00000088;
CHECKREG r5, 0x00000088;
CHECKREG r6, 0x00000088;
CHECKREG r7, 0x00000088;
pass
|
stsp/binutils-ia16
| 2,901
|
sim/testsuite/bfin/c_dsp32mac_dr_a0_is.s
|
//Original:/testcases/core/c_dsp32mac_dr_a0_is/c_dsp32mac_dr_a0_is.dsp
// Spec Reference: dsp32mac dr a0 is (scale by 2.0 signed fraction with round)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xf3545abd;
imm32 r1, 0x7fbcfec7;
imm32 r2, 0xc7fff679;
imm32 r3, 0xd0799007;
imm32 r4, 0xefb79f69;
imm32 r5, 0xcd35700b;
imm32 r6, 0xe00c87fd;
imm32 r7, 0xf78e909f;
A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (ISS2);
R1 = A0.w;
A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (ISS2);
R3 = A0.w;
A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (ISS2);
R5 = A0.w;
A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (ISS2);
R7 = A0.w;
CHECKREG r0, 0xF3548000;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0xC7FF8000;
CHECKREG r3, 0xE71226F2;
CHECKREG r4, 0xEFB78000;
CHECKREG r5, 0xEA4D52D5;
CHECKREG r6, 0xE00C8000;
CHECKREG r7, 0xEE42DC2B;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0xc5548abd;
imm32 r1, 0x9b5cfec7;
imm32 r2, 0xa9b55679;
imm32 r3, 0xb09b5007;
imm32 r4, 0xcfb9b5c9;
imm32 r5, 0x52359b5c;
imm32 r6, 0xe50c5098;
imm32 r7, 0x675e7509;
R0.L = ( A0 -= R1.L * R0.L ) (ISS2);
R1 = A0.w;
R2.L = ( A0 += R2.L * R3.H ) (ISS2);
R3 = A0.w;
R4.L = ( A0 = R4.H * R5.L ) (ISS2);
R5 = A0.w;
R6.L = ( A0 -= R6.H * R7.H ) (ISS2);
R7 = A0.w;
CHECKREG r0, 0xC5548000;
CHECKREG r1, 0xEDB37D40;
CHECKREG r2, 0xA9B58000;
CHECKREG r3, 0xD2E20883;
CHECKREG r4, 0xCFB97FFF;
CHECKREG r5, 0x12FAA97C;
CHECKREG r6, 0xE50C7FFF;
CHECKREG r7, 0x1DDCBB14;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x4b54babd;
imm32 r1, 0x12346ec7;
imm32 r2, 0xa4bbe679;
imm32 r3, 0x8abdb707;
imm32 r4, 0x9f4b7b69;
imm32 r5, 0xa234877b;
imm32 r6, 0xb00c4887;
imm32 r7, 0xc78ea4b8;
R0.L = ( A0 = R1.L * R0.L ) (ISS2);
R1 = A0.w;
R2.L = ( A0 -= R2.H * R3.L ) (ISS2);
R3 = A0.w;
R4.L = ( A0 = R4.H * R5.H ) (ISS2);
R5 = A0.w;
R6.L = ( A0 += R6.L * R7.H ) (ISS2);
R7 = A0.w;
CHECKREG r0, 0x4B548000;
CHECKREG r1, 0xE2075EEB;
CHECKREG r2, 0xA4BB8000;
CHECKREG r3, 0xC80330CE;
CHECKREG r4, 0x9F4B7FFF;
CHECKREG r5, 0x236ED13C;
CHECKREG r6, 0xB00C7FFF;
CHECKREG r7, 0x1370FD1E;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x1a545abd;
imm32 r1, 0x42fcfec7;
imm32 r2, 0xc53f5679;
imm32 r3, 0x9c64f007;
imm32 r4, 0xafc7ec69;
imm32 r5, 0xd23c891b;
imm32 r6, 0xc00cc602;
imm32 r7, 0x678edc7e;
A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (ISS2);
R3 = A0.w;
A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (ISS2);
R7 = A0.w;
A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (ISS2);
R5 = A0.w;
A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (ISS2);
R1 = A0.w;
CHECKREG r0, 0x1A548000;
CHECKREG r1, 0xF0477293;
CHECKREG r2, 0xC53F7FFF;
CHECKREG r3, 0x13020C09;
CHECKREG r4, 0xAFC78000;
CHECKREG r5, 0xEEE57293;
CHECKREG r6, 0xC00C8000;
CHECKREG r7, 0xFD3CE337;
pass
|
stsp/binutils-ia16
| 4,815
|
sim/testsuite/bfin/c_dsp32mac_dr_a1_m.s
|
//Original:/testcases/core/c_dsp32mac_dr_a1_m/c_dsp32mac_dr_a1_m.dsp
// Spec Reference: dsp32mac dr a1 m
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246700f;
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
R0.H = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L;
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L;
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H;
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H;
R7 = A1.w;
CHECKREG r0, 0xFF225ABD;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0x00045679;
CHECKREG r3, 0x00040DAC;
CHECKREG r4, 0xFFFF4569;
CHECKREG r5, 0xFFFE9A28;
CHECKREG r6, 0x0008000D;
CHECKREG r7, 0x00084F78;
// The result accumulated in A1, and stored to a reg half (MNOP)
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
R0.H = ( A1 += R1.L * R0.L );
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H );
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L );
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H );
R7 = A1.w;
CHECKREG r0, 0xFF2A5ABD;
CHECKREG r1, 0xFF2A6D4E;
CHECKREG r2, 0x00045679;
CHECKREG r3, 0x00040DAC;
CHECKREG r4, 0x00034569;
CHECKREG r5, 0x0002A7D4;
CHECKREG r6, 0x000A000D;
CHECKREG r7, 0x0009B550;
// The result accumulated in A1 , and stored to a reg half (MNOP)
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
R0.H = A1 , A0 += R1.L * R0.L;
R1 = A1.w;
R2.H = A1 , A0 = R2.H * R3.L;
R3 = A1.w;
R4.H = A1 , A0 = R4.H * R5.H;
R5 = A1.w;
R6.H = A1 , A0 += R6.L * R7.H;
R7 = A1.w;
CHECKREG r0, 0x000A5ABD;
CHECKREG r1, 0x0009B550;
CHECKREG r2, 0x000A5679;
CHECKREG r3, 0x0009B550;
CHECKREG r4, 0x000A4569;
CHECKREG r5, 0x0009B550;
CHECKREG r6, 0x000A000D;
CHECKREG r7, 0x0009B550;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
R4.H = ( A1 += R1.L * R0.L ) (M), A0 = R1.L * R0.L;
R5 = A1.w;
R6.H = ( A1 = R2.L * R3.H ) (M), A0 += R2.H * R3.L;
R7 = A1.w;
R0.H = ( A1 = R4.H * R5.L ) (M), A0 = R4.H * R5.H;
R1 = A1.w;
R2.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H;
R3 = A1.w;
CHECKREG r0, 0xFFB35ABD;
CHECKREG r1, 0xFFB294B9;
CHECKREG r2, 0x00005679;
CHECKREG r3, 0x00000004;
CHECKREG r4, 0xFF9B4569;
CHECKREG r5, 0xFF9AC43B;
CHECKREG r6, 0x0002000D;
CHECKREG r7, 0x000206D6;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x83545abd;
imm32 r1, 0xa8bcfec7;
imm32 r2, 0xc1845679;
imm32 r3, 0x1c080007;
imm32 r4, 0xe1cc8569;
imm32 r5, 0x121c080b;
imm32 r6, 0x7001008d;
imm32 r7, 0x678e1008;
R6.H = ( A1 += R1.L * R0.L ) (M);
R7 = A1.w;
R2.H = ( A1 = R2.L * R3.H ) (M);
R3 = A1.w;
R0.H = ( A1 += R4.H * R5.L ) (M);
R1 = A1.w;
R4.H = ( A1 = R6.H * R7.H ) (M);
R5 = A1.w;
CHECKREG r0, 0x08855ABD;
CHECKREG r1, 0x0885038C;
CHECKREG r2, 0x09785679;
CHECKREG r3, 0x0977EFC8;
CHECKREG r4, 0xFF918569;
CHECKREG r5, 0xFF913021;
CHECKREG r6, 0xFF91008D;
CHECKREG r7, 0xFF910EEF;
imm32 r0, 0x03545abd;
imm32 r1, 0xa0bcfec7;
imm32 r2, 0xa1045679;
imm32 r3, 0x00000007;
imm32 r4, 0xefbc0569;
imm32 r5, 0x1235100b;
imm32 r6, 0x000c020d;
imm32 r7, 0x678e003f;
R4.H = ( A1 -= R1.L * R0.L ) (M), A0 -= R1.L * R0.L;
R5 = A1.w;
R6.H = ( A1 -= R2.L * R3.H ) (M), A0 += R2.H * R3.L;
R7 = A1.w;
R0.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H;
R1 = A1.w;
R2.H = ( A1 -= R6.H * R7.H ) (M), A0 -= R6.L * R7.H;
R3 = A1.w;
CHECKREG r0, 0x00005ABD;
CHECKREG r1, 0x00002136;
CHECKREG r2, 0x00005679;
CHECKREG r3, 0x00002136;
CHECKREG r4, 0x00000569;
CHECKREG r5, 0x00002136;
CHECKREG r6, 0x0000020D;
CHECKREG r7, 0x00002136;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x83545abd;
imm32 r1, 0xa8bcfec7;
imm32 r2, 0xc1845679;
imm32 r3, 0x1c080007;
imm32 r4, 0xe1cc8569;
imm32 r5, 0x121c080b;
imm32 r6, 0x7001008d;
imm32 r7, 0x678e1008;
R6.H = ( A1 -= R1.L * R0.L ) (M);
R7 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M);
R3 = A1.w;
R0.H = ( A1 -= R4.H * R5.L ) (M);
R1 = A1.w;
R4.H = ( A1 -= R6.H * R7.H ) (M);
R5 = A1.w;
CHECKREG r0, 0xF7EA5ABD;
CHECKREG r1, 0xF7EA0EBF;
CHECKREG r2, 0xF6F75679;
CHECKREG r3, 0xF6F72283;
CHECKREG r4, 0xF7EA8569;
CHECKREG r5, 0xF7E9DE9E;
CHECKREG r6, 0x006F008D;
CHECKREG r7, 0x006F124B;
pass
|
stsp/binutils-ia16
| 3,115
|
sim/testsuite/bfin/s9.s
|
// Test rl3 = ashift (rh0 by 7);
// Test rl3 = lshift (rh0 by 7);
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
R0 = 0;
ASTAT = R0;
R0.L = 0x1;
R0.H = 0x1;
R7.L = R0.L << 4;
DBGA ( R7.L , 0x0010 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R0.L = 0x8000;
R0.H = 0x1;
R7.L = R0.L >>> 4;
DBGA ( R7.L , 0xf800 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R0.L = 0x0;
R0.H = 0x1;
R7.L = R0.L << 0;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 0;
R0.L = 0x1;
R0.H = 0x8000;
R7.H = R0.H >>> 4;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0xf800 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 0;
R0.L = 0x1;
R0.H = 0x8000;
R7.L = R0.H >>> 4;
DBGA ( R7.L , 0xf800 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// logic shifts
R0 = 0;
ASTAT = R0;
R7 = 0;
R0.L = 0x1;
R0.H = 0x8000;
R7.L = R0.H >> 4;
DBGA ( R7.L , 0x0800 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 0;
R0.L = 0x1;
R0.H = 0x1;
R7.H = R0.L << 4;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0010 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 1;
R0.L = 0x0;
R0.H = 0x0;
R7.L = R0.L << 0;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 1;
R0.L = 0x1;
R0.H = 0x0;
R7.L = R0.L << 15;
DBGA ( R7.L , 0x8000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
pass
|
stsp/binutils-ia16
| 5,914
|
sim/testsuite/bfin/c_dsp32alu_rl_p.s
|
//Original:/testcases/core/c_dsp32alu_rl_p/c_dsp32alu_rl_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x19678911;
imm32 r1, 0x2799ab1d;
imm32 r2, 0x34945515;
imm32 r3, 0x46967717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86669977;
R0.L = R0.L + R0.L (NS);
R1.L = R0.L + R1.H (NS);
R2.L = R0.H + R2.L (NS);
R3.L = R0.H + R3.H (NS);
R4.L = R0.L + R4.L (NS);
R5.L = R0.L + R5.H (NS);
R6.L = R0.H + R6.L (NS);
R7.L = R0.H + R7.H (NS);
CHECKREG r4, 0x56789B3D;
CHECKREG r5, 0x678979AB;
CHECKREG r6, 0x74446E7C;
CHECKREG r7, 0x86669FCD;
CHECKREG r4, 0x56789B3D;
CHECKREG r5, 0x678979AB;
CHECKREG r6, 0x74446E7C;
CHECKREG r7, 0x86669FCD;
imm32 r0, 0x15678911;
imm32 r1, 0xaa89ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46a67717;
imm32 r4, 0x567a891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445a15;
imm32 r7, 0x866677a7;
R0.L = R1.L + R0.L (NS);
R1.L = R1.L + R1.H (NS);
R2.L = R1.H + R2.L (NS);
R3.L = R1.H + R3.H (NS);
R4.L = R1.L + R4.L (NS);
R5.L = R1.L + R5.H (NS);
R6.L = R1.H + R6.L (NS);
R7.L = R1.H + R7.H (NS);
CHECKREG r4, 0x567ADEC1;
CHECKREG r5, 0x6789BD2F;
CHECKREG r6, 0x7444049E;
CHECKREG r7, 0x866630EF;
CHECKREG r4, 0x567ADEC1;
CHECKREG r5, 0x6789BD2F;
CHECKREG r6, 0x7444049E;
CHECKREG r7, 0x866630EF;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.L = R2.L + R0.L (NS);
R1.L = R2.L + R1.H (NS);
R2.L = R2.H + R2.L (NS);
R3.L = R2.H + R3.H (NS);
R4.L = R2.L + R4.L (NS);
R5.L = R2.L + R5.H (NS);
R6.L = R2.H + R6.L (NS);
R7.L = R2.H + R7.H (NS);
CHECKREG r4, 0x56781274;
CHECKREG r5, 0x6789F0E2;
CHECKREG r6, 0x74448959;
CHECKREG r7, 0x8666BAAA;
CHECKREG r4, 0x56781274;
CHECKREG r5, 0x6789F0E2;
CHECKREG r6, 0x74448959;
CHECKREG r7, 0x8666BAAA;
imm32 r0, 0xb5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3bb45515;
imm32 r3, 0x46667717;
imm32 r4, 0x567b891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444b515;
imm32 r7, 0x86667b77;
R0.L = R3.L + R0.L (NS);
R1.L = R3.L + R1.H (NS);
R2.L = R3.H + R2.L (NS);
R3.L = R3.H + R3.H (NS);
R4.L = R3.L + R4.L (NS);
R5.L = R3.L + R5.H (NS);
R6.L = R3.H + R6.L (NS);
R7.L = R3.H + R7.H (NS);
CHECKREG r4, 0x567B15E7;
CHECKREG r5, 0x6789F455;
CHECKREG r6, 0x7444FB7B;
CHECKREG r7, 0x8666CCCC;
CHECKREG r4, 0x567B15E7;
CHECKREG r5, 0x6789F455;
CHECKREG r6, 0x7444FB7B;
CHECKREG r7, 0x8666CCCC;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.L = R4.L + R0.L (NS);
R1.L = R4.L + R1.H (NS);
R2.L = R4.H + R2.L (NS);
R3.L = R4.H + R3.H (NS);
R4.L = R4.L + R4.L (NS);
R5.L = R4.L + R5.H (NS);
R6.L = R4.H + R6.L (NS);
R7.L = R4.H + R7.H (NS);
CHECKREG r4, 0x56781236;
CHECKREG r5, 0x678979BF;
CHECKREG r6, 0x7444AB8D;
CHECKREG r7, 0x8666DCDE;
CHECKREG r4, 0x56781236;
CHECKREG r5, 0x678979BF;
CHECKREG r6, 0x7444AB8D;
CHECKREG r7, 0x8666DCDE;
imm32 r0, 0xcc678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3c445515;
imm32 r3, 0x46c67717;
imm32 r4, 0x567c891b;
imm32 r5, 0x6789cb1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667c77;
R0.L = R5.L + R0.L (NS);
R1.L = R5.L + R1.H (NS);
R2.L = R5.H + R2.L (NS);
R3.L = R5.H + R3.H (NS);
R4.L = R5.L + R4.L (NS);
R5.L = R5.L + R5.H (NS);
R6.L = R5.H + R6.L (NS);
R7.L = R5.H + R7.H (NS);
CHECKREG r4, 0x567C5438;
CHECKREG r5, 0x678932A6;
CHECKREG r6, 0x7444BC9E;
CHECKREG r7, 0x8666EDEF;
CHECKREG r4, 0x567C5438;
CHECKREG r5, 0x678932A6;
CHECKREG r6, 0x7444BC9E;
CHECKREG r7, 0x8666EDEF;
imm32 r0, 0xd5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46d67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x7444d515;
imm32 r7, 0x86667d77;
R0.L = R6.L + R0.L (NS);
R1.L = R6.L + R1.H (NS);
R2.L = R6.H + R2.L (NS);
R3.L = R6.H + R3.H (NS);
R4.L = R6.L + R4.L (NS);
R5.L = R6.L + R5.H (NS);
R6.L = R6.H + R6.L (NS);
R7.L = R6.H + R7.H (NS);
CHECKREG r4, 0x56785E30;
CHECKREG r5, 0x678D3CA2;
CHECKREG r6, 0x74444959;
CHECKREG r7, 0x8666FAAA;
CHECKREG r4, 0x56785E30;
CHECKREG r5, 0x678D3CA2;
CHECKREG r6, 0x74444959;
CHECKREG r7, 0x8666FAAA;
imm32 r0, 0xf5678911;
imm32 r1, 0x2f89ab1d;
imm32 r2, 0x34f45515;
imm32 r3, 0x466f7717;
imm32 r4, 0x5678f91b;
imm32 r5, 0x6789af1d;
imm32 r6, 0x744455f5;
imm32 r7, 0x8666777f;
R0.L = R7.L + R0.L (NS);
R1.L = R7.L + R1.H (NS);
R2.L = R7.H + R2.L (NS);
R3.L = R7.H + R3.H (NS);
R4.L = R7.L + R4.L (NS);
R5.L = R7.L + R5.H (NS);
R6.L = R7.H + R6.L (NS);
R7.L = R7.H + R7.H (NS);
CHECKREG r4, 0x5678709A;
CHECKREG r5, 0x6789DF08;
CHECKREG r6, 0x7444DC5B;
CHECKREG r7, 0x86660CCC;
CHECKREG r4, 0x5678709A;
CHECKREG r5, 0x6789DF08;
CHECKREG r6, 0x7444DC5B;
CHECKREG r7, 0x86660CCC;
imm32 r0, 0x55678911;
imm32 r1, 0x2589ab1d;
imm32 r2, 0x35545515;
imm32 r3, 0x46d67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x7444d515;
imm32 r7, 0x86667d77;
R6.L = R2.L + R3.L (S);
R1.L = R4.L + R5.H (S);
R5.L = R7.H + R2.L (S);
R3.L = R0.H + R0.H (S);
R0.L = R3.L + R4.L (S);
R2.L = R5.L + R7.H (S);
R7.L = R6.H + R7.L (S);
R4.L = R1.H + R6.H (S);
CHECKREG r4, 0x56787FFF;
CHECKREG r5, 0x678DDB7B;
CHECKREG r6, 0x74447FFF;
CHECKREG r7, 0x86667FFF;
CHECKREG r4, 0x56787FFF;
CHECKREG r5, 0x678DDB7B;
CHECKREG r6, 0x74447FFF;
CHECKREG r7, 0x86667FFF;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R3.L = R4.L + R0.L (S);
R1.L = R6.L + R3.H (S);
R4.L = R3.H + R2.L (S);
R6.L = R7.H + R1.H (S);
R2.L = R5.L + R4.L (S);
R7.L = R2.L + R7.H (S);
R0.L = R1.H + R6.L (S);
R5.L = R0.H + R5.H (S);
CHECKREG r4, 0x56787FFF;
CHECKREG r5, 0x67897CF0;
CHECKREG r6, 0x7444ADEF;
CHECKREG r7, 0x8666B182;
CHECKREG r4, 0x56787FFF;
CHECKREG r5, 0x67897CF0;
CHECKREG r6, 0x7444ADEF;
CHECKREG r7, 0x8666B182;
pass
|
stsp/binutils-ia16
| 3,795
|
sim/testsuite/bfin/c_ccflag_dr_imm3.s
|
//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3/c_ccflag_dr_imm3.dsp
// Spec Reference: ccflag dr-imm3
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x00000002;
imm32 r2, 0x00000003;
imm32 r3, 0x00000004;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
imm32 r7, 0x00000000;
ASTAT = R7;
R4 = ASTAT;
// positive dreg EQUAL to positive imm3
CC = R0 == 1;
R5 = ASTAT;
CC = R0 < 1;
R6 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00001025;
CHECKREG r6, 0x00001005;
CC = R0 <= 1;
R5 = ASTAT;
CC = R0 < 1;
R6 = ASTAT;
CC = R0 <= 1;
R7 = ASTAT;
CHECKREG r5, 0x00001025;
CHECKREG r6, 0x00001005;
CHECKREG r7, 0x00001025;
// positive dreg GREATER than to positive imm3
CC = R1 == 1;
R5 = ASTAT;
CC = R1 < 1;
R6 = ASTAT;
CC = R1 <= 1;
R7 = ASTAT;
CHECKREG r5, 0x00001004; // carry
CHECKREG r6, 0x00001004;
CHECKREG r7, 0x00001004;
// positive dreg LESS than to positive imm3
CC = R0 == 2;
R5 = ASTAT;
CC = R0 < 2;
R6 = ASTAT;
CC = R0 <= 2;
R7 = ASTAT;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
// positive dreg GREATER than to neg imm3
CC = R2 == -4;
R5 = ASTAT;
CC = R2 < -4;
R6 = ASTAT;
CC = R2 <= -4;
R7 = ASTAT;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, -1;
imm32 r1, -2;
imm32 r2, -3;
imm32 r3, -4;
// negative dreg and positive imm3
R7 = 0;
ASTAT = R7;
R4 = ASTAT;
CC = R3 == 1;
R5 = ASTAT;
CC = R3 < 1;
R6 = ASTAT;
CC = R3 <= 1;
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00001006;
CHECKREG r6, 0x00001026;
CHECKREG r7, 0x00001026;
// negative dreg LESS than neg imm3
CC = R2 == -1;
R4 = ASTAT;
CC = R2 < -1;
R5 = ASTAT;
CC = R2 <= -1;
R6 = ASTAT;
CHECKREG r4, 0x00000002;
CHECKREG r5, 0x00000022;
CHECKREG r6, 0x00000022;
// negative dreg GREATER neg imm3
CC = R0 == -4;
R4 = ASTAT;
CC = R0 < -4;
R5 = ASTAT;
CC = R0 <= -4;
R6 = ASTAT;
CHECKREG r4, 0x00001004;
CHECKREG r5, 0x00001004;
CHECKREG r6, 0x00001004;
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000001;
imm32 r5, 0x00000002;
imm32 r6, 0x00000003;
imm32 r7, 0x00000004;
ASTAT = R0;
R3 = ASTAT;
// positive dreg EQUAL to positive imm3
CC = R4 == 1;
R1 = ASTAT;
CC = R4 < 1;
R2 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00001025;
CHECKREG r2, 0x00001005;
CC = R4 <= 1;
R1 = ASTAT;
CC = R4 < 1;
R2 = ASTAT;
CC = R4 <= 1;
R3 = ASTAT;
CHECKREG r1, 0x00001025;
CHECKREG r2, 0x00001005;
CHECKREG r3, 0x00001025;
// positive dreg GREATER than to positive imm3
CC = R5 == 1;
R1 = ASTAT;
CC = R5 < 1;
R2 = ASTAT;
CC = R5 <= 1;
R3 = ASTAT;
CHECKREG r1, 0x00001004; // carry
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001004;
// positive dreg LESS than to positive imm3
CC = R6 == 2;
R1 = ASTAT;
CC = R6 < 2;
R2 = ASTAT;
CC = R6 <= 2;
R3 = ASTAT;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001004;
// positive dreg GREATER than to neg imm3
CC = R6 == -4;
R1 = ASTAT;
CC = R6 < -4;
R2 = ASTAT;
CC = R6 <= -4;
R3 = ASTAT;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
imm32 r4, -1;
imm32 r5, -2;
imm32 r6, -3;
imm32 r7, -4;
// negative dreg and positive imm3
R3 = 0;
ASTAT = R3;
R0 = ASTAT;
CC = R7 == 1;
R1 = ASTAT;
CC = R7 < 1;
R2 = ASTAT;
CC = R7 <= 1;
R3 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00001006;
CHECKREG r2, 0x00001026;
CHECKREG r3, 0x00001026;
// negative dreg LESS than neg imm3
CC = R6 == -1;
R0 = ASTAT;
CC = R6 < -1;
R1 = ASTAT;
CC = R6 <= -1;
R2 = ASTAT;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000022;
CHECKREG r2, 0x00000022;
// negative dreg GREATER neg imm3
CC = R4 == -4;
R0 = ASTAT;
CC = R4 < -4;
R1 = ASTAT;
CC = R4 <= -4;
R2 = ASTAT;
CHECKREG r0, 0x00001004;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
pass;
|
stsp/binutils-ia16
| 1,669
|
sim/testsuite/bfin/c_dsp32alu_search.s
|
//Original:/testcases/core/c_dsp32alu_search/c_dsp32alu_search.dsp
// Spec Reference: dsp32alu search
# mach: bfin
.include "testutils.inc"
start
imm32 p0, 0x11234556;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
( R0 , R1 ) = SEARCH R2 (GE);
( R2 , R3 ) = SEARCH R4 (GT);
( R4 , R5 ) = SEARCH R0 (LE);
( R7 , R6 ) = SEARCH R1 (LT);
CHECKREG r0, 0x11234556;
CHECKREG r1, 0x11234556;
CHECKREG r2, 0x11234556;
CHECKREG r3, 0x46667717;
CHECKREG r4, 0x11234556;
CHECKREG r5, 0x11234556;
CHECKREG r6, 0x74445515;
CHECKREG r7, 0x86667777;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r0, 0x456789ab;
imm32 r1, 0x6689abcd;
imm32 r2, 0x47445555;
imm32 r3, 0x68667777;
( R2 , R1 ) = SEARCH R3 (LE);
( R6 , R3 ) = SEARCH R5 (GT);
( R4 , R7 ) = SEARCH R2 (GE);
( R0 , R5 ) = SEARCH R4 (LT);
CHECKREG r0, 0x11234556;
CHECKREG r1, 0x6689ABCD;
CHECKREG r2, 0x47445555;
CHECKREG r3, 0x68667777;
CHECKREG r4, 0x11234556;
CHECKREG r5, 0x11234556;
CHECKREG r6, 0x74445515;
CHECKREG r7, 0x11234556;
imm32 r0, 0x516789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x73445555;
imm32 r3, 0x84667777;
imm32 r0, 0x956789ab;
imm32 r1, 0xa689abcd;
imm32 r2, 0xb7445555;
imm32 r3, 0xc86def77;
( R3 , R4 ) = SEARCH R5 (GT);
( R0 , R7 ) = SEARCH R6 (GE);
( R6 , R1 ) = SEARCH R2 (LT);
( R2 , R5 ) = SEARCH R4 (LE);
CHECKREG r0, 0x11234556;
CHECKREG r1, 0xA689ABCD;
CHECKREG r2, 0xB7445555;
CHECKREG r3, 0xC86DEF77;
CHECKREG r4, 0x11234556;
CHECKREG r5, 0x11234556;
CHECKREG r6, 0x11234556;
CHECKREG r7, 0x11234556;
pass
|
stsp/binutils-ia16
| 3,100
|
sim/testsuite/bfin/a5.s
|
// ALU test program.
// Test instructions
// rL4= L+L (r2,r3);
// rH4= L+H (r2,r3) S;
// rL4= L-L (r2,r3);
// rH4= L-H (r2,r3) S;
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// overflow positive
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0x7fff;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R3.L = R0.H + R1.L (NS);
DBGA ( R3.L , 0xfffe );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// overflow negative
R0.L = 0xffff;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x8000;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.H = R0.L + R1.H (NS);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0x7fff;
R1.H = 0x0000;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.L = R0.H + R1.L (S);
DBGA ( R3.L , 0x7fff );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate negative
R0.L = 0xffff;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x8000;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.L = R0.L + R1.H (S);
DBGA ( R3.L , 0x8000 );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// overflow positive with subtraction
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0xffff;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R3.L = R0.H - R1.L (NS);
DBGA ( R3.L , 0x8000 );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// overflow negative with subtraction
R0.L = 0x8000;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0001;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.H = R0.L - R1.H (NS);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive with subtraction
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0xffff;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R3.H = R0.H - R1.L (S);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate negative with subtraction
R0.L = 0x8000;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0001;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.H = R0.L - R1.H (S);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
pass
|
stsp/binutils-ia16
| 1,355
|
sim/testsuite/bfin/random_0021.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x5c604280 | _VS | _AV1S | _AV0S);
imm32 R3, 0xfe0103fe;
imm32 R5, 0x1e53cdd8;
R3.H = R5.L * R3.H (M, IU);
checkreg R3, 0x800003fe;
checkreg ASTAT, (0x5c604280 | _VS | _V | _AV1S | _AV0S | _V_COPY);
dmm32 ASTAT, (0x74a04c00 | _VS | _AV1S | _CC | _AN);
imm32 R4, 0xfffeffff;
imm32 R5, 0x174e174e;
R5.H = R4.L * R5.H (M, IU);
checkreg R5, 0xe8b2174e;
checkreg ASTAT, (0x74a04c00 | _VS | _AV1S | _CC | _AN);
dmm32 ASTAT, (0x34308890 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AN);
imm32 R3, 0x7fffffff;
imm32 R4, 0x077b8000;
imm32 R7, 0x03bd03bd;
R3.H = R4.L * R7.H (M, IU);
checkreg R3, 0x8000ffff;
checkreg ASTAT, (0x34308890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x58700a90 | _VS | _AV1S | _AC1 | _AQ | _CC | _AN);
imm32 R1, 0x58978212;
imm32 R3, 0x62b5775a;
imm32 R6, 0x4c9c9ee3;
R6.H = R1.L * R3.L (M, IU);
checkreg R6, 0x80009ee3;
checkreg ASTAT, (0x58700a90 | _VS | _V | _AV1S | _AC1 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x40204e00 | _VS | _AV1S | _AV0S | _CC | _AN);
imm32 R3, 0x297fee00;
imm32 R5, 0x79aa9d21;
imm32 R6, 0xfffe7484;
R6.H = R5.L * R3.L (M, IU);
checkreg R6, 0x80007484;
checkreg ASTAT, (0x40204e00 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN);
pass
|
stsp/binutils-ia16
| 11,635
|
sim/testsuite/bfin/se_popkill.S
|
//Original:/proj/frio/dv/testcases/seq/se_popkill/se_popkill.dsp
// Description: Kill pops to sysregs in WB
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_RST_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_RST_2 //
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef IMASK
#define IMASK 0xFFE02104
#endif
#ifndef DMEM_CONTROL
#define DMEM_CONTROL 0xFFE00004
#endif
#ifndef DCPLB_ADDR0
#define DCPLB_ADDR0 0xFFE00100
#endif
#ifndef DCPLB_DATA0
#define DCPLB_DATA0 0xFFE00200
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
/////////////////////////////////////////////////////////////////////////////
//////////////////////// CPLB Setup /////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Setup CPLB for Data Memory starting at 0x00F0_0000;
WR_MMR(DCPLB_DATA0, DATA_ADDR_1, p0, r0);
//WR_MMR(DCPLB_DATA0, 0x00031005, p0, r0); // Page Size = 4MB
// CPLB_L1_CHLB = 1
// CPLB_USER_RD = 1
// CPLB_VALID = 1
//
// Setup CPLB Address to point to 0x00F0_0000
WR_MMR(DCPLB_ADDR0, DATA_ADDR_2, p0, r0);
//WR_MMR(DCPLB_ADDR0, 0x00F00000, p0, r0);
// Enable CPLB's
WR_MMR(DMEM_CONTROL, DATA_ADDR_3, p0, r0);
//WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1
// ENDCPLB = 1
// DMC = 11
// Sync it!
CSYNC;
// Return to Supervisor Code
RAISE 15;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
R3 = SEQSTAT;
R4 = RETX;
R4 += 8;
RETX = R4;
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
NOP;
ASTAT = R7;
RETS = R7;
LC0 = R7;
LB0 = R7;
LT0 = R7;
LC1 = R7;
LB1 = R7;
LT1 = R7;
CYCLES = R7;
CYCLES2 = R7;
SYSCFG = R7;
RETN = R7;
RETX = R7;
RETE = R7;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
EXCPT 1;
ASTAT = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 2;
RETS = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 3;
LC0 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 4;
LT0 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 5;
LB0 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 6;
LC1 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 7;
LB1 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 8;
LT1 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 9;
CYCLES = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 10;
CYCLES2 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 11;
SYSCFG = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 12;
RETI = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 13;
RETX = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 14;
RETN = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 15;
RETE = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Define Kernal Stack
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.space (STACKSIZE);
KSTACK :
.space (STACKSIZE);
USTACK :
.section MEM_DATA_ADDR_2 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 9,384
|
sim/testsuite/bfin/se_rts_rti.S
|
//Original:/proj/frio/dv/testcases/seq/se_rts_rti/se_rts_rti.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Load RETS
LD32_LABEL(r0, USER_CODE);
RETS = R0;
// Return to Supervisor Code
RAISE 2;
RAISE 5;
RAISE 6;
RAISE 7;
RAISE 8;
RAISE 9;
RAISE 10;
RAISE 11;
RAISE 12;
RAISE 13;
RAISE 14;
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
RTI;
NOP;
NOP;
RTS;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
EXCPT 0x5;
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 7,522
|
sim/testsuite/bfin/c_seq_ex2_mmrj_mvpop.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmrj_mvpop/c_seq_ex2_mmrj_mvpop.dsp
// Spec Reference: sequencer stage ex2 ( mmr + jump + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
LD32(p2, DATA_ADDR_1);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
LD32(r2, 0x14789232);
[ P1 ] = R2;
CSYNC;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
[ -- SP ] = ( R7:0 );
// RAISE 2; // RTN
[ P1 ] = R0;
JUMP.S LABEL1;
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
// RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
// wrt-rd EVT5 = 0xFFE02034
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
// RAISE 6; // RTI
R0 = [ P1 ];
JUMP.S LABEL2;
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
CHECKREG(r0, 0x00000001);
// RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000003);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
// wrt-rd EVT13 = 0xFFE02034
LD32(p1, 0xFFE02034);
// RAISE 8; // RTI
R0 = [ P1 ];
JUMP.S LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
CHECKREG(r0, 0x00000001);
// RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 10,005
|
sim/testsuite/bfin/c_ldstii_st_preg.s
|
//Original:/testcases/core/c_ldstii_st_preg/c_ldstii_st_preg.dsp
// Spec Reference: c_ldstii store preg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
P4 = 0x4567 (X);
P5 = 0x79ab (X);
FP = 0x6def (X);
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
[ P1 + 8 ] = P4;
[ P1 + 12 ] = P5;
[ P2 + 20 ] = P4;
[ P2 + 24 ] = P5;
[ P2 + 32 ] = FP;
R5 = [ P1 + 8 ];
R4 = [ P1 + 12 ];
R2 = [ P2 + 20 ];
R7 = [ P2 + 24 ];
R1 = [ P2 + 32 ];
CHECKREG r1, 0x00006DEF;
CHECKREG r2, 0x00004567;
CHECKREG r4, 0x000079AB;
CHECKREG r5, 0x00004567;
CHECKREG r7, 0x000079AB;
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
P1 = 0x3456 (X);
P2 = 0x1234 (X);
P5 = 0x5e23 (X);
FP = 0x2ac5 (X);
loadsym p4, DATA_ADDR_4;
[ P4 + 52 ] = P2;
[ P4 + 56 ] = P5;
[ P4 + 64 ] = FP;
R2 = [ P4 + 52 ];
R5 = [ P4 + 56 ];
R7 = [ P4 + 64 ];
CHECKREG r2, 0x00001234;
CHECKREG r5, 0x00005E23;
CHECKREG r7, 0x00002AC5;
// initial values
imm32 r0, 0x10cf50c0;
imm32 r1, 0x20ce60c1;
imm32 r2, 0x30c370c2;
imm32 r3, 0x40cc80c3;
imm32 r4, 0x50cb90c4;
imm32 r5, 0x60caa0c5;
imm32 r6, 0x70c9b0c6;
imm32 r7, 0xd0c8c0c7;
P1 = 0x2125 (X);
P2 = 0x7345 (X);
P4 = 0x5789 (X);
FP = 0x5bcd (X);
loadsym p5, DATA_ADDR_1;
[ P5 + 4 ] = P2;
[ P5 + 8 ] = P1;
[ P5 + 12 ] = P2;
R6 = [ P5 + 4 ];
R5 = [ P5 + 8 ];
R4 = [ P5 + 12 ];
CHECKREG r4, 0x00007345;
CHECKREG r5, 0x00002125;
CHECKREG r6, 0x00007345;
// initial values
imm32 r0, 0x60df50d0;
imm32 r1, 0x70de60d1;
imm32 r2, 0x80dd70d2;
imm32 r3, 0x90dc80d3;
imm32 r4, 0xa0db90d4;
imm32 r5, 0xb0daa0d5;
imm32 r6, 0xc0d9b0d6;
imm32 r7, 0xd0d8c0d7;
P1 = 0x5bcd (X);
P2 = 0x1122 (X);
P4 = 0x6677 (X);
P5 = 0x58ab (X);
loadsym fp, DATA_ADDR_2;
[ FP + 36 ] = P4;
[ FP + 40 ] = P1;
[ FP + 44 ] = P2;
[ FP + 52 ] = P4;
[ FP + 56 ] = P5;
[ FP + 64 ] = P2;
R3 = [ FP + 36 ];
R4 = [ FP + 40 ];
R0 = [ FP + 44 ];
R2 = [ FP + 52 ];
R5 = [ FP + 56 ];
R7 = [ FP + 64 ];
CHECKREG r0, 0x00001122;
CHECKREG r2, 0x00006677;
CHECKREG r3, 0x00006677;
CHECKREG r4, 0x00005BCD;
CHECKREG r5, 0x000058AB;
CHECKREG r7, 0x00001122;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 7,996
|
sim/testsuite/bfin/c_comp3op_dr_minus_dr.s
|
//Original:/testcases/core/c_comp3op_dr_minus_dr/c_comp3op_dr_minus_dr.dsp
// Spec Reference: comp3op dregs - dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 r7, 0x12345678;
R0 = R0 - R0;
R1 = R0 - R1;
R2 = R0 - R2;
R3 = R0 - R3;
R4 = R0 - R4;
R5 = R0 - R5;
R6 = R0 - R6;
R7 = R0 - R7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x76543211;
CHECKREG r2, 0xA9876544;
CHECKREG r3, 0x210FEDCC;
CHECKREG r4, 0xDCBA9767;
CHECKREG r5, 0x876EDCBB;
CHECKREG r6, 0x6789ABCE;
CHECKREG r7, 0xEDCBA988;
imm32 r0, 0x01231567;
imm32 r1, 0x89ab1def;
imm32 r2, 0x56781abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23451899;
imm32 r5, 0x78911345;
imm32 r6, 0x98761432;
imm32 r7, 0x12341678;
R0 = R1 - R0;
R1 = R1 - R1;
R2 = R1 - R2;
R3 = R1 - R3;
R4 = R1 - R4;
R5 = R1 - R5;
R6 = R1 - R6;
R7 = R1 - R7;
CHECKREG r0, 0x88880888;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xA987E544;
CHECKREG r3, 0x210FEDCC;
CHECKREG r4, 0xDCBAE767;
CHECKREG r5, 0x876EECBB;
CHECKREG r6, 0x6789EBCE;
CHECKREG r7, 0xEDCBE988;
imm32 r0, 0x01234527;
imm32 r1, 0x89abcd2f;
imm32 r2, 0x56789a2c;
imm32 r3, 0xdef01224;
imm32 r4, 0x23456829;
imm32 r5, 0x78912325;
imm32 r6, 0x98765422;
imm32 r7, 0x12345628;
R0 = R2 - R0;
R1 = R2 - R1;
R2 = R2 - R2;
R3 = R2 - R3;
R4 = R2 - R4;
R5 = R2 - R5;
R6 = R2 - R6;
R7 = R2 - R7;
CHECKREG r0, 0x55555505;
CHECKREG r1, 0xCCCCCCFD;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x210FEDDC;
CHECKREG r4, 0xDCBA97D7;
CHECKREG r5, 0x876EDCDB;
CHECKREG r6, 0x6789ABDE;
CHECKREG r7, 0xEDCBA9D8;
imm32 r0, 0x01234563;
imm32 r1, 0x89abcde3;
imm32 r2, 0x56789ab3;
imm32 r3, 0xdef01233;
imm32 r4, 0x23456893;
imm32 r5, 0x78912343;
imm32 r6, 0x98765433;
imm32 r7, 0x12345673;
R0 = R3 - R0;
R1 = R3 - R1;
R2 = R3 - R2;
R3 = R3 - R3;
R4 = R3 - R4;
R5 = R3 - R5;
R6 = R3 - R6;
R7 = R3 - R7;
CHECKREG r0, 0xDDCCCCD0;
CHECKREG r1, 0x55444450;
CHECKREG r2, 0x88777780;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xDCBA976D;
CHECKREG r5, 0x876EDCBD;
CHECKREG r6, 0x6789ABCD;
CHECKREG r7, 0xEDCBA98D;
imm32 r0, 0x41234567;
imm32 r1, 0x49abcdef;
imm32 r2, 0x46789abc;
imm32 r3, 0x4ef01234;
imm32 r4, 0x43456899;
imm32 r5, 0x48912345;
imm32 r6, 0x48765432;
imm32 r7, 0x42345678;
R0 = R4 - R0;
R1 = R4 - R1;
R2 = R4 - R2;
R3 = R4 - R3;
R4 = R4 - R4;
R5 = R4 - R5;
R6 = R4 - R6;
R7 = R4 - R7;
CHECKREG r0, 0x02222332;
CHECKREG r1, 0xF9999AAA;
CHECKREG r2, 0xFCCCCDDD;
CHECKREG r3, 0xF4555665;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0xB76EDCBB;
CHECKREG r6, 0xB789ABCE;
CHECKREG r7, 0xBDCBA988;
imm32 r0, 0x05234567;
imm32 r1, 0x85abcdef;
imm32 r2, 0x55789abc;
imm32 r3, 0xd5f01234;
imm32 r4, 0x25456899;
imm32 r5, 0x75912345;
imm32 r6, 0x95765432;
imm32 r7, 0x15345678;
R0 = R5 - R0;
R1 = R5 - R1;
R2 = R5 - R2;
R3 = R5 - R3;
R4 = R5 - R4;
R5 = R5 - R5;
R6 = R5 - R6;
R7 = R5 - R7;
CHECKREG r0, 0x706DDDDE;
CHECKREG r1, 0xEFE55556;
CHECKREG r2, 0x20188889;
CHECKREG r3, 0x9FA11111;
CHECKREG r4, 0x504BBAAC;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x6A89ABCE;
CHECKREG r7, 0xEACBA988;
imm32 r0, 0x01264567;
imm32 r1, 0x89a6cdef;
imm32 r2, 0x56769abc;
imm32 r3, 0xdef61234;
imm32 r4, 0x23466899;
imm32 r5, 0x78962345;
imm32 r6, 0x98765432;
imm32 r7, 0x12365678;
R0 = R6 - R0;
R1 = R6 - R1;
R2 = R6 - R2;
R3 = R6 - R3;
R4 = R6 - R4;
R5 = R6 - R5;
R6 = R6 - R6;
R7 = R6 - R7;
CHECKREG r0, 0x97500ECB;
CHECKREG r1, 0x0ECF8643;
CHECKREG r2, 0x41FFB976;
CHECKREG r3, 0xB98041FE;
CHECKREG r4, 0x752FEB99;
CHECKREG r5, 0x1FE030ED;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xEDC9A988;
imm32 r0, 0x01237567;
imm32 r1, 0x89ab7def;
imm32 r2, 0x56787abc;
imm32 r3, 0xdef07234;
imm32 r4, 0x23457899;
imm32 r5, 0x78917345;
imm32 r6, 0x98767432;
imm32 r7, 0x12345678;
R0 = R7 - R0;
R1 = R7 - R1;
R2 = R7 - R2;
R3 = R7 - R3;
R4 = R7 - R4;
R5 = R7 - R5;
R6 = R7 - R6;
R7 = R7 - R7;
CHECKREG r0, 0x1110E111;
CHECKREG r1, 0x8888D889;
CHECKREG r2, 0xBBBBDBBC;
CHECKREG r3, 0x3343E444;
CHECKREG r4, 0xEEEEDDDF;
CHECKREG r5, 0x99A2E333;
CHECKREG r6, 0x79BDE246;
CHECKREG r7, 0x00000000;
imm32 r0, 0x11234567;
imm32 r1, 0x81abcdef;
imm32 r2, 0x56189abc;
imm32 r3, 0xdef11234;
imm32 r4, 0x23451899;
imm32 r5, 0x78912145;
imm32 r6, 0x98765412;
imm32 r7, 0x12345671;
R0 = R1 - R0;
R1 = R2 - R0;
R2 = R3 - R0;
R3 = R4 - R0;
R4 = R5 - R0;
R5 = R6 - R0;
R6 = R7 - R0;
R7 = R0 - R0;
CHECKREG r0, 0x70888888;
CHECKREG r1, 0xE5901234;
CHECKREG r2, 0x6E6889AC;
CHECKREG r3, 0xB2BC9011;
CHECKREG r4, 0x080898BD;
CHECKREG r5, 0x27EDCB8A;
CHECKREG r6, 0xA1ABCDE9;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01231567;
imm32 r1, 0x29ab1def;
imm32 r2, 0x52781abc;
imm32 r3, 0xde201234;
imm32 r4, 0x23421899;
imm32 r5, 0x78912345;
imm32 r6, 0x98761232;
imm32 r7, 0x12341628;
R0 = R2 - R1;
R1 = R3 - R1;
R2 = R4 - R1;
R3 = R5 - R1;
R4 = R6 - R1;
R5 = R7 - R1;
R6 = R0 - R1;
R7 = R1 - R1;
CHECKREG r0, 0x28CCFCCD;
CHECKREG r1, 0xB474F445;
CHECKREG r2, 0x6ECD2454;
CHECKREG r3, 0xC41C2F00;
CHECKREG r4, 0xE4011DED;
CHECKREG r5, 0x5DBF21E3;
CHECKREG r6, 0x74580888;
CHECKREG r7, 0x00000000;
imm32 r0, 0x03234527;
imm32 r1, 0x893bcd2f;
imm32 r2, 0x56739a2c;
imm32 r3, 0x3ef03224;
imm32 r4, 0x23456329;
imm32 r5, 0x78312335;
imm32 r6, 0x98735423;
imm32 r7, 0x12343628;
R0 = R4 - R2;
R1 = R5 - R2;
R2 = R6 - R2;
R3 = R7 - R2;
R4 = R0 - R2;
R5 = R1 - R2;
R6 = R2 - R2;
R7 = R3 - R2;
CHECKREG r0, 0xCCD1C8FD;
CHECKREG r1, 0x21BD8909;
CHECKREG r2, 0x41FFB9F7;
CHECKREG r3, 0xD0347C31;
CHECKREG r4, 0x8AD20F06;
CHECKREG r5, 0xDFBDCF12;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x8E34C23A;
imm32 r0, 0x04234563;
imm32 r1, 0x894bcde3;
imm32 r2, 0x56749ab3;
imm32 r3, 0x4ef04233;
imm32 r4, 0x24456493;
imm32 r5, 0x78412344;
imm32 r6, 0x98745434;
imm32 r7, 0x12344673;
R0 = R5 - R3;
R1 = R6 - R3;
R2 = R7 - R3;
R3 = R0 - R3;
R4 = R1 - R3;
R5 = R2 - R3;
R6 = R3 - R3;
R7 = R4 - R3;
CHECKREG r0, 0x2950E111;
CHECKREG r1, 0x49841201;
CHECKREG r2, 0xC3440440;
CHECKREG r3, 0xDA609EDE;
CHECKREG r4, 0x6F237323;
CHECKREG r5, 0xE8E36562;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x94C2D445;
imm32 r0, 0x41235567;
imm32 r1, 0x49abc5ef;
imm32 r2, 0x46789a5c;
imm32 r3, 0x4ef01235;
imm32 r4, 0x53456899;
imm32 r5, 0x45912345;
imm32 r6, 0x48565432;
imm32 r7, 0x42355678;
R0 = R6 - R4;
R1 = R7 - R4;
R2 = R0 - R4;
R3 = R1 - R4;
R4 = R2 - R4;
R5 = R3 - R4;
R6 = R4 - R4;
R7 = R5 - R4;
CHECKREG r0, 0xF510EB99;
CHECKREG r1, 0xEEEFEDDF;
CHECKREG r2, 0xA1CB8300;
CHECKREG r3, 0x9BAA8546;
CHECKREG r4, 0x4E861A67;
CHECKREG r5, 0x4D246ADF;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xFE9E5078;
imm32 r0, 0x05264567;
imm32 r1, 0x85ab6def;
imm32 r2, 0x657896bc;
imm32 r3, 0xd6f01264;
imm32 r4, 0x25656896;
imm32 r5, 0x75962345;
imm32 r6, 0x95766432;
imm32 r7, 0x15345678;
R0 = R7 - R5;
R1 = R0 - R5;
R2 = R1 - R5;
R3 = R2 - R5;
R4 = R3 - R5;
R5 = R4 - R5;
R6 = R5 - R5;
R7 = R6 - R5;
CHECKREG r0, 0x9F9E3333;
CHECKREG r1, 0x2A080FEE;
CHECKREG r2, 0xB471ECA9;
CHECKREG r3, 0x3EDBC964;
CHECKREG r4, 0xC945A61F;
CHECKREG r5, 0x53AF82DA;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xAC507D26;
imm32 r0, 0x01764567;
imm32 r1, 0x89a7cdef;
imm32 r2, 0x56767abc;
imm32 r3, 0xdef61734;
imm32 r4, 0x73466879;
imm32 r5, 0x77962347;
imm32 r6, 0x98765432;
imm32 r7, 0x12375678;
R0 = R7 - R6;
R1 = R0 - R6;
R2 = R1 - R6;
R3 = R2 - R6;
R4 = R3 - R6;
R5 = R4 - R6;
R6 = R5 - R6;
R7 = R6 - R6;
CHECKREG r0, 0x79C10246;
CHECKREG r1, 0xE14AAE14;
CHECKREG r2, 0x48D459E2;
CHECKREG r3, 0xB05E05B0;
CHECKREG r4, 0x17E7B17E;
CHECKREG r5, 0x7F715D4C;
CHECKREG r6, 0xE6FB091A;
CHECKREG r7, 0x00000000;
imm32 r0, 0x81238567;
imm32 r1, 0x88ab78ef;
imm32 r2, 0x56887a8c;
imm32 r3, 0x8ef87238;
imm32 r4, 0x28458899;
imm32 r5, 0x78817845;
imm32 r6, 0x98787482;
imm32 r7, 0x12348678;
R0 = R1 - R7;
R1 = R2 - R7;
R2 = R3 - R7;
R3 = R4 - R7;
R4 = R5 - R7;
R5 = R6 - R7;
R6 = R7 - R7;
R7 = R0 - R7;
CHECKREG r0, 0x7676F277;
CHECKREG r1, 0x4453F414;
CHECKREG r2, 0x7CC3EBC0;
CHECKREG r3, 0x16110221;
CHECKREG r4, 0x664CF1CD;
CHECKREG r5, 0x8643EE0A;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x64426BFF;
pass
|
stsp/binutils-ia16
| 6,135
|
sim/testsuite/bfin/c_dsp32alu_rl_rnd12_m.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_m/c_dsp32alu_rl_rnd12_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x85678911;
imm32 r1, 0x9189ab1d;
imm32 r2, 0xa4245515;
imm32 r3, 0xb6637717;
imm32 r4, 0xc678491b;
imm32 r5, 0x6789a51d;
imm32 r6, 0xe4445565;
imm32 r7, 0x86667777;
R0.L = R0 - R0 (RND12);
R1.L = R0 - R1 (RND12);
R2.L = R0 - R2 (RND12);
R3.L = R0 - R3 (RND12);
R4.L = R0 - R4 (RND12);
R5.L = R0 - R5 (RND12);
R6.L = R0 - R6 (RND12);
R7.L = R0 - R7 (RND12);
CHECKREG r0, 0x85670000;
CHECKREG r1, 0x91898000;
CHECKREG r2, 0xA4248000;
CHECKREG r3, 0xB6638000;
CHECKREG r4, 0xC6788000;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0xE4448000;
CHECKREG r7, 0x8666F009;
imm32 r0, 0x75678921;
imm32 r1, 0x2789ab14;
imm32 r2, 0xd4745515;
imm32 r3, 0x4d677767;
imm32 r4, 0x56d8791b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86a6d777;
R0.L = R1 - R0 (RND12);
R1.L = R1 - R1 (RND12);
R2.L = R1 - R2 (RND12);
R3.L = R1 - R3 (RND12);
R4.L = R1 - R4 (RND12);
R5.L = R1 - R5 (RND12);
R6.L = R1 - R6 (RND12);
R7.L = R1 - R7 (RND12);
CHECKREG r0, 0x75678000;
CHECKREG r1, 0x27890000;
CHECKREG r2, 0xD4747FFF;
CHECKREG r3, 0x4D678000;
CHECKREG r4, 0x56D88000;
CHECKREG r5, 0x678D8000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86A67fff;
imm32 r0, 0x55678911;
imm32 r1, 0x2689ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46967717;
imm32 r4, 0xa67a891b;
imm32 r5, 0x6789bb1d;
imm32 r6, 0x7444d515;
imm32 r7, 0x8666c777;
R0.L = R2 - R0 (RND12);
R1.L = R2 - R1 (RND12);
R2.L = R2 - R2 (RND12);
R3.L = R2 - R3 (RND12);
R4.L = R2 - R4 (RND12);
R5.L = R2 - R5 (RND12);
R6.L = R2 - R6 (RND12);
R7.L = R2 - R7 (RND12);
CHECKREG r0, 0x55678000;
CHECKREG r1, 0x26897fff;
CHECKREG r2, 0x3D440000;
CHECKREG r3, 0x46968000;
CHECKREG r4, 0xA67A7fff;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86667fff;
imm32 r0, 0xf5678911;
imm32 r1, 0xd789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0xe6667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6d89ab1d;
imm32 r6, 0x7444d515;
imm32 r7, 0xe6667b77;
R0.L = R3 - R0 (RND12);
R1.L = R3 - R1 (RND12);
R2.L = R3 - R2 (RND12);
R3.L = R3 - R3 (RND12);
R4.L = R3 - R4 (RND12);
R5.L = R3 - R5 (RND12);
R6.L = R3 - R6 (RND12);
R7.L = R3 - R7 (RND12);
CHECKREG r0, 0xF5678000;
CHECKREG r1, 0xD7897fff;
CHECKREG r2, 0x34448000;
CHECKREG r3, 0xE6660000;
CHECKREG r4, 0x56788000;
CHECKREG r5, 0x6D898000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0xE666FFF8;
imm32 r0, 0xa5678911;
imm32 r1, 0x2b89ab1d;
imm32 r2, 0x34c45515;
imm32 r3, 0x46d67717;
imm32 r4, 0x56e8891b;
imm32 r5, 0x67f9ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86687777;
R0.L = R4 - R0 (RND12);
R1.L = R4 - R1 (RND12);
R2.L = R4 - R2 (RND12);
R3.L = R4 - R3 (RND12);
R4.L = R4 - R4 (RND12);
R5.L = R4 - R5 (RND12);
R6.L = R4 - R6 (RND12);
R7.L = R4 - R7 (RND12);
CHECKREG r0, 0xa5677fff;
CHECKREG r1, 0x2b897fff;
CHECKREG r2, 0x34c47fff;
CHECKREG r3, 0x46d67fff;
CHECKREG r4, 0x56E80000;
CHECKREG r5, 0x67F98000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86687fff;
imm32 r0, 0xe5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0xd6667717;
imm32 r4, 0x5ff8891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x744e5515;
imm32 r7, 0x8666a7b7;
R0.L = R5 - R0 (RND12);
R1.L = R5 - R1 (RND12);
R2.L = R5 - R2 (RND12);
R3.L = R5 - R3 (RND12);
R4.L = R5 - R4 (RND12);
R5.L = R5 - R5 (RND12);
R6.L = R5 - R6 (RND12);
R7.L = R5 - R7 (RND12);
CHECKREG r0, 0xE5677fff;
CHECKREG r1, 0x27897fff;
CHECKREG r2, 0x34447fff;
CHECKREG r3, 0xD6667fff;
CHECKREG r4, 0x5FF87912;
CHECKREG r5, 0x67890000;
CHECKREG r6, 0x744E8000;
CHECKREG r7, 0x86667fff;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ae1d;
imm32 r2, 0x344455e5;
imm32 r3, 0x4666771d;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789abdd;
imm32 r6, 0x74a45515;
imm32 r7, 0x866c77b7;
R0.L = R6 - R0 (RND12);
R1.L = R6 - R1 (RND12);
R2.L = R6 - R2 (RND12);
R3.L = R6 - R3 (RND12);
R4.L = R6 - R4 (RND12);
R5.L = R6 - R5 (RND12);
R6.L = R6 - R6 (RND12);
R7.L = R6 - R7 (RND12);
CHECKREG r0, 0x15677fff;
CHECKREG r1, 0x27897fff;
CHECKREG r2, 0x34447fff;
CHECKREG r3, 0x46667fff;
CHECKREG r4, 0x56787fff;
CHECKREG r5, 0x67897fff;
CHECKREG r6, 0x74A40000;
CHECKREG r7, 0x866C7fff;
imm32 r0, 0x25678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46567717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x7444b515;
imm32 r7, 0xb666a777;
R0.L = R7 - R0 (RND12);
R1.L = R7 - R1 (RND12);
R2.L = R7 - R2 (RND12);
R3.L = R7 - R3 (RND12);
R4.L = R7 - R4 (RND12);
R5.L = R7 - R5 (RND12);
R6.L = R7 - R6 (RND12);
R7.L = R7 - R7 (RND12);
CHECKREG r0, 0x25678000;
CHECKREG r1, 0x23898000;
CHECKREG r2, 0x34448000;
CHECKREG r3, 0x46568000;
CHECKREG r4, 0x56788000;
CHECKREG r5, 0x678D8000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0xB6660000;
imm32 r0, 0xaa678911;
imm32 r1, 0x27ddab1d;
imm32 r2, 0x344bb515;
imm32 r3, 0x46667717;
imm32 r4, 0x56dd891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444bb15;
imm32 r7, 0x86ff7777;
R6.L = R2 - R3 (RND12);
R1.L = R4 - R5 (RND12);
R5.L = R7 - R2 (RND12);
R3.L = R0 - R0 (RND12);
R0.L = R3 - R4 (RND12);
R2.L = R5 - R7 (RND12);
R7.L = R6 - R7 (RND12);
R4.L = R1 - R6 (RND12);
CHECKREG r0, 0xAA678000;
CHECKREG r1, 0x27DD8000;
CHECKREG r2, 0x344B7fff;
CHECKREG r3, 0x46660000;
CHECKREG r4, 0x56DD8000;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86FF7fff;
imm32 r0, 0x95678911;
imm32 r1, 0x2d89ab1d;
imm32 r2, 0x34b45515;
imm32 r3, 0x46c67717;
imm32 r4, 0x567e891b;
imm32 r5, 0x678fab1d;
imm32 r6, 0x744e5515;
imm32 r7, 0x8b66a777;
R3.L = R4 - R0 (RND12);
R1.L = R6 - R3 (RND12);
R4.L = R3 - R2 (RND12);
R6.L = R7 - R1 (RND12);
R2.L = R5 - R4 (RND12);
R7.L = R2 - R7 (RND12);
R0.L = R1 - R6 (RND12);
R5.L = R0 - R5 (RND12);
CHECKREG r0, 0x95678000;
CHECKREG r1, 0x2D897fff;
CHECKREG r2, 0x34B47fff;
CHECKREG r3, 0x46C67fff;
CHECKREG r4, 0x567E7fff;
CHECKREG r5, 0x678F8000;
CHECKREG r6, 0x744E8000;
CHECKREG r7, 0x8B667FFF;
pass
|
stsp/binutils-ia16
| 4,760
|
sim/testsuite/bfin/c_dsp32shift_fdepx.s
|
//Original:/testcases/core/c_dsp32shift_fdepx/c_dsp32shift_fdepx.dsp
// Spec Reference: dsp32shift fdep x
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0x08000807;
R1 = DEPOSIT( R1, R0 );
R2 = DEPOSIT( R2, R0 );
R3 = DEPOSIT( R3, R0 );
R4 = DEPOSIT( R4, R0 ) (X);
R5 = DEPOSIT( R5, R0 );
R6 = DEPOSIT( R6, R0 );
R7 = DEPOSIT( R7, R0 ) (X);
R0 = DEPOSIT( R0, R0 );
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x01000800;
CHECKREG r2, 0x08200802;
CHECKREG r3, 0x08030802;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x08000504;
CHECKREG r6, 0x08000866;
CHECKREG r7, 0x00000000;
imm32 r0, 0x0900d001;
imm32 r1, 0x09000002;
imm32 r2, 0x09000002;
imm32 r3, 0x09100003;
imm32 r4, 0x09020004;
imm32 r5, 0x09003005;
imm32 r6, 0x09000406;
imm32 r7, 0x09000057;
R0 = DEPOSIT( R0, R1 );
R2 = DEPOSIT( R2, R1 );
R3 = DEPOSIT( R3, R1 );
R4 = DEPOSIT( R4, R1 );
R5 = DEPOSIT( R5, R1 ) (X);
R6 = DEPOSIT( R6, R1 );
R7 = DEPOSIT( R7, R1 ) (X);
R1 = DEPOSIT( R1, R1 );
CHECKREG r0, 0x0900D000;
CHECKREG r1, 0x09000000;
CHECKREG r2, 0x09000000;
CHECKREG r3, 0x09100000;
CHECKREG r4, 0x09020004;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x09000404;
CHECKREG r7, 0x00000000;
imm32 r0, 0x0a00e001;
imm32 r1, 0x0a00e001;
imm32 r2, 0x0a00000f;
imm32 r3, 0x0a000010;
imm32 r4, 0x0a00e004;
imm32 r5, 0x0a00e005;
imm32 r6, 0x0a00e006;
imm32 r7, 0x0a00e007;
R0 = DEPOSIT( R0, R2 );
R1 = DEPOSIT( R1, R2 );
R3 = DEPOSIT( R3, R2 );
R4 = DEPOSIT( R4, R2 );
R5 = DEPOSIT( R5, R2 );
R6 = DEPOSIT( R6, R2 );
R7 = DEPOSIT( R7, R2 );
R2 = DEPOSIT( R2, R2 );
CHECKREG r0, 0x0A008A00;
CHECKREG r1, 0x0A008A00;
CHECKREG r2, 0x0A000A00;
CHECKREG r3, 0x0A000A00;
CHECKREG r4, 0x0A008A00;
CHECKREG r5, 0x0A008A00;
CHECKREG r6, 0x0A008A00;
CHECKREG r7, 0x0A008A00;
imm32 r0, 0x4b00f001;
imm32 r1, 0x5b00f001;
imm32 r2, 0x6b00f002;
imm32 r3, 0x9f000010;
imm32 r4, 0x8b00f004;
imm32 r5, 0x0900f005;
imm32 r6, 0x0b00f006;
imm32 r7, 0x0b0af007;
R0 = DEPOSIT( R0, R3 );
R1 = DEPOSIT( R1, R3 );
R2 = DEPOSIT( R2, R3 ) (X);
R4 = DEPOSIT( R4, R3 );
R5 = DEPOSIT( R5, R3 );
R6 = DEPOSIT( R6, R3 ) (X);
R7 = DEPOSIT( R7, R3 );
R3 = DEPOSIT( R3, R3 );
CHECKREG r0, 0x4B009F00;
CHECKREG r1, 0x5B009F00;
CHECKREG r2, 0xFFFF9F00;
CHECKREG r3, 0x9F009F00;
CHECKREG r4, 0x8B009F00;
CHECKREG r5, 0x09009F00;
CHECKREG r6, 0xFFFF9F00;
CHECKREG r7, 0x0B0A9F00;
imm32 r0, 0x0c0000c0;
imm32 r1, 0x0c0100c0;
imm32 r2, 0x0c0200c0;
imm32 r3, 0x0c0300c0;
imm32 r4, 0x0c04000c;
imm32 r5, 0x0c0500c0;
imm32 r6, 0x0c0600c0;
imm32 r7, 0x0c0700c0;
R0 = DEPOSIT( R0, R4 );
R1 = DEPOSIT( R1, R4 );
R2 = DEPOSIT( R2, R4 );
R3 = DEPOSIT( R3, R4 );
R5 = DEPOSIT( R5, R4 ) (X);
R6 = DEPOSIT( R6, R4 );
R7 = DEPOSIT( R7, R4 );
R4 = DEPOSIT( R4, R4 );
CHECKREG r0, 0x0C000C04;
CHECKREG r1, 0x0C010C04;
CHECKREG r2, 0x0C020C04;
CHECKREG r3, 0x0C030C04;
CHECKREG r4, 0x0C040C04;
CHECKREG r5, 0xFFFFFC04;
CHECKREG r6, 0x0C060C04;
CHECKREG r7, 0x0C070C04;
imm32 r0, 0xa00100d0;
imm32 r1, 0xa00100d1;
imm32 r2, 0xa00200d0;
imm32 r3, 0xa00300d0;
imm32 r4, 0xa00400d0;
imm32 r5, 0xa0050007;
imm32 r6, 0xa00600d0;
imm32 r7, 0xa00700d0;
R5 = DEPOSIT( R0, R5 );
R6 = DEPOSIT( R1, R5 ) (X);
R7 = DEPOSIT( R2, R5 );
R0 = DEPOSIT( R3, R5 );
R1 = DEPOSIT( R4, R5 ) (X);
R2 = DEPOSIT( R6, R5 );
R3 = DEPOSIT( R7, R5 );
R4 = DEPOSIT( R5, R5 );
CHECKREG r0, 0xA00300C1;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0xA00200C1;
CHECKREG r4, 0xA0010081;
CHECKREG r5, 0xA0010085;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0xA00200C1;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0x00237809;
imm32 r7, 0xb0070000;
R0 = DEPOSIT( R0, R6 );
R1 = DEPOSIT( R1, R6 );
R2 = DEPOSIT( R2, R6 );
R3 = DEPOSIT( R3, R6 ) (X);
R4 = DEPOSIT( R4, R6 );
R5 = DEPOSIT( R5, R6 );
R6 = DEPOSIT( R6, R6 );
R7 = DEPOSIT( R7, R6 );
CHECKREG r0, 0x23010000;
CHECKREG r1, 0x23010000;
CHECKREG r2, 0x2302000F;
CHECKREG r3, 0x23030000;
CHECKREG r4, 0x23040000;
CHECKREG r5, 0x23050000;
CHECKREG r6, 0x23237809;
CHECKREG r7, 0x23070000;
imm32 r0, 0xd00100e0;
imm32 r1, 0xd00100e0;
imm32 r2, 0xd00200e0;
imm32 r3, 0xd00300e0;
imm32 r4, 0xd00400e0;
imm32 r5, 0xd00500e0;
imm32 r6, 0xd00600e0;
imm32 r7, 0x00012345;
R1 = DEPOSIT( R0, R7 );
R2 = DEPOSIT( R1, R7 );
R3 = DEPOSIT( R2, R7 );
R4 = DEPOSIT( R3, R7 );
R5 = DEPOSIT( R4, R7 ) (X);
R6 = DEPOSIT( R5, R7 );
R7 = DEPOSIT( R6, R7 ) (X);
R0 = DEPOSIT( R7, R7 );
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xD0010008;
CHECKREG r2, 0xD0010008;
CHECKREG r3, 0xD0010008;
CHECKREG r4, 0xD0010008;
CHECKREG r5, 0x00000008;
CHECKREG r6, 0x00000008;
CHECKREG r7, 0x00000008;
pass
|
stsp/binutils-ia16
| 5,915
|
sim/testsuite/bfin/c_ldst_ld_d_p_xh.s
|
//Original:/testcases/core/c_ldst_ld_d_p_xh/c_ldst_ld_d_p_xh.dsp
// Spec Reference: c_ldst ld d [p] xh
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
// load 16 bits from memory and sign extend into 32-bit reg
R4 = W [ P5 ] (X);
R5 = W [ FP ] (X);
R7 = W [ P1 ] (X);
R0 = W [ P2 ] (X);
.ifndef BFIN_HOST
R1 = W [ P3 ] (X);
.else
imm32 r1, 0x00004243;
.endif
R2 = W [ P4 ] (X);
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00004243;
CHECKREG r2, 0x00006263;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xFFFF8283;
CHECKREG r5, 0x00000203;
CHECKREG r7, 0x00000203;
R5 = W [ FP ] (X);
R7 = W [ P1 ] (X);
R0 = W [ P2 ] (X);
.ifndef BFIN_HOST
R1 = W [ P3 ] (X);
.else
imm32 R1, 0x00004243;
.endif
R2 = W [ P4 ] (X);
R3 = W [ P5 ] (X);
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00004243;
CHECKREG r2, 0x00006263;
CHECKREG r3, 0xFFFF8283;
CHECKREG r4, 0xFFFF8283;
CHECKREG r5, 0x00000203;
CHECKREG r7, 0x00000203;
R7 = W [ P1 ] (X);
R0 = W [ P2 ] (X);
.ifndef BFIN_HOST
R1 = W [ P3 ] (X);
.else
imm32 R1, 0x00004243;
.endif
R2 = W [ P4 ] (X);
R3 = W [ P5 ] (X);
R4 = W [ FP ] (X);
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00004243;
CHECKREG r2, 0x00006263;
CHECKREG r3, 0xFFFF8283;
CHECKREG r4, 0x00000203;
CHECKREG r5, 0x00000203;
CHECKREG r7, 0x00000203;
R7 = W [ P1 ] (X);
R0 = W [ P2 ] (X);
.ifndef BFIN_HOST
R1 = W [ P3 ] (X);
.else
imm32 R1, 0x00004243;
.endif
R2 = W [ P4 ] (X);
R3 = W [ P5 ] (X);
R4 = W [ FP ] (X);
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00004243;
CHECKREG r2, 0x00006263;
CHECKREG r3, 0xFFFF8283;
CHECKREG r4, 0x00000203;
CHECKREG r7, 0x00000203;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 9,932
|
sim/testsuite/bfin/c_dsp32shift_ahalf_rn.s
|
//Original:/testcases/core/c_dsp32shift_ahalf_rn/c_dsp32shift_ahalf_rn.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=right (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
//rl0 = ashift (rl0 by rl0);
R1.L = ASHIFT R1.L BY R0.L;
R2.L = ASHIFT R2.L BY R0.L;
R3.L = ASHIFT R3.L BY R0.L;
R4.L = ASHIFT R4.L BY R0.L;
R5.L = ASHIFT R5.L BY R0.L;
R6.L = ASHIFT R6.L BY R0.L;
R7.L = ASHIFT R7.L BY R0.L;
//CHECKREG r0, 0x00000000;
CHECKREG r1, 0x0000c000;
CHECKREG r2, 0x0000c001;
CHECKREG r3, 0x0000c001;
CHECKREG r4, 0x0000c002;
CHECKREG r5, 0x0000c002;
CHECKREG r6, 0x0000c003;
CHECKREG r7, 0x0000c003;
imm32 r0, 0x00008001;
R1.L = -1;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R1.L;
//rl1 = ashift (rl1 by rl1);
R2.L = ASHIFT R2.L BY R1.L;
R3.L = ASHIFT R3.L BY R1.L;
R4.L = ASHIFT R4.L BY R1.L;
R5.L = ASHIFT R5.L BY R1.L;
R6.L = ASHIFT R6.L BY R1.L;
R7.L = ASHIFT R7.L BY R1.L;
CHECKREG r0, 0x0000c000;
//CHECKREG r1, 0x00000001;
CHECKREG r2, 0x0000c001;
CHECKREG r3, 0x0000c001;
CHECKREG r4, 0x0000c002;
CHECKREG r5, 0x0000c002;
CHECKREG r6, 0x0000c003;
CHECKREG r7, 0x0000c003;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
R2.L = -15;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R2.L;
R1.L = ASHIFT R1.L BY R2.L;
//rl2 = ashift (rl2 by rl2);
R3.L = ASHIFT R3.L BY R2.L;
R4.L = ASHIFT R4.L BY R2.L;
R5.L = ASHIFT R5.L BY R2.L;
R6.L = ASHIFT R6.L BY R2.L;
R7.L = ASHIFT R7.L BY R2.L;
CHECKREG r0, 0x0000ffff;
CHECKREG r1, 0x0000ffff;
//CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x0000ffff;
CHECKREG r4, 0x0000ffff;
CHECKREG r5, 0x0000ffff;
CHECKREG r6, 0x0000ffff;
CHECKREG r7, 0x0000ffff;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
R3.L = -16;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R3.L;
R1.L = ASHIFT R1.L BY R3.L;
R2.L = ASHIFT R2.L BY R3.L;
//rl3 = ashift (rl3 by rl3);
R4.L = ASHIFT R4.L BY R3.L;
R5.L = ASHIFT R5.L BY R3.L;
R6.L = ASHIFT R6.L BY R3.L;
R7.L = ASHIFT R7.L BY R3.L;
CHECKREG r0, 0x0000ffff;
CHECKREG r1, 0x0000ffff;
CHECKREG r2, 0x0000ffff;
//CHECKREG r3, 0x00000010;
CHECKREG r4, 0x0000ffff;
CHECKREG r5, 0x0000ffff;
CHECKREG r6, 0x0000ffff;
CHECKREG r7, 0x0000ffff;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.L = ASHIFT R0.H BY R0.L;
R1.L = ASHIFT R1.H BY R0.L;
R2.L = ASHIFT R2.H BY R0.L;
R3.L = ASHIFT R3.H BY R0.L;
R4.L = ASHIFT R4.H BY R0.L;
R5.L = ASHIFT R5.H BY R0.L;
R6.L = ASHIFT R6.H BY R0.L;
R7.L = ASHIFT R7.H BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x80018001;
CHECKREG r2, 0x80028002;
CHECKREG r3, 0x80038003;
CHECKREG r4, 0x80048004;
CHECKREG r5, 0x80058005;
CHECKREG r6, 0x80068006;
CHECKREG r7, 0x80078007;
imm32 r0, 0x80010000;
R1.L = -1;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.L = ASHIFT R0.H BY R1.L;
//rl1 = ashift (rh1 by rl1);
R2.L = ASHIFT R2.H BY R1.L;
R3.L = ASHIFT R3.H BY R1.L;
R4.L = ASHIFT R4.H BY R1.L;
R5.L = ASHIFT R5.H BY R1.L;
R6.L = ASHIFT R6.H BY R1.L;
R7.L = ASHIFT R7.H BY R1.L;
CHECKREG r0, 0x8001c000;
//CHECKREG r1, 0x00010001;
CHECKREG r2, 0x8002c001;
CHECKREG r3, 0x8003c001;
CHECKREG r4, 0x8004c002;
CHECKREG r5, 0x8005c002;
CHECKREG r6, 0x8006c003;
CHECKREG r7, 0x8007c003;
imm32 r0, 0xa0010000;
imm32 r1, 0xa0010000;
R2.L = -15;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.L = ASHIFT R0.H BY R2.L;
R1.L = ASHIFT R1.H BY R2.L;
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L;
R4.L = ASHIFT R4.H BY R2.L;
R5.L = ASHIFT R5.H BY R2.L;
R6.L = ASHIFT R6.H BY R2.L;
R7.L = ASHIFT R7.H BY R2.L;
CHECKREG r0, 0xa001ffff;
CHECKREG r1, 0xa001ffff;
//CHECKREG r2, 0x2002000f;
CHECKREG r3, 0xa003ffff;
CHECKREG r4, 0xa004ffff;
CHECKREG r5, 0xa005ffff;
CHECKREG r6, 0xa006ffff;
CHECKREG r7, 0xa007ffff;
imm32 r0, 0xb0010001;
imm32 r1, 0xb0010001;
imm32 r2, 0xb0020002;
R3.L = -16;
imm32 r4, 0xb0040004;
imm32 r5, 0xb0050005;
imm32 r6, 0xb0060006;
imm32 r7, 0xb0070007;
R0.L = ASHIFT R0.H BY R3.L;
R1.L = ASHIFT R1.H BY R3.L;
R2.L = ASHIFT R2.H BY R3.L;
//rl3 = ashift (rh3 by rl3);
R4.L = ASHIFT R4.H BY R3.L;
R5.L = ASHIFT R5.H BY R3.L;
R6.L = ASHIFT R6.H BY R3.L;
R7.L = ASHIFT R7.H BY R3.L;
CHECKREG r0, 0xb001ffff;
CHECKREG r1, 0xb001ffff;
CHECKREG r2, 0xb002ffff;
//CHECKREG r3, 0x30030010;
CHECKREG r4, 0xb004ffff;
CHECKREG r5, 0xb005ffff;
CHECKREG r6, 0xb006ffff;
CHECKREG r7, 0xb007ffff;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000000;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R4.L;
R1.H = ASHIFT R1.L BY R4.L;
R2.H = ASHIFT R2.L BY R4.L;
R3.H = ASHIFT R3.L BY R4.L;
//rh4 = ashift (rl4 by rl4);
R5.H = ASHIFT R5.L BY R4.L;
R6.H = ASHIFT R6.L BY R4.L;
R7.H = ASHIFT R7.L BY R4.L;
CHECKREG r0, 0x00010001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
//CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
R5.L = -1;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.H = ASHIFT R0.L BY R5.L;
R1.H = ASHIFT R1.L BY R5.L;
R2.H = ASHIFT R2.L BY R5.L;
R3.H = ASHIFT R3.L BY R5.L;
R4.H = ASHIFT R4.L BY R5.L;
//rh5 = ashift (rl5 by rl5);
R6.H = ASHIFT R6.L BY R5.L;
R7.H = ASHIFT R7.L BY R5.L;
CHECKREG r0, 0xc0008001;
CHECKREG r1, 0xc0008001;
CHECKREG r2, 0xc0018002;
CHECKREG r3, 0xc0018003;
CHECKREG r4, 0xc0028004;
//CHECKREG r5, 0x00020005;
CHECKREG r6, 0xc0038006;
CHECKREG r7, 0xc0038007;
imm32 r0, 0x00009001;
imm32 r1, 0x00009001;
imm32 r2, 0x00009002;
imm32 r3, 0x00009003;
imm32 r4, 0x00009004;
imm32 r5, 0x00009005;
R6.L = -15;
imm32 r7, 0x00009007;
R0.H = ASHIFT R0.L BY R6.L;
R1.H = ASHIFT R1.L BY R6.L;
R2.H = ASHIFT R2.L BY R6.L;
R3.H = ASHIFT R3.L BY R6.L;
R4.H = ASHIFT R4.L BY R6.L;
R5.H = ASHIFT R5.L BY R6.L;
//rh6 = ashift (rl6 by rl6);
R7.H = ASHIFT R7.L BY R6.L;
CHECKREG r0, 0xffff9001;
CHECKREG r1, 0xffff9001;
CHECKREG r2, 0xffff9002;
CHECKREG r3, 0xffff9003;
CHECKREG r4, 0xffff9004;
CHECKREG r5, 0xffff9005;
//CHECKREG r6, 0x00006006;
CHECKREG r7, 0xffff9007;
imm32 r0, 0x0000a001;
imm32 r1, 0x0000a001;
imm32 r2, 0x0000a002;
imm32 r3, 0x0000a003;
imm32 r4, 0x0000a004;
imm32 r5, 0x0000a005;
imm32 r6, 0x0000a006;
R7.L = -16;
R0.H = ASHIFT R0.L BY R7.L;
R1.H = ASHIFT R1.L BY R7.L;
R2.H = ASHIFT R2.L BY R7.L;
R3.H = ASHIFT R3.L BY R7.L;
R4.H = ASHIFT R4.L BY R7.L;
R5.H = ASHIFT R5.L BY R7.L;
R6.H = ASHIFT R6.L BY R7.L;
R7.H = ASHIFT R7.L BY R7.L;
CHECKREG r0, 0xffffa001;
CHECKREG r1, 0xffffa001;
CHECKREG r2, 0xffffa002;
CHECKREG r3, 0xffffa003;
CHECKREG r4, 0xffffa004;
CHECKREG r5, 0xffffa005;
CHECKREG r6, 0xffffa006;
//CHECKREG r7, 0x00007007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x80010000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
R4.L = -1;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.H = ASHIFT R0.H BY R4.L;
R1.H = ASHIFT R1.H BY R4.L;
R2.H = ASHIFT R2.H BY R4.L;
R3.H = ASHIFT R3.H BY R4.L;
//rh4 = ashift (rh4 by rl4);
R5.H = ASHIFT R5.H BY R4.L;
R6.H = ASHIFT R6.H BY R4.L;
R7.H = ASHIFT R7.H BY R4.L;
CHECKREG r0, 0xc0000000;
CHECKREG r1, 0xc0000000;
CHECKREG r2, 0xc0010000;
CHECKREG r3, 0xc0010000;
//CHECKREG r4, 0x00020000;
CHECKREG r5, 0xc0020000;
CHECKREG r6, 0xc0030000;
CHECKREG r7, 0xc0030000;
imm32 r0, 0x80010000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
R5.L = -1;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.H = ASHIFT R0.H BY R5.L;
R1.H = ASHIFT R1.H BY R5.L;
R2.H = ASHIFT R2.H BY R5.L;
R3.H = ASHIFT R3.H BY R5.L;
R4.H = ASHIFT R4.H BY R5.L;
//rh5 = ashift (rh5 by rl5);
R6.H = ASHIFT R6.H BY R5.L;
R7.H = ASHIFT R7.H BY R5.L;
CHECKREG r0, 0xc0000000;
CHECKREG r1, 0xc0000000;
CHECKREG r2, 0xc0010000;
CHECKREG r3, 0xc0010000;
CHECKREG r4, 0xc0020000;
//CHECKREG r5, 0x28020000;
CHECKREG r6, 0xc0030000;
CHECKREG r7, 0xc0030000;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030000;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
R6.L = -15;
imm32 r7, 0xd0070000;
R0.L = ASHIFT R0.H BY R6.L;
R1.L = ASHIFT R1.H BY R6.L;
R2.L = ASHIFT R2.H BY R6.L;
R3.L = ASHIFT R3.H BY R6.L;
R4.L = ASHIFT R4.H BY R6.L;
R5.L = ASHIFT R5.H BY R6.L;
//rl6 = ashift (rh6 by rl6);
R7.L = ASHIFT R7.H BY R6.L;
CHECKREG r0, 0xd001ffff;
CHECKREG r1, 0xd001ffff;
CHECKREG r2, 0xd002ffff;
CHECKREG r3, 0xd003ffff;
CHECKREG r4, 0xd004ffff;
CHECKREG r5, 0xd005ffff;
//CHECKREG r6, 0x60060000;
CHECKREG r7, 0xd007ffff;
imm32 r0, 0xe0010000;
imm32 r1, 0xe0010000;
imm32 r2, 0xe0020000;
imm32 r3, 0xe0030000;
imm32 r4, 0xe0040000;
imm32 r5, 0xe0050000;
imm32 r6, 0xe0060000;
R7.L = -16;
R0.H = ASHIFT R0.H BY R7.L;
R1.H = ASHIFT R1.H BY R7.L;
R2.H = ASHIFT R2.H BY R7.L;
R3.H = ASHIFT R3.H BY R7.L;
R4.H = ASHIFT R4.H BY R7.L;
R5.H = ASHIFT R5.H BY R7.L;
R6.H = ASHIFT R6.H BY R7.L;
//rh7 = ashift (rh7 by rl7);
CHECKREG r0, 0xffff0000;
CHECKREG r1, 0xffff0000;
CHECKREG r2, 0xffff0000;
CHECKREG r3, 0xffff0000;
CHECKREG r4, 0xffff0000;
CHECKREG r5, 0xffff0000;
CHECKREG r6, 0xffff0000;
//CHECKREG r7, -16;
pass
|
stsp/binutils-ia16
| 6,681
|
sim/testsuite/bfin/c_dsp32mac_dr_a1_t.s
|
//Original:/testcases/core/c_dsp32mac_dr_a1_t/c_dsp32mac_dr_a1_t.dsp
// Spec Reference: dsp32mac dr a1 t (truncation)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd0069007;
imm32 r4, 0xefbc4569;
imm32 r5, 0xcd35500b;
imm32 r6, 0xe00c800d;
imm32 r7, 0xf78e900f;
R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (T);
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (T);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (T);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (T);
R7 = A1.w;
CHECKREG r0, 0xFF225ABD;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0x2D8C8679;
CHECKREG r3, 0x2D8CEDAC;
CHECKREG r4, 0xF5D44569;
CHECKREG r5, 0xF5D41A28;
CHECKREG r6, 0x021B800D;
CHECKREG r7, 0x021BB550;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x63548abd;
imm32 r1, 0x7dbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0xb0069007;
imm32 r4, 0xcfbc4569;
imm32 r5, 0xd235c00b;
imm32 r6, 0xe00ca00d;
imm32 r7, 0x678e700f;
R0.H = ( A1 = R1.L * R0.L ) (T);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (T);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ) (T);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (T);
R7 = A1.w;
CHECKREG r0, 0x011E8ABD;
CHECKREG r1, 0x011EBDD6;
CHECKREG r2, 0xCB175679;
CHECKREG r3, 0xCB172B82;
CHECKREG r4, 0x181D4569;
CHECKREG r5, 0x181DDA28;
CHECKREG r6, 0xE626A00D;
CHECKREG r7, 0xE6263550;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x5354babd;
imm32 r1, 0x6dbcdec7;
imm32 r2, 0x7124e679;
imm32 r3, 0x80067007;
imm32 r4, 0x9fbc4569;
imm32 r5, 0xa235900b;
imm32 r6, 0xb00c300d;
imm32 r7, 0xc78ea00f;
R0.H = A1 , A0 = R1.L * R0.L (T);
R1 = A1.w;
R2.H = A1 , A0 = R2.H * R3.L (T);
R3 = A1.w;
R4.H = A1 , A0 = R4.H * R5.H (T);
R5 = A1.w;
R6.H = A1 , A0 += R6.L * R7.H (T);
R7 = A1.w;
CHECKREG r0, 0xE626BABD;
CHECKREG r1, 0xE6263550;
CHECKREG r2, 0xE626E679;
CHECKREG r3, 0xE6263550;
CHECKREG r4, 0xE6264569;
CHECKREG r5, 0xE6263550;
CHECKREG r6, 0xE626300D;
CHECKREG r7, 0xE6263550;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71245679;
imm32 r3, 0x90060007;
imm32 r4, 0xafbc4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00ca00d;
imm32 r7, 0x678ed00f;
R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (T);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (T);
R3 = A0.w;
R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (T);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (T);
R7 = A0.w;
CHECKREG r0, 0xFF915ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x30375679;
CHECKREG r3, 0x00062FF8;
CHECKREG r4, 0x030D4569;
CHECKREG r5, 0x030D72D5;
CHECKREG r6, 0xE621A00D;
CHECKREG r7, 0xCF173844;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x83545abd;
imm32 r1, 0xa8bcfec7;
imm32 r2, 0xc1845679;
imm32 r3, 0x1c080007;
imm32 r4, 0xe1cc8569;
imm32 r5, 0x921c080b;
imm32 r6, 0x7901908d;
imm32 r7, 0x679e9008;
R0.H = ( A1 += R1.L * R0.L ) (M,T);
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ) (M,T);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ) (M,T);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (M,T);
R7 = A1.w;
CHECKREG r0, 0xE5B25ABD;
CHECKREG r1, 0xE5B26993;
CHECKREG r2, 0x09775679;
CHECKREG r3, 0x0977EFC8;
CHECKREG r4, 0x08858569;
CHECKREG r5, 0x0885038C;
CHECKREG r6, 0x30FA908D;
CHECKREG r7, 0x30FA159E;
imm32 r0, 0x03545abd;
imm32 r1, 0xb0bcfec7;
imm32 r2, 0xc1048679;
imm32 r3, 0xd0009007;
imm32 r4, 0xefbc0569;
imm32 r5, 0xcd35510b;
imm32 r6, 0xe00c802d;
imm32 r7, 0xf78e9003;
R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (T);
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (T);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (T);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (T);
R7 = A1.w;
CHECKREG r0, 0x31D75ABD;
CHECKREG r1, 0x31D7F7C8;
CHECKREG r2, 0x2D928679;
CHECKREG r3, 0x2D92A000;
CHECKREG r4, 0x37DF0569;
CHECKREG r5, 0x37DF0DD8;
CHECKREG r6, 0x39FA802D;
CHECKREG r7, 0x39FAC328;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x63548abd;
imm32 r1, 0x7dbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0xb0069007;
imm32 r4, 0xcfbc4569;
imm32 r5, 0xd235c00b;
imm32 r6, 0xe00ca00d;
imm32 r7, 0x678e700f;
R0.H = ( A1 -= R1.L * R0.L ) (T);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (T);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (T);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (T);
R7 = A1.w;
CHECKREG r0, 0x38DC8ABD;
CHECKREG r1, 0x38DC0552;
CHECKREG r2, 0x6EE35679;
CHECKREG r3, 0x6EE397A6;
CHECKREG r4, 0x56C54569;
CHECKREG r5, 0x56C5BD7E;
CHECKREG r6, 0x709FA00D;
CHECKREG r7, 0x709F882E;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x5354babd;
imm32 r1, 0x6dbcdec7;
imm32 r2, 0x7124e679;
imm32 r3, 0x80067007;
imm32 r4, 0x9fbc4569;
imm32 r5, 0xa235900b;
imm32 r6, 0xb00c300d;
imm32 r7, 0xc78ea00f;
R0.H = A1 , A0 -= R1.L * R0.L (T);
R1 = A1.w;
R2.H = A1 , A0 -= R2.H * R3.L (T);
R3 = A1.w;
R4.H = A1 , A0 -= R4.H * R5.H (T);
R5 = A1.w;
R6.H = A1 , A0 -= R6.L * R7.H (T);
R7 = A1.w;
CHECKREG r0, 0x709FBABD;
CHECKREG r1, 0x709F882E;
CHECKREG r2, 0x709FE679;
CHECKREG r3, 0x709F882E;
CHECKREG r4, 0x709F4569;
CHECKREG r5, 0x709F882E;
CHECKREG r6, 0x709F300D;
CHECKREG r7, 0x709F882E;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71245679;
imm32 r3, 0x90060007;
imm32 r4, 0xafbc4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00ca00d;
imm32 r7, 0x678ed00f;
R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (T);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M), A0 -= R2.H * R3.L (T);
R3 = A0.w;
R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (T);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (T);
R7 = A0.w;
CHECKREG r0, 0x710E5ABD;
CHECKREG r1, 0x710E7943;
CHECKREG r2, 0x40685679;
CHECKREG r3, 0x1ED0EB56;
CHECKREG r4, 0x133E4569;
CHECKREG r5, 0x133EAF81;
CHECKREG r6, 0xF960A00D;
CHECKREG r7, 0x4FB9B312;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x83545abd;
imm32 r1, 0xa8bcfec7;
imm32 r2, 0xc1845679;
imm32 r3, 0x1c080007;
imm32 r4, 0xe1cc8569;
imm32 r5, 0x921c080b;
imm32 r6, 0x7901908d;
imm32 r7, 0x679e9008;
R0.H = ( A1 -= R1.L * R0.L ) (M,T);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M,T);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (M,T);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (M,T);
R7 = A1.w;
CHECKREG r0, 0xF9CE5ABD;
CHECKREG r1, 0xF9CEFB3E;
CHECKREG r2, 0xF0575679;
CHECKREG r3, 0xF0570B76;
CHECKREG r4, 0xF1498569;
CHECKREG r5, 0xF149F7B2;
CHECKREG r6, 0xC04F908D;
CHECKREG r7, 0xC04FE214;
pass
|
stsp/binutils-ia16
| 1,057
|
sim/testsuite/bfin/c_brcc_bp2.s
|
//Original:/testcases/core/c_brcc_bp2/c_brcc_bp2.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1 (BP); // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch)
JUMP.S good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF !CC JUMP good3; // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP bad2; // branch on true (should not branch)
JUMP.S end; // we're done
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 6,338
|
sim/testsuite/bfin/c_progctrl_clisti_interr.S
|
//Original:/proj/frio/dv/testcases/core/c_progctrl_clisti_interr/c_progctrl_clisti_interr.dsp
// Spec Reference: CLI STI interrupt on HW TIMER
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL 0xFFE03000
#endif
#ifndef TPERIOD
#define TPERIOD 0xFFE03004
#endif
#ifndef TSCALE
#define TSCALE 0xFFE03008
#endif
#ifndef TCOUNT
#define TCOUNT 0xFFE0300c
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203c
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0x000FF000
#endif
#ifndef PROGRAM_STACK
#define PROGRAM_STACK 0x000FF100
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000300
#endif
// Boot code
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
//CHECK_INIT(p5, 0xE0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
BOOT :
LD32(sp, 0x000FF200);
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken
LD32_LABEL(r7, START);
RETI = r7;
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
START :
R7 = 0x0;
R6 = 0x1;
[ -- SP ] = RETI; // Enable Nested Interrupts
CLI R1; // stop interrupt
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state)
WR_MMR(TPERIOD, 0x00000050, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000000, p0, r0);
CSYNC;
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000050);
// RD_MMR(TCOUNT, p0, r3);
// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN)
CSYNC;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
RD_MMR(TPERIOD, p0, r4);
CHECKREG(r4, 0x00000050);
// RD_MMR(TCNTL, p0, r5);
// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP;
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
WR_MMR(TPERIOD, 0x00000015, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000002, p0, r0);
WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1)
CSYNC;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label4;
R4.L = 0x1111; // Will be killed
R4.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
label5: R5.H = 0x7777;
R5.L = 0x7888;
JUMP.S label6;
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
label4: R4.H = 0x5555;
R4.L = 0x6666;
NOP;
JUMP.S label5;
R5.L = 0x2222; // Will be killed
R5.H = 0x2222; // Will be killed
NOP;
NOP;
NOP;
NOP;
label6: R3.H = 0x7999;
R3.L = 0x7aaa;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
// With auto reload
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000015);
// RD_MMR(TCNTL , p0, r3);
// CHECKREG(r3, 0x0000000F);
NOP;
CHECKREG(r7, 0x00000000); // no interrupt being serviced
NOP;
STI R1;
NOP; NOP; NOP;
NOP; NOP; NOP;
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP; NOP; NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
R7 = R7 + R6;
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
R5 = RETI;
P0 = R5;
JUMP ( P0 );
RTI;
.section MEM_PROGRAM_STACK,"aw"
.space (STACKSIZE);
STACK:
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
|
stsp/binutils-ia16
| 5,912
|
sim/testsuite/bfin/c_ldst_ld_d_p_pp_h.s
|
//Original:/testcases/core/c_ldst_ld_d_p_pp_h/c_ldst_ld_d_p_pp_h.dsp
// Spec Reference: c_ldst ld d [p++] h
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_4;
.endif
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = W [ P5 ++ ] (Z);
R1 = W [ P1 ++ ] (Z);
R2 = W [ P2 ++ ] (Z);
.ifndef BFIN_HOST
R3 = W [ P3 ++ ] (Z);
.endif
R4 = W [ P4 ++ ] (Z);
R5 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00002223;
CHECKREG r2, 0x00004243;
.ifndef BFIN_HOST
CHECKREG r3, 0x00006263;
.endif
CHECKREG r4, 0x00008283;
CHECKREG r5, 0x00000203;
R1 = W [ P5 ++ ] (Z);
R2 = W [ P1 ++ ] (Z);
R3 = W [ P2 ++ ] (Z);
.ifndef BFIN_HOST
R4 = W [ P3 ++ ] (Z);
.endif
R5 = W [ P4 ++ ] (Z);
R6 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00002021;
CHECKREG r3, 0x00004041;
.ifndef BFIN_HOST
CHECKREG r4, 0x00006061;
.endif
CHECKREG r5, 0x00008081;
CHECKREG r6, 0x00000001;
R2 = W [ P5 ++ ] (Z);
R3 = W [ P1 ++ ] (Z);
R4 = W [ P2 ++ ] (Z);
.ifndef BFIN_HOST
R5 = W [ P3 ++ ] (Z);
.endif
R6 = W [ P4 ++ ] (Z);
R7 = W [ FP ++ ] (Z);
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000607;
CHECKREG r3, 0x00002627;
CHECKREG r4, 0x00004647;
.ifndef BFIN_HOST
CHECKREG r5, 0x00006667;
.endif
CHECKREG r6, 0x00008687;
CHECKREG r7, 0x00000607;
R3 = W [ P5 ++ ] (Z);
R4 = W [ P1 ++ ] (Z);
R5 = W [ P2 ++ ] (Z);
.ifndef BFIN_HOST
R6 = W [ P3 ++ ] (Z);
.endif
R7 = W [ P4 ++ ] (Z);
R0 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000405;
CHECKREG r2, 0x00000607;
CHECKREG r3, 0x00000405;
CHECKREG r4, 0x00002425;
.ifndef BFIN_HOST
CHECKREG r5, 0x00004445;
CHECKREG r6, 0x00006465;
.endif
CHECKREG r7, 0x00008485;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 6,193
|
sim/testsuite/bfin/c_ldst_ld_d_p.s
|
//Original:/testcases/core/c_ldst_ld_d_p/c_ldst_ld_d_p.dsp
// Spec Reference: c_ldst ld d [p]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ P5 ];
R6 = [ FP ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x20212223;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x80818283;
CHECKREG r6, 0x00010203;
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
R7 = [ P1 ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x20212223;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
R7 = [ P1 ];
R0 = [ P2 ];
CHECKREG r0, 0x20212223;
CHECKREG r1, 0x20212223;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
R7 = [ P1 ];
R0 = [ P2 ];
CHECKREG r0, 0x20212223;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R4 = [ P5 ];
R5 = [ FP ];
R7 = [ P1 ];
R0 = [ P2 ];
R2 = [ P4 ];
CHECKREG r0, 0x20212223;
CHECKREG r2, 0x60616263;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R5 = [ FP ];
R7 = [ P1 ];
R0 = [ P2 ];
R2 = [ P4 ];
R3 = [ P5 ];
CHECKREG r0, 0x20212223;
CHECKREG r2, 0x60616263;
CHECKREG r3, 0x80818283;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R7 = [ P1 ];
R0 = [ P2 ];
R2 = [ P4 ];
R3 = [ P5 ];
R4 = [ FP ];
CHECKREG r0, 0x20212223;
CHECKREG r2, 0x60616263;
CHECKREG r3, 0x80818283;
CHECKREG r4, 0x00010203;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R7 = [ P1 ];
R0 = [ P2 ];
R2 = [ P4 ];
R3 = [ P5 ];
R4 = [ FP ];
CHECKREG r0, 0x20212223;
CHECKREG r2, 0x60616263;
CHECKREG r3, 0x80818283;
CHECKREG r4, 0x00010203;
CHECKREG r6, 0x00010203;
CHECKREG r7, 0x00010203;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 6,642
|
sim/testsuite/bfin/c_mmr_loop_user_except.S
|
//Original:/proj/frio/dv/testcases/core/c_mmr_loop_user_except/c_mmr_loop_user_except.dsp
// Spec Reference: c_mmr_loop_user_except
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we set the processor operating modes, initialize registers
// etc.)
//
BOOT:
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP; // and frame pointer
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
// LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
// [p0++] = r0;
// LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
// [p0++] = r0;
//*****************
// wrt-rd EVT13 = 0xFFE02034
LD32(p0, 0xFFE02034);
LD32(r0, 0xDDDDABC6);
[ P0 ] = R0;
// wrt-rd EVT14 = 0xFFE02038
LD32(p0, 0xFFE02038);
LD32(r0, 0xEEEEABC6);
[ P0 ] = R0;
//*****************
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI; // execute this instr put us in USER mode
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// USER MODE & go to different RAISE in USER mode
// until the end of the test.
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
// LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
// Raise 1 requires some intelligence so the test
// doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
// RAISE 2; // RTN // exception because we execute this in USER mode
R0 = 0;
LD32(p0, 0xFFE02034);
P2 = 2;
LSETUP ( start1 , end1 ) LC0 = P2;
start1:
R0 = [ P0 ++ ]; // 16 bit instr
end1: R1 = R0;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000000);
//CHECKREG(r3, 0x00000030);
CHECKREG(r4, 0x0000000F);
CHECKREG(r5, 0x00000012);
CHECKREG(r6, 0x00000015);
CHECKREG(r7, 0x00000018);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = RETN;
R0 += 2;
RETN = r0;
RTN;
XHANDLE: // Exception Handler 3
R3 = RETX;
R4 += 5;
R5 += 6;
R6 += 7;
R7 += 8;
R3 += 2; // for resturn address
RETX = r3;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = RETI;
R2 += 2;
RETI = r2;
RTI;
THANDLE: // Timer Handler 6
R3 = RETI;
R3 += 2;
RETI = r3;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = RETI;
R4 += 2;
RETI = r4;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = RETI;
R5 += 2;
RETI = r5;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = RETI;
R6 += 2;
RETI = r6;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = RETI;
R7 += 2;
RETI = r7;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = RETI;
R0 += 2;
RETI = r0;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = RETI;
R1 += 2;
RETI = r1;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = RETI;
R2 += 2;
RETI = r2;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = RETI;
R3 += 2;
RETI = r3;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
// .space (STACKSIZE); // adding this may solve the problem
|
stsp/binutils-ia16
| 9,484
|
sim/testsuite/bfin/c_ldstii_ld_dr_h.s
|
//Original:testcases/core/c_ldstii_ld_dr_h/c_ldstii_ld_dr_h.dsp
// Spec Reference: c_ldstii load dreg h
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0x04;
loadsym i1, DATA_ADDR_3, 0x04;
loadsym p4, DATA_ADDR_1, 0x00;
loadsym p5, DATA_ADDR_2, 0x00;
loadsym fp, DATA_ADDR_3, 0x00;
loadsym i3, DATA_ADDR_4, 0x00;
P3 = I1; SP = I3;
R0 = W [ P1 + 0 ] (Z);
R1 = W [ P1 + 4 ] (Z);
R2 = W [ P1 + 8 ] (Z);
R3 = W [ P1 + 12 ] (Z);
R4 = W [ P1 + 16 ] (Z);
R5 = W [ P1 + 20 ] (Z);
R6 = W [ P1 + 24 ] (Z);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00000607;
CHECKREG r2, 0x00000A0B;
CHECKREG r3, 0x00000E0F;
CHECKREG r4, 0x00001213;
CHECKREG r5, 0x00001617;
CHECKREG r6, 0x00001A1B;
R0 = W [ P2 + 28 ] (Z);
R1 = W [ P2 + 32 ] (Z);
R2 = W [ P2 + 36 ] (Z);
R3 = W [ P2 + 40 ] (Z);
R4 = W [ P2 + 44 ] (Z);
R5 = W [ P2 + 48 ] (Z);
R6 = W [ P2 + 52 ] (Z);
CHECKREG r0, 0x00009394;
CHECKREG r1, 0x00009798;
CHECKREG r2, 0x0000A2A3;
CHECKREG r3, 0x0000A7A8;
CHECKREG r4, 0x0000B1B2;
CHECKREG r5, 0x0000B5B6;
CHECKREG r6, 0x0000B9C0;
R0 = W [ P3 + 56 ] (Z);
R1 = W [ P3 + 60 ] (Z);
R2 = W [ P3 + 64 ] (Z);
R3 = W [ P3 + 60 ] (Z);
R4 = W [ P3 + 56 ] (Z);
R5 = W [ P3 + 52 ] (Z);
R6 = W [ P3 + 48 ] (Z);
CHECKREG r0, 0x000099EA;
CHECKREG r1, 0x000099EA;
CHECKREG r2, 0x000099EA;
CHECKREG r3, 0x000099EA;
CHECKREG r4, 0x000099EA;
CHECKREG r5, 0x0000E5E6;
CHECKREG r6, 0x0000E1E2;
R0 = W [ P4 + 44 ] (Z);
R1 = W [ P4 + 40 ] (Z);
R2 = W [ P4 + 36 ] (Z);
R3 = W [ P4 + 32 ] (Z);
R4 = W [ P4 + 28 ] (Z);
R5 = W [ P4 + 24 ] (Z);
R6 = W [ P4 + 20 ] (Z);
CHECKREG r0, 0x00007677;
CHECKREG r1, 0x00007273;
CHECKREG r2, 0x00007788;
CHECKREG r3, 0x00003344;
CHECKREG r4, 0x00001E1F;
CHECKREG r5, 0x00001A1B;
CHECKREG r6, 0x00001617;
R0 = W [ P5 + 16 ] (Z);
R1 = W [ P5 + 12 ] (Z);
R2 = W [ P5 + 8 ] (Z);
R3 = W [ P5 + 4 ] (Z);
R4 = W [ P5 + 0 ] (Z);
R5 = W [ P5 + 4 ] (Z);
R6 = W [ P5 + 8 ] (Z);
CHECKREG r0, 0x00003233;
CHECKREG r1, 0x00002E2F;
CHECKREG r2, 0x00002A2B;
CHECKREG r3, 0x00002627;
CHECKREG r4, 0x00002223;
CHECKREG r5, 0x00002627;
CHECKREG r6, 0x00002A2B;
R0 = W [ FP + 12 ] (Z);
R1 = W [ FP + 16 ] (Z);
R2 = W [ FP + 20 ] (Z);
R3 = W [ FP + 24 ] (Z);
R4 = W [ FP + 28 ] (Z);
R5 = W [ FP + 32 ] (Z);
R6 = W [ FP + 36 ] (Z);
CHECKREG r0, 0x00004E4F;
CHECKREG r1, 0x00005253;
CHECKREG r2, 0x00005657;
CHECKREG r3, 0x00005A5B;
CHECKREG r4, 0x0000C7C8;
CHECKREG r5, 0x0000CBCD;
CHECKREG r6, 0x0000D1D2;
R0 = W [ SP + 40 ] (Z);
R1 = W [ SP + 44 ] (Z);
R2 = W [ SP + 48 ] (Z);
R3 = W [ SP + 52 ] (Z);
R4 = W [ SP + 56 ] (Z);
R5 = W [ SP + 60 ] (Z);
R6 = W [ SP + 64 ] (Z);
CHECKREG r0, 0x0000F9FA;
CHECKREG r1, 0x0000FDFE;
CHECKREG r2, 0x00000102;
CHECKREG r3, 0x00000506;
CHECKREG r4, 0x0000090A;
CHECKREG r5, 0x0000AD0E;
CHECKREG r6, 0x0000AD01;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 1,346
|
sim/testsuite/bfin/mc_s2.s
|
/* SHIFT test program.
* Test r0, r1, A0 <<= BITMUX;
*/
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// load r0=0x90000001
// load r1=0x90000002
// load r2=0x00000000
// load r3=0x00000000
// load r4=0x20000002
// load r5=0x00000000
loadsym P1, data0;
// insert two bits, both equal to 1
// A0: 00 0000 0000 -> 00 0000 0003
// r0: 9000 0001 -> 2000 0002
// r1: 9000 0002 -> 2000 0004
R0 = [ P1 + 0 ];
R1 = [ P1 + 4 ];
A0.w = R2;
A0.x = R3.L;
BITMUX( R0 , R1, A0) (ASL);
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0003 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
DBGA ( R0.L , 0x0002 );
DBGA ( R0.H , 0x2000 );
DBGA ( R1.L , 0x0004 );
DBGA ( R1.H , 0x2000 );
// insert two bits, one equal to 1, other to 0
// A0: 00 0000 0000 -> 00 0000 0001
// r0: 9000 0001 -> 2000 0002
// r4: 2000 0002 -> 4000 0004
R0 = [ P1 + 0 ];
R4 = [ P1 + 16 ];
A0.w = R2;
A0.x = R3.L;
BITMUX( R0 , R4, A0) (ASL);
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0001 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
DBGA ( R0.L , 0x0002 );
DBGA ( R0.H , 0x2000 );
DBGA ( R4.L , 0x0004 );
DBGA ( R4.H , 0x4000 );
pass
.data
data0:
.dw 0x0001
.dw 0x9000
.dw 0x0002
.dw 0x9000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0002
.dw 0x2000
.dw 0x0000
.dw 0x0000
|
stsp/binutils-ia16
| 4,524
|
sim/testsuite/bfin/c_dsp32mult_pair_i.s
|
//Original:/testcases/core/c_dsp32mult_pair_i/c_dsp32mult_pair_i.dsp
// Spec Reference: dsp32mult pair i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467029;
R1 = R0.L * R0.L, R0 = R0.L * R0.L (IS);
R3 = R0.L * R1.L, R2 = R0.L * R1.H (IS);
R5 = R1.L * R0.L, R4 = R1.H * R0.L (IS);
R7 = R1.L * R1.L, R6 = R1.H * R1.H (IS);
CHECKREG r0, 0x1CFCE159;
CHECKREG r1, 0x1CFCE159;
CHECKREG r2, 0xFC878F9C;
CHECKREG r3, 0x03AB90F1;
CHECKREG r4, 0xFC878F9C;
CHECKREG r5, 0x03AB90F1;
CHECKREG r6, 0x03481810;
CHECKREG r7, 0x03AB90F1;
imm32 r0, 0x5b33a635;
imm32 r1, 0x6fbe5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x9006d037;
imm32 r4, 0x80abcb39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c00dd;
imm32 r7, 0x12469003;
R1 = R2.L * R2.L, R0 = R2.L * R2.L (IS);
R3 = R2.L * R3.L, R2 = R2.L * R3.H (IS);
R5 = R3.L * R2.L, R4 = R3.H * R2.L (IS);
R7 = R3.L * R3.L, R6 = R3.H * R3.H (IS);
CHECKREG r0, 0x14B2D0F9;
CHECKREG r1, 0x14B2D0F9;
CHECKREG r2, 0x1FD71B3E;
CHECKREG r3, 0x0D966C63;
CHECKREG r4, 0x01721C54;
CHECKREG r5, 0x0B88B0FA;
CHECKREG r6, 0x00B893E4;
CHECKREG r7, 0x2DE3AE49;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x00060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00c005d;
imm32 r7, 0x1246705f;
R1 = R4.L * R4.L, R0 = R4.L * R4.L (IS);
R3 = R4.L * R5.L, R2 = R4.L * R5.H (IS);
R5 = R5.L * R4.L, R4 = R5.H * R4.L (IS);
R7 = R5.L * R5.L, R6 = R5.H * R5.H (IS);
CHECKREG r0, 0x0D94DA51;
CHECKREG r1, 0x0D94DA51;
CHECKREG r2, 0xFC28F20C;
CHECKREG r3, 0x03D57133;
CHECKREG r4, 0xFC28F20C;
CHECKREG r5, 0x03D57133;
CHECKREG r6, 0x000EAF39;
CHECKREG r7, 0x320E1029;
imm32 r0, 0xab235666;
imm32 r1, 0xeaba5166;
imm32 r2, 0x13d48766;
imm32 r3, 0xf00b0066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10ac5f6b;
imm32 r6, 0x800cb66d;
imm32 r7, 0x1246707f;
R1 = R6.L * R6.L, R0 = R6.L * R6.L (IS);
R3 = R6.L * R7.L, R2 = R6.L * R7.H (IS);
R5 = R7.L * R6.L, R4 = R7.H * R6.L (IS);
R7 = R7.L * R7.L, R6 = R7.H * R7.H (IS);
CHECKREG r0, 0x15252A69;
CHECKREG r1, 0x15252A69;
CHECKREG r2, 0xFABF8BCE;
CHECKREG r3, 0xDFAB3013;
CHECKREG r4, 0xFABF8BCE;
CHECKREG r5, 0xDFAB3013;
CHECKREG r6, 0x014DEB24;
CHECKREG r7, 0x316F5F01;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (IS);
R3 = R1.L * R0.H, R2 = R1.H * R0.L (IS);
R5 = R7.H * R4.L, R4 = R7.H * R4.L (IS);
R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (IS);
CHECKREG r0, 0x000085FC;
CHECKREG r1, 0x0002D123;
CHECKREG r2, 0xFFFF0BF8;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xFC5CB276;
CHECKREG r5, 0xFC5CB276;
CHECKREG r6, 0xFFFFD0AC;
CHECKREG r7, 0xFFFC0FFE;
imm32 r0, 0x9b235a75;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946905;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d9d;
imm32 r7, 0x12467009;
R3 = R6.L * R5.L, R2 = R6.L * R5.H (IS);
R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (IS);
R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (IS);
R7 = R2.H * R7.L, R6 = R2.H * R7.L (IS);
CHECKREG r0, 0xFF9549FA;
CHECKREG r1, 0xB8ADBDCD;
CHECKREG r2, 0x00E2F57C;
CHECKREG r3, 0xFED28A4F;
CHECKREG r4, 0x1B929715;
CHECKREG r5, 0xD7646535;
CHECKREG r6, 0x0062E7F2;
CHECKREG r7, 0x0062E7F2;
imm32 r0, 0x8b235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13846705;
imm32 r3, 0x00080007;
imm32 r4, 0x90ab8d09;
imm32 r5, 0x10ace8db;
imm32 r6, 0x000c008d;
imm32 r7, 0x12467008;
R3 = R6.H * R5.L, R2 = R6.L * R5.H (IS);
R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (IS);
R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (IS);
R1 = R2.H * R7.L, R0 = R2.L * R7.H (IS);
CHECKREG r0, 0x04A2FAE8;
CHECKREG r1, 0x00043554;
CHECKREG r2, 0x00092EBC;
CHECKREG r3, 0xFFFEEA44;
CHECKREG r4, 0x04B15568;
CHECKREG r5, 0x4A43345C;
CHECKREG r6, 0x00030A1D;
CHECKREG r7, 0x196677B4;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R1.H * R4.L, R0 = R1.H * R4.L (IS);
R3 = R2.L * R5.L, R2 = R2.L * R5.H (IS);
R5 = R3.H * R6.L, R4 = R3.L * R6.L (IS);
R7 = R4.L * R0.H, R6 = R4.H * R0.L (IS);
CHECKREG r0, 0x03A6768A;
CHECKREG r1, 0x03A6768A;
CHECKREG r2, 0x06B5875C;
CHECKREG r3, 0xF919C747;
CHECKREG r4, 0xFFCB7CBB;
CHECKREG r5, 0xFFF99C25;
CHECKREG r6, 0xFFE7756E;
CHECKREG r7, 0x01C71242;
pass
|
stsp/binutils-ia16
| 4,925
|
sim/testsuite/bfin/c_progctrl_excpt.S
|
//Original:/proj/frio/dv/testcases/core/c_progctrl_excpt/c_progctrl_excpt.dsp
// Spec Reference: progctrl excpt uimm4
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
EXCPT 2; // RETX RTX
CHECKREG(r0, 0x0000000A);
CHECKREG(r1, 0x0000000B);
CHECKREG(r2, 0x0000000C);
CHECKREG(r3, 0x0000000D);
CHECKREG(r4, 0x00000000);
CHECKREG(r5, 0x00000000);
CHECKREG(r6, 0x00000000);
CHECKREG(r7, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = 2;
RTN;
XHANDLE: // Exception Handler 3
R0 = 10;
R1 = 11;
R2 = 12;
R3 = 13;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = 5;
RTI;
THANDLE: // Timer Handler 6
R3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 4,586
|
sim/testsuite/bfin/c_dsp32shift_signbits_rl.s
|
//Original:/testcases/core/c_dsp32shift_signbits_rl/c_dsp32shift_signbits_rl.dsp
// Spec Reference: dsp32shift signbits dregs_lo
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;
imm32 r3, 0x0000c003;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000c006;
imm32 r7, 0x0000c007;
R7.L = SIGNBITS R0.L;
R1.L = SIGNBITS R0.L;
R2.L = SIGNBITS R0.L;
R3.L = SIGNBITS R0.L;
R4.L = SIGNBITS R0.L;
R5.L = SIGNBITS R0.L;
R6.L = SIGNBITS R0.L;
R0.L = SIGNBITS R0.L;
CHECKREG r1, 0x0000000F;
CHECKREG r0, 0x0000000F;
CHECKREG r2, 0x0000000F;
CHECKREG r3, 0x0000000F;
CHECKREG r4, 0x0000000F;
CHECKREG r5, 0x0000000F;
CHECKREG r6, 0x0000000F;
CHECKREG r7, 0x0000000F;
imm32 r0, 0x00000001;
imm32 r1, 0x00008001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000e007;
R0.L = SIGNBITS R1.L;
R7.L = SIGNBITS R1.L;
R2.L = SIGNBITS R1.L;
R3.L = SIGNBITS R1.L;
R4.L = SIGNBITS R1.L;
R5.L = SIGNBITS R1.L;
R6.L = SIGNBITS R1.L;
R1.L = SIGNBITS R1.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x0000c001;
imm32 r1, 0x0000d001;
imm32 r2, 0x0000c00f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R0.L = SIGNBITS R2.L;
R1.L = SIGNBITS R2.L;
R7.L = SIGNBITS R2.L;
R3.L = SIGNBITS R2.L;
R4.L = SIGNBITS R2.L;
R5.L = SIGNBITS R2.L;
R6.L = SIGNBITS R2.L;
R2.L = SIGNBITS R2.L;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000001;
imm32 r0, 0x00009001;
imm32 r1, 0x0000a001;
imm32 r2, 0x0000b002;
imm32 r3, 0x00000e10;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000f007;
R0.L = SIGNBITS R3.L;
R1.L = SIGNBITS R3.L;
R2.L = SIGNBITS R3.L;
R7.L = SIGNBITS R3.L;
R4.L = SIGNBITS R3.L;
R5.L = SIGNBITS R3.L;
R6.L = SIGNBITS R3.L;
R3.L = SIGNBITS R3.L;
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00000003;
CHECKREG r2, 0x00000003;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000003;
CHECKREG r5, 0x00000003;
CHECKREG r6, 0x00000003;
CHECKREG r7, 0x00000003;
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x0000f000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = SIGNBITS R4.L;
R1.L = SIGNBITS R4.L;
R2.L = SIGNBITS R4.L;
R3.L = SIGNBITS R4.L;
R7.L = SIGNBITS R4.L;
R5.L = SIGNBITS R4.L;
R6.L = SIGNBITS R4.L;
R4.L = SIGNBITS R4.L;
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00010003;
CHECKREG r2, 0x00020003;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00000003;
CHECKREG r5, 0x00050003;
CHECKREG r6, 0x00060003;
CHECKREG r7, 0x00070003;
imm32 r0, 0x90010000;
imm32 r1, 0x00010001;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x9008f000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R0.L = SIGNBITS R5.L;
R1.L = SIGNBITS R5.L;
R2.L = SIGNBITS R5.L;
R3.L = SIGNBITS R5.L;
R4.L = SIGNBITS R5.L;
R7.L = SIGNBITS R5.L;
R6.L = SIGNBITS R5.L;
R5.L = SIGNBITS R5.L;
CHECKREG r0, 0x90010003;
CHECKREG r1, 0x00010003;
CHECKREG r2, 0x90020003;
CHECKREG r3, 0x90030003;
CHECKREG r4, 0x90040003;
CHECKREG r5, 0x90080003;
CHECKREG r6, 0x90060003;
CHECKREG r7, 0x90070003;
imm32 r1, 0xa0010000;
imm32 r2, 0xa002000f;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa000fc00;
imm32 r7, 0xa0070000;
R0.L = SIGNBITS R6.L;
R1.L = SIGNBITS R6.L;
R2.L = SIGNBITS R6.L;
R3.L = SIGNBITS R6.L;
R4.L = SIGNBITS R6.L;
R5.L = SIGNBITS R6.L;
R7.L = SIGNBITS R6.L;
R6.L = SIGNBITS R6.L;
CHECKREG r0, 0x90010005;
CHECKREG r1, 0xA0010005;
CHECKREG r2, 0xA0020005;
CHECKREG r3, 0xA0030005;
CHECKREG r4, 0xA0040005;
CHECKREG r5, 0xA0050005;
CHECKREG r6, 0xA0000005;
CHECKREG r7, 0xA0070005;
imm32 r0, 0xc0010001;
imm32 r1, 0xc0010001;
imm32 r2, 0xc0020002;
imm32 r3, 0xc0030010;
imm32 r4, 0xc0040004;
imm32 r5, 0xc0050005;
imm32 r6, 0xc0060006;
imm32 r7, 0xc007e007;
R0.L = SIGNBITS R7.L;
R1.L = SIGNBITS R7.L;
R2.L = SIGNBITS R7.L;
R3.L = SIGNBITS R7.L;
R4.L = SIGNBITS R7.L;
R5.L = SIGNBITS R7.L;
R6.L = SIGNBITS R7.L;
R7.L = SIGNBITS R7.L;
CHECKREG r0, 0xC0010002;
CHECKREG r1, 0xC0010002;
CHECKREG r2, 0xC0020002;
CHECKREG r3, 0xC0030002;
CHECKREG r4, 0xC0040002;
CHECKREG r5, 0xC0050002;
CHECKREG r6, 0xC0060002;
CHECKREG r7, 0xC0070002;
pass
|
stsp/binutils-ia16
| 3,495
|
sim/testsuite/bfin/cc-alu.S
|
# Blackfin testcase for CC/A0/A1 compares
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
/* Clear ASTAT before test */
#define CHECK_ASTAT(op, exp) ASTAT = R2; CC = A0 op A1; check_astat exp
.macro check_astat exp:req
R5 = ASTAT;
R6 = \exp;
CC = R5 == R6;
IF !CC JUMP 1f;
.endm
.macro _acc_test exp_eq:req, exp_le:req, exp_lt:req
CHECK_ASTAT(==, \exp_eq)
CHECK_ASTAT(<=, \exp_le)
CHECK_ASTAT(<, \exp_lt)
jump 2f;
1: fail
2:
.endm
.macro acc_test acc0:req, acc1:req, eq:req, le:req, lt:req
dmm32 A0, \acc0
dmm32 A1, \acc1
_acc_test \eq, \le, \lt
.endm
.macro acc_ex_test a0x:req, a0w:req, a1x:req, a1w:req, eq:req, le:req, lt:req
imm32 R0, \a0w
A0.W = R0;
R0 = \a0x;
A0.X = R0;
imm32 R1, \a1w
A1.W = R1;
R1 = \a1x;
A1.X = R1;
_acc_test \eq, \le, \lt
.endm
# Keep R2 with a value of 0
imm32 R2, 0
#define _EQ _AC0|_CC|_AC0_COPY|_AZ, _AC0|_CC|_AC0_COPY|_AZ, _AC0| _AC0_COPY|_AZ
#define _POS_GT _AN, _CC| _AN, _CC| _AN
#define _POS_LT _AC0| _AC0_COPY , _AC0| _AC0_COPY , _AC0| _AC0_COPY
#define _NEG_GT _AC0| _AC0_COPY|_AN, _AC0|_CC|_AC0_COPY|_AN, _AC0|_CC|_AC0_COPY|_AN
#define _NEG_LT 0, 0, 0
# Simple tests around zero
acc_test 0, 0, _EQ
acc_test 0, 1, _POS_GT
acc_test 0, 10000, _POS_GT
acc_test 1, 0, _POS_LT
acc_test 10000, 0, _POS_LT
acc_test 0, -1, _NEG_LT
acc_test 0, -10000, _NEG_LT
acc_test -1, 0, _NEG_GT
acc_test -10000, 0, _NEG_GT
# Simple positive-only tests
acc_test 1, 1, _EQ
acc_test 10000, 10000, _EQ
acc_test 1, 2, _POS_GT
acc_test 1, 20000, _POS_GT
acc_test 2, 1, _POS_LT
acc_test 20000, 1, _POS_LT
# Simple negative-only tests
acc_test -1, -1, _EQ
acc_test -10000, -10000, _EQ
acc_test -1, -2, _POS_LT
acc_test -1, -20000, _POS_LT
acc_test -2, -1, _POS_GT
acc_test -20000, -1, _POS_GT
# Simple postitive/negative tests
acc_test 1, -1, _NEG_LT
acc_test -1, 1, _NEG_GT
acc_test 1, -10000, _NEG_LT
acc_test -10000, 1, _NEG_GT
acc_test -1, 10000, _NEG_GT
acc_test 10000, -1, _NEG_LT
acc_test -10000, 10000, _NEG_GT
acc_test 10000, -10000, _NEG_LT
# Max boundary limits
#define MAX_POS 0x7f, 0xffffffff
#define MAX_NEG 0x80, 0x00000000
acc_ex_test 0, 0, MAX_POS, _POS_GT
acc_ex_test MAX_POS, 0, 0, _POS_LT
acc_ex_test 0, 1, MAX_POS, _POS_GT
acc_ex_test MAX_POS, 0, 1, _POS_LT
acc_ex_test -1, -1, MAX_POS, _NEG_GT
acc_ex_test MAX_POS, -1, -1, _NEG_LT
acc_ex_test MAX_POS, MAX_POS, _EQ
acc_ex_test 0, 0, MAX_POS, _POS_GT
acc_ex_test MAX_POS, 0, 0, _POS_LT
acc_ex_test 0, 1, MAX_POS, _POS_GT
acc_ex_test MAX_POS, 0, 1, _POS_LT
acc_ex_test -1, -1, MAX_POS, _NEG_GT
acc_ex_test MAX_POS, -1, -1, _NEG_LT
acc_ex_test 0, 0, MAX_NEG, _NEG_LT
acc_ex_test MAX_NEG, 0, 0, _NEG_GT
acc_ex_test 0, 1, MAX_NEG, _NEG_LT
acc_ex_test MAX_NEG, 0, 1, _NEG_GT
acc_ex_test -1, -1, MAX_NEG, _POS_LT
acc_ex_test MAX_NEG, -1, -1, _POS_GT
acc_ex_test MAX_NEG, MAX_NEG, _EQ
acc_ex_test 0, 0, MAX_NEG, _NEG_LT
acc_ex_test MAX_NEG, 0, 0, _NEG_GT
acc_ex_test 0, 1, MAX_NEG, _NEG_LT
acc_ex_test MAX_NEG, 0, 1, _NEG_GT
acc_ex_test -1, -1, MAX_NEG, _POS_LT
acc_ex_test MAX_NEG, -1, -1, _POS_GT
acc_ex_test MAX_POS, MAX_NEG, _NEG_LT
acc_ex_test MAX_NEG, MAX_POS, _NEG_GT
pass
|
stsp/binutils-ia16
| 14,252
|
sim/testsuite/bfin/random_0013.S
|
# Ensure that dsp insns with IH modifiers saturate first, then round
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x24304400 | _VS | _AV1S | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ);
dmm32 A0.w, 0x3883de11;
dmm32 A0.x, 0x00000025;
imm32 R2, 0xeb641947;
imm32 R3, 0x66d10863;
imm32 R5, 0x00d44f5a;
R5.L = (A0 += R3.L * R2.L) (IH);
checkreg R5, 0x00d47fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x24304400 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x04b04e10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0x1e069e1a;
dmm32 A0.x, 0xfffffff5;
imm32 R3, 0xffff0001;
R3.L = A0 (IH);
checkreg R3, 0xffff8000;
checkreg ASTAT, (0x04b04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x14f08600 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0x766c79cc;
dmm32 A0.x, 0xffffffd9;
imm32 R4, 0x14801bff;
R4.L = A0 (IH);
checkreg R4, 0x14808000;
checkreg ASTAT, (0x14f08600 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x6060c600 | _VS | _AV1S | _AV0S | _AC1 | _V_COPY | _AN | _AZ);
dmm32 A0.w, 0x1e7461de;
dmm32 A0.x, 0xffffff91;
imm32 R6, 0x1ba08a9e;
R6.L = A0 (IH);
checkreg R6, 0x1ba08000;
checkreg ASTAT, (0x6060c600 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AN);
dmm32 ASTAT, (0x28700e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 A0.w, 0xfb5acc4e;
dmm32 A0.x, 0xfffffffe;
imm32 R4, 0x15baf604;
R4.L = A0 (IH);
checkreg R4, 0x15ba8000;
checkreg ASTAT, (0x28700e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x24708610 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A0.w, 0x0de70c92;
dmm32 A0.x, 0xffffffde;
imm32 R3, 0x0f323c4c;
R3.L = A0 (IH);
checkreg R3, 0x0f328000;
checkreg ASTAT, (0x24708610 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x6800c880 | _AV1 | _AV0 | _AQ | _AZ);
dmm32 A0.w, 0x482bfb59;
dmm32 A0.x, 0x0000005e;
imm32 R6, 0x4616e4ad;
imm32 R7, 0x4a88b2b1;
R6.L = (A0 += R6.H * R7.L) (IH);
checkreg R6, 0x46167fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x6800c880 | _VS | _V | _AV1 | _AV0S | _AV0 | _AQ | _V_COPY | _AZ);
dmm32 ASTAT, (0x44d08280 | _VS | _V | _AQ | _V_COPY | _AZ);
dmm32 A0.w, 0xf29e3a4c;
dmm32 A0.x, 0x0000003b;
imm32 R2, 0x004027d0;
imm32 R4, 0x44761fd1;
imm32 R7, 0x7fff0001;
R7.L = (A0 -= R4.H * R2.H) (IH);
checkreg R7, 0x7fff7fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x44d08280 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AZ);
dmm32 ASTAT, (0x18a00680 | _VS | _AV1S | _AQ | _CC);
dmm32 A0.w, 0x174c203a;
dmm32 A0.x, 0x00000060;
imm32 R3, 0x1f100000;
R3.L = A0 (IH);
checkreg R3, 0x1f107fff;
checkreg ASTAT, (0x18a00680 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x38e04090 | _VS | _AV0S | _AQ | _AN | _AZ);
dmm32 A0.w, 0x5db9b913;
dmm32 A0.x, 0x00000048;
imm32 R0, 0xd513ffff;
imm32 R2, 0xfcee02ff;
R0.L = (A0 -= R2.H * R0.H) (IH);
checkreg R0, 0xd5137fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x38e04090 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AN | _AZ);
dmm32 ASTAT, (0x2030c680 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0x113de06e;
dmm32 A0.x, 0x00000006;
imm32 R3, 0x3de9b335;
R3.L = A0 (IH);
checkreg R3, 0x3de97fff;
checkreg ASTAT, (0x2030c680 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x14300210 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0x3219dde5;
dmm32 A0.x, 0xfffffffe;
imm32 R2, 0x8000ffde;
R2.L = A0 (IH);
checkreg R2, 0x80008000;
checkreg ASTAT, (0x14300210 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x5c304e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0x500d8a96;
dmm32 A0.x, 0x00000071;
imm32 R2, 0x47bc6a2d;
R2.L = A0 (IH);
checkreg R2, 0x47bc7fff;
checkreg ASTAT, (0x5c304e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x40d04410 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0xed76198b;
dmm32 A0.x, 0xffffffdd;
imm32 R4, 0x485f8000;
R4.L = A0 (IH);
checkreg ASTAT, (0x40d04410 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x34f00290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0xc0000000;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x80008000;
imm32 R3, 0x2cb77eda;
R0.L = (A0 += R3.H * R3.H) (IH);
checkreg R0, 0x80007fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x34f00290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x2490c610 | _VS | _V | _V_COPY | _AN);
dmm32 A0.w, 0xc2375c00;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x8000ffff;
imm32 R1, 0xac86b35f;
imm32 R6, 0x3cb137de;
R0.L = (A0 -= R6.H * R1.H) (IH);
checkreg R0, 0x80007fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x2490c610 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AN);
dmm32 ASTAT, (0x3000c810 | _VS | _AC0 | _AQ | _CC | _AN);
dmm32 A0.w, 0x44fe7a9d;
dmm32 A0.x, 0x0000006e;
imm32 R2, 0xbb4f8000;
imm32 R4, 0xfe2d7fff;
imm32 R7, 0x5da7ea43;
R7.L = (A0 += R4.L * R2.L) (IH);
checkreg R7, 0x5da77fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x3000c810 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x1c708000 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AZ);
dmm32 A0.w, 0x6ad001aa;
dmm32 A0.x, 0x0000002a;
imm32 R6, 0x7fff65d9;
R6.L = A0 (IH);
checkreg R6, 0x7fff7fff;
checkreg ASTAT, (0x1c708000 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x1430cc80 | _AV0S | _AC0 | _AQ | _AN | _AZ);
dmm32 A0.w, 0x5c04c87a;
dmm32 A0.x, 0x00000002;
imm32 R1, 0x6752c24c;
imm32 R7, 0x21f7c24f;
R1.L = (A0 -= R1.H * R7.H) (IH);
checkreg R1, 0x67527fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x1430cc80 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY | _AN | _AZ);
dmm32 ASTAT, (0x44500c80 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A0.w, 0x603980cf;
dmm32 A0.x, 0xffffffff;
imm32 R3, 0xffffffff;
R3.L = A0 (IH);
checkreg R3, 0xffff8000;
checkreg ASTAT, (0x44500c80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x70508c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY);
dmm32 A0.w, 0x097b558d;
dmm32 A0.x, 0x00000005;
imm32 R1, 0x80002c0a;
R1.L = A0 (IH);
checkreg R1, 0x80007fff;
checkreg ASTAT, (0x70508c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY);
dmm32 ASTAT, (0x1820c410 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ);
dmm32 A0.w, 0x69470e6b;
dmm32 A0.x, 0x0000005a;
imm32 R1, 0x3a0e82ef;
imm32 R4, 0x2c0af024;
imm32 R6, 0x5a301523;
R1.L = (A0 += R6.L * R4.L) (IH);
checkreg R1, 0x3a0e7fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x1820c410 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x14a04e10 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0xaaa829c8;
dmm32 A0.x, 0x0000000f;
imm32 R3, 0x901b7fff;
imm32 R4, 0xf8d50755;
imm32 R6, 0x0a98c742;
R4.L = (A0 += R3.L * R6.L) (IH);
checkreg R4, 0xf8d57fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x14a04e10 | _VS | _V | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x7c70c800 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY);
dmm32 A0.w, 0x3875c265;
dmm32 A0.x, 0x0000000e;
imm32 R0, 0x8000af00;
imm32 R3, 0x071fe97d;
imm32 R5, 0x72d82b4b;
R0.L = (A0 += R3.H * R5.H) (IH);
checkreg R0, 0x80007fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x7c70c800 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x04508a80 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY);
dmm32 A0.w, 0x5055d0b1;
dmm32 A0.x, 0x00000009;
imm32 R2, 0x7b9b1a96;
imm32 R4, 0x56a17f45;
R4.L = (A0 -= R4.L * R2.L) (IH);
checkreg R4, 0x56a17fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x04508a80 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x60408c90 | _VS | _AV1 | _CC | _AC0_COPY);
dmm32 A1.w, 0x4d722bbd;
dmm32 A1.x, 0x0000000a;
imm32 R1, 0x31c46841;
imm32 R4, 0xe31521b2;
imm32 R6, 0x49d747d4;
R6.H = (A1 -= R1.L * R4.L) (M, IH);
checkreg R6, 0x7fff47d4;
checkreg A1.w, 0x7fffffff;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x60408c90 | _VS | _V | _AV1S | _AV1 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x7c808690 | _VS | _AV1S | _AC1 | _AC0 | _AC0_COPY);
dmm32 A0.w, 0x48379e0d;
dmm32 A0.x, 0x00000061;
imm32 R0, 0x272c8000;
imm32 R4, 0x7fff7fff;
R0.L = (A0 += R4.L * R4.H) (IH);
checkreg R0, 0x272c7fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x7c808690 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x10308800 | _VS | _AC1 | _AC0 | _AQ | _AN);
dmm32 A1.w, 0x9ddbf339;
dmm32 A1.x, 0x00000010;
imm32 R1, 0x00679160;
imm32 R5, 0x1fa0ffff;
imm32 R6, 0x4312c2cd;
R6.H = (A1 -= R1.L * R5.H) (IH);
checkreg R6, 0x7fffc2cd;
checkreg A1.w, 0x7fffffff;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x10308800 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x3040ca90 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC | _AN | _AZ);
dmm32 A0.w, 0x2d631ab7;
dmm32 A0.x, 0x00000066;
imm32 R5, 0x325c8000;
R5.L = A0 (IH);
checkreg R5, 0x325c7fff;
checkreg ASTAT, (0x3040ca90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x5ca08c90 | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0x86fce74b;
dmm32 A0.x, 0x0000007f;
imm32 R1, 0x3e9e0014;
imm32 R7, 0x6d73d06c;
R7.L = (A0 += R1.L * R7.H) (IH);
checkreg R7, 0x6d737fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x5ca08c90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x50e0c880 | _VS | _AC1);
dmm32 A0.w, 0x9e40a194;
dmm32 A0.x, 0x00000000;
imm32 R5, 0x6ba7ac29;
imm32 R6, 0x50a97ffe;
R5.L = (A0 += R6.L * R5.H) (IH);
checkreg R5, 0x6ba77fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x50e0c880 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY);
dmm32 ASTAT, (0x3ce0c810 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0x9abe32ae;
dmm32 A0.x, 0xffffffc2;
imm32 R2, 0x8000e9a0;
R2.L = A0 (IH);
checkreg R2, 0x80008000;
checkreg ASTAT, (0x3ce0c810 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x6090c010 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY);
dmm32 A0.w, 0x53e97a53;
dmm32 A0.x, 0x0000004d;
imm32 R1, 0x289e2e4e;
R1.L = A0 (IH);
checkreg R1, 0x289e7fff;
checkreg ASTAT, (0x6090c010 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x34708800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN);
dmm32 A0.w, 0x1035b3fa;
dmm32 A0.x, 0x00000001;
imm32 R1, 0xec227fff;
R1.L = A0 (IH);
checkreg ASTAT, (0x34708800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x30200c00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _V_COPY);
imm32 R1, 0x30d07fff;
imm32 R2, 0x007f1105;
imm32 R4, 0x7fffffff;
R1.H = R2.L * R4.L (M, IH);
checkreg R1, 0x11057fff;
checkreg ASTAT, (0x30200c00 | _VS | _AV1S | _AV0S | _AV0 | _AC1);
dmm32 ASTAT, (0x1c008200 | _VS | _V | _AV1S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 A0.w, 0x46ccaead;
dmm32 A0.x, 0x0000006b;
imm32 R4, 0x80003753;
imm32 R5, 0x128216a3;
imm32 R6, 0x7c3455c4;
R4.L = (A0 += R5.L * R6.H) (IH);
checkreg R4, 0x80007fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x1c008200 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x14304e10 | _VS | _AV0S | _AV0 | _AC0);
dmm32 A0.w, 0x7fc17d70;
dmm32 A0.x, 0x0000000f;
imm32 R3, 0x5cb72991;
imm32 R4, 0x3a823142;
imm32 R7, 0xde5bf5a2;
R7.L = (A0 += R4.H * R3.H) (IH);
checkreg R7, 0xde5b7fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x14304e10 | _VS | _V | _AV0S | _AV0 | _AC0 | _V_COPY);
dmm32 ASTAT, (0x10900290 | _VS | _V | _AQ | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0x7fb16a1d;
dmm32 A0.x, 0x00000052;
imm32 R0, 0x1e4a7fff;
imm32 R2, 0x62b886f4;
imm32 R3, 0x80004104;
R3.L = (A0 -= R2.H * R0.H) (IH);
checkreg R3, 0x80007fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x10900290 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x18608400 | _VS | _AV1S | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0x62fcbde0;
dmm32 A1.x, 0x0000006a;
imm32 R2, 0x60339fcc;
imm32 R3, 0x5fa9f612;
imm32 R4, 0x6f006000;
R2.H = (A1 += R3.L * R4.H) (IH);
checkreg R2, 0x7fff9fcc;
checkreg A1.w, 0x7fffffff;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x18608400 | _VS | _V | _AV1S | _AV1 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x60100210 | _VS | _V | _CC | _V_COPY | _AN);
dmm32 A0.w, 0x52a9b75e;
dmm32 A0.x, 0x00000003;
imm32 R0, 0xffff349c;
imm32 R6, 0x0084550f;
R0.L = (A0 += R6.L * R0.H) (IH);
checkreg R0, 0xffff7fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x60100210 | _VS | _V | _AV0S | _AV0 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x7840cc10 | _VS | _V | _AV0 | _AC1 | _V_COPY | _AN | _AZ);
dmm32 A0.w, 0x22aa6b49;
dmm32 A0.x, 0x0000006a;
imm32 R1, 0x17528642;
imm32 R5, 0x8000a49b;
imm32 R6, 0x03ec4bb6;
R5.L = (A0 -= R1.H * R6.H) (IH);
checkreg R5, 0x80007fff;
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x7840cc10 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN | _AZ);
pass
|
stsp/binutils-ia16
| 8,487
|
sim/testsuite/bfin/c_seq_wb_cs_lsmmrj_mvp.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_wb_cs_lsmmrj_mvp/c_seq_wb_cs_lsmmrj_mvp.dsp
// Spec Reference: sequencer:wb ( csync ldst mmr jump regmv pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
//LD32(p2, DATA_ADDR_1);
loadsym P2, DATA;
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
LD32(r2, 0x14789232);
[ P1 ] = R2;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
[ -- SP ] = ( R7:0 );
// RAISE 2; // RTN
CSYNC;
R0 = [ P2 ++ ];
R1 = [ P1 ];
JUMP.S LABEL1;
P3 = R7;
R4 = P3;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
// RAISE 5; // RTI
CSYNC;
R2 = [ P2 ++ ];
P4 = R6;
R3 = P4;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
// wrt-rd EVT5 = 0xFFE02034
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
// RAISE 6; // RTI
CSYNC;
R4 = [ P2 ++ ];
R6 = [ P1 ];
JUMP.S LABEL2;
P3 = R3;
R5 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
CSYNC;
CHECKREG(r0, 0x00010203);
CHECKREG(r1, 0x14789232);
CHECKREG(r2, 0x00000023);
CHECKREG(r3, 0x00000024);
CHECKREG(r4, 0x08090A0B);
CHECKREG(r5, 0x00000026);
CHECKREG(r6, 0x14789232);
// RAISE 7; // RTI
CSYNC;
R0 = [ P2 ++ ];
R1 = [ P1 ];
P4 = R4;
R2 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00010203);
CHECKREG(r1, 0x14789232);
CHECKREG(r2, 0x04050607);
CHECKREG(r3, 0x00000007);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
// wrt-rd EVT13 = 0xFFE02034
LD32(p1, 0xFFE02034);
// RAISE 8; // RTI
CSYNC;
R0 = [ P2 ++ ];
R1 = [ P1 ];
JUMP.S LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
CSYNC;
CHECKREG(r0, 0x10111213);
CHECKREG(r1, 0x14789232);
// RAISE 9; // RTI
CSYNC;
P3 = R6;
R7 = P3;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.section MEM_DATA_ADDR_1,"aw"
DATA:
// .space (0x10);
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
.section MEM_DATA_ADDR_2,"aw"
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
|
stsp/binutils-ia16
| 2,555
|
sim/testsuite/bfin/c_brcc_kills_dhits.s
|
//Original:/testcases/core/c_brcc_kills_dhits/c_brcc_kills_dhits.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
imm32 p1, 0x00000011;
imm32 p2, 0x00000012;
.ifndef BFIN_HOST
imm32 p3, 0x00000013;
.endif
imm32 p4, 0x00000014;
loadsym P5, DATA0;
loadsym I0, DATA1;
begin:
ASTAT = R0; // clear CC
IF !CC JUMP LABEL1; // (bp);
CC = R4 < R5; // CC FLAG killed
R1 = 21;
LABEL1:
IF !CC JUMP LABEL2; // (bp);
CC = ! CC;
LABEL2:
IF !CC JUMP LABEL3; // (bp);
R2 = - R2; // ALU2op killed
LABEL3:
IF !CC JUMP LABEL4;
R3 <<= 2; // LOGI2op killed
LABEL4:
IF !CC JUMP LABEL5;
R0 = R1 + R2; // COMP3op killed
LABEL5:
IF !CC JUMP LABEL6;
R4 += 3; // COMPI2opD killed
LABEL6:
IF !CC JUMP LABEL7; // (bp);
R5 = 25; // LDIMMHALF killed
LABEL7:
IF !CC JUMP LABEL8;
R6 = CC; // CC2REG killed
LABEL8:
IF !CC JUMP LABEL9;
JUMP.S BAD1; // UJUMP killed
LABEL9:
IF !CC JUMP LABELCHK1;
BAD1:
R7 = [ P5 ]; // LDST killed
LABELCHK1:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
LABEL10:
IF !CC JUMP LABEL11;
R1 = ( A1 += R4.L * R5.H ), A0 += R4.H * R5.L;
// DSP32MAC killed
LABEL11:
IF !CC JUMP LABEL12;
R2 = R2 +|+ R3; // DSP32ALU killed
LABEL12:
IF !CC JUMP LABEL13;
R3 = LSHIFT R2 BY R3.L (V); // dsp32shift killed
LABEL13:
IF !CC JUMP LABEL14;
R4.H = R1.L << 6; // DSP32SHIFTIMM killed
LABEL14:
IF !CC JUMP LABEL15;
P2 = P1; // REGMV PREG-PREG killed
LABEL15:
IF !CC JUMP LABEL16;
R5 = P1; // REGMV Pr-to-Dr killed
LABEL16:
IF !CC JUMP LABEL17;
ASTAT = R2; // REGMV Dr-to-sys killed
LABEL17:
IF !CC JUMP LABEL18;
R6 = ASTAT; // REGMV sys-to-Dr killed
LABEL18:
IF !CC JUMP LABEL19;
[ I0 ] = R2; // DSPLDST store killed
LABEL19:
IF !CC JUMP end;
R7 = [ I0 ]; // DSPLDST load killed
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
|
stsp/binutils-ia16
| 2,470
|
sim/testsuite/bfin/dsp_a4.s
|
/* ALU test program.
* Test instructions
* r3= + (r0,r0);
* r3= + (r0,r0) s;
* r3= - (r0,r0);
* r3= - (r0,r0) s;
*/
# mach: bfin
.include "testutils.inc"
start
// overflow positive
R0.L = 0xffff;
R0.H = 0x7fff;
R7 = 0;
ASTAT = R7;
R3 = R0 + R0 (NS);
DBGA ( R3.L , 0xfffe );
DBGA ( R3.H , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// overflow negative
R0.L = 0x0000;
R0.H = 0x8000;
R7 = 0;
ASTAT = R7;
R3 = R0 + R0 (NS);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// zero
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0x0001;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R3 = R1 + R0 (NS);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive
R0.L = 0;
R0.H = 0x7fff;
R7 = 0;
ASTAT = R7;
R3 = R0 + R0 (S);
DBGA ( R3.L , 0xffff );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate negative
R0.L = 0;
R0.H = 0x8000;
R7 = 0;
ASTAT = R7;
R3 = R0 + R0 (S);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive with subtraction
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0xffff;
R1.H = 0x7fff;
R7 = 0;
ASTAT = R7;
R3 = R1 - R0 (S);
DBGA ( R3.L , 0xffff );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate negative with subtraction
R0.L = 0x1;
R0.H = 0x0;
R1.L = 0x0000;
R1.H = 0x8000;
R7 = 0;
ASTAT = R7;
R3 = R1 - R0 (S);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
pass
|
stsp/binutils-ia16
| 1,211
|
sim/testsuite/bfin/c_dsp32alu_absabs.s
|
//Original:/testcases/core/c_dsp32alu_absabs/c_dsp32alu_absabs.dsp
// Spec Reference: dsp32alu dregs = abs / abs ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0 = ABS R0 (V);
R1 = ABS R1 (V);
R2 = ABS R2 (V);
R3 = ABS R3 (V);
R4 = ABS R4 (V);
R5 = ABS R5 (V);
R6 = ABS R6 (V);
R7 = ABS R7 (V);
CHECKREG r0, 0x156776EF;
CHECKREG r1, 0x278954E3;
CHECKREG r2, 0x34445515;
CHECKREG r3, 0x46667717;
CHECKREG r4, 0x556776E5;
CHECKREG r5, 0x678954E3;
CHECKREG r6, 0x74445515;
CHECKREG r7, 0x799A7777;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = ABS R7 (V);
R1 = ABS R6 (V);
R2 = ABS R5 (V);
R3 = ABS R4 (V);
R4 = ABS R3 (V);
R5 = ABS R2 (V);
R6 = ABS R1 (V);
R7 = ABS R0 (V);
CHECKREG r0, 0x0EEE0001;
CHECKREG r1, 0x033422D3;
CHECKREG r2, 0x155644D5;
CHECKREG r3, 0x277866D7;
CHECKREG r4, 0x277866D7;
CHECKREG r5, 0x155644D5;
CHECKREG r6, 0x033422D3;
CHECKREG r7, 0x0EEE0001;
pass
|
stsp/binutils-ia16
| 2,735
|
sim/testsuite/bfin/c_compi2opp_pr_add_i7_n.s
|
//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_n/c_compi2opp_pr_add_i7_n.dsp
// Spec Reference: compi2opp pregs += imm7 negative
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
INIT_P_REGS 0;
imm32 sp, 0x00000000;
imm32 fp, 0x00000000;
P1 += -1;
P2 += -2;
P3 += -3;
P4 += -4;
P5 += -5;
SP += -6;
FP += -7;
CHECKREG p1, 0xFFFFFFFF;
CHECKREG p2, 0xFFFFFFFE;
CHECKREG p3, 0xFFFFFFFD;
CHECKREG p4, 0xFFFFFFFC;
CHECKREG p5, 0xFFFFFFFB;
CHECKREG sp, 0xFFFFFFFA;
CHECKREG fp, 0xFFFFFFF9;
P1 += -9;
P2 += -10;
P3 += -11;
P4 += -12;
P5 += -13;
SP += -14;
FP += -15;
CHECKREG p1, 0xFFFFFFF6;
CHECKREG p2, 0xFFFFFFF4;
CHECKREG p3, 0xFFFFFFF2;
CHECKREG p4, 0xFFFFFFF0;
CHECKREG p5, 0xFFFFFFEE;
CHECKREG sp, 0xFFFFFFEC;
CHECKREG fp, 0xFFFFFFEA;
P1 += -17;
P2 += -18;
P3 += -19;
P4 += -20;
P5 += -21;
SP += -22;
FP += -23;
CHECKREG p1, 0xFFFFFFE5;
CHECKREG p2, 0xFFFFFFE2;
CHECKREG p3, 0xFFFFFFDF;
CHECKREG p4, 0xFFFFFFDC;
CHECKREG p5, 0xFFFFFFD9;
CHECKREG sp, 0xFFFFFFD6;
CHECKREG fp, 0xFFFFFFD3;
P1 += -25;
P2 += -26;
P3 += -27;
P4 += -28;
P5 += -29;
SP += -30;
FP += -31;
CHECKREG p1, 0xFFFFFFCC;
CHECKREG p2, 0xFFFFFFC8;
CHECKREG p3, 0xFFFFFFC4;
CHECKREG p4, 0xFFFFFFC0;
CHECKREG p5, 0xFFFFFFBC;
CHECKREG sp, 0xFFFFFFB8;
CHECKREG fp, 0xFFFFFFB4;
P1 += -33;
P2 += -34;
P3 += -35;
P4 += -36;
P5 += -37;
SP += -38;
FP += -39;
CHECKREG p1, 0xFFFFFFAB;
CHECKREG p2, 0xFFFFFFA6;
CHECKREG p3, 0xFFFFFFA1;
CHECKREG p4, 0xFFFFFF9C;
CHECKREG p5, 0xFFFFFF97;
CHECKREG sp, 0xFFFFFF92;
CHECKREG fp, 0xFFFFFF8D;
P1 += -41;
P2 += -42;
P3 += -43;
P4 += -44;
P5 += -45;
SP += -46;
FP += -47;
CHECKREG p1, 0xFFFFFF82;
CHECKREG p2, 0xFFFFFF7C;
CHECKREG p3, 0xFFFFFF76;
CHECKREG p4, 0xFFFFFF70;
CHECKREG p5, 0xFFFFFF6A;
CHECKREG sp, 0xFFFFFF64;
CHECKREG fp, 0xFFFFFF5E;
P1 += -49;
P2 += -50;
P3 += -51;
P4 += -52;
P5 += -53;
SP += -54;
FP += -55;
CHECKREG p1, 0xFFFFFF51;
CHECKREG p2, 0xFFFFFF4A;
CHECKREG p3, 0xFFFFFF43;
CHECKREG p4, 0xFFFFFF3C;
CHECKREG p5, 0xFFFFFF35;
CHECKREG sp, 0xFFFFFF2E;
CHECKREG fp, 0xFFFFFF27;
P1 += -57;
P2 += -58;
P3 += -59;
P4 += -60;
P5 += -61;
SP += -62;
FP += -63;
CHECKREG p1, 0xFFFFFF18;
CHECKREG p2, 0xFFFFFF10;
CHECKREG p3, 0xFFFFFF08;
CHECKREG p4, 0xFFFFFF00;
CHECKREG p5, 0xFFFFFEF8;
CHECKREG sp, 0xFFFFFEF0;
CHECKREG fp, 0xFFFFFEE8;
P1 += -64;
P2 += -64;
P3 += -64;
P4 += -64;
P5 += -64;
SP += -64;
FP += -64;
CHECKREG p1, 0xFFFFFED8;
CHECKREG p2, 0xFFFFFED0;
CHECKREG p3, 0xFFFFFEC8;
CHECKREG p4, 0xFFFFFEC0;
CHECKREG p5, 0xFFFFFEB8;
CHECKREG sp, 0xFFFFFEB0;
CHECKREG fp, 0xFFFFFEA8;
pass
|
stsp/binutils-ia16
| 5,188
|
sim/testsuite/bfin/c_dsp32mac_a1a0.s
|
//Original:/testcases/core/c_dsp32mac_a1a0/c_dsp32mac_a1a0.dsp
// Spec Reference: dsp32mac a1 a0
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
// test the default (signed fraction : left )
imm32 r0, 0x12345678;
imm32 r1, 0x33456789;
imm32 r2, 0x5556789a;
imm32 r3, 0x75678912;
imm32 r4, 0x86789123;
imm32 r5, 0xa7891234;
imm32 r6, 0xc1234567;
imm32 r7, 0xf1234567;
A1 = R0.L * R1.L, A0 = R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 = R2.L * R3.L, A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 += R4.L * R5.L, A0 = R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.L * R7.L, A0 += R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x45F11C70;
CHECKREG r1, 0x45F11C70;
CHECKREG r2, 0xB48EEC5C;
CHECKREG r3, 0x8FF1C9A8;
CHECKREG r4, 0xEEB780C0;
CHECKREG r5, 0x802DABE0;
CHECKREG r6, 0xF6043652;
CHECKREG r7, 0xA5CF0AC2;
imm32 r0, 0x12245618;
imm32 r1, 0x23256719;
imm32 r2, 0x3426781a;
imm32 r3, 0x45278912;
imm32 r4, 0x56289113;
imm32 r5, 0x67291214;
imm32 r6, 0xa1234517;
imm32 r7, 0xc1234517;
A1 = R0.L * R1.H, A0 += R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 = R2.L * R3.H, A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 = R4.L * R5.H, A0 += R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 = R6.L * R7.H, A0 += R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x3B5C5702;
CHECKREG r1, 0x17A372F0;
CHECKREG r2, 0x7C3EF2EE;
CHECKREG r3, 0x40E29BEC;
CHECKREG r4, 0x886A092E;
CHECKREG r5, 0xA699C216;
CHECKREG r6, 0xB700DEC0;
CHECKREG r7, 0xDE11924A;
imm32 r0, 0x15245648;
imm32 r1, 0x25256749;
imm32 r2, 0x3526784a;
imm32 r3, 0x45278942;
imm32 r4, 0x55389143;
imm32 r5, 0x65391244;
imm32 r6, 0xa5334547;
imm32 r7, 0xc5334547;
A1 += R0.H * R1.H, A0 = R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 += R2.H * R3.H, A0 = R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 += R4.H * R5.H, A0 = R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.H * R7.H, A0 = R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x459F2510;
CHECKREG r1, 0xE43416B2;
CHECKREG r2, 0x40FC8A8C;
CHECKREG r3, 0x00EAC446;
CHECKREG r4, 0x0C2925C0;
CHECKREG r5, 0x444EE736;
CHECKREG r6, 0x29B65052;
CHECKREG r7, 0x6E053788;
imm32 r0, 0x13245628;
imm32 r1, 0x23256729;
imm32 r2, 0x3326782a;
imm32 r3, 0x43278922;
imm32 r4, 0x56389123;
imm32 r5, 0x67391224;
imm32 r6, 0xa1334527;
imm32 r7, 0xc1334527;
A1 += R0.H * R1.L, A0 += R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 = R2.H * R3.L, A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 = R4.H * R5.L, A0 += R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 = R6.H * R7.L, A0 += R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x6F261922;
CHECKREG r1, 0x7D725110;
CHECKREG r2, 0xAE30B1EE;
CHECKREG r3, 0xD0804218;
CHECKREG r4, 0xBA68D1AE;
CHECKREG r5, 0x0C381FC0;
CHECKREG r6, 0xE8EBF200;
CHECKREG r7, 0xCCC89B8A;
imm32 r0, 0x01340678;
imm32 r1, 0x02450789;
imm32 r2, 0x0356089a;
imm32 r3, 0x04670912;
imm32 r4, 0x05780123;
imm32 r5, 0x06890234;
imm32 r6, 0x07230567;
imm32 r7, 0x00230567;
A1 -= R0.L * R1.L, A0 = R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 = R2.L * R3.L, A0 -= R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 -= R4.L * R5.L, A0 -= R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 -= R6.L * R7.L, A0 += R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x00617C70;
CHECKREG r1, 0xCC671F1A;
CHECKREG r2, 0x0015C084;
CHECKREG r3, 0x009C09A8;
CHECKREG r4, 0xFFFDA7C4;
CHECKREG r5, 0x00970770;
CHECKREG r6, 0xFFFF9B56;
CHECKREG r7, 0x005CA88E;
imm32 r0, 0x00245618;
imm32 r1, 0x01256719;
imm32 r2, 0x0226781a;
imm32 r3, 0x03278912;
imm32 r4, 0x06489113;
imm32 r5, 0x05291214;
imm32 r6, 0x01634517;
imm32 r7, 0x02234517;
A1 += R0.L * R1.H, A0 -= R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 -= R2.L * R3.H, A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 -= R4.L * R5.H, A0 -= R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.L * R7.H, A0 -= R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0xBAA77AA6;
CHECKREG r1, 0x0121BB7E;
CHECKREG r2, 0xBD9CAE92;
CHECKREG r3, 0xFE2C8792;
CHECKREG r4, 0xBCB99352;
CHECKREG r5, 0x02A5517C;
CHECKREG r6, 0xBCB3A640;
CHECKREG r7, 0x03CC91C6;
imm32 r0, 0x10240648;
imm32 r1, 0x25156749;
imm32 r2, 0x3526084a;
imm32 r3, 0x45238942;
imm32 r4, 0x51381143;
imm32 r5, 0x62392244;
imm32 r6, 0xa3333547;
imm32 r7, 0xc4334547;
A1 += R0.H * R1.H, A0 -= R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 -= R2.H * R3.H, A0 -= R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 -= R4.H * R5.H, A0 += R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.H * R7.H, A0 -= R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0xB7A22130;
CHECKREG r1, 0x08799FAE;
CHECKREG r2, 0xB327F8F4;
CHECKREG r3, 0xEBC49B4A;
CHECKREG r4, 0xC8E5FEB4;
CHECKREG r5, 0xAD71905A;
CHECKREG r6, 0x9D8AE062;
CHECKREG r7, 0xD8CCAEAC;
imm32 r0, 0x10245628;
imm32 r1, 0x23056729;
imm32 r2, 0x3320782a;
imm32 r3, 0x43270922;
imm32 r4, 0x56389023;
imm32 r5, 0x67391024;
imm32 r6, 0x21334507;
imm32 r7, 0x11334520;
A1 += R0.H * R1.L, A0 -= R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 -= R2.H * R3.L, A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 -= R4.H * R5.L, A0 -= R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.H * R7.L, A0 -= R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x581B1792;
CHECKREG r1, 0xE5CED234;
CHECKREG r2, 0x9725B05E;
CHECKREG r3, 0xE228FDB4;
CHECKREG r4, 0x8C46709E;
CHECKREG r5, 0xD749BDF4;
CHECKREG r6, 0x87D0704C;
CHECKREG r7, 0xE93788B4;
pass
|
stsp/binutils-ia16
| 2,422
|
sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_s1.s
|
//Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_s1/c_cc_flagdreg_mvbrsft_s1.dsp
// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
INIT_P_REGS 0;
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00740088;
imm32 r5, 0x609950aa;
imm32 r6, 0x20bb06cc;
imm32 r7, 0xd90e108f;
ASTAT = R0;
CC = R1; // cc2dreg
R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac
IF CC R1 = R3; // ccmov
CC = ! CC; // cc2dreg
R4.H = R1.L + R0.L (S); // dsp32alu
IF CC R3 = R2; // ccmov
CC = R0 < R1; // ccflag
R4.L = R5.L << 1; // dsp32shiftimm
IF CC R4 = R5; // ccmov
CC = R2 == R3; // ccflag
R7 = R1.L * R4.L, R6 = R1.H * R4.H; // dsp32mult
IF CC R4 = R5; // ccmov
CC = R0; // cc2dreg
A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac
IF !CC JUMP LABEL1; // branch on
CC = ! CC; // cc2dreg
P1.L = 0x3000; // ldimmhalf
IF !CC JUMP LABEL2 (BP); // branch
LABEL1:
R6 = R6 + R2;
JUMP.S END;
LABEL2:
R7 = R5 - R7;
CC = R0 < R1; // ccflag
P2 = A0.w;
IF CC JUMP END (BP); // branch
P3 = A1.w;
R5 = R5 + R7;
END:
CHECKREG r0, 0xA08D2311;
CHECKREG r1, 0x07300007;
CHECKREG r2, 0x00011557;
CHECKREG r3, 0x07300007;
CHECKREG r4, 0x609950AA;
CHECKREG r5, 0x609950AA;
CHECKREG r6, 0x056C9760;
CHECKREG r7, 0x6094E75E;
CHECKREG p1, 0x00003000;
CHECKREG p2, 0x01382894;
CHECKREG p3, 0x00000000;
imm32 r0, 0x408d2711;
imm32 r1, 0x15124040;
imm32 r2, 0x62661557;
imm32 r3, 0x073b0007;
imm32 r4, 0x01f49088;
imm32 r5, 0x6e2959aa;
imm32 r6, 0xa0b506cc;
imm32 r7, 0x00000002;
CC = R1; // cc2dreg
R2 = ROT R2 BY 1; // dsp32shiftim_rot
CC = ! CC; // cc2dreg
R3 >>= R7; // alu2op sft
R3 = ROT R0 BY -3; // dsp32shiftim_rot
CC = R0 < R1; // ccflag
R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair
R6 = ROT R4 BY 5; // dsp32shiftim_rot
CC = R2 == R3; // ccflag
P1 = R1; // regmv
IF CC R4 = R5; // ccmov
CC = R0; // cc2dreg
R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft
R7 = ROT R6 BY R7.L; // dsp32shiftim_rot
CHECKREG r0, 0x408D2711;
CHECKREG r1, 0x2ACFF368;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0xFFFC8440;
CHECKREG r4, 0x01F49088;
CHECKREG r5, 0x6E2959AA;
CHECKREG r6, 0x15BD33A8;
CHECKREG r7, 0x56F4CEA2;
CHECKREG p1, 0x15124040;
pass
|
stsp/binutils-ia16
| 4,653
|
sim/testsuite/bfin/c_logi2op_bittgl.s
|
//Original:/testcases/core/c_logi2op_bittgl/c_logi2op_bittgl.dsp
// Spec Reference: Logi2op functions: bittgl
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// bit 0-7
BITTGL( R0 , 0 ); /* r0 = 0x00000001 */
BITTGL( R1 , 1 ); /* r1 = 0x00000002 */
BITTGL( R2 , 2 ); /* r2 = 0x00000004 */
BITTGL( R3 , 3 ); /* r3 = 0x00000008 */
BITTGL( R4 , 4 ); /* r4 = 0x00000010 */
BITTGL( R5 , 5 ); /* r5 = 0x00000020 */
BITTGL( R6 , 6 ); /* r6 = 0x00000040 */
BITTGL( R7 , 7 ); /* r7 = 0x00000080 */
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000004;
CHECKREG r3, 0x00000008;
CHECKREG r4, 0x00000010;
CHECKREG r5, 0x00000020;
CHECKREG r6, 0x00000040;
CHECKREG r7, 0x00000080;
// bit 8-15
BITTGL( R0 , 8 ); /* r0 = 0x00000100 */
BITTGL( R1 , 9 ); /* r1 = 0x00000200 */
BITTGL( R2 , 10 ); /* r2 = 0x00000400 */
BITTGL( R3 , 11 ); /* r3 = 0x00000800 */
BITTGL( R4 , 12 ); /* r4 = 0x00001000 */
BITTGL( R5 , 13 ); /* r5 = 0x00002000 */
BITTGL( R6 , 14 ); /* r6 = 0x00004000 */
BITTGL( R7 , 15 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x00000101;
CHECKREG r1, 0x00000202;
CHECKREG r2, 0x00000404;
CHECKREG r3, 0x00000808;
CHECKREG r4, 0x00001010;
CHECKREG r5, 0x00002020;
CHECKREG r6, 0x00004040;
CHECKREG r7, 0x00008080;
// bit 16-23
BITTGL( R0 , 16 ); /* r0 = 0x00000100 */
BITTGL( R1 , 17 ); /* r1 = 0x00000200 */
BITTGL( R2 , 18 ); /* r2 = 0x00000400 */
BITTGL( R3 , 19 ); /* r3 = 0x00000800 */
BITTGL( R4 , 20 ); /* r4 = 0x00001000 */
BITTGL( R5 , 21 ); /* r5 = 0x00002000 */
BITTGL( R6 , 22 ); /* r6 = 0x00004000 */
BITTGL( R7 , 23 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x00010101;
CHECKREG r1, 0x00020202;
CHECKREG r2, 0x00040404;
CHECKREG r3, 0x00080808;
CHECKREG r4, 0x00101010;
CHECKREG r5, 0x00202020;
CHECKREG r6, 0x00404040;
CHECKREG r7, 0x00808080;
// bit 24-31
BITTGL( R0 , 24 ); /* r0 = 0x00000100 */
BITTGL( R1 , 25 ); /* r1 = 0x00000200 */
BITTGL( R2 , 26 ); /* r2 = 0x00000400 */
BITTGL( R3 , 27 ); /* r3 = 0x00000800 */
BITTGL( R4 , 28 ); /* r4 = 0x00001000 */
BITTGL( R5 , 29 ); /* r5 = 0x00002000 */
BITTGL( R6 , 30 ); /* r6 = 0x00004000 */
BITTGL( R7 , 31 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x01010101;
CHECKREG r1, 0x02020202;
CHECKREG r2, 0x04040404;
CHECKREG r3, 0x08080808;
CHECKREG r4, 0x10101010;
CHECKREG r5, 0x20202020;
CHECKREG r6, 0x40404040;
CHECKREG r7, 0x80808080;
// bit 0-7
BITTGL( R0 , 0 ); /* r0 = 0x00000001 */
BITTGL( R1 , 1 ); /* r1 = 0x00000002 */
BITTGL( R2 , 2 ); /* r2 = 0x00000004 */
BITTGL( R3 , 3 ); /* r3 = 0x00000008 */
BITTGL( R4 , 4 ); /* r4 = 0x00000010 */
BITTGL( R5 , 5 ); /* r5 = 0x00000020 */
BITTGL( R6 , 6 ); /* r6 = 0x00000040 */
BITTGL( R7 , 7 ); /* r7 = 0x00000080 */
CHECKREG r0, 0x01010100;
CHECKREG r1, 0x02020200;
CHECKREG r2, 0x04040400;
CHECKREG r3, 0x08080800;
CHECKREG r4, 0x10101000;
CHECKREG r5, 0x20202000;
CHECKREG r6, 0x40404000;
CHECKREG r7, 0x80808000;
// bit 8-15
BITTGL( R0 , 8 ); /* r0 = 0x00000100 */
BITTGL( R1 , 9 ); /* r1 = 0x00000200 */
BITTGL( R2 , 10 ); /* r2 = 0x00000400 */
BITTGL( R3 , 11 ); /* r3 = 0x00000800 */
BITTGL( R4 , 12 ); /* r4 = 0x00001000 */
BITTGL( R5 , 13 ); /* r5 = 0x00002000 */
BITTGL( R6 , 14 ); /* r6 = 0x00004000 */
BITTGL( R7 , 15 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x01010000;
CHECKREG r1, 0x02020000;
CHECKREG r2, 0x04040000;
CHECKREG r3, 0x08080000;
CHECKREG r4, 0x10100000;
CHECKREG r5, 0x20200000;
CHECKREG r6, 0x40400000;
CHECKREG r7, 0x80800000;
// bit 16-23
BITTGL( R0 , 16 ); /* r0 = 0x00000100 */
BITTGL( R1 , 17 ); /* r1 = 0x00000200 */
BITTGL( R2 , 18 ); /* r2 = 0x00000400 */
BITTGL( R3 , 19 ); /* r3 = 0x00000800 */
BITTGL( R4 , 20 ); /* r4 = 0x00001000 */
BITTGL( R5 , 21 ); /* r5 = 0x00002000 */
BITTGL( R6 , 22 ); /* r6 = 0x00004000 */
BITTGL( R7 , 23 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x01000000;
CHECKREG r1, 0x02000000;
CHECKREG r2, 0x04000000;
CHECKREG r3, 0x08000000;
CHECKREG r4, 0x10000000;
CHECKREG r5, 0x20000000;
CHECKREG r6, 0x40000000;
CHECKREG r7, 0x80000000;
// bit 24-31
BITTGL( R0 , 24 ); /* r0 = 0x00000100 */
BITTGL( R1 , 25 ); /* r1 = 0x00000200 */
BITTGL( R2 , 26 ); /* r2 = 0x00000400 */
BITTGL( R3 , 27 ); /* r3 = 0x00000800 */
BITTGL( R4 , 28 ); /* r4 = 0x00001000 */
BITTGL( R5 , 29 ); /* r5 = 0x00002000 */
BITTGL( R6 , 30 ); /* r6 = 0x00004000 */
BITTGL( R7 , 31 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 3,633
|
sim/testsuite/bfin/c_dsp32alu_byteop1ew.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop1ew/c_dsp32alu_byteop1ew.dsp
// Spec Reference: dsp32alu byteop1ew
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R4 = BYTEOP1P ( R1:0 , R3:2 );
R5 = BYTEOP1P ( R1:0 , R3:2 ) (R);
R6 = BYTEOP1P ( R1:0 , R3:2 ) (T);
R7 = BYTEOP1P ( R1:0 , R3:2 ) (T , R);
R0 = BYTEOP1P ( R1:0 , R3:2 ) (T , R);
CHECKREG r4, 0x25566F13;
CHECKREG r5, 0x3778911A;
CHECKREG r6, 0x24556F13;
CHECKREG r7, 0x3677911A;
CHECKREG r0, 0x3677911A;
imm32 r0, 0x1567892b;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x34445525;
imm32 r3, 0x46667727;
imm32 r4, 0x58889929;
imm32 r5, 0x6aaabb2b;
imm32 r6, 0x7cccdd2d;
imm32 r7, 0x8eeeffff;
R0 = BYTEOP1P ( R3:2 , R1:0 );
R1 = BYTEOP1P ( R3:2 , R1:0 ) (R);
R2 = BYTEOP1P ( R3:2 , R1:0 ) (T);
R3 = BYTEOP1P ( R3:2 , R1:0 ) (T , R);
R4 = BYTEOP1P ( R3:2 , R1:0 ) (T , R);
R5 = BYTEOP1P ( R3:2 , R1:0 ) (T , R);
R6 = BYTEOP1P ( R3:2 , R1:0 ) (T , R);
R7 = BYTEOP1P ( R3:2 , R1:0 ) (T , R);
CHECKREG r0, 0x25566F28;
CHECKREG r1, 0x3778912A;
CHECKREG r2, 0x2C4D6226;
CHECKREG r3, 0x3E6F8428;
CHECKREG r4, 0x3A738A29;
CHECKREG r5, 0x3A738A29;
CHECKREG r6, 0x3A738A29;
CHECKREG r7, 0x3A738A29;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r0, 0x456789ab;
imm32 r1, 0x6689abcd;
imm32 r2, 0x47445555;
imm32 r3, 0x68667777;
( R1 , R2 ) = BYTEOP16P ( R1:0 , R3:2 );
( R0 , R3 ) = BYTEOP16P ( R1:0 , R3:2 ) (R);
( R4 , R5 ) = BYTEOP16P ( R3:2 , R1:0 );
( R6 , R7 ) = BYTEOP16P ( R3:2 , R1:0 );
CHECKREG r0, 0x006800F2;
CHECKREG r1, 0x008C00AB;
CHECKREG r2, 0x00DE0100;
CHECKREG r3, 0x00770122;
CHECKREG r4, 0x00000146;
CHECKREG r5, 0x000100F2;
CHECKREG r6, 0x00000146;
CHECKREG r7, 0x000100F2;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r0, 0x456789ab;
imm32 r1, 0x6689abcd;
imm32 r2, 0x47445555;
imm32 r3, 0x68667777;
( R7 , R6 ) = BYTEOP16P ( R3:2 , R1:0 );
( R5 , R4 ) = BYTEOP16P ( R3:2 , R1:0 ) (R);
( R2 , R3 ) = BYTEOP16P ( R3:2 , R1:0 );
( R1 , R0 ) = BYTEOP16P ( R3:2 , R1:0 );
CHECKREG r0, 0x00890156;
CHECKREG r1, 0x004500F3;
CHECKREG r2, 0x008C00AB;
CHECKREG r3, 0x00DE0100;
CHECKREG r4, 0x01220144;
CHECKREG r5, 0x00CE00EF;
CHECKREG r6, 0x00DE0100;
CHECKREG r7, 0x008C00AB;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r0, 0x456789ab;
imm32 r1, 0x6689abcd;
imm32 r2, 0x47445555;
imm32 r3, 0x68667777;
( R1 , R2 ) = BYTEOP16M ( R1:0 , R3:2 );
( R0 , R3 ) = BYTEOP16M ( R1:0 , R3:2 ) (R);
( R4 , R5 ) = BYTEOP16M ( R3:2 , R1:0 );
( R6 , R7 ) = BYTEOP16M ( R3:2 , R1:0 );
CHECKREG r0, 0x00970098;
CHECKREG r1, 0xFFFE0023;
CHECKREG r2, 0x00340056;
CHECKREG r3, 0xFF89FFAC;
CHECKREG r4, 0x0000FF9D;
CHECKREG r5, 0x0000FFBE;
CHECKREG r6, 0x0000FF9D;
CHECKREG r7, 0x0000FFBE;
imm32 r0, 0x516789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x73445555;
imm32 r3, 0x84667777;
imm32 r0, 0x956789ab;
imm32 r1, 0xa689abcd;
imm32 r2, 0xb7445555;
imm32 r3, 0xc86def77;
( R7 , R6 ) = BYTEOP16M ( R3:2 , R1:0 );
( R5 , R4 ) = BYTEOP16M ( R3:2 , R1:0 ) (R);
( R2 , R3 ) = BYTEOP16M ( R3:2 , R1:0 );
( R1 , R0 ) = BYTEOP16M ( R3:2 , R1:0 );
CHECKREG r0, 0x00760032;
CHECKREG r1, 0xFF6BFFBB;
CHECKREG r2, 0x0022FFDD;
CHECKREG r3, 0xFFCCFFAA;
CHECKREG r4, 0x0044FFAA;
CHECKREG r5, 0x0022FFE4;
CHECKREG r6, 0xFFCCFFAA;
CHECKREG r7, 0x0022FFDD;
pass
|
stsp/binutils-ia16
| 9,103
|
sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln_s.s
|
//Original:/testcases/core/c_dsp32shiftim_ahalf_ln_s/c_dsp32shiftim_ahalf_ln_s.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x1000c000;
imm32 r1, 0x1000c001;
imm32 r2, 0x1000c002;
imm32 r3, 0x1000c003;
imm32 r4, 0x1000c004;
imm32 r5, 0x1000c005;
imm32 r6, 0x1000c006;
imm32 r7, 0x1000c007;
R0.L = R0.L << 1 (S);
R1.L = R1.L << 1 (S);
R2.L = R2.L << 1 (S);
R3.L = R3.L << 1 (S);
R4.L = R4.L << 1 (S);
R5.L = R5.L << 1 (S);
R6.L = R6.L << 1 (S);
R7.L = R7.L << 1 (S);
CHECKREG r0, 0x10008000;
CHECKREG r1, 0x10008002;
CHECKREG r2, 0x10008004;
CHECKREG r3, 0x10008006;
CHECKREG r4, 0x10008008;
CHECKREG r5, 0x1000800A;
CHECKREG r6, 0x1000800C;
CHECKREG r7, 0x1000800E;
imm32 r0, 0x20008001;
imm32 r1, 0x20000001;
imm32 r2, 0x2000d002;
imm32 r3, 0x2000e003;
imm32 r4, 0x2000f004;
imm32 r5, 0x2000c005;
imm32 r6, 0x2000d006;
imm32 r7, 0x2000e007;
R7.L = R0.L << 1 (S);
R6.L = R1.L << 1 (S);
R5.L = R2.L << 1 (S);
R4.L = R3.L << 1 (S);
R3.L = R4.L << 1 (S);
R2.L = R5.L << 1 (S);
R1.L = R6.L << 1 (S);
R0.L = R7.L << 1 (S);
imm32 r0, 0x3000c001;
imm32 r1, 0x3000d001;
imm32 r2, 0x3000000f;
imm32 r3, 0x3000e003;
imm32 r4, 0x3000f004;
imm32 r5, 0x3000f005;
imm32 r6, 0x3000f006;
imm32 r7, 0x3000f007;
R6.L = R0.L << 12 (S);
R7.L = R1.L << 12 (S);
R5.L = R2.L << 12 (S);
R4.L = R3.L << 12 (S);
R3.L = R4.L << 12 (S);
R2.L = R5.L << 12 (S);
R1.L = R6.L << 12 (S);
R0.L = R7.L << 12 (S);
CHECKREG r1, 0x30008000;
CHECKREG r0, 0x30008000;
CHECKREG r2, 0x30007FFF;
CHECKREG r3, 0x30008000;
CHECKREG r4, 0x30008000;
CHECKREG r5, 0x30007FFF;
CHECKREG r6, 0x30008000;
CHECKREG r7, 0x30008000;
imm32 r0, 0x40009001;
imm32 r1, 0x4000a001;
imm32 r2, 0x4000b002;
imm32 r3, 0x40000010;
imm32 r4, 0x4000c004;
imm32 r5, 0x4000d005;
imm32 r6, 0x4000e006;
imm32 r7, 0x4000f007;
R5.L = R0.L << 13 (S);
R6.L = R1.L << 13 (S);
R7.L = R2.L << 13 (S);
R0.L = R3.L << 13 (S);
R1.L = R4.L << 13 (S);
R2.L = R5.L << 13 (S);
R3.L = R6.L << 13 (S);
R4.L = R7.L << 13 (S);
CHECKREG r0, 0x40007FFF;
CHECKREG r1, 0x40008000;
CHECKREG r2, 0x40008000;
CHECKREG r3, 0x40008000;
CHECKREG r4, 0x40008000;
CHECKREG r5, 0x40008000;
CHECKREG r6, 0x40008000;
CHECKREG r7, 0x40008000;
imm32 r0, 0x00005000;
imm32 r1, 0x00015000;
imm32 r2, 0x00025000;
imm32 r3, 0x00035000;
imm32 r4, 0x00045000;
imm32 r5, 0x00055000;
imm32 r6, 0x00065000;
imm32 r7, 0x00075500;
R0.L = R0.H << 10 (S);
R1.L = R1.H << 10 (S);
R2.L = R2.H << 10 (S);
R3.L = R3.H << 10 (S);
R4.L = R4.H << 10 (S);
R5.L = R5.H << 10 (S);
R6.L = R6.H << 10 (S);
R7.L = R7.H << 10 (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010400;
CHECKREG r2, 0x00020800;
CHECKREG r3, 0x00030C00;
CHECKREG r4, 0x00041000;
CHECKREG r5, 0x00051400;
CHECKREG r6, 0x00061800;
CHECKREG r7, 0x00071C00;
imm32 r0, 0x90010000;
imm32 r1, 0x90010001;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R2.L = R0.H << 11 (S);
R3.L = R1.H << 11 (S);
R4.L = R2.H << 11 (S);
R5.L = R3.H << 11 (S);
R6.L = R4.H << 11 (S);
R7.L = R5.H << 11 (S);
R0.L = R6.H << 11 (S);
R1.L = R7.H << 11 (S);
CHECKREG r0, 0x90018000;
CHECKREG r1, 0x90018000;
CHECKREG r2, 0x90028000;
CHECKREG r3, 0x90038000;
CHECKREG r4, 0x90048000;
CHECKREG r5, 0x90058000;
CHECKREG r6, 0x90068000;
CHECKREG r7, 0x90078000;
imm32 r0, 0xa0010600;
imm32 r1, 0xa0010600;
imm32 r2, 0xa002060f;
imm32 r3, 0xa0030600;
imm32 r4, 0xa0040600;
imm32 r5, 0xa0050600;
imm32 r6, 0xa0060600;
imm32 r7, 0xa0070600;
R0.L = R0.H << 12 (S);
R1.L = R1.H << 12 (S);
R2.L = R2.H << 12 (S);
R3.L = R3.H << 12 (S);
R4.L = R4.H << 12 (S);
R5.L = R5.H << 12 (S);
R6.L = R6.H << 12 (S);
R7.L = R7.H << 12 (S);
CHECKREG r0, 0xA0018000;
CHECKREG r1, 0xA0018000;
CHECKREG r2, 0xA0028000;
CHECKREG r3, 0xA0038000;
CHECKREG r4, 0xA0048000;
CHECKREG r5, 0xA0058000;
CHECKREG r6, 0xA0068000;
CHECKREG r7, 0xA0078000;
imm32 r0, 0xc0010701;
imm32 r1, 0xc0010701;
imm32 r2, 0xc0020702;
imm32 r3, 0xc0030710;
imm32 r4, 0xc0040704;
imm32 r5, 0xc0050705;
imm32 r6, 0xc0060706;
imm32 r7, 0xc0070707;
R0.L = R0.H << 13 (S);
R1.L = R1.H << 13 (S);
R2.L = R2.H << 13 (S);
R3.L = R3.H << 13 (S);
R4.L = R4.H << 13 (S);
R5.L = R5.H << 13 (S);
R6.L = R6.H << 13 (S);
R7.L = R7.H << 13 (S);
CHECKREG r0, 0xC0018000;
CHECKREG r1, 0xC0018000;
CHECKREG r2, 0xC0028000;
CHECKREG r3, 0xC0038000;
CHECKREG r4, 0xC0048000;
CHECKREG r5, 0xC0058000;
CHECKREG r6, 0xC0068000;
CHECKREG r7, 0xC0078000;
imm32 r0, 0x00008000;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.H = R0.L << 0 (S);
R1.H = R1.L << 1 (S);
R2.H = R2.L << 2 (S);
R3.H = R3.L << 3 (S);
R4.H = R4.L << 4 (S);
R5.H = R5.L << 5 (S);
R6.H = R6.L << 6 (S);
R7.H = R7.L << 7 (S);
CHECKREG r0, 0x80008000;
CHECKREG r1, 0x80008001;
CHECKREG r2, 0x80008002;
CHECKREG r3, 0x80008003;
CHECKREG r4, 0x80008004;
CHECKREG r5, 0x80008005;
CHECKREG r6, 0x80008006;
CHECKREG r7, 0x80008007;
imm32 r0, 0x0000d001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000d003;
imm32 r4, 0x0000d004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000d007;
R2.H = R0.L << 8 (S);
R3.H = R1.L << 9 (S);
R4.H = R2.L << 10 (S);
R5.H = R3.L << 11 (S);
R6.H = R4.L << 12 (S);
R7.H = R5.L << 13 (S);
R0.H = R6.L << 14 (S);
R1.H = R7.L << 15 (S);
CHECKREG r0, 0x8000D001;
CHECKREG r1, 0x80000001;
CHECKREG r2, 0x8000D002;
CHECKREG r3, 0x0200D003;
CHECKREG r4, 0x8000D004;
CHECKREG r5, 0x8000D005;
CHECKREG r6, 0x8000D006;
CHECKREG r7, 0x8000D007;
imm32 r0, 0x0000e001;
imm32 r1, 0x0000e001;
imm32 r2, 0x0000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000e004;
imm32 r5, 0x0000e005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000e007;
R0.H = R0.L << 12 (S);
R1.H = R1.L << 12 (S);
R2.H = R2.L << 12 (S);
R3.H = R3.L << 12 (S);
R4.H = R4.L << 12 (S);
R5.H = R5.L << 12 (S);
R6.H = R6.L << 12 (S);
R7.H = R7.L << 12 (S);
CHECKREG r0, 0x8000E001;
CHECKREG r1, 0x8000E001;
CHECKREG r2, 0x7FFF000F;
CHECKREG r3, 0x8000E003;
CHECKREG r4, 0x8000E004;
CHECKREG r5, 0x8000E005;
CHECKREG r6, 0x8000E006;
CHECKREG r7, 0x8000E007;
imm32 r0, 0x0000f001;
imm32 r1, 0x0000f001;
imm32 r2, 0x0000f002;
imm32 r3, 0x00000010;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R5.H = R0.L << 13 (S);
R6.H = R1.L << 13 (S);
R7.H = R2.L << 13 (S);
R0.H = R3.L << 13 (S);
R1.H = R4.L << 13 (S);
R2.H = R5.L << 13 (S);
R3.H = R6.L << 13 (S);
R4.H = R7.L << 13 (S);
CHECKREG r0, 0x7FFFF001;
CHECKREG r1, 0x8000F001;
CHECKREG r2, 0x8000F002;
CHECKREG r3, 0x80000010;
CHECKREG r4, 0x8000F004;
CHECKREG r5, 0x8000F005;
CHECKREG r6, 0x8000F006;
CHECKREG r7, 0x8000F007;
// d_lo = ashift (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x90000000;
imm32 r1, 0x90010000;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R4.H = R0.H << 10 (S);
R5.H = R1.H << 10 (S);
R6.H = R2.H << 10 (S);
R7.H = R3.H << 10 (S);
R0.H = R4.H << 10 (S);
R1.H = R5.H << 10 (S);
R2.H = R6.H << 10 (S);
R3.H = R7.H << 10 (S);
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
imm32 r0, 0xa0010000;
imm32 r1, 0x00010001;
imm32 r2, 0xa0020000;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R7.H = R0.H << 11 (S);
R0.H = R1.H << 11 (S);
R1.H = R2.H << 11 (S);
R2.H = R3.H << 11 (S);
R3.H = R4.H << 11 (S);
R4.H = R5.H << 11 (S);
R5.H = R6.H << 11 (S);
R6.H = R7.H << 11 (S);
CHECKREG r0, 0x08000000;
CHECKREG r1, 0x80000001;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060000;
imm32 r7, 0xb0070000;
R6.H = R0.H << 12 (S);
R7.H = R1.H << 12 (S);
R0.H = R2.H << 12 (S);
R1.H = R3.H << 12 (S);
R2.H = R4.H << 12 (S);
R3.H = R5.H << 12 (S);
R4.H = R6.H << 12 (S);
R5.H = R7.H << 12 (S);
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x8000000F;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030010;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
imm32 r6, 0xd0060000;
imm32 r7, 0xd0070000;
R5.H = R0.H << 3 (S);
R6.H = R1.H << 3 (S);
R7.H = R2.H << 3 (S);
R0.H = R3.H << 3 (S);
R1.H = R4.H << 3 (S);
R2.H = R5.H << 3 (S);
R3.H = R6.H << 3 (S);
R4.H = R7.H << 3 (S);
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x80000010;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
pass
|
stsp/binutils-ia16
| 1,212
|
sim/testsuite/bfin/c_dsp32shiftim_af_s.s
|
//Original:/testcases/core/c_dsp32shiftim_af_s/c_dsp32shiftim_af_s.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: ashift saturated
imm32 r0, 0x81230001;
imm32 r1, 0x19345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x3ed6789a;
imm32 r4, 0x85d789ab;
imm32 r5, 0x967f9abc;
imm32 r6, 0xa789bbcd;
imm32 r7, 0xb891acde;
R0 = R0 << 0 (S);
R1 = R1 << 3 (S);
R2 = R2 << 7 (S);
R3 = R3 << 8 (S);
R4 = R4 << 15 (S);
R5 = R5 << 24 (S);
R6 = R6 << 31 (S);
R7 = R7 << 20 (S);
CHECKREG r0, 0x81230001;
CHECKREG r1, 0x7FFFFFFF;
CHECKREG r2, 0x7FFFFFFF;
CHECKREG r3, 0x7FFFFFFF;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
imm32 r0, 0xa1230001;
imm32 r1, 0x1e345678;
imm32 r2, 0x23f56789;
imm32 r3, 0x34db789a;
imm32 r4, 0x85a7a9ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa78dabcd;
imm32 r7, 0xb8914cde;
R6 = R0 >>> 1;
R7 = R1 >>> 3;
R0 = R2 >>> 7;
R1 = R3 >>> 8;
R2 = R4 >>> 15;
R3 = R5 >>> 24;
R4 = R6 >>> 31;
R5 = R7 >>> 20;
CHECKREG r0, 0x0047EACF;
CHECKREG r1, 0x0034DB78;
CHECKREG r2, 0xFFFF0B4F;
CHECKREG r3, 0xFFFFFF96;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0x0000003C;
CHECKREG r6, 0xD0918000;
CHECKREG r7, 0x03C68ACF;
pass
|
stsp/binutils-ia16
| 6,686
|
sim/testsuite/bfin/c_dsp32alu_rrpmmp.s
|
//Original:/testcases/core/c_dsp32alu_rrpmmp/c_dsp32alu_rrpmmp.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) amod0
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x35678911;
imm32 r1, 0x2489ab1d;
imm32 r2, 0x34545515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x67889b1d;
imm32 r2, 0x74445915;
imm32 r3, 0x86667797;
R0 = R0 +|- R0 , R7 = R0 -|+ R0;
R1 = R0 +|- R1 , R6 = R0 -|+ R1;
R2 = R0 +|- R2 , R5 = R0 -|+ R2;
R3 = R0 +|- R3 , R4 = R0 -|+ R3;
R4 = R0 +|- R4 , R3 = R0 -|+ R4;
R5 = R0 +|- R5 , R2 = R0 -|+ R5;
R6 = R0 +|- R6 , R1 = R0 -|+ R6;
R7 = R0 +|- R7 , R0 = R0 -|+ R7;
CHECKREG r0, 0xAACE1236;
CHECKREG r1, 0x67889B1D;
CHECKREG r2, 0x74445915;
CHECKREG r3, 0x86667797;
CHECKREG r4, 0xCF368869;
CHECKREG r5, 0xE158A6EB;
CHECKREG r6, 0xEE1464E3;
CHECKREG r7, 0xAACEEDCA;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34e45515;
imm32 r3, 0x466e7717;
imm32 r0, 0x5567ee1b;
imm32 r1, 0x6789abed;
imm32 r2, 0x7444551e;
imm32 r3, 0x86e67777;
R0 = R1 +|- R0 , R7 = R1 -|+ R0;
R1 = R1 +|- R1 , R6 = R1 -|+ R1;
R2 = R1 +|- R2 , R5 = R1 -|+ R2;
R3 = R1 +|- R3 , R4 = R1 -|+ R3;
R4 = R1 +|- R4 , R3 = R1 -|+ R4;
R5 = R1 +|- R5 , R2 = R1 -|+ R5;
R6 = R1 +|- R6 , R1 = R1 -|+ R6;
R7 = R1 +|- R7 , R0 = R1 -|+ R7;
CHECKREG r0, 0xBCF0F1E2;
CHECKREG r1, 0xCF1257DA;
CHECKREG r2, 0x7444551E;
CHECKREG r3, 0x86E67777;
CHECKREG r4, 0x173E8889;
CHECKREG r5, 0x29E0AAE2;
CHECKREG r6, 0xCF12A826;
CHECKREG r7, 0xE134BDD2;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0x86667777;
R0 = R2 +|- R0 , R7 = R2 -|+ R0;
R1 = R2 +|- R1 , R6 = R2 -|+ R1;
R2 = R2 +|- R2 , R5 = R2 -|+ R2;
R3 = R2 +|- R3 , R4 = R2 -|+ R3;
R4 = R2 +|- R4 , R3 = R2 -|+ R4;
R5 = R2 +|- R5 , R2 = R2 -|+ R5;
R6 = R2 +|- R6 , R1 = R2 -|+ R6;
R7 = R2 +|- R7 , R0 = R2 -|+ R7;
CHECKREG r0, 0xC9AB885A;
CHECKREG r1, 0xDBCDAA5C;
CHECKREG r2, 0xE888AA2A;
CHECKREG r3, 0x86667777;
CHECKREG r4, 0x4AAA8889;
CHECKREG r5, 0xE88855D6;
CHECKREG r6, 0xF543A9F8;
CHECKREG r7, 0x0765CBFA;
imm32 r0, 0x85678911;
imm32 r1, 0x2889ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5587891b;
imm32 r1, 0x6788ab1d;
imm32 r2, 0x74448515;
imm32 r3, 0x86667877;
R0 = R3 +|- R0 , R7 = R3 -|+ R0;
R1 = R3 +|- R1 , R6 = R3 -|+ R1;
R2 = R3 +|- R2 , R5 = R3 -|+ R2;
R3 = R3 +|- R3 , R4 = R3 -|+ R3;
R4 = R3 +|- R4 , R3 = R3 -|+ R4;
R5 = R3 +|- R5 , R2 = R3 -|+ R5;
R6 = R3 +|- R6 , R1 = R3 -|+ R6;
R7 = R3 +|- R7 , R0 = R3 -|+ R7;
CHECKREG r0, 0xDBEDF280;
CHECKREG r1, 0xEDEE1482;
CHECKREG r2, 0xFAAAEE7A;
CHECKREG r3, 0x0CCCF0EE;
CHECKREG r4, 0x0CCC0F12;
CHECKREG r5, 0x1EEEF362;
CHECKREG r6, 0x2BAACD5A;
CHECKREG r7, 0x3DABEF5C;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0x86667777;
R0 = R4 +|- R0 , R7 = R4 -|+ R0;
R1 = R4 +|- R1 , R6 = R4 -|+ R1;
R2 = R4 +|- R2 , R5 = R4 -|+ R2;
R3 = R4 +|- R3 , R4 = R4 -|+ R3;
R4 = R4 +|- R4 , R3 = R4 -|+ R4;
R5 = R4 +|- R5 , R2 = R4 -|+ R5;
R6 = R4 +|- R6 , R1 = R4 -|+ R6;
R7 = R4 +|- R7 , R0 = R4 -|+ R7;
CHECKREG r0, 0x5567982D;
CHECKREG r1, 0x6789BA2F;
CHECKREG r2, 0x74446427;
CHECKREG r3, 0x00000D12;
CHECKREG r4, 0x0CCC0000;
CHECKREG r5, 0xA5549BD9;
CHECKREG r6, 0xB20F45D1;
CHECKREG r7, 0xC43167D3;
imm32 r0, 0x95678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x39445515;
imm32 r3, 0x46967717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74495515;
imm32 r3, 0x86669777;
R0 = R5 +|- R0 , R7 = R5 -|+ R0;
R1 = R5 +|- R1 , R6 = R5 -|+ R1;
R2 = R5 +|- R2 , R5 = R5 -|+ R2;
R3 = R5 +|- R3 , R4 = R5 -|+ R3;
R4 = R5 +|- R4 , R3 = R5 -|+ R4;
R5 = R5 +|- R5 , R2 = R5 -|+ R5;
R6 = R5 +|- R6 , R1 = R5 -|+ R6;
R7 = R5 +|- R7 , R0 = R5 -|+ R7;
CHECKREG r0, 0x122924F4;
CHECKREG r1, 0x244B46F6;
CHECKREG r2, 0x0000E1DC;
CHECKREG r3, 0x86667953;
CHECKREG r4, 0xDBB06889;
CHECKREG r5, 0x62160000;
CHECKREG r6, 0x9FE1B90A;
CHECKREG r7, 0xB203DB0C;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0x86667777;
R0 = R6 +|- R0 , R7 = R6 -|+ R0;
R1 = R6 +|- R1 , R6 = R6 -|+ R1;
R2 = R6 +|- R2 , R5 = R6 -|+ R2;
R3 = R6 +|- R3 , R4 = R6 -|+ R3;
R4 = R6 +|- R4 , R3 = R6 -|+ R4;
R5 = R6 +|- R5 , R2 = R6 -|+ R5;
R6 = R6 +|- R6 , R1 = R6 -|+ R6;
R7 = R6 +|- R7 , R0 = R6 -|+ R7;
CHECKREG r0, 0x26364225;
CHECKREG r1, 0x0000C84E;
CHECKREG r2, 0x74441D63;
CHECKREG r3, 0x86663FC5;
CHECKREG r4, 0xEA4A8889;
CHECKREG r5, 0xFC6CAAEB;
CHECKREG r6, 0x70B00000;
CHECKREG r7, 0xBB2ABDDB;
imm32 r0, 0x67898911;
imm32 r1, 0xb789ab1d;
imm32 r2, 0x3b445515;
imm32 r3, 0x46b67717;
imm32 r0, 0x5567891b;
imm32 r1, 0x678bab1d;
imm32 r2, 0x7444b515;
imm32 r3, 0x86667b77;
R0 = R7 +|- R0 , R7 = R7 -|+ R0;
R1 = R7 +|- R1 , R6 = R7 -|+ R1;
R2 = R7 +|- R2 , R5 = R7 -|+ R2;
R3 = R7 +|- R3 , R4 = R7 -|+ R3;
R4 = R7 +|- R4 , R3 = R7 -|+ R4;
R5 = R7 +|- R5 , R2 = R7 -|+ R5;
R6 = R7 +|- R6 , R1 = R7 -|+ R6;
R7 = R7 +|- R7 , R0 = R7 -|+ R7;
CHECKREG r0, 0x00008DEC;
CHECKREG r1, 0x678B3909;
CHECKREG r2, 0x74444301;
CHECKREG r3, 0x86660963;
CHECKREG r4, 0x45208489;
CHECKREG r5, 0x57424AEB;
CHECKREG r6, 0x63FB54E3;
CHECKREG r7, 0xCB860000;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34ee5515;
imm32 r3, 0x4666e717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ae1d;
imm32 r2, 0x744455e5;
imm32 r3, 0x8666777e;
R4 = R2 +|- R5 , R3 = R2 -|+ R5 (S);
R0 = R5 +|- R3 , R5 = R5 -|+ R3 (CO);
R2 = R6 +|- R2 , R0 = R6 -|+ R2 (SCO);
R3 = R4 +|- R0 , R2 = R4 -|+ R0 (S);
R7 = R7 +|- R6 , R6 = R7 -|+ R6 (CO);
R6 = R1 +|- R7 , R1 = R1 -|+ R7 (SCO);
R5 = R0 +|- R4 , R7 = R0 -|+ R4 (S);
R1 = R3 +|- R1 , R4 = R3 -|+ R1 (CO);
CHECKREG r0, 0x7FFFEFB7;
CHECKREG r1, 0xFFFFE33B;
CHECKREG r2, 0x0000FAB1;
CHECKREG r3, 0x7FFF1B43;
CHECKREG r4, 0x534BFFFF;
CHECKREG r5, 0x7FFFE4BD;
CHECKREG r6, 0x7FFF0300;
CHECKREG r7, 0x0000FAB1;
imm32 r0, 0xff678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3f445515;
imm32 r3, 0x46f67717;
imm32 r0, 0x556f891b;
imm32 r1, 0x6789fb1d;
imm32 r2, 0x74445f15;
imm32 r3, 0x866677f7;
R4 = R3 +|- R3 , R5 = R3 -|+ R3 (SCO);
R1 = R6 +|- R1 , R6 = R6 -|+ R1 (SCO);
R6 = R1 +|- R4 , R4 = R1 -|+ R4 (S);
R7 = R4 +|- R2 , R0 = R4 -|+ R2 (S);
R2 = R2 +|- R6 , R1 = R2 -|+ R6 (CO);
R3 = R5 +|- R5 , R7 = R5 -|+ R5 (CO);
R5 = R7 +|- R7 , R3 = R7 -|+ R7 (SCO);
R0 = R0 +|- R0 , R2 = R0 -|+ R0 (SCO);
CHECKREG r0, 0x17760000;
CHECKREG r1, 0x66F87445;
CHECKREG r2, 0x7FFF0000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x7FFF07E3;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0xFFFF07E3;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 4,740
|
sim/testsuite/bfin/s21.s
|
// Test A0 = ROT (A0 by imm6);
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
A0 = A1 = 0;
// rot
// left by 1
// 00 8000 0001 -> 01 0000 0002 cc=0
R0.L = 0x0001;
R0.H = 0x8000;
R7 = 0;
CC = R7;
A1 = A0 = 0;
A0.w = R0;
A0 = ROT A0 BY 1;
R1 = A0.w;
DBGA ( R1.L , 0x0002 );
DBGA ( R1.H , 0x0000 );
R1.L = A0.x;
DBGA ( R1.L , 0x0001 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// left by 1
// 80 0000 0001 -> 00 0000 0002 cc=1
R7 = 0;
CC = R7;
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0080;
A1 = A0 = 0;
A0.w = R0;
A0.x = R1.L;
A0 = ROT A0 BY 1;
R1 = A0.w;
DBGA ( R1.L , 0x0002 );
DBGA ( R1.H , 0x0000 );
R1.L = A0.x;
DBGA ( R1.L , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
// rot
// left by 1 with cc=1
// 80 8000 0001 -> 01 0000 0003 cc=1
R7 = 1;
CC = R7;
R0.L = 0x0001;
R0.H = 0x8000;
R1.L = 0x0080;
A1 = A0 = 0;
A0.w = R0;
A0.x = R1.L;
A0 = ROT A0 BY 1;
R1 = A0.w;
DBGA ( R1.L , 0x0003 );
DBGA ( R1.H , 0x0000 );
R1.L = A0.x;
DBGA ( R1.L , 0x0001 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
// rot
// left by 2 with cc=1
// 80 0000 0001 -> 00 0000 0007 cc=0
R7 = 1;
CC = R7;
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0080;
A1 = A0 = 0;
A0.w = R0;
A0.x = R1.L;
A0 = ROT A0 BY 2;
R1 = A0.w;
DBGA ( R1.L , 0x0007 );
DBGA ( R1.H , 0x0000 );
R1.L = A0.x;
DBGA ( R1.L , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// left by 3 with cc=0
R7 = 0;
CC = R7;
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0080;
A1 = A0 = 0;
A0.w = R0;
A0.x = R1.L;
A0 = ROT A0 BY 3;
R1 = A0.w;
DBGA ( R1.L , 0x000a );
DBGA ( R1.H , 0x0000 );
R1.L = A0.x;
DBGA ( R1.L , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// left by largest positive magnitude of 31
// 80 0000 0001 -> 00 a000 0000 cc=0
R7 = 0;
CC = R7;
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0080;
A1 = A0 = 0;
A0.w = R0;
A0.x = R1.L;
A0 = ROT A0 BY 31;
R1 = A0.w;
DBGA ( R1.L , 0x0000 );
DBGA ( R1.H , 0xa000 );
R1.L = A0.x;
DBGA ( R1.L , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// right by 1
// 80 0000 0001 -> 40 0000 0000 cc=1
R7 = 0;
CC = R7;
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0080;
A1 = A0 = 0;
A0.w = R0;
A0.x = R1.L;
A0 = ROT A0 BY -1;
R1 = A0.w;
DBGA ( R1.L , 0x0000 );
DBGA ( R1.H , 0x0000 );
R1.L = A0.x;
DBGA ( R1.L , 0x0040 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
// rot
// right by 1
// 80 0000 0001 -> c0 0000 0000 cc=1
R7 = 1;
CC = R7;
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0080;
A1 = A0 = 0;
A0.w = R0;
A0.x = R1.L;
A0 = ROT A0 BY -1;
R1 = A0.w;
DBGA ( R1.L , 0x0000 );
DBGA ( R1.H , 0x0000 );
R1.L = A0.x;
DBGA ( R1.L , 0xffc0 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
// rot
// right by 2
// 80 0000 0001 -> e0 0000 0000 cc=0
R7 = 1;
CC = R7;
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0080;
A1 = A0 = 0;
A0.w = R0;
A0.x = R1.L;
A0 = ROT A0 BY -2;
R1 = A0.w;
DBGA ( R1.L , 0x0000 );
DBGA ( R1.H , 0x0000 );
R1.L = A0.x;
DBGA ( R1.L , 0xffe0 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// right by 9
// 80 0000 0001 -> 01 c000 0000 cc=0
R7 = 1;
CC = R7;
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0080;
A1 = A0 = 0;
A0.w = R0;
A0.x = R1.L;
A0 = ROT A0 BY -9;
R1 = A0.w;
DBGA ( R1.L , 0x0000 );
DBGA ( R1.H , 0xc000 );
R1.L = A0.x;
DBGA ( R1.L , 0x0001 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// right by 9 with reg
// 80 0000 0001 -> 01 c000 0000 cc=0
R7 = 1;
CC = R7;
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0080;
A1 = A0 = 0;
A0.w = R0;
A0.x = R1.L;
R5 = -9;
A0 = ROT A0 BY R5.L;
R1 = A0.w;
DBGA ( R1.L , 0x0000 );
DBGA ( R1.H , 0xc000 );
R1.L = A0.x;
DBGA ( R1.L , 0x0001 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot left by 4 with cc=1
R0.L = 0x789a;
R0.H = 0x3456;
A0.w = R0;
R0.L = 0x12;
A0.x = R0;
R0 = 1;
CC = R0;
A0 = ROT A0 BY 4;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x4567 ); DBGA ( R4.L , 0x89a8 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0023 );
// rot left by 28 with cc=1
R0.L = 0x789a;
R0.H = 0x3456;
A0.w = R0;
R0.L = 0x12;
A0.x = R0;
R0 = 1;
CC = R0;
A0 = ROT A0 BY 28;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xa891 ); DBGA ( R4.L , 0xa2b3 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff89 );
// rot right by 4 with cc=1
R0.L = 0x789a;
R0.H = 0x3456;
A0.w = R0;
R0.L = 0x12;
A0.x = R0;
R0 = 1;
CC = R0;
A0 = ROT A0 BY -4;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x2345 ); DBGA ( R4.L , 0x6789 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0051 );
// rot right by 8 with cc=1
R0.L = 0x789a;
R0.H = 0x3456;
A0.w = R0;
R0.L = 0x12;
A0.x = R0;
R0 = 1;
CC = R0;
A0 = ROT A0 BY -28;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xcf13 ); DBGA ( R4.L , 0x5123 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff8a );
pass
|
stsp/binutils-ia16
| 4,049
|
sim/testsuite/bfin/random_0034.S
|
# Verify sign extension behavior with simultaneous acc additions, and
# verify that no ASTAT bits get changed as a result
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ);
dmm32 A0.w, 0x589145b7;
dmm32 A0.x, 0xffffffee;
dmm32 A1.w, 0x0b247b05;
dmm32 A1.x, 0x0000005a;
imm32 R3, 0x1e414332;
imm32 R4, 0x351715b7;
R3 = A1.L + A1.H, R4 = A0.L + A0.H;
checkreg R3, 0x00008629;
checkreg R4, 0x00009e48;
checkreg ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ);
dmm32 ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0xb2c58001;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xe999dc28;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0xe58d5ffa;
imm32 R4, 0x7fff7fff;
R0 = A1.L + A1.H, R4 = A0.L + A0.H;
checkreg R0, 0xffffc5c1;
checkreg R4, 0xffff32c6;
checkreg ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC);
dmm32 A0.w, 0xeff48350;
dmm32 A0.x, 0xffffffff;
dmm32 A1.w, 0x5a3f623a;
dmm32 A1.x, 0xffffffff;
imm32 R4, 0xffff152f;
imm32 R6, 0xdd13218a;
R4 = A1.L + A1.H, R6 = A0.L + A0.H;
checkreg R4, 0x0000bc79;
checkreg R6, 0xffff7344;
checkreg ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC);
dmm32 ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN);
dmm32 A0.w, 0x6da679bb;
dmm32 A0.x, 0xffffff96;
dmm32 A1.w, 0x1f5fb024;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x3ebf8000;
imm32 R6, 0x025f2e8c;
R6 = A1.L + A1.H, R3 = A0.L + A0.H;
checkreg R3, 0x0000e761;
checkreg R6, 0xffffcf83;
checkreg ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ);
dmm32 A0.w, 0x59abaa84;
dmm32 A0.x, 0xffffffe1;
dmm32 A1.w, 0x71541efe;
dmm32 A1.x, 0x00000009;
imm32 R0, 0x2c41e797;
imm32 R5, 0x7bfa5e8a;
R0 = A1.L + A1.H, R5 = A0.L + A0.H;
checkreg R0, 0x00009052;
checkreg R5, 0x0000042f;
checkreg ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN);
dmm32 A0.w, 0xffffffff;
dmm32 A0.x, 0xffffffff;
dmm32 A1.w, 0xc49ca8db;
dmm32 A1.x, 0xffffffff;
imm32 R3, 0x0f62ffff;
imm32 R4, 0x09505188;
R4 = A1.L + A1.H, R3 = A0.L + A0.H;
checkreg R3, 0xfffffffe;
checkreg R4, 0xffff6d77;
checkreg ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN);
dmm32 ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ);
dmm32 A0.w, 0xd827823e;
dmm32 A0.x, 0xffffffff;
dmm32 A1.w, 0x303d11ba;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x80007fff;
imm32 R6, 0xffc4feb3;
R6 = A1.L + A1.H, R1 = A0.L + A0.H;
checkreg R1, 0xffff5a65;
checkreg R6, 0x000041f7;
checkreg ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ);
dmm32 ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN);
dmm32 A0.w, 0x97049850;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xffffa014;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0x04828378;
imm32 R5, 0x3d9effff;
R0 = A1.L + A1.H, R5 = A0.L + A0.H;
checkreg R0, 0xffffa013;
checkreg R5, 0xffff2f54;
checkreg ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN);
dmm32 ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ);
dmm32 A0.w, 0xac43c455;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0x03de6f39;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x5bbfd2d1;
imm32 R3, 0x22425ebc;
R3 = A1.L + A1.H, R0 = A0.L + A0.H;
checkreg R0, 0xffff7098;
checkreg R3, 0x00007317;
checkreg ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ);
dmm32 ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0xb63ac8f5;
dmm32 A0.x, 0xffffffe0;
dmm32 A1.w, 0x358b94e8;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x80007fff;
imm32 R6, 0x4f4a8883;
R6 = A1.L + A1.H, R1 = A0.L + A0.H;
checkreg R1, 0xffff7f2f;
checkreg R6, 0xffffca73;
checkreg ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
pass
|
stsp/binutils-ia16
| 9,304
|
sim/testsuite/bfin/c_dsp32shift_lf.s
|
//Original:/testcases/core/c_dsp32shift_lf/c_dsp32shift_lf.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : mix data, count (+)= (half reg)
// d_reg = lshift (d BY d_lo)
// Rx by RLx
imm32 r0, 0x01210001;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bcde;
R7 = LSHIFT R0 BY R0.L;
R6 = LSHIFT R1 BY R0.L;
R0 = LSHIFT R2 BY R0.L;
R1 = LSHIFT R3 BY R0.L;
R2 = LSHIFT R4 BY R0.L;
R3 = LSHIFT R5 BY R0.L;
R4 = LSHIFT R6 BY R0.L;
R5 = LSHIFT R7 BY R0.L;
CHECKREG r0, 0x4682CF12;
CHECKREG r1, 0xE2680000;
CHECKREG r2, 0x26AC0000;
CHECKREG r3, 0x6AF00000;
CHECKREG r4, 0xB3C00000;
CHECKREG r5, 0x00080000;
CHECKREG r6, 0x2462ACF0;
CHECKREG r7, 0x02420002;
imm32 r0, 0x01220002;
imm32 r1, 0x12325678;
imm32 r2, 0x23426789;
imm32 r3, 0x3452789a;
imm32 r4, 0x956289ab;
imm32 r5, 0xa6729abc;
imm32 r6, 0xb782abcd;
imm32 r7, 0xc892bcde;
R1.L = 2;
R3 = LSHIFT R0 BY R1.L;
R4 = LSHIFT R1 BY R1.L;
R5 = LSHIFT R2 BY R1.L;
R6 = LSHIFT R3 BY R1.L;
R7 = LSHIFT R4 BY R1.L;
R0 = LSHIFT R5 BY R1.L;
R1 = LSHIFT R6 BY R1.L;
R2 = LSHIFT R7 BY R1.L;
CHECKREG r0, 0x34267890;
CHECKREG r1, 0x48800080;
CHECKREG r2, 0x23200020;
CHECKREG r3, 0x04880008;
CHECKREG r4, 0x48C80008;
CHECKREG r5, 0x8D099E24;
CHECKREG r6, 0x12200020;
CHECKREG r7, 0x23200020;
imm32 r0, 0x01230002;
imm32 r1, 0x12335678;
imm32 r2, 0x23436789;
imm32 r3, 0x3453789a;
imm32 r4, 0x456389ab;
imm32 r5, 0x56739abc;
imm32 r6, 0x6783abcd;
imm32 r7, 0x789abcde;
R2 = 14;
R0 = LSHIFT R4 BY R2.L;
R1 = LSHIFT R5 BY R2.L;
R2 = LSHIFT R6 BY R2.L;
R3 = LSHIFT R7 BY R2.L;
CHECKREG r0, 0xE26AC000;
CHECKREG r1, 0xE6AF0000;
CHECKREG r2, 0xEAF34000;
CHECKREG r3, 0x789ABCDE;
imm32 r0, 0x01240002;
imm32 r1, 0x12345678;
imm32 r2, 0x23446789;
imm32 r3, 0x3454789a;
imm32 r4, 0xa56489ab;
imm32 r5, 0xb6749abc;
imm32 r6, 0xc784abcd;
imm32 r7, 0xd894bcde;
R3.L = 15;
R4 = LSHIFT R0 BY R3.L;
R5 = LSHIFT R1 BY R3.L;
R6 = LSHIFT R2 BY R3.L;
R7 = LSHIFT R3 BY R3.L;
R0 = LSHIFT R4 BY R3.L;
R1 = LSHIFT R5 BY R3.L;
R2 = LSHIFT R6 BY R3.L;
R3 = LSHIFT R7 BY R3.L;
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x40000000;
CHECKREG r3, 0xC0000000;
CHECKREG r4, 0x00010000;
CHECKREG r5, 0x2B3C0000;
CHECKREG r6, 0x33C48000;
CHECKREG r7, 0x00078000;
imm32 r0, 0x01250002;
imm32 r1, 0x12355678;
imm32 r2, 0x23456789;
imm32 r3, 0x3455789a;
imm32 r4, 0x456589ab;
imm32 r5, 0x56759abc;
imm32 r6, 0x6785abcd;
imm32 r7, 0x7895bcde;
R4.L = -1;
R7 = LSHIFT R0 BY R4.L;
R6 = LSHIFT R1 BY R4.L;
R5 = LSHIFT R2 BY R4.L;
R3 = LSHIFT R4 BY R4.L;
R2 = LSHIFT R5 BY R4.L;
R1 = LSHIFT R6 BY R4.L;
R0 = LSHIFT R7 BY R4.L;
R4 = LSHIFT R3 BY R4.L;
CHECKREG r0, 0x00494000;
CHECKREG r1, 0x048D559E;
CHECKREG r2, 0x08D159E2;
CHECKREG r3, 0x22B2FFFF;
CHECKREG r4, 0x11597FFF;
CHECKREG r5, 0x11A2B3C4;
CHECKREG r6, 0x091AAB3C;
CHECKREG r7, 0x00928001;
imm32 r0, 0x01260002;
imm32 r1, 0x82365678;
imm32 r2, 0x93466789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56689ab;
imm32 r5, 0xc6769abc;
imm32 r6, 0xd786abcd;
imm32 r7, 0xe896bcde;
R5.L = -8;
R6 = LSHIFT R0 BY R5.L;
R7 = LSHIFT R1 BY R5.L;
R0 = LSHIFT R2 BY R5.L;
R1 = LSHIFT R3 BY R5.L;
R2 = LSHIFT R4 BY R5.L;
R3 = LSHIFT R5 BY R5.L;
R4 = LSHIFT R6 BY R5.L;
R5 = LSHIFT R7 BY R5.L;
CHECKREG r0, 0x00934667;
CHECKREG r1, 0x00A45678;
CHECKREG r2, 0x00B56689;
CHECKREG r3, 0x00C676FF;
CHECKREG r4, 0x00000126;
CHECKREG r5, 0x00008236;
CHECKREG r6, 0x00012600;
CHECKREG r7, 0x00823656;
imm32 r0, 0x01270002;
imm32 r1, 0x12375678;
imm32 r2, 0x23476789;
imm32 r3, 0x3457789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56779abc;
imm32 r6, 0x6787abcd;
imm32 r7, 0x7897bcde;
R6.L = -15;
R7 = LSHIFT R0 BY R6.L;
R0 = LSHIFT R1 BY R6.L;
R1 = LSHIFT R2 BY R6.L;
R2 = LSHIFT R3 BY R6.L;
R3 = LSHIFT R4 BY R6.L;
R4 = LSHIFT R5 BY R6.L;
R5 = LSHIFT R6 BY R6.L;
R6 = LSHIFT R7 BY R6.L;
CHECKREG r0, 0x0000246E;
CHECKREG r1, 0x0000468E;
CHECKREG r2, 0x000068AE;
CHECKREG r3, 0x00008ACF;
CHECKREG r4, 0x0000ACEF;
CHECKREG r5, 0x0000CF0F;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x0000024E;
imm32 r0, 0x01280002;
imm32 r1, 0x82385678;
imm32 r2, 0x93486789;
imm32 r3, 0xa458789a;
imm32 r4, 0xb56889ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd788abcd;
imm32 r7, 0xe898bcde;
R7.L = -16;
R0 = LSHIFT R0 BY R7.L;
R1 = LSHIFT R1 BY R7.L;
R2 = LSHIFT R2 BY R7.L;
R3 = LSHIFT R3 BY R7.L;
R4 = LSHIFT R4 BY R7.L;
R5 = LSHIFT R5 BY R7.L;
R6 = LSHIFT R6 BY R7.L;
R7 = LSHIFT R7 BY R7.L;
CHECKREG r0, 0x00000128;
CHECKREG r1, 0x00008238;
CHECKREG r2, 0x00009348;
CHECKREG r3, 0x0000A458;
CHECKREG r4, 0x0000B568;
CHECKREG r5, 0x0000C678;
CHECKREG r6, 0x0000D788;
CHECKREG r7, 0x0000E898;
imm32 r0, 0x81290002;
imm32 r1, 0x92395678;
imm32 r2, 0xa3496789;
imm32 r3, 0xb459789a;
imm32 r4, 0xc56989ab;
imm32 r5, 0xd6799abc;
imm32 r6, 0xe789abcd;
imm32 r7, 0xf899bcde;
R0.L = 4;
//r0 = lshift (r0 by rl0);
R1 = LSHIFT R1 BY R0.L;
R2 = LSHIFT R2 BY R0.L;
R3 = LSHIFT R3 BY R0.L;
R4 = LSHIFT R4 BY R0.L;
R5 = LSHIFT R5 BY R0.L;
R6 = LSHIFT R6 BY R0.L;
R7 = LSHIFT R7 BY R0.L;
CHECKREG r1, 0x23956780;
CHECKREG r2, 0x34967890;
CHECKREG r3, 0x459789A0;
CHECKREG r4, 0x56989AB0;
CHECKREG r5, 0x6799ABC0;
CHECKREG r6, 0x789ABCD0;
CHECKREG r7, 0x899BCDE0;
imm32 r0, 0x012a0002;
imm32 r1, 0x123a5678;
imm32 r2, 0x234a6789;
imm32 r3, 0x345a789a;
imm32 r4, 0x456a89ab;
imm32 r5, 0x567a9abc;
imm32 r6, 0x678aabcd;
imm32 r7, 0xf89abcde;
R1.L = 2;
R7 = LSHIFT R0 BY R1.L;
R6 = LSHIFT R1 BY R1.L;
R5 = LSHIFT R2 BY R1.L;
R4 = LSHIFT R3 BY R1.L;
R3 = LSHIFT R4 BY R1.L;
R2 = LSHIFT R5 BY R1.L;
R0 = LSHIFT R6 BY R1.L;
R1 = LSHIFT R7 BY R1.L;
CHECKREG r0, 0x23A00020;
CHECKREG r1, 0x12A00020;
CHECKREG r2, 0x34A67890;
CHECKREG r3, 0x45A789A0;
CHECKREG r4, 0xD169E268;
CHECKREG r5, 0x8D299E24;
CHECKREG r6, 0x48E80008;
CHECKREG r7, 0x04A80008;
imm32 r0, 0x012b0002;
imm32 r1, 0x123b5678;
imm32 r2, 0x234b6789;
imm32 r3, 0x345b789a;
imm32 r4, 0x456b89ab;
imm32 r5, 0x567b9abc;
imm32 r6, 0x678babcd;
imm32 r7, 0x789bbcde;
R2.L = 15;
R0 = LSHIFT R0 BY R2.L;
R1 = LSHIFT R1 BY R2.L;
R3 = LSHIFT R3 BY R2.L;
R4 = LSHIFT R4 BY R2.L;
R5 = LSHIFT R5 BY R2.L;
R6 = LSHIFT R6 BY R2.L;
R7 = LSHIFT R7 BY R2.L;
R2 = LSHIFT R2 BY R2.L;
CHECKREG r0, 0x80010000;
CHECKREG r1, 0xAB3C0000;
CHECKREG r2, 0x80078000;
CHECKREG r3, 0xBC4D0000;
CHECKREG r4, 0xC4D58000;
CHECKREG r5, 0xCD5E0000;
CHECKREG r6, 0xD5E68000;
CHECKREG r7, 0xDE6F0000;
imm32 r0, 0x012c0002;
imm32 r1, 0x123c5678;
imm32 r2, 0x234c6789;
imm32 r3, 0x345c789a;
imm32 r4, 0x456c89ab;
imm32 r5, 0x567c9abc;
imm32 r6, 0x678cabcd;
imm32 r7, 0x789cbcde;
R3.L = 16;
R0 = LSHIFT R0 BY R3.L;
R1 = LSHIFT R1 BY R3.L;
R2 = LSHIFT R2 BY R3.L;
R4 = LSHIFT R4 BY R3.L;
R5 = LSHIFT R5 BY R3.L;
R6 = LSHIFT R6 BY R3.L;
R7 = LSHIFT R7 BY R3.L;
R3 = LSHIFT R3 BY R3.L;
CHECKREG r0, 0x00020000;
CHECKREG r1, 0x56780000;
CHECKREG r2, 0x67890000;
CHECKREG r3, 0x00100000;
CHECKREG r4, 0x89AB0000;
CHECKREG r5, 0x9ABC0000;
CHECKREG r6, 0xABCD0000;
CHECKREG r7, 0xBCDE0000;
imm32 r0, 0x012d0002;
imm32 r1, 0x123d5678;
imm32 r2, 0x234d6789;
imm32 r3, 0x345d789a;
imm32 r4, 0x456d89ab;
imm32 r5, 0x567d9abc;
imm32 r6, 0x678dabcd;
imm32 r7, 0x789dbcde;
R4.L = -9;
R7 = LSHIFT R0 BY R4.L;
R0 = LSHIFT R1 BY R4.L;
R1 = LSHIFT R2 BY R4.L;
R2 = LSHIFT R3 BY R4.L;
//r4 = lshift (r4 by rl4);
R3 = LSHIFT R5 BY R4.L;
R5 = LSHIFT R6 BY R4.L;
R6 = LSHIFT R7 BY R4.L;
CHECKREG r0, 0x00091EAB;
CHECKREG r1, 0x0011A6B3;
CHECKREG r2, 0x001A2EBC;
CHECKREG r3, 0x002B3ECD;
CHECKREG r4, 0x456DFFF7;
CHECKREG r5, 0x0033C6D5;
CHECKREG r6, 0x0000004B;
CHECKREG r7, 0x00009680;
imm32 r0, 0x012e0002;
imm32 r1, 0x123e5678;
imm32 r2, 0x234e6789;
imm32 r3, 0x345e789a;
imm32 r4, 0x456e89ab;
imm32 r5, 0x567e9abc;
imm32 r6, 0x678eabcd;
imm32 r7, 0x789ebcde;
R5.L = -14;
R0 = LSHIFT R0 BY R5.L;
R1 = LSHIFT R1 BY R5.L;
R2 = LSHIFT R2 BY R5.L;
R3 = LSHIFT R3 BY R5.L;
R4 = LSHIFT R4 BY R5.L;
//r5 = lshift (r5 by rl5);
R6 = LSHIFT R6 BY R5.L;
R7 = LSHIFT R7 BY R5.L;
CHECKREG r0, 0x000004B8;
CHECKREG r1, 0x000048F9;
CHECKREG r2, 0x00008D39;
CHECKREG r3, 0x0000D179;
CHECKREG r4, 0x000115BA;
CHECKREG r5, 0x567EFFF2;
CHECKREG r6, 0x00019E3A;
CHECKREG r7, 0x0001E27A;
imm32 r0, 0x012f0002;
imm32 r1, 0x623f5678;
imm32 r2, 0x734f6789;
imm32 r3, 0x845f789a;
imm32 r4, 0x956f89ab;
imm32 r5, 0xa67f9abc;
imm32 r6, 0xc78fabcd;
imm32 r7, 0xd89fbcde;
R6.L = -15;
R0 = LSHIFT R0 BY R6.L;
R1 = LSHIFT R1 BY R6.L;
R2 = LSHIFT R2 BY R6.L;
R3 = LSHIFT R3 BY R6.L;
R4 = LSHIFT R4 BY R6.L;
R5 = LSHIFT R5 BY R6.L;
//r6 = lshift (r6 by rl6);
R7 = LSHIFT R7 BY R6.L;
CHECKREG r0, 0x0000025E;
CHECKREG r1, 0x0000C47E;
CHECKREG r2, 0x0000E69E;
CHECKREG r3, 0x000108BE;
CHECKREG r4, 0x00012ADF;
CHECKREG r5, 0x00014CFF;
CHECKREG r6, 0xC78FFFF1;
CHECKREG r7, 0x0001B13F;
imm32 r0, 0x71230072;
imm32 r1, 0x82345678;
imm32 r2, 0x93456779;
imm32 r3, 0xa456787a;
imm32 r4, 0xb567897b;
imm32 r5, 0xc6789a7c;
imm32 r6, 0x6789ab7d;
imm32 r7, 0x789abc7e;
R7.L = -16;
R0 = LSHIFT R0 BY R7.L;
R1 = LSHIFT R1 BY R7.L;
R2 = LSHIFT R2 BY R7.L;
R3 = LSHIFT R3 BY R7.L;
R4 = LSHIFT R4 BY R7.L;
R5 = LSHIFT R5 BY R7.L;
R6 = LSHIFT R6 BY R7.L;
R7 = LSHIFT R7 BY R7.L;
CHECKREG r0, 0x00007123;
CHECKREG r1, 0x00008234;
CHECKREG r2, 0x00009345;
CHECKREG r3, 0x0000A456;
CHECKREG r4, 0x0000B567;
CHECKREG r5, 0x0000C678;
CHECKREG r6, 0x00006789;
CHECKREG r7, 0x0000789A;
pass
|
stsp/binutils-ia16
| 1,827
|
sim/testsuite/bfin/dsp_d1.s
|
/* DAG test program.
* Test circular buffers
*/
# mach: bfin
.include "testutils.inc"
start
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x10 (X);
M1 = 8 (X);
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2
DBGA ( R1.L , 0x0008 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2
DBGA ( R1.L , 0x0008 );
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x10 (X);
M1 = -4 (X);
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2
DBGA ( R1.L , 0x000c );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2
DBGA ( R1.L , 0x0008 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x000c );
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x8 (X);
R0 = [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
R0 = [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 );
R0 = [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x8 (X);
R0.L = W [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0002 );
R0.L = W [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
R0.L = W [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0006 );
R0.L = W [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 );
R0.L = W [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0002 );
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x8 (X);
R0 = [ I0 -- ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
R0 = [ I0 -- ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 );
R0 = [ I0 -- ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
pass
.data
foo:
.space (0x10);
|
stsp/binutils-ia16
| 1,470
|
sim/testsuite/bfin/m9.s
|
// Test extraction from accumulators:
// ROUND/TRUNCATE in SIGNED FRACTIONAL mode
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7ffef000
// load r1=0x7ffff000
// load r2=0x00008000
// load r3=0x00018000
// load r4=0x0000007f
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// round
// 0x007ffef00 -> 0x7fff
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R5.H = A1, R5.L = A0;
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
// round with ovflw
// 0x007ffff00 -> 0x7fff
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
R5.H = A1, R5.L = A0;
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
// trunc
// 0x007ffef00 -> 0x7ffe
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R5.H = A1, R5.L = A0 (T);
DBGA ( R5.L , 0x7ffe );
DBGA ( R5.H , 0x7ffe );
// round with ovflw
// 0x7f7ffff00 -> 0x7fff
A1 = A0 = 0;
A1.w = R1;
A1.x = R4.L;
A0.w = R1;
A0.x = R4.L;
R5.H = A1, R5.L = A0;
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
// round, nearest even is zero
// 0x0000008000 -> 0x0000
A1 = A0 = 0;
A1.w = R2;
A0.w = R2;
R5.H = A1, R5.L = A0;
DBGA ( R5.L , 0x0 );
DBGA ( R5.H , 0x0 );
// round, nearest even is 2
// 0x00000018000 -> 0x0002
A1 = A0 = 0;
A1.w = R3;
A0.w = R3;
R5.H = A1, R5.L = A0;
DBGA ( R5.L , 0x2 );
DBGA ( R5.H , 0x2 );
pass
.data
data0:
.dw 0xf000
.dw 0x7ffe
.dw 0xf000
.dw 0x7ffe
.dw 0x8000
.dw 0x0000
.dw 0x8000
.dw 0x0001
.dw 0x007f
.dw 0x0000
|
stsp/binutils-ia16
| 4,305
|
sim/testsuite/bfin/c_cc2stat_cc_ac.S
|
//Original:/testcases/core/c_cc2stat_cc_ac/c_cc2stat_cc_ac.dsp
// Spec Reference: cc2stat cc ac
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, _UNSET;
imm32 r1, _UNSET;
imm32 r2, _UNSET;
imm32 r3, _UNSET;
imm32 r4, _UNSET;
imm32 r5, _UNSET;
imm32 r6, _UNSET;
imm32 r7, _UNSET;
// test CC = AC 0-0, 0-1, 1-0, 1-1
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC = AC0; //
R0 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC = AC0; //
R1 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
CC = AC0; //
R2 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC = AC0; //
R3 = CC; //
// test cc |= AC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC |= AC0; //
R4 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC |= AC0; //
R5 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 0
CC |= AC0; //
R6 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC |= AC0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _SET;
// test CC &= AC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC &= AC0; //
R4 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC &= AC0; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
CC &= AC0; //
R6 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC &= AC0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _UNSET;
CHECKREG r7, _SET;
// test CC ^= AC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC ^= AC0; //
R4 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC ^= AC0; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
CC ^= AC0; //
R6 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC ^= AC0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _UNSET;
// test AC0 = CC 0-0, 0-1, 1-0, 1-1
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 = CC; //
R0 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 = CC; //
R1 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 = CC; //
R2 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 = CC; //
R3 = ASTAT; //
// test AC0 |= CC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 |= CC; //
R4 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 |= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 |= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 |= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_AC0|_CC);
CHECKREG r3, (_CC|_AC0);
CHECKREG r4, _UNSET;
CHECKREG r5, (_AC0);
CHECKREG r6, (_AC0|_CC);
CHECKREG r7, (_CC|_AC0);
// test AC0 &= CC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 &= CC; //
R4 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 &= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 &= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 &= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AC0);
CHECKREG r3, (_CC|_AC0);
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _CC;
CHECKREG r7, (_CC|_AC0);
// test AC0 ^= CC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 ^= CC; //
R4 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 ^= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 ^= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 ^= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AC0);
CHECKREG r3, (_CC|_AC0);
CHECKREG r4, _UNSET;
CHECKREG r5, (_AC0);
CHECKREG r6, (_CC|_AC0);
CHECKREG r7, _CC;
pass
|
stsp/binutils-ia16
| 1,303
|
sim/testsuite/bfin/c_dsp32shiftim_rot.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_rot/c_dsp32shiftim_rot.dsp
// Spec Reference: dsp32shiftimm rot:
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8912cde;
R0 = ROT R0 BY 1;
R1 = ROT R1 BY 5;
R2 = ROT R2 BY 9;
R3 = ROT R3 BY 8;
R4 = ROT R4 BY 24;
R5 = ROT R5 BY 31;
R6 = ROT R6 BY 14;
R7 = ROT R7 BY 25;
CHECKREG r0, 0x42460002;
CHECKREG r1, 0x668ACF11;
CHECKREG r2, 0x8ACF1323;
CHECKREG r3, 0xD6789A9A;
CHECKREG r4, 0xAB42D3C4;
CHECKREG r5, 0x659F26AF;
CHECKREG r6, 0x6AF354F1;
CHECKREG r7, 0xBCB8912C;
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8912cde;
R6 = ROT R0 BY -3;
R7 = ROT R1 BY -9;
R0 = ROT R2 BY -8;
R1 = ROT R3 BY -7;
R2 = ROT R4 BY -15;
R3 = ROT R5 BY -24;
R4 = ROT R6 BY -31;
R5 = ROT R7 BY -22;
CHECKREG r0, 0x1223C567;
CHECKREG r1, 0x6A69ACF1;
CHECKREG r2, 0x26AD0B4F;
CHECKREG r3, 0xF9357896;
CHECKREG r4, 0xD0918000;
CHECKREG r5, 0x6CD15DE0;
CHECKREG r6, 0x74246000;
CHECKREG r7, 0x780D9A2B;
pass
|
stsp/binutils-ia16
| 1,458
|
sim/testsuite/bfin/c_dsp32alu_r_lh_a0pa1.s
|
//Original:/testcases/core/c_dsp32alu_r_lh_a0pa1/c_dsp32alu_r_lh_a0pa1.dsp
// Spec Reference: dsp32alu r(lh) = ( a0 += a1)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x0125ab2d;
imm32 r2, 0x04445535;
imm32 r3, 0x00567747;
imm32 r4, 0x0566895b;
imm32 r5, 0x07897b6d;
imm32 r6, 0x04445875;
imm32 r7, 0x06667797;
A0 = R0;
A1 = R1;
R0 = ( A0 += A1 );
R1 = ( A0 += A1 );
R2 = ( A0 += A1 );
R3 = ( A0 += A1 );
R4 = ( A0 += A1 );
R5 = ( A0 += A1 );
R6 = ( A0 += A1 );
R7 = ( A0 += A1 );
CHECKREG r0, 0x168D343E;
CHECKREG r1, 0x17B2DF6B;
CHECKREG r2, 0x18D88A98;
CHECKREG r3, 0x19FE35C5;
CHECKREG r4, 0x1B23E0F2;
CHECKREG r5, 0x1C498C1F;
CHECKREG r6, 0x1D6F374C;
CHECKREG r7, 0x1E94E279;
imm32 r0, 0x068D343E;
imm32 r1, 0x02B2DF6B;
imm32 r2, 0x48388A98;
imm32 r3, 0x59F435C5;
imm32 r4, 0x6B25E0F2;
imm32 r5, 0x7C496C1F;
imm32 r6, 0x886F374C;
imm32 r7, 0x9E94E279;
A0 = R0;
A1 = R1;
R0.L = ( A0 += A1 );
R0.H = ( A0 += A1 );
R1.L = ( A0 += A1 );
R1.H = ( A0 += A1 );
R2.L = ( A0 += A1 );
R2.H = ( A0 += A1 );
R3.L = ( A0 += A1 );
R3.H = ( A0 += A1 );
R4.L = ( A0 += A1 );
R4.H = ( A0 += A1 );
R5.L = ( A0 += A1 );
R5.H = ( A0 += A1 );
R6.L = ( A0 += A1 );
R6.H = ( A0 += A1 );
R7.L = ( A0 += A1 );
R7.H = ( A0 += A1 );
CHECKREG r0, 0x0BF30940;
CHECKREG r1, 0x11590EA6;
CHECKREG r2, 0x16BE140C;
CHECKREG r3, 0x1C241971;
CHECKREG r4, 0x218A1ED7;
CHECKREG r5, 0x26F0243D;
CHECKREG r6, 0x2C5529A3;
CHECKREG r7, 0x31BB2F08;
pass
|
stsp/binutils-ia16
| 1,530
|
sim/testsuite/bfin/c_ldimmhalf_drlo.s
|
//Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp
// Spec Reference: ldimmhalf dreg lo
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.L = 0x0001;
R1.L = 0x0003;
R2.L = 0x0005;
R3.L = 0x0007;
R4.L = 0x0009;
R5.L = 0x000b;
R6.L = 0x000d;
R7.L = 0x000f;
CHECKREG r0, 0xFFFF0001;
CHECKREG r1, 0xFFFF0003;
CHECKREG r2, 0xFFFF0005;
CHECKREG r3, 0xFFFF0007;
CHECKREG r4, 0xFFFF0009;
CHECKREG r5, 0xFFFF000b;
CHECKREG r6, 0xFFFF000D;
CHECKREG r7, 0xFFFF000F;
R0.L = 0x0020;
R1.L = 0x0040;
R2.L = 0x0060;
R3.L = 0x0080;
R4.L = 0x00a0;
R5.L = 0x00b0;
R6.L = 0x00c0;
R7.L = 0x00d0;
CHECKREG r0, 0xFFFF0020;
CHECKREG r1, 0xFFFF0040;
CHECKREG r2, 0xFFFF0060;
CHECKREG r3, 0xFFFF0080;
CHECKREG r4, 0xFFFF00a0;
CHECKREG r5, 0xFFFF00b0;
CHECKREG r6, 0xFFFF00c0;
CHECKREG r7, 0xFFFF00d0;
R0.L = 0x0100;
R1.L = 0x0200;
R2.L = 0x0300;
R3.L = 0x0400;
R4.L = 0x0500;
R5.L = 0x0600;
R6.L = 0x0700;
R7.L = 0x0800;
CHECKREG r0, 0xFFFF0100;
CHECKREG r1, 0xFFFF0200;
CHECKREG r2, 0xFFFF0300;
CHECKREG r3, 0xFFFF0400;
CHECKREG r4, 0xFFFF0500;
CHECKREG r5, 0xFFFF0600;
CHECKREG r6, 0xFFFF0700;
CHECKREG r7, 0xFFFF0800;
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
R0.L = 0x7fff;
R1.L = 0x7ffe;
R2.L = -32768;
R3.L = -32767;
R4.L = 32767;
R5.L = 32766;
R6.L = 32765;
R7.L = 32764;
CHECKREG r0, 0x00007fff;
CHECKREG r1, 0x00007ffe;
CHECKREG r2, 0x00008000;
CHECKREG r3, 0x00008001;
CHECKREG r4, 0x00007FFF;
CHECKREG r5, 0x00007FFE;
CHECKREG r6, 0x00007FFD;
CHECKREG r7, 0x00007FFC;
pass
|
stsp/binutils-ia16
| 5,771
|
sim/testsuite/bfin/se_excpt_dagprotviol.S
|
//Original:/proj/frio/dv/testcases/seq/se_excpt_dagprotviol/se_excpt_dagprotviol.dsp
// Description: EXCPT instruction combined with DAG Misaligned Access
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x100 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
RETI = r0; // prevent Xs later on
RETX = r0;
RETN = r0;
RETE = r0;
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the user stack pointer
FP = SP;
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
// [--sp] = RETI; // enable interrupts in supervisor mode
R0 = 0;
R1 = -1;
LD32_LABEL(p1, USTACK);
P1 += 1; // misalign it
EXCPT 2; // the RAISE should not prevent the EXCPT from being taken
R2 = [ P1 ];
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
CHECKREG(r5, 2); // check the flag
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
[ -- SP ] = ASTAT; // save what we damage
[ -- SP ] = ( R7:6 );
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 instruction
CC = r7 == r6;
IF CC JUMP EXCPT2;
R6 = 0x24; // EXCAUSE 0x24 means DAG misalign
CC = r7 == r6;
IF CC JUMP DGPROTVIOL;
JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop
EXCPT2:
R5 = 1; // Set a Flag
JUMP.S OUT;
DGPROTVIOL:
R7 = RETX; // Fix up return address
R7 += 2; // skip offending 16 bit instruction
RETX = r7; // and put back in RETX
R5 <<= 1; // Alter Global Flag
OUT:
( R7:6 ) = [ SP ++ ];
ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 2,869
|
sim/testsuite/bfin/m5.s
|
// Test result extraction of mac instructions.
// Test basic edge values
// SIGNED FRACTIONAL mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym p0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// simple extraction with no saturation
// 0x7fff * 0x7fff = 0x007ffe0002 -> 0x7ffe
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
R5.H = (A1 += R0.L * R1.L), R5.L = (A0 += R0.L * R1.L);
DBGA ( R5.L , 0x7ffe );
DBGA ( R5.H , 0x7ffe );
_DBG ASTAT;
R7 = ASTAT;
DBGA (R7.H, 0x0);
DBGA (R7.L, 0x0);
// positive saturation at 32 bits
// 0x0 * 0x0 + 0x7ff0000000 -> 0x7fff
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R3.L;
A0.x = R3.L;
A0.w = R2;
R5.H = (A1 += R0.L * R2.L), R5.L = (A0 += R0.L * R2.L);
_DBG A1;
_DBG A0;
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
_DBG ASTAT;
R7 = ASTAT;
_DBG R7;
DBGA (R7.H, 0x300);
DBGA (R7.L, 0x8);
// positive saturation at 32 bits
// 0x7fff * 0x7fff + 0x7ff0000000 -> 0x7fff
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R3.L;
A0.w = R2;
A0.x = R3.L;
R5.H = (A1 += R0.L * R1.L), R5.L = (A0 += R0.L * R1.L);
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
_DBG ASTAT;
R7 = ASTAT;
DBGA (R7.H, 0x30f);
DBGA (R7.L, 0x8);
// negative saturation at 32 bits
// 0x0 * 0x0 + 0x80f0000000 -> 0x8000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R4.L;
A0.w = R2;
A0.x = R4.L;
R5.H = (A1 += R0.L * R2.L), R5.L = (A0 += R0.L * R2.L);
DBGA ( R5.L , 0x8000 );
DBGA ( R5.H , 0x8000 );
_DBG A1;
_DBG A0;
_DBG ASTAT;
R7=ASTAT;
_DBG R7;
DBGA (R7.H, 0x300);
DBGA (R7.L, 0x0008);
// negative saturation at 32 bits
// 0x7fff * 0x8000 + 0x80f0000000 -> 0x8000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R4.L;
A0.w = R2;
A0.x = R4.L;
R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L);
DBGA ( R5.L , 0x8000 );
DBGA ( R5.H , 0x8000 );
R7=ASTAT;
_DBG ASTAT;
DBGA (R7.H, 0x300);
DBGA (R7.L, 0x0008);
// negative saturation at 32 bits on MAC only
// 0x7fff * 0x8000 + 0x80f0000000 -> 0x8000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A0.w = R2;
A0.x = R4.L;
_DBG ASTAT;
R5.H = A1, R5.L = (A0 += R0.H * R1.L);
_DBG A0;
DBGA ( R5.L , 0x8000 );
DBGA ( R5.H , 0x0000 );
R7=ASTAT;
_DBG ASTAT;
DBGA (R7.H, 0x300);
DBGA (R7.L, 0x0009);
// 0x0100 * 0x0100 = 0x00020000 -> 0x0002
R7 = 0;
ASTAT = R7;
R0.L = 0x0100;
R1.L = 0x0100;
A1 = A0 = 0;
R5.H = (A1 = R0.L * R1.L), R5.L = (A0 = R0.L * R1.L) (T);
DBGA ( R5.L , 0x0002 );
DBGA ( R5.H , 0x0002 );
R7 = ASTAT;
DBGA (R7.H, 0x000);
DBGA (R7.L, 0x000);
pass
.data
data0:
.dw 0x7fff
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
|
stsp/binutils-ia16
| 10,670
|
sim/testsuite/bfin/se_brtarget_stall.S
|
//Original:/proj/frio/dv/testcases/seq/se_brtarget_stall/se_brtarget_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE 0x00000500
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000020
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef IMASK
#define IMASK 0xFFE02104
#endif
#ifndef DMEM_CONTROL
#define DMEM_CONTROL 0xFFE00004
#endif
#ifndef DCPLB_ADDR0
#define DCPLB_ADDR0 0xFFE00100
#endif
#ifndef DCPLB_DATA0
#define DCPLB_DATA0 0xFFE00200
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
/////////////////////////////////////////////////////////////////////////////
//////////////////////// CPLB Setup /////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Setup CPLB for Data Memory starting at 0x00F0_0000;
WR_MMR(DCPLB_DATA0, 0x0003109d, p0, r0); // Page Size = 4MB
// CPLB_L1_CHLB = 1
// CPLB_DIRTY = 1
// CPLB_USER_RD = 1
// CPLB_USER_WR = 1
// CPLB_SUPV_WR = 1
// CPLB_VALID = 1
//
// Setup CPLB Address to point to 0x00F0_0000
WR_MMR_LABEL(DCPLB_ADDR0, data, p0, r0);
// Enable CPLB's
WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1
// ENDCPLB = 1
// DMC = 11
// Sync it!
CSYNC;
// Return to Supervisor Code
RAISE 15;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
NOP;
P0 = 0x0100 (Z);
P0.H = 0x00f0;
JUMP.S lab1; // Branch in EX1
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
lab1:
[ -- SP ] = ( R7:3 );
P0 = 0x0200 (Z);
P0.H = 0x00f0;
RTI;
JUMP.S 8; // Branch in EX1
NOP;
NOP;
NOP;
[ -- SP ] = ( R7:4 );
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
data:
.section MEM_0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_0x00F00200,"aw"
.dd 0x01010101;
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE);
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 2,424
|
sim/testsuite/bfin/cc-astat-bits.s
|
# Blackfin testcase for setting all ASTAT bits via CC
# mach: bfin
# We encode the opcodes directly since we test reserved bits
# which lack an insn in the ISA for it. It's a 16bit insn;
# the low 8 bits are always 0x03 while the encoding for the
# high 8 bits are:
# bit 7 - direction
# 0: CC=...;
# 1: ...=CC;
# bit 6/5 - operation
# 0: = assignment
# 1: | bit or
# 2: & bit and
# 3: ^ bit xor
# bit 4-0 - the bit in ASTAT to access
.include "testutils.inc"
.macro _do dir:req, op:req, bit:req, bit_in:req, cc_in:req, bg_val:req, bit_out:req, cc_out:req
/* CC = CC; is invalid, so skip it */
.if \bit != 5
/* Calculate the before and after ASTAT values */
imm32 R1, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_in << \bit) | (\cc_in << 5);
imm32 R3, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_out << \bit) | (\cc_out << 5);
/* Test the actual opcode */
ASTAT = R1;
.byte (\dir << 7) | (\op << 5) | \bit
.byte 0x03
R2 = ASTAT;
/* Make sure things line up */
CC = R3 == R2;
IF !CC JUMP 1f;
JUMP 2f;
1: fail
2:
.endif
/* Recurse through all the bits */
.if \bit > 0
_do \dir, \op, \bit - 1, \bit_in, \cc_in, \bg_val, \bit_out, \cc_out
.endif
.endm
/* Test different background fields on ASTAT */
.macro do dir:req, op:req, bit_in:req, cc_in:req, bit_out:req, cc_out:req
_do \dir, \op, 31, \bit_in, \cc_in, 0, \bit_out, \cc_out
_do \dir, \op, 31, \bit_in, \cc_in, -1, \bit_out, \cc_out
.endm
start
nop;
_cc_eq_bit: /* CC = bit */
do 0, 0, 0, 0, 0, 0
do 0, 0, 0, 1, 0, 0
do 0, 0, 1, 0, 1, 1
do 0, 0, 1, 1, 1, 1
_bit_eq_cc: /* bit = CC */
do 1, 0, 0, 0, 0, 0
do 1, 0, 0, 1, 1, 1
do 1, 0, 1, 0, 0, 0
do 1, 0, 1, 1, 1, 1
_cc_or_bit: /* CC |= bit */
do 0, 1, 0, 0, 0, 0
do 0, 1, 0, 1, 0, 1
do 0, 1, 1, 0, 1, 1
do 0, 1, 1, 1, 1, 1
_bit_or_cc: /* bit |= CC */
do 1, 1, 0, 0, 0, 0
do 1, 1, 0, 1, 1, 1
do 1, 1, 1, 0, 1, 0
do 1, 1, 1, 1, 1, 1
_cc_and_bit: /* CC &= bit */
do 0, 2, 0, 0, 0, 0
do 0, 2, 0, 1, 0, 0
do 0, 2, 1, 0, 1, 0
do 0, 2, 1, 1, 1, 1
_bit_and_cc: /* bit &= CC */
do 1, 2, 0, 0, 0, 0
do 1, 2, 0, 1, 0, 1
do 1, 2, 1, 0, 0, 0
do 1, 2, 1, 1, 1, 1
_cc_xor_bit: /* CC ^= bit */
do 0, 3, 0, 0, 0, 0
do 0, 3, 0, 1, 0, 1
do 0, 3, 1, 0, 1, 1
do 0, 3, 1, 1, 1, 0
_bit_xor_cc: /* bit ^= CC */
do 1, 3, 0, 0, 0, 0
do 1, 3, 0, 1, 1, 1
do 1, 3, 1, 0, 1, 0
do 1, 3, 1, 1, 0, 1
pass
|
stsp/binutils-ia16
| 1,910
|
sim/testsuite/bfin/hwloop-branch-in.s
|
# Blackfin testcase for branching into the middle of a hardware loop
# mach: bfin
.include "testutils.inc"
.macro test_prep lc:req
loadsym P5, 1f;
dmm32 LC0, \lc
R5 = 0;
R6 = 0;
R7 = 0;
.endm
.macro test_check exp5:req, exp6:req, exp7:req, expLC:req
1:
imm32 R4, \exp5;
CC = R4 == R5;
IF !CC JUMP 2f;
imm32 R4, \exp6;
CC = R4 == R6;
IF !CC JUMP 2f;
imm32 R4, \exp7;
CC = R4 == R7;
IF !CC JUMP 2f;
R3 = LC0;
imm32 R4, \expLC;
CC = R4 == R3;
IF !CC JUMP 2f;
JUMP 3f;
2: fail
3:
.endm
.macro test_rts entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req
loadsym R1, \entry;
RETS = R1;
test_prep \lc
RTS;
test_check \exp5, \exp6, \exp7, \expLC
.endm
.macro test_jump entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req
loadsym P1, \entry;
test_prep \lc
JUMP (P1);
test_check \exp5, \exp6, \exp7, \expLC
.endm
start
loadsym R1, hws;
LT0 = R1;
loadsym R1, hwe;
LB0 = R1;
test_rts hws, 0, 1, 1, 1, 0
test_rts hws, 1, 1, 1, 1, 0
test_rts hws, 2, 2, 2, 2, 0
test_rts hws, 20, 20, 20, 20, 0
test_rts hwm, 0, 0, 1, 1, 0
test_rts hwm, 1, 0, 1, 1, 0
test_rts hwm, 2, 1, 2, 2, 0
test_rts hwm, 20, 19, 20, 20, 0
test_rts hwe, 0, 0, 0, 1, 0
test_rts hwe, 1, 0, 0, 1, 0
test_rts hwe, 2, 1, 1, 2, 0
test_rts hwe, 20, 19, 19, 20, 0
test_rts hwp, 0, 0, 0, 0, 0
test_rts hwp, 1, 0, 0, 0, 1
test_rts hwp, 2, 0, 0, 0, 2
test_jump hws, 0, 1, 1, 1, 0
test_jump hws, 1, 1, 1, 1, 0
test_jump hws, 2, 2, 2, 2, 0
test_jump hws, 20, 20, 20, 20, 0
test_jump hwm, 0, 0, 1, 1, 0
test_jump hwm, 1, 0, 1, 1, 0
test_jump hwm, 2, 1, 2, 2, 0
test_jump hwm, 20, 19, 20, 20, 0
test_jump hwe, 0, 0, 0, 1, 0
test_jump hwe, 1, 0, 0, 1, 0
test_jump hwe, 2, 1, 1, 2, 0
test_jump hwe, 20, 19, 19, 20, 0
test_jump hwp, 0, 0, 0, 0, 0
test_jump hwp, 1, 0, 0, 0, 1
test_jump hwp, 2, 0, 0, 0, 2
pass
hws: R5 += 1;
hwm: R6 += 1;
hwe: R7 += 1;
hwp: JUMP (P5);
|
stsp/binutils-ia16
| 10,244
|
sim/testsuite/bfin/se_mv2lp.S
|
//Original:/proj/frio/dv/testcases/seq/se_mv2lp/se_mv2lp.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_1 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
P0 = 0x5 (Z);
P1 = 0xa (Z);
P2 = 0x0100 (Z);
P2.H = 0x00f0;
LD32_LABEL(r0, L0T);
LD32_LABEL(r1, L0B);
LSETUP ( L0T , L0B ) LC0 = P0;
L0T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
R0 += 2;
R1 += 2;
LT0 = R0;
LB0 = R1;
L0B:R7 += 6;
R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
LD32_LABEL(r0, L1T);
LD32_LABEL(r1, L1B);
LSETUP ( L1T , L1B ) LC1 = P0;
L1T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
R0 += 2;
R1 += 2;
LT1 = R0;
LB1 = R1;
L1B:R7 += 6;
R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
LD32_LABEL(r0, L2T);
LD32_LABEL(r1, L2B);
LSETUP ( L2T , L2B ) LC0 = P0;
L2T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
R0 += 2;
R1 += -2;
LT0 = R0;
LB0 = R1;
R7 += 6;
R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
L2B:R6 += 5;
LD32_LABEL(r0, L3T);
LD32_LABEL(r1, L3B);
LSETUP ( L3T , L3B ) LC1 = P0;
L3T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
R0 += 2;
R1 += -2;
LT1 = R0;
LB1 = R1;
R7 += 6;
R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
L3B:R6 += 5;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0x01010101;
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
.dd 0x05050505;
.dd 0x06060606;
.dd 0x07070707;
.dd 0x08080808;
.dd 0x09090909;
.dd 0x0a0a0a0a;
.dd 0x0b0b0b0b;
.dd 0x0c0c0c0c;
.dd 0x0d0d0d0d;
.dd 0x0e0e0e0e;
.dd 0x0f0f0f0f;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 1,990
|
sim/testsuite/bfin/l0.s
|
// simple test to ensure that we can load data from memory.
# mach: bfin
.include "testutils.inc"
start
loadsym P0, tab;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
R5 = [ P0 ++ ];
R6 = [ P0 ++ ];
R7 = [ P0 ++ ];
DBGA ( R0.H , 0x1111 );
DBGA ( R1.H , 0x2222 );
DBGA ( R2.H , 0x3333 );
DBGA ( R3.H , 0x4444 );
DBGA ( R4.H , 0x5555 );
DBGA ( R5.H , 0x6666 );
DBGA ( R6.H , 0x7777 );
DBGA ( R7.H , 0x8888 );
loadsym P0, tab2;
R0 = W [ P0 ++ ] (Z);
DBGA ( R0.L , 0x1111 );
R1 = W [ P0 ++ ] (Z);
DBGA ( R1.L , 0x8888 );
R2 = W [ P0 ++ ] (Z);
DBGA ( R2.L , 0x2222 );
R3 = W [ P0 ++ ] (Z);
DBGA ( R3.L , 0x7777 );
R4 = W [ P0 ++ ] (Z);
DBGA ( R4.L , 0x3333 );
R5 = W [ P0 ++ ] (Z);
DBGA ( R5.L , 0x6666 );
R0 = B [ P0 ++ ] (Z);
DBGA ( R0.L , 0x44 );
R1 = B [ P0 ++ ] (Z);
DBGA ( R1.L , 0x44 );
R2 = B [ P0 ++ ] (Z);
DBGA ( R2.L , 0x55 );
R3 = B [ P0 ++ ] (Z);
DBGA ( R3.L , 0x55 );
R0 = B [ P0 ++ ] (X);
DBGA ( R0.L , 0x55 );
R1 = B [ P0 ++ ] (X);
DBGA ( R1.L , 0x55 );
R0 = W [ P0 ++ ] (X);
DBGA ( R0.L , 0x4444 );
R1 = [ P0 ++ ];
DBGA ( R1.L , 0x6666 );
DBGA ( R1.H , 0x3333 );
P1 = [ P0 ++ ];
R0 = P1;
DBGA ( R0.L , 0x7777 );
DBGA ( R0.H , 0x2222 );
P1 = [ P0 ++ ];
R0 = P1;
DBGA ( R0.L , 0x8888 );
DBGA ( R0.H , 0x1111 );
loadsym P5, tab3;
R0 = B [ P5 ++ ] (X);
DBGA ( R0.H , 0 );
DBGA ( R0.L , 0 );
R0 = B [ P5 ++ ] (X);
DBGA ( R0.H , 0xffff );
DBGA ( R0.L , 0xffff );
R1 = W [ P5 ++ ] (X);
DBGA ( R1.H , 0xffff );
DBGA ( R1.L , 0xffff );
pass
.data
tab:
.dw 0
.dw 0x1111
.dw 0
.dw 0x2222
.dw 0
.dw 0x3333
.dw 0
.dw 0x4444
.dw 0
.dw 0x5555
.dw 0
.dw 0x6666
.dw 0
.dw 0x7777
.dw 0
.dw 0x8888
.dw 0
.dw 0
.dw 0
.dw 0
tab2:
.dw 0x1111
.dw 0x8888
.dw 0x2222
.dw 0x7777
.dw 0x3333
.dw 0x6666
.dw 0x4444
.dw 0x5555
.dw 0x5555
.dw 0x4444
.dw 0x6666
.dw 0x3333
.dw 0x7777
.dw 0x2222
.dw 0x8888
.dw 0x1111
tab3:
.dw 0xff00
.dw 0xffff
|
stsp/binutils-ia16
| 8,575
|
sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln.s
|
//Original:/testcases/core/c_dsp32shiftim_ahalf_ln/c_dsp32shiftim_ahalf_ln.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x1000c000;
imm32 r1, 0x1000c001;
imm32 r2, 0x1000c002;
imm32 r3, 0x1000c003;
imm32 r4, 0x1000c004;
imm32 r5, 0x1000c005;
imm32 r6, 0x1000c006;
imm32 r7, 0x1000c007;
R0.L = R0.L << 1;
R1.L = R1.L << 1;
R2.L = R2.L << 1;
R3.L = R3.L << 1;
R4.L = R4.L << 1;
R5.L = R5.L << 1;
R6.L = R6.L << 1;
R7.L = R7.L << 1;
CHECKREG r0, 0x10008000;
CHECKREG r1, 0x10008002;
CHECKREG r2, 0x10008004;
CHECKREG r3, 0x10008006;
CHECKREG r4, 0x10008008;
CHECKREG r5, 0x1000800A;
CHECKREG r6, 0x1000800C;
CHECKREG r7, 0x1000800E;
imm32 r0, 0x20008001;
imm32 r1, 0x20000001;
imm32 r2, 0x2000d002;
imm32 r3, 0x2000e003;
imm32 r4, 0x2000f004;
imm32 r5, 0x2000c005;
imm32 r6, 0x2000d006;
imm32 r7, 0x2000e007;
R7.L = R0.L << 1;
R6.L = R1.L << 1;
R5.L = R2.L << 1;
R4.L = R3.L << 1;
R3.L = R4.L << 1;
R2.L = R5.L << 1;
R1.L = R6.L << 1;
R0.L = R7.L << 1;
imm32 r0, 0x3000c001;
imm32 r1, 0x3000d001;
imm32 r2, 0x3000000f;
imm32 r3, 0x3000e003;
imm32 r4, 0x3000f004;
imm32 r5, 0x3000f005;
imm32 r6, 0x3000f006;
imm32 r7, 0x3000f007;
R6.L = R0.L << 12;
R7.L = R1.L << 12;
R5.L = R2.L << 12;
R4.L = R3.L << 12;
R3.L = R4.L << 12;
R2.L = R5.L << 12;
R1.L = R6.L << 12;
R0.L = R7.L << 12;
CHECKREG r1, 0x30000000;
CHECKREG r0, 0x30000000;
CHECKREG r2, 0x30000000;
CHECKREG r3, 0x30000000;
CHECKREG r4, 0x30003000;
CHECKREG r5, 0x3000F000;
CHECKREG r6, 0x30001000;
CHECKREG r7, 0x30001000;
imm32 r0, 0x40009001;
imm32 r1, 0x4000a001;
imm32 r2, 0x4000b002;
imm32 r3, 0x40000010;
imm32 r4, 0x4000c004;
imm32 r5, 0x4000d005;
imm32 r6, 0x4000e006;
imm32 r7, 0x4000f007;
R5.L = R0.L << 13;
R6.L = R1.L << 13;
R7.L = R2.L << 13;
R0.L = R3.L << 13;
R1.L = R4.L << 13;
R2.L = R5.L << 13;
R3.L = R6.L << 13;
R4.L = R7.L << 13;
CHECKREG r0, 0x40000000;
CHECKREG r1, 0x40008000;
CHECKREG r2, 0x40000000;
CHECKREG r3, 0x40000000;
CHECKREG r4, 0x40000000;
CHECKREG r5, 0x40002000;
CHECKREG r6, 0x40002000;
CHECKREG r7, 0x40004000;
imm32 r0, 0x00005000;
imm32 r1, 0x00015000;
imm32 r2, 0x00025000;
imm32 r3, 0x00035000;
imm32 r4, 0x00045000;
imm32 r5, 0x00055000;
imm32 r6, 0x00065000;
imm32 r7, 0x00075500;
R0.L = R0.H << 10;
R1.L = R1.H << 10;
R2.L = R2.H << 10;
R3.L = R3.H << 10;
R4.L = R4.H << 10;
R5.L = R5.H << 10;
R6.L = R6.H << 10;
R7.L = R7.H << 10;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010400;
CHECKREG r2, 0x00020800;
CHECKREG r3, 0x00030C00;
CHECKREG r4, 0x00041000;
CHECKREG r5, 0x00051400;
CHECKREG r6, 0x00061800;
CHECKREG r7, 0x00071C00;
imm32 r0, 0x90010000;
imm32 r1, 0x90010001;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R2.L = R0.H << 11;
R3.L = R1.H << 11;
R4.L = R2.H << 11;
R5.L = R3.H << 11;
R6.L = R4.H << 11;
R7.L = R5.H << 11;
R0.L = R6.H << 11;
R1.L = R7.H << 11;
CHECKREG r0, 0x90013000;
CHECKREG r1, 0x90013800;
CHECKREG r2, 0x90020800;
CHECKREG r3, 0x90030800;
CHECKREG r4, 0x90041000;
CHECKREG r5, 0x90051800;
CHECKREG r6, 0x90062000;
CHECKREG r7, 0x90072800;
imm32 r0, 0xa0010600;
imm32 r1, 0xa0010600;
imm32 r2, 0xa002060f;
imm32 r3, 0xa0030600;
imm32 r4, 0xa0040600;
imm32 r5, 0xa0050600;
imm32 r6, 0xa0060600;
imm32 r7, 0xa0070600;
R0.L = R0.H << 12;
R1.L = R1.H << 12;
R2.L = R2.H << 12;
R3.L = R3.H << 12;
R4.L = R4.H << 12;
R5.L = R5.H << 12;
R6.L = R6.H << 12;
R7.L = R7.H << 12;
CHECKREG r0, 0xA0011000;
CHECKREG r1, 0xA0011000;
CHECKREG r2, 0xA0022000;
CHECKREG r3, 0xA0033000;
CHECKREG r4, 0xA0044000;
CHECKREG r5, 0xA0055000;
CHECKREG r6, 0xA0066000;
CHECKREG r7, 0xA0077000;
imm32 r0, 0xc0010701;
imm32 r1, 0xc0010701;
imm32 r2, 0xc0020702;
imm32 r3, 0xc0030710;
imm32 r4, 0xc0040704;
imm32 r5, 0xc0050705;
imm32 r6, 0xc0060706;
imm32 r7, 0xc0070707;
R0.L = R0.H << 13;
R1.L = R1.H << 13;
R2.L = R2.H << 13;
R3.L = R3.H << 13;
R4.L = R4.H << 13;
R5.L = R5.H << 13;
R6.L = R6.H << 13;
R7.L = R7.H << 13;
CHECKREG r0, 0xC0012000;
CHECKREG r1, 0xC0012000;
CHECKREG r2, 0xC0024000;
CHECKREG r3, 0xC0036000;
CHECKREG r4, 0xC0048000;
CHECKREG r5, 0xC005A000;
CHECKREG r6, 0xC006C000;
CHECKREG r7, 0xC007E000;
imm32 r0, 0x00008000;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.H = R0.L << 0;
R1.H = R1.L << 1;
R2.H = R2.L << 2;
R3.H = R3.L << 3;
R4.H = R4.L << 4;
R5.H = R5.L << 5;
R6.H = R6.L << 6;
R7.H = R7.L << 7;
CHECKREG r0, 0x80008000;
CHECKREG r1, 0x00028001;
CHECKREG r2, 0x00088002;
CHECKREG r3, 0x00188003;
CHECKREG r4, 0x00408004;
CHECKREG r5, 0x00A08005;
CHECKREG r6, 0x01808006;
CHECKREG r7, 0x03808007;
imm32 r0, 0x0000d001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000d003;
imm32 r4, 0x0000d004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000d007;
R2.H = R0.L << 8;
R3.H = R1.L << 9;
R4.H = R2.L << 10;
R5.H = R3.L << 11;
R6.H = R4.L << 12;
R7.H = R5.L << 13;
R0.H = R6.L << 14;
R1.H = R7.L << 15;
CHECKREG r0, 0x8000D001;
CHECKREG r1, 0x80000001;
CHECKREG r2, 0x0100D002;
CHECKREG r3, 0x0200D003;
CHECKREG r4, 0x0800D004;
CHECKREG r5, 0x1800D005;
CHECKREG r6, 0x4000D006;
CHECKREG r7, 0xA000D007;
imm32 r0, 0x0000e001;
imm32 r1, 0x0000e001;
imm32 r2, 0x0000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000e004;
imm32 r5, 0x0000e005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000e007;
R0.H = R0.L << 12;
R1.H = R1.L << 12;
R2.H = R2.L << 12;
R3.H = R3.L << 12;
R4.H = R4.L << 12;
R5.H = R5.L << 12;
R6.H = R6.L << 12;
R7.H = R7.L << 12;
CHECKREG r0, 0x1000E001;
CHECKREG r1, 0x1000E001;
CHECKREG r2, 0xF000000F;
CHECKREG r3, 0x3000E003;
CHECKREG r4, 0x4000E004;
CHECKREG r5, 0x5000E005;
CHECKREG r6, 0x6000E006;
CHECKREG r7, 0x7000E007;
imm32 r0, 0x0000f001;
imm32 r1, 0x0000f001;
imm32 r2, 0x0000f002;
imm32 r3, 0x00000010;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R5.H = R0.L << 13;
R6.H = R1.L << 13;
R7.H = R2.L << 13;
R0.H = R3.L << 13;
R1.H = R4.L << 13;
R2.H = R5.L << 13;
R3.H = R6.L << 13;
R4.H = R7.L << 13;
CHECKREG r0, 0x0000F001;
CHECKREG r1, 0x8000F001;
CHECKREG r2, 0xA000F002;
CHECKREG r3, 0xC0000010;
CHECKREG r4, 0xE000F004;
CHECKREG r5, 0x2000F005;
CHECKREG r6, 0x2000F006;
CHECKREG r7, 0x4000F007;
// d_lo = ashift (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x90000000;
imm32 r1, 0x90010000;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R4.H = R0.H << 10;
R5.H = R1.H << 10;
R6.H = R2.H << 10;
R7.H = R3.H << 10;
R0.H = R4.H << 10;
R1.H = R5.H << 10;
R2.H = R6.H << 10;
R3.H = R7.H << 10;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x04000000;
CHECKREG r6, 0x08000000;
CHECKREG r7, 0x0C000000;
imm32 r0, 0xa0010000;
imm32 r1, 0x00010001;
imm32 r2, 0xa0020000;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R7.H = R0.H << 11;
R0.H = R1.H << 11;
R1.H = R2.H << 11;
R2.H = R3.H << 11;
R3.H = R4.H << 11;
R4.H = R5.H << 11;
R5.H = R6.H << 11;
R6.H = R7.H << 11;
CHECKREG r0, 0x08000000;
CHECKREG r1, 0x10000001;
CHECKREG r2, 0x18000000;
CHECKREG r3, 0x20000000;
CHECKREG r4, 0x28000000;
CHECKREG r5, 0x30000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x08000000;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060000;
imm32 r7, 0xb0070000;
R6.H = R0.H << 12;
R7.H = R1.H << 12;
R0.H = R2.H << 12;
R1.H = R3.H << 12;
R2.H = R4.H << 12;
R3.H = R5.H << 12;
R4.H = R6.H << 12;
R5.H = R7.H << 12;
CHECKREG r0, 0x20000000;
CHECKREG r1, 0x30000000;
CHECKREG r2, 0x4000000F;
CHECKREG r3, 0x50000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x10000000;
CHECKREG r7, 0x10000000;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030010;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
imm32 r6, 0xd0060000;
imm32 r7, 0xd0070000;
R5.H = R0.H << 3;
R6.H = R1.H << 3;
R7.H = R2.H << 3;
R0.H = R3.H << 3;
R1.H = R4.H << 3;
R2.H = R5.H << 3;
R3.H = R6.H << 3;
R4.H = R7.H << 3;
CHECKREG r0, 0x80180000;
CHECKREG r1, 0x80200000;
CHECKREG r2, 0x00400000;
CHECKREG r3, 0x00400010;
CHECKREG r4, 0x00800000;
CHECKREG r5, 0x80080000;
CHECKREG r6, 0x80080000;
CHECKREG r7, 0x80100000;
pass
|
stsp/binutils-ia16
| 3,885
|
sim/testsuite/bfin/c_alu2op_conv_toggle.s
|
//Original:/testcases/core/c_alu2op_conv_toggle/c_alu2op_conv_toggle.dsp
// Spec Reference: alu2op (~) toggle
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = ~ R0;
R1 = ~ R0;
R2 = ~ R0;
R3 = ~ R0;
R4 = ~ R0;
R5 = ~ R0;
R6 = ~ R0;
R7 = ~ R0;
CHECKREG r0, 0xFF876543;
CHECKREG r1, 0x00789ABC;
CHECKREG r2, 0x00789ABC;
CHECKREG r3, 0x00789ABC;
CHECKREG r4, 0x00789ABC;
CHECKREG r5, 0x00789ABC;
CHECKREG r6, 0x00789ABC;
CHECKREG r7, 0x00789ABC;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R0 = ~ R1;
R1 = ~ R1;
R2 = ~ R1;
R3 = ~ R1;
R4 = ~ R1;
R5 = ~ R1;
R6 = ~ R1;
R7 = ~ R1;
CHECKREG r0, 0xFFC8B9A6;
CHECKREG r1, 0xFFC8B9A6;
CHECKREG r2, 0x00374659;
CHECKREG r3, 0x00374659;
CHECKREG r4, 0x00374659;
CHECKREG r5, 0x00374659;
CHECKREG r6, 0x00374659;
CHECKREG r7, 0x00374659;
imm32 r0, 0x10789abc;
imm32 r1, 0x11345678;
imm32 r2, 0x93156789;
imm32 r3, 0xd451789a;
imm32 r4, 0x856719ab;
imm32 r5, 0x267891bc;
imm32 r6, 0xa789ab1d;
imm32 r7, 0x989ab1de;
R0 = ~ R2;
R1 = ~ R2;
R2 = ~ R2;
R3 = ~ R2;
R4 = ~ R2;
R5 = ~ R2;
R6 = ~ R2;
R7 = ~ R2;
CHECKREG r0, 0x6CEA9876;
CHECKREG r1, 0x6CEA9876;
CHECKREG r2, 0x6CEA9876;
CHECKREG r3, 0x93156789;
CHECKREG r4, 0x93156789;
CHECKREG r5, 0x93156789;
CHECKREG r6, 0x93156789;
CHECKREG r7, 0x93156789;
imm32 r0, 0x21230002;
imm32 r1, 0x02374659;
imm32 r2, 0x93256789;
imm32 r3, 0xa952789a;
imm32 r4, 0xb59729ab;
imm32 r5, 0xc67992bc;
imm32 r6, 0xd7899b2d;
imm32 r7, 0xe89ab9d2;
R0 = ~ R3;
R1 = ~ R3;
R2 = ~ R3;
R3 = ~ R3;
R4 = ~ R3;
R5 = ~ R3;
R6 = ~ R3;
R7 = ~ R3;
CHECKREG r0, 0x56AD8765;
CHECKREG r1, 0x56AD8765;
CHECKREG r2, 0x56AD8765;
CHECKREG r3, 0x56AD8765;
CHECKREG r4, 0xA952789A;
CHECKREG r5, 0xA952789A;
CHECKREG r6, 0xA952789A;
CHECKREG r7, 0xA952789A;
imm32 r0, 0xa0789abc;
imm32 r1, 0x1a345678;
imm32 r2, 0x23a56789;
imm32 r3, 0x645a789a;
imm32 r4, 0x8667a9ab;
imm32 r5, 0x96689abc;
imm32 r6, 0xa787abad;
imm32 r7, 0xb89a7cda;
R0 = ~ R4;
R1 = ~ R4;
R2 = ~ R4;
R3 = ~ R4;
R4 = ~ R4;
R5 = ~ R4;
R6 = ~ R4;
R7 = ~ R4;
CHECKREG r0, 0x79985654;
CHECKREG r1, 0x79985654;
CHECKREG r2, 0x79985654;
CHECKREG r3, 0x79985654;
CHECKREG r4, 0x79985654;
CHECKREG r5, 0x8667A9AB;
CHECKREG r6, 0x8667A9AB;
CHECKREG r7, 0x8667A9AB;
imm32 r0, 0xf1230002;
imm32 r1, 0x0f374659;
imm32 r2, 0x93f56789;
imm32 r3, 0xa45f789a;
imm32 r4, 0xb567f9ab;
imm32 r5, 0xc6789fbc;
imm32 r6, 0xd789abfd;
imm32 r7, 0xe89abcdf;
R0 = ~ R5;
R1 = ~ R5;
R2 = ~ R5;
R3 = ~ R5;
R4 = ~ R5;
R5 = ~ R5;
R6 = ~ R5;
R7 = ~ R5;
CHECKREG r0, 0x39876043;
CHECKREG r1, 0x39876043;
CHECKREG r2, 0x39876043;
CHECKREG r3, 0x39876043;
CHECKREG r4, 0x39876043;
CHECKREG r5, 0x39876043;
CHECKREG r6, 0xC6789FBC;
CHECKREG r7, 0xC6789FBC;
imm32 r0, 0xe0789abc;
imm32 r1, 0xe2345678;
imm32 r2, 0x2e456789;
imm32 r3, 0x34e6789a;
imm32 r4, 0x856e89ab;
imm32 r5, 0x9678eabc;
imm32 r6, 0xa789aecd;
imm32 r7, 0xb89abcee;
R0 = ~ R6;
R1 = ~ R6;
R2 = ~ R6;
R3 = ~ R6;
R4 = ~ R6;
R5 = ~ R6;
R6 = ~ R6;
R7 = ~ R6;
CHECKREG r0, 0x58765132;
CHECKREG r1, 0x58765132;
CHECKREG r2, 0x58765132;
CHECKREG r3, 0x58765132;
CHECKREG r4, 0x58765132;
CHECKREG r5, 0x58765132;
CHECKREG r6, 0x58765132;
CHECKREG r7, 0xA789AECD;
imm32 r0, 0x012300f5;
imm32 r1, 0x80374659;
imm32 r2, 0x98456589;
imm32 r3, 0xa486589a;
imm32 r4, 0xb56589ab;
imm32 r5, 0xc6588abc;
imm32 r6, 0xd589a8cd;
imm32 r7, 0x589abc88;
R0 = ~ R7;
R1 = ~ R7;
R2 = ~ R7;
R3 = ~ R7;
R4 = ~ R7;
R5 = ~ R7;
R7 = ~ R7;
R6 = ~ R7;
CHECKREG r0, 0xA7654377;
CHECKREG r1, 0xA7654377;
CHECKREG r2, 0xA7654377;
CHECKREG r3, 0xA7654377;
CHECKREG r4, 0xA7654377;
CHECKREG r5, 0xA7654377;
CHECKREG r6, 0x589ABC88;
CHECKREG r7, 0xA7654377;
pass
|
stsp/binutils-ia16
| 5,171
|
sim/testsuite/bfin/se_more_ret_haz.S
|
//Original:/proj/frio/dv/testcases/seq/se_more_ret_haz/se_more_ret_haz.dsp
// Description: Return insts following pop, move.
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
CLI R1;
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC;
STI R1;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
// Raise 1 requires some intelligence so the test
// doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
RAISE 2;
R2.L = 0xBAD;
CHECKREG(r2, 0);
AFTER_RTN:
EXCPT 5;
R2.L = 0xBAD;
CHECKREG(r2, 0);
AFTER_RTX:
RAISE 5;
R2.L = 0xBAD;
CHECKREG(r2, 0);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R1.L = AFTER_RTN;
R1.H = AFTER_RTN;
[ -- SP ] = R1;
RETN = [ SP ++ ];
RTN;
XHANDLE: // Exception Handler 3
R1.L = AFTER_RTX;
R1.H = AFTER_RTX;
[ -- SP ] = R1;
RETX = [ SP ++ ];
RTX;
HWHANDLE: // HW Error Handler 5
R1.L = END;
R1.H = END;
[ -- SP ] = R1;
RETI = [ SP ++ ];
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 4,138
|
sim/testsuite/bfin/c_alu2op_arith_r_sft.s
|
//Original:/testcases/core/c_alu2op_arith_r_sft/c_alu2op_arith_r_sft.dsp
// Spec Reference: alu2op arith right
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R1.L = 1;
R1 >>>= R0;
R2 >>>= R0;
R3 >>>= R0;
R4 >>>= R0;
R5 >>>= R0;
R6 >>>= R0;
R7 >>>= R0;
R4 >>>= R0;
R0 >>>= R0;
CHECKREG r1, 0x12340001;
CHECKREG r2, 0x23456789;
CHECKREG r3, 0x3456789A;
CHECKREG r4, 0x856789AB;
CHECKREG r5, 0x96789ABC;
CHECKREG r6, 0xA789ABCD;
CHECKREG r7, 0xB89ABCDE;
CHECKREG r0, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R1.L = -1;
R0 >>>= R1;
R2 >>>= R1;
R3 >>>= R1;
R4 >>>= R1;
R5 >>>= R1;
R6 >>>= R1;
R7 >>>= R1;
R1 >>>= R1;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
R0 >>>= R2;
R1 >>>= R2;
R3 >>>= R2;
R4 >>>= R2;
R5 >>>= R2;
R6 >>>= R2;
R7 >>>= R2;
R2 >>>= R2;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R3.L = -31;
R0 >>>= R3;
R1 >>>= R3;
R2 >>>= R3;
R4 >>>= R3;
R5 >>>= R3;
R6 >>>= R3;
R7 >>>= R3;
R3 >>>= R3;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x00000001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R4.L = 15;
R1 >>>= R4;
R2 >>>= R4;
R3 >>>= R4;
R0 >>>= R4;
R5 >>>= R4;
R6 >>>= R4;
R7 >>>= R4;
R4 >>>= R4;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00002468;
CHECKREG r2, 0x0000468A;
CHECKREG r3, 0x000068AC;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0xFFFF2CF1;
CHECKREG r6, 0xFFFF4F13;
CHECKREG r7, 0xFFFF7135;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x00000000;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R5.L = -15;
R0 >>>= R5;
R1 >>>= R5;
R2 >>>= R5;
R3 >>>= R5;
R4 >>>= R5;
R6 >>>= R5;
R7 >>>= R5;
R5 >>>= R5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0xb1256790;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R6.L = 24;
R0 >>>= R6;
R1 >>>= R6;
R2 >>>= R6;
R3 >>>= R6;
R4 >>>= R6;
R5 >>>= R6;
R7 >>>= R6;
R6 >>>= R6;
CHECKREG r0, 0x00000051;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0xFFFFFFB1;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0xFFFFFF95;
CHECKREG r5, 0xFFFFFF86;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000078;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0x00000000;
R7.L = -24;
R0 >>>= R7;
R1 >>>= R7;
R2 >>>= R7;
R3 >>>= R7;
R4 >>>= R7;
R5 >>>= R7;
R6 >>>= R7;
R7 >>>= R7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0x00000000;
// special case
R2.L = -1;
R2.H = 32767;
R0 = 0;
R2 >>>= R0;
CHECKREG r2, 0x7FFFFFFF;
pass
|
stsp/binutils-ia16
| 2,919
|
sim/testsuite/bfin/random_0023.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0xf41fbf3f;
dmm32 A1.x, 0x00000000;
imm32 R5, 0xd8d95310;
imm32 R6, 0xd0457fff;
R5.H = (A1 -= R6.L * R6.H) (M, FU);
checkreg R5, 0x7fff5310;
checkreg A1.w, 0x8bfe0f84;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x54b0ca90 | _VS | _AV1S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0xf88288c8;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0xfffe6736;
imm32 R2, 0x8000f882;
imm32 R3, 0xffff8391;
R0.H = (A1 += R3.L * R2.L) (M, FU);
checkreg R0, 0x80006736;
checkreg A1.w, 0x7fb7d06a;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x54b0ca90 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x1c500480 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x9083dd08;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x00000000;
imm32 R4, 0x00002492;
R4.H = (A1 += R4.L * R0.H) (M, FU);
checkreg R4, 0x7fff2492;
checkreg ASTAT, (0x1c500480 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x7c00c810 | _AV1S | _AC1 | _AC0);
dmm32 A1.w, 0x69e86d3f;
dmm32 A1.x, 0xffffffc2;
imm32 R1, 0x64f42c5b;
imm32 R3, 0x4128529d;
R3 = (A1 -= R3.L * R1.L) (M, FU);
checkreg R3, 0x80000000;
checkreg A1.w, 0x5b981370;
checkreg A1.x, 0xffffffc2;
checkreg ASTAT, (0x7c00c810 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY);
dmm32 ASTAT, (0x5cc0c480 | _VS | _AQ | _CC);
dmm32 A1.w, 0x34bbe964;
dmm32 A1.x, 0x00000036;
imm32 R1, 0x7fffffff;
imm32 R5, 0x7fff427e;
A1 -= R5.L * R1.L (M, FU);
checkreg A1.w, 0xf23e2be2;
checkreg A1.x, 0x00000035;
checkreg ASTAT, (0x5cc0c480 | _VS | _AQ | _CC);
# here the result is zero, and the _V bit is set
dmm32 ASTAT, 0x0;
dmm32 A0.w, 0x00008492;
dmm32 A0.x, 0x00000000;
imm32 R2, 0x7fff0002;
imm32 R3, 0xfa6e8492;
imm32 R6, 0xffff0002;
R6 = (A0 -= R3.L * R2.L) (FU);
checkreg R6, 0x00000000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, ( _VS | _V | _AV0S | _AV0 | _V_COPY);
# here the result is zero, and the _V bit is not set
dmm32 ASTAT, (_V | _V_COPY);
dmm32 A0.w, 0x1fffc000;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x80004000;
imm32 R4, 0x1fffffff;
imm32 R6, 0x80000000;
R4.L = (A0 -= R0.L * R6.H) (FU);
checkreg R4, 0x1fff0000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (_AV0S | _AV0);
dmm32 ASTAT, (0x0c108610 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
dmm32 A0.w, 0x0000eaf0;
dmm32 A0.x, 0x00000000;
imm32 R1, 0x00010000;
imm32 R6, 0xfbf10001;
R1.L = (A0 -= R6.H * R1.H) (FU);
checkreg R1, 0x00010000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x0c108610 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
pass
|
stsp/binutils-ia16
| 3,885
|
sim/testsuite/bfin/c_dsp32mac_dr_a1a0_m.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_m/c_dsp32mac_dr_a1a0_m.dsp
// Spec Reference: dsp32mac dr_a1a0 m
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0;
ASTAT = R0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xb2bcfec7;
imm32 r2, 0xc1348679;
imm32 r3, 0xd0049007;
imm32 r4, 0xefbc5569;
imm32 r5, 0xcd35560b;
imm32 r6, 0xe00c807d;
imm32 r7, 0xf78e9008;
A1 = A0 = 0;
R6.H = (A1 += R0.L * R0.L) (M), R6.L = (A0 = R0.L * R0.L);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 += R2.L * R3.L) (M), R1.L = (A0 -= R2.H * R3.L);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 -= R4.L * R5.L) (M), R2.L = (A0 -= R4.H * R5.H);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 += R0.L * R7.L) (M), R3.L = (A0 += R0.L * R7.H);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0x13545ABD;
CHECKREG r1, 0xDBCA0964;
CHECKREG r2, 0xBF1502EF;
CHECKREG r3, 0xF222FCF3;
CHECKREG r4, 0xF222613D;
CHECKREG r5, 0xFCF2D20E;
CHECKREG r6, 0x20294053;
CHECKREG r7, 0xF78E9008;
CHECKREG p1, 0x20296F89;
CHECKREG p2, 0x4052DF12;
CHECKREG p3, 0xDBCA2CD8;
CHECKREG p4, 0x0963CE3A;
CHECKREG p5, 0xBF153B55;
CHECKREG fp, 0x02EF7262;
imm32 r0, 0x13545abd;
imm32 r1, 0x22bcfec7;
imm32 r2, 0x43348679;
imm32 r3, 0x50049007;
imm32 r4, 0x6fbc5569;
imm32 r5, 0x7d35560b;
imm32 r6, 0x800c807d;
imm32 r7, 0xf98e9008;
A1 = A0 = 0;
R0.H = (A1 += R1.L * R0.H) (M), R0.L = (A0 -= R1.L * R0.L);
P1 = A1.w;
P2 = A0.w;
R6.H = (A1 += R2.L * R2.H) (M), R6.L = (A0 = R2.H * R2.L);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 -= R4.L * R5.H) (M), R2.L = (A0 += R4.H * R5.H);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 += R3.L * R7.H) (M), R3.L = (A0 -= R3.L * R7.H);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0xFFE800DE;
CHECKREG r1, 0x22BCFEC7;
CHECKREG r2, 0xB63B2D7E;
CHECKREG r3, 0x800027DA;
CHECKREG r4, 0x49141905;
CHECKREG r5, 0x27DA6D3C;
CHECKREG r6, 0xE001C032;
CHECKREG r7, 0xF98E9008;
CHECKREG p1, 0xFFE85E4C;
CHECKREG p2, 0x00DDE22A;
CHECKREG p3, 0xE00159E0;
CHECKREG p4, 0xC031F728;
CHECKREG p5, 0xB63B6623;
CHECKREG fp, 0x2D7DD300;
imm32 r0, 0x13545abd;
imm32 r1, 0x42bcfec7;
imm32 r2, 0x51348679;
imm32 r3, 0x60049007;
imm32 r4, 0x7fbc5569;
imm32 r5, 0x8d35560b;
imm32 r6, 0x900c807d;
imm32 r7, 0xa78e9008;
A1 = A0 = 0;
R0.H = (A1 += R1.H * R0.L) (M), R0.L = (A0 = R1.L * R0.L);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 -= R2.H * R3.L) (M), R1.L = (A0 -= R2.H * R3.L);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 -= R4.H * R5.L) (M), R2.L = (A0 += R4.H * R5.H);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 += R6.H * R7.L) (M), R3.L = (A0 += R6.L * R7.H);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0x17A7FF22;
CHECKREG r1, 0xE9F8462B;
CHECKREG r2, 0xBF09D39D;
CHECKREG r3, 0x800C2BB9;
CHECKREG r4, 0x800C7FAC;
CHECKREG r5, 0x2BB8C982;
CHECKREG r6, 0x900C807D;
CHECKREG r7, 0xA78E9008;
CHECKREG p1, 0x17A75CCC;
CHECKREG p2, 0xFF221DD6;
CHECKREG p3, 0xE9F7E460;
CHECKREG p4, 0x462B2CFE;
CHECKREG p5, 0xBF093F4C;
CHECKREG fp, 0xD39D28D6;
imm32 r0, 0x03545abd;
imm32 r1, 0xb3bcfec7;
imm32 r2, 0x24348679;
imm32 r3, 0x60049007;
imm32 r4, 0x7fbc5569;
imm32 r5, 0x9d35560b;
imm32 r6, 0xa00c807d;
imm32 r7, 0x078e9008;
A1 = A0 = 0;
R0.H = (A1 += R1.H * R0.H) (M), R0.L = (A0 -= R1.L * R0.L);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 -= R2.H * R3.H) (M), R1.L = (A0 = R2.H * R3.L);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 = R4.H * R5.H) (M), R2.L = (A0 += R4.H * R5.H);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 += R6.H * R7.H) (M), R3.L = (A0 += R6.L * R7.H);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0xFF0200DE;
CHECKREG r1, 0xF16EE054;
CHECKREG r2, 0x4E718000;
CHECKREG r3, 0x4B9C8000;
CHECKREG r4, 0x4B9BD894;
CHECKREG r5, 0x7637575C;
CHECKREG r6, 0xA00C807D;
CHECKREG r7, 0x078E9008;
CHECKREG p1, 0xFF022DB0;
CHECKREG p2, 0x00DDE22A;
CHECKREG p3, 0xF16E1CE0;
CHECKREG p4, 0xE0547AD8;
CHECKREG p5, 0x4E70BDEC;
CHECKREG fp, 0x7DBDF6B0;
pass
|
stsp/binutils-ia16
| 103,044
|
sim/testsuite/bfin/se_undefinedinstruction3.S
|
//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction3/se_undefinedinstruction3.dsp
// Description: 32 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
# xfail: "missing checks in A0/A1 macfunc" *-*
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
A0 = 0; // reset accumulators
A1 = 0;
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// count of UI's will be in r5, which was initialized to 0 by header
.dw 0xE802 ;
.dw 0xB3FD ;
.dw 0xE803 ;
.dw 0xD461 ;
.dw 0xE804 ;
.dw 0x36A1 ;
.dw 0xE805 ;
.dw 0x7FED ;
.dw 0xE806 ;
.dw 0xFEB3 ;
.dw 0xE807 ;
.dw 0x8785 ;
.dw 0xE808 ;
.dw 0x2F21 ;
.dw 0xE809 ;
.dw 0x2889 ;
.dw 0xE80A ;
.dw 0x96B7 ;
.dw 0xE80B ;
.dw 0x8357 ;
.dw 0xE80C ;
.dw 0x5D07 ;
.dw 0xE80D ;
.dw 0x13D5 ;
.dw 0xE80E ;
.dw 0x1C11 ;
.dw 0xE80F ;
.dw 0x19D3 ;
.dw 0xE810 ;
.dw 0xBF4B ;
.dw 0xE811 ;
.dw 0xEF89 ;
.dw 0xE812 ;
.dw 0x2BD ;
.dw 0xE813 ;
.dw 0x6FC5 ;
.dw 0xE814 ;
.dw 0x89F1 ;
.dw 0xE815 ;
.dw 0x1D13 ;
.dw 0xE816 ;
.dw 0xA03F ;
.dw 0xE817 ;
.dw 0x9681 ;
.dw 0xE818 ;
.dw 0x2961 ;
.dw 0xE819 ;
.dw 0xEE23 ;
.dw 0xE81A ;
.dw 0x7ABB ;
.dw 0xE81B ;
.dw 0x8927 ;
.dw 0xE81C ;
.dw 0x2343 ;
.dw 0xE81D ;
.dw 0x308F ;
.dw 0xE81E ;
.dw 0x718F ;
.dw 0xE81F ;
.dw 0xC549 ;
.dw 0xE820 ;
.dw 0x2CD3 ;
.dw 0xE821 ;
.dw 0x81D9 ;
.dw 0xE822 ;
.dw 0xD76B ;
.dw 0xE823 ;
.dw 0xB735 ;
.dw 0xE824 ;
.dw 0x4EBB ;
.dw 0xE825 ;
.dw 0x6223 ;
.dw 0xE826 ;
.dw 0x15EB ;
.dw 0xE827 ;
.dw 0xB19F ;
.dw 0xE828 ;
.dw 0x6E6B ;
.dw 0xE829 ;
.dw 0x7EA3 ;
.dw 0xE82A ;
.dw 0xF2A7 ;
.dw 0xE82B ;
.dw 0xA8E1 ;
.dw 0xE82C ;
.dw 0x14ED ;
.dw 0xE82D ;
.dw 0x2BA5 ;
.dw 0xE82E ;
.dw 0xDD5 ;
.dw 0xE82F ;
.dw 0x69AD ;
.dw 0xE830 ;
.dw 0xCB47 ;
.dw 0xE831 ;
.dw 0x85F7 ;
.dw 0xE832 ;
.dw 0xB25D ;
.dw 0xE833 ;
.dw 0x8351 ;
.dw 0xE834 ;
.dw 0xE445 ;
.dw 0xE835 ;
.dw 0x33E5 ;
.dw 0xE836 ;
.dw 0x8F6B ;
.dw 0xE837 ;
.dw 0x9D5B ;
.dw 0xE838 ;
.dw 0xBE1 ;
.dw 0xE839 ;
.dw 0x3DB9 ;
.dw 0xE83A ;
.dw 0x7391 ;
.dw 0xE83B ;
.dw 0x70E5 ;
.dw 0xE83C ;
.dw 0x7409 ;
.dw 0xE83D ;
.dw 0xF5A9 ;
.dw 0xE83E ;
.dw 0xA15B ;
.dw 0xE83F ;
.dw 0x1D3F ;
.dw 0xE840 ;
.dw 0xF709 ;
.dw 0xE841 ;
.dw 0x6751 ;
.dw 0xE842 ;
.dw 0xD565 ;
.dw 0xE843 ;
.dw 0x1035 ;
.dw 0xE844 ;
.dw 0x755 ;
.dw 0xE845 ;
.dw 0x46AD ;
.dw 0xE846 ;
.dw 0x95F3 ;
.dw 0xE847 ;
.dw 0x39B3 ;
.dw 0xE848 ;
.dw 0xC4EB ;
.dw 0xE849 ;
.dw 0xD693 ;
.dw 0xE84A ;
.dw 0xE40F ;
.dw 0xE84B ;
.dw 0xC30F ;
.dw 0xE84C ;
.dw 0x101F ;
.dw 0xE84D ;
.dw 0xBEA7 ;
.dw 0xE84E ;
.dw 0xE617 ;
.dw 0xE84F ;
.dw 0x1BD ;
.dw 0xE850 ;
.dw 0xF203 ;
.dw 0xE851 ;
.dw 0x48D5 ;
.dw 0xE852 ;
.dw 0xA3DD ;
.dw 0xE853 ;
.dw 0xDD7F ;
.dw 0xE854 ;
.dw 0x3233 ;
.dw 0xE855 ;
.dw 0xFE45 ;
.dw 0xE856 ;
.dw 0x6C3D ;
.dw 0xE857 ;
.dw 0x6225 ;
.dw 0xE858 ;
.dw 0x722F ;
.dw 0xE859 ;
.dw 0x1BDD ;
.dw 0xE85A ;
.dw 0xFC35 ;
.dw 0xE85B ;
.dw 0xB4C1 ;
.dw 0xE85C ;
.dw 0xA635 ;
.dw 0xE85D ;
.dw 0xD62D ;
.dw 0xE85E ;
.dw 0xFF7D ;
.dw 0xE85F ;
.dw 0x2463 ;
.dw 0xE860 ;
.dw 0x439B ;
.dw 0xE861 ;
.dw 0xE4EF ;
.dw 0xE862 ;
.dw 0x299 ;
.dw 0xE863 ;
.dw 0x8E4F ;
.dw 0xE864 ;
.dw 0xFCA1 ;
.dw 0xE865 ;
.dw 0x4DFD ;
.dw 0xE866 ;
.dw 0x6E7D ;
.dw 0xE867 ;
.dw 0xCDAF ;
.dw 0xE868 ;
.dw 0x61D1 ;
.dw 0xE869 ;
.dw 0xE7C7 ;
.dw 0xE86A ;
.dw 0xA59D ;
.dw 0xE86B ;
.dw 0x6ED7 ;
.dw 0xE86C ;
.dw 0x40CF ;
.dw 0xE86D ;
.dw 0x8B4B ;
.dw 0xE86E ;
.dw 0xDA83 ;
.dw 0xE86F ;
.dw 0x5DF1 ;
.dw 0xE870 ;
.dw 0x18B5 ;
.dw 0xE871 ;
.dw 0x6D91 ;
.dw 0xE872 ;
.dw 0xB7EF ;
.dw 0xE873 ;
.dw 0xC941 ;
.dw 0xE874 ;
.dw 0x7BE9 ;
.dw 0xE875 ;
.dw 0x98A3 ;
.dw 0xE876 ;
.dw 0x7269 ;
.dw 0xE877 ;
.dw 0xEECF ;
.dw 0xE878 ;
.dw 0xB77B ;
.dw 0xE879 ;
.dw 0xFBFD ;
.dw 0xE87A ;
.dw 0x5B59 ;
.dw 0xE87B ;
.dw 0xDAD ;
.dw 0xE87C ;
.dw 0x97F5 ;
.dw 0xE87D ;
.dw 0xC8B ;
.dw 0xE87E ;
.dw 0x8DA1 ;
.dw 0xE87F ;
.dw 0x32A5 ;
.dw 0xE880 ;
.dw 0xA3B7 ;
.dw 0xE881 ;
.dw 0x6C27 ;
.dw 0xE882 ;
.dw 0xCBB7 ;
.dw 0xE883 ;
.dw 0x1873 ;
.dw 0xE884 ;
.dw 0xA2CF ;
.dw 0xE885 ;
.dw 0x9083 ;
.dw 0xE886 ;
.dw 0x2737 ;
.dw 0xE887 ;
.dw 0xD383 ;
.dw 0xE888 ;
.dw 0xCC51 ;
.dw 0xE889 ;
.dw 0xE1AD ;
.dw 0xE88A ;
.dw 0x8A01 ;
.dw 0xE88B ;
.dw 0x8123 ;
.dw 0xE88C ;
.dw 0x712D ;
.dw 0xE88D ;
.dw 0x47FF ;
.dw 0xE88E ;
.dw 0xB8CD ;
.dw 0xE88F ;
.dw 0xB23B ;
.dw 0xE890 ;
.dw 0x7C89 ;
.dw 0xE891 ;
.dw 0xA19F ;
.dw 0xE892 ;
.dw 0xE745 ;
.dw 0xE893 ;
.dw 0xC985 ;
.dw 0xE894 ;
.dw 0xA199 ;
.dw 0xE895 ;
.dw 0x176F ;
.dw 0xE896 ;
.dw 0x759D ;
.dw 0xE897 ;
.dw 0x54B ;
.dw 0xE898 ;
.dw 0x8EF7 ;
.dw 0xE899 ;
.dw 0xC987 ;
.dw 0xE89A ;
.dw 0xEFAB ;
.dw 0xE89B ;
.dw 0x6C97 ;
.dw 0xE89C ;
.dw 0xFF7B ;
.dw 0xE89D ;
.dw 0xCB35 ;
.dw 0xE89E ;
.dw 0xE57B ;
.dw 0xE89F ;
.dw 0x57F1 ;
.dw 0xE8A0 ;
.dw 0x8F ;
.dw 0xE8A1 ;
.dw 0xE667 ;
.dw 0xE8A2 ;
.dw 0xB56F ;
.dw 0xE8A3 ;
.dw 0xCD93 ;
.dw 0xE8A4 ;
.dw 0x460F ;
.dw 0xE8A5 ;
.dw 0x1EAF ;
.dw 0xE8A6 ;
.dw 0xDFD1 ;
.dw 0xE8A7 ;
.dw 0x6921 ;
.dw 0xE8A8 ;
.dw 0xE397 ;
.dw 0xE8A9 ;
.dw 0x6BB9 ;
.dw 0xE8AA ;
.dw 0xFBEB ;
.dw 0xE8AB ;
.dw 0x6E7 ;
.dw 0xE8AC ;
.dw 0x4367 ;
.dw 0xE8AD ;
.dw 0xA337 ;
.dw 0xE8AE ;
.dw 0xE6A3 ;
.dw 0xE8AF ;
.dw 0xEA89 ;
.dw 0xE8B0 ;
.dw 0xB2B1 ;
.dw 0xE8B1 ;
.dw 0xA6D ;
.dw 0xE8B2 ;
.dw 0x428D ;
.dw 0xE8B3 ;
.dw 0x993D ;
.dw 0xE8B4 ;
.dw 0x5B73 ;
.dw 0xE8B5 ;
.dw 0x8717 ;
.dw 0xE8B6 ;
.dw 0xE189 ;
.dw 0xE8B7 ;
.dw 0x1F87 ;
.dw 0xE8B8 ;
.dw 0x3D3 ;
.dw 0xE8B9 ;
.dw 0xE7ED ;
.dw 0xE8BA ;
.dw 0x2FDB ;
.dw 0xE8BB ;
.dw 0xFA71 ;
.dw 0xE8BC ;
.dw 0x6AF7 ;
.dw 0xE8BD ;
.dw 0x3C97 ;
.dw 0xE8BE ;
.dw 0x38B9 ;
.dw 0xE8BF ;
.dw 0x5C3B ;
.dw 0xE8C0 ;
.dw 0x9B53 ;
.dw 0xE8C1 ;
.dw 0xB51F ;
.dw 0xE8C2 ;
.dw 0x5C73 ;
.dw 0xE8C3 ;
.dw 0x49D ;
.dw 0xE8C4 ;
.dw 0xA8F ;
.dw 0xE8C5 ;
.dw 0xF3 ;
.dw 0xE8C6 ;
.dw 0x4FFB ;
.dw 0xE8C7 ;
.dw 0x6479 ;
.dw 0xE8C8 ;
.dw 0xDED5 ;
.dw 0xE8C9 ;
.dw 0xA557 ;
.dw 0xE8CA ;
.dw 0x7E0D ;
.dw 0xE8CB ;
.dw 0x4513 ;
.dw 0xE8CC ;
.dw 0x31AF ;
.dw 0xE8CD ;
.dw 0x4361 ;
.dw 0xE8CE ;
.dw 0x61B5 ;
.dw 0xE8CF ;
.dw 0xAACB ;
.dw 0xE8D0 ;
.dw 0xA85B ;
.dw 0xE8D1 ;
.dw 0x4569 ;
.dw 0xE8D2 ;
.dw 0xF277 ;
.dw 0xE8D3 ;
.dw 0x2B57 ;
.dw 0xE8D4 ;
.dw 0x39A5 ;
.dw 0xE8D5 ;
.dw 0xEC0F ;
.dw 0xE8D6 ;
.dw 0xB9DF ;
.dw 0xE8D7 ;
.dw 0x6F75 ;
.dw 0xE8D8 ;
.dw 0x793F ;
.dw 0xE8D9 ;
.dw 0x32A1 ;
.dw 0xE8DA ;
.dw 0xAA99 ;
.dw 0xE8DB ;
.dw 0x1829 ;
.dw 0xE8DC ;
.dw 0x4097 ;
.dw 0xE8DD ;
.dw 0x8323 ;
.dw 0xE8DE ;
.dw 0x510B ;
.dw 0xE8DF ;
.dw 0xBF73 ;
.dw 0xE8E0 ;
.dw 0xD31 ;
.dw 0xE8E1 ;
.dw 0xB1BD ;
.dw 0xE8E2 ;
.dw 0x756F ;
.dw 0xE8E3 ;
.dw 0x4C83 ;
.dw 0xE8E4 ;
.dw 0xEC7F ;
.dw 0xE8E5 ;
.dw 0x37BB ;
.dw 0xE8E6 ;
.dw 0xC767 ;
.dw 0xE8E7 ;
.dw 0x5379 ;
.dw 0xE8E8 ;
.dw 0x4D39 ;
.dw 0xE8E9 ;
.dw 0x25F9 ;
.dw 0xE8EA ;
.dw 0xAB13 ;
.dw 0xE8EB ;
.dw 0xB895 ;
.dw 0xE8EC ;
.dw 0x8E35 ;
.dw 0xE8ED ;
.dw 0xC6EB ;
.dw 0xE8EE ;
.dw 0xBFB3 ;
.dw 0xE8EF ;
.dw 0x4EF3 ;
.dw 0xE8F0 ;
.dw 0xA2B9 ;
.dw 0xE8F1 ;
.dw 0x6807 ;
.dw 0xE8F2 ;
.dw 0x37B3 ;
.dw 0xE8F3 ;
.dw 0xAAC3 ;
.dw 0xE8F4 ;
.dw 0xA461 ;
.dw 0xE8F5 ;
.dw 0x42C3 ;
.dw 0xE8F6 ;
.dw 0x9A4B ;
.dw 0xE8F7 ;
.dw 0xDF03 ;
.dw 0xE8F8 ;
.dw 0xAA6B ;
.dw 0xE8F9 ;
.dw 0xFD0F ;
.dw 0xE8FA ;
.dw 0x695 ;
.dw 0xE8FB ;
.dw 0x5EB1 ;
.dw 0xE8FC ;
.dw 0xBE8D ;
.dw 0xE8FD ;
.dw 0xB949 ;
.dw 0xE8FE ;
.dw 0x9023 ;
.dw 0xE8FF ;
.dw 0xB987 ;
.dw 0xE900 ;
.dw 0x475B ;
.dw 0xE901 ;
.dw 0x2DB5 ;
.dw 0xE902 ;
.dw 0xCD17 ;
.dw 0xE903 ;
.dw 0x6C33 ;
.dw 0xE904 ;
.dw 0xC013 ;
.dw 0xE905 ;
.dw 0xBB77 ;
.dw 0xE906 ;
.dw 0x2DC3 ;
.dw 0xE907 ;
.dw 0x7C11 ;
.dw 0xE908 ;
.dw 0x15F7 ;
.dw 0xE909 ;
.dw 0xFD0F ;
.dw 0xE90A ;
.dw 0x35B1 ;
.dw 0xE90B ;
.dw 0x165D ;
.dw 0xE90C ;
.dw 0x8327 ;
.dw 0xE90D ;
.dw 0xC449 ;
.dw 0xE90E ;
.dw 0x2E4F ;
.dw 0xE90F ;
.dw 0xEAEF ;
.dw 0xE910 ;
.dw 0x3EFB ;
.dw 0xE911 ;
.dw 0xFFB3 ;
.dw 0xE912 ;
.dw 0x6AF3 ;
.dw 0xE913 ;
.dw 0x7A73 ;
.dw 0xE914 ;
.dw 0xDBD7 ;
.dw 0xE915 ;
.dw 0x7FA7 ;
.dw 0xE916 ;
.dw 0xB681 ;
.dw 0xE917 ;
.dw 0x1023 ;
.dw 0xE918 ;
.dw 0xAA85 ;
.dw 0xE919 ;
.dw 0x12A9 ;
.dw 0xE91A ;
.dw 0x27F ;
.dw 0xE91B ;
.dw 0x9EF7 ;
.dw 0xE91C ;
.dw 0xFB09 ;
.dw 0xE91D ;
.dw 0xF179 ;
.dw 0xE91E ;
.dw 0xEFAD ;
.dw 0xE91F ;
.dw 0x3A67 ;
.dw 0xE920 ;
.dw 0x9301 ;
.dw 0xE921 ;
.dw 0xF273 ;
.dw 0xE922 ;
.dw 0x4819 ;
.dw 0xE923 ;
.dw 0x629F ;
.dw 0xE924 ;
.dw 0x3177 ;
.dw 0xE925 ;
.dw 0x7C9B ;
.dw 0xE926 ;
.dw 0x2BD ;
.dw 0xE927 ;
.dw 0xDC33 ;
.dw 0xE928 ;
.dw 0x783B ;
.dw 0xE929 ;
.dw 0xB20B ;
.dw 0xE92A ;
.dw 0xE895 ;
.dw 0xE92B ;
.dw 0x4B5D ;
.dw 0xE92C ;
.dw 0x12B7 ;
.dw 0xE92D ;
.dw 0xC9E7 ;
.dw 0xE92E ;
.dw 0x7335 ;
.dw 0xE92F ;
.dw 0x4AB1 ;
.dw 0xE930 ;
.dw 0x7251 ;
.dw 0xE931 ;
.dw 0x11E1 ;
.dw 0xE932 ;
.dw 0xFCE3 ;
.dw 0xE933 ;
.dw 0x3557 ;
.dw 0xE934 ;
.dw 0xF837 ;
.dw 0xE935 ;
.dw 0x8F27 ;
.dw 0xE936 ;
.dw 0xDA2F ;
.dw 0xE937 ;
.dw 0x5CC3 ;
.dw 0xE938 ;
.dw 0xE4BD ;
.dw 0xE939 ;
.dw 0xB6DF ;
.dw 0xE93A ;
.dw 0x7509 ;
.dw 0xE93B ;
.dw 0xE1EB ;
.dw 0xE93C ;
.dw 0xE439 ;
.dw 0xE93D ;
.dw 0x3621 ;
.dw 0xE93E ;
.dw 0x15D ;
.dw 0xE93F ;
.dw 0xEA05 ;
.dw 0xE940 ;
.dw 0x9151 ;
.dw 0xE941 ;
.dw 0x4169 ;
.dw 0xE942 ;
.dw 0xE325 ;
.dw 0xE943 ;
.dw 0x66B5 ;
.dw 0xE944 ;
.dw 0xC4DD ;
.dw 0xE945 ;
.dw 0x6395 ;
.dw 0xE946 ;
.dw 0x5E09 ;
.dw 0xE947 ;
.dw 0x29CD ;
.dw 0xE948 ;
.dw 0xB35 ;
.dw 0xE949 ;
.dw 0x4459 ;
.dw 0xE94A ;
.dw 0xA671 ;
.dw 0xE94B ;
.dw 0x7C83 ;
.dw 0xE94C ;
.dw 0x1715 ;
.dw 0xE94D ;
.dw 0x5E37 ;
.dw 0xE94E ;
.dw 0xEC19 ;
.dw 0xE94F ;
.dw 0xF227 ;
.dw 0xE950 ;
.dw 0x89E9 ;
.dw 0xE951 ;
.dw 0x1BFD ;
.dw 0xE952 ;
.dw 0x7637 ;
.dw 0xE953 ;
.dw 0xAE5B ;
.dw 0xE954 ;
.dw 0xE9AF ;
.dw 0xE955 ;
.dw 0x55B5 ;
.dw 0xE956 ;
.dw 0x6905 ;
.dw 0xE957 ;
.dw 0xD6D3 ;
.dw 0xE958 ;
.dw 0x1C47 ;
.dw 0xE959 ;
.dw 0xA523 ;
.dw 0xE95A ;
.dw 0x4CE1 ;
.dw 0xE95B ;
.dw 0x687F ;
.dw 0xE95C ;
.dw 0x404F ;
.dw 0xE95D ;
.dw 0x89B5 ;
.dw 0xE95E ;
.dw 0xEEE1 ;
.dw 0xE95F ;
.dw 0x2851 ;
.dw 0xE960 ;
.dw 0x3B7D ;
.dw 0xE961 ;
.dw 0xD409 ;
.dw 0xE962 ;
.dw 0xB2ED ;
.dw 0xE963 ;
.dw 0xE767 ;
.dw 0xE964 ;
.dw 0xD673 ;
.dw 0xE965 ;
.dw 0x50D5 ;
.dw 0xE966 ;
.dw 0xEF57 ;
.dw 0xE967 ;
.dw 0xD2D1 ;
.dw 0xE968 ;
.dw 0xBE17 ;
.dw 0xE969 ;
.dw 0x2B6B ;
.dw 0xE96A ;
.dw 0x69F1 ;
.dw 0xE96B ;
.dw 0x6C1 ;
.dw 0xE96C ;
.dw 0x426F ;
.dw 0xE96D ;
.dw 0xFFA9 ;
.dw 0xE96E ;
.dw 0x8EA9 ;
.dw 0xE96F ;
.dw 0x1D41 ;
.dw 0xE970 ;
.dw 0x2AF5 ;
.dw 0xE971 ;
.dw 0x1379 ;
.dw 0xE972 ;
.dw 0x779D ;
.dw 0xE973 ;
.dw 0xF075 ;
.dw 0xE974 ;
.dw 0x7871 ;
.dw 0xE975 ;
.dw 0xAFC1 ;
.dw 0xE976 ;
.dw 0x5EB3 ;
.dw 0xE977 ;
.dw 0x4845 ;
.dw 0xE978 ;
.dw 0x6C4F ;
.dw 0xE979 ;
.dw 0x10E1 ;
.dw 0xE97A ;
.dw 0x90B7 ;
.dw 0xE97B ;
.dw 0xABA3 ;
.dw 0xE97C ;
.dw 0xAD7B ;
.dw 0xE97D ;
.dw 0xE6A3 ;
.dw 0xE97E ;
.dw 0x79E9 ;
.dw 0xE97F ;
.dw 0xD37 ;
.dw 0xE980 ;
.dw 0xE2B5 ;
.dw 0xE981 ;
.dw 0xDBBF ;
.dw 0xE982 ;
.dw 0xE41D ;
.dw 0xE983 ;
.dw 0x8BA3 ;
.dw 0xE984 ;
.dw 0x9A6B ;
.dw 0xE985 ;
.dw 0x1CCB ;
.dw 0xE986 ;
.dw 0xFE53 ;
.dw 0xE987 ;
.dw 0xFD2D ;
.dw 0xE988 ;
.dw 0xD811 ;
.dw 0xE989 ;
.dw 0x56B1 ;
.dw 0xE98A ;
.dw 0x45C9 ;
.dw 0xE98B ;
.dw 0x7F05 ;
.dw 0xE98C ;
.dw 0x1EF7 ;
.dw 0xE98D ;
.dw 0x24AF ;
.dw 0xE98E ;
.dw 0xE895 ;
.dw 0xE98F ;
.dw 0xBFF1 ;
.dw 0xE990 ;
.dw 0x52A5 ;
.dw 0xE991 ;
.dw 0x65C7 ;
.dw 0xE992 ;
.dw 0xB9C5 ;
.dw 0xE993 ;
.dw 0x3E8F ;
.dw 0xE994 ;
.dw 0x44AB ;
.dw 0xE995 ;
.dw 0x71BD ;
.dw 0xE996 ;
.dw 0x4EEB ;
.dw 0xE997 ;
.dw 0x3307 ;
.dw 0xE998 ;
.dw 0x4807 ;
.dw 0xE999 ;
.dw 0xA58B ;
.dw 0xE99A ;
.dw 0x5F3B ;
.dw 0xE99B ;
.dw 0x5C45 ;
.dw 0xE99C ;
.dw 0xA1EB ;
.dw 0xE99D ;
.dw 0x3F5B ;
.dw 0xE99E ;
.dw 0xFC25 ;
.dw 0xE99F ;
.dw 0x68AD ;
.dw 0xE9A0 ;
.dw 0x3029 ;
.dw 0xE9A1 ;
.dw 0x1FD ;
.dw 0xE9A2 ;
.dw 0xBB69 ;
.dw 0xE9A3 ;
.dw 0x3259 ;
.dw 0xE9A4 ;
.dw 0x1CF5 ;
.dw 0xE9A5 ;
.dw 0x97E5 ;
.dw 0xE9A6 ;
.dw 0x6AB1 ;
.dw 0xE9A7 ;
.dw 0x86D3 ;
.dw 0xE9A8 ;
.dw 0xF853 ;
.dw 0xE9A9 ;
.dw 0x2D9B ;
.dw 0xE9AA ;
.dw 0x64A5 ;
.dw 0xE9AB ;
.dw 0xB23F ;
.dw 0xE9AC ;
.dw 0xEDD ;
.dw 0xE9AD ;
.dw 0x3BB5 ;
.dw 0xE9AE ;
.dw 0x1F8F ;
.dw 0xE9AF ;
.dw 0x8627 ;
.dw 0xE9B0 ;
.dw 0x5627 ;
.dw 0xE9B1 ;
.dw 0xF853 ;
.dw 0xE9B2 ;
.dw 0xD5F ;
.dw 0xE9B3 ;
.dw 0x139F ;
.dw 0xE9B4 ;
.dw 0xC691 ;
.dw 0xE9B5 ;
.dw 0x6815 ;
.dw 0xE9B6 ;
.dw 0x655B ;
.dw 0xE9B7 ;
.dw 0xD10B ;
.dw 0xE9B8 ;
.dw 0x7A9D ;
.dw 0xE9B9 ;
.dw 0x868F ;
.dw 0xE9BA ;
.dw 0xEF1F ;
.dw 0xE9BB ;
.dw 0x6355 ;
.dw 0xE9BC ;
.dw 0x6BD3 ;
.dw 0xE9BD ;
.dw 0x7E4B ;
.dw 0xE9BE ;
.dw 0x6747 ;
.dw 0xE9BF ;
.dw 0xC29D ;
.dw 0xE9C0 ;
.dw 0x2507 ;
.dw 0xE9C1 ;
.dw 0x6833 ;
.dw 0xE9C2 ;
.dw 0x957F ;
.dw 0xE9C3 ;
.dw 0xF27B ;
.dw 0xE9C4 ;
.dw 0x4241 ;
.dw 0xE9C5 ;
.dw 0x8A97 ;
.dw 0xE9C6 ;
.dw 0xAC1D ;
.dw 0xE9C7 ;
.dw 0x5B1 ;
.dw 0xE9C8 ;
.dw 0x160B ;
.dw 0xE9C9 ;
.dw 0x8F99 ;
.dw 0xE9CA ;
.dw 0x939 ;
.dw 0xE9CB ;
.dw 0xA561 ;
.dw 0xE9CC ;
.dw 0x4C51 ;
.dw 0xE9CD ;
.dw 0xAB2D ;
.dw 0xE9CE ;
.dw 0xF143 ;
.dw 0xE9CF ;
.dw 0xD3CF ;
.dw 0xE9D0 ;
.dw 0xE2AD ;
.dw 0xE9D1 ;
.dw 0x288F ;
.dw 0xE9D2 ;
.dw 0x5B1D ;
.dw 0xE9D3 ;
.dw 0x228F ;
.dw 0xE9D4 ;
.dw 0x4E4D ;
.dw 0xE9D5 ;
.dw 0x573B ;
.dw 0xE9D6 ;
.dw 0x65B1 ;
.dw 0xE9D7 ;
.dw 0x143F ;
.dw 0xE9D8 ;
.dw 0x2743 ;
.dw 0xE9D9 ;
.dw 0x4F61 ;
.dw 0xE9DA ;
.dw 0x8F0F ;
.dw 0xE9DB ;
.dw 0xE1C5 ;
.dw 0xE9DC ;
.dw 0x315D ;
.dw 0xE9DD ;
.dw 0x85E7 ;
.dw 0xE9DE ;
.dw 0x44FB ;
.dw 0xE9DF ;
.dw 0x5AFB ;
.dw 0xE9E0 ;
.dw 0x1A81 ;
.dw 0xE9E1 ;
.dw 0xA7D3 ;
.dw 0xE9E2 ;
.dw 0xE70F ;
.dw 0xE9E3 ;
.dw 0x1AF7 ;
.dw 0xE9E4 ;
.dw 0xC67D ;
.dw 0xE9E5 ;
.dw 0xB54D ;
.dw 0xE9E6 ;
.dw 0xD24B ;
.dw 0xE9E7 ;
.dw 0xC7B7 ;
.dw 0xE9E8 ;
.dw 0x806B ;
.dw 0xE9E9 ;
.dw 0xD419 ;
.dw 0xE9EA ;
.dw 0x8E35 ;
.dw 0xE9EB ;
.dw 0x955B ;
.dw 0xE9EC ;
.dw 0xE981 ;
.dw 0xE9ED ;
.dw 0xD187 ;
.dw 0xE9EE ;
.dw 0xB365 ;
.dw 0xE9EF ;
.dw 0xC4DF ;
.dw 0xE9F0 ;
.dw 0xFD67 ;
.dw 0xE9F1 ;
.dw 0xCBEB ;
.dw 0xE9F2 ;
.dw 0xA3AD ;
.dw 0xE9F3 ;
.dw 0x5653 ;
.dw 0xE9F4 ;
.dw 0x415 ;
.dw 0xE9F5 ;
.dw 0xFB9F ;
.dw 0xE9F6 ;
.dw 0xABA3 ;
.dw 0xE9F7 ;
.dw 0xA695 ;
.dw 0xE9F8 ;
.dw 0xC929 ;
.dw 0xE9F9 ;
.dw 0x136F ;
.dw 0xE9FA ;
.dw 0xA5BF ;
.dw 0xE9FB ;
.dw 0x3083 ;
.dw 0xE9FC ;
.dw 0xF0BF ;
.dw 0xE9FD ;
.dw 0x309B ;
.dw 0xE9FE ;
.dw 0xB6F5 ;
.dw 0xE9FF ;
.dw 0x29B7 ;
.dw 0xEA00 ;
.dw 0xC1C5 ;
.dw 0xEA01 ;
.dw 0xD249 ;
.dw 0xEA02 ;
.dw 0x3CCB ;
.dw 0xEA03 ;
.dw 0x32BF ;
.dw 0xEA04 ;
.dw 0x3DDB ;
.dw 0xEA05 ;
.dw 0xD07B ;
.dw 0xEA06 ;
.dw 0x84EB ;
.dw 0xEA07 ;
.dw 0xD2D7 ;
.dw 0xEA08 ;
.dw 0xDEA3 ;
.dw 0xEA09 ;
.dw 0xCA8F ;
.dw 0xEA0A ;
.dw 0x6645 ;
.dw 0xEA0B ;
.dw 0xF71B ;
.dw 0xEA0C ;
.dw 0xD09F ;
.dw 0xEA0D ;
.dw 0x533 ;
.dw 0xEA0E ;
.dw 0x53A3 ;
.dw 0xEA0F ;
.dw 0x2D41 ;
.dw 0xEA10 ;
.dw 0x383 ;
.dw 0xEA11 ;
.dw 0x2FD7 ;
.dw 0xEA12 ;
.dw 0xFFBF ;
.dw 0xEA13 ;
.dw 0xD1DB ;
.dw 0xEA14 ;
.dw 0xE815 ;
.dw 0xEA15 ;
.dw 0x9B1 ;
.dw 0xEA16 ;
.dw 0x2ADB ;
.dw 0xEA17 ;
.dw 0xE9FB ;
.dw 0xEA18 ;
.dw 0x337F ;
.dw 0xEA19 ;
.dw 0x5E29 ;
.dw 0xEA1A ;
.dw 0xB1DD ;
.dw 0xEA1B ;
.dw 0xE07F ;
.dw 0xEA1C ;
.dw 0x8025 ;
.dw 0xEA1D ;
.dw 0x50DB ;
.dw 0xEA1E ;
.dw 0x76E3 ;
.dw 0xEA1F ;
.dw 0xDEBF ;
.dw 0xEA20 ;
.dw 0x2407 ;
.dw 0xEA21 ;
.dw 0x7107 ;
.dw 0xEA22 ;
.dw 0x3B5F ;
.dw 0xEA23 ;
.dw 0xF8C1 ;
.dw 0xEA24 ;
.dw 0x148B ;
.dw 0xEA25 ;
.dw 0x8C8D ;
.dw 0xEA26 ;
.dw 0x3A9 ;
.dw 0xEA27 ;
.dw 0xE4FF ;
.dw 0xEA28 ;
.dw 0x2FE3 ;
.dw 0xEA29 ;
.dw 0xBA69 ;
.dw 0xEA2A ;
.dw 0x1C1D ;
.dw 0xEA2B ;
.dw 0x7791 ;
.dw 0xEA2C ;
.dw 0xC3D9 ;
.dw 0xEA2D ;
.dw 0x94A1 ;
.dw 0xEA2E ;
.dw 0x57AD ;
.dw 0xEA2F ;
.dw 0x98EB ;
.dw 0xEA30 ;
.dw 0xAA33 ;
.dw 0xEA31 ;
.dw 0x19C3 ;
.dw 0xEA32 ;
.dw 0xA003 ;
.dw 0xEA33 ;
.dw 0xF015 ;
.dw 0xEA34 ;
.dw 0xD27F ;
.dw 0xEA35 ;
.dw 0x2DE1 ;
.dw 0xEA36 ;
.dw 0x6F0B ;
.dw 0xEA37 ;
.dw 0xF863 ;
.dw 0xEA38 ;
.dw 0x9173 ;
.dw 0xEA39 ;
.dw 0x32FD ;
.dw 0xEA3A ;
.dw 0x4A19 ;
.dw 0xEA3B ;
.dw 0xBAAB ;
.dw 0xEA3C ;
.dw 0x8DC1 ;
.dw 0xEA3D ;
.dw 0xB113 ;
.dw 0xEA3E ;
.dw 0xD677 ;
.dw 0xEA3F ;
.dw 0xE203 ;
.dw 0xEA40 ;
.dw 0xA271 ;
.dw 0xEA41 ;
.dw 0x857B ;
.dw 0xEA42 ;
.dw 0x9F7F ;
.dw 0xEA43 ;
.dw 0x63EF ;
.dw 0xEA44 ;
.dw 0x8EBB ;
.dw 0xEA45 ;
.dw 0x91F7 ;
.dw 0xEA46 ;
.dw 0x2639 ;
.dw 0xEA47 ;
.dw 0x7421 ;
.dw 0xEA48 ;
.dw 0xCB59 ;
.dw 0xEA49 ;
.dw 0x6317 ;
.dw 0xEA4A ;
.dw 0x5269 ;
.dw 0xEA4B ;
.dw 0xFBAF ;
.dw 0xEA4C ;
.dw 0x5D63 ;
.dw 0xEA4D ;
.dw 0xC63F ;
.dw 0xEA4E ;
.dw 0xDD33 ;
.dw 0xEA4F ;
.dw 0x4BC7 ;
.dw 0xEA50 ;
.dw 0xFEA7 ;
.dw 0xEA51 ;
.dw 0xC71F ;
.dw 0xEA52 ;
.dw 0xCD29 ;
.dw 0xEA53 ;
.dw 0x43F1 ;
.dw 0xEA54 ;
.dw 0x7383 ;
.dw 0xEA55 ;
.dw 0xC9D ;
.dw 0xEA56 ;
.dw 0x9BE5 ;
.dw 0xEA57 ;
.dw 0xA3BB ;
.dw 0xEA58 ;
.dw 0x6637 ;
.dw 0xEA59 ;
.dw 0xD5F ;
.dw 0xEA5A ;
.dw 0x1D23 ;
.dw 0xEA5B ;
.dw 0xBFF7 ;
.dw 0xEA5C ;
.dw 0x9FC3 ;
.dw 0xEA5D ;
.dw 0x13B5 ;
.dw 0xEA5E ;
.dw 0xBF5D ;
.dw 0xEA5F ;
.dw 0x5375 ;
.dw 0xEA60 ;
.dw 0xF639 ;
.dw 0xEA61 ;
.dw 0x8919 ;
.dw 0xEA62 ;
.dw 0x3DD9 ;
.dw 0xEA63 ;
.dw 0xA337 ;
.dw 0xEA64 ;
.dw 0xC89D ;
.dw 0xEA65 ;
.dw 0x8125 ;
.dw 0xEA66 ;
.dw 0x5C47 ;
.dw 0xEA67 ;
.dw 0xAE2B ;
.dw 0xEA68 ;
.dw 0x6035 ;
.dw 0xEA69 ;
.dw 0xFC07 ;
.dw 0xEA6A ;
.dw 0xC3DD ;
.dw 0xEA6B ;
.dw 0xA063 ;
.dw 0xEA6C ;
.dw 0xF69 ;
.dw 0xEA6D ;
.dw 0xD881 ;
.dw 0xEA6E ;
.dw 0x99E7 ;
.dw 0xEA6F ;
.dw 0x41C9 ;
.dw 0xEA70 ;
.dw 0x660F ;
.dw 0xEA71 ;
.dw 0xED5B ;
.dw 0xEA72 ;
.dw 0xE7E3 ;
.dw 0xEA73 ;
.dw 0x9861 ;
.dw 0xEA74 ;
.dw 0x534F ;
.dw 0xEA75 ;
.dw 0x4259 ;
.dw 0xEA76 ;
.dw 0x6D17 ;
.dw 0xEA77 ;
.dw 0x75F3 ;
.dw 0xEA78 ;
.dw 0x8CFB ;
.dw 0xEA79 ;
.dw 0xE0BD ;
.dw 0xEA7A ;
.dw 0xF1AD ;
.dw 0xEA7B ;
.dw 0x2951 ;
.dw 0xEA7C ;
.dw 0x1459 ;
.dw 0xEA7D ;
.dw 0x3331 ;
.dw 0xEA7E ;
.dw 0xB349 ;
.dw 0xEA7F ;
.dw 0xB03 ;
.dw 0xEA80 ;
.dw 0x308B ;
.dw 0xEA81 ;
.dw 0x6D4F ;
.dw 0xEA82 ;
.dw 0x31D ;
.dw 0xEA83 ;
.dw 0x1D8B ;
.dw 0xEA84 ;
.dw 0xB661 ;
.dw 0xEA85 ;
.dw 0xF289 ;
.dw 0xEA86 ;
.dw 0xAD87 ;
.dw 0xEA87 ;
.dw 0x790F ;
.dw 0xEA88 ;
.dw 0xF5AB ;
.dw 0xEA89 ;
.dw 0x34AD ;
.dw 0xEA8A ;
.dw 0x4327 ;
.dw 0xEA8B ;
.dw 0xBA9D ;
.dw 0xEA8C ;
.dw 0x241B ;
.dw 0xEA8D ;
.dw 0x1D5 ;
.dw 0xEA8E ;
.dw 0xDB77 ;
.dw 0xEA8F ;
.dw 0x2EE1 ;
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.dw 0xEC27 ;
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.dw 0xEC32 ;
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.dw 0xEC36 ;
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.dw 0xEC37 ;
.dw 0x4449 ;
.dw 0xEC38 ;
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.dw 0xD65D ;
.dw 0xEC3E ;
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.dw 0xEC46 ;
.dw 0x36DD ;
.dw 0xEC47 ;
.dw 0x976F ;
.dw 0xEC48 ;
.dw 0x3927 ;
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.dw 0xA2CB ;
.dw 0xEFB3 ;
.dw 0xF903 ;
.dw 0xEFB4 ;
.dw 0x9E77 ;
.dw 0xEFB5 ;
.dw 0x6DB ;
.dw 0xEFB6 ;
.dw 0x2035 ;
.dw 0xEFB7 ;
.dw 0x5ABB ;
.dw 0xEFB8 ;
.dw 0xB40F ;
.dw 0xEFB9 ;
.dw 0x4CB5 ;
.dw 0xEFBA ;
.dw 0x562D ;
.dw 0xEFBB ;
.dw 0xAAC3 ;
.dw 0xEFBC ;
.dw 0x3531 ;
.dw 0xEFBD ;
.dw 0xA461 ;
.dw 0xEFBE ;
.dw 0xA98F ;
.dw 0xEFBF ;
.dw 0x47F ;
.dw 0xEFC0 ;
.dw 0x2EF9 ;
.dw 0xEFC1 ;
.dw 0x1C0F ;
.dw 0xEFC2 ;
.dw 0xCE43 ;
.dw 0xEFC3 ;
.dw 0x82C5 ;
.dw 0xEFC4 ;
.dw 0xA3A9 ;
.dw 0xEFC5 ;
.dw 0x34B ;
.dw 0xEFC6 ;
.dw 0x66E3 ;
.dw 0xEFC7 ;
.dw 0x8395 ;
.dw 0xEFC8 ;
.dw 0x700D ;
.dw 0xEFC9 ;
.dw 0x6179 ;
.dw 0xEFCA ;
.dw 0x5C3 ;
.dw 0xEFCB ;
.dw 0x6F55 ;
.dw 0xEFCC ;
.dw 0x2E51 ;
.dw 0xEFCD ;
.dw 0x5BCF ;
.dw 0xEFCE ;
.dw 0x2795 ;
.dw 0xEFCF ;
.dw 0xBB87 ;
.dw 0xEFD0 ;
.dw 0x6E4F ;
.dw 0xEFD1 ;
.dw 0x2C7 ;
.dw 0xEFD2 ;
.dw 0x3F7B ;
.dw 0xEFD3 ;
.dw 0x60FD ;
.dw 0xEFD4 ;
.dw 0x1B77 ;
.dw 0xEFD5 ;
.dw 0x7F1B ;
.dw 0xEFD6 ;
.dw 0x6C9F ;
.dw 0xEFD7 ;
.dw 0x7D99 ;
.dw 0xEFD8 ;
.dw 0x6817 ;
.dw 0xEFD9 ;
.dw 0x163F ;
.dw 0xEFDA ;
.dw 0xF151 ;
.dw 0xEFDB ;
.dw 0x597D ;
.dw 0xEFDC ;
.dw 0x163F ;
.dw 0xEFDD ;
.dw 0xFE55 ;
.dw 0xEFDE ;
.dw 0x395 ;
.dw 0xEFDF ;
.dw 0x87C7 ;
.dw 0xEFE0 ;
.dw 0x7615 ;
.dw 0xEFE1 ;
.dw 0x79A7 ;
.dw 0xEFE2 ;
.dw 0xF45 ;
.dw 0xEFE3 ;
.dw 0x5ACB ;
.dw 0xEFE4 ;
.dw 0xF1A7 ;
.dw 0xEFE5 ;
.dw 0x319B ;
.dw 0xEFE6 ;
.dw 0x1A3 ;
.dw 0xEFE7 ;
.dw 0x63C5 ;
.dw 0xEFE8 ;
.dw 0x7E4F ;
.dw 0xEFE9 ;
.dw 0x4935 ;
.dw 0xEFEA ;
.dw 0xB66F ;
.dw 0xEFEB ;
.dw 0x3617 ;
.dw 0xEFEC ;
.dw 0xCB83 ;
.dw 0xEFED ;
.dw 0x1F03 ;
.dw 0xEFEE ;
.dw 0x1E89 ;
.dw 0xEFEF ;
.dw 0x25FF ;
.dw 0xEFF0 ;
.dw 0x872B ;
.dw 0xEFF1 ;
.dw 0x369D ;
.dw 0xEFF2 ;
.dw 0x37FB ;
.dw 0xEFF3 ;
.dw 0x3ACB ;
.dw 0xEFF4 ;
.dw 0x8F81 ;
.dw 0xEFF5 ;
.dw 0x4199 ;
.dw 0xEFF6 ;
.dw 0x6FA1 ;
.dw 0xEFF7 ;
.dw 0xC99 ;
.dw 0xEFF8 ;
.dw 0x6A5F ;
.dw 0xEFF9 ;
.dw 0xC007 ;
.dw 0xEFFA ;
.dw 0x8433 ;
.dw 0xEFFB ;
.dw 0xC585 ;
.dw 0xEFFC ;
.dw 0xDA23 ;
.dw 0xEFFD ;
.dw 0x3065 ;
.dw 0xEFFE ;
.dw 0x82E1 ;
.dw 0xEFFF ;
.dw 0xFE6D ;
.dw 0xC700 ;
.dw 0xE7FB ;
.dw 0xC701 ;
.dw 0x4717 ;
.dw 0xC702 ;
.dw 0xF573 ;
.dw 0xC703 ;
.dw 0xAF1D ;
.dw 0xC704 ;
.dw 0x3BC7 ;
.dw 0xC705 ;
.dw 0x2563 ;
.dw 0xC706 ;
.dw 0xD9D3 ;
.dw 0xC707 ;
.dw 0xEA0F ;
.dw 0xC708 ;
.dw 0x1969 ;
.dw 0xC709 ;
.dw 0x7E5 ;
.dw 0xC70A ;
.dw 0x7B31 ;
.dw 0xC70B ;
.dw 0x9BA1 ;
.dw 0xC70C ;
.dw 0xDBA3 ;
.dw 0xC70D ;
.dw 0x6489 ;
.dw 0xC70E ;
.dw 0xC499 ;
.dw 0xC70F ;
.dw 0x4CD ;
.dw 0xC710 ;
.dw 0x446B ;
.dw 0xC711 ;
.dw 0xF003 ;
.dw 0xC712 ;
.dw 0x24FF ;
.dw 0xC713 ;
.dw 0x295D ;
.dw 0xC714 ;
.dw 0x7AC3 ;
.dw 0xC715 ;
.dw 0x82C5 ;
.dw 0xC716 ;
.dw 0x9CED ;
.dw 0xC717 ;
.dw 0xE9A9 ;
.dw 0xC718 ;
.dw 0xE15 ;
.dw 0xC719 ;
.dw 0x557B ;
.dw 0xC71A ;
.dw 0xD83 ;
.dw 0xC71B ;
.dw 0xFFCD ;
.dw 0xC71C ;
.dw 0xD70B ;
.dw 0xC71D ;
.dw 0x8CFD ;
.dw 0xC71E ;
.dw 0x6121 ;
.dw 0xC71F ;
.dw 0x985F ;
.dw 0xC720 ;
.dw 0xDDD ;
.dw 0xC721 ;
.dw 0x8DCF ;
.dw 0xC722 ;
.dw 0xA579 ;
.dw 0xC723 ;
.dw 0xBEA9 ;
.dw 0xC724 ;
.dw 0x6E39 ;
.dw 0xC725 ;
.dw 0xF0F ;
.dw 0xC726 ;
.dw 0xAF23 ;
.dw 0xC727 ;
.dw 0x5461 ;
.dw 0xC728 ;
.dw 0xC08B ;
.dw 0xC729 ;
.dw 0x64F9 ;
.dw 0xC72A ;
.dw 0x5EBB ;
.dw 0xC72B ;
.dw 0xCCE3 ;
.dw 0xC72C ;
.dw 0xA0E1 ;
.dw 0xC72D ;
.dw 0xFAD1 ;
.dw 0xC72E ;
.dw 0x1F75 ;
.dw 0xC72F ;
.dw 0x63DF ;
.dw 0xC730 ;
.dw 0xDB3D ;
.dw 0xC731 ;
.dw 0x7469 ;
.dw 0xC732 ;
.dw 0xB735 ;
.dw 0xC733 ;
.dw 0x7A1 ;
.dw 0xC734 ;
.dw 0x356F ;
.dw 0xC735 ;
.dw 0x6F0F ;
.dw 0xC736 ;
.dw 0x2F ;
.dw 0xC737 ;
.dw 0xAEB9 ;
.dw 0xC738 ;
.dw 0xFE6D ;
.dw 0xC739 ;
.dw 0x5A0B ;
.dw 0xC73A ;
.dw 0xA3F1 ;
.dw 0xC73B ;
.dw 0x5143 ;
.dw 0xC73C ;
.dw 0x3B29 ;
.dw 0xC73D ;
.dw 0x5E91 ;
.dw 0xC73E ;
.dw 0x7007 ;
.dw 0xC73F ;
.dw 0x3D8D ;
.dw 0xC740 ;
.dw 0xC8EB ;
.dw 0xC741 ;
.dw 0xCF3F ;
.dw 0xC742 ;
.dw 0x5C0B ;
.dw 0xC743 ;
.dw 0x61 ;
.dw 0xC744 ;
.dw 0x4D2B ;
.dw 0xC745 ;
.dw 0x1713 ;
.dw 0xC746 ;
.dw 0xD945 ;
.dw 0xC747 ;
.dw 0x98AD ;
.dw 0xC748 ;
.dw 0x4AE3 ;
.dw 0xC749 ;
.dw 0x9FDF ;
.dw 0xC74A ;
.dw 0x83BB ;
.dw 0xC74B ;
.dw 0x2EC9 ;
.dw 0xC74C ;
.dw 0x356B ;
.dw 0xC74D ;
.dw 0xA84B ;
.dw 0xC74E ;
.dw 0xCCCD ;
.dw 0xC74F ;
.dw 0x727 ;
.dw 0xC750 ;
.dw 0xD8D1 ;
.dw 0xC751 ;
.dw 0x813F ;
.dw 0xC752 ;
.dw 0xB74F ;
.dw 0xC753 ;
.dw 0xE887 ;
.dw 0xC754 ;
.dw 0xEFB3 ;
.dw 0xC755 ;
.dw 0x2AE7 ;
.dw 0xC756 ;
.dw 0x3D1B ;
.dw 0xC757 ;
.dw 0xADBB ;
.dw 0xC758 ;
.dw 0x3E93 ;
.dw 0xC759 ;
.dw 0xC925 ;
.dw 0xC75A ;
.dw 0x762D ;
.dw 0xC75B ;
.dw 0x3AD7 ;
.dw 0xC75C ;
.dw 0xCAB ;
.dw 0xC75D ;
.dw 0xE78D ;
.dw 0xC75E ;
.dw 0x193F ;
.dw 0xC75F ;
.dw 0x8DE9 ;
.dw 0xC760 ;
.dw 0x5255 ;
.dw 0xC761 ;
.dw 0x4D7 ;
.dw 0xC762 ;
.dw 0x6DD7 ;
.dw 0xC763 ;
.dw 0x2333 ;
.dw 0xC764 ;
.dw 0x74CF ;
.dw 0xC765 ;
.dw 0x5DDB ;
.dw 0xC766 ;
.dw 0x47E5 ;
.dw 0xC767 ;
.dw 0x64E1 ;
.dw 0xC768 ;
.dw 0xE7A1 ;
.dw 0xC769 ;
.dw 0x700B ;
.dw 0xC76A ;
.dw 0x24E1 ;
.dw 0xC76B ;
.dw 0x5E49 ;
.dw 0xC76C ;
.dw 0x8B73 ;
.dw 0xC76D ;
.dw 0x2B65 ;
.dw 0xC76E ;
.dw 0x253 ;
.dw 0xC76F ;
.dw 0x6A93 ;
.dw 0xC770 ;
.dw 0x225B ;
.dw 0xC771 ;
.dw 0x4BF5 ;
.dw 0xC772 ;
.dw 0x5F9 ;
.dw 0xC773 ;
.dw 0x1701 ;
.dw 0xC774 ;
.dw 0xB1C3 ;
.dw 0xC775 ;
.dw 0xD2BD ;
.dw 0xC776 ;
.dw 0x8F5D ;
.dw 0xC777 ;
.dw 0xF09F ;
.dw 0xC778 ;
.dw 0x29B7 ;
.dw 0xC779 ;
.dw 0x163D ;
.dw 0xC77A ;
.dw 0xCAE9 ;
.dw 0xC77B ;
.dw 0x757B ;
.dw 0xC77C ;
.dw 0x29C5 ;
.dw 0xC77D ;
.dw 0x6263 ;
.dw 0xC77E ;
.dw 0x5E7D ;
.dw 0xC77F ;
.dw 0xE161 ;
.dw 0xC780 ;
.dw 0x3B49 ;
.dw 0xC781 ;
.dw 0xA005 ;
.dw 0xC782 ;
.dw 0x478D ;
.dw 0xC783 ;
.dw 0xE0F ;
.dw 0xC784 ;
.dw 0x5955 ;
.dw 0xC785 ;
.dw 0xFBD9 ;
.dw 0xC786 ;
.dw 0x82B7 ;
.dw 0xC787 ;
.dw 0x1EEF ;
.dw 0xC788 ;
.dw 0x1DF9 ;
.dw 0xC789 ;
.dw 0x4E9 ;
.dw 0xC78A ;
.dw 0x94DD ;
.dw 0xC78B ;
.dw 0x304D ;
.dw 0xC78C ;
.dw 0x6D27 ;
.dw 0xC78D ;
.dw 0x3A93 ;
.dw 0xC78E ;
.dw 0x8DB3 ;
.dw 0xC78F ;
.dw 0xC213 ;
.dw 0xC790 ;
.dw 0xF507 ;
.dw 0xC791 ;
.dw 0x81F9 ;
.dw 0xC792 ;
.dw 0x9BE7 ;
.dw 0xC793 ;
.dw 0x15FD ;
.dw 0xC794 ;
.dw 0x5BCB ;
.dw 0xC795 ;
.dw 0x7AFF ;
.dw 0xC796 ;
.dw 0xCAA9 ;
.dw 0xC797 ;
.dw 0x3951 ;
.dw 0xC798 ;
.dw 0x730D ;
.dw 0xC799 ;
.dw 0x2CBF ;
.dw 0xC79A ;
.dw 0xD3 ;
.dw 0xC79B ;
.dw 0xF21D ;
.dw 0xC79C ;
.dw 0x48A3 ;
.dw 0xC79D ;
.dw 0x183 ;
.dw 0xC79E ;
.dw 0xD96D ;
.dw 0xC79F ;
.dw 0x47E7 ;
.dw 0xC7A0 ;
.dw 0x6CF9 ;
.dw 0xC7A1 ;
.dw 0x8A3D ;
.dw 0xC7A2 ;
.dw 0x6DDD ;
.dw 0xC7A3 ;
.dw 0xDFE7 ;
.dw 0xC7A4 ;
.dw 0x46EB ;
.dw 0xC7A5 ;
.dw 0x17D ;
.dw 0xC7A6 ;
.dw 0xA96B ;
.dw 0xC7A7 ;
.dw 0xE4C5 ;
.dw 0xC7A8 ;
.dw 0xCD17 ;
.dw 0xC7A9 ;
.dw 0x5ED ;
.dw 0xC7AA ;
.dw 0x3E5F ;
.dw 0xC7AB ;
.dw 0xB1C9 ;
.dw 0xC7AC ;
.dw 0x7CBB ;
.dw 0xC7AD ;
.dw 0x8443 ;
.dw 0xC7AE ;
.dw 0xD4A1 ;
.dw 0xC7AF ;
.dw 0xF999 ;
.dw 0xC7B0 ;
.dw 0xE607 ;
.dw 0xC7B1 ;
.dw 0x48BF ;
.dw 0xC7B2 ;
.dw 0x89C7 ;
.dw 0xC7B3 ;
.dw 0xA06D ;
.dw 0xC7B4 ;
.dw 0xA5FD ;
.dw 0xC7B5 ;
.dw 0x3021 ;
.dw 0xC7B6 ;
.dw 0x5AAF ;
.dw 0xC7B7 ;
.dw 0x1C7 ;
.dw 0xC7B8 ;
.dw 0x25C1 ;
.dw 0xC7B9 ;
.dw 0x701F ;
.dw 0xC7BA ;
.dw 0x8E99 ;
.dw 0xC7BB ;
.dw 0xD9AF ;
.dw 0xC7BC ;
.dw 0xF775 ;
.dw 0xC7BD ;
.dw 0xEF5D ;
.dw 0xC7BE ;
.dw 0xBBC3 ;
.dw 0xC7BF ;
.dw 0x8969 ;
.dw 0xC7C0 ;
.dw 0x2895 ;
.dw 0xC7C1 ;
.dw 0x24ED ;
.dw 0xC7C2 ;
.dw 0x7D79 ;
.dw 0xC7C3 ;
.dw 0xEFA9 ;
.dw 0xC7C4 ;
.dw 0x61C3 ;
.dw 0xC7C5 ;
.dw 0x7737 ;
.dw 0xC7C6 ;
.dw 0x73AD ;
.dw 0xC7C7 ;
.dw 0x8C53 ;
.dw 0xC7C8 ;
.dw 0x2C2D ;
.dw 0xC7C9 ;
.dw 0x9283 ;
.dw 0xC7CA ;
.dw 0xA419 ;
.dw 0xC7CB ;
.dw 0x27AD ;
.dw 0xC7CC ;
.dw 0x345B ;
.dw 0xC7CD ;
.dw 0xAEE3 ;
.dw 0xC7CE ;
.dw 0xD4CB ;
.dw 0xC7CF ;
.dw 0xB513 ;
.dw 0xC7D0 ;
.dw 0xE289 ;
.dw 0xC7D1 ;
.dw 0x3DB5 ;
.dw 0xC7D2 ;
.dw 0xF849 ;
.dw 0xC7D3 ;
.dw 0xA93F ;
.dw 0xC7D4 ;
.dw 0x2087 ;
.dw 0xC7D5 ;
.dw 0xF68F ;
.dw 0xC7D6 ;
.dw 0x431B ;
.dw 0xC7D7 ;
.dw 0x7BEB ;
.dw 0xC7D8 ;
.dw 0xA503 ;
.dw 0xC7D9 ;
.dw 0xBBC9 ;
.dw 0xC7DA ;
.dw 0x2F1 ;
.dw 0xC7DB ;
.dw 0x8D1F ;
.dw 0xC7DC ;
.dw 0x9C6F ;
.dw 0xC7DD ;
.dw 0x4E61 ;
.dw 0xC7DE ;
.dw 0xCF2F ;
.dw 0xC7DF ;
.dw 0x25D7 ;
.dw 0xC7E0 ;
.dw 0x74B ;
.dw 0xC7E1 ;
.dw 0x4983 ;
.dw 0xC7E2 ;
.dw 0x2B0D ;
.dw 0xC7E3 ;
.dw 0xCC47 ;
.dw 0xC7E4 ;
.dw 0xA60D ;
.dw 0xC7E5 ;
.dw 0x5D77 ;
.dw 0xC7E6 ;
.dw 0x312F ;
.dw 0xC7E7 ;
.dw 0xA38B ;
.dw 0xC7E8 ;
.dw 0xCA6B ;
.dw 0xC7E9 ;
.dw 0x421D ;
.dw 0xC7EA ;
.dw 0x60B7 ;
.dw 0xC7EB ;
.dw 0xEE7 ;
.dw 0xC7EC ;
.dw 0xE637 ;
.dw 0xC7ED ;
.dw 0x58E7 ;
.dw 0xC7EE ;
.dw 0x23E1 ;
.dw 0xC7EF ;
.dw 0x5073 ;
.dw 0xC7F0 ;
.dw 0x2FC1 ;
.dw 0xC7F1 ;
.dw 0x7649 ;
.dw 0xC7F2 ;
.dw 0x281D ;
.dw 0xC7F3 ;
.dw 0x5B63 ;
.dw 0xC7F4 ;
.dw 0x339B ;
.dw 0xC7F5 ;
.dw 0xCABD ;
.dw 0xC7F6 ;
.dw 0x1FA1 ;
.dw 0xC7F7 ;
.dw 0x91B3 ;
.dw 0xC7F8 ;
.dw 0xAC07 ;
.dw 0xC7F9 ;
.dw 0x632F ;
.dw 0xC7FA ;
.dw 0x485 ;
.dw 0xC7FB ;
.dw 0xA55F ;
.dw 0xC7FC ;
.dw 0x75BD ;
.dw 0xC7FD ;
.dw 0x38FF ;
.dw 0xC7FE ;
.dw 0x755D ;
.dw 0xC7FF ;
.dw 0x5523 ;
.dw 0xE0C0 ;
.dw 0x0000 ;
.dw 0xE0A0 ;
.dw 0x8000 ;
.dw 0xE1A0 ;
.dw 0x0 ;
.dw 0xC401 ;
.dw 0x4000 ;
.dw 0xC404 ;
.dw 0xC000 ;
.dw 0xC406 ;
.dw 0xC000 ;
.dw 0xC407 ;
.dw 0xC000 ;
.dw 0xC40A ;
.dw 0x8000 ;
.dw 0xC40A ;
.dw 0xC000 ;
.dw 0xC40C ;
.dw 0x8000 ;
.dw 0xC40E ;
.dw 0x8000 ;
.dw 0xC40F ;
.dw 0x0 ;
.dw 0xC40F ;
.dw 0x4000 ;
.dw 0xC40F ;
.dw 0x8000 ;
.dw 0xC410 ;
.dw 0x8000 ;
.dw 0xC411 ;
.dw 0x8000 ;
.dw 0xC411 ;
.dw 0xC000 ;
.dw 0xC412 ;
.dw 0x4000 ;
.dw 0xC412 ;
.dw 0x8000 ;
.dw 0xC413 ;
.dw 0x0 ;
.dw 0xC413 ;
.dw 0x4000 ;
.dw 0xC413 ;
.dw 0x8000 ;
.dw 0xC413 ;
.dw 0xC000 ;
.dw 0xC414 ;
.dw 0x8000 ;
.dw 0xC414 ;
.dw 0xC000 ;
.dw 0xC415 ;
.dw 0x8000 ;
.dw 0xC415 ;
.dw 0xC000 ;
.dw 0xC418 ;
.dw 0x8000 ;
.dw 0xC418 ;
.dw 0xC000 ;
.dw 0xC417 ;
.dw 0x4000 ;
.dw 0xC417 ;
.dw 0x8000 ;
.dw 0xC417 ;
.dw 0xC000 ;
.dw 0xC419 ;
.dw 0x0 ;
.dw 0xC419 ;
.dw 0x4000 ;
.dw 0xC419 ;
.dw 0x8000 ;
.dw 0xC419 ;
.dw 0xC000 ;
.dw 0xC41A ;
.dw 0x0 ;
.dw 0xC41A ;
.dw 0x4000 ;
.dw 0xC41A ;
.dw 0x8000 ;
.dw 0xC41A ;
.dw 0xC000 ;
.dw 0xC41B ;
.dw 0x0 ;
.dw 0xC41B ;
.dw 0x4000 ;
.dw 0xC41B ;
.dw 0x8000 ;
.dw 0xC41B ;
.dw 0xC000 ;
.dw 0xC41C ;
.dw 0x0 ;
.dw 0xC41C ;
.dw 0x4000 ;
.dw 0xC41C ;
.dw 0x8000 ;
.dw 0xC41C ;
.dw 0xC000 ;
.dw 0xC41D ;
.dw 0x0 ;
.dw 0xC41D ;
.dw 0x4000 ;
.dw 0xC41D ;
.dw 0x8000 ;
.dw 0xC41D ;
.dw 0xC000 ;
.dw 0xC41E ;
.dw 0x0 ;
.dw 0xC41E ;
.dw 0x4000 ;
.dw 0xC41E ;
.dw 0x8000 ;
.dw 0xC41E ;
.dw 0xC000 ;
.dw 0xC41F ;
.dw 0x0 ;
.dw 0xC41F ;
.dw 0x4000 ;
.dw 0xC41F ;
.dw 0x8000 ;
.dw 0xC41F ;
.dw 0xC000 ;
.dw 0xC401 ;
.dw 0x0 ;
.dw 0xC401 ;
.dw 0x240 ;
.dw 0xC401 ;
.dw 0x480 ;
.dw 0xC401 ;
.dw 0x6C0 ;
.dw 0xC401 ;
.dw 0x900 ;
.dw 0xC401 ;
.dw 0xB40 ;
.dw 0xC401 ;
.dw 0xD80 ;
.dw 0xC401 ;
.dw 0xFC0 ;
.dw 0xC401 ;
.dw 0x8000 ;
.dw 0xC401 ;
.dw 0x8240 ;
.dw 0xC401 ;
.dw 0x8480 ;
.dw 0xC401 ;
.dw 0x86C0 ;
.dw 0xC401 ;
.dw 0x8900 ;
.dw 0xC401 ;
.dw 0x8B40 ;
.dw 0xC401 ;
.dw 0x8D80 ;
.dw 0xC401 ;
.dw 0x8FC0 ;
.dw 0xC401 ;
.dw 0xC000 ;
.dw 0xC401 ;
.dw 0xC240 ;
.dw 0xC401 ;
.dw 0xC480 ;
.dw 0xC401 ;
.dw 0xC6C0 ;
.dw 0xC401 ;
.dw 0xC900 ;
.dw 0xC401 ;
.dw 0xCB40 ;
.dw 0xC401 ;
.dw 0xCD80 ;
.dw 0xC401 ;
.dw 0xCFC0 ;
.dw 0xC404 ;
.dw 0x8000 ;
.dw 0xC404 ;
.dw 0x8240 ;
.dw 0xC404 ;
.dw 0x8480 ;
.dw 0xC404 ;
.dw 0x86C0 ;
.dw 0xC404 ;
.dw 0x8900 ;
.dw 0xC404 ;
.dw 0x8B40 ;
.dw 0xC404 ;
.dw 0x8D80 ;
.dw 0xC404 ;
.dw 0x8FC0 ;
.dw 0xC40C ;
.dw 0x4000 ;
.dw 0xC40C ;
.dw 0x4240 ;
.dw 0xC40C ;
.dw 0x4480 ;
.dw 0xC40C ;
.dw 0x46C0 ;
.dw 0xC40C ;
.dw 0x4900 ;
.dw 0xC40C ;
.dw 0x4B40 ;
.dw 0xC40C ;
.dw 0x4D80 ;
.dw 0xC40C ;
.dw 0x4FC0 ;
.dw 0xC40D ;
.dw 0x0 ;
.dw 0xC40D ;
.dw 0x240 ;
.dw 0xC40D ;
.dw 0x480 ;
.dw 0xC40D ;
.dw 0x6C0 ;
.dw 0xC40D ;
.dw 0x900 ;
.dw 0xC40D ;
.dw 0xB40 ;
.dw 0xC40D ;
.dw 0xD80 ;
.dw 0xC40D ;
.dw 0xFC0 ;
.dw 0xC40D ;
.dw 0x4000 ;
.dw 0xC40D ;
.dw 0x4240 ;
.dw 0xC40D ;
.dw 0x4480 ;
.dw 0xC40D ;
.dw 0x46C0 ;
.dw 0xC40D ;
.dw 0x4900 ;
.dw 0xC40D ;
.dw 0x4B40 ;
.dw 0xC40D ;
.dw 0x4D80 ;
.dw 0xC40D ;
.dw 0x4FC0 ;
.dw 0xC40D ;
.dw 0x8000 ;
.dw 0xC40D ;
.dw 0x8240 ;
.dw 0xC40D ;
.dw 0x8480 ;
.dw 0xC40D ;
.dw 0x86C0 ;
.dw 0xC40D ;
.dw 0x8900 ;
.dw 0xC40D ;
.dw 0x8B40 ;
.dw 0xC40D ;
.dw 0x8D80 ;
.dw 0xC40D ;
.dw 0x8FC0 ;
.dw 0xC40D ;
.dw 0xC000 ;
.dw 0xC40D ;
.dw 0xC240 ;
.dw 0xC40D ;
.dw 0xC480 ;
.dw 0xC40D ;
.dw 0xC6C0 ;
.dw 0xC40D ;
.dw 0xC900 ;
.dw 0xC40D ;
.dw 0xCB40 ;
.dw 0xC40D ;
.dw 0xCD80 ;
.dw 0xC40D ;
.dw 0xCFC0 ;
.dw 0xC411 ;
.dw 0x0 ;
.dw 0xC411 ;
.dw 0x240 ;
.dw 0xC411 ;
.dw 0x480 ;
.dw 0xC411 ;
.dw 0x6C0 ;
.dw 0xC411 ;
.dw 0x900 ;
.dw 0xC411 ;
.dw 0xB40 ;
.dw 0xC411 ;
.dw 0xD80 ;
.dw 0xC411 ;
.dw 0xFC0 ;
.dw 0xC411 ;
.dw 0x4000 ;
.dw 0xC411 ;
.dw 0x4240 ;
.dw 0xC411 ;
.dw 0x4480 ;
.dw 0xC411 ;
.dw 0x46C0 ;
.dw 0xC411 ;
.dw 0x4900 ;
.dw 0xC411 ;
.dw 0x4B40 ;
.dw 0xC411 ;
.dw 0x4D80 ;
.dw 0xC411 ;
.dw 0x4FC0 ;
.dw 0xC415 ;
.dw 0x0 ;
.dw 0xC415 ;
.dw 0x240 ;
.dw 0xC415 ;
.dw 0x480 ;
.dw 0xC415 ;
.dw 0x6C0 ;
.dw 0xC415 ;
.dw 0x900 ;
.dw 0xC415 ;
.dw 0xB40 ;
.dw 0xC415 ;
.dw 0xD80 ;
.dw 0xC415 ;
.dw 0xFC0 ;
.dw 0xC415 ;
.dw 0x4000 ;
.dw 0xC415 ;
.dw 0x4240 ;
.dw 0xC415 ;
.dw 0x4480 ;
.dw 0xC415 ;
.dw 0x46C0 ;
.dw 0xC415 ;
.dw 0x4900 ;
.dw 0xC415 ;
.dw 0x4B40 ;
.dw 0xC415 ;
.dw 0x4D80 ;
.dw 0xC415 ;
.dw 0x4FC0 ;
.dw 0xC418 ;
.dw 0x4000 ;
.dw 0xC418 ;
.dw 0x4240 ;
.dw 0xC418 ;
.dw 0x4480 ;
.dw 0xC418 ;
.dw 0x46C0 ;
.dw 0xC418 ;
.dw 0x4900 ;
.dw 0xC418 ;
.dw 0x4B40 ;
.dw 0xC418 ;
.dw 0x4D80 ;
.dw 0xC418 ;
.dw 0x4FC0 ;
.dw 0xC412 ;
.dw 0x9 ;
.dw 0xC412 ;
.dw 0x1B ;
.dw 0xC412 ;
.dw 0x24 ;
.dw 0xC412 ;
.dw 0x2D ;
.dw 0xC412 ;
.dw 0x36 ;
.dw 0xC412 ;
.dw 0x3F ;
.dw 0xC414 ;
.dw 0x9 ;
.dw 0xC414 ;
.dw 0x1B ;
.dw 0xC414 ;
.dw 0x24 ;
.dw 0xC414 ;
.dw 0x2D ;
.dw 0xC414 ;
.dw 0x36 ;
.dw 0xC414 ;
.dw 0x3F ;
.dw 0xC414 ;
.dw 0x4009 ;
.dw 0xC414 ;
.dw 0x401B ;
.dw 0xC414 ;
.dw 0x4024 ;
.dw 0xC414 ;
.dw 0x402D ;
.dw 0xC414 ;
.dw 0x4036 ;
.dw 0xC414 ;
.dw 0x403F ;
.dw 0xC415 ;
.dw 0x9 ;
.dw 0xC415 ;
.dw 0x1B ;
.dw 0xC415 ;
.dw 0x24 ;
.dw 0xC415 ;
.dw 0x2D ;
.dw 0xC415 ;
.dw 0x36 ;
.dw 0xC415 ;
.dw 0x3F ;
.dw 0xC415 ;
.dw 0x4009 ;
.dw 0xC415 ;
.dw 0x401B ;
.dw 0xC415 ;
.dw 0x4024 ;
.dw 0xC415 ;
.dw 0x402D ;
.dw 0xC415 ;
.dw 0x4036 ;
.dw 0xC415 ;
.dw 0x403F ;
.dw 0xC416 ;
.dw 0x9 ;
.dw 0xC416 ;
.dw 0x1B ;
.dw 0xC416 ;
.dw 0x24 ;
.dw 0xC416 ;
.dw 0x2D ;
.dw 0xC416 ;
.dw 0x36 ;
.dw 0xC416 ;
.dw 0x3F ;
.dw 0xC416 ;
.dw 0x4009 ;
.dw 0xC416 ;
.dw 0x401B ;
.dw 0xC416 ;
.dw 0x4024 ;
.dw 0xC416 ;
.dw 0x402D ;
.dw 0xC416 ;
.dw 0x4036 ;
.dw 0xC416 ;
.dw 0x403F ;
.dw 0xC416 ;
.dw 0x8009 ;
.dw 0xC416 ;
.dw 0x801B ;
.dw 0xC416 ;
.dw 0x8024 ;
.dw 0xC416 ;
.dw 0x802D ;
.dw 0xC416 ;
.dw 0x8036 ;
.dw 0xC416 ;
.dw 0x803F ;
.dw 0xC416 ;
.dw 0xC009 ;
.dw 0xC416 ;
.dw 0xC01B ;
.dw 0xC416 ;
.dw 0xC024 ;
.dw 0xC416 ;
.dw 0xC02D ;
.dw 0xC416 ;
.dw 0xC036 ;
.dw 0xC416 ;
.dw 0xC03F ;
.dw 0xC417 ;
.dw 0x9 ;
.dw 0xC417 ;
.dw 0x1B ;
.dw 0xC417 ;
.dw 0x24 ;
.dw 0xC417 ;
.dw 0x2D ;
.dw 0xC417 ;
.dw 0x36 ;
.dw 0xC417 ;
.dw 0x3F ;
.dw 0xC418 ;
.dw 0x4009 ;
.dw 0xC418 ;
.dw 0x401B ;
.dw 0xC418 ;
.dw 0x4024 ;
.dw 0xC418 ;
.dw 0x402D ;
.dw 0xC418 ;
.dw 0x4036 ;
.dw 0xC418 ;
.dw 0x403F ;
.dw 0xC600 ;
.dw 0xC000 ;
.dw 0xC601 ;
.dw 0xC000 ;
.dw 0xC603 ;
.dw 0xC000 ;
.dw 0xC605 ;
.dw 0xC000 ;
.dw 0xC608 ;
.dw 0xC000 ;
.dw 0xC60B ;
.dw 0xC000 ;
.dw 0xC60C ;
.dw 0xC000 ;
.dw 0xC60D ;
.dw 0xC000 ;
.dw 0xC606 ;
.dw 0x8000 ;
.dw 0xC608 ;
.dw 0x8000 ;
.dw 0xC60B ;
.dw 0x8000 ;
.dw 0xC60C ;
.dw 0x8000 ;
.dw 0xC60E ;
.dw 0x0 ;
.dw 0xC60E ;
.dw 0x4000 ;
.dw 0xC60E ;
.dw 0x8000 ;
.dw 0xC60E ;
.dw 0xC000 ;
.dw 0xC60F ;
.dw 0x0 ;
.dw 0xC60F ;
.dw 0x4000 ;
.dw 0xC60F ;
.dw 0x8000 ;
.dw 0xC60F ;
.dw 0xC000 ;
.dw 0xC610 ;
.dw 0x0 ;
.dw 0xC610 ;
.dw 0x4000 ;
.dw 0xC610 ;
.dw 0x8000 ;
.dw 0xC610 ;
.dw 0xC000 ;
.dw 0xC611 ;
.dw 0x0 ;
.dw 0xC611 ;
.dw 0x4000 ;
.dw 0xC611 ;
.dw 0x8000 ;
.dw 0xC611 ;
.dw 0xC000 ;
.dw 0xC612 ;
.dw 0x0 ;
.dw 0xC612 ;
.dw 0x4000 ;
.dw 0xC612 ;
.dw 0x8000 ;
.dw 0xC612 ;
.dw 0xC000 ;
.dw 0xC613 ;
.dw 0x0 ;
.dw 0xC613 ;
.dw 0x4000 ;
.dw 0xC613 ;
.dw 0x8000 ;
.dw 0xC613 ;
.dw 0xC000 ;
.dw 0xC614 ;
.dw 0x0 ;
.dw 0xC614 ;
.dw 0x4000 ;
.dw 0xC614 ;
.dw 0x8000 ;
.dw 0xC614 ;
.dw 0xC000 ;
.dw 0xC615 ;
.dw 0x0 ;
.dw 0xC615 ;
.dw 0x4000 ;
.dw 0xC615 ;
.dw 0x8000 ;
.dw 0xC615 ;
.dw 0xC000 ;
.dw 0xC616 ;
.dw 0x0 ;
.dw 0xC616 ;
.dw 0x4000 ;
.dw 0xC616 ;
.dw 0x8000 ;
.dw 0xC616 ;
.dw 0xC000 ;
.dw 0xC617 ;
.dw 0x0 ;
.dw 0xC617 ;
.dw 0x4000 ;
.dw 0xC617 ;
.dw 0x8000 ;
.dw 0xC617 ;
.dw 0xC000 ;
.dw 0xC618 ;
.dw 0x0 ;
.dw 0xC618 ;
.dw 0x4000 ;
.dw 0xC618 ;
.dw 0x8000 ;
.dw 0xC618 ;
.dw 0xC000 ;
.dw 0xC619 ;
.dw 0x0 ;
.dw 0xC619 ;
.dw 0x4000 ;
.dw 0xC619 ;
.dw 0x8000 ;
.dw 0xC619 ;
.dw 0xC000 ;
.dw 0xC61A ;
.dw 0x0 ;
.dw 0xC61A ;
.dw 0x4000 ;
.dw 0xC61A ;
.dw 0x8000 ;
.dw 0xC61A ;
.dw 0xC000 ;
.dw 0xC61B ;
.dw 0x0 ;
.dw 0xC61B ;
.dw 0x4000 ;
.dw 0xC61B ;
.dw 0x8000 ;
.dw 0xC61B ;
.dw 0xC000 ;
.dw 0xC61C ;
.dw 0x0 ;
.dw 0xC61C ;
.dw 0x4000 ;
.dw 0xC61C ;
.dw 0x8000 ;
.dw 0xC61C ;
.dw 0xC000 ;
.dw 0xC61D ;
.dw 0x0 ;
.dw 0xC61D ;
.dw 0x4000 ;
.dw 0xC61D ;
.dw 0x8000 ;
.dw 0xC61D ;
.dw 0xC000 ;
.dw 0xC61E ;
.dw 0x0 ;
.dw 0xC61E ;
.dw 0x4000 ;
.dw 0xC61E ;
.dw 0x8000 ;
.dw 0xC61E ;
.dw 0xC000 ;
.dw 0xC61F ;
.dw 0x0 ;
.dw 0xC61F ;
.dw 0x4000 ;
.dw 0xC61F ;
.dw 0x8000 ;
.dw 0xC61F ;
.dw 0xC000 ;
.dw 0xC608 ;
.dw 0x0 ;
.dw 0xC608 ;
.dw 0x9 ;
.dw 0xC608 ;
.dw 0x12 ;
.dw 0xC608 ;
.dw 0x1B ;
.dw 0xC608 ;
.dw 0x24 ;
.dw 0xC608 ;
.dw 0x2D ;
.dw 0xC608 ;
.dw 0x36 ;
.dw 0xC608 ;
.dw 0x3F ;
.dw 0xC608 ;
.dw 0x4000 ;
.dw 0xC608 ;
.dw 0x4009 ;
.dw 0xC608 ;
.dw 0x4012 ;
.dw 0xC608 ;
.dw 0x401B ;
.dw 0xC608 ;
.dw 0x4024 ;
.dw 0xC608 ;
.dw 0x402D ;
.dw 0xC608 ;
.dw 0x4036 ;
.dw 0xC608 ;
.dw 0x403F ;
.dw 0xC680 ;
.dw 0xC000 ;
.dw 0xC681 ;
.dw 0xC000 ;
.dw 0xC683 ;
.dw 0xC000 ;
.dw 0xC684 ;
.dw 0x0 ;
.dw 0xC684 ;
.dw 0x4000 ;
.dw 0xC684 ;
.dw 0x8000 ;
.dw 0xC684 ;
.dw 0xC000 ;
.dw 0xC685 ;
.dw 0x0 ;
.dw 0xC685 ;
.dw 0x4000 ;
.dw 0xC685 ;
.dw 0x8000 ;
.dw 0xC685 ;
.dw 0xC000 ;
.dw 0xC686 ;
.dw 0x0 ;
.dw 0xC686 ;
.dw 0x4000 ;
.dw 0xC686 ;
.dw 0x8000 ;
.dw 0xC686 ;
.dw 0xC000 ;
.dw 0xC687 ;
.dw 0x0 ;
.dw 0xC687 ;
.dw 0x4000 ;
.dw 0xC687 ;
.dw 0x8000 ;
.dw 0xC687 ;
.dw 0xC000 ;
.dw 0xC688 ;
.dw 0x0 ;
.dw 0xC688 ;
.dw 0x4000 ;
.dw 0xC688 ;
.dw 0x8000 ;
.dw 0xC688 ;
.dw 0xC000 ;
.dw 0xC689 ;
.dw 0x0 ;
.dw 0xC689 ;
.dw 0x4000 ;
.dw 0xC689 ;
.dw 0x8000 ;
.dw 0xC689 ;
.dw 0xC000 ;
.dw 0xC68A ;
.dw 0x0 ;
.dw 0xC68A ;
.dw 0x4000 ;
.dw 0xC68A ;
.dw 0x8000 ;
.dw 0xC68A ;
.dw 0xC000 ;
.dw 0xC68B ;
.dw 0x0 ;
.dw 0xC68B ;
.dw 0x4000 ;
.dw 0xC68B ;
.dw 0x8000 ;
.dw 0xC68B ;
.dw 0xC000 ;
.dw 0xC68C ;
.dw 0x0 ;
.dw 0xC68C ;
.dw 0x4000 ;
.dw 0xC68C ;
.dw 0x8000 ;
.dw 0xC68C ;
.dw 0xC000 ;
.dw 0xC68D ;
.dw 0x0 ;
.dw 0xC68D ;
.dw 0x4000 ;
.dw 0xC68D ;
.dw 0x8000 ;
.dw 0xC68D ;
.dw 0xC000 ;
.dw 0xC68E ;
.dw 0x0 ;
.dw 0xC68E ;
.dw 0x4000 ;
.dw 0xC68E ;
.dw 0x8000 ;
.dw 0xC68E ;
.dw 0xC000 ;
.dw 0xC68F ;
.dw 0x0 ;
.dw 0xC68F ;
.dw 0x4000 ;
.dw 0xC68F ;
.dw 0x8000 ;
.dw 0xC68F ;
.dw 0xC000 ;
.dw 0xC690 ;
.dw 0x0 ;
.dw 0xC690 ;
.dw 0x4000 ;
.dw 0xC690 ;
.dw 0x8000 ;
.dw 0xC690 ;
.dw 0xC000 ;
.dw 0xC691 ;
.dw 0x0 ;
.dw 0xC691 ;
.dw 0x4000 ;
.dw 0xC691 ;
.dw 0x8000 ;
.dw 0xC691 ;
.dw 0xC000 ;
.dw 0xC692 ;
.dw 0x0 ;
.dw 0xC692 ;
.dw 0x4000 ;
.dw 0xC692 ;
.dw 0x8000 ;
.dw 0xC692 ;
.dw 0xC000 ;
.dw 0xC693 ;
.dw 0x0 ;
.dw 0xC693 ;
.dw 0x4000 ;
.dw 0xC693 ;
.dw 0x8000 ;
.dw 0xC693 ;
.dw 0xC000 ;
.dw 0xC694 ;
.dw 0x0 ;
.dw 0xC694 ;
.dw 0x4000 ;
.dw 0xC694 ;
.dw 0x8000 ;
.dw 0xC694 ;
.dw 0xC000 ;
.dw 0xC695 ;
.dw 0x0 ;
.dw 0xC695 ;
.dw 0x4000 ;
.dw 0xC695 ;
.dw 0x8000 ;
.dw 0xC695 ;
.dw 0xC000 ;
.dw 0xC696 ;
.dw 0x0 ;
.dw 0xC696 ;
.dw 0x4000 ;
.dw 0xC696 ;
.dw 0x8000 ;
.dw 0xC696 ;
.dw 0xC000 ;
.dw 0xC697 ;
.dw 0x0 ;
.dw 0xC697 ;
.dw 0x4000 ;
.dw 0xC697 ;
.dw 0x8000 ;
.dw 0xC697 ;
.dw 0xC000 ;
.dw 0xC698 ;
.dw 0x0 ;
.dw 0xC698 ;
.dw 0x4000 ;
.dw 0xC698 ;
.dw 0x8000 ;
.dw 0xC698 ;
.dw 0xC000 ;
.dw 0xC699 ;
.dw 0x0 ;
.dw 0xC699 ;
.dw 0x4000 ;
.dw 0xC699 ;
.dw 0x8000 ;
.dw 0xC699 ;
.dw 0xC000 ;
.dw 0xC69A ;
.dw 0x0 ;
.dw 0xC69A ;
.dw 0x4000 ;
.dw 0xC69A ;
.dw 0x8000 ;
.dw 0xC69A ;
.dw 0xC000 ;
.dw 0xC69B ;
.dw 0x0 ;
.dw 0xC69B ;
.dw 0x4000 ;
.dw 0xC69B ;
.dw 0x8000 ;
.dw 0xC69B ;
.dw 0xC000 ;
.dw 0xC69C ;
.dw 0x0 ;
.dw 0xC69C ;
.dw 0x4000 ;
.dw 0xC69C ;
.dw 0x8000 ;
.dw 0xC69C ;
.dw 0xC000 ;
.dw 0xC69D ;
.dw 0x0 ;
.dw 0xC69D ;
.dw 0x4000 ;
.dw 0xC69D ;
.dw 0x8000 ;
.dw 0xC69D ;
.dw 0xC000 ;
.dw 0xC69E ;
.dw 0x0 ;
.dw 0xC69E ;
.dw 0x4000 ;
.dw 0xC69E ;
.dw 0x8000 ;
.dw 0xC69E ;
.dw 0xC000 ;
.dw 0xC69F ;
.dw 0x0 ;
.dw 0xC69F ;
.dw 0x4000 ;
.dw 0xC69F ;
.dw 0x8000 ;
.dw 0xC69F ;
.dw 0xC000 ;
.dw 0xC008 ;
.dw 0x0 ;
.dw 0xC008 ;
.dw 0x40 ;
.dw 0xC008 ;
.dw 0xC0 ;
.dw 0xC008 ;
.dw 0x140 ;
.dw 0xC008 ;
.dw 0x1C0 ;
.dw 0xC020 ;
.dw 0x0 ;
.dw 0xC040 ;
.dw 0x0 ;
.dw 0xC0A0 ;
.dw 0x0 ;
.dw 0xC0C0 ;
.dw 0x0 ;
.dw 0xC0E0 ;
.dw 0x0 ;
.dw 0xC120 ;
.dw 0x0 ;
.dw 0xC140 ;
.dw 0x0 ;
.dw 0xC160 ;
.dw 0x0 ;
.dw 0xC180 ;
.dw 0x0 ;
.dw 0xC1A0 ;
.dw 0x0 ;
.dw 0xC1C0 ;
.dw 0x0 ;
.dw 0xC1E0 ;
.dw 0x0 ;
.dw 0xC060 ;
.dw 0x2000 ;
.dw 0xC0E0 ;
.dw 0x2000 ;
.dw 0xC140 ;
.dw 0x2000 ;
.dw 0xC1A0 ;
.dw 0x2000 ;
.dw 0xC1C0 ;
.dw 0x2000 ;
.dw 0xC1E0 ;
.dw 0x2000 ;
.dw 0xC064 ;
.dw 0x0 ;
.dw 0xC0E4 ;
.dw 0x0 ;
.dw 0xC144 ;
.dw 0x0 ;
.dw 0xC1A4 ;
.dw 0x0 ;
.dw 0xC1C4 ;
.dw 0x0 ;
.dw 0xC1E4 ;
.dw 0x0 ;
.dw 0xC064 ;
.dw 0x2000 ;
.dw 0xC0E4 ;
.dw 0x2000 ;
.dw 0xC144 ;
.dw 0x2000 ;
.dw 0xC1A4 ;
.dw 0x2000 ;
.dw 0xC1C4 ;
.dw 0x2000 ;
.dw 0xC1E4 ;
.dw 0x2000 ;
.dw 0xC048 ;
.dw 0x2000 ;
.dw 0xC068 ;
.dw 0x2000 ;
.dw 0xC0A8 ;
.dw 0x2000 ;
.dw 0xC0C8 ;
.dw 0x2000 ;
.dw 0xC0E8 ;
.dw 0x2000 ;
.dw 0xC148 ;
.dw 0x2000 ;
.dw 0xC168 ;
.dw 0x2000 ;
.dw 0xC188 ;
.dw 0x2000 ;
.dw 0xC1A8 ;
.dw 0x2000 ;
.dw 0xC1C8 ;
.dw 0x2000 ;
.dw 0xC1E8 ;
.dw 0x2000 ;
.dw 0xC04C ;
.dw 0x0 ;
.dw 0xC06C ;
.dw 0x0 ;
.dw 0xC0AC ;
.dw 0x0 ;
.dw 0xC0CC ;
.dw 0x0 ;
.dw 0xC0EC ;
.dw 0x0 ;
.dw 0xC14C ;
.dw 0x0 ;
.dw 0xC16C ;
.dw 0x0 ;
.dw 0xC18C ;
.dw 0x0 ;
.dw 0xC1AC ;
.dw 0x0 ;
.dw 0xC1CC ;
.dw 0x0 ;
.dw 0xC1EC ;
.dw 0x0 ;
.dw 0xC04C ;
.dw 0x2000 ;
.dw 0xC06C ;
.dw 0x2000 ;
.dw 0xC0AC ;
.dw 0x2000 ;
.dw 0xC0CC ;
.dw 0x2000 ;
.dw 0xC0EC ;
.dw 0x2000 ;
.dw 0xC14C ;
.dw 0x2000 ;
.dw 0xC16C ;
.dw 0x2000 ;
.dw 0xC18C ;
.dw 0x2000 ;
.dw 0xC1AC ;
.dw 0x2000 ;
.dw 0xC1CC ;
.dw 0x2000 ;
.dw 0xC1EC ;
.dw 0x2000 ;
.dw 0xC20C ;
.dw 0x2040 ;
.dw 0xC20C ;
.dw 0x20C0 ;
.dw 0xC20C ;
.dw 0x2140 ;
.dw 0xC20C ;
.dw 0x21C0 ;
.dw 0xC248 ;
.dw 0x2000 ;
.dw 0xC268 ;
.dw 0x2000 ;
.dw 0xC2A8 ;
.dw 0x2000 ;
.dw 0xC2C8 ;
.dw 0x2000 ;
.dw 0xC2E8 ;
.dw 0x2000 ;
.dw 0xC348 ;
.dw 0x2000 ;
.dw 0xC368 ;
.dw 0x2000 ;
.dw 0xC388 ;
.dw 0x2000 ;
.dw 0xC3A8 ;
.dw 0x2000 ;
.dw 0xC3C8 ;
.dw 0x2000 ;
.dw 0xC3E8 ;
.dw 0x2000 ;
.dw 0xC24C ;
.dw 0x0 ;
.dw 0xC26C ;
.dw 0x0 ;
.dw 0xC2AC ;
.dw 0x0 ;
.dw 0xC2CC ;
.dw 0x0 ;
.dw 0xC2EC ;
.dw 0x0 ;
.dw 0xC34C ;
.dw 0x0 ;
.dw 0xC36C ;
.dw 0x0 ;
.dw 0xC38C ;
.dw 0x0 ;
.dw 0xC3AC ;
.dw 0x0 ;
.dw 0xC3CC ;
.dw 0x0 ;
.dw 0xC3EC ;
.dw 0x0 ;
.dw 0xC24C ;
.dw 0x2000 ;
.dw 0xC26C ;
.dw 0x2000 ;
.dw 0xC2AC ;
.dw 0x2000 ;
.dw 0xC2CC ;
.dw 0x2000 ;
.dw 0xC2EC ;
.dw 0x2000 ;
.dw 0xC34C ;
.dw 0x2000 ;
.dw 0xC36C ;
.dw 0x2000 ;
.dw 0xC38C ;
.dw 0x2000 ;
.dw 0xC3AC ;
.dw 0x2000 ;
.dw 0xC3CC ;
.dw 0x2000 ;
.dw 0xC3EC ;
.dw 0x2000 ;
.dw 0xC20D ;
.dw 0x2800 ;
.dw 0xC20E ;
.dw 0x2800 ;
.dw 0xC20F ;
.dw 0x2800 ;
.dw 0xC20D ;
.dw 0x3000 ;
.dw 0xC20E ;
.dw 0x3000 ;
.dw 0xC20F ;
.dw 0x3000 ;
.dw 0xC20D ;
.dw 0x3800 ;
.dw 0xC20E ;
.dw 0x3800 ;
.dw 0xC20F ;
.dw 0x3800 ;
.dw 0xC200 ;
.dw 0x0 ;
.dw 0xC264 ;
.dw 0x2000 ;
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
// Xhandler counts all EXCAUSE = 0x21;
CHECKREG(r5, 2871); // count of all 16 bit UI's.
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
// 32 bit illegal opcode handler - skips bad instruction
// handler MADE LEAN and destructive so test runs more quckly
// se_undefinedinstruction1.dsp tests using a "nice" handler
// [--sp] = ASTAT; // save what we damage
// [--sp] = (r7 - r6);
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction
CC = r7 == r6;
IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave
// Also allow 0x22 for illegal instruction combinations (parallel)
R6 = 0x22;
CC = r7 == r6;
IF CC JUMP UNDEFINEDINSTRUCTION;
dbg_fail;
UNDEFINEDINSTRUCTION:
R7 = RETX; // Fix up return address
R7 += 4; // skip offending 32 bit instruction
RETX = r7; // and put back in RETX
R5 += 1; // Increment global counter
OUT:
// (r7 - r6) = [sp++];
// ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 2,356
|
sim/testsuite/bfin/c_regmv_pr_dr.s
|
//Original:/testcases/core/c_regmv_pr_dr/c_regmv_pr_dr.dsp
// Spec Reference: regmv preg to dreg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
//imm32 p0, 0x00000001;
imm32 p1, 0x10082001;
imm32 p2, 0x10092002;
imm32 p3, 0x100a2003;
imm32 p4, 0x100b2004;
imm32 p5, 0x100c2005;
imm32 sp, 0x100d2006;
imm32 fp, 0x100e2007;
//--------- Preg to dreg : Rx <= Px ------
R0 = P1;
R1 = P1;
R2 = P1;
R3 = P1;
R4 = P1;
R5 = P1;
R6 = P1;
R7 = P1;
CHECKREG r1, 0x10082001;
CHECKREG r2, 0x10082001;
CHECKREG r3, 0x10082001;
CHECKREG r4, 0x10082001;
CHECKREG r5, 0x10082001;
CHECKREG r6, 0x10082001;
CHECKREG r7, 0x10082001;
R0 = P2;
R1 = P2;
R2 = P2;
R3 = P2;
R4 = P2;
R5 = P2;
R6 = P2;
R7 = P2;
CHECKREG r0, 0x10092002;
CHECKREG r1, 0x10092002;
CHECKREG r2, 0x10092002;
CHECKREG r3, 0x10092002;
CHECKREG r4, 0x10092002;
CHECKREG r5, 0x10092002;
CHECKREG r6, 0x10092002;
CHECKREG r7, 0x10092002;
R0 = P3;
R1 = P3;
R2 = P3;
R3 = P3;
R4 = P3;
R5 = P3;
R6 = P3;
R7 = P3;
CHECKREG r1, 0x100a2003;
CHECKREG r2, 0x100a2003;
CHECKREG r3, 0x100a2003;
CHECKREG r4, 0x100a2003;
CHECKREG r5, 0x100a2003;
CHECKREG r6, 0x100a2003;
CHECKREG r7, 0x100a2003;
R0 = P4;
R1 = P4;
R2 = P4;
R3 = P4;
R4 = P4;
R5 = P4;
R6 = P4;
R7 = P4;
CHECKREG r0, 0x100b2004;
CHECKREG r1, 0x100b2004;
CHECKREG r2, 0x100b2004;
CHECKREG r3, 0x100b2004;
CHECKREG r4, 0x100b2004;
CHECKREG r5, 0x100b2004;
CHECKREG r6, 0x100b2004;
CHECKREG r7, 0x100b2004;
R1 = P5;
R2 = P5;
R3 = P5;
R4 = P5;
R5 = P5;
R6 = P5;
R7 = P5;
CHECKREG r1, 0x100c2005;
CHECKREG r2, 0x100c2005;
CHECKREG r3, 0x100c2005;
CHECKREG r4, 0x100c2005;
CHECKREG r5, 0x100c2005;
CHECKREG r6, 0x100c2005;
CHECKREG r7, 0x100c2005;
R0 = SP;
R1 = SP;
R2 = SP;
R3 = SP;
R4 = SP;
R5 = SP;
R6 = SP;
R7 = SP;
CHECKREG r0, 0x100d2006;
CHECKREG r1, 0x100d2006;
CHECKREG r2, 0x100d2006;
CHECKREG r3, 0x100d2006;
CHECKREG r4, 0x100d2006;
CHECKREG r5, 0x100d2006;
CHECKREG r6, 0x100d2006;
CHECKREG r7, 0x100d2006;
R0 = FP;
R1 = FP;
R2 = FP;
R3 = FP;
R4 = FP;
R5 = FP;
R6 = FP;
R7 = FP;
CHECKREG r1, 0x100e2007;
CHECKREG r2, 0x100e2007;
CHECKREG r3, 0x100e2007;
CHECKREG r4, 0x100e2007;
CHECKREG r5, 0x100e2007;
CHECKREG r6, 0x100e2007;
CHECKREG r7, 0x100e2007;
pass
|
stsp/binutils-ia16
| 1,711
|
sim/testsuite/bfin/c_loopsetup_preg_div2_lc1.s
|
//Original:/testcases/core/c_loopsetup_preg_div2_lc1/c_loopsetup_preg_div2_lc1.dsp
// Spec Reference: loopsetup preg lc1 / 2
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
P1 = 12;
P2 = 14;
P3 = 16;
P4 = 18;
P5 = 20;
SP = 22;
FP = 24;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start11 , end11 ) LC1 = P1 >> 1;
start11: R0 += 1;
R1 += -1;
end11: R2 += 1;
R3 += 1;
LSETUP ( start12 , end12 ) LC1 = P2 >> 1;
start12: R4 += 1;
end12: R5 += -1;
R3 += 1;
LSETUP ( start13 , end13 ) LC1 = P3 >> 1;
start13: R6 += 1;
end13: R7 += -1;
R3 += 1;
CHECKREG r0, 0x0000000B;
CHECKREG r1, 0x0000000A;
CHECKREG r2, 0x00000026;
CHECKREG r3, 0x00000033;
CHECKREG r4, 0x00000047;
CHECKREG r5, 0x00000049;
CHECKREG r6, 0x00000068;
CHECKREG r7, 0x00000068;
R0 = 0x06;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start14 , end14 ) LC1 = P4 >> 1;
start14: R0 += 1;
R1 += -1;
end14: R2 += 1;
R3 += 1;
LSETUP ( start15 , end15 ) LC1 = P5 >> 1;
start15: R4 += 1;
end15: R5 += -1;
R3 += 1;
LSETUP ( start16 , end16 ) LC1 = SP >> 1;
start16: R6 += 1;
end16: R7 += -1;
R3 += 1;
CHECKREG r0, 0x0000000F;
CHECKREG r1, 0x00000007;
CHECKREG r2, 0x00000029;
CHECKREG r3, 0x00000033;
CHECKREG r4, 0x0000004A;
CHECKREG r5, 0x00000046;
CHECKREG r6, 0x0000006B;
CHECKREG r7, 0x00000065;
LSETUP ( start17 , end17 ) LC1 = FP >> 1;
start17: R4 += 1;
end17: R5 += -1;
R3 += 1;
CHECKREG r0, 0x0000000F;
CHECKREG r1, 0x00000007;
CHECKREG r2, 0x00000029;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000056;
CHECKREG r5, 0x0000003A;
CHECKREG r6, 0x0000006B;
CHECKREG r7, 0x00000065;
pass
|
stsp/binutils-ia16
| 1,464
|
sim/testsuite/bfin/c_ldimmhalf_lz_pr.s
|
//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lz_pr/c_ldimmhalf_lz_pr.dsp
// Spec Reference: ldimmhalf lz preg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Preg
P1 = 0x0003 (Z);
P2 = 0x0005 (Z);
P3 = 0x0007 (Z);
P4 = 0x0009 (Z);
P5 = 0x000b (Z);
FP = 0x000d (Z);
SP = 0x000f (Z);
CHECKREG p1, 0x00000003;
CHECKREG p2, 0x00000005;
CHECKREG p3, 0x00000007;
CHECKREG p4, 0x00000009;
CHECKREG p5, 0x0000000b;
CHECKREG fp, 0x0000000d;
CHECKREG sp, 0x0000000f;
P1 = 0x0030 (Z);
P2 = 0x0050 (Z);
P3 = 0x0070 (Z);
P4 = 0x0090 (Z);
P5 = 0x00b0 (Z);
FP = 0x00d0 (Z);
SP = 0x00f0 (Z);
//CHECKREG p0, 0x00000010;
CHECKREG p1, 0x00000030;
CHECKREG p2, 0x00000050;
CHECKREG p3, 0x00000070;
CHECKREG p4, 0x00000090;
CHECKREG p5, 0x000000b0;
CHECKREG fp, 0x000000d0;
CHECKREG sp, 0x000000f0;
P1 = 0x0300 (Z);
P2 = 0x0500 (Z);
P3 = 0x0700 (Z);
P4 = 0x0900 (Z);
P5 = 0x0b00 (Z);
FP = 0x0d00 (Z);
SP = 0x0f00 (Z);
CHECKREG p1, 0x00000300;
CHECKREG p2, 0x00000500;
CHECKREG p3, 0x00000700;
CHECKREG p4, 0x00000900;
CHECKREG p5, 0x00000b00;
CHECKREG fp, 0x00000d00;
CHECKREG sp, 0x00000f00;
P1 = 0x3000 (Z);
P2 = 0x5000 (Z);
P3 = 0x7000 (Z);
P4 = 0x9000 (Z);
P5 = 0xb000 (Z);
FP = 0xd000 (Z);
SP = 0xf000 (Z);
CHECKREG p1, 0x00003000;
CHECKREG p2, 0x00005000;
CHECKREG p3, 0x00007000;
CHECKREG p4, 0x00009000;
CHECKREG p5, 0x0000b000;
CHECKREG fp, 0x0000d000;
CHECKREG sp, 0x0000f000;
pass
|
stsp/binutils-ia16
| 1,517
|
sim/testsuite/bfin/stk4.s
|
// load up some registers.
// setup up a global pointer table and load some state.
// save the machine state and clear some of the values.
// then restore and assert some of the values to ensure that
// we maintain consitent machine state.
# mach: bfin
.include "testutils.inc"
start
R0 = 1;
R1 = 2;
R2 = 3;
R3 = -7;
R4 = 4;
R5 = 5;
R6 = 6;
R7 = 7;
loadsym P0, a;
P1.L = 0x1000;
_DBG P0;
_DBG P1;
SP = P0;
FP = P0;
CALL try;
P1 = [ P0 ++ ];
P2 = [ P0 ++ ];
P0 += 4;
P4 = [ P0 ++ ];
P5 = [ P0 ++ ];
[ -- SP ] = ( R7:0, P5:0 );
_DBG SP;
_DBG FP;
R0 = R0 ^ R0;
R1 = R1 ^ R1;
R2 = R2 ^ R2;
R4 = R4 ^ R4;
R5 = R5 ^ R5;
R6 = R6 ^ R6;
R7 = R7 ^ R7;
( R7:0, P5:0 ) = [ SP ++ ];
DBGA ( R0.L , 1 );
DBGA ( R1.L , 2 );
DBGA ( R2.L , 3 );
DBGA ( R3.L , 0xfff9 );
DBGA ( R4.L , 4 );
DBGA ( R5.L , 5 );
DBGA ( R6.L , 6 );
DBGA ( R7.L , 7 );
R0 = SP;
loadsym R1, a;
CC = R0 == R1;
IF !CC JUMP abrt;
R0 = FP;
CC = R0 == R1;
CC = R0 == R1;
IF !CC JUMP abrt;
pass
abrt:
fail;
try:
LINK 0;
[ -- SP ] = ( R7:0, P5:0 );
R7 = 0x1234 (X);
[ -- SP ] = R7;
CALL bar;
R7 = [ SP ++ ];
( R7:0, P5:0 ) = [ SP ++ ];
UNLINK;
RTS;
bar:
LINK 0;
[ -- SP ] = ( R7:0, P5:0 );
R0 = [ FP + 8 ];
DBGA ( R0.L , 0x1234 );
CALL foo;
( R7:0, P5:0 ) = [ SP ++ ];
UNLINK;
RTS;
foo:
DBGA ( R0.L , 0x1234 );
RTS;
.data
_gptab:
.dw 0x200
.dw 0x000
.dw 0x300
.dw 0x400
.dw 0x500
.dw 0x600
.space (0x100)
a:
.dw 1
.dw 2
.dw 3
.dw 4
.dw 5
.dw 6
.dw 7
.dw 8
.dw 9
.dw 0xa
|
stsp/binutils-ia16
| 2,796
|
sim/testsuite/bfin/push-pop-multiple.s
|
# Blackfin testcase for push/pop multiples instructions
# mach: bfin
.include "testutils.inc"
# Tests follow the pattern:
# - do the push multiple
# - write a garbage value to all registers pushed
# - do the pop multiple
# - check all registers popped against known values
start
# Repeat the same operation multiple times, so this:
# do_x moo, R, 1
# becomes this:
# moo R1, 0x11111111
# moo R0, 0x00000000
.macro _do_x func:req, reg:req, max:req, x:req
.ifle (\max - \x)
\func \reg\()\x, 0x\x\x\x\x\x\x\x\x
.endif
.endm
.macro do_x func:req, reg:req, max:req
.ifc \reg, R
_do_x \func, \reg, \max, 7
_do_x \func, \reg, \max, 6
.endif
_do_x \func, \reg, \max, 5
_do_x \func, \reg, \max, 4
_do_x \func, \reg, \max, 3
_do_x \func, \reg, \max, 2
_do_x \func, \reg, \max, 1
_do_x \func, \reg, \max, 0
.endm
# Keep the garbage value in I0
.macro loadi reg:req, val:req
\reg = I0;
.endm
imm32 I0, 0xAABCDEFF
#
# Test push/pop multiples with (R7:x) syntax
#
_push_r_tests:
# initialize all Rx regs with a known value
do_x imm32, R, 0
.macro checkr tochk:req, val:req
P0 = \tochk;
imm32 P1, \val
CC = P0 == P1;
IF !CC JUMP 8f;
.endm
.macro pushr maxr:req
_push_r\maxr:
[--SP] = (R7:\maxr);
do_x loadi, R, \maxr
(R7:\maxr) = [SP++];
do_x checkr, R, \maxr
# need to do a long jump to avoid PCREL issues
jump 9f;
8: jump.l 1f;
9:
.endm
pushr 7
pushr 6
pushr 5
pushr 4
pushr 3
pushr 2
pushr 1
pushr 0
#
# Test push/pop multiples with (P5:x) syntax
#
_push_p_tests:
# initialize all Px regs with a known value
do_x imm32, P, 0
.macro checkp tochk:req, val:req
R0 = \tochk;
imm32 R1, \val
CC = R0 == R1;
IF !CC JUMP 8f;
.endm
.macro pushp maxp:req
_push_p\maxp:
[--SP] = (P5:\maxp);
do_x loadi, P, \maxp
(P5:\maxp) = [SP++];
do_x checkp, P, \maxp
# need to do a long jump to avoid PCREL issues
jump 9f;
8: jump.l 1f;
9:
.endm
# checkp func clobbers R0/R1
L0 = R0;
L1 = R1;
pushp 5
pushp 4
pushp 3
pushp 2
pushp 1
pushp 0
R0 = L0;
R1 = L1;
#
# Test push/pop multiples with (R7:x, P5:x) syntax
#
_push_rp_tests:
.macro _pushrp maxr:req, maxp:req
_push_r\maxr\()_p\maxp:
[--SP] = (R7:\maxr, P5:\maxp);
do_x loadi, R, \maxr
do_x loadi, P, \maxp
(R7:\maxr, P5:\maxp) = [SP++];
# checkr func clobbers P0/P1
L0 = P0;
L1 = P1;
do_x checkr, R, \maxr
P1 = L1;
P0 = L0;
# checkp func clobbers R0/R1
L0 = R0;
L1 = R1;
do_x checkp, P, \maxp
R0 = L0;
R1 = L1;
# need to do a long jump to avoid PCREL issues
jump 9f;
8: jump.l 1f;
9:
.endm
.macro pushrp maxr:req
_pushrp \maxr, 5
_pushrp \maxr, 4
_pushrp \maxr, 3
_pushrp \maxr, 2
_pushrp \maxr, 1
_pushrp \maxr, 0
.endm
pushrp 7
pushrp 6
pushrp 5
pushrp 4
pushrp 3
pushrp 2
pushrp 1
pushrp 0
pass
1:
fail
|
stsp/binutils-ia16
| 5,833
|
sim/testsuite/bfin/random_0029.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2030ca00 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0xdf7ce5c7;
dmm32 A1.x, 0xffffff9c;
imm32 R0, 0x098ecb70;
imm32 R1, 0x80000000;
R1.H = (A1 += R0.L * R1.H) (M, ISS2);
checkreg R1, 0x80000000;
checkreg A1.w, 0xc534e5c7;
checkreg A1.x, 0xffffff9c;
checkreg ASTAT, (0x2030ca00 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x00100600 | _VS | _AQ | _AZ);
dmm32 A1.w, 0xdf39474d;
dmm32 A1.x, 0xffffffd9;
imm32 R2, 0x64864b87;
imm32 R3, 0x61a97f85;
imm32 R6, 0x1bcacb1a;
R2.H = (A1 -= R6.L * R3.L) (M, ISS2);
checkreg R2, 0x80004b87;
checkreg A1.w, 0xf992dccb;
checkreg A1.x, 0xffffffd9;
checkreg ASTAT, (0x00100600 | _VS | _V | _AQ | _V_COPY | _AZ);
dmm32 ASTAT, (0x50f0c290 | _VS | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A1.w, 0xb0a49eb4;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x1a1607f3;
imm32 R1, 0x6dcc7fff;
imm32 R6, 0x80008000;
R6.H = (A1 -= R1.L * R0.H) (M, ISS2);
checkreg R6, 0x7fff8000;
checkreg A1.w, 0xa399b8ca;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x50f0c290 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x48b04c10 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x91b35cde;
dmm32 A1.x, 0x0000006c;
imm32 R1, 0xf473c458;
imm32 R5, 0x1358b0c2;
imm32 R7, 0xfbf00410;
R5.H = (A1 -= R1.L * R7.H) (M, ISS2);
checkreg R5, 0x7fffb0c2;
checkreg A1.w, 0xcc69025e;
checkreg A1.x, 0x0000006c;
checkreg ASTAT, (0x48b04c10 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x1ca04210 | _VS | _AC0 | _AQ | _AN | _AZ);
dmm32 A1.w, 0xf516677c;
dmm32 A1.x, 0x00000015;
imm32 R5, 0x218d4960;
imm32 R6, 0xfa8c8000;
R5 = (A1 -= R6.L * R5.H) (M, ISS2);
checkreg R5, 0x7fffffff;
checkreg A1.w, 0x05dce77c;
checkreg A1.x, 0x00000016;
checkreg ASTAT, (0x1ca04210 | _VS | _V | _AC0 | _AQ | _V_COPY | _AN | _AZ);
dmm32 ASTAT, (0x04004490 | _VS | _AC1 | _AN);
dmm32 A1.w, 0xd1795d0a;
dmm32 A1.x, 0x00000000;
imm32 R2, 0x67bd270e;
imm32 R3, 0xda302534;
imm32 R7, 0x7fffa2af;
R2.H = (A1 += R7.L * R3.L) (M, ISS2);
checkreg R2, 0x7fff270e;
checkreg A1.w, 0xc3e9b396;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x04004490 | _VS | _V | _AC1 | _V_COPY | _AN);
dmm32 ASTAT, (0x60600490 | _VS | _AV1S | _AC1 | _CC | _AC0_COPY | _AZ);
dmm32 A1.w, 0xeb8abaea;
dmm32 A1.x, 0x00000036;
imm32 R1, 0x111687e8;
imm32 R5, 0x111687e8;
R1 = (A1 += R1.L * R5.L) (M, ISS2);
checkreg R1, 0x7fffffff;
checkreg A1.w, 0xabc93d2a;
checkreg A1.x, 0x00000036;
checkreg ASTAT, (0x60600490 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x30200e80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY | _AN);
dmm32 A1.w, 0xd3275e78;
dmm32 A1.x, 0xffffff89;
imm32 R3, 0xfee80d8d;
imm32 R6, 0x1c1a8000;
imm32 R7, 0x00000000;
R3 = (A1 += R7.L * R6.L) (M, ISS2);
checkreg R3, 0x80000000;
checkreg A1.w, 0xd3275e78;
checkreg A1.x, 0xffffff89;
checkreg ASTAT, (0x30200e80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x50208610 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY);
dmm32 A1.w, 0xb3b71810;
dmm32 A1.x, 0x00000000;
imm32 R4, 0xfc2f7ffe;
imm32 R5, 0x7fffffff;
imm32 R7, 0x3488c040;
R7.H = (A1 -= R4.L * R5.H) (M, ISS2);
checkreg R7, 0x7fffc040;
checkreg A1.w, 0x73b8980e;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x48d04410 | _VS | _AV1S | _AV0S | _AC0 | _AQ);
dmm32 A1.w, 0xeb066305;
dmm32 A1.x, 0xffffff9c;
imm32 R0, 0x80002105;
imm32 R4, 0xf4fbe11e;
imm32 R7, 0xffffb83a;
R7 = (A1 += R0.L * R4.L) (M, ISS2);
checkreg R7, 0x80000000;
checkreg A1.w, 0x080fa69b;
checkreg A1.x, 0xffffff9d;
checkreg ASTAT, (0x48d04410 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY);
dmm32 ASTAT, (0x3850c090 | _VS | _AV1S | _AV0S | _AC1 | _CC);
dmm32 A1.w, 0xdfed6537;
dmm32 A1.x, 0xffffffae;
imm32 R0, 0xe962c700;
imm32 R4, 0x32c97fff;
imm32 R7, 0x28da7373;
R4.H = (A1 += R7.L * R0.H) (M, ISS2);
checkreg R4, 0x80007fff;
checkreg A1.w, 0x492d423d;
checkreg A1.x, 0xffffffaf;
checkreg ASTAT, (0x3850c090 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY);
dmm32 ASTAT, (0x78a0ce00 | _VS | _AV1S | _AC0 | _AQ | _CC);
dmm32 A1.w, 0x8c733a78;
dmm32 A1.x, 0x0000002d;
imm32 R1, 0x3840acb0;
imm32 R3, 0x47b843ad;
imm32 R7, 0x7fff4d00;
R7 = (A1 += R1.L * R3.H) (M, ISS2);
checkreg R7, 0x7fffffff;
checkreg A1.w, 0x751c28f8;
checkreg A1.x, 0x0000002d;
checkreg ASTAT, (0x78a0ce00 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x3cf08880 | _VS | _AV1S | _AV0S | _AC0);
dmm32 A1.w, 0xbde0b55f;
dmm32 A1.x, 0xfffffffd;
imm32 R0, 0x80002300;
imm32 R5, 0x635db45a;
imm32 R7, 0x67e67af3;
R7 = (A1 += R0.L * R5.L) (M, ISS2);
checkreg R7, 0x80000000;
checkreg A1.w, 0xd689035f;
checkreg A1.x, 0xfffffffd;
checkreg ASTAT, (0x3cf08880 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY);
dmm32 ASTAT, (0x58608410 | _VS | _AQ | _CC | _AZ);
dmm32 A1.w, 0xe4660b32;
dmm32 A1.x, 0xffffff84;
imm32 R1, 0x2c6c9118;
imm32 R2, 0x007793ad;
imm32 R7, 0x526c17d9;
R1.H = (A1 -= R2.L * R7.L) (M, ISS2);
checkreg R1, 0x80009118;
checkreg A1.w, 0xee7d528d;
checkreg A1.x, 0xffffff84;
checkreg ASTAT, (0x58608410 | _VS | _V | _AQ | _CC | _V_COPY | _AZ);
dmm32 ASTAT, (0x2020c210 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN);
dmm32 A1.w, 0x8da6c28f;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x0000fff7;
imm32 R4, 0xf85a0000;
imm32 R7, 0x7fff0000;
R7 = (A1 += R4.L * R1.L) (M, ISS2);
checkreg R7, 0x7fffffff;
checkreg A1.w, 0x8da6c28f;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x2020c210 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
pass
|
stsp/binutils-ia16
| 6,542
|
sim/testsuite/bfin/c_except_user_mode.S
|
//Original:/proj/frio/dv/testcases/core/c_except_user_mode/c_except_user_mode.dsp
// Spec Reference: except_mode_user
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
//
////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI; // execute this instr put us in USER mode
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// USER MODE & go to different RAISE in USER mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
// Raise 1 requires some intelligence so the test
// doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
RAISE 2; // RTN // exception because we execute this in USER mode
RAISE 5; // RTI
RAISE 6; // RTI
RAISE 7; // RTI
RAISE 8; // RTI
RAISE 9; // RTI
RAISE 10; // RTI
RAISE 11; // RTI
RAISE 12; // RTI
RAISE 13; // RTI
RAISE 14; // RTI
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG(r0, 0x00000018);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
CHECKREG(r4, 0x00000000);
CHECKREG(r5, 0x00000000);
CHECKREG(r6, 0x00000000);
CHECKREG(r7, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = RETN;
R0 += 2;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
RETN = r0;
RTN;
XHANDLE: // Exception Handler 3
R1 = RETX;
I0 += 2;
R1 += 2; // for return address
RETX = r1;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = RETI;
R2 += 2;
I0 += 2;
I1 += 2;
RETI = r2;
RTI;
THANDLE: // Timer Handler 6
R3 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
R3 += 2;
RETI = r3;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = RETI;
I0 += 2;
I1 += 2;
I3 += 2;
R4 += 2;
RETI = r4;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R5 += 2;
RETI = r5;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R6 += 2;
RETI = r6;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R7 += 2;
RETI = r7;
RTI;
I11HANDLE: // IVG 11 Handler
R0 = RETI;
R0 += 2;
M0 = I0;
M1 = I1;
M2 = I2;
M3 = I3;
RETI = r0;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R1 += 2;
RETI = r1;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R2 += 2;
RETI = r2;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R3 += 2;
RETI = r3;
RTI;
I15HANDLE: // IVG 15 Handler
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
RTI;
// nop;nop;nop;nop;nop;nop;nop; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
// .space (STACKSIZE); // adding this may solve the problem
|
stsp/binutils-ia16
| 4,358
|
sim/testsuite/bfin/c_dsp32mult_pair.s
|
//Original:/testcases/core/c_dsp32mult_pair/c_dsp32mult_pair.dsp
// Spec Reference: dsp32mult pair
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467029;
R1 = R0.L * R0.L, R0 = R0.L * R0.L;
R3 = R0.L * R1.L, R2 = R0.L * R1.H;
R5 = R1.L * R0.L, R4 = R1.H * R0.L;
R7 = R1.L * R1.L, R6 = R1.H * R1.H;
CHECKREG r0, 0x39F9C2B2;
CHECKREG r1, 0x39F9C2B2;
CHECKREG r2, 0xE43C0244;
CHECKREG r3, 0x1D5C8788;
CHECKREG r4, 0xE43C0244;
CHECKREG r5, 0x1D5C8788;
CHECKREG r6, 0x1A41A862;
CHECKREG r7, 0x1D5C8788;
imm32 r0, 0x5b33a635;
imm32 r1, 0x6fbe5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x9006d037;
imm32 r4, 0x80abcb39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c00dd;
imm32 r7, 0x12469003;
R1 = R2.L * R2.L, R0 = R2.L * R2.L;
R3 = R2.L * R3.L, R2 = R2.L * R3.H;
R5 = R3.L * R2.L, R4 = R3.H * R2.L;
R7 = R3.L * R3.L, R6 = R3.H * R3.H;
CHECKREG r0, 0x2965A1F2;
CHECKREG r1, 0x2965A1F2;
CHECKREG r2, 0x3FAE367C;
CHECKREG r3, 0x1B2CD8C6;
CHECKREG r4, 0x0B90E2A0;
CHECKREG r5, 0xEF4D87D0;
CHECKREG r6, 0x05C49F20;
CHECKREG r7, 0x0C057248;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x00060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00c005d;
imm32 r7, 0x1246705f;
R1 = R4.L * R4.L, R0 = R4.L * R4.L;
R3 = R4.L * R5.L, R2 = R4.L * R5.H;
R5 = R5.L * R4.L, R4 = R5.H * R4.L;
R7 = R5.L * R5.L, R6 = R5.H * R5.H;
CHECKREG r0, 0x1B29B4A2;
CHECKREG r1, 0x1B29B4A2;
CHECKREG r2, 0xF851E418;
CHECKREG r3, 0x07AAE266;
CHECKREG r4, 0xF851E418;
CHECKREG r5, 0x07AAE266;
CHECKREG r6, 0x007579C8;
CHECKREG r7, 0x06D88148;
imm32 r0, 0xab235666;
imm32 r1, 0xeaba5166;
imm32 r2, 0x13d48766;
imm32 r3, 0xf00b0066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10ac5f6b;
imm32 r6, 0x800cb66d;
imm32 r7, 0x1246707f;
R1 = R6.L * R6.L, R0 = R6.L * R6.L;
R3 = R6.L * R7.L, R2 = R6.L * R7.H;
R5 = R7.L * R6.L, R4 = R7.H * R6.L;
R7 = R7.L * R7.L, R6 = R7.H * R7.H;
CHECKREG r0, 0x2A4A54D2;
CHECKREG r1, 0x2A4A54D2;
CHECKREG r2, 0xF57F179C;
CHECKREG r3, 0xBF566026;
CHECKREG r4, 0xF57F179C;
CHECKREG r5, 0xBF566026;
CHECKREG r6, 0x029BD648;
CHECKREG r7, 0x62DEBE02;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R1 = R3.L * R2.L (M), R0 = R3.L * R2.H;
R3 = R1.L * R0.H, R2 = R1.H * R0.L;
R5 = R7.H * R4.L, R4 = R7.H * R4.L;
R7 = R5.L * R6.L (M), R6 = R5.H * R6.L;
CHECKREG r0, 0x00010BF8;
CHECKREG r1, 0x0002D123;
CHECKREG r2, 0x00002FE0;
CHECKREG r3, 0xFFFFA246;
CHECKREG r4, 0xF8B964EC;
CHECKREG r5, 0xF8B964EC;
CHECKREG r6, 0xFFFF42CA;
CHECKREG r7, 0x00051FFC;
imm32 r0, 0x9b235a75;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946905;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d9d;
imm32 r7, 0x12467009;
R3 = R6.L * R5.L, R2 = R6.L * R5.H;
R1 = R3.L * R0.H (M), R0 = R3.H * R0.L;
R5 = R1.L * R4.L (M), R4 = R1.H * R4.L;
R7 = R2.H * R7.L, R6 = R2.H * R7.L;
CHECKREG r0, 0xFE55DCD2;
CHECKREG r1, 0x0C7E7B9A;
CHECKREG r2, 0x01C5EAF8;
CHECKREG r3, 0xFDA5149E;
CHECKREG r4, 0xF6576CDC;
CHECKREG r5, 0x4BD1CA6A;
CHECKREG r6, 0x018C7FDA;
CHECKREG r7, 0x018C7FDA;
imm32 r0, 0x8b235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13846705;
imm32 r3, 0x00080007;
imm32 r4, 0x90ab8d09;
imm32 r5, 0x10ace8db;
imm32 r6, 0x000c008d;
imm32 r7, 0x12467008;
R3 = R6.H * R5.L, R2 = R6.L * R5.H;
R7 = R2.L * R0.H (M), R6 = R2.H * R0.L;
R5 = R1.L * R3.L (M), R4 = R1.H * R3.L;
R1 = R2.H * R7.L, R0 = R2.L * R7.H;
CHECKREG r0, 0x2517D740;
CHECKREG r1, 0xFFFDAAA0;
CHECKREG r2, 0x00125D78;
CHECKREG r3, 0xFFFDD488;
CHECKREG r4, 0x12C555A0;
CHECKREG r5, 0x435F68B8;
CHECKREG r6, 0x000C2874;
CHECKREG r7, 0x32CCEF68;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R1.H * R4.L, R0 = R1.H * R4.L;
R3 = R2.L * R5.L, R2 = R2.L * R5.H;
R5 = R3.H * R6.L, R4 = R3.L * R6.L;
R7 = R4.L * R0.H, R6 = R4.H * R0.L;
CHECKREG r0, 0x074CED14;
CHECKREG r1, 0x074CED14;
CHECKREG r2, 0x0D6B0EB8;
CHECKREG r3, 0xF2338E8E;
CHECKREG r4, 0xFF2DF2EC;
CHECKREG r5, 0xFFE6726E;
CHECKREG r6, 0x001F3108;
CHECKREG r7, 0xFF412420;
pass
|
stsp/binutils-ia16
| 7,512
|
sim/testsuite/bfin/c_seq_ex2_mmr_mvpop.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmr_mvpop/c_seq_ex2_mmr_mvpop.dsp
// Spec Reference: sequencer stage ex2 (mmr + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
// [--sp] = (r7-r0);
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
LD32(r0, 0x55552345);
// RAISE 2; // RTN
[ P1 ] = R0;
// jump LABEL1;
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
// RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
CSYNC;
// wrt-rd EVT5 = 0xFFE02034
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
// RAISE 6; // RTI
R0 = [ P1 ];
// jump LABEL2;
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
//CHECKREG(r0, 0x55552345);
// RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x55552345);
CHECKREG(r1, 0x00000012);
CHECKREG(r2, 0x00000023);
CHECKREG(r3, 0x00000024);
CHECKREG(r4, 0x00000024);
CHECKREG(r5, 0x00000026);
CHECKREG(r6, 0x00000027);
CHECKREG(r7, 0x00000028);
// wrt-rd EVT13 = 0xFFE02034
LD32(p1, 0xFFE02034);
// RAISE 8; // RTI
R0 = [ P1 ];
// jump LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
CSYNC;
CHECKREG(r0, 0x55552345); // CHECKREG can not be skipped
CHECKREG(r1, 0x00000012); // so they cannot appear here
CHECKREG(r2, 0x00000013);
CHECKREG(r3, 0x00000013);
CHECKREG(r4, 0x00000015);
CHECKREG(r5, 0x00000016);
CHECKREG(r6, 0x00000017);
CHECKREG(r7, 0x00000018);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
//CHECKREG(r0, 0x55552345);
// RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x55552345);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 1,672
|
sim/testsuite/bfin/random_0007.S
|
# Make sure the acc regs are updated even when the search criteria is not met
# (this implicitly affects the top 8 bits)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x08e00690 | _VS | _AC1 | _AN);
dmm32 A0.w, 0x42357aea;
dmm32 A0.x, 0x00000001;
dmm32 A1.w, 0x3a3f0000;
dmm32 A1.x, 0x00000000;
imm32 P0, 0x7119f94d;
imm32 R4, 0xcdeea690;
imm32 R5, 0xffb58000;
imm32 R6, 0x72252b1e;
(R4, R5) = SEARCH R6 (GE);
checkreg R4, 0x7119f94d;
checkreg A0.w, 0x00007aea;
checkreg A0.x, 0x00000000;
checkreg A1.w, 0x00007225;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x08e00690 | _VS | _AC1 | _AN);
dmm32 ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0x4193c6bc;
dmm32 A0.x, 0xffffffd4;
dmm32 A1.w, 0xa97e7452;
dmm32 A1.x, 0xffffffff;
imm32 P0, 0x51e152a5;
imm32 R1, 0x36deeb9a;
imm32 R5, 0x386ab3f7;
imm32 R7, 0x2a3d5114;
(R5, R1) = SEARCH R7 (GT);
checkreg R1, 0x51e152a5;
checkreg A0.w, 0x00005114;
checkreg A0.x, 0x00000000;
checkreg A1.w, 0x00007452;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0x4193c6bc;
dmm32 A0.x, 0xffffffd4;
dmm32 A1.w, 0x0000ffff;
dmm32 A1.x, 0x00000000;
imm32 P0, 0x51e152a5;
imm32 R1, 0x36deeb9a;
imm32 R5, 0x386ab3f7;
imm32 R7, 0xFa3d5114;
(R5, R1) = SEARCH R7 (GT);
checkreg R1, 0x51e152a5;
checkreg A0.w, 0x00005114;
checkreg A0.x, 0x00000000;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
pass
|
stsp/binutils-ia16
| 10,540
|
sim/testsuite/bfin/se_oneins_zoff.S
|
//Original:/proj/frio/dv/testcases/seq/se_oneins_zoff/se_oneins_zoff.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE 0x00000500
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef IMASK
#define IMASK 0xFFE02104
#endif
#ifndef DMEM_CONTROL
#define DMEM_CONTROL 0xFFE00004
#endif
#ifndef DCPLB_ADDR0
#define DCPLB_ADDR0 0xFFE00100
#endif
#ifndef DCPLB_DATA0
#define DCPLB_DATA0 0xFFE00200
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
P0 = 0x5 (Z);
P1 = 0xa (Z);
P2 = 0x0100 (Z);
P2.H = 0x00f0;
/////////////////////////////////////////////////////////////////////////////
// Loop 0 (One instruction Zero-offset)
/////////////////////////////////////////////////////////////////////////////
R0 = [ P2 ++ ];
LSETUP ( L0T , L0T ) LC0 = P0;
L0T:R0 += 5;
R1 = [ P2 ++ ];
NOP;
LSETUP ( L1T , L1T ) LC0 = P0;
L1T:R1 += 5;
R2 = [ P2 ++ ];
NOP;
NOP;
LSETUP ( L2T , L2T ) LC0 = P0;
L2T:R2 += 5;
R3 = [ P2 ++ ];
NOP;
NOP;
NOP;
LSETUP ( L3T , L3T ) LC0 = P0;
L3T:R3 += 5;
R4 = [ P2 ++ ];
NOP;
NOP;
NOP;
NOP;
LSETUP ( L4T , L4T ) LC0 = P0;
L4T:R4 += 5;
/////////////////////////////////////////////////////////////////////////////
// Loop 1 (One instruction Zero-offset)
/////////////////////////////////////////////////////////////////////////////
R0 = [ P2 ++ ];
LSETUP ( M0T , M0T ) LC1 = P0;
M0T:R0 += 5;
R1 = [ P2 ++ ];
NOP;
LSETUP ( M1T , M1T ) LC1 = P0;
M1T:R1 += 5;
R2 = [ P2 ++ ];
NOP;
NOP;
LSETUP ( M2T , M2T ) LC1 = P0;
M2T:R2 += 5;
R3 = [ P2 ++ ];
NOP;
NOP;
NOP;
LSETUP ( M3T , M3T ) LC1 = P0;
M3T:R3 += 5;
R4 = [ P2 ++ ];
NOP;
NOP;
NOP;
NOP;
LSETUP ( M4T , M4T ) LC1 = P0;
M4T:R4 += 5;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_0x00F00100,"aw"
.dd 0x01010101;
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
.dd 0x05050505;
.dd 0x06060606;
.dd 0x07070707;
.dd 0x08080808;
.dd 0x09090909;
.dd 0x0a0a0a0a;
.dd 0x0b0b0b0b;
.dd 0x0c0c0c0c;
.dd 0x0d0d0d0d;
.dd 0x0e0e0e0e;
.dd 0x0f0f0f0f;
// Define Kernal Stack
.section MEM_0x00F00210,"aw"
.space (STACKSIZE);
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 2,862
|
sim/testsuite/bfin/byteop1p.s
|
# Blackfin testcase for BYTEOP1P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop1p i0:req, i1:req, res:req, resT:req, resR:req, resTR:req
dmm32 I0, \i0
dmm32 I1, \i1
R6 = BYTEOP1P (R1:0, R3:2);
check_it \res
R6 = BYTEOP1P (R1:0, R3:2) (T);
check_it \resT
R6 = BYTEOP1P (R1:0, R3:2) (R);
check_it \resR
R6 = BYTEOP1P (R1:0, R3:2) (T, R);
check_it \resTR
jump 2f;
1: fail
2:
.endm
imm32 R0, 0x01020304
imm32 R1, 0x10203040
imm32 R2, 0x0a0b0c0d
imm32 R3, 0xa0b0c0d0
test_byteop1p 0, 0, 0x06070809, 0x05060708, 0x58687888, 0x58687888
test_byteop1p 0, 1, 0x69060708, 0x68060708, 0x0f607080, 0x0e607080
test_byteop1p 0, 2, 0x61690708, 0x60690607, 0x0e176878, 0x0e166878
test_byteop1p 0, 3, 0x59616a07, 0x58616907, 0x0e161f70, 0x0d161e70
test_byteop1p 1, 0, 0x25060708, 0x25060708, 0x52607080, 0x52607080
test_byteop1p 1, 1, 0x88060708, 0x88050607, 0x09586878, 0x08586878
test_byteop1p 1, 2, 0x80690607, 0x80680607, 0x080f6070, 0x080e6070
test_byteop1p 1, 3, 0x78616907, 0x78606906, 0x080e1768, 0x070e1668
test_byteop1p 2, 0, 0x1d260708, 0x1d250607, 0x525a6878, 0x515a6878
test_byteop1p 2, 1, 0x80250607, 0x80250607, 0x08526070, 0x08526070
test_byteop1p 2, 2, 0x78880607, 0x78880506, 0x08095868, 0x07085868
test_byteop1p 2, 3, 0x70806906, 0x70806806, 0x07080f60, 0x07080e60
test_byteop1p 3, 0, 0x151e2607, 0x151d2607, 0x515a6270, 0x51596270
test_byteop1p 3, 1, 0x781d2607, 0x781d2506, 0x08525a68, 0x07515a68
test_byteop1p 3, 2, 0x70802506, 0x70802506, 0x07085260, 0x07085260
test_byteop1p 3, 3, 0x68788806, 0x68788805, 0x07080958, 0x06070858
imm32 R0, ~0x01020304
imm32 R1, ~0x10203040
imm32 R2, ~0x0a0b0c0d
imm32 R3, ~0xa0b0c0d0
test_byteop1p 0, 0, 0xfaf9f8f7, 0xf9f8f7f6, 0xa7978777, 0xa7978777
test_byteop1p 0, 1, 0x97f9f8f7, 0x96f9f8f7, 0xf19f8f7f, 0xf09f8f7f
test_byteop1p 0, 2, 0x9f96f9f8, 0x9e96f8f7, 0xf1e99787, 0xf1e89787
test_byteop1p 0, 3, 0xa79e96f8, 0xa69e95f8, 0xf2e9e18f, 0xf1e9e08f
test_byteop1p 1, 0, 0xdaf9f8f7, 0xdaf9f8f7, 0xad9f8f7f, 0xad9f8f7f
test_byteop1p 1, 1, 0x77faf9f8, 0x77f9f8f7, 0xf7a79787, 0xf6a79787
test_byteop1p 1, 2, 0x7f97f9f8, 0x7f96f9f8, 0xf7f19f8f, 0xf7f09f8f
test_byteop1p 1, 3, 0x879f96f9, 0x879e96f8, 0xf8f1e997, 0xf7f1e897
test_byteop1p 2, 0, 0xe2daf9f8, 0xe2d9f8f7, 0xaea59787, 0xada59787
test_byteop1p 2, 1, 0x7fdaf9f8, 0x7fdaf9f8, 0xf7ad9f8f, 0xf7ad9f8f
test_byteop1p 2, 2, 0x8777faf9, 0x8777f9f8, 0xf8f7a797, 0xf7f6a797
test_byteop1p 2, 3, 0x8f7f97f9, 0x8f7f96f9, 0xf8f7f19f, 0xf8f7f09f
test_byteop1p 3, 0, 0xeae2d9f8, 0xeae1d9f8, 0xaea69d8f, 0xaea59d8f
test_byteop1p 3, 1, 0x87e2daf9, 0x87e2d9f8, 0xf8aea597, 0xf7ada597
test_byteop1p 3, 2, 0x8f7fdaf9, 0x8f7fdaf9, 0xf8f7ad9f, 0xf8f7ad9f
test_byteop1p 3, 3, 0x978777fa, 0x978777f9, 0xf9f8f7a7, 0xf8f7f6a7
pass
|
stsp/binutils-ia16
| 3,313
|
sim/testsuite/bfin/a2.s
|
# mach: bfin
.include "testutils.inc"
start
loadsym P0, middle;
R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 );
R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 );
R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 );
R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 );
R0 = [ P0 + 16 ]; DBGA ( R0.L , 54 );
R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 );
R0 = [ P0 + 24 ]; DBGA ( R0.L , 56 );
R0 = [ P0 + 28 ]; DBGA ( R0.L , 57 );
R0 = [ P0 + -4 ]; DBGA ( R0.L , 49 );
R0 = [ P0 + -8 ]; DBGA ( R0.L , 48 );
R0 = [ P0 + -12 ]; DBGA ( R0.L , 47 );
R0 = [ P0 + -16 ]; DBGA ( R0.L , 46 );
R0 = [ P0 + -20 ]; DBGA ( R0.L , 45 );
R0 = [ P0 + -24 ]; DBGA ( R0.L , 44 );
R0 = [ P0 + -28 ]; DBGA ( R0.L , 43 );
R0 = [ P0 + -32 ]; DBGA ( R0.L , 42 );
FP = P0;
R0 = [ FP + 0 ]; DBGA ( R0.L , 50 );
R0 = [ FP + 4 ]; DBGA ( R0.L , 51 );
R0 = [ FP + 8 ]; DBGA ( R0.L , 52 );
R0 = [ FP + 12 ]; DBGA ( R0.L , 53 );
R0 = [ FP + 16 ]; DBGA ( R0.L , 54 );
R0 = [ FP + 20 ]; DBGA ( R0.L , 55 );
R0 = [ FP + 24 ]; DBGA ( R0.L , 56 );
R0 = [ FP + 28 ]; DBGA ( R0.L , 57 );
R0 = [ FP + 32 ]; DBGA ( R0.L , 58 );
R0 = [ FP + 36 ]; DBGA ( R0.L , 59 );
R0 = [ FP + 40 ]; DBGA ( R0.L , 60 );
R0 = [ FP + 44 ]; DBGA ( R0.L , 61 );
R0 = [ FP + 48 ]; DBGA ( R0.L , 62 );
R0 = [ FP + 52 ]; DBGA ( R0.L , 63 );
R0 = [ FP + 56 ]; DBGA ( R0.L , 64 );
R0 = [ FP + 60 ]; DBGA ( R0.L , 65 );
R0 = [ FP + -4 ]; DBGA ( R0.L , 49 );
R0 = [ FP + -8 ]; DBGA ( R0.L , 48 );
R0 = [ FP + -12 ]; DBGA ( R0.L , 47 );
R0 = [ FP + -16 ]; DBGA ( R0.L , 46 );
R0 = [ FP + -20 ]; DBGA ( R0.L , 45 );
R0 = [ FP + -24 ]; DBGA ( R0.L , 44 );
R0 = [ FP + -28 ]; DBGA ( R0.L , 43 );
R0 = [ FP + -32 ]; DBGA ( R0.L , 42 );
R0 = [ FP + -36 ]; DBGA ( R0.L , 41 );
R0 = [ FP + -40 ]; DBGA ( R0.L , 40 );
R0 = [ FP + -44 ]; DBGA ( R0.L , 39 );
R0 = [ FP + -48 ]; DBGA ( R0.L , 38 );
R0 = [ FP + -52 ]; DBGA ( R0.L , 37 );
R0 = [ FP + -56 ]; DBGA ( R0.L , 36 );
R0 = [ FP + -60 ]; DBGA ( R0.L , 35 );
R0 = [ FP + -64 ]; DBGA ( R0.L , 34 );
R0 = [ FP + -68 ]; DBGA ( R0.L , 33 );
R0 = [ FP + -72 ]; DBGA ( R0.L , 32 );
R0 = [ FP + -76 ]; DBGA ( R0.L , 31 );
R0 = [ FP + -80 ]; DBGA ( R0.L , 30 );
R0 = [ FP + -84 ]; DBGA ( R0.L , 29 );
R0 = [ FP + -88 ]; DBGA ( R0.L , 28 );
R0 = [ FP + -92 ]; DBGA ( R0.L , 27 );
R0 = [ FP + -96 ]; DBGA ( R0.L , 26 );
R0 = [ FP + -100 ]; DBGA ( R0.L , 25 );
R0 = [ FP + -104 ]; DBGA ( R0.L , 24 );
R0 = [ FP + -108 ]; DBGA ( R0.L , 23 );
R0 = [ FP + -112 ]; DBGA ( R0.L , 22 );
R0 = [ FP + -116 ]; DBGA ( R0.L , 21 );
pass
.data
base:
.dd 0
.dd 1
.dd 2
.dd 3
.dd 4
.dd 5
.dd 6
.dd 7
.dd 8
.dd 9
.dd 10
.dd 11
.dd 12
.dd 13
.dd 14
.dd 15
.dd 16
.dd 17
.dd 18
.dd 19
.dd 20
.dd 21
.dd 22
.dd 23
.dd 24
.dd 25
.dd 26
.dd 27
.dd 28
.dd 29
.dd 30
.dd 31
.dd 32
.dd 33
.dd 34
.dd 35
.dd 36
.dd 37
.dd 38
.dd 39
.dd 40
.dd 41
.dd 42
.dd 43
.dd 44
.dd 45
.dd 46
.dd 47
.dd 48
.dd 49
middle:
.dd 50
.dd 51
.dd 52
.dd 53
.dd 54
.dd 55
.dd 56
.dd 57
.dd 58
.dd 59
.dd 60
.dd 61
.dd 62
.dd 63
.dd 64
.dd 65
.dd 66
.dd 67
.dd 68
.dd 69
.dd 70
.dd 71
.dd 72
.dd 73
.dd 74
.dd 75
.dd 76
.dd 77
.dd 78
.dd 79
.dd 80
.dd 81
.dd 82
.dd 83
.dd 84
.dd 85
.dd 86
.dd 87
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.dd 89
.dd 90
.dd 91
.dd 92
.dd 93
.dd 94
.dd 95
.dd 96
.dd 97
.dd 98
.dd 99
|
stsp/binutils-ia16
| 7,286
|
sim/testsuite/bfin/c_dsp32alu_rrppmm_sft.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft/c_dsp32alu_rrppmm_sft.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, <<
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x95679911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34945515;
imm32 r3, 0x46967717;
imm32 r4, 0x5597891b;
imm32 r5, 0x6989ab1d;
imm32 r6, 0x94445515;
imm32 r7, 0x96667777;
R0 = R0 +|+ R0, R7 = R0 -|- R0 (ASR);
R1 = R0 +|+ R1, R6 = R0 -|- R1 (ASL);
R2 = R0 +|+ R2, R5 = R0 -|- R2 (ASR);
R3 = R0 +|+ R3, R4 = R0 -|- R3 (ASR);
R4 = R0 +|+ R4, R3 = R0 -|- R4 (ASL);
R5 = R0 +|+ R5, R2 = R0 -|- R5 (ASR);
R6 = R0 +|+ R6, R1 = R0 -|- R6 (ASL);
R7 = R0 +|+ R7, R0 = R0 -|- R7 (ASR);
CHECKREG r0, 0xcAB3cC88;
CHECKREG r1, 0x73567A52;
CHECKREG r2, 0xf27FfB89;
CHECKREG r3, 0xdBFE1028;
CHECKREG r4, 0x799E541C;
CHECKREG r5, 0xa2E89D87;
CHECKREG r6, 0xE246e9F2;
CHECKREG r7, 0xcAB3cC88;
imm32 r0, 0x11678911;
imm32 r1, 0xa719ab1d;
imm32 r2, 0x3a415515;
imm32 r3, 0x46a67717;
imm32 r4, 0x556a891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445a15;
imm32 r7, 0x866677a7;
R0 = R1 +|+ R0, R7 = R1 -|- R0 (ASR);
R1 = R1 +|+ R1, R6 = R1 -|- R1 (ASR);
R2 = R1 +|+ R2, R5 = R1 -|- R2 (ASL);
R3 = R1 +|+ R3, R4 = R1 -|- R3 (ASR);
R4 = R1 +|+ R4, R3 = R1 -|- R4 (ASR);
R5 = R1 +|+ R5, R2 = R1 -|- R5 (ASR);
R6 = R1 +|+ R6, R1 = R1 -|- R6 (ASL);
R7 = R1 +|+ R7, R0 = R1 -|- R7 (ASR);
CHECKREG r0, 0x41AC229A;
CHECKREG r1, 0x4E32563A;
CHECKREG r2, 0xe6B4fF86;
CHECKREG r3, 0xfB70088D;
CHECKREG r4, 0xaBA9a290;
CHECKREG r5, 0xc064aB96;
CHECKREG r6, 0x4E32563A;
CHECKREG r7, 0x0C8533A0;
imm32 r0, 0xb567891b;
imm32 r1, 0x2b89abbd;
imm32 r2, 0x34b45b15;
imm32 r3, 0x466bb717;
imm32 r4, 0x556bb91b;
imm32 r5, 0x67b9ab1d;
imm32 r6, 0x7b4455b5;
imm32 r7, 0xb666777b;
R0 = R2 +|+ R0, R7 = R2 -|- R0 (ASR);
R1 = R2 +|+ R1, R6 = R2 -|- R1 (ASR);
R2 = R2 +|+ R2, R5 = R2 -|- R2 (ASR);
R3 = R2 +|+ R3, R4 = R2 -|- R3 (ASL);
R4 = R2 +|+ R4, R3 = R2 -|- R4 (ASR);
R5 = R2 +|+ R5, R2 = R2 -|- R5 (ASR);
R6 = R2 +|+ R6, R1 = R2 -|- R6 (ASL);
R7 = R2 +|+ R7, R0 = R2 -|- R7 (ASR);
CHECKREG r0, 0xED5Ae246;
CHECKREG r1, 0x2B8AaBBC;
CHECKREG r2, 0x1A5A2D8A;
CHECKREG r3, 0x2C11098C;
CHECKREG r4, 0x08A35188;
CHECKREG r5, 0x1A5A2D8A;
CHECKREG r6, 0x3DDE0A6C;
CHECKREG r7, 0x2D004B43;
imm32 r0, 0xbc678c11;
imm32 r1, 0x27c9cb1d;
imm32 r2, 0x344c5515;
imm32 r3, 0x46c6c717;
imm32 r4, 0x55678c1b;
imm32 r5, 0x6c89abcd;
imm32 r6, 0x7444551c;
imm32 r7, 0x8c667777;
R0 = R3 +|+ R0, R7 = R3 -|- R0 (ASL);
R1 = R3 +|+ R1, R6 = R3 -|- R1 (ASR);
R2 = R3 +|+ R2, R5 = R3 -|- R2 (ASR);
R3 = R3 +|+ R3, R4 = R3 -|- R3 (ASR);
R4 = R3 +|+ R4, R3 = R3 -|- R4 (ASL);
R5 = R3 +|+ R5, R2 = R3 -|- R5 (ASR);
R6 = R3 +|+ R6, R1 = R3 -|- R6 (ASR);
R7 = R3 +|+ R7, R0 = R3 -|- R7 (ASL);
CHECKREG r0, 0xF19C3044;
CHECKREG r1, 0xbF07C818;
CHECKREG r2, 0xC227eA96;
CHECKREG r3, 0x8D8C8E2E;
CHECKREG r4, 0x8D8C8E2E;
CHECKREG r5, 0xCB64a397;
CHECKREG r6, 0xCE85C615;
CHECKREG r7, 0x44940874;
imm32 r0, 0xd56789d1;
imm32 r1, 0x2d89abdd;
imm32 r2, 0x34d455d5;
imm32 r3, 0x4d667717;
imm32 r4, 0x5dd7891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0xd44d5515;
imm32 r7, 0xd666d777;
R0 = R4 +|+ R0, R7 = R4 -|- R0 (ASR);
R1 = R4 +|+ R1, R6 = R4 -|- R1 (ASR);
R2 = R4 +|+ R2, R5 = R4 -|- R2 (ASR);
R3 = R4 +|+ R3, R4 = R4 -|- R3 (ASL);
R4 = R4 +|+ R4, R3 = R4 -|- R4 (ASR);
R5 = R4 +|+ R5, R2 = R4 -|- R5 (ASL);
R6 = R4 +|+ R6, R1 = R4 -|- R6 (ASR);
R7 = R4 +|+ R7, R0 = R4 -|- R7 (ASR);
CHECKREG r0, 0xeE551231;
CHECKREG r1, 0x045D1AB4;
CHECKREG r2, 0x18C214CA;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x20E22408;
CHECKREG r5, 0x6AC67B56;
CHECKREG r6, 0x1C840953;
CHECKREG r7, 0x328D11D6;
imm32 r0, 0xc567a911;
imm32 r1, 0x278aab1d;
imm32 r2, 0x3c445515;
imm32 r3, 0x46a67717;
imm32 r4, 0x55c7891b;
imm32 r5, 0x6a8cab1d;
imm32 r6, 0x7444c515;
imm32 r7, 0xa6667c77;
R0 = R5 +|+ R0, R7 = R5 -|- R0 (ASR);
R1 = R5 +|+ R1, R6 = R5 -|- R1 (ASL);
R2 = R5 +|+ R2, R5 = R5 -|- R2 (ASR);
R3 = R5 +|+ R3, R4 = R5 -|- R3 (ASR);
R4 = R5 +|+ R4, R3 = R5 -|- R4 (ASR);
R5 = R5 +|+ R5, R2 = R5 -|- R5 (ASL);
R6 = R5 +|+ R6, R1 = R5 -|- R6 (ASR);
R7 = R5 +|+ R7, R0 = R5 -|- R7 (ASR);
CHECKREG r0, 0x04FFD585;
CHECKREG r1, 0x6B46D608;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x17720887;
CHECKREG r4, 0xFFB1a27D;
CHECKREG r5, 0x5C90AC10;
CHECKREG r6, 0xF14AD608;
CHECKREG r7, 0x5791D68B;
imm32 r0, 0xd5678911;
imm32 r1, 0x2ddddd1d;
imm32 r2, 0x34ddd515;
imm32 r3, 0x46d67717;
imm32 r4, 0x5d6d891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x74445d15;
imm32 r7, 0xd66677d7;
R0 = R6 +|+ R0, R7 = R6 -|- R0 (ASR);
R1 = R6 +|+ R1, R6 = R6 -|- R1 (ASR);
R2 = R6 +|+ R2, R5 = R6 -|- R2 (ASR);
R3 = R6 +|+ R3, R4 = R6 -|- R3 (ASL);
R4 = R6 +|+ R4, R3 = R6 -|- R4 (ASR);
R5 = R6 +|+ R5, R2 = R6 -|- R5 (ASR);
R6 = R6 +|+ R6, R1 = R6 -|- R6 (ASL);
R7 = R6 +|+ R7, R0 = R6 -|- R7 (ASR);
CHECKREG r0, 0x9EAFcAF7;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x16040544;
CHECKREG r3, 0x353C5719;
CHECKREG r4, 0xEDF6E8E3;
CHECKREG r5, 0x0D2F3AB7;
CHECKREG r6, 0x8CCCFFF0;
CHECKREG r7, 0xeE1D34F9;
imm32 r0, 0xf567a911;
imm32 r1, 0x2f8aab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x4a6f7717;
imm32 r4, 0x5567f91b;
imm32 r5, 0xa789af1d;
imm32 r6, 0x74445515;
imm32 r7, 0x866677f7;
R0 = R7 +|+ R0, R7 = R7 -|- R0 (ASR);
R1 = R7 +|+ R1, R6 = R7 -|- R1 (ASL);
R2 = R7 +|+ R2, R5 = R7 -|- R2 (ASR);
R3 = R7 +|+ R3, R4 = R7 -|- R3 (ASR);
R4 = R7 +|+ R4, R3 = R7 -|- R4 (ASL);
R5 = R7 +|+ R5, R2 = R7 -|- R5 (ASL);
R6 = R7 +|+ R6, R1 = R7 -|- R6 (ASR);
R7 = R7 +|+ R7, R0 = R7 -|- R7 (ASL);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xCB4Af763;
CHECKREG r2, 0xFD24bC88;
CHECKREG r3, 0x12EEdE8A;
CHECKREG r4, 0x0F0EbF42;
CHECKREG r5, 0x24D8e144;
CHECKREG r6, 0xFD34700F;
CHECKREG r7, 0x21FC9DCC;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34e45515;
imm32 r3, 0x46667717;
imm32 r4, 0x556e891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444e515;
imm32 r7, 0x86667e77;
R4 = R2 +|+ R5, R3 = R2 -|- R5 (ASR);
R0 = R5 +|+ R3, R5 = R5 -|- R3 (ASL);
R2 = R6 +|+ R2, R0 = R6 -|- R2 (ASL);
R3 = R4 +|+ R0, R2 = R4 -|- R0 (ASR);
R7 = R7 +|+ R6, R6 = R7 -|- R6 (ASL);
R6 = R1 +|+ R7, R1 = R1 -|- R7 (ASL);
R5 = R0 +|+ R4, R7 = R0 -|- R4 (ASR);
R1 = R3 +|+ R1, R4 = R3 -|- R1 (ASR);
CHECKREG r0, 0x7EC02000;
CHECKREG r1, 0x6C72EC0B;
CHECKREG r2, 0xe7BBF00C;
CHECKREG r3, 0x667B100C;
CHECKREG r4, 0xfA082401;
CHECKREG r5, 0x667B100C;
CHECKREG r6, 0x47BAE46A;
CHECKREG r7, 0x18450FF3;
imm32 r0, 0xd5678911;
imm32 r1, 0xff89ab1d;
imm32 r2, 0x34f45515;
imm32 r3, 0x46667717;
imm32 r4, 0x556f891b;
imm32 r5, 0x6789fb1d;
imm32 r6, 0x74445f15;
imm32 r7, 0x866677f7;
R4 = R3 +|+ R3, R5 = R3 -|- R3 (ASR);
R1 = R6 +|+ R1, R6 = R6 -|- R1 (ASL);
R6 = R1 +|+ R4, R4 = R1 -|- R4 (ASL);
R7 = R4 +|+ R2, R0 = R4 -|- R2 (ASR);
R2 = R2 +|+ R6, R1 = R2 -|- R6 (ASR);
R3 = R5 +|+ R5, R7 = R5 -|- R5 (ASL);
R5 = R7 +|+ R7, R3 = R7 -|- R7 (ASL);
R0 = R0 +|+ R0, R2 = R0 -|- R0 (ASR);
CHECKREG r0, 0x06BAF2C2;
CHECKREG r1, 0xEC7A1F0F;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x42683A9A;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x5C0016F6;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 6,835
|
sim/testsuite/bfin/c_seq_ac_raise_mv_ppop.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv_ppop/c_seq_ac_raise_mv_ppop.dsp
// Spec Reference: sequencer stage AC (raise + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
RAISE 2; // RTN
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:1 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
RAISE 6; // RTI
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:2 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:2 ) = [ SP ++ ];
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000023);
CHECKREG(r3, 0x00000024);
CHECKREG(r4, 0x00000024);
CHECKREG(r5, 0x00000026);
CHECKREG(r6, 0x00000027);
CHECKREG(r7, 0x00000028);
RAISE 8; // RTI
P1 = R1;
R5 = P1;
( R7:1 ) = [ SP ++ ];
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000012);
CHECKREG(r2, 0x00000013);
CHECKREG(r3, 0x00000013);
CHECKREG(r4, 0x00000015);
CHECKREG(r5, 0x00000016);
CHECKREG(r6, 0x00000017);
CHECKREG(r7, 0x00000018);
RAISE 9; // RTI
P2 = R2;
R5 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 6,034
|
sim/testsuite/bfin/c_dsp32alu_maxmax.s
|
//Original:/testcases/core/c_dsp32alu_maxmax/c_dsp32alu_maxmax.dsp
// Spec Reference: dsp32alu dregs = max / max ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x25678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0xe6657717;
imm32 r4, 0x5a67891b;
imm32 r5, 0x67b9ab1d;
imm32 r6, 0x744d5515;
imm32 r7, 0x8666c777;
R0 = MAX ( R0 , R0 ) (V);
R1 = MAX ( R0 , R1 ) (V);
R2 = MAX ( R0 , R2 ) (V);
R3 = MAX ( R0 , R3 ) (V);
R4 = MAX ( R0 , R4 ) (V);
R5 = MAX ( R0 , R5 ) (V);
R6 = MAX ( R0 , R6 ) (V);
R7 = MAX ( R0 , R7 ) (V);
CHECKREG r0, 0x25678911;
CHECKREG r1, 0x2567AB1D;
CHECKREG r2, 0x34445515;
CHECKREG r3, 0x25677717;
CHECKREG r4, 0x5A67891B;
CHECKREG r5, 0x67B9AB1D;
CHECKREG r6, 0x744D5515;
CHECKREG r7, 0x2567C777;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = MAX ( R1 , R0 ) (V);
R1 = MAX ( R1 , R1 ) (V);
R2 = MAX ( R1 , R2 ) (V);
R3 = MAX ( R1 , R3 ) (V);
R4 = MAX ( R1 , R4 ) (V);
R5 = MAX ( R1 , R5 ) (V);
R6 = MAX ( R1 , R6 ) (V);
R7 = MAX ( R1 , R7 ) (V);
CHECKREG r0, 0xA789AB2D;
CHECKREG r1, 0xA789AB2D;
CHECKREG r2, 0xB4445525;
CHECKREG r3, 0xC6667727;
CHECKREG r4, 0xD888AB2D;
CHECKREG r5, 0xEAAABB2B;
CHECKREG r6, 0xFCCCDD2D;
CHECKREG r7, 0x0EEEFFFF;
imm32 r0, 0x416789ab;
imm32 r1, 0x5289abcd;
imm32 r2, 0x63445555;
imm32 r3, 0xa7669777;
imm32 r4, 0x456789ab;
imm32 r5, 0xb689abcd;
imm32 r6, 0xd7445555;
imm32 r7, 0x68667777;
R0 = MAX ( R2 , R0 ) (V);
R1 = MAX ( R2 , R1 ) (V);
R2 = MAX ( R2 , R2 ) (V);
R3 = MAX ( R2 , R3 ) (V);
R4 = MAX ( R2 , R4 ) (V);
R5 = MAX ( R2 , R5 ) (V);
R6 = MAX ( R2 , R6 ) (V);
R7 = MAX ( R2 , R7 ) (V);
CHECKREG r0, 0x63445555;
CHECKREG r1, 0x63445555;
CHECKREG r2, 0x63445555;
CHECKREG r3, 0x63445555;
CHECKREG r4, 0x63445555;
CHECKREG r5, 0x63445555;
CHECKREG r6, 0x63445555;
CHECKREG r7, 0x68667777;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
R0 = MAX ( R3 , R0 ) (V);
R1 = MAX ( R3 , R1 ) (V);
R2 = MAX ( R3 , R2 ) (V);
R3 = MAX ( R3 , R3 ) (V);
R4 = MAX ( R3 , R4 ) (V);
R5 = MAX ( R3 , R5 ) (V);
R6 = MAX ( R3 , R6 ) (V);
R7 = MAX ( R3 , R7 ) (V);
CHECKREG r0, 0xC6667727;
CHECKREG r1, 0xC6667727;
CHECKREG r2, 0xC6667727;
CHECKREG r3, 0xC6667727;
CHECKREG r4, 0x63447727;
CHECKREG r5, 0x63447727;
CHECKREG r6, 0x63447727;
CHECKREG r7, 0x68667777;
imm32 r0, 0x4537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x44555535;
imm32 r3, 0x66665747;
imm32 r4, 0x88789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cdd85;
imm32 r7, 0xeeaeff9f;
R0 = MAX ( R4 , R0 ) (V);
R1 = MAX ( R4 , R1 ) (V);
R2 = MAX ( R4 , R2 ) (V);
R3 = MAX ( R4 , R3 ) (V);
R4 = MAX ( R4 , R4 ) (V);
R5 = MAX ( R4 , R5 ) (V);
R6 = MAX ( R4 , R6 ) (V);
R7 = MAX ( R4 , R7 ) (V);
CHECKREG r0, 0x45379565;
CHECKREG r1, 0x6759AB2D;
CHECKREG r2, 0x44555535;
CHECKREG r3, 0x66665747;
CHECKREG r4, 0x88789565;
CHECKREG r5, 0xAA8ABB5B;
CHECKREG r6, 0xCC9CDD85;
CHECKREG r7, 0xEEAEFF9F;
imm32 r0, 0xa56b89ab;
imm32 r1, 0x659b4bcd;
imm32 r2, 0xd9736564;
imm32 r3, 0x61278394;
imm32 r4, 0xb8876439;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0xcccc1ddd;
imm32 r7, 0x12346fff;
R0 = MAX ( R5 , R0 ) (V);
R1 = MAX ( R5 , R1 ) (V);
R2 = MAX ( R5 , R2 ) (V);
R3 = MAX ( R5 , R3 ) (V);
R4 = MAX ( R5 , R4 ) (V);
R5 = MAX ( R5 , R5 ) (V);
R6 = MAX ( R5 , R6 ) (V);
R7 = MAX ( R5 , R7 ) (V);
CHECKREG r0, 0xAAAA0BBB;
CHECKREG r1, 0x659B4BCD;
CHECKREG r2, 0xD9736564;
CHECKREG r3, 0x61270BBB;
CHECKREG r4, 0xB8876439;
CHECKREG r5, 0xAAAA0BBB;
CHECKREG r6, 0xCCCC1DDD;
CHECKREG r7, 0x12346FFF;
imm32 r0, 0x956739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0xd3456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R0 = MAX ( R6 , R0 ) (V);
R1 = MAX ( R6 , R1 ) (V);
R2 = MAX ( R6 , R2 ) (V);
R3 = MAX ( R6 , R3 ) (V);
R4 = MAX ( R6 , R4 ) (V);
R5 = MAX ( R6 , R5 ) (V);
R6 = MAX ( R6 , R6 ) (V);
R7 = MAX ( R6 , R7 ) (V);
CHECKREG r0, 0x043239AB;
CHECKREG r1, 0x67694BCD;
CHECKREG r2, 0x04326755;
CHECKREG r3, 0x66666777;
CHECKREG r4, 0x12345699;
CHECKREG r5, 0x456790D6;
CHECKREG r6, 0x043290D6;
CHECKREG r7, 0x1234567F;
imm32 r0, 0x876789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0xd3456755;
imm32 r3, 0x56789007;
imm32 r4, 0x789ab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcd2ff7;
R0 = MAX ( R7 , R0 ) (V);
R1 = MAX ( R7 , R1 ) (V);
R2 = MAX ( R7 , R2 ) (V);
R3 = MAX ( R7 , R3 ) (V);
R4 = MAX ( R7 , R4 ) (V);
R5 = MAX ( R7 , R5 ) (V);
R6 = MAX ( R7 , R6 ) (V);
R7 = MAX ( R7 , R7 ) (V);
CHECKREG r0, 0xABCD2FF7;
CHECKREG r1, 0x67792FF7;
CHECKREG r2, 0xD3456755;
CHECKREG r3, 0x56782FF7;
CHECKREG r4, 0x789A2FF7;
CHECKREG r5, 0xABCD2FF7;
CHECKREG r6, 0xABCD2FF7;
CHECKREG r7, 0xABCD2FF7;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R4 = MAX ( R4 , R7 ) (V);
R5 = MAX ( R5 , R5 ) (V);
R2 = MAX ( R6 , R3 ) (V);
R6 = MAX ( R0 , R4 ) (V);
R0 = MAX ( R1 , R6 ) (V);
R2 = MAX ( R2 , R1 ) (V);
R1 = MAX ( R3 , R0 ) (V);
R7 = MAX ( R7 , R4 ) (V);
CHECKREG r0, 0x67695699;
CHECKREG r1, 0x67696777;
CHECKREG r2, 0x67696777;
CHECKREG r3, 0x66666777;
CHECKREG r4, 0x12345699;
CHECKREG r5, 0x45678B6B;
CHECKREG r6, 0x45675699;
CHECKREG r7, 0x12345699;
imm32 r0, 0x876789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0x2345d755;
imm32 r3, 0x5678b007;
imm32 r4, 0x789ab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcd2ff7;
R3 = MAX ( R4 , R0 ) (V);
R5 = MAX ( R5 , R1 ) (V);
R2 = MAX ( R2 , R2 ) (V);
R7 = MAX ( R7 , R3 ) (V);
R4 = MAX ( R3 , R4 ) (V);
R0 = MAX ( R1 , R5 ) (V);
R1 = MAX ( R0 , R6 ) (V);
R6 = MAX ( R6 , R7 ) (V);
CHECKREG r0, 0x67790BBB;
CHECKREG r1, 0x67791D7D;
CHECKREG r2, 0x2345D755;
CHECKREG r3, 0x789AB799;
CHECKREG r4, 0x789AB799;
CHECKREG r5, 0x67790BBB;
CHECKREG r6, 0x789A2FF7;
CHECKREG r7, 0x789A2FF7;
pass
|
stsp/binutils-ia16
| 4,029
|
sim/testsuite/bfin/c_dsp32mult_pair_m_s.s
|
//Original:/testcases/core/c_dsp32mult_pair_m_s/c_dsp32mult_pair_m_s.dsp
// Spec Reference: dsp32mult pair MUNOP s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm32 r7, 0xd246712f;
R0 = R0.L * R0.L (S2RND);
R2 = R0.L * R1.H (S2RND);
R4 = R1.H * R1.H (S2RND);
R6 = R0.L * R0.L (S2RND);
CHECKREG r0, 0x73F38564;
CHECKREG r1, 0x9F7A5127;
CHECKREG r2, 0x7FFFFFFF;
CHECKREG r3, 0x00069027;
CHECKREG r4, 0x7FFFFFFF;
CHECKREG r5, 0x10ACEF2B;
CHECKREG r6, 0x7FFFFFFF;
CHECKREG r7, 0xD246712F;
imm32 r0, 0x5b23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x90060037;
imm32 r4, 0x80abcd39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c003d;
imm32 r7, 0x12467003;
R0 = R2.L * R2.L (S2RND);
R2 = R2.L * R3.H (S2RND);
R4 = R3.H * R2.H (S2RND);
R6 = R2.L * R3.L (S2RND);
CHECKREG r0, 0x52CB43E4;
CHECKREG r1, 0x6FBA5137;
CHECKREG r2, 0x7F5C6CF8;
CHECKREG r3, 0x90060037;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0xB0ACEF3B;
CHECKREG r6, 0x005DA520;
CHECKREG r7, 0x12467003;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x43246755;
imm32 r3, 0x05060055;
imm32 r4, 0x906bc509;
imm32 r5, 0x10a7ef5b;
imm32 r6, 0xb00c805d;
imm32 r7, 0x1246795f;
R0 = R4.L * R4.L (S2RND);
R2 = R4.L * R5.H (S2RND);
R4 = R5.H * R5.H (S2RND);
R6 = R4.L * R5.L (S2RND);
CHECKREG r0, 0x36536944;
CHECKREG r1, 0xC4BA5157;
CHECKREG r2, 0xF0A8637C;
CHECKREG r3, 0x05060055;
CHECKREG r4, 0x045533C4;
CHECKREG r5, 0x10A7EF5B;
CHECKREG r6, 0xF2898AB0;
CHECKREG r7, 0x1246795F;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cb06d;
imm32 r7, 0x1246706f;
R0 = R6.L * R6.L (S2RND);
R2 = R6.L * R7.H (S2RND);
R4 = R7.H * R7.H (S2RND);
R6 = R6.L * R7.L (S2RND);
CHECKREG r0, 0x62F039A4;
CHECKREG r1, 0xEFBA5166;
CHECKREG r2, 0xE9479F38;
CHECKREG r3, 0xF0060066;
CHECKREG r4, 0x0537AC90;
CHECKREG r5, 0x10ACEF6B;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x1246706F;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R0 = R0.L * R7.L (S2RND);
R2 = R1.L * R6.H (S2RND);
R4 = R3.H * R4.H (S2RND);
R6 = R4.L * R3.L (S2RND);
CHECKREG r0, 0x164DC36C;
CHECKREG r1, 0xCFBA5127;
CHECKREG r2, 0x000F3750;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0xFFF59008;
CHECKREG r5, 0x10ACDFDB;
CHECKREG r6, 0xFFF3C0E0;
CHECKREG r7, 0x1246F00F;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246905;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R1 = R7.H * R0.H (S2RND);
R3 = R6.H * R1.H (S2RND);
R5 = R5.H * R2.L (S2RND);
R7 = R4.L * R3.H (S2RND);
CHECKREG r0, 0xAB235A75;
CHECKREG r1, 0xE7C50648;
CHECKREG r2, 0x13246905;
CHECKREG r3, 0xFFFB74F0;
CHECKREG r4, 0x90ABCD09;
CHECKREG r5, 0x1B5B7D70;
CHECKREG r6, 0x000C0D0D;
CHECKREG r7, 0x0003FB4C;
imm32 r0, 0x9b235675;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946705;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c009d;
imm32 r7, 0x12467009;
R1 = R6.H * R4.L (S2RND);
R3 = R5.L * R3.H (S2RND);
R5 = R3.H * R1.L (S2RND);
R7 = R1.H * R2.H (S2RND);
CHECKREG r0, 0x9B235675;
CHECKREG r1, 0xFFED71B0;
CHECKREG r2, 0x13946705;
CHECKREG r3, 0xFFFCE2CC;
CHECKREG r4, 0x90AB9D09;
CHECKREG r5, 0xFFF8E500;
CHECKREG r6, 0x000C009D;
CHECKREG r7, 0xFFFA3010;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R4.L * R0.H (S2RND);
R3 = R6.H * R1.H (S2RND);
R5 = R1.L * R2.L (S2RND);
R7 = R4.H * R2.L (S2RND);
CHECKREG r0, 0xEB235675;
CHECKREG r1, 0x062EACEC;
CHECKREG r2, 0x13E46705;
CHECKREG r3, 0x000128A0;
CHECKREG r4, 0x90ABED09;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x000C00ED;
CHECKREG r7, 0x80000000;
pass
|
stsp/binutils-ia16
| 5,752
|
sim/testsuite/bfin/m2.s
|
// MAC test program.
// Test basic edge values
// SIGNED FRACTIONAL mode
// test ops: "+=" "-=" "=" "NOP"
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// 0x7fff * 0x7fff = 0x007ffe0002
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.L * R1.L, A0 += R0.L * R1.L;
R6 = A1.w;
_DBG ASTAT;
_DBG A0;
R7.L = A1.x;
_DBG ASTAT;
DBGA ( R6.L , 0x0002 );
DBGA ( R6.H , 0x7ffe );
DBGA ( R7.L , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// 0x8000 * 0x7fff = 0xff80010000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.H * R1.L, A0 += R0.H * R1.L;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x8001 );
DBGA ( R7.L , 0xffff );
_DBG ASTAT;
R7 = ASTAT;
DBGA (R7.H, 0x0);
DBGA (R7.L, 0x0);
// 0x8000 * 0x8000 = 0x007fffffff
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.H * R1.H, A0 += R0.H * R1.H;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x8000 );
DBGA ( R7.L , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate positive by first loading large value into accums
// expected value is 0x7fffffffff
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R3.L;
A0.w = R2;
A0.x = R3.L;
A1 += R0.L * R1.L, A0 += R0.L * R1.L;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
DBGA ( R7.L , 0x007f );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate negative
// expected value is 0x8000000000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.x = R4.L;
A0.x = R4.L;
A1 += R0.L * R1.H, A0 += R0.L * R1.H;
R6 = A1.w;
_DBG ASTAT;
R7.L = A1.x;
_DBG ASTAT;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0xff80 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive with "-="
// expected value is 0x7fffffffff
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R3.L;
A0.w = R2;
A0.x = R3.L;
A1 -= R0.H * R1.L, A0 -= R0.H * R1.L;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
DBGA ( R7.L , 0x007f );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate negative with "-="
// expected value is 0x8000000000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.x = R4.L;
A0.x = R4.L;
A1 -= R0.L * R1.L, A0 -= R0.L * R1.L;
R6 = A1.w;
_DBG ASTAT;
R7.L = A1.x;
_DBG ASTAT;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0xff80 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 );
// 0x8000 * 0x8000 = 0xff80000001 with "-="
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 -= R0.H * R1.H, A0 -= R0.H * R1.H;
R6 = A1.w;
_DBG ASTAT;
R7.L = A1.x;
_DBG ASTAT;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x8000 );
DBGA ( R7.L , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// 0x7fff * 0x7fff = 0x007ffe0002 with "="
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.L * R1.L, A0 += R0.L * R1.L;
A1 = R0.L * R1.L, A0 = R0.L * R1.L;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0002 );
DBGA ( R6.H , 0x7ffe );
DBGA ( R7.L , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// 0x7fff * 0x7fff = 0x007ffe0002 with "NOP"
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.L * R1.L;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0002 );
DBGA ( R6.H , 0x7ffe );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// 0x8000 * 0x8000 = 0x007fffffff with "NOP"
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.H * R1.H;
_DBG A1;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x8000 );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
_DBG ASTAT;
R7.L = A0.x;
_DBG ASTAT;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
R7 = ASTAT; _dbg astat;
//AV1 AV1S should be 0.
DBGA ( R7.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
_DBG ASTAT;
A1 = A0 = 0;
_DBG A1;
_DBG R0; _DBG R1;
A1 += R0.L * R1.L; // make sure overflow flag is not set to zero
_DBG A1;
_DBG ASTAT;
R7 = ASTAT;
//AV1S should be 0.
DBGA ( R7.H, 0x0000 );
DBGA ( R7.L, 0x0000 );
pass
.data
data0:
.dw 0x7fff
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
|
stsp/binutils-ia16
| 2,790
|
sim/testsuite/bfin/c_compi2opd_dr_add_i7_n.s
|
//Original:/testcases/core/c_compi2opd_dr_add_i7_n/c_compi2opd_dr_add_i7_n.dsp
// Spec Reference: compi2opd dregs += imm7 negative
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 += 0;
R1 += -1;
R2 += -2;
R3 += -3;
R4 += -4;
R5 += -5;
R6 += -6;
R7 += -7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFE;
CHECKREG r3, 0xFFFFFFFD;
CHECKREG r4, 0xFFFFFFFC;
CHECKREG r5, 0xFFFFFFFB;
CHECKREG r6, 0xFFFFFFFA;
CHECKREG r7, 0xFFFFFFF9;
R0 += -8;
R1 += -9;
R2 += -10;
R3 += -11;
R4 += -12;
R5 += -13;
R6 += -14;
R7 += -15;
CHECKREG r0, 0xFFFFFFF8;
CHECKREG r1, 0xFFFFFFF6;
CHECKREG r2, 0xFFFFFFF4;
CHECKREG r3, 0xFFFFFFF2;
CHECKREG r4, 0xFFFFFFF0;
CHECKREG r5, 0xFFFFFFEE;
CHECKREG r6, 0xFFFFFFEC;
CHECKREG r7, 0xFFFFFFEA;
R0 += -16;
R1 += -17;
R2 += -18;
R3 += -19;
R4 += -20;
R5 += -21;
R6 += -22;
R7 += -23;
CHECKREG r0, 0xFFFFFFE8;
CHECKREG r1, 0xFFFFFFE5;
CHECKREG r2, 0xFFFFFFE2;
CHECKREG r3, 0xFFFFFFDF;
CHECKREG r4, 0xFFFFFFDC;
CHECKREG r5, 0xFFFFFFD9;
CHECKREG r6, 0xFFFFFFD6;
CHECKREG r7, 0xFFFFFFD3;
R0 += -24;
R1 += -25;
R2 += -26;
R3 += -27;
R4 += -28;
R5 += -29;
R6 += -30;
R7 += -31;
CHECKREG r0, 0xFFFFFFD0;
CHECKREG r1, 0xFFFFFFCC;
CHECKREG r2, 0xFFFFFFC8;
CHECKREG r3, 0xFFFFFFC4;
CHECKREG r4, 0xFFFFFFC0;
CHECKREG r5, 0xFFFFFFBC;
CHECKREG r6, 0xFFFFFFB8;
CHECKREG r7, 0xFFFFFFB4;
R0 += -32;
R1 += -33;
R2 += -34;
R3 += -35;
R4 += -36;
R5 += -37;
R6 += -38;
R7 += -39;
CHECKREG r0, 0xFFFFFFB0;
CHECKREG r1, 0xFFFFFFAB;
CHECKREG r2, 0xFFFFFFA6;
CHECKREG r3, 0xFFFFFFA1;
CHECKREG r4, 0xFFFFFF9C;
CHECKREG r5, 0xFFFFFF97;
CHECKREG r6, 0xFFFFFF92;
CHECKREG r7, 0xFFFFFF8D;
R0 += -40;
R1 += -41;
R2 += -42;
R3 += -43;
R4 += -44;
R5 += -45;
R6 += -46;
R7 += -47;
CHECKREG r0, 0xFFFFFF88;
CHECKREG r1, 0xFFFFFF82;
CHECKREG r2, 0xFFFFFF7C;
CHECKREG r3, 0xFFFFFF76;
CHECKREG r4, 0xFFFFFF70;
CHECKREG r5, 0xFFFFFF6A;
CHECKREG r6, 0xFFFFFF64;
CHECKREG r7, 0xFFFFFF5E;
R0 += -48;
R1 += -49;
R2 += -50;
R3 += -51;
R4 += -52;
R5 += -53;
R6 += -54;
R7 += -55;
CHECKREG r0, 0xFFFFFF58;
CHECKREG r1, 0xFFFFFF51;
CHECKREG r2, 0xFFFFFF4A;
CHECKREG r3, 0xFFFFFF43;
CHECKREG r4, 0xFFFFFF3C;
CHECKREG r5, 0xFFFFFF35;
CHECKREG r6, 0xFFFFFF2E;
CHECKREG r7, 0xFFFFFF27;
R0 += -56;
R1 += -57;
R2 += -58;
R3 += -59;
R4 += -60;
R5 += -61;
R6 += -62;
R7 += -63;
CHECKREG r0, 0xFFFFFF20;
CHECKREG r1, 0xFFFFFF18;
CHECKREG r2, 0xFFFFFF10;
CHECKREG r3, 0xFFFFFF08;
CHECKREG r4, 0xFFFFFF00;
CHECKREG r5, 0xFFFFFEF8;
CHECKREG r6, 0xFFFFFEF0;
CHECKREG r7, 0xFFFFFEE8;
R0 += -64;
R1 += -64;
R2 += -64;
R3 += -64;
R4 += -64;
R5 += -64;
R6 += -64;
R7 += -64;
CHECKREG r0, 0xFFFFFEE0;
CHECKREG r1, 0xFFFFFED8;
CHECKREG r2, 0xFFFFFED0;
CHECKREG r3, 0xFFFFFEC8;
CHECKREG r4, 0xFFFFFEC0;
CHECKREG r5, 0xFFFFFEB8;
CHECKREG r6, 0xFFFFFEB0;
CHECKREG r7, 0xFFFFFEA8;
pass
|
stsp/binutils-ia16
| 23,178
|
sim/testsuite/bfin/random_0025.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R0, 0x10cfffff;
imm32 R6, 0x06a1ea20;
R0.H = R6.H >>> 0x1b;
checkreg R0, 0xd420ffff;
checkreg ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x78704000 | _VS | _V | _AC0 | _V_COPY);
imm32 R3, 0x80007fff;
R3.L = R3.L >>> 0x1f;
checkreg R3, 0x8000fffe;
checkreg ASTAT, (0x78704000 | _VS | _V | _AC0 | _V_COPY | _AN);
dmm32 ASTAT, (0x5ce08c00 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AN);
imm32 R3, 0xef9f04f4;
imm32 R6, 0x11037fff;
R3.L = R6.H >>> 0x1d;
checkreg R3, 0xef9f8818;
checkreg ASTAT, (0x5ce08c00 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x14904890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R2, 0x00af03a2;
imm32 R7, 0x0b470440;
R7.L = R2.L >>> 0x1a;
checkreg R7, 0x0b47e880;
checkreg ASTAT, (0x14904890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3040ca00 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN);
imm32 R1, 0x3bd8d8ef;
imm32 R7, 0x7b15ffff;
R1.H = R7.H >>> 0x1f;
checkreg R1, 0xf62ad8ef;
checkreg ASTAT, (0x3040ca00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x68404600 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AZ);
imm32 R0, 0xfffffffc;
imm32 R1, 0x7ffffffe;
R0.H = R1.H >>> 0x1f;
checkreg R0, 0xfffefffc;
checkreg ASTAT, (0x68404600 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AN);
dmm32 ASTAT, (0x54108890 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R1, 0x30b38b8d;
imm32 R3, 0x1c830bb1;
R1.H = R3.L >>> 0x1c;
checkreg R1, 0xbb108b8d;
checkreg ASTAT, (0x54108890 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3cc00e80 | _VS | _AV1S | _AC0);
imm32 R6, 0x1b42549c;
R6.L = R6.L >>> 0x1f;
checkreg R6, 0x1b42a938;
checkreg ASTAT, (0x3cc00e80 | _VS | _V | _AV1S | _AC0 | _V_COPY | _AN);
dmm32 ASTAT, (0x1ca04490 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY);
imm32 R0, 0x0b040a99;
imm32 R6, 0x2716ffff;
R6.H = R0.L >>> 0x1c;
checkreg R6, 0xa990ffff;
checkreg ASTAT, (0x1ca04490 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x14800880 | _VS | _AC0 | _AN | _AZ);
imm32 R2, 0x7fff7fff;
imm32 R7, 0x0a014f10;
R7 = R2 >>> 0x1f (V);
checkreg R7, 0xfffefffe;
checkreg ASTAT, (0x14800880 | _VS | _V | _AC0 | _V_COPY | _AN);
dmm32 ASTAT, (0x04a08000 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ);
imm32 R7, 0x7fffffff;
R7 = R7 >>> 0x10 (V);
checkreg R7, 0x0000ffff;
checkreg ASTAT, (0x04a08000 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x4c204090 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY);
imm32 R2, 0x00030003;
imm32 R6, 0x2c962c96;
R6 = R2 >>> 0x10 (V);
checkreg R6, 0x00000000;
checkreg ASTAT, (0x4c204090 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x14400e00 | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AQ | _AC0_COPY);
imm32 R0, 0x3a567ee8;
imm32 R4, 0x7e163337;
R0 = R4 >>> 0x10 (V);
checkreg R0, 0x00000000;
checkreg ASTAT, (0x14400e00 | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AQ | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x30200a10 | _VS | _AN);
imm32 R2, 0xffff0f44;
R2 = R2 >>> 0x1c (V);
checkreg R2, 0xfff0f440;
checkreg ASTAT, (0x30200a10 | _VS | _V | _V_COPY | _AN);
dmm32 ASTAT, (0x10c0c080 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ);
imm32 R1, 0x1d4571f3;
imm32 R2, 0x1d45ffff;
R2 = R1 >>> 0x10 (V);
checkreg R2, 0x00000000;
checkreg ASTAT, (0x10c0c080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x4cd08c90 | _VS | _AV1S | _AV0S | _CC);
imm32 R2, 0x8000ffff;
imm32 R3, 0x0f757fff;
R3 = R2 >>> 0x10 (V);
checkreg R3, 0xffffffff;
checkreg ASTAT, (0x4cd08c90 | _VS | _AV1S | _AV0S | _CC | _AN);
dmm32 ASTAT, (0x68004a00 | _VS | _AV0S | _AQ | _AN);
imm32 R6, 0x366a7fff;
imm32 R7, 0xe4ca366a;
R7 = R6 >>> 0x1f (V);
checkreg R7, 0x6cd4fffe;
checkreg ASTAT, (0x68004a00 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x14c0ca80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
imm32 R6, 0x3468e405;
imm32 R7, 0x0fd2ee59;
R7 = R6 >>> 0x10 (V);
checkreg R7, 0x0000ffff;
checkreg ASTAT, (0x14c0ca80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x1460cc90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN | _AZ);
imm32 R3, 0x2b8ffe22;
imm32 R4, 0x2f17d9d2;
R4 = R3 >>> 0x1e (V);
checkreg R4, 0xae3cf888;
checkreg ASTAT, (0x1460cc90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x30d04290 | _VS | _AC1 | _AQ | _CC);
imm32 R1, 0x3afe2bd0;
imm32 R4, 0x57e37450;
R4 = R1 >>> 0x10 (V);
checkreg R4, 0x00000000;
checkreg ASTAT, (0x30d04290 | _VS | _AC1 | _AQ | _CC | _AZ);
dmm32 ASTAT, (0x04600600 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN);
imm32 R0, 0xedbbfffe;
imm32 R4, 0x169330ac;
R0 = R4 >>> 0x1e (V);
checkreg R0, 0x5a4cc2b0;
checkreg ASTAT, (0x04600600 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AN);
dmm32 ASTAT, (0x64c0c290 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _CC | _AN);
imm32 R1, 0x788b2d30;
imm32 R6, 0x78f61ce9;
R6 = R1 >>> 0x10 (V);
checkreg R6, 0x00000000;
checkreg ASTAT, (0x64c0c290 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _CC | _AZ);
dmm32 ASTAT, (0x74d04680 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY);
imm32 R0, 0x0b7d1dc6;
imm32 R7, 0x3d27f3e5;
R7 = R0 >>> 0x10 (V);
checkreg R7, 0x00000000;
checkreg ASTAT, (0x74d04680 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x74900000 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC);
imm32 R5, 0xffc70074;
imm32 R7, 0xf49916ce;
R5 = R7 >>> 0x10 (V);
checkreg R5, 0xffff0000;
checkreg ASTAT, (0x74900000 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AN | _AZ);
dmm32 ASTAT, (0x6ca0c400 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN);
imm32 R0, 0x1e0287a7;
imm32 R4, 0x30aa2286;
R0 = R4 >>> 0x10 (V);
checkreg R0, 0x00000000;
checkreg ASTAT, (0x6ca0c400 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x10204a00 | _VS | _CC | _AN);
imm32 R5, 0xa6b04dd0;
imm32 R6, 0xfedb4cd8;
R5 = R6 >>> 0x1f (V);
checkreg R5, 0xfdb699b0;
checkreg ASTAT, (0x10204a00 | _VS | _V | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x30e04290 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY);
imm32 R2, 0x0c55766f;
imm32 R3, 0x28c00004;
R2 = R3 >>> 0x10 (V);
checkreg R2, 0x00000000;
checkreg ASTAT, (0x30e04290 | _VS | _AV1S | _AV0S | _AC1 | _AZ);
dmm32 ASTAT, (0x34b0c410 | _VS | _AQ | _CC);
imm32 R7, 0x0f7b2928;
R7 = R7 >>> 0x1e (V);
checkreg R7, 0x3deca4a0;
checkreg ASTAT, (0x34b0c410 | _VS | _V | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x18504800 | _VS | _AV1S | _AC1 | _AC0_COPY);
imm32 R4, 0x0baad54f;
imm32 R7, 0x05bf0c50;
R4 = R7 >>> 0x10 (V);
checkreg R4, 0x00000000;
checkreg ASTAT, (0x18504800 | _VS | _AV1S | _AC1 | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x2cd04290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY);
imm32 R0, 0x1199ca48;
imm32 R7, 0x4ee24366;
R7 = R0 >>> 0x10 (V);
checkreg R7, 0x0000ffff;
checkreg ASTAT, (0x2cd04290 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x24304c90 | _VS | _AV0S | _AC1 | _AC0 | _CC);
imm32 R3, 0x528af4b6;
imm32 R6, 0x18d26b4a;
R3 = R6 >>> 0x10 (V);
checkreg R3, 0x00000000;
checkreg ASTAT, (0x24304c90 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AZ);
dmm32 ASTAT, (0x70504200 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
imm32 R1, 0x255f0000;
imm32 R4, 0x96e0e654;
imm32 R6, 0x255fd442;
R4 = ASHIFT R1 BY R6.L;
checkreg R4, 0x957c0000;
checkreg ASTAT, (0x70504200 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x10004210 | _VS | _AV1S | _AC1 | _AQ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x13f865f4;
A1 = ASHIFT A1 BY R3.L;
checkreg ASTAT, (0x10004210 | _VS | _AV1S | _AC1 | _AQ | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R3, 0x13f865f4;
dmm32 ASTAT, (0x1c90c400 | _VS | _AV0S | _AC1 | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R3, 0x00000000;
A0 = ASHIFT A0 BY R3.L;
checkreg ASTAT, (0x1c90c400 | _VS | _AV0S | _AC1 | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R3, 0x00000000;
dmm32 ASTAT, (0x4820c280 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN);
dmm32 A1.w, 0x00000001;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x4a4a7fff;
A1 = LSHIFT A1 BY R3.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x4820c280 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ);
dmm32 ASTAT, (0x1c20cc10 | _VS | _AC1 | _AN);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x00000000;
A1 = LSHIFT A1 BY R0.L;
checkreg ASTAT, (0x1c20cc10 | _VS | _AC1 | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R0, 0x00000000;
dmm32 ASTAT, (0x1c608e90 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AC0_COPY | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R4, 0x10cb0000;
A0 = ASHIFT A0 BY R4.L;
checkreg ASTAT, (0x1c608e90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R4, 0x10cb0000;
dmm32 ASTAT, (0x6870ce00 | _VS | _AC1 | _AC0_COPY | _AZ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R4, 0x00000000;
A1 = LSHIFT A1 BY R4.L;
checkreg ASTAT, (0x6870ce00 | _VS | _AC1 | _AC0_COPY | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R4, 0x00000000;
dmm32 ASTAT, (0x04200290 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R2, 0x00000000;
A0 = LSHIFT A0 BY R2.L;
checkreg ASTAT, (0x04200290 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R2, 0x00000000;
dmm32 ASTAT, (0x0c404e80 | _VS | _V | _V_COPY);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R7, 0xc400e200;
A0 = ASHIFT A0 BY R7.L;
checkreg ASTAT, (0x0c404e80 | _VS | _V | _V_COPY | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R7, 0xc400e200;
dmm32 ASTAT, (0x04e00800 | _VS | _AV1S | _AV0S);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R0, 0xe603ffff;
A0 = LSHIFT A0 BY R0.L;
checkreg ASTAT, (0x04e00800 | _VS | _AV1S | _AV0S | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R0, 0xe603ffff;
dmm32 ASTAT, (0x40904090 | _VS | _AV0S | _AC1 | _CC | _AZ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R6, 0x00000000;
A1 = LSHIFT A1 BY R6.L;
checkreg ASTAT, (0x40904090 | _VS | _AV0S | _AC1 | _CC | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R6, 0x00000000;
dmm32 ASTAT, (0x24f04c10 | _VS | _V | _AC1 | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0x023d0ac0;
dmm32 A0.x, 0x00000000;
imm32 R2, 0xfffe05e0;
A0 = ASHIFT A0 BY R2.L;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x24f04c10 | _VS | _V | _AC1 | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x2860c410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AC0_COPY);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R4, 0x00000000;
A1 = ASHIFT A1 BY R4.L;
checkreg ASTAT, (0x2860c410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AC0_COPY | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R4, 0x00000000;
dmm32 ASTAT, (0x40000a00 | _VS | _V | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AN);
imm32 R2, 0x4e59ffff;
imm32 R6, 0x2c450001;
R6 = ASHIFT R2 BY R6.L (V);
checkreg R6, 0x9cb2fffe;
checkreg ASTAT, (0x40000a00 | _VS | _V | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x3c700410 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AC0_COPY | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R6, 0x0d1144c0;
A0 = LSHIFT A0 BY R6.L;
checkreg ASTAT, (0x3c700410 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R6, 0x0d1144c0;
dmm32 ASTAT, (0x5c10ca80 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x80000000;
dmm32 A1.x, 0x00000000;
imm32 R7, 0x472d2397;
A1 = LSHIFT A1 BY R7.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x5c10ca80 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x10004c00 | _VS | _AQ | _AZ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R2, 0x80000000;
A1 = LSHIFT A1 BY R2.L;
checkreg ASTAT, (0x10004c00 | _VS | _AQ | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R2, 0x80000000;
dmm32 ASTAT, (0x30308480 | _VS | _AV0S | _AQ);
dmm32 A0.w, 0x19b289d0;
dmm32 A0.x, 0x00000000;
imm32 R6, 0xffff0ce2;
A0 = LSHIFT A0 BY R6.L;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x30308480 | _VS | _AV0S | _AQ | _AZ);
dmm32 ASTAT, (0x28708280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0x3f050000;
dmm32 A0.x, 0x00000000;
imm32 R6, 0xc0fb081a;
A0 = LSHIFT A0 BY R6.L;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x28708280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x18708280 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AN);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R3, 0xeca83337;
A0 = LSHIFT A0 BY R3.L;
checkreg ASTAT, (0x18708280 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R3, 0xeca83337;
dmm32 ASTAT, (0x78b0c010 | _VS | _AV1S | _AC1 | _AC0 | _AN);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R5, 0x00000000;
A1 = ASHIFT A1 BY R5.L;
checkreg ASTAT, (0x78b0c010 | _VS | _AV1S | _AC1 | _AC0 | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R5, 0x00000000;
dmm32 ASTAT, (0x50d00680 | _VS | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x05600000;
A1 = LSHIFT A1 BY R3.L;
checkreg ASTAT, (0x50d00680 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R3, 0x05600000;
dmm32 ASTAT, (0x04108880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC);
dmm32 A0.w, 0x046b40e7;
dmm32 A0.x, 0x00000000;
imm32 R3, 0x20a220a2;
A0 = ASHIFT A0 BY R3.L;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x04108880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AZ);
dmm32 ASTAT, (0x6850cc80 | _VS | _AV1S | _AV0S | _AV0 | _AC0_COPY | _AN);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R1, 0x623d1bad;
A0 = ASHIFT A0 BY R1.L;
checkreg ASTAT, (0x6850cc80 | _VS | _AV1S | _AV0S | _AC0_COPY | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R1, 0x623d1bad;
dmm32 ASTAT, (0x44d04a80 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R4, 0x211b1629;
A1 = LSHIFT A1 BY R4.L;
checkreg ASTAT, (0x44d04a80 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R4, 0x211b1629;
dmm32 ASTAT, (0x1c304480 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R1, 0xffffa0e5;
A0 = ASHIFT A0 BY R1.L;
checkreg ASTAT, (0x1c304480 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R1, 0xffffa0e5;
dmm32 ASTAT, (0x54c00c90 | _VS | _AV0S | _AC1 | _CC | _AZ);
dmm32 A1.w, 0x01cdbb21;
dmm32 A1.x, 0x00000000;
imm32 R7, 0x696f3de3;
A1 = ASHIFT A1 BY R7.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x54c00c90 | _VS | _AV0S | _AC1 | _CC | _AZ);
dmm32 ASTAT, (0x7c30c690 | _VS | _AV1S | _AV0S | _AC1 | _AC0_COPY | _AN);
dmm32 A1.w, 0x00007400;
dmm32 A1.x, 0x00000000;
imm32 R4, 0x6fc3cc21;
A1 = LSHIFT A1 BY R4.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x7c30c690 | _VS | _AV1S | _AV0S | _AC1 | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x1c404200 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN);
imm32 R2, 0x1e000001;
imm32 R4, 0x037b7038;
imm32 R5, 0x57beffff;
R4.L = ASHIFT R5.H BY R2.L;
checkreg R4, 0x037baf7c;
checkreg ASTAT, (0x1c404200 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x24e08c80 | _VS | _AV1S | _CC);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R6, 0x11f23024;
A0 = LSHIFT A0 BY R6.L;
checkreg ASTAT, (0x24e08c80 | _VS | _AV1S | _CC | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R6, 0x11f23024;
dmm32 ASTAT, (0x3ce04080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R2, 0x00000000;
A0 = ASHIFT A0 BY R2.L;
checkreg ASTAT, (0x3ce04080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R2, 0x00000000;
dmm32 ASTAT, (0x28800280 | _VS | _AV1S | _AV0S | _CC | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x00000000;
A0 = LSHIFT A0 BY R0.L;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x28800280 | _VS | _AV1S | _AV0S | _CC | _AZ);
dmm32 ASTAT, (0x68708810 | _VS | _V | _AV1S | _AV0S | _AV1 | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0x80000000;
dmm32 A1.x, 0xffffffea;
imm32 R2, 0x0121e8d9;
A1 = ASHIFT A1 BY R2.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x68708810 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x24c00890 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x1b9411f4;
A1 = LSHIFT A1 BY R0.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x24c00890 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x4480ce00 | _VS | _AC1);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
A1 = A1 << 0x5;
checkreg ASTAT, (0x4480ce00 | _VS | _AC1 | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
dmm32 ASTAT, (0x6cf0cc10 | _VS | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x3b;
checkreg ASTAT, (0x6cf0cc10 | _VS | _AC0 | _AQ | _CC | _AC0_COPY | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
dmm32 ASTAT, (0x50d00a80 | _VS | _AV1S | _AV0S | _AC1 | _AN);
dmm32 A1.w, 0x028ab5f4;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x1f;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x50d00a80 | _VS | _AV1S | _AV0S | _AC1 | _AZ);
dmm32 ASTAT, (0x14c00490 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x0001f0f0;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x14;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x14c00490 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x14808a80 | _VS | _AV1S | _AV0S | _AC1 | _AN);
dmm32 A0.w, 0x000fc1a6;
dmm32 A0.x, 0x00000000;
A0 = A0 >> 0x1f;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x14808a80 | _VS | _AV1S | _AV0S | _AC1 | _AZ);
dmm32 ASTAT, (0x3c80ca90 | _VS | _AV0S | _AC0 | _AQ | _CC | _AZ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
A1 = A1 >>> 0x1e;
checkreg ASTAT, (0x3c80ca90 | _VS | _AV0S | _AC0 | _AQ | _CC | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
dmm32 ASTAT, (0x4c200c90 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ);
imm32 R2, 0xf1815f1a;
imm32 R7, 0x0a917fff;
R7.L = R2.L >>> 0x13;
checkreg R7, 0x0a914000;
checkreg ASTAT, (0x4c200c90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY);
dmm32 ASTAT, (0x0cf0cc80 | _VS | _AV0S | _AC0_COPY | _AZ);
imm32 R0, 0x000081ad;
imm32 R2, 0x00000000;
R2.H = R0.L >>> 0x19;
checkreg R2, 0xd6800000;
checkreg ASTAT, (0x0cf0cc80 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x04304c10 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AN);
imm32 R1, 0x33dd7fff;
imm32 R7, 0xae86a2f4;
R1 = R7 >>> 0x13 (V);
checkreg R1, 0xc0008000;
checkreg ASTAT, (0x04304c10 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x7850c800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN);
imm32 R4, 0x0000fffe;
imm32 R7, 0x5906fc4f;
R4.L = R7.H >>> 0x15;
checkreg R4, 0x00003000;
checkreg ASTAT, (0x7850c800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY);
dmm32 ASTAT, (0x64804c90 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN);
imm32 R1, 0x000009e3;
imm32 R4, 0x44418b70;
R1.H = R4.L >>> 0x17;
checkreg R1, 0xe00009e3;
checkreg ASTAT, (0x64804c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x2c508410 | _VS | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY | _AZ);
imm32 R0, 0x43d731e2;
imm32 R4, 0x60995f48;
R0.L = R4.H >>> 0x17;
checkreg R0, 0x43d73200;
checkreg ASTAT, (0x2c508410 | _VS | _V | _AV1 | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x0c900010 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
A0 = A0 >>> 0xc;
checkreg ASTAT, (0x0c900010 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
dmm32 ASTAT, (0x40c00e80 | _VS | _AV1 | _AV0S | _CC | _AN | _AZ);
imm32 R1, 0x0bf14680;
imm32 R3, 0x1875266d;
R3.H = R1.L >>> 0x1d;
checkreg R3, 0x3400266d;
checkreg ASTAT, (0x40c00e80 | _VS | _V | _AV1 | _AV0S | _CC | _V_COPY);
dmm32 ASTAT, (0x78100a00 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AC0_COPY | _AN);
imm32 R4, 0x67c0a470;
imm32 R7, 0x000026c0;
R4 = R7 >>> 0x1d (V);
checkreg R4, 0x00003600;
checkreg ASTAT, (0x78100a00 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x6cd04610 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY);
imm32 R0, 0x0f9535a6;
imm32 R5, 0x31018b62;
R0 = R5 >>> 0x12 (V);
checkreg R0, 0x40008000;
checkreg ASTAT, (0x6cd04610 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x58a08800 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R2, 0x023cffff;
imm32 R6, 0x0d6d8000;
R6.L = R2.H >>> 0x18;
checkreg R6, 0x0d6d3c00;
checkreg ASTAT, (0x58a08800 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x5cc00600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
imm32 R2, 0xa9d7c2fd;
imm32 R4, 0xfffed266;
R2.L = R4.L >>> 0x12;
checkreg R2, 0xa9d78000;
checkreg ASTAT, (0x5cc00600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x5c900400 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AN);
imm32 R1, 0xf37e61a8;
imm32 R4, 0x5522a41c;
R4 = R1 >>> 0x12 (V);
checkreg R4, 0x80000000;
checkreg ASTAT, (0x5c900400 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ);
pass
|
stsp/binutils-ia16
| 1,335
|
sim/testsuite/bfin/add_sub_acc.s
|
// ACP 5.9 A0 -= A1 doesn't set flags
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0x0;
astat=r0;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R1 = 1;
_DBG A0;
_DBG A1;
A0 -= A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x0);
dbga (r7.l, 0x1006);
A1 = A0 = 0;
R0 = 0x1 (z);
astat=r0;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R1 = 1;
_DBG A0;
_DBG A1;
A0 -= A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x0);
dbga (r7.l, 0x1006);
A1 = A0 = 0;
R0 = 0x0;
astat=r0;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R1 = 1;
A1 = R1;
_DBG A0;
_DBG A1;
A0 -= A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x3);
dbga (r7.l, 0x1006);
A1 = A0 = 0;
R0 = 0x1 (z);
astat=r0;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R1 = 2 (z);
A1 = R1;
_DBG A0;
_DBG A1;
A0 -= A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x3);
dbga (r7.l, 0x1006);
#
A1 = A0 = 0;
R0 = 0x0;
astat=r0;
R0.L=0xffff;
R0.H=0xffff;
A0.w = R0;
R1=0x7f;
A0.x = R1;
A1.x = R1;
A1.w = R0;
_DBG A0;
_DBG A1;
A0 += A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x3);
dbga (r7.l, 0x0);
A1 = A0 = 0;
R0 = 0x0;
astat=r0;
A0.w = R0;
R1=0x80;
A0.x = R1;
A1.x = R1;
A1.w = R0;
_DBG A0;
_DBG A1;
A0 += A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x3);
dbga (r7.l, 0x1006);
pass;
|
stsp/binutils-ia16
| 7,994
|
sim/testsuite/bfin/c_comp3op_dr_plus_dr.s
|
//Original:/testcases/core/c_comp3op_dr_plus_dr/c_comp3op_dr_plus_dr.dsp
// Spec Reference: comp3op dregs + dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 r7, 0x12345678;
R0 = R0 + R0;
R1 = R0 + R1;
R2 = R0 + R2;
R3 = R0 + R3;
R4 = R0 + R4;
R5 = R0 + R5;
R6 = R0 + R6;
R7 = R0 + R7;
CHECKREG r0, 0x02468ACE;
CHECKREG r1, 0x8BF258BD;
CHECKREG r2, 0x58BF258A;
CHECKREG r3, 0xE1369D02;
CHECKREG r4, 0x258BF367;
CHECKREG r5, 0x7AD7AE13;
CHECKREG r6, 0x9ABCDF00;
CHECKREG r7, 0x147AE146;
imm32 r0, 0x01231567;
imm32 r1, 0x89ab1def;
imm32 r2, 0x56781abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23451899;
imm32 r5, 0x78911345;
imm32 r6, 0x98761432;
imm32 r7, 0x12341678;
R0 = R1 + R0;
R1 = R1 + R1;
R2 = R1 + R2;
R3 = R1 + R3;
R4 = R1 + R4;
R5 = R1 + R5;
R6 = R1 + R6;
R7 = R1 + R7;
CHECKREG r0, 0x8ACE3356;
CHECKREG r1, 0x13563BDE;
CHECKREG r2, 0x69CE569A;
CHECKREG r3, 0xF2464E12;
CHECKREG r4, 0x369B5477;
CHECKREG r5, 0x8BE74F23;
CHECKREG r6, 0xABCC5010;
CHECKREG r7, 0x258A5256;
imm32 r0, 0x01234527;
imm32 r1, 0x89abcd2f;
imm32 r2, 0x56789a2c;
imm32 r3, 0xdef01224;
imm32 r4, 0x23456829;
imm32 r5, 0x78912325;
imm32 r6, 0x98765422;
imm32 r7, 0x12345628;
R0 = R2 + R0;
R1 = R2 + R1;
R2 = R2 + R2;
R3 = R2 + R3;
R4 = R2 + R4;
R5 = R2 + R5;
R6 = R2 + R6;
R7 = R2 + R7;
CHECKREG r0, 0x579BDF53;
CHECKREG r1, 0xE024675B;
CHECKREG r2, 0xACF13458;
CHECKREG r3, 0x8BE1467C;
CHECKREG r4, 0xD0369C81;
CHECKREG r5, 0x2582577D;
CHECKREG r6, 0x4567887A;
CHECKREG r7, 0xBF258A80;
imm32 r0, 0x01234563;
imm32 r1, 0x89abcde3;
imm32 r2, 0x56789ab3;
imm32 r3, 0xdef01233;
imm32 r4, 0x23456893;
imm32 r5, 0x78912343;
imm32 r6, 0x98765433;
imm32 r7, 0x12345673;
R0 = R3 + R0;
R1 = R3 + R1;
R2 = R3 + R2;
R3 = R3 + R3;
R4 = R3 + R4;
R5 = R3 + R5;
R6 = R3 + R6;
R7 = R3 + R7;
CHECKREG r0, 0xE0135796;
CHECKREG r1, 0x689BE016;
CHECKREG r2, 0x3568ACE6;
CHECKREG r3, 0xBDE02466;
CHECKREG r4, 0xE1258CF9;
CHECKREG r5, 0x367147A9;
CHECKREG r6, 0x56567899;
CHECKREG r7, 0xD0147AD9;
imm32 r0, 0x41234567;
imm32 r1, 0x49abcdef;
imm32 r2, 0x46789abc;
imm32 r3, 0x4ef01234;
imm32 r4, 0x43456899;
imm32 r5, 0x48912345;
imm32 r6, 0x48765432;
imm32 r7, 0x42345678;
R0 = R4 + R0;
R1 = R4 + R1;
R2 = R4 + R2;
R3 = R4 + R3;
R4 = R4 + R4;
R5 = R4 + R5;
R6 = R4 + R6;
R7 = R4 + R7;
CHECKREG r0, 0x8468AE00;
CHECKREG r1, 0x8CF13688;
CHECKREG r2, 0x89BE0355;
CHECKREG r3, 0x92357ACD;
CHECKREG r4, 0x868AD132;
CHECKREG r5, 0xCF1BF477;
CHECKREG r6, 0xCF012564;
CHECKREG r7, 0xC8BF27AA;
imm32 r0, 0x05234567;
imm32 r1, 0x85abcdef;
imm32 r2, 0x55789abc;
imm32 r3, 0xd5f01234;
imm32 r4, 0x25456899;
imm32 r5, 0x75912345;
imm32 r6, 0x95765432;
imm32 r7, 0x15345678;
R0 = R5 + R0;
R1 = R5 + R1;
R2 = R5 + R2;
R3 = R5 + R3;
R4 = R5 + R4;
R5 = R5 + R5;
R6 = R5 + R6;
R7 = R5 + R7;
CHECKREG r0, 0x7AB468AC;
CHECKREG r1, 0xFB3CF134;
CHECKREG r2, 0xCB09BE01;
CHECKREG r3, 0x4B813579;
CHECKREG r4, 0x9AD68BDE;
CHECKREG r5, 0xEB22468A;
CHECKREG r6, 0x80989ABC;
CHECKREG r7, 0x00569D02;
imm32 r0, 0x01264567;
imm32 r1, 0x89a6cdef;
imm32 r2, 0x56769abc;
imm32 r3, 0xdef61234;
imm32 r4, 0x23466899;
imm32 r5, 0x78962345;
imm32 r6, 0x98765432;
imm32 r7, 0x12365678;
R0 = R6 + R0;
R1 = R6 + R1;
R2 = R6 + R2;
R3 = R6 + R3;
R4 = R6 + R4;
R5 = R6 + R5;
R6 = R6 + R6;
R7 = R6 + R7;
CHECKREG r0, 0x999C9999;
CHECKREG r1, 0x221D2221;
CHECKREG r2, 0xEEECEEEE;
CHECKREG r3, 0x776C6666;
CHECKREG r4, 0xBBBCBCCB;
CHECKREG r5, 0x110C7777;
CHECKREG r6, 0x30ECA864;
CHECKREG r7, 0x4322FEDC;
imm32 r0, 0x01237567;
imm32 r1, 0x89ab7def;
imm32 r2, 0x56787abc;
imm32 r3, 0xdef07234;
imm32 r4, 0x23457899;
imm32 r5, 0x78917345;
imm32 r6, 0x98767432;
imm32 r7, 0x12345678;
R0 = R7 + R0;
R1 = R7 + R1;
R2 = R7 + R2;
R3 = R7 + R3;
R4 = R7 + R4;
R5 = R7 + R5;
R6 = R7 + R6;
R7 = R7 + R7;
CHECKREG r0, 0x1357CBDF;
CHECKREG r1, 0x9BDFD467;
CHECKREG r2, 0x68ACD134;
CHECKREG r3, 0xF124C8AC;
CHECKREG r4, 0x3579CF11;
CHECKREG r5, 0x8AC5C9BD;
CHECKREG r6, 0xAAAACAAA;
CHECKREG r7, 0x2468ACF0;
imm32 r0, 0x11234567;
imm32 r1, 0x81abcdef;
imm32 r2, 0x56189abc;
imm32 r3, 0xdef11234;
imm32 r4, 0x23451899;
imm32 r5, 0x78912145;
imm32 r6, 0x98765412;
imm32 r7, 0x12345671;
R0 = R1 + R0;
R1 = R2 + R0;
R2 = R3 + R0;
R3 = R4 + R0;
R4 = R5 + R0;
R5 = R6 + R0;
R6 = R7 + R0;
R7 = R0 + R0;
CHECKREG r0, 0x92CF1356;
CHECKREG r1, 0xE8E7AE12;
CHECKREG r2, 0x71C0258A;
CHECKREG r3, 0xB6142BEF;
CHECKREG r4, 0x0B60349B;
CHECKREG r5, 0x2B456768;
CHECKREG r6, 0xA50369C7;
CHECKREG r7, 0x259E26AC;
imm32 r0, 0x01231567;
imm32 r1, 0x29ab1def;
imm32 r2, 0x52781abc;
imm32 r3, 0xde201234;
imm32 r4, 0x23421899;
imm32 r5, 0x78912345;
imm32 r6, 0x98761232;
imm32 r7, 0x12341628;
R0 = R2 + R1;
R1 = R3 + R1;
R2 = R4 + R1;
R3 = R5 + R1;
R4 = R6 + R1;
R5 = R7 + R1;
R6 = R0 + R1;
R7 = R1 + R1;
CHECKREG r0, 0x7C2338AB;
CHECKREG r1, 0x07CB3023;
CHECKREG r2, 0x2B0D48BC;
CHECKREG r3, 0x805C5368;
CHECKREG r4, 0xA0414255;
CHECKREG r5, 0x19FF464B;
CHECKREG r6, 0x83EE68CE;
CHECKREG r7, 0x0F966046;
imm32 r0, 0x03234527;
imm32 r1, 0x893bcd2f;
imm32 r2, 0x56739a2c;
imm32 r3, 0x3ef03224;
imm32 r4, 0x23456329;
imm32 r5, 0x78312335;
imm32 r6, 0x98735423;
imm32 r7, 0x12343628;
R0 = R3 + R2;
R1 = R4 + R2;
R2 = R5 + R2;
R3 = R6 + R2;
R4 = R7 + R2;
R5 = R0 + R2;
R6 = R1 + R2;
R7 = R2 + R2;
CHECKREG r0, 0x9563CC50;
CHECKREG r1, 0x79B8FD55;
CHECKREG r2, 0xCEA4BD61;
CHECKREG r3, 0x67181184;
CHECKREG r4, 0xE0D8F389;
CHECKREG r5, 0x640889B1;
CHECKREG r6, 0x485DBAB6;
CHECKREG r7, 0x9D497AC2;
imm32 r0, 0x04234563;
imm32 r1, 0x894bcde3;
imm32 r2, 0x56749ab3;
imm32 r3, 0x4ef04233;
imm32 r4, 0x24456493;
imm32 r5, 0x78412344;
imm32 r6, 0x98745434;
imm32 r7, 0x12344673;
R0 = R4 + R3;
R1 = R5 + R3;
R2 = R6 + R3;
R3 = R7 + R3;
R4 = R0 + R3;
R5 = R1 + R3;
R6 = R2 + R3;
R7 = R3 + R3;
CHECKREG r0, 0x7335A6C6;
CHECKREG r1, 0xC7316577;
CHECKREG r2, 0xE7649667;
CHECKREG r3, 0x612488A6;
CHECKREG r4, 0xD45A2F6C;
CHECKREG r5, 0x2855EE1D;
CHECKREG r6, 0x48891F0D;
CHECKREG r7, 0xC249114C;
imm32 r0, 0x41235567;
imm32 r1, 0x49abc5ef;
imm32 r2, 0x46789a5c;
imm32 r3, 0x4ef01235;
imm32 r4, 0x53456899;
imm32 r5, 0x45912345;
imm32 r6, 0x48565432;
imm32 r7, 0x42355678;
R0 = R5 + R4;
R1 = R6 + R4;
R2 = R7 + R4;
R3 = R0 + R4;
R4 = R1 + R4;
R5 = R2 + R4;
R6 = R3 + R4;
R7 = R4 + R4;
CHECKREG r0, 0x98D68BDE;
CHECKREG r1, 0x9B9BBCCB;
CHECKREG r2, 0x957ABF11;
CHECKREG r3, 0xEC1BF477;
CHECKREG r4, 0xEEE12564;
CHECKREG r5, 0x845BE475;
CHECKREG r6, 0xDAFD19DB;
CHECKREG r7, 0xDDC24AC8;
imm32 r0, 0x05264567;
imm32 r1, 0x85ab6def;
imm32 r2, 0x657896bc;
imm32 r3, 0xd6f01264;
imm32 r4, 0x25656896;
imm32 r5, 0x75962345;
imm32 r6, 0x95766432;
imm32 r7, 0x15345678;
R0 = R6 + R5;
R1 = R7 + R5;
R2 = R0 + R5;
R3 = R1 + R5;
R4 = R2 + R5;
R5 = R3 + R5;
R6 = R4 + R5;
R7 = R5 + R5;
CHECKREG r0, 0x0B0C8777;
CHECKREG r1, 0x8ACA79BD;
CHECKREG r2, 0x80A2AABC;
CHECKREG r3, 0x00609D02;
CHECKREG r4, 0xF638CE01;
CHECKREG r5, 0x75F6C047;
CHECKREG r6, 0x6C2F8E48;
CHECKREG r7, 0xEBED808E;
imm32 r0, 0x01764567;
imm32 r1, 0x89a7cdef;
imm32 r2, 0x56767abc;
imm32 r3, 0xdef61734;
imm32 r4, 0x73466879;
imm32 r5, 0x77962347;
imm32 r6, 0x98765432;
imm32 r7, 0x12375678;
R0 = R7 + R6;
R1 = R0 + R6;
R2 = R1 + R6;
R3 = R2 + R6;
R4 = R3 + R6;
R5 = R4 + R6;
R6 = R5 + R6;
R7 = R6 + R6;
CHECKREG r0, 0xAAADAAAA;
CHECKREG r1, 0x4323FEDC;
CHECKREG r2, 0xDB9A530E;
CHECKREG r3, 0x7410A740;
CHECKREG r4, 0x0C86FB72;
CHECKREG r5, 0xA4FD4FA4;
CHECKREG r6, 0x3D73A3D6;
CHECKREG r7, 0x7AE747AC;
imm32 r0, 0x81238567;
imm32 r1, 0x88ab78ef;
imm32 r2, 0x56887a8c;
imm32 r3, 0x8ef87238;
imm32 r4, 0x28458899;
imm32 r5, 0x78817845;
imm32 r6, 0x98787482;
imm32 r7, 0x12348678;
R0 = R1 + R7;
R1 = R2 + R7;
R2 = R3 + R7;
R3 = R4 + R7;
R4 = R5 + R7;
R5 = R6 + R7;
R6 = R7 + R7;
R7 = R0 + R7;
CHECKREG r0, 0x9ADFFF67;
CHECKREG r1, 0x68BD0104;
CHECKREG r2, 0xA12CF8B0;
CHECKREG r3, 0x3A7A0F11;
CHECKREG r4, 0x8AB5FEBD;
CHECKREG r5, 0xAAACFAFA;
CHECKREG r6, 0x24690CF0;
CHECKREG r7, 0xAD1485DF;
pass
|
stsp/binutils-ia16
| 11,066
|
sim/testsuite/bfin/c_ldstidxl_st_dr_b.s
|
//Original:testcases/core/c_ldstidxl_st_dr_b/c_ldstidxl_st_dr_b.dsp
// Spec Reference: c_ldstidxl store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f5080;
imm32 r1, 0x204e6091;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80b3;
imm32 r4, 0x501b90c4;
imm32 r5, 0x600aa0d5;
imm32 r6, 0x7019b0e6;
imm32 r7, 0xd028c0f7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0xc8;
loadsym i1, DATA_ADDR_1, 0x10;
loadsym p4, DATA_ADDR_2, 0xc8;
loadsym p5, DATA_ADDR_1, 0x00;
loadsym fp, DATA_ADDR_2, 0xc8;
loadsym i3, DATA_ADDR_1, 0x00;
P3 = I1; SP = I3;
B [ P1 + 0x1101 ] = R0;
B [ P1 + 0x1013 ] = R1;
B [ P1 + 0x1015 ] = R2;
B [ P1 + 0x1007 ] = R3;
B [ P2 + -0x1019 ] = R4;
B [ P2 + -0x1011 ] = R5;
B [ P2 + -0x1013 ] = R6;
B [ P2 + -0x1015 ] = R7;
R6 = B [ P1 + 0x1101 ] (Z);
R5 = B [ P1 + 0x1013 ] (Z);
R4 = B [ P1 + 0x1015 ] (Z);
R3 = B [ P1 + 0x1007 ] (Z);
R2 = B [ P2 + -0x1019 ] (Z);
R7 = B [ P2 + -0x1011 ] (Z);
R0 = B [ P2 + -0x1013 ] (Z);
R1 = B [ P2 + -0x1015 ] (Z);
CHECKREG r0, 0x000000E6;
CHECKREG r1, 0x000000F7;
CHECKREG r2, 0x000000C4;
CHECKREG r3, 0x000000B3;
CHECKREG r4, 0x000000A2;
CHECKREG r5, 0x00000091;
CHECKREG r6, 0x00000080;
CHECKREG r7, 0x000000D5;
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
B [ P3 + 0x1011 ] = R0;
B [ P3 + 0x1023 ] = R1;
B [ P3 + 0x1025 ] = R2;
B [ P3 + 0x1027 ] = R3;
B [ P4 + -0x1029 ] = R4;
B [ P4 + -0x1021 ] = R5;
B [ P4 + -0x1033 ] = R6;
B [ P4 + -0x1035 ] = R7;
R3 = B [ P3 + 0x1011 ] (Z);
R4 = B [ P3 + 0x1023 ] (Z);
R0 = B [ P3 + 0x1025 ] (Z);
R1 = B [ P3 + 0x1027 ] (Z);
R2 = B [ P4 + -0x1029 ] (Z);
R5 = B [ P4 + -0x1021 ] (Z);
R6 = B [ P4 + -0x1033 ] (Z);
R7 = B [ P4 + -0x1035 ] (Z);
CHECKREG r0, 0x000000B2;
CHECKREG r1, 0x000000B3;
CHECKREG r2, 0x000000B4;
CHECKREG r3, 0x000000B0;
CHECKREG r4, 0x000000B1;
CHECKREG r5, 0x000000B5;
CHECKREG r6, 0x000000B6;
CHECKREG r7, 0x000000B7;
// initial values
imm32 r0, 0x10cf50c0;
imm32 r1, 0x20ce60c1;
imm32 r2, 0x30c370c2;
imm32 r3, 0x40cc80c3;
imm32 r4, 0x50cb90c4;
imm32 r5, 0x60caa0c5;
imm32 r6, 0x70c9b0c6;
imm32 r7, 0xd0c8c0c7;
B [ P5 + 0x1031 ] = R0;
B [ P5 + 0x1033 ] = R1;
B [ P5 + 0x1035 ] = R2;
B [ P5 + 0x1047 ] = R3;
B [ SP + -0x1049 ] = R4;
B [ SP + -0x1041 ] = R5;
B [ SP + -0x1043 ] = R6;
B [ SP + -0x1045 ] = R7;
R6 = B [ P5 + 0x1031 ] (Z);
R5 = B [ P5 + 0x1033 ] (Z);
R4 = B [ P5 + 0x1035 ] (Z);
R3 = B [ P5 + 0x1047 ] (Z);
R2 = B [ SP + -0x1049 ] (Z);
R0 = B [ SP + -0x1041 ] (Z);
R7 = B [ SP + -0x1043 ] (Z);
R1 = B [ SP + -0x1045 ] (Z);
CHECKREG r0, 0x000000C5;
CHECKREG r1, 0x000000C7;
CHECKREG r2, 0x000000C4;
CHECKREG r3, 0x000000C3;
CHECKREG r4, 0x000000C2;
CHECKREG r5, 0x000000C1;
CHECKREG r6, 0x000000C0;
// initial values
imm32 r0, 0x60df50d0;
imm32 r1, 0x70de60d1;
imm32 r2, 0x80dd70d2;
imm32 r3, 0x90dc80d3;
imm32 r4, 0xa0db90d4;
imm32 r5, 0xb0daa0d5;
imm32 r6, 0xc0d9b0d6;
imm32 r7, 0xd0d8c0d7;
B [ FP + 0x1051 ] = R0;
B [ FP + 0x1053 ] = R1;
B [ FP + 0x1055 ] = R2;
B [ FP + 0x1057 ] = R3;
B [ FP + 0x1059 ] = R4;
B [ FP + 0x1061 ] = R5;
B [ FP + 0x1063 ] = R6;
B [ FP + 0x1065 ] = R7;
R3 = B [ FP + 0x1051 ] (Z);
R4 = B [ FP + 0x1053 ] (Z);
R0 = B [ FP + 0x1055 ] (Z);
R1 = B [ FP + 0x1057 ] (Z);
R2 = B [ FP + 0x1059 ] (Z);
R5 = B [ FP + 0x1061 ] (Z);
R6 = B [ FP + 0x1063 ] (Z);
R7 = B [ FP + 0x1065 ] (Z);
CHECKREG r0, 0x000000D2;
CHECKREG r1, 0x000000D3;
CHECKREG r2, 0x000000D4;
CHECKREG r3, 0x000000D0;
CHECKREG r4, 0x000000D1;
CHECKREG r5, 0x000000D5;
CHECKREG r6, 0x000000D6;
CHECKREG r7, 0x000000D7;
P3 = I0; SP = I2;
pass
// Pre-load memory witb known data
// More data is defined than will actually be used
.data
// Make sure there is space between the text and data sections
.space (0x2000);
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
// Make sure there is space for us to scribble
.space (0x2000);
|
stsp/binutils-ia16
| 1,056
|
sim/testsuite/bfin/c_dsp32alu_sgn.s
|
//Original:/testcases/core/c_dsp32alu_sgn/c_dsp32alu_sgn.dsp
// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x456789ab;
imm32 r1, 0x6689abcd;
imm32 r2, 0x47445555;
imm32 r3, 0x68667777;
R4.H = R4.L = SIGN(R2.H) * R0.H + SIGN(R2.L) * R0.L;
R5.H = R5.L = SIGN(R2.H) * R1.H + SIGN(R2.L) * R1.L;
R6.H = R6.L = SIGN(R2.H) * R2.H + SIGN(R2.L) * R2.L;
R7.H = R7.L = SIGN(R2.H) * R3.H + SIGN(R2.L) * R3.L;
CHECKREG r4, 0xCF12CF12;
CHECKREG r5, 0x12561256;
CHECKREG r6, 0x9C999C99;
CHECKREG r7, 0xDFDDDFDD;
imm32 r0, 0x496789ab;
imm32 r1, 0x6489abcd;
imm32 r2, 0x4b445555;
imm32 r3, 0x6c647777;
imm32 r4, 0x8d889999;
imm32 r5, 0xaeaa4bbb;
imm32 r6, 0xcfccd44d;
imm32 r7, 0xe1eefff4;
R0.H = R0.L = SIGN(R3.H) * R4.H + SIGN(R3.L) * R4.L;
R1.H = R1.L = SIGN(R3.H) * R5.H + SIGN(R3.L) * R5.L;
R2.H = R2.L = SIGN(R3.H) * R6.H + SIGN(R3.L) * R6.L;
R3.H = R3.L = SIGN(R3.H) * R7.H + SIGN(R3.L) * R7.L;
CHECKREG r0, 0x27212721;
CHECKREG r1, 0xFA65FA65;
CHECKREG r2, 0xA419A419;
CHECKREG r3, 0xE1E2E1E2;
pass
|
stsp/binutils-ia16
| 3,385
|
sim/testsuite/bfin/c_dsp32shiftim_amix.s
|
//Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: mix
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// Ashift : positive data, count (+)=left (half reg)
imm32 r0, 0x00010001;
imm32 r1, 1;
imm32 r2, 0x00020002;
imm32 r3, 2;
R4.H = R0.H << 1;
R4.L = R0.L << 1; /* r4 = 0x00020002 */
R5.H = R2.H << 2;
R5.L = R2.L << 2; /* r5 = 0x00080008 */
R6 = R0 << 1 (V); /* r6 = 0x00020002 */
R7 = R2 << 2 (V); /* r7 = 0x00080008 */
CHECKREG r4, 0x00020002;
CHECKREG r5, 0x00080008;
CHECKREG r6, 0x00020002;
CHECKREG r7, 0x00080008;
imm32 r1, 3;
imm32 r3, 4;
R6 = R0 << 3; /* r6 = 0x00080010 */
R7 = R2 << 4;
CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */
CHECKREG r7, 0x00200020;
A0 = 0;
A0.L = R0.L;
A0.H = R0.H;
A0 = A0 << 3; /* a0 = 0x00080008 */
R5 = A0.w; /* r5 = 0x00080008 */
CHECKREG r5, 0x00080008;
imm32 r4, 0x30000003;
imm32 r1, 1;
R5 = R4 << 1; /* r5 = 0x60000006 */
imm32 r1, 2;
R6 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */
CHECKREG r5, 0x60000006;
CHECKREG r6, 0xc000000c;
// Ashift : count (-)=right (half reg)
imm32 r0, 0x10001000;
imm32 r1, -1;
imm32 r2, 0x10001000;
imm32 r3, -2;
R4.H = R0.H >>> 1;
R4.L = R0.L >>> 1; /* r4 = 0x08000800 */
R5.H = R2.H >>> 2;
R5.L = R2.L >>> 2; /* r4 = 0x04000400 */
R6 = R0 >>> 1 (V); /* r4 = 0x08000800 */
R7 = R2 >>> 2 (V); /* r4 = 0x04000400 */
CHECKREG r4, 0x08000800;
CHECKREG r5, 0x04000400;
CHECKREG r6, 0x08000800;
CHECKREG r7, 0x04000400;
// Ashift : (full reg)
imm32 r1, -3;
imm32 r3, -4;
R6 = R0 >>> 3; /* r6 = 0x02000200 */
R7 = R2 >>> 4; /* r7 = 0x01000100 */
CHECKREG r6, 0x02000200;
CHECKREG r7, 0x01000100;
// NEGATIVE
// Ashift : NEGATIVE data, count (+)=left (half reg)
imm32 r0, 0xc00f800f;
imm32 r1, 1;
imm32 r2, 0xe00fe00f;
imm32 r3, 2;
R4.H = R0.H << 1;
R4.L = R0.L << 1 (S); /* r4 = 0x801e801e */
R5.H = R2.H << 2;
R5.L = R2.L << 2; /* r4 = 0x803c803c */
CHECKREG r4, 0x801e8000;
CHECKREG r5, 0x803c803c;
imm32 r0, 0xc80fe00f;
imm32 r2, 0xe40fe00f;
imm32 r1, 4;
imm32 r3, 5;
R6 = R0 << 4; /* r6 = 0x80fe00f0 */
R7 = R2 << 5; /* r7 = 0x81fc01e0 */
CHECKREG r6, 0x80fe00f0;
CHECKREG r7, 0x81fc01e0;
imm32 r0, 0xf80fe00f;
imm32 r2, 0xfc0fe00f;
R6 = R0 << 4 (S); /* r6 = 0x80fe00f0 */
R7 = R2 << 5 (S); /* r7 = 0x81fc01e0 */
CHECKREG r6, 0x80fe00f0;
CHECKREG r7, 0x81fc01e0;
imm32 r0, 0xc80fe00f;
imm32 r2, 0xe40fe00f;
R6 = R0 << 4 (S); /* r6 = 0x80000000 zero bubble tru MSB */
R7 = R2 << 5 (S); /* r7 = 0x80000000 */
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
imm32 r0, 0xFFFFFFF4;
imm32 r2, 0xFFF00001;
R6 = R0 << 31 (S); /* r6 = 0x80000000 */
R7 = R2 << 31 (S); /* r7 = 0x80000000 */
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok
imm32 r0, 0x80f080f0;
imm32 r1, -1;
imm32 r2, 0x80f080f0;
imm32 r3, -2;
R4.H = R0.H >>> 1;
R4.L = R0.L >>> 1; /* r4 = 0xc078c078 */
R5.H = R2.H >>> 2;
R5.L = R2.L >>> 2; /* r4 = 0xe03ce03c */
CHECKREG r4, 0xc078c078;
CHECKREG r5, 0xe03ce03c;
R6 = R0 >>> 1 (V); /* r6 = 0xc078c078 */
R7 = R2 >>> 2 (V); /* r7 = 0xe03ce03c */
CHECKREG r6, 0xc078c078;
CHECKREG r7, 0xe03ce03c;
imm32 r1, -3;
imm32 r3, -4;
R6 = R0 >>> 3; /* r6 = 0xf01e101e */
R7 = R2 >>> 4; /* r7 = 0xf80f080f */
CHECKREG r6, 0xf01e101e;
CHECKREG r7, 0xf80f080f;
pass
|
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