repo_id
stringlengths 5
115
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stringlengths 4
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stsp/binutils-ia16
| 4,916
|
sim/testsuite/bfin/c_dsp32mult_dr_m_iutsh.s
|
//Original:/testcases/core/c_dsp32mult_dr_m_iutsh/c_dsp32mult_dr_m_iutsh.dsp
// Spec Reference: dsp32mult single dr munop iu tu is ih
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm32 r7, 0xd24f702f;
R4.L = R0.H * R0.L (TFU);
R5.H = R0.L * R1.L (IU);
R6.L = R1.L * R0.H (TFU);
R7.L = R1.L * R1.L (TFU);
R0.H = R0.L * R0.L (IU);
R1.L = R0.L * R1.L (TFU);
R2.L = R1.H * R0.L (IU);
R3.H = R1.L * R1.L (TFU);
CHECKREG r0, 0xFFFF5625;
CHECKREG r1, 0x9FBA1B4E;
CHECKREG r2, 0xA3FFFFFF;
CHECKREG r3, 0x02E9F027;
CHECKREG r4, 0xB0AB5482;
CHECKREG r5, 0xFFFFEF2B;
CHECKREG r6, 0xC0FC4F9C;
CHECKREG r7, 0xD24F19B9;
imm32 r0, 0xeb23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b7e5;
imm32 r3, 0x9e060037;
imm32 r4, 0x80ebcd39;
imm32 r5, 0xb0aeef3b;
imm32 r6, 0xa00ce03d;
imm32 r7, 0x12467e03;
R4.H = R2.L * R2.L (ISS2);
R5.L = R2.L * R3.H (IH);
R6.L = R3.H * R2.L (ISS2);
R7.H = R3.L * R3.L (ISS2);
R2.H = R2.L * R2.H (IH);
R3.L = R2.H * R3.H (ISS2);
R0.H = R3.L * R2.L (IH);
R1.L = R3.L * R3.L (ISS2);
CHECKREG r0, 0xDBF3A635;
CHECKREG r1, 0x6FBA7FFF;
CHECKREG r2, 0xFA9CB7E5;
CHECKREG r3, 0x9E067FFF;
CHECKREG r4, 0x7FFFCD39;
CHECKREG r5, 0xB0AE1B99;
CHECKREG r6, 0xA00C7FFF;
CHECKREG r7, 0x17A27E03;
imm32 r0, 0xdd235655;
imm32 r1, 0xc4dd5157;
imm32 r2, 0x6324d755;
imm32 r3, 0x00060055;
imm32 r4, 0x90dbc509;
imm32 r5, 0x10adef5b;
imm32 r6, 0xb00cd05d;
imm32 r7, 0x12467d5f;
R0.L = R4.L * R4.H (IU);
R1.H = R4.H * R5.L (TFU);
R2.L = R5.H * R4.L (ISS2);
R3.L = R5.L * R5.L (IH);
R4.H = R4.L * R4.H (ISS2);
R5.L = R4.L * R5.H (TFU);
R6.H = R5.H * R4.H (IU);
R7.L = R5.H * R5.H (ISS2);
CHECKREG r0, 0xDD23FFFF;
CHECKREG r1, 0x876F5157;
CHECKREG r2, 0x63248000;
CHECKREG r3, 0x00060115;
CHECKREG r4, 0x7FFFC509;
CHECKREG r5, 0x10AD0CD5;
CHECKREG r6, 0xFFFFD05D;
CHECKREG r7, 0x12467FFF;
imm32 r0, 0xcb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x1c248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90cb9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cc06d;
imm32 r7, 0x12467c6f;
// test the unsigned U=1
R0.L = R6.L * R6.L (TFU);
R1.H = R6.H * R7.L (IH);
R2.L = R7.L * R6.L (ISS2);
R3.L = R7.L * R7.L (IH);
R6.L = R6.L * R6.L (TFU);
R7.L = R6.L * R7.L (IH);
R4.L = R7.L * R6.L (TFU);
R5.L = R7.L * R7.L (ISS2);
CHECKREG r0, 0xCB2390A3;
CHECKREG r1, 0xC1CE5166;
CHECKREG r2, 0x1C248000;
CHECKREG r3, 0xF0063C7C;
CHECKREG r4, 0x90CB720D;
CHECKREG r5, 0x10AC7FFF;
CHECKREG r6, 0x800C90A3;
CHECKREG r7, 0x1246C9DF;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0xe0060007;
imm32 r4, 0x9eabcd09;
imm32 r5, 0x10ecdfdb;
imm32 r6, 0x000e000d;
imm32 r7, 0x1246e00f;
R0.H = R0.L * R7.H (IU);
R1.L = R1.H * R6.H (ISS2);
R2.L = R2.L * R5.L (IU);
R3.H = R3.H * R4.H (ISS2);
R4.L = R4.L * R3.H (IU);
R5.L = R5.H * R2.H (ISS2);
R6.H = R6.H * R1.L (IH);
R7.L = R7.L * R0.H (IU);
CHECKREG r0, 0xFFFFA675;
CHECKREG r1, 0xCFBA8000;
CHECKREG r2, 0x1324FFFF;
CHECKREG r3, 0x7FFF0007;
CHECKREG r4, 0x9EABFFFF;
CHECKREG r5, 0x10EC7FFF;
CHECKREG r6, 0xFFF9000D;
CHECKREG r7, 0x1246FFFF;
imm32 r0, 0x9b235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x93246905;
imm32 r3, 0x09060007;
imm32 r4, 0x909bcd09;
imm32 r5, 0x10a9e9db;
imm32 r6, 0x000c9d0d;
imm32 r7, 0x1246790f;
R0.L = R7.L * R0.H (TFU);
R1.L = R6.L * R1.L (TFU);
R2.H = R5.L * R2.L (TFU);
R3.L = R4.H * R3.L (TFU);
R4.L = R3.H * R4.H (TFU);
R5.H = R2.H * R5.L (TFU);
R6.L = R1.H * R6.L (TFU);
R7.L = R0.L * R7.L (TFU);
CHECKREG r0, 0x9B23495C;
CHECKREG r1, 0xCFBA31C9;
CHECKREG r2, 0x5FEF6905;
CHECKREG r3, 0x09060003;
CHECKREG r4, 0x909B0518;
CHECKREG r5, 0x57A2E9DB;
CHECKREG r6, 0x000C7F6F;
CHECKREG r7, 0x124622B0;
imm32 r0, 0xa9235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x08060007;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a88fdb;
imm32 r6, 0x000c080d;
imm32 r7, 0x1246708f;
R2.L = R0.L * R6.L (IU);
R3.L = R1.H * R7.L (IH);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IU);
R1.H = R3.L * R1.L (IH);
R4.L = R4.H * R2.L (IU);
R5.L = R5.L * R3.L (ISS2);
R6.L = R6.L * R4.L (IH);
R7.H = R7.H * R5.L (IU);
CHECKREG r0, 0xFFFFFFFF;
CHECKREG r1, 0xF84C5127;
CHECKREG r2, 0x1324FFFF;
CHECKREG r3, 0x0806E7B2;
CHECKREG r4, 0x908BFFFF;
CHECKREG r5, 0x10A87FFF;
CHECKREG r6, 0x000C0000;
CHECKREG r7, 0xFFFF708F;
imm32 r0, 0x7b235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x17246705;
imm32 r3, 0x00760007;
imm32 r4, 0x907bcd09;
imm32 r5, 0x10a7efdb;
imm32 r6, 0x000c700d;
imm32 r7, 0x1246770f;
R4.L = R5.L * R2.L (TFU);
R6.L = R6.L * R3.H (ISS2);
R0.H = R7.L * R4.H (ISS2);
R1.L = R0.H * R5.L (ISS2);
R2.L = R1.L * R6.L (IH);
R5.L = R2.L * R7.H (TFU);
R3.H = R3.H * R0.L (IH);
R7.L = R4.H * R1.H (IU);
CHECKREG r0, 0x80005675;
CHECKREG r1, 0xCFBA7FFF;
CHECKREG r2, 0x17243FFF;
CHECKREG r3, 0x00280007;
CHECKREG r4, 0x907B6085;
CHECKREG r5, 0x10A70491;
CHECKREG r6, 0x000C7FFF;
CHECKREG r7, 0x1246FFFF;
pass
|
stsp/binutils-ia16
| 10,963
|
sim/testsuite/bfin/se_loop_ppm_1.S
|
//Original:/proj/frio/dv/testcases/seq/se_loop_ppm_1/se_loop_ppm_1.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
LSETUP ( l0s , l0s ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l0s:[ -- SP ] = ( R7:5 );
LSETUP ( l1s , l1e ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l1s:R5 += 1;
l1e:[ -- SP ] = ( R7:5 );
LSETUP ( l2s , l2e ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l2s:R5 += 1;
R6 += 2;
l2e:[ -- SP ] = ( R7:5 );
LSETUP ( l3s , l3e ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l3s:R5 += 1;
R6 += 2;
R7 += 3;
l3e:[ -- SP ] = ( R7:5 );
LSETUP ( l4s , l4e ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
l4e:[ -- SP ] = ( R7:4 );
LSETUP ( l5s , l5e ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
l5e:[ -- SP ] = ( R7:4 );
LSETUP ( l6s , l6e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
l6e:[ -- SP ] = ( R7:4 );
NOP;
LSETUP ( m0s , m0s ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m0s:[ -- SP ] = ( R7:5 );
LSETUP ( m1s , m1e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m1s:R5 += 1;
m1e:[ -- SP ] = ( R7:5 );
LSETUP ( m2s , m2e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m2s:R5 += 1;
R6 += 2;
m2e:[ -- SP ] = ( R7:5 );
LSETUP ( m3s , m3e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m3s:R5 += 1;
R6 += 2;
R7 += 3;
m3e:[ -- SP ] = ( R7:5 );
LSETUP ( m4s , m4e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
m4e:[ -- SP ] = ( R7:4 );
LSETUP ( m5s , m5e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
m5e:[ -- SP ] = ( R7:4 );
LSETUP ( m6s , m6e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
m6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 1,500
|
sim/testsuite/bfin/random_0003.S
|
# Test for ASTAT AN setting when overflows occur
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x18204a80 | _AV1S | _AV0 | _AQ | _CC | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x1098e30b;
dmm32 A1.x, 0x0000001f;
imm32 R0, 0x440ed6ae;
imm32 R5, 0x3272c296;
R0.H = (A1 += R0.L * R5.H);
checkreg R0, 0x7fffd6ae;
checkreg A1.w, 0x00500e03;
checkreg A1.x, 0x0000001f;
checkreg ASTAT, (0x18204a80 | _VS | _V | _AV1S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x28c08e90 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN);
dmm32 A0.w, 0xb9da9f02;
dmm32 A0.x, 0x00000010;
imm32 R0, 0xc104b252;
R0.L = A0 (IS);
checkreg R0, 0xc1047fff;
checkreg ASTAT, (0x28c08e90 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x3cc04000 | _AV0S | _AV0 | _CC | _AC0_COPY | _AZ);
dmm32 A0.w, 0x2cc20f30;
dmm32 A0.x, 0xffffffd0;
imm32 R2, 0x367adfeb;
imm32 R5, 0x53eeff3c;
A0 += R5.H * R2.H (IS);
checkreg A0.w, 0x3e9e429c;
checkreg A0.x, 0xffffffd0;
checkreg ASTAT, (0x3cc04000 | _AV0S | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x18c0ca90 | _V | _AV1S | _AV1 | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x0614ca96;
dmm32 A1.x, 0x00000053;
imm32 R3, 0x6c490457;
R3 = (A1 -= R3.L * R3.L) (M, S2RND);
checkreg R3, 0x7fffffff;
checkreg A1.w, 0x0601f505;
checkreg A1.x, 0x00000053;
checkreg ASTAT, (0x18c0ca90 | _VS | _V | _AV1S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ);
pass
|
stsp/binutils-ia16
| 7,686
|
sim/testsuite/bfin/c_dsp32mac_pair_a1a0_s.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_s/c_dsp32mac_pair_a1a0_s.dsp
// Spec Reference: dsp32mac pair a1a0 S
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (S2RND);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (S2RND);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (S2RND);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (S2RND);
FP = A1.w;
CHECKREG r0, 0xFFF66AF0;
CHECKREG r1, 0x0009753C;
CHECKREG r2, 0x00675E70;
CHECKREG r3, 0x5E8D5630;
CHECKREG r4, 0x116128E0;
CHECKREG r5, 0xECD7B7C0;
CHECKREG r6, 0xFE443BAC;
CHECKREG r7, 0xFE443BAC;
CHECKREG p1, 0xFF221DD6;
CHECKREG p2, 0xFF221DD6;
CHECKREG p3, 0x0004BA9E;
CHECKREG p4, 0xFFFB3578;
CHECKREG p5, 0x2F46AB18;
CHECKREG sp, 0x0033AF38;
CHECKREG fp, 0xF66BDBE0;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
A0 = R2;
A1 = R3;
R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ) (S2RND);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (S2RND);
P2 = A0.w;
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (S2RND);
P5 = A1.w;
SP = A0.w;
R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (S2RND);
FP = A0.w;
CHECKREG r0, 0xFC6F3BF8;
CHECKREG r1, 0xFCAF6688;
CHECKREG r2, 0xFC404FA0;
CHECKREG r3, 0xFC807A30;
CHECKREG r4, 0xF2E4F3AC;
CHECKREG r5, 0x1229EEF2;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x0914F779;
CHECKREG p2, 0xFFFC4AC8;
CHECKREG p3, 0x0000AC92;
CHECKREG p4, 0xFFFC4AC8;
CHECKREG p5, 0xFE403D18;
CHECKREG sp, 0xFE2027D0;
CHECKREG fp, 0xFE379DFC;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
A0 = R0;
A1 = R1;
R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (S2RND);
P1 = A1.w;
P2 = A0.w;
R7 = ( A1 = R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (S2RND);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (S2RND);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ) (S2RND);
FP = A0.w;
CHECKREG r0, 0x7FFFFFFF;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x7FFFFFFF;
CHECKREG r5, 0x0011A900;
CHECKREG r6, 0x000C5E30;
CHECKREG r7, 0x000C5E30;
CHECKREG p1, 0x7E10BF43;
CHECKREG p2, 0xCB200616;
CHECKREG p3, 0x00062F18;
CHECKREG p5, 0x00000000;
CHECKREG p4, 0x00062F18;
CHECKREG sp, 0x69C62F18;
CHECKREG fp, 0x69CF0398;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
A0 = R0;
A1 = R1;
R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (S2RND);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (S2RND);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (S2RND);
P5 = A1.w;
SP = A0.w;
R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (S2RND);
FP = A0.w;
CHECKREG r0, 0xFFF3DD34;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x7FFFFFFF;
CHECKREG r4, 0xFFEAE6E8;
CHECKREG r5, 0xFFEAE6E8;
CHECKREG r6, 0xFACD5268;
CHECKREG r7, 0xFFE66AC8;
CHECKREG p1, 0xA2B53ED1;
CHECKREG p2, 0xFFF9EE9A;
CHECKREG p3, 0x56EC0000;
CHECKREG p4, 0x00000000;
CHECKREG p5, 0xFFF57374;
CHECKREG sp, 0xFFF57374;
CHECKREG fp, 0xFD66A934;
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
A0 = R0;
A1 = R1;
R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (S2RND);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 -= R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (S2RND);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (S2RND);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (S2RND);
FP = A0.w;
CHECKREG r0, 0xFFF66AF0;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x20866AF0;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x31803560;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0xFE443BAC;
CHECKREG r7, 0x80000000;
CHECKREG p1, 0x864E0DB2;
CHECKREG p2, 0xFF221DD6;
CHECKREG p3, 0x864BB063;
CHECKREG p4, 0xFFFB3578;
CHECKREG p5, 0x864BB063;
CHECKREG sp, 0x10433578;
CHECKREG fp, 0x18C01AB0;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
A0 = R0;
A1 = R1;
R5 = A1, R4 = ( A0 = R3.L * R0.L ) (S2RND);
P1 = A1.w;
P2 = A0.w;
R1 = A1, R0 = ( A0 = R2.H * R1.L ) (S2RND);
P3 = A1.w;
P4 = A0.w;
R3 = A1, R2 = ( A0 += R7.H * R5.H ) (S2RND);
P5 = A1.w;
SP = A0.w;
R1 = A1, R0 = ( A0 += R4.L * R6.H ) (S2RND);
FP = A1.w;
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x0005D6C4;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xA1BCF4C7;
CHECKREG p2, 0x0002EB62;
CHECKREG p3, 0xA1BCF4C7;
CHECKREG p4, 0x08528D18;
CHECKREG p5, 0xA1BCF4C7;
CHECKREG sp, 0xA0C48D18;
CHECKREG fp, 0xA1BCF4C7;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
A0 = R0;
A1 = R1;
R5 = ( A1 += R1.H * R6.L ) (M), R4 = ( A0 = R1.L * R6.L ) (S2RND);
P1 = A1.w;
P2 = A0.w;
R7 = A1, R6 = ( A0 -= R4.H * R3.L ) (S2RND);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R2.H * R5.L ) (M), R0 = ( A0 += R2.H * R5.H ) (S2RND);
P5 = A1.w;
SP = A0.w;
R5 = A1, R4 = ( A0 += R0.L * R7.H ) (S2RND);
FP = A1.w;
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x9EA59954;
CHECKREG r7, 0x80000000;
CHECKREG p1, 0x96C29605;
CHECKREG p2, 0xCF4D7916;
CHECKREG p3, 0x96C29605;
CHECKREG p4, 0xCF52CCAA;
CHECKREG p5, 0x00000000;
CHECKREG sp, 0x5E3ECCAA;
CHECKREG fp, 0x00000000;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
A0 = R0;
A1 = R1;
R1 = A1, R0 = ( A0 -= R5.L * R3.L ) (S2RND);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 -= R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (S2RND);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 -= R7.H * R0.H ) (S2RND);
P5 = A0.w;
SP = A1.w;
R7 = A1, R6 = ( A0 += R4.L * R6.H ) (S2RND);
FP = A0.w;
CHECKREG r0, 0x24753646;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0xC4D53E28;
CHECKREG r5, 0x1D9560EC;
CHECKREG r6, 0xD18105A8;
CHECKREG r7, 0x1D9560EC;
CHECKREG p1, 0x91BCFEC7;
CHECKREG p2, 0x123A9B23;
CHECKREG p3, 0xBD32FEC7;
CHECKREG p4, 0x00000000;
CHECKREG p5, 0xE26A9F14;
CHECKREG sp, 0x0ECAB076;
CHECKREG fp, 0xE8C082D4;
pass
|
stsp/binutils-ia16
| 3,835
|
sim/testsuite/bfin/c_pushpopmultiple_dp_pair.s
|
//Original:/testcases/core/c_pushpopmultiple_dp_pair/c_pushpopmultiple_dp_pair.dsp
// Spec Reference: pushpopmultiple dreg preg in group pair
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
P1 = 0xa1 (X);
P2 = 0xa2 (X);
P3 = 0xa3 (X);
P4 = 0xa4 (X);
P5 = 0xa5 (X);
[ -- SP ] = ( R7:0, P5:1 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
P2 = 0xb2 (X);
P3 = 0xb3 (X);
P4 = 0xb4 (X);
P5 = 0xb5 (X);
[ -- SP ] = ( R7:1, P5:2 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
P3 = 0xc3 (X);
P4 = 0xc4 (X);
P5 = 0xc5 (X);
[ -- SP ] = ( R7:2, P5:3 );
R3 = 0x34;
R4 = 0x35;
R5 = 0x36;
R6 = 0x37;
R7 = 0x38;
P4 = 0xd4 (X);
P5 = 0xd5 (X);
[ -- SP ] = ( R7:3, P5:4 );
R4 = 0x45 (X);
R5 = 0x46 (X);
R6 = 0x47 (X);
R7 = 0x48 (X);
P5 = 0xe5 (X);
[ -- SP ] = ( R7:4, P5:5 );
R5 = 0x56 (X);
R6 = 0x57 (X);
R7 = 0x58 (X);
[ -- SP ] = ( R7:5 );
R6 = 0x67 (X);
R7 = 0x68 (X);
[ -- SP ] = ( R7:6 );
R7 = 0x78 (X);
[ -- SP ] = ( R7:7 );
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
P1 = 0;
P2 = 0;
P3 = 0;
P4 = 0;
P5 = 0;
( R7:7 ) = [ SP ++ ];
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000078;
( R7:6 ) = [ SP ++ ];
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000067;
CHECKREG r7, 0x00000068;
( R7:5 ) = [ SP ++ ];
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000056;
CHECKREG r6, 0x00000057;
CHECKREG r7, 0x00000058;
( R7:4, P5:5 ) = [ SP ++ ];
CHECKREG p1, 0x00000000;
CHECKREG p2, 0x00000000;
CHECKREG p3, 0x00000000;
CHECKREG p4, 0x00000000;
CHECKREG p5, 0x000000e5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000045;
CHECKREG r5, 0x00000046;
CHECKREG r6, 0x00000047;
CHECKREG r7, 0x00000048;
( R7:3, P5:4 ) = [ SP ++ ];
CHECKREG p1, 0x00000000;
CHECKREG p2, 0x00000000;
CHECKREG p3, 0x00000000;
CHECKREG p4, 0x000000d4;
CHECKREG p5, 0x000000d5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000035;
CHECKREG r5, 0x00000036;
CHECKREG r6, 0x00000037;
CHECKREG r7, 0x00000038;
( R7:2, P5:3 ) = [ SP ++ ];
CHECKREG p1, 0x00000000;
CHECKREG p2, 0x00000000;
CHECKREG p3, 0x000000c3;
CHECKREG p4, 0x000000c4;
CHECKREG p5, 0x000000c5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000023;
CHECKREG r3, 0x00000024;
CHECKREG r4, 0x00000025;
CHECKREG r5, 0x00000026;
CHECKREG r6, 0x00000027;
CHECKREG r7, 0x00000028;
( R7:1, P5:2 ) = [ SP ++ ];
CHECKREG p1, 0x00000000;
CHECKREG p2, 0x000000b2;
CHECKREG p3, 0x000000b3;
CHECKREG p4, 0x000000b4;
CHECKREG p5, 0x000000b5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x00000013;
CHECKREG r3, 0x00000014;
CHECKREG r4, 0x00000015;
CHECKREG r5, 0x00000016;
CHECKREG r6, 0x00000017;
CHECKREG r7, 0x00000018;
( R7:0, P5:1 ) = [ SP ++ ];
CHECKREG p1, 0x000000a1;
CHECKREG p2, 0x000000a2;
CHECKREG p3, 0x000000a3;
CHECKREG p4, 0x000000a4;
CHECKREG p5, 0x000000a5;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000003;
CHECKREG r3, 0x00000004;
CHECKREG r4, 0x00000005;
CHECKREG r5, 0x00000006;
CHECKREG r6, 0x00000007;
CHECKREG r7, 0x00000008;
pass
|
stsp/binutils-ia16
| 1,967
|
sim/testsuite/bfin/c_dsp32alu_byteop2.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop2/c_dsp32alu_byteop2.dsp
// Spec Reference: dsp32alu byteop2
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R4 = BYTEOP2P ( R1:0 , R3:2 ) (RNDL);
R5 = BYTEOP2P ( R1:0 , R3:2 ) (RNDL , R);
R6 = BYTEOP2P ( R1:0 , R3:2 ) (RNDH);
R7 = BYTEOP2P ( R1:0 , R3:2 ) (RNDH , R);
CHECKREG r4, 0x003D0041;
CHECKREG r5, 0x00570056;
CHECKREG r6, 0x3D004100;
CHECKREG r7, 0x57005600;
imm32 r0, 0x1567892b;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x34445525;
imm32 r3, 0x46667727;
imm32 r4, 0x58889929;
imm32 r5, 0x6aaabb2b;
imm32 r6, 0x7cccdd2d;
imm32 r7, 0x8eeeffff;
R0 = BYTEOP2P ( R3:2 , R1:0 ) (RNDL);
R1 = BYTEOP2P ( R3:2 , R1:0 ) (RNDL , R);
R2 = BYTEOP2P ( R3:2 , R1:0 ) (RNDH);
R3 = BYTEOP2P ( R3:2 , R1:0 ) (RNDH , R);
CHECKREG r0, 0x003D004C;
CHECKREG r1, 0x0057005E;
CHECKREG r2, 0x2D003200;
CHECKREG r3, 0x41003F00;
imm32 r0, 0x716789ab;
imm32 r1, 0x8289abcd;
imm32 r2, 0x93445555;
imm32 r3, 0xa4667777;
imm32 r4, 0xb56789ab;
imm32 r5, 0xd689abcd;
imm32 r6, 0xe7445555;
imm32 r7, 0x6f661235;
R4 = BYTEOP2P ( R1:0 , R3:2 ) (TL);
R5 = BYTEOP2P ( R1:0 , R3:2 ) (TL , R);
R6 = BYTEOP2P ( R1:0 , R3:2 ) (TH);
R7 = BYTEOP2P ( R1:0 , R3:2 ) (TH , R);
CHECKREG r4, 0x006B0077;
CHECKREG r5, 0x00850099;
CHECKREG r6, 0x6B007700;
CHECKREG r7, 0x85009900;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r4, 0x456789ab;
imm32 r5, 0x6689abcd;
imm32 r6, 0x47445555;
imm32 r7, 0x68667777;
R0 = BYTEOP2P ( R3:2 , R1:0 ) (TL);
R1 = BYTEOP2P ( R3:2 , R1:0 ) (TL , R);
R2 = BYTEOP2P ( R3:2 , R1:0 ) (TH);
R3 = BYTEOP2P ( R3:2 , R1:0 ) (TH , R);
CHECKREG r0, 0x004B0077;
CHECKREG r1, 0x006D0099;
CHECKREG r2, 0x34004800;
CHECKREG r3, 0x4D006100;
pass
|
stsp/binutils-ia16
| 5,857
|
sim/testsuite/bfin/c_dsp32alu_rh_rnd20_m.s
|
//Original:/testcases/core/c_dsp32alu_rh_rnd20_m/c_dsp32alu_rh_rnd20_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x46a67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678aab1d;
imm32 r6, 0x7444a515;
imm32 r7, 0x86667a77;
R0.H = R0 - R0 (RND20);
R1.H = R0 - R1 (RND20);
R2.H = R0 - R2 (RND20);
R3.H = R0 - R3 (RND20);
R4.H = R0 - R4 (RND20);
R5.H = R0 - R5 (RND20);
R6.H = R0 - R6 (RND20);
R7.H = R0 - R7 (RND20);
CHECKREG r0, 0x00008911;
CHECKREG r1, 0xFD57AB1D;
CHECKREG r2, 0xFCB65515;
CHECKREG r3, 0xFB967717;
CHECKREG r4, 0xFA98891B;
CHECKREG r5, 0xF987AB1D;
CHECKREG r6, 0xF8BCA515;
CHECKREG r7, 0x079A7A77;
imm32 r0, 0xa5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xb4445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5b78891b;
imm32 r5, 0x67bbab1d;
imm32 r6, 0x7444b515;
imm32 r7, 0x86667b77;
R0.H = R1 - R0 (RND20);
R1.H = R1 - R1 (RND20);
R2.H = R1 - R2 (RND20);
R3.H = R1 - R3 (RND20);
R4.H = R1 - R4 (RND20);
R5.H = R1 - R5 (RND20);
R6.H = R1 - R6 (RND20);
R7.H = R1 - R7 (RND20);
CHECKREG r0, 0x08228911;
CHECKREG r1, 0x0000AB1D;
CHECKREG r2, 0x04BC5515;
CHECKREG r3, 0xFB9A7717;
CHECKREG r4, 0xFA49891B;
CHECKREG r5, 0xF984AB1D;
CHECKREG r6, 0xF8BCB515;
CHECKREG r7, 0x079A7B77;
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x3a445515;
imm32 r3, 0x46a67717;
imm32 r4, 0x567a891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445a15;
imm32 r7, 0x866677a7;
R0.H = R2 - R0 (RND20);
R1.H = R2 - R1 (RND20);
R2.H = R2 - R2 (RND20);
R3.H = R2 - R3 (RND20);
R4.H = R2 - R4 (RND20);
R5.H = R2 - R5 (RND20);
R6.H = R2 - R6 (RND20);
R7.H = R2 - R7 (RND20);
CHECKREG r0, 0x094E8911;
CHECKREG r1, 0x00FCAB1D;
CHECKREG r2, 0x00005515;
CHECKREG r3, 0xFB967717;
CHECKREG r4, 0xFA98891B;
CHECKREG r5, 0xF987AB1D;
CHECKREG r6, 0xF8BC5A15;
CHECKREG r7, 0x079A77A7;
imm32 r0, 0xb5678911;
imm32 r1, 0xb789ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46d67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678ddb1d;
imm32 r6, 0x74445d15;
imm32 r7, 0x866677d7;
R0.H = R3 - R0 (RND20);
R1.H = R3 - R1 (RND20);
R2.H = R3 - R2 (RND20);
R3.H = R3 - R3 (RND20);
R4.H = R3 - R4 (RND20);
R5.H = R3 - R5 (RND20);
R6.H = R3 - R6 (RND20);
R7.H = R3 - R7 (RND20);
CHECKREG r0, 0x09178911;
CHECKREG r1, 0x08F5AB1D;
CHECKREG r2, 0x00995515;
CHECKREG r3, 0x00007717;
CHECKREG r4, 0xFA98891B;
CHECKREG r5, 0xF987DB1D;
CHECKREG r6, 0xF8BC5D15;
CHECKREG r7, 0x079A77D7;
imm32 r0, 0xd5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xd4445515;
imm32 r3, 0xd6667717;
imm32 r4, 0x5d78891b;
imm32 r5, 0x67d9ab1d;
imm32 r6, 0x744d5515;
imm32 r7, 0x8666dd77;
R0.H = R4 - R0 (RND20);
R1.H = R4 - R1 (RND20);
R2.H = R4 - R2 (RND20);
R3.H = R4 - R3 (RND20);
R4.H = R4 - R4 (RND20);
R5.H = R4 - R5 (RND20);
R6.H = R4 - R6 (RND20);
R7.H = R4 - R7 (RND20);
CHECKREG r0, 0x08818911;
CHECKREG r1, 0x035FAB1D;
CHECKREG r2, 0x08935515;
CHECKREG r3, 0x08717717;
CHECKREG r4, 0x0000891B;
CHECKREG r5, 0xF982AB1D;
CHECKREG r6, 0xF8BB5515;
CHECKREG r7, 0x079ADD77;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34d45515;
imm32 r3, 0x46667717;
imm32 r4, 0x567d891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x74445d15;
imm32 r7, 0x866677d7;
R0.H = R5 - R0 (RND20);
R1.H = R5 - R1 (RND20);
R2.H = R5 - R2 (RND20);
R3.H = R5 - R3 (RND20);
R4.H = R5 - R4 (RND20);
R5.H = R5 - R5 (RND20);
R6.H = R5 - R6 (RND20);
R7.H = R5 - R7 (RND20);
CHECKREG r0, 0x08228911;
CHECKREG r1, 0x0390AB1D;
CHECKREG r2, 0x032B5515;
CHECKREG r3, 0x02127717;
CHECKREG r4, 0x0111891B;
CHECKREG r5, 0x0000DB1D;
CHECKREG r6, 0xF8BC5D15;
CHECKREG r7, 0x079A77D7;
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x46a67717;
imm32 r4, 0x56a8891b;
imm32 r5, 0x678aab1d;
imm32 r6, 0x7444a515;
imm32 r7, 0x86667a77;
R0.H = R6 - R0 (RND20);
R1.H = R6 - R1 (RND20);
R2.H = R6 - R2 (RND20);
R3.H = R6 - R3 (RND20);
R4.H = R6 - R4 (RND20);
R5.H = R6 - R5 (RND20);
R6.H = R6 - R6 (RND20);
R7.H = R6 - R7 (RND20);
CHECKREG r0, 0x0CEE8911;
CHECKREG r1, 0x049CAB1D;
CHECKREG r2, 0x03FA5515;
CHECKREG r3, 0x02DA7717;
CHECKREG r4, 0x01DA891B;
CHECKREG r5, 0x00CCAB1D;
CHECKREG r6, 0x0000A515;
CHECKREG r7, 0x079A7A77;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.H = R7 - R0 (RND20);
R1.H = R7 - R1 (RND20);
R2.H = R7 - R2 (RND20);
R3.H = R7 - R3 (RND20);
R4.H = R7 - R4 (RND20);
R5.H = R7 - R5 (RND20);
R6.H = R7 - R6 (RND20);
R7.H = R7 - R7 (RND20);
CHECKREG r0, 0xF7108911;
CHECKREG r1, 0xF5EEAB1D;
CHECKREG r2, 0xF5225515;
CHECKREG r3, 0xF4007717;
CHECKREG r4, 0xF2FF891B;
CHECKREG r5, 0xF1EEAB1D;
CHECKREG r6, 0xF1225515;
CHECKREG r7, 0x00007777;
imm32 r0, 0xe5678911;
imm32 r1, 0xe789ab1d;
imm32 r2, 0xe4445515;
imm32 r3, 0x4ee67717;
imm32 r4, 0x567e891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444e515;
imm32 r7, 0x86667e77;
R6.H = R2 - R3 (RND20);
R1.H = R4 - R5 (RND20);
R5.H = R7 - R2 (RND20);
R3.H = R0 - R0 (RND20);
R0.H = R3 - R4 (RND20);
R2.H = R5 - R7 (RND20);
R7.H = R6 - R7 (RND20);
R4.H = R1 - R6 (RND20);
CHECKREG r0, 0xFA988911;
CHECKREG r1, 0xFEEFAB1D;
CHECKREG r2, 0x073C5515;
CHECKREG r3, 0x00007717;
CHECKREG r4, 0x005A891B;
CHECKREG r5, 0xFA22AB1D;
CHECKREG r6, 0xF956E515;
CHECKREG r7, 0x072F7E77;
imm32 r0, 0xe5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46d67717;
imm32 r4, 0x567d891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x7444d515;
imm32 r7, 0x86667d77;
R3.H = R4 - R0 (RND20);
R1.H = R6 - R3 (RND20);
R4.H = R3 - R2 (RND20);
R6.H = R7 - R1 (RND20);
R2.H = R5 - R4 (RND20);
R7.H = R2 - R7 (RND20);
R0.H = R1 - R6 (RND20);
R5.H = R0 - R5 (RND20);
CHECKREG r0, 0x00EE8911;
CHECKREG r1, 0x06D3AB1D;
CHECKREG r2, 0x06AF5515;
CHECKREG r3, 0x07117717;
CHECKREG r4, 0xFC9D891B;
CHECKREG r5, 0xF996DB1D;
CHECKREG r6, 0xF7F9D515;
CHECKREG r7, 0x08057D77;
pass
|
stsp/binutils-ia16
| 1,239
|
sim/testsuite/bfin/c_dsp32alu_rlh_rnd.s
|
//Original:/testcases/core/c_dsp32alu_rlh_rnd/c_dsp32alu_rlh_rnd.dsp
// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x4537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x44555535;
imm32 r3, 0x66665747;
imm32 r4, 0x88789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cdd85;
imm32 r7, 0xeeaeff9f;
R0.L = R1 (RND);
R0.H = R2 (RND);
R1.L = R3 (RND);
R1.H = R4 (RND);
R2.L = R5 (RND);
R2.H = R6 (RND);
CHECKREG r0, 0x4455675A;
CHECKREG r1, 0x88796666;
CHECKREG r2, 0xCC9DAA8B;
imm32 r0, 0xe537891b;
imm32 r1, 0xf759ab2d;
imm32 r2, 0x4ef55535;
imm32 r3, 0x666b5747;
imm32 r4, 0xc8789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0x8c9cdd85;
imm32 r7, 0x9eaeff9f;
R3.L = R0 (RND);
R3.H = R1 (RND);
R4.L = R2 (RND);
R4.H = R5 (RND);
R5.L = R6 (RND);
R5.H = R7 (RND);
CHECKREG r3, 0xF75AE538;
CHECKREG r4, 0xAA8B4EF5;
CHECKREG r5, 0x9EAF8C9D;
imm32 r0, 0x5537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x8ef55535;
imm32 r3, 0x666b5747;
imm32 r4, 0xc8789565;
imm32 r5, 0xea8abb5b;
imm32 r6, 0xfc9cdd85;
imm32 r7, 0x9eaeff9f;
R6.L = R0 (RND);
R6.H = R1 (RND);
R7.L = R2 (RND);
R7.H = R3 (RND);
R5.L = R4 (RND);
R5.H = R5 (RND);
CHECKREG r5, 0xEA8BC879;
CHECKREG r6, 0x675A5538;
CHECKREG r7, 0x666B8EF5;
pass
|
stsp/binutils-ia16
| 9,410
|
sim/testsuite/bfin/lmu_excpt_default.S
|
//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_default/lmu_excpt_default.dsp
// Description: Default protection checks (CPLB disabled)
// - MMR access in User mode
// - DAG1 Access MMRs (supv/user mode, read/write)
// - DAG1 Access Scratch SRAM (user or supervisor mode, read/write)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#define EXCPT_PROTVIOL 0x23
#define OMODE_SUPV 0 // not used in the hardware
CHECK_INIT(p5, 0xE0000000);
// setup interrupt controller with exception handler address
WR_MMR_LABEL(EVT3, handler, p0, r1);
WR_MMR_LABEL(EVT15, Supv, p0, r1);
WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0);
WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0);
CSYNC;
A0 = 0;
// go to user mode. and enable exceptions
LD32_LABEL(r0, User);
RETI = R0;
// But first raise interrupt 15 so we can run in supervisor mode.
RAISE 15;
RTI;
Supv:
//-------------------------------------------------------
// DAG1 MMR Write access
LD32(i1, (DCPLB_ADDR0));
LD32_LABEL(p2, Y01); // Exception handler will return to this address
LD32(r0, 0xdeadbeef);
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X01: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
Y01:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS
CHECKREG_SYM(r7, X01, r0); // RETX X01: (HARDCODED ADDR!!)
//-------------------------------------------------------
// DAG1 MMR Read access
LD32(i1, (DCPLB_ADDR1));
LD32_LABEL(p2, Y02); // Exception handler will return to this address
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X02: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
Y02:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS
CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS
CHECKREG_SYM(r7, X02, r0); // RETX X02: (HARDCODED ADDR!!)
#if 0
//-------------------------------------------------------
// DAG1 Scratch SRAM Write access
LD32(i1, (( 0xFF800000 + 0x300000)));
LD32_LABEL(p2, Y03); // Exception handler will return to this address
LD32(r1, 0xdeadbeef);
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X03: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
Y03:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS
CHECKREG_SYM(r7, X03, r0); // RETX X03: (HARDCODED ADDR!!)
//-------------------------------------------------------
// DAG1 Scratch SRAM Read access
LD32(i1, ((( 0xFF800000 + 0x300000) + 4)));
LD32_LABEL(p2, Y04); // Exception handler will return to this address
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X04: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
Y04:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS
CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS
CHECKREG_SYM(r7, X04, r0); // RETX X04: (HARDCODED ADDR!!)
#endif
//-------------------------------------------------------
// Now, go to User mode
LD32_LABEL(r0, User);
RETI = R0;
RTI;
User:
//-------------------------------------------------------
// DAG0 MMR Write access (multi-issue)
LD32(i1, (DCPLB_ADDR0));
LD32_LABEL(p2, Y11); // Exception handler will return to this address
LD32(r0, 0xdeadbeef);
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X11: A0 = 0 || [ I1 ] = R1 || NOP; // Exception should occur here
Y11:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS
CHECKREG_SYM(r7, X11, r0); // RETX X11: (HARDCODED ADDR!!)
//-------------------------------------------------------
// DAG0 MMR Read access (multi-issue)
LD32(i1, (DCPLB_ADDR1));
LD32_LABEL(p2, Y12); // Exception handler will return to this address
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X12: A0 = 0 || R1 = [ I1 ] || NOP; // Exception should occur here
Y12:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS
CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS
CHECKREG_SYM(r7, X12, r0); // RETX X12: (HARDCODED ADDR!!)
//-------------------------------------------------------
// DAG1 MMR Write access
LD32(i1, (DCPLB_ADDR0));
LD32_LABEL(p2, Y13); // Exception handler will return to this address
LD32(r0, 0xdeadbeef);
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
Y13:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS
CHECKREG_SYM(r7, X13, r0); // RETX X13: (HARDCODED ADDR!!)
//-------------------------------------------------------
// DAG1 MMR Read access
LD32(i1, (DCPLB_ADDR1));
LD32_LABEL(p2, Y14); // Exception handler will return to this address
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X14: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
Y14:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS
CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS
CHECKREG_SYM(r7, X14, r0); // RETX X14: (HARDCODED ADDR!!)
#if 0
//-------------------------------------------------------
// DAG1 Scratch SRAM Write access
LD32(i1, (( 0xFF800000 + 0x300000)));
LD32_LABEL(p2, Y15); // Exception handler will return to this address
LD32(r1, 0xdeadbeef);
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X15: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
Y15:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS
CHECKREG_SYM(r7, X15, r0); // RETX X15: (HARDCODED ADDR!!)
//-------------------------------------------------------
// DAG1 Scratch SRAM Read access
LD32(i1, ((( 0xFF800000 + 0x300000) + 4)));
LD32_LABEL(p2, Y16); // Exception handler will return to this address
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
Y16:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS
CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS
CHECKREG_SYM(r7, X16, r0); // RETX X16: (HARDCODED ADDR!!)
#endif
//-------------------------------------------------------
// DAG0 MMR Write access (single-issue)
LD32(i1, (DCPLB_ADDR0));
LD32_LABEL(p2, Y17); // Exception handler will return to this address
LD32(r0, 0xdeadbeef);
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X17: [ I1 ] = R1; // Exception should occur here
Y17:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS
CHECKREG_SYM(r7, X17, r0); // RETX X17: (HARDCODED ADDR!!)
//-------------------------------------------------------
// DAG0 MMR Read access (single-issue)
LD32(i1, (DCPLB_ADDR1));
LD32_LABEL(p2, Y18); // Exception handler will return to this address
R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X18: R1 = [ I1 ]; // Exception should occur here
Y18:
// Now check that handler read correct values
CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS
CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS
CHECKREG_SYM(r7, X18, r0); // RETX X18: (HARDCODED ADDR!!)
//-------------------------------------------------------
dbg_pass;
handler:
R4 = SEQSTAT; // Get exception cause
// read and check fail addr (addr_which_causes_exception)
// should not be set for alignment exception
RD_MMR(DCPLB_FAULT_ADDR, p0, r5);
RD_MMR(DCPLB_STATUS, p0, r6);
R7 = RETX; // get address of excepting instruction
RETX = P2;
RTX;
|
stsp/binutils-ia16
| 5,916
|
sim/testsuite/bfin/c_ldst_ld_d_p_h.s
|
//Original:/testcases/core/c_ldst_ld_d_p_h/c_ldst_ld_d_p_h.dsp
// Spec Reference: c_ldst ld d [p] h
# mach: bfin
.include "testutils.inc"
start
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
// load 16 bits from memory and zero extend into 32-bit reg
R0 = W [ P1 ] (Z);
R1 = W [ P2 ] (Z);
.ifndef BFIN_HOST
R2 = W [ P3 ] (Z);
.else
R2 = 0x4243(Z);
.endif
R3 = W [ P4 ] (Z);
R4 = W [ P5 ] (Z);
R5 = W [ P5 ] (Z);
R6 = W [ FP ] (Z);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00002223;
CHECKREG r2, 0x00004243;
CHECKREG r3, 0x00006263;
CHECKREG r4, 0x00008283;
CHECKREG r5, 0x00008283;
CHECKREG r6, 0x00000203;
R1 = W [ P2 ] (Z);
.ifndef BFIN_HOST
R2 = W [ P3 ] (Z);
.else
R2 = 0x4243 (Z);
.endif
R3 = W [ P4 ] (Z);
R4 = W [ P5 ] (Z);
R5 = W [ FP ] (Z);
R7 = W [ P1 ] (Z);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00002223;
CHECKREG r2, 0x00004243;
CHECKREG r3, 0x00006263;
CHECKREG r4, 0x00008283;
CHECKREG r5, 0x00000203;
CHECKREG r7, 0x00000203;
.ifndef BFIN_HOST
R2 = W [ P3 ] (Z);
.else
R2 = 0x4243 (Z);
.endif
R3 = W [ P4 ] (Z);
R4 = W [ P5 ] (Z);
R5 = W [ FP ] (Z);
R7 = W [ P1 ] (Z);
R0 = W [ P2 ] (Z);
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00002223;
CHECKREG r2, 0x00004243;
CHECKREG r3, 0x00006263;
CHECKREG r4, 0x00008283;
CHECKREG r5, 0x00000203;
CHECKREG r7, 0x00000203;
R3 = W [ P4 ] (Z);
R4 = W [ P5 ] (Z);
R5 = W [ FP ] (Z);
R7 = W [ P1 ] (Z);
R0 = W [ P2 ] (Z);
.ifndef BFIN_HOST
R1 = W [ P3 ] (Z);
.else
R1 = 0x4243 (Z);
.endif
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00004243;
CHECKREG r2, 0x00004243;
CHECKREG r3, 0x00006263;
CHECKREG r4, 0x00008283;
CHECKREG r5, 0x00000203;
CHECKREG r7, 0x00000203;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 4,503
|
sim/testsuite/bfin/c_dsp32mult_dr_m.s
|
//Original:/testcases/core/c_dsp32mult_dr_m/c_dsp32mult_dr_m.dsp
// Spec Reference: dsp32mult single dr (mix) MUNOP
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm32 r7, 0xd246712f;
R4.L = R0.L * R0.L;
R5.L = R0.L * R1.H;
R6.L = R1.H * R0.L;
R7.L = R1.H * R1.H;
R0.L = R0.L * R0.L;
R1.L = R0.L * R1.H;
R2.L = R1.H * R0.L;
R3.L = R1.H * R1.H;
CHECKREG r0, 0x342339FA;
CHECKREG r1, 0x9F7AD448;
CHECKREG r2, 0xA328D448;
CHECKREG r3, 0x000648CA;
CHECKREG r4, 0xB0AB39FA;
CHECKREG r5, 0x10ACBF0A;
CHECKREG r6, 0xC00CBF0A;
CHECKREG r7, 0xD24648CA;
imm32 r0, 0x5b23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x90060037;
imm32 r4, 0x80abcd39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c003d;
imm32 r7, 0x12467003;
R4.L = R2.H * R2.L;
R5.L = R2.H * R3.H;
R6.L = R3.L * R2.L;
R7.L = R3.L * R3.H;
R0.L = R2.H * R2.L;
R1.L = R2.H * R3.H;
R2.L = R3.L * R2.L;
R3.L = R3.L * R3.H;
CHECKREG r0, 0x5B23F51D;
CHECKREG r1, 0x6FBAEF41;
CHECKREG r2, 0x1324FFE1;
CHECKREG r3, 0x9006FFD0;
CHECKREG r4, 0x80ABF51D;
CHECKREG r5, 0xB0ACEF41;
CHECKREG r6, 0xA00CFFE1;
CHECKREG r7, 0x1246FFD0;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x43246755;
imm32 r3, 0x05060055;
imm32 r4, 0x906bc509;
imm32 r5, 0x10a7ef5b;
imm32 r6, 0xb00c805d;
imm32 r7, 0x1246795f;
R0.L = R4.L * R4.L;
R1.L = R4.L * R5.H;
R2.L = R5.H * R4.L;
R3.L = R5.H * R5.H;
R4.L = R4.L * R4.L;
R5.L = R4.L * R5.H;
R6.L = R5.H * R4.L;
R7.L = R5.H * R5.H;
CHECKREG r0, 0x1B231B2A;
CHECKREG r1, 0xC4BAF854;
CHECKREG r2, 0x4324F854;
CHECKREG r3, 0x0506022B;
CHECKREG r4, 0x906B1B2A;
CHECKREG r5, 0x10A70389;
CHECKREG r6, 0xB00C0389;
CHECKREG r7, 0x1246022B;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cb06d;
imm32 r7, 0x1246706f;
// test the unsigned U=1
R0.L = R6.L * R6.L;
R1.L = R6.L * R7.H;
R2.L = R7.H * R6.L;
R3.L = R7.H * R7.H;
R4.L = R6.L * R6.L;
R5.L = R6.L * R7.H;
R6.L = R7.H * R6.L;
R7.L = R7.H * R7.H;
CHECKREG r0, 0xBB233178;
CHECKREG r1, 0xEFBAF4A4;
CHECKREG r2, 0x1324F4A4;
CHECKREG r3, 0xF006029C;
CHECKREG r4, 0x90AB3178;
CHECKREG r5, 0x10ACF4A4;
CHECKREG r6, 0x800CF4A4;
CHECKREG r7, 0x1246029C;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R0.L = R0.H * R7.L;
R1.L = R1.H * R6.H;
R2.L = R2.L * R5.L;
R3.L = R3.H * R4.H;
R4.L = R4.L * R3.H;
R5.L = R5.H * R2.L;
R6.L = R6.L * R1.L;
R7.L = R7.H * R0.L;
CHECKREG r0, 0xAB230A92;
CHECKREG r1, 0xCFBAFFFB;
CHECKREG r2, 0x1324E621;
CHECKREG r3, 0x0006FFFB;
CHECKREG r4, 0x90ABFFFE;
CHECKREG r5, 0x10ACFCA1;
CHECKREG r6, 0x000C0000;
CHECKREG r7, 0x12460182;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246905;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R0.H = R7.H * R0.H;
R1.H = R6.H * R1.H;
R2.H = R5.H * R2.L;
R3.H = R4.H * R3.H;
R4.H = R3.L * R4.H;
R5.H = R2.H * R5.L;
R6.H = R1.H * R6.H;
R7.H = R0.L * R7.H;
CHECKREG r0, 0xF3E35A75;
CHECKREG r1, 0xFFFB5127;
CHECKREG r2, 0x0DAE6905;
CHECKREG r3, 0xFFFB0007;
CHECKREG r4, 0xFFFACD09;
CHECKREG r5, 0xFDA2E9DB;
CHECKREG r6, 0x00000D0D;
CHECKREG r7, 0x0CEA700F;
imm32 r0, 0x9b235675;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946705;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c009d;
imm32 r7, 0x12467009;
R2.H = R0.L * R6.L;
R3.H = R1.H * R7.L;
R0.H = R2.L * R0.L;
R1.H = R3.L * R1.H;
R4.H = R4.H * R2.H;
R5.H = R5.L * R3.H;
R6.H = R6.H * R4.L;
R7.H = R7.L * R5.H;
CHECKREG r0, 0x45965675;
CHECKREG r1, 0xFFFD5127;
CHECKREG r2, 0x006A6705;
CHECKREG r3, 0xD07F0007;
CHECKREG r4, 0xFFA49D09;
CHECKREG r5, 0x0838E9DB;
CHECKREG r6, 0xFFF7009D;
CHECKREG r7, 0x07327009;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R4.H = R5.L * R2.L;
R6.H = R6.H * R3.H;
R0.H = R7.H * R4.L;
R1.H = R0.H * R5.L;
R2.H = R1.H * R6.H;
R5.H = R2.H * R7.L;
R3.H = R3.H * R0.L;
R7.H = R4.L * R1.H;
CHECKREG r0, 0xFD4B5675;
CHECKREG r1, 0x005D5127;
CHECKREG r2, 0x00006705;
CHECKREG r3, 0x00090007;
CHECKREG r4, 0xF234ED09;
CHECKREG r5, 0x0000EEDB;
CHECKREG r6, 0x000000ED;
CHECKREG r7, 0xFFF2700E;
pass
|
stsp/binutils-ia16
| 2,252
|
sim/testsuite/bfin/c_regmv_acc_acc.s
|
//Original:/testcases/core/c_regmv_acc_acc/c_regmv_acc_acc.dsp
// Spec Reference: regmv acc-acc
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa9627911;
imm32 r1, 0xd0158978;
imm32 r2, 0xc1234567;
imm32 r3, 0x10060007;
imm32 r4, 0x02080009;
imm32 r5, 0x003a000b;
imm32 r6, 0x0004000d;
imm32 r7, 0x000e500f;
A0 = R0;
A1 = A0;
R2 = A1.w;
R3 = A1.x;
A1.x = A0.w;
A1.w = A0.w;
A0.x = A0.w;
A0.w = A0.w;
R4 = A0.w;
R5 = A0.x;
R6 = A1.w;
R7 = A1.x;
CHECKREG r0, 0xA9627911;
CHECKREG r1, 0xD0158978;
CHECKREG r2, 0xA9627911;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xA9627911;
CHECKREG r5, 0x00000011;
CHECKREG r6, 0xA9627911;
CHECKREG r7, 0x00000011;
imm32 r0, 0x90ba7911;
imm32 r1, 0xe3458978;
imm32 r2, 0xc1234567;
imm32 r3, 0x10060007;
imm32 r4, 0x56080009;
imm32 r5, 0x783a000b;
imm32 r6, 0xf247890d;
imm32 r7, 0x489e534f;
A1 = R0;
A0 = A1;
R2 = A0.w;
R3 = A0.x;
A0.x = A1.w;
A0.w = A1.w;
A1.x = A1.w;
A1.w = A1.w;
R4 = A0.w;
R5 = A0.x;
R6 = A1.w;
R7 = A1.x;
CHECKREG r0, 0x90BA7911;
CHECKREG r1, 0xE3458978;
CHECKREG r2, 0x90BA7911;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0x90BA7911;
CHECKREG r5, 0x00000011;
CHECKREG r6, 0x90BA7911;
CHECKREG r7, 0x00000011;
imm32 r0, 0xf9627911;
imm32 r1, 0xd0158978;
imm32 r2, 0xc1234567;
imm32 r3, 0x10060007;
imm32 r4, 0x02080009;
imm32 r5, 0x003a000b;
imm32 r6, 0xf247890d;
imm32 r7, 0x789e534f;
A0 = R0;
A0.x = A0.x;
A0.w = A0.x;
A1.w = A0.x;
A1.x = A0.x;
R4 = A0.w;
R5 = A0.x;
R6 = A1.w;
R7 = A1.x;
CHECKREG r0, 0xF9627911;
CHECKREG r1, 0xD0158978;
CHECKREG r2, 0xC1234567;
CHECKREG r3, 0x10060007;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x90ba7911;
imm32 r1, 0xe3458978;
imm32 r2, 0xc1234567;
imm32 r3, 0x10060007;
imm32 r4, 0x56080009;
imm32 r5, 0x783a000b;
imm32 r6, 0xf247890d;
imm32 r7, 0x489e534f;
A1 = R0;
A0.x = A1.x;
A0.w = A1.x;
A1.w = A1.x;
A1.x = A1.x;
R4 = A0.w;
R5 = A0.x;
R6 = A1.w;
R7 = A1.x;
CHECKREG r0, 0x90BA7911;
CHECKREG r1, 0xE3458978;
CHECKREG r2, 0xC1234567;
CHECKREG r3, 0x10060007;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
pass
|
stsp/binutils-ia16
| 5,517
|
sim/testsuite/bfin/c_interr_excpt.S
|
//Original:/proj/frio/dv/testcases/core/c_interr_excpt/c_interr_excpt.dsp
// Spec Reference: interr excpt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC;
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
// Raise 1 requires some intelligence so the test
// doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
R0 = 1;
R1 = 2;
R2 = 3;
R3 = 4;
EXCPT 1; // RTX
EXCPT 2; // RTX
EXCPT 3; // RTX
EXCPT 4; // RTX
EXCPT 5; // RTX
EXCPT 5; // RTX
EXCPT 6; // RTX
EXCPT 7; // RTX
EXCPT 8; // RTX
EXCPT 9; // RTX
EXCPT 10; // RTX
EXCPT 11; // RTX
EXCPT 12; // RTX
EXCPT 13; // RTX
EXCPT 14; // RTX
EXCPT 15; // RTX
CHECKREG(r0, 0x33333333);
CHECKREG(r1, 0xCCCCCCCD);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x33333333);
CHECKREG(r4, 0x00000000);
CHECKREG(r5, 0x00000000);
CHECKREG(r6, 0x00000000);
CHECKREG(r7, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = 2;
RTN;
XHANDLE: // Exception Handler 3
R0 = R1 + R2;
R1 = R2 + R3;
R2 = R0 + R1;
R3 = R0 + R2;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = 5;
RTI;
THANDLE: // Timer Handler 6
R3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
//.data 0xF0000000
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 2,911
|
sim/testsuite/bfin/c_dsp32mac_dr_a0_s.s
|
//Original:/testcases/core/c_dsp32mac_dr_a0_s/c_dsp32mac_dr_a0_s.dsp
// Spec Reference: dsp32mac dr a0 s (scale by 2.0 signed fraction with round)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x83545abd;
imm32 r1, 0x98bcfec7;
imm32 r2, 0xc9948679;
imm32 r3, 0xd0999007;
imm32 r4, 0xefb99569;
imm32 r5, 0xcd35900b;
imm32 r6, 0xe00c89ad;
imm32 r7, 0xf78e909a;
A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (S2RND);
R1 = A0.w;
A1 = R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (S2RND);
R3 = A0.w;
A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (S2RND);
R5 = A0.w;
A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (S2RND);
R7 = A0.w;
CHECKREG r0, 0x8354FE44;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0xC9945F37;
CHECKREG r3, 0x2F9B8618;
CHECKREG r4, 0xEFB96C22;
CHECKREG r5, 0x361112B2;
CHECKREG r6, 0xE00C7BBF;
CHECKREG r7, 0x3DDFA49E;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0xc8548abd;
imm32 r1, 0x7bccfec7;
imm32 r2, 0xa1bc5679;
imm32 r3, 0xb00bc007;
imm32 r4, 0xcfbcb8c9;
imm32 r5, 0x5235cb8c;
imm32 r6, 0xe50ca0b8;
imm32 r7, 0x675e700b;
R0.L = ( A0 = R1.L * R0.L ) (S2RND);
R1 = A0.w;
R2.L = ( A0 += R2.L * R3.H ) (S2RND);
R3 = A0.w;
R4.L = ( A0 -= R4.H * R5.L ) (S2RND);
R5 = A0.w;
R6.L = ( A0 = R6.H * R7.H ) (S2RND);
R7 = A0.w;
CHECKREG r0, 0xC854023D;
CHECKREG r1, 0x011EBDD6;
CHECKREG r2, 0xA1BC9635;
CHECKREG r3, 0xCB1A8C3C;
CHECKREG r4, 0xCFBC8000;
CHECKREG r5, 0xB7532E9C;
CHECKREG r6, 0xE50CD478;
CHECKREG r7, 0xEA3BDCD0;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x7b54babd;
imm32 r1, 0xbabcdec7;
imm32 r2, 0xabbbe679;
imm32 r3, 0x8abdb007;
imm32 r4, 0x9fab7b69;
imm32 r5, 0xa23a87bb;
imm32 r6, 0xb00ca88b;
imm32 r7, 0xc78eaab8;
R0.L = ( A0 = R1.L * R0.L ) (S2RND);
R1 = A0.w;
R2.L = ( A0 -= R2.H * R3.L ) (S2RND);
R3 = A0.w;
R4.L = ( A0 = R4.H * R5.H ) (S2RND);
R5 = A0.w;
R6.L = ( A0 += R6.L * R7.H ) (S2RND);
R7 = A0.w;
CHECKREG r0, 0x7B5423F4;
CHECKREG r1, 0x11FA1DD6;
CHECKREG r2, 0xABBBBAA7;
CHECKREG r3, 0xDD53999C;
CHECKREG r4, 0x9FAB7FFF;
CHECKREG r5, 0x4692C57C;
CHECKREG r6, 0xB00C7FFF;
CHECKREG r7, 0x6D23D9B0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xfa545abd;
imm32 r1, 0x5ffcfec7;
imm32 r2, 0xc1ef5679;
imm32 r3, 0x9c0ef007;
imm32 r4, 0xafccec69;
imm32 r5, 0xd23c9e1b;
imm32 r6, 0xc00cc0e2;
imm32 r7, 0x678edc0e;
A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (S2RND);
R3 = A0.w;
A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (S2RND);
R7 = A0.w;
A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (S2RND);
R5 = A0.w;
A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (S2RND);
R1 = A0.w;
CHECKREG r0, 0xFA54CF65;
CHECKREG r1, 0xE7B2ACD4;
CHECKREG r2, 0xC1EF7FFF;
CHECKREG r3, 0x6C45F786;
CHECKREG r4, 0xAFCCCEDE;
CHECKREG r5, 0xE76F2094;
CHECKREG r6, 0xC00C0838;
CHECKREG r7, 0x041C3834;
pass
|
stsp/binutils-ia16
| 13,554
|
sim/testsuite/bfin/c_ldstidxl_st_dreg.s
|
//Original:testcases/core/c_ldstidxl_st_dreg/c_ldstidxl_st_dreg.dsp
// Spec Reference: c_ldstidxl store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0xc8;
loadsym i1, DATA_ADDR_1, 0x10;
loadsym p4, DATA_ADDR_2, 0xc8;
loadsym p5, DATA_ADDR_1, 0x00;
loadsym fp, DATA_ADDR_2, 0xc8;
loadsym i3, DATA_ADDR_1, 0x00;
P3 = I1; SP = I3;
[ P1 + 0x1004 ] = R0;
[ P1 + 0x1008 ] = R1;
[ P1 + 0x1010 ] = R2;
[ P1 + 0x1014 ] = R3;
[ P2 + -0x1020 ] = R4;
[ P2 + -0x1024 ] = R5;
[ P2 + -0x1028 ] = R6;
[ P2 + -0x1030 ] = R7;
R6 = [ P1 + 0x1004 ];
R5 = [ P1 + 0x1008 ];
R4 = [ P1 + 0x1010 ];
R3 = [ P1 + 0x1014 ];
R2 = [ P2 + -0x1020 ];
R7 = [ P2 + -0x1024 ];
R0 = [ P2 + -0x1028 ];
R1 = [ P2 + -0x1030 ];
CHECKREG r0, 0x7019B0A6;
CHECKREG r1, 0xD028C0A7;
CHECKREG r2, 0x501B90A4;
CHECKREG r3, 0x402C80A3;
CHECKREG r4, 0x300370A2;
CHECKREG r5, 0x204E60A1;
CHECKREG r6, 0x105F50A0;
CHECKREG r7, 0x600AA0A5;
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
[ P3 + 0x1034 ] = R0;
[ P3 + 0x1040 ] = R1;
[ P3 + 0x1044 ] = R2;
[ P3 + 0x1048 ] = R3;
[ P4 + -0x1050 ] = R4;
[ P4 + -0x1054 ] = R5;
[ P4 + -0x1060 ] = R6;
[ P4 + -0x1064 ] = R7;
R3 = [ P3 + 0x1034 ];
R4 = [ P3 + 0x1040 ];
R0 = [ P3 + 0x1044 ];
R1 = [ P3 + 0x1048 ];
R2 = [ P4 + -0x1050 ];
R5 = [ P4 + -0x1054 ];
R6 = [ P4 + -0x1060 ];
R7 = [ P4 + -0x1064 ];
CHECKREG r0, 0x30BD70B2;
CHECKREG r1, 0x40BC80B3;
CHECKREG r2, 0x55BB90B4;
CHECKREG r3, 0x10BF50B0;
CHECKREG r4, 0x20BE60B1;
CHECKREG r5, 0x60BAA0B5;
CHECKREG r6, 0x70B9B0B6;
CHECKREG r7, 0x80B8C0B7;
// initial values
imm32 r0, 0x10cf50c0;
imm32 r1, 0x20ce60c1;
imm32 r2, 0x30c370c2;
imm32 r3, 0x40cc80c3;
imm32 r4, 0x50cb90c4;
imm32 r5, 0x60caa0c5;
imm32 r6, 0x70c9b0c6;
imm32 r7, 0xd0c8c0c7;
[ P5 + 1004 ] = R0;
[ P5 + 1008 ] = R1;
[ P5 + 1012 ] = R2;
[ P5 + 1016 ] = R3;
[ SP + -0x1020 ] = R4;
[ SP + -0x1024 ] = R5;
[ SP + -0x1028 ] = R6;
[ SP + -0x1030 ] = R7;
R6 = [ P5 + 1004 ];
R4 = [ P5 + 1008 ];
R5 = [ P5 + 1012 ];
R3 = [ P5 + 1016 ];
R2 = [ SP + -0x1020 ];
R0 = [ SP + -0x1024 ];
R7 = [ SP + -0x1028 ];
R1 = [ SP + -0x1030 ];
CHECKREG r0, 0x60CAA0C5;
CHECKREG r1, 0xD0C8C0C7;
CHECKREG r2, 0x50CB90C4;
CHECKREG r3, 0x40CC80C3;
CHECKREG r4, 0x20CE60C1;
CHECKREG r5, 0x30C370C2;
CHECKREG r6, 0x10CF50C0;
// initial values
imm32 r0, 0x60df50d0;
imm32 r1, 0x70de60d1;
imm32 r2, 0x80dd70d2;
imm32 r3, 0x90dc80d3;
imm32 r4, 0xa0db90d4;
imm32 r5, 0xb0daa0d5;
imm32 r6, 0xc0d9b0d6;
imm32 r7, 0xd0d8c0d7;
[ FP + 0x1034 ] = R0;
[ FP + 0x1040 ] = R1;
[ FP + 0x1044 ] = R2;
[ FP + 0x1048 ] = R3;
[ FP + 0x1050 ] = R4;
[ FP + 0x1054 ] = R5;
[ FP + 0x1060 ] = R6;
[ FP + 0x1064 ] = R7;
R3 = [ FP + 0x1034 ];
R4 = [ FP + 0x1040 ];
R0 = [ FP + 0x1044 ];
R1 = [ FP + 0x1048 ];
R2 = [ FP + 0x1050 ];
R5 = [ FP + 0x1054 ];
R6 = [ FP + 0x1060 ];
R7 = [ FP + 0x1064 ];
CHECKREG r0, 0x80DD70D2;
CHECKREG r1, 0x90DC80D3;
CHECKREG r2, 0xA0DB90D4;
CHECKREG r3, 0x60DF50D0;
CHECKREG r4, 0x70DE60D1;
CHECKREG r5, 0xB0DAA0D5;
CHECKREG r6, 0xC0D9B0D6;
CHECKREG r7, 0xD0D8C0D7;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
// Make sure there is space between the text section, and the data section
.space (0x2000);
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_2:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xa263646a
.dd 0xa667686a
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
// Make sure there is space for us to scribble
.space (0x2000);
|
stsp/binutils-ia16
| 2,738
|
sim/testsuite/bfin/c_dspldst_ld_dr_i.s
|
//Original:/testcases/core/c_dspldst_ld_dr_i/c_dspldst_ld_dr_i.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: c_dspldst ld_dr_i
// set all regs
INIT_R_REGS 0;
// initial values
loadsym I0, DATA1
loadsym I1, DATA2
loadsym I2, DATA3
loadsym I3, DATA4
R0 = [ I0 ];
R1 = [ I1 ];
R2 = [ I2 ];
R3 = [ I3 ];
R4 = [ I0 ];
R5 = [ I1 ];
R6 = [ I2 ];
R7 = [ I3 ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x20212223;
CHECKREG r2, 0x40414243;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x00010203;
CHECKREG r5, 0x20212223;
CHECKREG r6, 0x40414243;
CHECKREG r7, 0x60616263;
R1 = [ I0 ];
R2 = [ I1 ];
R3 = [ I2 ];
R4 = [ I3 ];
R5 = [ I0 ];
R6 = [ I1 ];
R7 = [ I2 ];
R0 = [ I3 ];
CHECKREG r0, 0x60616263;
CHECKREG r1, 0x00010203;
CHECKREG r2, 0x20212223;
CHECKREG r3, 0x40414243;
CHECKREG r4, 0x60616263;
CHECKREG r5, 0x00010203;
CHECKREG r6, 0x20212223;
CHECKREG r7, 0x40414243;
R2 = [ I0 ];
R3 = [ I1 ];
R4 = [ I2 ];
R5 = [ I3 ];
R6 = [ I0 ];
R7 = [ I1 ];
R0 = [ I2 ];
R1 = [ I3 ];
CHECKREG r0, 0x40414243;
CHECKREG r1, 0x60616263;
CHECKREG r2, 0x00010203;
CHECKREG r3, 0x20212223;
CHECKREG r4, 0x40414243;
CHECKREG r5, 0x60616263;
CHECKREG r6, 0x00010203;
CHECKREG r7, 0x20212223;
R3 = [ I0 ];
R4 = [ I1 ];
R5 = [ I2 ];
R6 = [ I3 ];
R7 = [ I0 ];
R0 = [ I1 ];
R1 = [ I2 ];
R2 = [ I3 ];
CHECKREG r0, 0x20212223;
CHECKREG r1, 0x40414243;
CHECKREG r2, 0x60616263;
CHECKREG r3, 0x00010203;
CHECKREG r4, 0x20212223;
CHECKREG r5, 0x40414243;
CHECKREG r6, 0x60616263;
CHECKREG r7, 0x00010203;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 6,219
|
sim/testsuite/bfin/se_bug_ui3.S
|
//Original:/proj/frio/dv/testcases/seq/se_bug_ui3/se_bug_ui3.dsp
// Description: 32 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// count of UI's will be in r5, which was initialized to 0 by header
.dw 0xC0E0 ;
.dw 0x2000 ;
.dw 0xC140 ;
.dw 0x2000 ;
.dw 0xC1A0 ;
.dw 0x2000 ;
.dw 0xC1C0 ;
.dw 0x2000 ;
.dw 0xC1E0 ;
.dw 0x2000 ;
.dw 0xC0E4 ;
.dw 0x0 ;
.dw 0xC144 ;
.dw 0x0 ;
.dw 0xC1A4 ;
.dw 0x0 ;
.dw 0xC1C4 ;
.dw 0x0 ;
.dw 0xC1E4 ;
.dw 0x0 ;
.dw 0xC0E4 ;
.dw 0x2000 ;
.dw 0xC144 ;
.dw 0x2000 ;
.dw 0xC1A4 ;
.dw 0x2000 ;
.dw 0xC1C4 ;
.dw 0x2000 ;
.dw 0xC1E4 ;
.dw 0x2000 ;
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
// Xhandler counts all EXCAUSE = 0x21;
CHECKREG(r5, 15); // count of all 16 bit UI's.
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
// 32 bit illegal opcode handler - skips bad instruction
// handler MADE LEAN and destructive so test runs more quckly
// se_undefinedinstruction1.dsp tests using a "nice" handler
// [--sp] = ASTAT; // save what we damage
// [--sp] = (r7 - r6);
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction
CC = r7 == r6;
IF !CC JUMP OUT; // If EXCAUSE != 0x21 then leave
UNDEFINEDINSTRUCTION:
R7 = RETX; // Fix up return address
R7 += 4; // skip offending 32 bit instruction
RETX = r7; // and put back in RETX
R5 += 1; // Increment global counter
OUT:
// (r7 - r6) = [sp++];
// ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 13,476
|
sim/testsuite/bfin/c_regmv_imlb_imlb.s
|
//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_imlb/c_regmv_imlb_imlb.dsp
// Spec Reference: regmv imlb-imlb
# mach: bfin
.include "testutils.inc"
start
// initialize source regs
imm32 i0, 0x11111111;
imm32 i1, 0x22222222;
imm32 i2, 0x33333333;
imm32 i3, 0x44444444;
imm32 m0, 0x55555555;
imm32 m1, 0x66666666;
imm32 m2, 0x77777777;
imm32 m3, 0x88888888;
imm32 l0, 0x99999999;
imm32 l1, 0xAAAAAAAA;
imm32 l2, 0xBBBBBBBB;
imm32 l3, 0xCCCCCCCC;
imm32 b0, 0xDDDDDDDD;
imm32 b1, 0xEEEEEEEE;
imm32 b2, 0xFFFFFFFF;
imm32 b3, 0x12345667;
//*******************i-i & m-m, i-m & m-i, l-l & b-b, l-b & b-l
// i to i & m to m
I0 = I0;
I1 = I1;
I2 = I2;
I3 = I3;
M0 = M0;
M1 = M1;
M2 = M2;
M3 = M3;
I0 = I1;
I1 = I2;
I2 = I3;
I3 = I0;
M0 = M1;
M1 = M2;
M2 = M3;
M3 = M0;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x22222222;
CHECKREG r1, 0x33333333;
CHECKREG r2, 0x44444444;
CHECKREG r3, 0x22222222;
CHECKREG r4, 0x66666666;
CHECKREG r5, 0x77777777;
CHECKREG r6, 0x88888888;
CHECKREG r7, 0x66666666;
I0 = I2;
I1 = I3;
I2 = I0;
I3 = I1;
M0 = M2;
M1 = M3;
M2 = M0;
M3 = M1;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x44444444;
CHECKREG r1, 0x22222222;
CHECKREG r2, 0x44444444;
CHECKREG r3, 0x22222222;
CHECKREG r4, 0x88888888;
CHECKREG r5, 0x66666666;
CHECKREG r6, 0x88888888;
CHECKREG r7, 0x66666666;
I0 = I3;
I1 = I0;
I2 = I1;
I3 = I2;
M0 = M3;
M1 = M0;
M2 = M1;
M3 = M2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x22222222;
CHECKREG r1, 0x22222222;
CHECKREG r2, 0x22222222;
CHECKREG r3, 0x22222222;
CHECKREG r4, 0x66666666;
CHECKREG r5, 0x66666666;
CHECKREG r6, 0x66666666;
CHECKREG r7, 0x66666666;
imm32 i0, 0xa1111110;
imm32 i1, 0xb2222220;
imm32 i2, 0xc3333330;
imm32 i3, 0xd4444440;
imm32 m0, 0xe5555550;
imm32 m1, 0xf6666660;
imm32 m2, 0x17777770;
imm32 m3, 0x28888888;
// m to i & i to m
I0 = M0;
I1 = M1;
I2 = M2;
I3 = M3;
M0 = I0;
M1 = I1;
M2 = I2;
M3 = I3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0xE5555550;
CHECKREG r1, 0xF6666660;
CHECKREG r2, 0x17777770;
CHECKREG r3, 0x28888888;
CHECKREG r4, 0xE5555550;
CHECKREG r5, 0xF6666660;
CHECKREG r6, 0x17777770;
CHECKREG r7, 0x28888888;
I0 = M1;
I1 = M2;
I2 = M3;
I3 = M0;
M0 = I1;
M1 = I2;
M2 = I3;
M3 = I0;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0xF6666660;
CHECKREG r1, 0x17777770;
CHECKREG r2, 0x28888888;
CHECKREG r3, 0xE5555550;
CHECKREG r4, 0x17777770;
CHECKREG r5, 0x28888888;
CHECKREG r6, 0xE5555550;
CHECKREG r7, 0xF6666660;
I0 = M2;
I1 = M3;
I2 = M0;
I3 = M1;
M0 = I2;
M1 = I3;
M2 = I0;
M3 = I1;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0xE5555550;
CHECKREG r1, 0xF6666660;
CHECKREG r2, 0x17777770;
CHECKREG r3, 0x28888888;
CHECKREG r4, 0x17777770;
CHECKREG r5, 0x28888888;
CHECKREG r6, 0xE5555550;
CHECKREG r7, 0xF6666660;
I0 = M3;
I1 = M0;
I2 = M1;
I3 = M2;
M0 = I3;
M1 = I0;
M2 = I1;
M3 = I2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0xF6666660;
CHECKREG r1, 0x17777770;
CHECKREG r2, 0x28888888;
CHECKREG r3, 0xE5555550;
CHECKREG r4, 0xE5555550;
CHECKREG r5, 0xF6666660;
CHECKREG r6, 0x17777770;
CHECKREG r7, 0x28888888;
// l to l & b to b
L0 = L0;
L1 = L1;
L2 = L2;
L3 = L3;
B0 = B0;
B1 = B1;
B2 = B2;
B3 = B3;
L0 = L1;
L1 = L2;
L2 = L3;
L3 = L0;
B0 = B1;
B1 = B2;
B2 = B3;
B3 = B0;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0xAAAAAAAA;
CHECKREG r1, 0xBBBBBBBB;
CHECKREG r2, 0xCCCCCCCC;
CHECKREG r3, 0xAAAAAAAA;
CHECKREG r4, 0xEEEEEEEE;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x12345667;
CHECKREG r7, 0xEEEEEEEE;
L0 = L2;
L1 = L3;
L2 = L0;
L3 = L1;
B0 = B2;
B1 = B3;
B2 = B0;
B3 = B1;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0xCCCCCCCC;
CHECKREG r1, 0xAAAAAAAA;
CHECKREG r2, 0xCCCCCCCC;
CHECKREG r3, 0xAAAAAAAA;
CHECKREG r4, 0x12345667;
CHECKREG r5, 0xEEEEEEEE;
CHECKREG r6, 0x12345667;
CHECKREG r7, 0xEEEEEEEE;
imm32 l0, 0x09499091;
imm32 l1, 0x0A55A0A2;
imm32 l2, 0x0B6BB0B3;
imm32 l3, 0x0C7CC0C4;
imm32 b0, 0x0D8DD0D5;
imm32 b1, 0x0E9EE0E6;
imm32 b2, 0x0F0FF0F7;
imm32 b3, 0x12145068;
L0 = L3;
L1 = L0;
L2 = L1;
L3 = L2;
B0 = B3;
B1 = B0;
B2 = B1;
B3 = B2;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x0C7CC0C4;
CHECKREG r1, 0x0C7CC0C4;
CHECKREG r2, 0x0C7CC0C4;
CHECKREG r3, 0x0C7CC0C4;
CHECKREG r4, 0x12145068;
CHECKREG r5, 0x12145068;
CHECKREG r6, 0x12145068;
CHECKREG r7, 0x12145068;
// b to l & l to b
L0 = B0;
L1 = B1;
L2 = B2;
L3 = B3;
B0 = L0;
B1 = L1;
B2 = L2;
B3 = L3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0xF6666660;
CHECKREG r1, 0x17777770;
CHECKREG r2, 0x28888888;
CHECKREG r3, 0xE5555550;
CHECKREG r4, 0xE5555550;
CHECKREG r5, 0xF6666660;
CHECKREG r6, 0x17777770;
CHECKREG r7, 0x28888888;
imm32 l0, 0x01909910;
imm32 l1, 0x12A11220;
imm32 l2, 0x23B25530;
imm32 l3, 0x34C36640;
imm32 b0, 0x45D47750;
imm32 b1, 0x56E58860;
imm32 b2, 0x67F66676;
imm32 b3, 0x78375680;
L0 = B1;
L1 = B2;
L2 = B3;
L3 = B0;
B0 = L1;
B1 = L2;
B2 = L3;
B3 = L0;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x56E58860;
CHECKREG r1, 0x67F66676;
CHECKREG r2, 0x78375680;
CHECKREG r3, 0x45D47750;
CHECKREG r4, 0x67F66676;
CHECKREG r5, 0x78375680;
CHECKREG r6, 0x45D47750;
CHECKREG r7, 0x56E58860;
imm32 l0, 0x09909990;
imm32 l1, 0x1AA11230;
imm32 l2, 0x2BB25550;
imm32 l3, 0x3CC36660;
imm32 b0, 0x4DD47770;
imm32 b1, 0x5EE58880;
imm32 b2, 0x6FF66666;
imm32 b3, 0x72375660;
L0 = B2;
L1 = B3;
L2 = B0;
L3 = B1;
B0 = L2;
B1 = L3;
B2 = L0;
B3 = L1;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x6FF66666;
CHECKREG r1, 0x72375660;
CHECKREG r2, 0x4DD47770;
CHECKREG r3, 0x5EE58880;
CHECKREG r4, 0x4DD47770;
CHECKREG r5, 0x5EE58880;
CHECKREG r6, 0x6FF66666;
CHECKREG r7, 0x72375660;
L0 = B3;
L1 = B0;
L2 = B1;
L3 = B2;
B0 = L3;
B1 = L0;
B2 = L1;
B3 = L2;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x72375660;
CHECKREG r1, 0x4DD47770;
CHECKREG r2, 0x5EE58880;
CHECKREG r3, 0x6FF66666;
CHECKREG r4, 0x6FF66666;
CHECKREG r5, 0x72375660;
CHECKREG r6, 0x4DD47770;
CHECKREG r7, 0x5EE58880;
imm32 l0, 0x09999990;
imm32 l1, 0x1AAAAAA0;
imm32 l2, 0x2BBBBBB0;
imm32 l3, 0x3CCCCCC0;
imm32 b0, 0x4DDDDDD0;
imm32 b1, 0x5EEEEEE0;
imm32 b2, 0x6FFFFFF0;
imm32 b3, 0x72345660;
//*******************l-i & l-m, b-i & b-m, i-l & i-b, m-l & m-b
// l to i & l to m
I0 = L0;
I1 = L1;
I2 = L2;
I3 = L3;
M0 = L0;
M1 = L1;
M2 = L2;
M3 = L3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x09999990;
CHECKREG r1, 0x1AAAAAA0;
CHECKREG r2, 0x2BBBBBB0;
CHECKREG r3, 0x3CCCCCC0;
CHECKREG r4, 0x09999990;
CHECKREG r5, 0x1AAAAAA0;
CHECKREG r6, 0x2BBBBBB0;
CHECKREG r7, 0x3CCCCCC0;
I0 = L1;
I1 = L2;
I2 = L3;
I3 = L0;
M0 = L1;
M1 = L2;
M2 = L3;
M3 = L0;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x1AAAAAA0;
CHECKREG r1, 0x2BBBBBB0;
CHECKREG r2, 0x3CCCCCC0;
CHECKREG r3, 0x09999990;
CHECKREG r4, 0x1AAAAAA0;
CHECKREG r5, 0x2BBBBBB0;
CHECKREG r6, 0x3CCCCCC0;
CHECKREG r7, 0x09999990;
I0 = L2;
I1 = L3;
I2 = L0;
I3 = L1;
M0 = L2;
M1 = L3;
M2 = L0;
M3 = L1;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x1AAAAAA0;
CHECKREG r1, 0x2BBBBBB0;
CHECKREG r2, 0x3CCCCCC0;
CHECKREG r3, 0x09999990;
CHECKREG r4, 0x2BBBBBB0;
CHECKREG r5, 0x3CCCCCC0;
CHECKREG r6, 0x09999990;
CHECKREG r7, 0x1AAAAAA0;
I0 = L3;
I1 = L0;
I2 = L1;
I3 = L2;
M0 = L3;
M1 = L0;
M2 = L1;
M3 = L2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x3CCCCCC0;
CHECKREG r1, 0x09999990;
CHECKREG r2, 0x1AAAAAA0;
CHECKREG r3, 0x2BBBBBB0;
CHECKREG r4, 0x3CCCCCC0;
CHECKREG r5, 0x09999990;
CHECKREG r6, 0x1AAAAAA0;
CHECKREG r7, 0x2BBBBBB0;
// b to i & b to m
I0 = B0;
I1 = B1;
I2 = B2;
I3 = B3;
M0 = B0;
M1 = B1;
M2 = B2;
M3 = B3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x4DDDDDD0;
CHECKREG r1, 0x5EEEEEE0;
CHECKREG r2, 0x6FFFFFF0;
CHECKREG r3, 0x72345660;
CHECKREG r4, 0x4DDDDDD0;
CHECKREG r5, 0x5EEEEEE0;
CHECKREG r6, 0x6FFFFFF0;
CHECKREG r7, 0x72345660;
I0 = B1;
I1 = B2;
I2 = B3;
I3 = B0;
M0 = B1;
M1 = B2;
M2 = B3;
M3 = B0;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x5EEEEEE0;
CHECKREG r1, 0x6FFFFFF0;
CHECKREG r2, 0x72345660;
CHECKREG r3, 0x4DDDDDD0;
CHECKREG r4, 0x5EEEEEE0;
CHECKREG r5, 0x6FFFFFF0;
CHECKREG r6, 0x72345660;
CHECKREG r7, 0x4DDDDDD0;
I0 = B2;
I1 = B3;
I2 = B0;
I3 = B1;
M0 = B2;
M1 = B3;
M2 = B0;
M3 = B1;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x6FFFFFF0;
CHECKREG r1, 0x72345660;
CHECKREG r2, 0x4DDDDDD0;
CHECKREG r3, 0x5EEEEEE0;
CHECKREG r4, 0x6FFFFFF0;
CHECKREG r5, 0x72345660;
CHECKREG r6, 0x4DDDDDD0;
CHECKREG r7, 0x5EEEEEE0;
I0 = B3;
I1 = B0;
I2 = B1;
I3 = B2;
M0 = B3;
M1 = B0;
M2 = B1;
M3 = B2;
P1 = I1;
P2 = I2;
P3 = I3;
P4 = M0;
P5 = M1;
FP = M2;
SP = M3;
CHECKREG p1, 0x4DDDDDD0;
CHECKREG p2, 0x5EEEEEE0;
CHECKREG p3, 0x6FFFFFF0;
CHECKREG p4, 0x72345660;
CHECKREG p5, 0x4DDDDDD0;
CHECKREG fp, 0x5EEEEEE0;
CHECKREG sp, 0x6FFFFFF0;
// i to l & i to b
imm32 i0, 0x09999990;
imm32 i1, 0x1AAAAAA0;
imm32 i2, 0x2BBBBBB0;
imm32 i3, 0x3CCCCCC0;
L0 = I0;
L1 = I1;
L2 = I2;
L3 = I3;
B0 = I0;
B1 = I1;
B2 = I2;
B3 = I3;
L0 = I1;
L1 = I2;
L2 = I3;
L3 = I0;
B0 = I1;
B1 = I2;
B2 = I3;
B3 = I0;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x1AAAAAA0;
CHECKREG r1, 0x2BBBBBB0;
CHECKREG r2, 0x3CCCCCC0;
CHECKREG r3, 0x09999990;
CHECKREG r4, 0x1AAAAAA0;
CHECKREG r5, 0x2BBBBBB0;
CHECKREG r6, 0x3CCCCCC0;
CHECKREG r7, 0x09999990;
L0 = I2;
L1 = I3;
L2 = I0;
L3 = I1;
B0 = I2;
B1 = I3;
B2 = I0;
B3 = I1;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x2BBBBBB0;
CHECKREG r1, 0x3CCCCCC0;
CHECKREG r2, 0x09999990;
CHECKREG r3, 0x1AAAAAA0;
CHECKREG r4, 0x2BBBBBB0;
CHECKREG r5, 0x3CCCCCC0;
CHECKREG r6, 0x09999990;
CHECKREG r7, 0x1AAAAAA0;
imm32 l0, 0x09499091;
imm32 l1, 0x0A55A0A2;
imm32 l2, 0x0B6BB0B3;
imm32 l3, 0x0C7CC0C4;
imm32 b0, 0x0D8DD0D5;
imm32 b1, 0x0E9EE0E6;
imm32 b2, 0x0F0FF0F7;
imm32 b3, 0x12145068;
L0 = I3;
L1 = I0;
L2 = I1;
L3 = I2;
B0 = I3;
B1 = I0;
B2 = I1;
B3 = I2;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x3CCCCCC0;
CHECKREG r1, 0x09999990;
CHECKREG r2, 0x1AAAAAA0;
CHECKREG r3, 0x2BBBBBB0;
CHECKREG r4, 0x3CCCCCC0;
CHECKREG r5, 0x09999990;
CHECKREG r6, 0x1AAAAAA0;
CHECKREG r7, 0x2BBBBBB0;
// m to l & m to b
imm32 m0, 0x4DDDDDD0;
imm32 m1, 0x5EEEEEE0;
imm32 m2, 0x6FFFFFF0;
imm32 m3, 0x72345660;
L0 = M0;
L1 = M1;
L2 = M2;
L3 = M3;
B0 = M0;
B1 = M1;
B2 = M2;
B3 = M3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x09999990;
CHECKREG r1, 0x1AAAAAA0;
CHECKREG r2, 0x2BBBBBB0;
CHECKREG r3, 0x3CCCCCC0;
CHECKREG r4, 0x4DDDDDD0;
CHECKREG r5, 0x5EEEEEE0;
CHECKREG r6, 0x6FFFFFF0;
CHECKREG r7, 0x72345660;
imm32 l0, 0x01909910;
imm32 l1, 0x12A11220;
imm32 l2, 0x23B25530;
imm32 l3, 0x34C36640;
imm32 b0, 0x45D47750;
imm32 b1, 0x56E58860;
imm32 b2, 0x67F66676;
imm32 b3, 0x78375680;
L0 = M1;
L1 = M2;
L2 = M3;
L3 = M0;
B0 = M1;
B1 = M2;
B2 = M3;
B3 = M0;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x5EEEEEE0;
CHECKREG r1, 0x6FFFFFF0;
CHECKREG r2, 0x72345660;
CHECKREG r3, 0x4DDDDDD0;
CHECKREG r4, 0x5EEEEEE0;
CHECKREG r5, 0x6FFFFFF0;
CHECKREG r6, 0x72345660;
CHECKREG r7, 0x4DDDDDD0;
imm32 l0, 0x09909990;
imm32 l1, 0x1AA11230;
imm32 l2, 0x2BB25550;
imm32 l3, 0x3CC36660;
imm32 b0, 0x4DD47770;
imm32 b1, 0x5EE58880;
imm32 b2, 0x6FF66666;
imm32 b3, 0x72375660;
L0 = M2;
L1 = M3;
L2 = M0;
L3 = M1;
B0 = M2;
B1 = M3;
B2 = M0;
B3 = M1;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x6FFFFFF0;
CHECKREG r1, 0x72345660;
CHECKREG r2, 0x4DDDDDD0;
CHECKREG r3, 0x5EEEEEE0;
CHECKREG r4, 0x6FFFFFF0;
CHECKREG r5, 0x72345660;
CHECKREG r6, 0x4DDDDDD0;
CHECKREG r7, 0x5EEEEEE0;
L0 = M3;
L1 = M0;
L2 = M1;
L3 = M2;
B0 = M3;
B1 = M0;
B2 = M1;
B3 = M2;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x72345660;
CHECKREG r1, 0x4DDDDDD0;
CHECKREG r2, 0x5EEEEEE0;
CHECKREG r3, 0x6FFFFFF0;
CHECKREG r4, 0x72345660;
CHECKREG r5, 0x4DDDDDD0;
CHECKREG r6, 0x5EEEEEE0;
CHECKREG r7, 0x6FFFFFF0;
pass
|
stsp/binutils-ia16
| 13,726
|
sim/testsuite/bfin/se_loop_mv2lc.S
|
//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc/se_loop_mv2lc.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x3 (Z);
// Loop 0
LD32_LABEL(r0, L0T);
LD32_LABEL(r1, L0B);
LT0 = r0;
LB0 = r1;
LC0 = P0;
NOP;
JUMP.S 2;
JUMP.S 6;
NOP;
LC0 = P0;
LC0 = P1;
L0T:R2 += 3;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
L0B:R7 += 8;
// Loop 1
LD32_LABEL(r0, L1T);
LD32_LABEL(r1, L1B);
LT1 = r0;
LB1 = r1;
LC1 = P0;
NOP;
JUMP.S 2;
JUMP.S 6;
NOP;
LC1 = P0;
LC1 = P1;
L1T:R2 += 3;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
L1B:R7 += 8;
// Loop 0
LSETUP ( L2T , L2T ) LC0 = P0;
NOP;
NOP;
NOP;
LC0 = P1;
L2T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
L2B:R7 += 6;
LC0 = P1;
NOP;
NOP;
NOP;
LSETUP ( L3T , L3T ) LC0 = P0;
L3T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
L3B:R7 += 6;
LSETUP ( L4T , L4B ) LC0 = P0;
NOP;
NOP;
LC0 = P1;
L4T:R2 += 1;
L4B:R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC0 = P1;
NOP;
NOP;
LSETUP ( L5T , L5B ) LC0 = P0;
L5T:R2 += 1;
L5B:R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( L6T , L6B ) LC0 = P0;
NOP;
LC0 = P1;
L6T:R2 += 1;
R3 += 2;
L6B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC0 = P1;
NOP;
LSETUP ( L7T , L7B ) LC0 = P0;
L7T:R2 += 1;
R3 += 2;
L7B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( L8T , L8B ) LC0 = P0;
LC0 = P1;
L8T:R2 += 1;
R3 += 2;
R4 += 3;
L8B:R5 += 4;
R6 += 5;
R7 += 6;
LC0 = P1;
LSETUP ( L9T , L9B ) LC0 = P0;
L9T:R2 += 1;
R3 += 2;
R4 += 3;
L9B:R5 += 4;
R6 += 5;
R7 += 6;
// Loop 1
LSETUP ( M2T , M2T ) LC1 = P0;
NOP;
NOP;
NOP;
LC1 = P1;
M2T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
M2B:R7 += 6;
LC1 = P1;
NOP;
NOP;
NOP;
LSETUP ( M3T , M3T ) LC1 = P0;
M3T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
M3B:R7 += 6;
LSETUP ( M4T , M4B ) LC1 = P0;
NOP;
NOP;
LC1 = P1;
M4T:R2 += 1;
M4B:R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC1 = P1;
NOP;
NOP;
LSETUP ( M5T , M5B ) LC1 = P0;
M5T:R2 += 1;
M5B:R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( M6T , M6B ) LC1 = P0;
NOP;
LC1 = P1;
M6T:R2 += 1;
R3 += 2;
M6B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC1 = P1;
NOP;
LSETUP ( M7T , M7B ) LC1 = P0;
M7T:R2 += 1;
R3 += 2;
M7B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( M8T , M8B ) LC1 = P0;
LC1 = P1;
M8T:R2 += 1;
R3 += 2;
R4 += 3;
M8B:R5 += 4;
R6 += 5;
R7 += 6;
LC1 = P1;
LSETUP ( M9T , M9B ) LC1 = P0;
M9T:R2 += 1;
R3 += 2;
R4 += 3;
M9B:R5 += 4;
R6 += 5;
R7 += 6;
// Loop 0
LSETUP ( N2T , N2B ) LC0 = P0 >> 1;
NOP;
NOP;
NOP;
LC0 = P1;
N2T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
N2B:R7 += 6;
LC0 = P1;
NOP;
NOP;
NOP;
LSETUP ( N3T , N3B ) LC0 = P0 >> 1;
N3T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
N3B:R7 += 6;
LSETUP ( N4T , N4B ) LC0 = P0 >> 1;
NOP;
NOP;
LC0 = P1;
N4T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
N4B:R6 += 5;
R7 += 6;
LC0 = P1;
NOP;
NOP;
LSETUP ( N5T , N5B ) LC0 = P0 >> 1;
N5T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
N5B:R6 += 5;
R7 += 6;
LSETUP ( N6T , N6B ) LC0 = P0 >> 1;
NOP;
LC0 = P1;
N6T:R2 += 1;
R3 += 2;
R4 += 3;
N6B:R5 += 4;
R6 += 5;
R7 += 6;
LC0 = P1;
NOP;
LSETUP ( N7T , N7B ) LC0 = P0 >> 1;
N7T:R2 += 1;
R3 += 2;
R4 += 3;
N7B:R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( N8T , N8T ) LC0 = P0 >> 1;
LC0 = P1;
N8T:R2 += 1;
R3 += 2;
N8B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC0 = P1;
LSETUP ( N9T , N9T ) LC0 = P0 >> 1;
N9T:R2 += 1;
R3 += 2;
N9B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
// Loop 1
LSETUP ( O2T , O2B ) LC1 = P0 >> 1;
NOP;
NOP;
NOP;
LC1 = P1;
O2T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
O2B:R7 += 6;
LC1 = P1;
NOP;
NOP;
NOP;
LSETUP ( O3T , O3B ) LC1 = P0 >> 1;
O3T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
O3B:R7 += 6;
LSETUP ( O4T , O4B ) LC1 = P0 >> 1;
NOP;
NOP;
LC1 = P1;
O4T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
O4B:R6 += 5;
R7 += 6;
LC1 = P1;
NOP;
NOP;
LSETUP ( O5T , O5B ) LC1 = P0 >> 1;
O5T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
O5B:R6 += 5;
R7 += 6;
LSETUP ( O6T , O6B ) LC1 = P0 >> 1;
NOP;
LC1 = P1;
O6T:R2 += 1;
R3 += 2;
R4 += 3;
O6B:R5 += 4;
R6 += 5;
R7 += 6;
LC1 = P1;
NOP;
LSETUP ( O7T , O7B ) LC1 = P0 >> 1;
O7T:R2 += 1;
R3 += 2;
R4 += 3;
O7B:R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( O8T , O8T ) LC1 = P0 >> 1;
LC1 = P1;
O8T:R2 += 1;
R3 += 2;
O8B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC1 = P1;
LSETUP ( O9T , O9T ) LC1 = P0 >> 1;
O9T:R2 += 1;
R3 += 2;
O9B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 6,235
|
sim/testsuite/bfin/se_bug_ui2.S
|
//Original:/proj/frio/dv/testcases/seq/se_bug_ui2/se_bug_ui2.dsp
// Description: 16 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// count of UI's will be in r5, which was initialized to 0 by header
// .dw 0x41FD ;
// .dw 0x41FE ;
// .dw 0x41FF ;
.dw 0x9040 ;
.dw 0x9049 ;
.dw 0x9052 ;
.dw 0x905B ;
.dw 0x9064 ;
.dw 0x906D ;
.dw 0x9076 ;
.dw 0x907F ;
.dw 0x90C0 ;
.dw 0x90C9 ;
.dw 0x90D2 ;
.dw 0x90DB ;
.dw 0x90E4 ;
.dw 0x90ED ;
.dw 0x90F6 ;
.dw 0x90FF ;
.dw 0x9180 ;
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
// Xhandler counts all EXCAUSE = 0x21;
CHECKREG(r5, 17); // count of all 16 bit UI's.
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
// 16 bit illegal opcode handler - skips bad instruction
// handler MADE LEAN and destructive so test runs more quckly
// se_undefinedinstruction1.dsp tests using a "nice" handler
// [--sp] = ASTAT; // save what we damage
// [--sp] = (r7 - r6);
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction
CC = r7 == r6;
IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave
R6 = 0x22; // Also accept illegal insn combo
CC = r7 == r6;
IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave
dbg_fail;
UNDEFINEDINSTRUCTION:
R7 = RETX; // Fix up return address
R7 += 2; // skip offending 16 bit instruction
RETX = r7; // and put back in RETX
R5 += 1; // Increment global counter
OUT:
// (r7 - r6) = [sp++];
// ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 6,169
|
sim/testsuite/bfin/c_ldst_ld_d_p_pp_xb.s
|
//Original:testcases/core/c_ldst_ld_d_p_pp_xb/c_ldst_ld_d_p_pp_xb.dsp
// Spec Reference: c_ldst ld d [p++] xb
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x04;
loadsym p1, DATA_ADDR_2, 0x04;
loadsym p2, DATA_ADDR_3, 0x04;
loadsym i1, DATA_ADDR_4, 0x04;
loadsym p4, DATA_ADDR_5, 0x04;
loadsym fp, DATA_ADDR_6, 0x04;
loadsym i3, DATA_ADDR_7, 0x04;
P3 = I1; SP = I3;
R4 = B [ P5 ++ ] (X);
R5 = B [ P1 ++ ] (X);
R6 = B [ P2 ++ ] (X);
R7 = B [ P3 ++ ] (X);
R0 = B [ P4 ++ ] (X);
R1 = B [ FP ++ ] (X);
R2 = B [ SP ++ ] (X);
CHECKREG r0, 0xFFFFFF87;
CHECKREG r1, 0x00000007;
CHECKREG r2, 0xFFFFFF87;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000027;
CHECKREG r6, 0x00000047;
CHECKREG r7, 0x00000067;
R5 = B [ P5 ++ ] (X);
R6 = B [ P1 ++ ] (X);
R7 = B [ P2 ++ ] (X);
R0 = B [ P3 ++ ] (X);
R1 = B [ P4 ++ ] (X);
R2 = B [ FP ++ ] (X);
R3 = B [ SP ++ ] (X);
CHECKREG r0, 0x00000066;
CHECKREG r1, 0xFFFFFF86;
CHECKREG r2, 0x00000006;
CHECKREG r3, 0xFFFFFF86;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000006;
CHECKREG r6, 0x00000026;
CHECKREG r7, 0x00000046;
R6 = B [ P5 ++ ] (X);
R7 = B [ P1 ++ ] (X);
R0 = B [ P2 ++ ] (X);
R1 = B [ P3 ++ ] (X);
R2 = B [ P4 ++ ] (X);
R3 = B [ FP ++ ] (X);
R4 = B [ SP ++ ] (X);
CHECKREG r0, 0x00000045;
CHECKREG r1, 0x00000065;
CHECKREG r2, 0xFFFFFF85;
CHECKREG r3, 0x00000005;
CHECKREG r4, 0xFFFFFF85;
CHECKREG r5, 0x00000006;
CHECKREG r6, 0x00000005;
CHECKREG r7, 0x00000025;
R7 = B [ P5 ++ ] (X);
R0 = B [ P1 ++ ] (X);
R1 = B [ P2 ++ ] (X);
R2 = B [ P3 ++ ] (X);
R3 = B [ P4 ++ ] (X);
R4 = B [ FP ++ ] (X);
R5 = B [ SP ++ ] (X);
CHECKREG r0, 0x00000024;
CHECKREG r1, 0x00000044;
CHECKREG r2, 0x00000064;
CHECKREG r3, 0xFFFFFF84;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0xFFFFFF84;
CHECKREG r6, 0x00000005;
CHECKREG r7, 0x00000004;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 5,922
|
sim/testsuite/bfin/c_ldst_ld_d_p_b.s
|
//Original:/testcases/core/c_ldst_ld_d_p_b/c_ldst_ld_d_p_b.dsp
// Spec Reference: c_ldst ld d [p] b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
// load 8 bits from memory, and zero extend into 32-bit reg
R0 = B [ P1 ] (Z);
R1 = B [ P2 ] (Z);
.ifndef BFIN_HOST
R2 = B [ P3 ] (Z);
.else
R2 = 0x43 (Z);
.endif
R3 = B [ P4 ] (Z);
R4 = B [ P5 ] (Z);
R5 = B [ P5 ] (Z);
R6 = B [ FP ] (Z);
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00000023;
CHECKREG r2, 0x00000043;
CHECKREG r3, 0x00000063;
CHECKREG r4, 0x00000083;
CHECKREG r5, 0x00000083;
CHECKREG r6, 0x00000003;
R1 = B [ P2 ] (Z);
.ifndef BFIN_HOST
R2 = B [ P3 ] (Z);
.else
R2 = 0x43 (Z);
.endif
R3 = B [ P4 ] (Z);
R4 = B [ P5 ] (Z);
R5 = B [ FP ] (Z);
R7 = B [ P1 ] (Z);
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00000023;
CHECKREG r2, 0x00000043;
CHECKREG r3, 0x00000063;
CHECKREG r4, 0x00000083;
CHECKREG r5, 0x00000003;
CHECKREG r7, 0x00000003;
.ifndef BFIN_HOST
R2 = B [ P3 ] (Z);
.else
R2 = 0x43 (Z);
.endif
R3 = B [ P4 ] (Z);
R4 = B [ P5 ] (Z);
R5 = B [ FP ] (Z);
R7 = B [ P1 ] (Z);
R0 = B [ P2 ] (Z);
CHECKREG r0, 0x00000023;
CHECKREG r1, 0x00000023;
CHECKREG r2, 0x00000043;
CHECKREG r3, 0x00000063;
CHECKREG r4, 0x00000083;
CHECKREG r5, 0x00000003;
CHECKREG r7, 0x00000003;
R3 = B [ P4 ] (Z);
R4 = B [ P5 ] (Z);
R5 = B [ FP ] (Z);
R7 = B [ P1 ] (Z);
R0 = B [ P2 ] (Z);
.ifndef BFIN_HOST
R1 = B [ P3 ] (Z);
.else
R1 = 0x43;
.endif
CHECKREG r0, 0x00000023;
CHECKREG r1, 0x00000043;
CHECKREG r2, 0x00000043;
CHECKREG r3, 0x00000063;
CHECKREG r4, 0x00000083;
CHECKREG r5, 0x00000003;
CHECKREG r7, 0x00000003;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 7,285
|
sim/testsuite/bfin/c_seq_ex1_raise_call_mv_pop.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_call_mv_pop/c_seq_ex1_raise_call_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (raise+ call + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
LD32_LABEL(p1, SUBR1);
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
[ -- SP ] = ( R7:0 );
RAISE 2; // RTN
CALL (p1);
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
RAISE 6; // RTI
CALL SUBR2;
P1 = R3;
R4 = P1;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000012);
CHECKREG(r2, 0x00000023);
CHECKREG(r3, 0x00000024);
CHECKREG(r4, 0x00000024);
CHECKREG(r5, 0x00000026);
CHECKREG(r6, 0x00000027);
CHECKREG(r7, 0x00000028);
RAISE 8; // RTI
CALL SUBR3;
P3 = R5;
R6 = P3;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000012);
CHECKREG(r2, 0x00000013);
CHECKREG(r3, 0x00000013);
CHECKREG(r4, 0x00000015);
CHECKREG(r5, 0x00000016);
CHECKREG(r6, 0x00000017);
CHECKREG(r7, 0x00000018);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
RAISE 9; // RTI
P4 = R6;
R7 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000008);
CHECKREG(r1, 0x00000004);
CHECKREG(r2, 0x00000004);
CHECKREG(r3, 0x00000002);
END:
dbg_pass; // End the test
SUBR1: // should jump here
I0 += 2;
RTS;
I3 += 2; // should not go here
RTS;
SUBR2: // should jump here
I1 += 2;
RTS;
I3 += 2; // should not go here
RTS;
SUBR3: // should jump here
I2 += 2;
RTS;
I3 += 2; // should not go here
RTS;
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 5,561
|
sim/testsuite/bfin/dbg_tr_simplejp.S
|
//Original:/proj/frio/dv/testcases/debug/dbg_tr_simplejp/dbg_tr_simplejp.dsp
// Description: This test performs simple jumps and verifies the trace buffer
// recording for simple jumps.
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfcheck.inc)
include(symtable.inc)
#ifndef ITABLE
#define ITABLE CODE_ADDR_1 //
#endif
// This test embeds .text offsets, so pad our test so it lines up.
.space 0x5e
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
CHECK_INIT_DEF(p5); // CHECK_INIT(p5, 0x00BFFFFC);
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
LD32_LABEL(r7, DUMMY);
RETI = r7;
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
START :
WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer
// TBUFPWR = 1
// TBUFEN = 1
// TBUFOVF = 0
// CMPLP = 0
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label1; // 0x0224
R4.L = 0x1111; // Will be killed
R4.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
label2: R5.H = 0x7777; // 0x0234
R5.L = 0x7888;
JUMP.S label3; //0x023c
R6.L = 0x1111; // Will be killed
R6.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
NOP;
label1: R4.H = 0x5555; // 0x0250
R4.L = 0x6666;
NOP;
JUMP.S label2; // 0x0258
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
label3: R6.H = 0x7999; //0x026c
R6.L = 0x7aaa;
NOP;
NOP;
NOP;
NOP;
WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn OFF trace Buffer
NOP;
NOP;
NOP;
NOP;
NOP;
// Read the contents of the Trace Buffer
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000003);
// Read 3rd Entry of the Trace Buffer
RD_MMR(TBUF, p0, r0);
CHECKREG(r0, 0x0000026c);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000003);
RD_MMR(TBUF, p0, r1);
CHECKREG(r1, 0x0000023c);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000002);
// Read 2nd Entry of the Trace Buffer
RD_MMR(TBUF, p0, r0);
CHECKREG(r0, 0x00000234);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000002);
RD_MMR(TBUF, p0, r1);
CHECKREG(r1, 0x0000025a);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000001);
// Read ist Entry of the Trace Buffer
RD_MMR(TBUF, p0, r0);
CHECKREG(r0, 0x00000250);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000001);
RD_MMR(TBUF, p0, r1);
CHECKREG(r1, 0x00000224);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000000);
WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn OFF trace Buffer Power
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
|
stsp/binutils-ia16
| 5,619
|
sim/testsuite/bfin/c_dspldst_st_dr_ipp.s
|
//Original:testcases/core/c_dspldst_st_dr_ipp/c_dspldst_st_dr_ipp.dsp
// Spec Reference: c_dspldst st_dr_ipp
# mach: bfin
.include "testutils.inc"
start
// set all regs
//INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 r7, 0x719abc7e;
// initial values
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
[ I0 ++ ] = R0;
[ I1 ++ ] = R1;
[ I2 ++ ] = R2;
[ I3 ++ ] = R3;
[ I0 ++ ] = R1;
[ I1 ++ ] = R2;
[ I2 ++ ] = R3;
[ I3 ++ ] = R4;
[ I0 ++ ] = R3;
[ I1 ++ ] = R4;
[ I2 ++ ] = R5;
[ I3 ++ ] = R6;
[ I0 ++ ] = R4;
[ I1 ++ ] = R5;
[ I2 ++ ] = R6;
[ I3 ++ ] = R7;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 = [ I2 ++ ];
R3 = [ I3 ++ ];
R4 = [ I0 ++ ];
R5 = [ I1 ++ ];
R6 = [ I2 ++ ];
R7 = [ I3 ++ ];
CHECKREG r0, 0x0a234507;
CHECKREG r1, 0x1b345618;
CHECKREG r2, 0x2c456729;
CHECKREG r3, 0x3d56783a;
CHECKREG r4, 0x1B345618;
CHECKREG r5, 0x2C456729;
CHECKREG r6, 0x3D56783A;
CHECKREG r7, 0x4E67894B;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 = [ I2 ++ ];
R3 = [ I3 ++ ];
R4 = [ I0 ++ ];
R5 = [ I1 ++ ];
R6 = [ I2 ++ ];
R7 = [ I3 ++ ];
CHECKREG r0, 0x3D56783A;
CHECKREG r1, 0x4E67894B;
CHECKREG r2, 0x5F789A5C;
CHECKREG r3, 0x6089AB6D;
CHECKREG r4, 0x4E67894B;
CHECKREG r5, 0x5F789A5C;
CHECKREG r6, 0x6089AB6D;
CHECKREG r7, 0x719ABC7E;
// initial values
imm32 r0, 0xa0b2c3d4;
imm32 r1, 0x1b245618;
imm32 r2, 0x22b36729;
imm32 r3, 0xbd3c483a;
imm32 r4, 0xde64d54b;
imm32 r5, 0x5f785e6c;
imm32 r6, 0x30896bf7;
imm32 r7, 0x719ab770;
loadsym i0, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym i2, DATA_ADDR_5, 0x20;
loadsym i3, DATA_ADDR_6, 0x20;
[ I0 -- ] = R0;
[ I1 -- ] = R1;
[ I2 -- ] = R2;
[ I3 -- ] = R3;
[ I0 -- ] = R4;
[ I1 -- ] = R5;
[ I2 -- ] = R6;
[ I3 -- ] = R7;
loadsym i0, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym i2, DATA_ADDR_5, 0x20;
loadsym i3, DATA_ADDR_6, 0x20;
R0 = [ I0 -- ];
R1 = [ I1 -- ];
R2 = [ I2 -- ];
R3 = [ I3 -- ];
R4 = [ I0 -- ];
R5 = [ I1 -- ];
R6 = [ I2 -- ];
R7 = [ I3 -- ];
CHECKREG r0, 0xA0B2C3D4;
CHECKREG r1, 0x1B245618;
CHECKREG r2, 0x22B36729;
CHECKREG r3, 0xBD3C483A;
CHECKREG r4, 0xDE64D54B;
CHECKREG r5, 0x5F785E6C;
CHECKREG r6, 0x30896BF7;
CHECKREG r7, 0x719AB770;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 4,735
|
sim/testsuite/bfin/c_except_sys_sstep.S
|
//Original:/proj/frio/dv/testcases/core/c_except_sys_sstep/c_except_sys_sstep.dsp
// Spec Reference: Single Step Supervisor Exception Test (NO REGTRACE!)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
//
////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// CHECK_INIT(p2, 0x2000);
include(symtable.inc)
CHECK_INIT_DEF(p2);
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
R0 = 1;
SYSCFG = r0; // Enable Supervisor Single Step
R4 = 0;
LD32_LABEL(r0, START);
RETI = r0; // We need to load the return address
RTI;
START:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
R0 = 0;
R1 = 1;
R2 = 2;
R3 = 3;
R5 = 5;
R6 = 6;
R7 = 7;
EXCPT 3; // turn off single step via handler
CHECKREG(r4, 0x0b); // 11 instrs are executed before single step = disabled
CHECKREG(r0, 0x00);
CHECKREG(r1, 0x03);
CHECKREG(r2, 0x10);
CHECKREG(r3, 0x04);
CHECKREG(r5, 0x09);
CHECKREG(r6, 0x06);
CHECKREG(r7, 0x07);
// PUT YOUR TEST HERE!
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
[ -- SP ] = ASTAT; // save ASTAT
R1 = SEQSTAT;
R1 <<= 26;
R1 >>= 26; // only want EXCAUSE
R2 = 0x10; // EXCAUSE 0x10 means Single Step (exception)
CC = r1 == r2;
IF CC JUMP SSCOUNT; // Go to Single Step Handler
SYSCFG = r0; // otherwise must be an EXCPT, so turn off singlestep
R3 += 1;
JUMP.S EXIT;
SSCOUNT:
R4 += 1; // R4 counts single step events
EXIT:
ASTAT = [sp++];
R5 += 1;
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 1,071
|
sim/testsuite/bfin/c_logi2op_log_l_shft_astat.S
|
# Test ASTAT bits with logical left shift (<<=)
# mach: bfin
.include "testutils.inc"
#include "test.h"
start
.macro __do val:req, shift:req, exp:req
# First test when ASTAT starts with all bits cleared
imm32 R2, \val;
ASTAT = R0;
R2 <<= \shift;
R3 = ASTAT;
CHECKREG R2, (\val << \shift);
CHECKREG R3, \exp;
# Then test when ASTAT starts with all bits set
imm32 R2, \val;
ASTAT = R1;
R2 <<= \shift;
R3 = ASTAT;
CHECKREG R3, (\exp) | ~(_AZ|_AN|_V|_V_COPY);
.endm
.macro _do shift:req, val:req
# Automatically test all shifted values
.if ((\val << \shift) & 0xffffffff) == 0
__do \val, \shift, _AZ
.else
.if (\val << \shift) == 0x80000000
__do \val, \shift, _AN
.else
__do \val, \shift, 0
.endif
.endif
.if (\val << 1) & 0xffffffff
_do \shift, (\val << 1)
.endif
.endm
.macro do shift:req
_l_shft_\shift:
_do \shift, 1
.endm
R0 = 0;
R1 = -1;
do 0
do 1
do 2
do 3
do 4
do 5
do 6
do 7
do 8
do 9
do 10
do 11
do 12
do 13
do 14
do 15
do 16
do 17
do 18
do 19
do 20
do 21
do 22
do 23
do 24
do 25
do 26
do 27
do 28
do 29
do 30
do 31
pass
|
stsp/binutils-ia16
| 5,243
|
sim/testsuite/bfin/c_dsp32shift_expexp_r.s
|
//Original:/testcases/core/c_dsp32shift_expexp_r/c_dsp32shift_expexp_r.dsp
// Spec Reference: dsp32shift expadj / expadj r
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0800d001;
imm32 r1, 0x08000001;
imm32 r2, 0x0800d002;
imm32 r3, 0x0800d003;
imm32 r4, 0x0800d004;
imm32 r5, 0x0800d005;
imm32 r6, 0x0800d006;
imm32 r7, 0x0800d007;
R1.L = EXPADJ( R1 , R0.L ) (V);
R2.L = EXPADJ( R2 , R0.L ) (V);
R3.L = EXPADJ( R3 , R0.L ) (V);
R4.L = EXPADJ( R4 , R0.L ) (V);
R5.L = EXPADJ( R5 , R0.L ) (V);
R6.L = EXPADJ( R6 , R0.L ) (V);
R7.L = EXPADJ( R7 , R0.L ) (V);
R0.L = EXPADJ( R0 , R0.L ) (V);
CHECKREG r0, 0x0800D001;
CHECKREG r1, 0x0800D001;
CHECKREG r2, 0x0800D001;
CHECKREG r3, 0x0800D001;
CHECKREG r4, 0x0800D001;
CHECKREG r5, 0x0800D001;
CHECKREG r6, 0x0800D001;
CHECKREG r7, 0x0800D001;
imm32 r0, 0x0900d001;
imm32 r1, 0x09000001;
imm32 r2, 0x0900d002;
imm32 r3, 0x0900d003;
imm32 r4, 0x0900d004;
imm32 r5, 0x0900d005;
imm32 r6, 0x0900d006;
imm32 r7, 0x0900d007;
R0.L = EXPADJ( R0 , R1.L ) (V);
R1.L = EXPADJ( R1 , R1.L ) (V);
R2.L = EXPADJ( R2 , R1.L ) (V);
R3.L = EXPADJ( R3 , R1.L ) (V);
R4.L = EXPADJ( R4 , R1.L ) (V);
R5.L = EXPADJ( R5 , R1.L ) (V);
R6.L = EXPADJ( R6 , R1.L ) (V);
R7.L = EXPADJ( R7 , R1.L ) (V);
CHECKREG r0, 0x09000001;
CHECKREG r1, 0x09000001;
CHECKREG r2, 0x09000001;
CHECKREG r3, 0x09000001;
CHECKREG r4, 0x09000001;
CHECKREG r5, 0x09000001;
CHECKREG r6, 0x09000001;
CHECKREG r7, 0x09000001;
imm32 r0, 0x0a00e001;
imm32 r1, 0x0a00e001;
imm32 r2, 0x0a00000f;
imm32 r3, 0x0a00e003;
imm32 r4, 0x0a00e004;
imm32 r5, 0x0a00e005;
imm32 r6, 0x0a00e006;
imm32 r7, 0x0a00e007;
R0.L = EXPADJ( R0 , R2.L ) (V);
R1.L = EXPADJ( R1 , R2.L ) (V);
R3.L = EXPADJ( R3 , R2.L ) (V);
R4.L = EXPADJ( R4 , R2.L ) (V);
R5.L = EXPADJ( R5 , R2.L ) (V);
R6.L = EXPADJ( R6 , R2.L ) (V);
R7.L = EXPADJ( R7 , R2.L ) (V);
R2.L = EXPADJ( R2 , R2.L ) (V);
CHECKREG r0, 0x0A000002;
CHECKREG r1, 0x0A000002;
CHECKREG r2, 0x0A000003;
CHECKREG r3, 0x0A000002;
CHECKREG r4, 0x0A000002;
CHECKREG r5, 0x0A000002;
CHECKREG r6, 0x0A000002;
CHECKREG r7, 0x0A000002;
imm32 r0, 0x0b00f001;
imm32 r1, 0x0b00f001;
imm32 r2, 0x0b00f002;
imm32 r3, 0x0b000010;
imm32 r4, 0x0b00f004;
imm32 r5, 0x0b00f005;
imm32 r6, 0x0b00f006;
imm32 r7, 0x0b00f007;
R0.L = EXPADJ( R0 , R3.L ) (V);
R1.L = EXPADJ( R1 , R3.L ) (V);
R2.L = EXPADJ( R2 , R3.L ) (V);
R3.L = EXPADJ( R3 , R3.L ) (V);
R4.L = EXPADJ( R4 , R3.L ) (V);
R5.L = EXPADJ( R5 , R3.L ) (V);
R6.L = EXPADJ( R6 , R3.L ) (V);
R7.L = EXPADJ( R7 , R3.L ) (V);
CHECKREG r0, 0x0B000010;
CHECKREG r1, 0x0B000010;
CHECKREG r2, 0x0B000010;
CHECKREG r3, 0x0B000010;
CHECKREG r4, 0x0B000010;
CHECKREG r5, 0x0B000010;
CHECKREG r6, 0x0B000010;
CHECKREG r7, 0x0B000010;
imm32 r0, 0x0c0000c0;
imm32 r1, 0x0c0100c0;
imm32 r2, 0x0c0200c0;
imm32 r3, 0x0c0300c0;
imm32 r4, 0x0c0400c0;
imm32 r5, 0x0c0500c0;
imm32 r6, 0x0c0600c0;
imm32 r7, 0x0c0700c0;
R0.L = EXPADJ( R0 , R4.L ) (V);
R1.L = EXPADJ( R1 , R4.L ) (V);
R2.L = EXPADJ( R2 , R4.L ) (V);
R3.L = EXPADJ( R3 , R4.L ) (V);
R4.L = EXPADJ( R4 , R4.L ) (V);
R5.L = EXPADJ( R5 , R4.L ) (V);
R6.L = EXPADJ( R6 , R4.L ) (V);
R7.L = EXPADJ( R7 , R4.L ) (V);
CHECKREG r0, 0x0C0000C0;
CHECKREG r1, 0x0C0100C0;
CHECKREG r2, 0x0C0200C0;
CHECKREG r3, 0x0C0300C0;
CHECKREG r4, 0x0C0400C0;
CHECKREG r5, 0x0C0500C0;
CHECKREG r6, 0x0C0600C0;
CHECKREG r7, 0x0C0700C0;
imm32 r0, 0xa00100d0;
imm32 r1, 0x000100d1;
imm32 r2, 0xa00200d0;
imm32 r3, 0xa00300d0;
imm32 r4, 0xa00400d0;
imm32 r5, 0xa00500d0;
imm32 r6, 0xa00600d0;
imm32 r7, 0xa00700d0;
R0.L = EXPADJ( R0 , R5.L ) (V);
R1.L = EXPADJ( R1 , R5.L ) (V);
R2.L = EXPADJ( R2 , R5.L ) (V);
R3.L = EXPADJ( R3 , R5.L ) (V);
R4.L = EXPADJ( R4 , R5.L ) (V);
R5.L = EXPADJ( R5 , R5.L ) (V);
R6.L = EXPADJ( R6 , R5.L ) (V);
R7.L = EXPADJ( R7 , R5.L ) (V);
CHECKREG r0, 0xA00100D0;
CHECKREG r1, 0x000100D0;
CHECKREG r2, 0xA00200D0;
CHECKREG r3, 0xA00300D0;
CHECKREG r4, 0xA00400D0;
CHECKREG r5, 0xA00500D0;
CHECKREG r6, 0xA00600D0;
CHECKREG r7, 0xA00700D0;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060000;
imm32 r7, 0xb0070000;
R0.L = EXPADJ( R0 , R6.L ) (V);
R1.L = EXPADJ( R1 , R6.L ) (V);
R2.L = EXPADJ( R2 , R6.L ) (V);
R3.L = EXPADJ( R3 , R6.L ) (V);
R4.L = EXPADJ( R4 , R6.L ) (V);
R5.L = EXPADJ( R5 , R6.L ) (V);
R6.L = EXPADJ( R6 , R6.L ) (V);
R7.L = EXPADJ( R7 , R6.L ) (V);
CHECKREG r0, 0xB0010000;
CHECKREG r1, 0xB0010000;
CHECKREG r2, 0xB0020000;
CHECKREG r3, 0xB0030000;
CHECKREG r4, 0xB0040000;
CHECKREG r5, 0xB0050000;
CHECKREG r6, 0xB0060000;
CHECKREG r7, 0xB0070000;
imm32 r0, 0xd00102e7;
imm32 r1, 0xd00104e7;
imm32 r2, 0xd00206e7;
imm32 r3, 0xd00308e7;
imm32 r4, 0xd0040ae7;
imm32 r5, 0xd0050ce7;
imm32 r6, 0xd0060ee7;
imm32 r7, 0xd00707e7;
R0.L = EXPADJ( R0 , R7.L ) (V);
R1.L = EXPADJ( R1 , R7.L ) (V);
R2.L = EXPADJ( R2 , R7.L ) (V);
R3.L = EXPADJ( R3 , R7.L ) (V);
R4.L = EXPADJ( R4 , R7.L ) (V);
R5.L = EXPADJ( R5 , R7.L ) (V);
R6.L = EXPADJ( R6 , R7.L ) (V);
R7.L = EXPADJ( R7 , R7.L ) (V);
CHECKREG r0, 0xD0010001;
CHECKREG r1, 0xD0010001;
CHECKREG r2, 0xD0020001;
CHECKREG r3, 0xD0030001;
CHECKREG r4, 0xD0040001;
CHECKREG r5, 0xD0050001;
CHECKREG r6, 0xD0060001;
CHECKREG r7, 0xD0070001;
pass
|
stsp/binutils-ia16
| 7,367
|
sim/testsuite/bfin/c_dsp32alu_rrpmmp_sft.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft/c_dsp32alu_rrpmmp_sft.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, <<
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x35678911;
imm32 r1, 0x2489ab1d;
imm32 r2, 0x34545515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x67889b1d;
imm32 r2, 0x74445915;
imm32 r3, 0x86667797;
R0 = R0 +|- R0 , R7 = R0 -|+ R0 (ASR);
R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR);
R2 = R0 +|- R2 , R5 = R0 -|+ R2 (ASR);
R3 = R0 +|- R3 , R4 = R0 -|+ R3 (ASR);
R4 = R0 +|- R4 , R3 = R0 -|+ R4 (ASR);
R5 = R0 +|- R5 , R2 = R0 -|+ R5 (ASR);
R6 = R0 +|- R6 , R1 = R0 -|+ R6 (ASR);
R7 = R0 +|- R7 , R0 = R0 -|+ R7 (ASR);
CHECKREG r0, 0x2AB3c48D;
CHECKREG r1, 0x2F3CE6C7;
CHECKREG r2, 0x326B1645;
CHECKREG r3, 0xf6F31DE5;
CHECKREG r4, 0x5E73E21A;
CHECKREG r5, 0x22FCE9BB;
CHECKREG r6, 0x262B1939;
CHECKREG r7, 0x2AB33B72;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34e45515;
imm32 r3, 0x466e7717;
imm32 r0, 0x5567ee1b;
imm32 r1, 0x6789abed;
imm32 r2, 0x7444551e;
imm32 r3, 0x86e67777;
R0 = R1 +|- R0 , R7 = R1 -|+ R0 (ASR);
R1 = R1 +|- R1 , R6 = R1 -|+ R1 (ASR);
R2 = R1 +|- R2 , R5 = R1 -|+ R2 (ASR);
R3 = R1 +|- R3 , R4 = R1 -|+ R3 (ASR);
R4 = R1 +|- R4 , R3 = R1 -|+ R4 (ASR);
R5 = R1 +|- R5 , R2 = R1 -|+ R5 (ASR);
R6 = R1 +|- R6 , R1 = R1 -|+ R6 (ASR);
R7 = R1 +|- R7 , R0 = R1 -|+ R7 (ASR);
CHECKREG r0, 0x1559d17D;
CHECKREG r1, 0x33C4d5F6;
CHECKREG r2, 0x36F31547;
CHECKREG r3, 0xfB9C1DDD;
CHECKREG r4, 0x6BEDE222;
CHECKREG r5, 0x3095eAB8;
CHECKREG r6, 0x33C42A09;
CHECKREG r7, 0x1E6A0479;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0x86667777;
R0 = R2 +|- R0 , R7 = R2 -|+ R0 (ASR);
R1 = R2 +|- R1 , R6 = R2 -|+ R1 (ASR);
R2 = R2 +|- R2 , R5 = R2 -|+ R2 (ASR);
R3 = R2 +|- R3 , R4 = R2 -|+ R3 (ASR);
R4 = R2 +|- R4 , R3 = R2 -|+ R4 (ASR);
R5 = R2 +|- R5 , R2 = R2 -|+ R5 (ASR);
R6 = R2 +|- R6 , R1 = R2 -|+ R6 (ASR);
R7 = R2 +|- R7 , R0 = R2 -|+ R7 (ASR);
CHECKREG r0, 0x155A0CD1;
CHECKREG r1, 0x19E21551;
CHECKREG r2, 0x3A222A8A;
CHECKREG r3, 0xfEAA1DDD;
CHECKREG r4, 0x7599e222;
CHECKREG r5, 0x3A22d575;
CHECKREG r6, 0x203F1538;
CHECKREG r7, 0x24C81DB9;
imm32 r0, 0x85678911;
imm32 r1, 0x2889ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5587891b;
imm32 r1, 0x6788ab1d;
imm32 r2, 0x74448515;
imm32 r3, 0x86667877;
R0 = R3 +|- R0 , R7 = R3 -|+ R0 (ASR);
R1 = R3 +|- R1 , R6 = R3 -|+ R1 (ASR);
R2 = R3 +|- R2 , R5 = R3 -|+ R2 (ASR);
R3 = R3 +|- R3 , R4 = R3 -|+ R3 (ASR);
R4 = R3 +|- R4 , R3 = R3 -|+ R4 (ASR);
R5 = R3 +|- R5 , R2 = R3 -|+ R5 (ASR);
R6 = R3 +|- R6 , R1 = R3 -|+ R6 (ASR);
R7 = R3 +|- R7 , R0 = R3 -|+ R7 (ASR);
CHECKREG r0, 0x15621E82;
CHECKREG r1, 0x19E22702;
CHECKREG r2, 0x1D111D80;
CHECKREG r3, 0xc3333C3B;
CHECKREG r4, 0xc333c3C4;
CHECKREG r5, 0xa6221EBA;
CHECKREG r6, 0xa9511538;
CHECKREG r7, 0xaDD11DB9;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0x86667777;
R0 = R4 +|- R0 , R7 = R4 -|+ R0 (ASR);
R1 = R4 +|- R1 , R6 = R4 -|+ R1 (ASR);
R2 = R4 +|- R2 , R5 = R4 -|+ R2 (ASR);
R3 = R4 +|- R3 , R4 = R4 -|+ R3 (ASR);
R4 = R4 +|- R4 , R3 = R4 -|+ R4 (ASR);
R5 = R4 +|- R5 , R2 = R4 -|+ R5 (ASR);
R6 = R4 +|- R6 , R1 = R4 -|+ R6 (ASR);
R7 = R4 +|- R7 , R0 = R4 -|+ R7 (ASR);
CHECKREG r0, 0x33C0d337;
CHECKREG r1, 0x3848dBB8;
CHECKREG r2, 0x3B770636;
CHECKREG r3, 0x00001D9D;
CHECKREG r4, 0x1E660000;
CHECKREG r5, 0xe2EEf9CA;
CHECKREG r6, 0xe61D2448;
CHECKREG r7, 0xeAA62CC8;
imm32 r0, 0x95678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x39445515;
imm32 r3, 0x46967717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74495515;
imm32 r3, 0x86669777;
R0 = R5 +|- R0 , R7 = R5 -|+ R0 (ASR);
R1 = R5 +|- R1 , R6 = R5 -|+ R1 (ASL);
R2 = R5 +|- R2 , R5 = R5 -|+ R2 (ASR);
R3 = R5 +|- R3 , R4 = R5 -|+ R3 (ASL);
R4 = R5 +|- R4 , R3 = R5 -|+ R4 (ASR);
R5 = R5 +|- R5 , R2 = R5 -|+ R5 (ASR);
R6 = R5 +|- R6 , R1 = R5 -|+ R6 (ASR);
R7 = R5 +|- R7 , R0 = R5 -|+ R7 (ASL);
CHECKREG r0, 0xE11E82E4;
CHECKREG r1, 0xe04424E7;
CHECKREG r2, 0x0000276F;
CHECKREG r3, 0xaaBD529D;
CHECKREG r4, 0x0c95D4D1;
CHECKREG r5, 0xb7520000;
CHECKREG r6, 0xd70EdB19;
CHECKREG r7, 0xfC2A7D1C;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0x86667777;
R0 = R6 +|- R0 , R7 = R6 -|+ R0 (ASR);
R1 = R6 +|- R1 , R6 = R6 -|+ R1 (ASL);
R2 = R6 +|- R2 , R5 = R6 -|+ R2 (ASL);
R3 = R6 +|- R3 , R4 = R6 -|+ R3 (ASR);
R4 = R6 +|- R4 , R3 = R6 -|+ R4 (ASR);
R5 = R6 +|- R5 , R2 = R6 -|+ R5 (ASR);
R6 = R6 +|- R6 , R1 = R6 -|+ R6 (ASL);
R7 = R6 +|- R7 , R0 = R6 -|+ R7 (ASR);
CHECKREG r0, 0x5dAAd90D;
CHECKREG r1, 0x000031B0;
CHECKREG r2, 0x04BFe7B7;
CHECKREG r3, 0xd95C272E;
CHECKREG r4, 0x05AEe53D;
CHECKREG r5, 0xDa4B24B5;
CHECKREG r6, 0x7C280000;
CHECKREG r7, 0x1e7D26F3;
imm32 r0, 0x67898911;
imm32 r1, 0xb789ab1d;
imm32 r2, 0x3b445515;
imm32 r3, 0x46b67717;
imm32 r0, 0x5567891b;
imm32 r1, 0x678bab1d;
imm32 r2, 0x7444b515;
imm32 r3, 0x86667b77;
R0 = R7 +|- R0 , R7 = R7 -|+ R0 (ASR);
R1 = R7 +|- R1 , R6 = R7 -|+ R1 (ASR);
R2 = R7 +|- R2 , R5 = R7 -|+ R2 (ASL);
R3 = R7 +|- R3 , R4 = R7 -|+ R3 (ASR);
R4 = R7 +|- R4 , R3 = R7 -|+ R4 (ASL);
R5 = R7 +|- R5 , R2 = R7 -|+ R5 (ASL);
R6 = R7 +|- R6 , R1 = R7 -|+ R6 (ASL);
R7 = R7 +|- R7 , R0 = R7 -|+ R7 (ASR);
CHECKREG r0, 0x0000d807;
CHECKREG r1, 0x4c163332;
CHECKREG r2, 0x07FAe47E;
CHECKREG r3, 0x6aF2038C;
CHECKREG r4, 0x273A5c90;
CHECKREG r5, 0x8a327b9E;
CHECKREG r6, 0x46162cEA;
CHECKREG r7, 0xe48B0000;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34ee5515;
imm32 r3, 0x4666e717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ae1d;
imm32 r2, 0x744455e5;
imm32 r3, 0x8666777e;
R4 = R2 +|- R5 , R3 = R2 -|+ R5 (ASR);
R0 = R5 +|- R3 , R5 = R5 -|+ R3 (ASL);
R2 = R6 +|- R2 , R0 = R6 -|+ R2 (ASR);
R3 = R4 +|- R0 , R2 = R4 -|+ R0 (ASR);
R7 = R7 +|- R6 , R6 = R7 -|+ R6 (ASR);
R6 = R1 +|- R7 , R1 = R1 -|+ R7 (ASL);
R5 = R0 +|- R4 , R7 = R0 -|+ R4 (ASR);
R1 = R3 +|- R1 , R4 = R3 -|+ R1 (ASL);
CHECKREG r0, 0xE8e94167;
CHECKREG r1, 0x31084d1C;
CHECKREG r2, 0x0b291745;
CHECKREG r3, 0xF412d5de;
CHECKREG r4, 0x9f400a5C;
CHECKREG r5, 0xF4122a22;
CHECKREG r6, 0xf9B28924;
CHECKREG r7, 0xF4D71745;
imm32 r0, 0xff678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3f445515;
imm32 r3, 0x46f67717;
imm32 r0, 0x556f891b;
imm32 r1, 0x6789fb1d;
imm32 r2, 0x74445f15;
imm32 r3, 0x866677f7;
R4 = R3 +|- R3 , R5 = R3 -|+ R3 (ASR);
R1 = R6 +|- R1 , R6 = R6 -|+ R1 (ASL);
R6 = R1 +|- R4 , R4 = R1 -|+ R4 (ASR);
R7 = R4 +|- R2 , R0 = R4 -|+ R2 (ASL);
R2 = R2 +|- R6 , R1 = R2 -|+ R6 (ASR);
R3 = R5 +|- R5 , R7 = R5 -|+ R5 (ASL);
R5 = R7 +|- R7 , R3 = R7 -|+ R7 (ASR);
R0 = R0 +|- R0 , R2 = R0 -|+ R0 (ASR);
CHECKREG r0, 0x53880000;
CHECKREG r1, 0x67eb368e;
CHECKREG r2, 0x0000da38;
CHECKREG r3, 0x0000dfdc;
CHECKREG r4, 0x1e080e07;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0xa46e0e07;
CHECKREG r7, 0x0000dfdc;
pass
|
stsp/binutils-ia16
| 3,649
|
sim/testsuite/bfin/pushpopreg_1.s
|
# mach: bfin
.include "testutils.inc"
start
r0.l = 0x1111;
r0.h = 0x0011;
r1.l = 0x2222;
r1.h = 0x0022;
r2.l = 0x3333;
r2.h = 0x0033;
r3.l = 0x4444;
r3.h = 0x0044;
r4.l = 0x5555;
r4.h = 0x0055;
r5.l = 0x6666;
r5.h = 0x0066;
r6.l = 0x7777;
r6.h = 0x0077;
r7.l = 0x8888;
r7.h = 0x0088;
p1.l = 0x5a5a;
p1.h = 0x005a;
p2.l = 0x6363;
p2.h = 0x0063;
p3.l = 0x7777;
p3.h = 0x0077;
p4.l = 0x7878;
p4.h = 0x0078;
p5.l = 0x3e3e;
p5.h = 0x003e;
sp = 0x4000(x);
jump.s prog_start;
nop;
nop; // ADD reg update to roll back
nop;
prog_start:
nop;
[--sp] = r0;
[--sp] = r1;
[--sp] = r2;
[--sp] = r3;
[--sp] = r4;
[--sp] = r5;
[--sp] = r6;
[--sp] = r7;
[--sp] = p0;
[--sp] = p1;
[--sp] = p2;
[--sp] = p3;
[--sp] = p4;
[--sp] = p5;
nop;
nop;
nop;
nop;
r0.l = 0xdead;
r0.h = 0xdead;
r1.l = 0xdead;
r1.h = 0xdead;
r2.l = 0xdead;
r2.h = 0xdead;
r3.l = 0xdead;
r3.h = 0xdead;
r4.l = 0xdead;
r4.h = 0xdead;
r5.l = 0xdead;
r5.h = 0xdead;
r6.l = 0xdead;
r6.h = 0xdead;
r7.l = 0xdead;
r7.h = 0xdead;
p1.l = 0xdead;
p1.h = 0xdead;
p2.l = 0xdead;
p2.h = 0xdead;
p3.l = 0xdead;
p3.h = 0xdead;
p4.l = 0xdead;
p4.h = 0xdead;
p5.l = 0xdead;
p5.h = 0xdead;
nop;
nop;
nop;
r0 = [sp++];
r1 = [sp++];
r2 = [sp++];
r3 = [sp++];
r4 = [sp++];
r5 = [sp++];
r6 = [sp++];
r7 = [sp++];
p0 = [sp++];
p1 = [sp++];
p2 = [sp++];
p3 = [sp++];
p4 = [sp++];
p5 = [sp++];
nop;
nop;
nop;
nop;
nop;
nop;
nop;
_tp1:
nop;
nop;
nop;
nop;
nop;
nop;
nop;
[--sp] = r0;
[--sp] = r1;
[--sp] = r2;
[--sp] = r3;
[--sp] = r4;
[--sp] = r5;
[--sp] = r6;
[--sp] = r7;
[--sp] = p0;
[--sp] = p1;
[--sp] = p2;
[--sp] = p3;
[--sp] = p4;
[--sp] = p5;
nop;
nop;
nop;
nop;
r0.l = 0xdead;
r0.h = 0xdead;
r1.l = 0xdead;
r1.h = 0xdead;
r2.l = 0xdead;
r2.h = 0xdead;
r3.l = 0xdead;
r3.h = 0xdead;
r4.l = 0xdead;
r4.h = 0xdead;
r5.l = 0xdead;
r5.h = 0xdead;
r6.l = 0xdead;
r6.h = 0xdead;
r7.l = 0xdead;
r7.h = 0xdead;
p1.l = 0xdead;
p1.h = 0xdead;
p2.l = 0xdead;
p2.h = 0xdead;
p3.l = 0xdead;
p3.h = 0xdead;
p4.l = 0xdead;
p4.h = 0xdead;
p5.l = 0xdead;
p5.h = 0xdead;
nop;
nop;
nop;
r0 = [sp++];
r1 = [sp++];
r2 = [sp++];
r3 = [sp++];
r4 = [sp++];
r5 = [sp++];
r6 = [sp++];
r7 = [sp++];
p0 = [sp++];
p1 = [sp++];
a0.x = [sp++];
a1.w = r0; //preserve r0
r0 = a0.x;
DBGA(r0.l,0x0063);
a0.w = [sp++];
r0 = a0.w;
DBGA(r0.l,0x7777);
DBGA(r0.h,0x0077);
a0 = a1; //perserver r0, still
a1.x = [sp++];
r0 = a1.x;
DBGA(r0.l,0x0078);
a1.w = [sp++];
r0 = a1.w;
DBGA(r0.l,0x3e3e);
DBGA(r0.h,0x003e);
r0 = a0.w; //restore r0
nop;
nop;
nop;
nop;
nop;
nop;
nop;
_tp2:
nop;
nop;
nop;
[--sp] = r0;
[--sp] = r1;
[--sp] = r2;
[--sp] = r3;
[--sp] = a0.x;
[--sp] = a0.w;
[--sp] = a1.x;
[--sp] = a1.w;
[--sp] = p0;
[--sp] = p1;
[--sp] = p2;
[--sp] = p3;
[--sp] = p4;
[--sp] = p5;
nop;
nop;
nop;
nop;
r0.l = 0xdead;
r0.h = 0xdead;
r1.l = 0xdead;
r1.h = 0xdead;
r2.l = 0xdead;
r2.h = 0xdead;
r3.l = 0xdead;
r3.h = 0xdead;
r4.l = 0xdead;
r4.h = 0xdead;
r5.l = 0xdead;
r5.h = 0xdead;
r6.l = 0xdead;
r6.h = 0xdead;
r7.l = 0xdead;
r7.h = 0xdead;
p1.l = 0xdead;
p1.h = 0xdead;
p2.l = 0xdead;
p2.h = 0xdead;
p3.l = 0xdead;
p3.h = 0xdead;
p4.l = 0xdead;
p4.h = 0xdead;
p5.l = 0xdead;
p5.h = 0xdead;
nop;
nop;
nop;
r0 = [sp++];
r1 = [sp++];
r2 = [sp++];
r3 = [sp++];
r4 = [sp++];
r5 = [sp++];
r6 = [sp++];
r7 = [sp++];
p0 = [sp++];
p1 = [sp++];
p2 = [sp++];
p3 = [sp++];
p4 = [sp++];
p5 = [sp++];
nop;
nop;
nop;
nop;
nop;
nop;
nop;
_tp3:
nop;
nop;
nop;
nop;
nop;
_halt:
pass;
|
stsp/binutils-ia16
| 9,178
|
sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp_s.s
|
//Original:/testcases/core/c_dsp32shiftim_ahalf_lp_s/c_dsp32shiftim_ahalf_lp_s.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00100a00;
imm32 r1, 0x00100a01;
imm32 r2, 0x00100a02;
imm32 r3, 0x00100a03;
imm32 r4, 0x00100a04;
imm32 r5, 0x00100a05;
imm32 r6, 0x00100a06;
imm32 r7, 0x00100a07;
R7.L = R0.L << 0 (S);
R0.L = R1.L << 1 (S);
R1.L = R2.L << 2 (S);
R2.L = R3.L << 3 (S);
R3.L = R4.L << 4 (S);
R4.L = R5.L << 5 (S);
R5.L = R6.L << 6 (S);
R6.L = R7.L << 7 (S);
CHECKREG r1, 0x00102808;
CHECKREG r0, 0x00101402;
CHECKREG r2, 0x00105018;
CHECKREG r3, 0x00107FFF;
CHECKREG r4, 0x00107FFF;
CHECKREG r5, 0x00107FFF;
CHECKREG r6, 0x00107FFF;
CHECKREG r7, 0x00100A00;
imm32 r0, 0x00200018;
imm32 r1, 0x00200019;
imm32 r2, 0x0020001a;
imm32 r3, 0x0020001b;
imm32 r4, 0x0020001c;
imm32 r5, 0x0020001d;
imm32 r6, 0x0020001e;
imm32 r7, 0x0020001f;
R2.L = R0.L << 8 (S);
R3.L = R1.L << 9 (S);
R4.L = R2.L << 10 (S);
R5.L = R3.L << 11 (S);
R6.L = R4.L << 12 (S);
R7.L = R5.L << 13 (S);
R0.L = R6.L << 14 (S);
R1.L = R7.L << 15 (S);
CHECKREG r0, 0x00207FFF;
CHECKREG r1, 0x00207FFF;
CHECKREG r2, 0x00201800;
CHECKREG r3, 0x00203200;
CHECKREG r4, 0x00207FFF;
CHECKREG r5, 0x00207FFF;
CHECKREG r6, 0x00207FFF;
CHECKREG r7, 0x00207FFF;
imm32 r0, 0x05002001;
imm32 r1, 0x05002001;
imm32 r2, 0x0500000f;
imm32 r3, 0x05002003;
imm32 r4, 0x05002004;
imm32 r5, 0x05002005;
imm32 r6, 0x05002006;
imm32 r7, 0x05002007;
R3.L = R0.L << 0 (S);
R4.L = R1.L << 1 (S);
R5.L = R2.L << 2 (S);
R6.L = R3.L << 3 (S);
R7.L = R4.L << 4 (S);
R0.L = R5.L << 5 (S);
R1.L = R6.L << 6 (S);
R2.L = R7.L << 7 (S);
CHECKREG r0, 0x05000780;
CHECKREG r1, 0x05007FFF;
CHECKREG r2, 0x05007FFF;
CHECKREG r3, 0x05002001;
CHECKREG r4, 0x05004002;
CHECKREG r5, 0x0500003C;
CHECKREG r6, 0x05007FFF;
CHECKREG r7, 0x05007FFF;
imm32 r0, 0x03000031;
imm32 r1, 0x03000031;
imm32 r2, 0x03000032;
imm32 r3, 0x03000030;
imm32 r4, 0x03000034;
imm32 r5, 0x03000035;
imm32 r6, 0x03000036;
imm32 r7, 0x03000037;
R4.L = R0.L << 8 (S);
R5.L = R1.L << 9 (S);
R6.L = R2.L << 10 (S);
R7.L = R3.L << 11 (S);
R0.L = R4.L << 12 (S);
R1.L = R5.L << 13 (S);
R2.L = R6.L << 14 (S);
R3.L = R7.L << 15 (S);
CHECKREG r0, 0x03007FFF;
CHECKREG r1, 0x03007FFF;
CHECKREG r2, 0x03007FFF;
CHECKREG r3, 0x03007FFF;
CHECKREG r4, 0x03003100;
CHECKREG r5, 0x03006200;
CHECKREG r6, 0x03007FFF;
CHECKREG r7, 0x03007FFF;
// RHx by RLx
imm32 r0, 0x03000000;
imm32 r1, 0x03000000;
imm32 r2, 0x03000000;
imm32 r3, 0x03000000;
imm32 r4, 0x03003100;
imm32 r5, 0x03006200;
imm32 r6, 0x0300C800;
imm32 r7, 0x03008000;
R5.L = R0.H << 0 (S);
R6.L = R1.H << 1 (S);
R7.L = R2.H << 2 (S);
R0.L = R3.H << 3 (S);
R1.L = R4.H << 4 (S);
R2.L = R5.H << 5 (S);
R3.L = R6.H << 6 (S);
R4.L = R7.H << 7 (S);
CHECKREG r0, 0x03001800;
CHECKREG r1, 0x03003000;
CHECKREG r2, 0x03006000;
CHECKREG r3, 0x03007FFF;
CHECKREG r4, 0x03007FFF;
CHECKREG r5, 0x03000300;
CHECKREG r6, 0x03000600;
CHECKREG r7, 0x03000C00;
imm32 r0, 0x05018000;
imm32 r1, 0x05018001;
imm32 r2, 0x05028000;
imm32 r3, 0x05038000;
imm32 r4, 0x05048000;
imm32 r5, 0x05058000;
imm32 r6, 0x05068000;
imm32 r7, 0x05078000;
R6.L = R0.H << 8 (S);
R7.L = R1.H << 9 (S);
R0.L = R2.H << 10 (S);
R1.L = R3.H << 11 (S);
R2.L = R4.H << 12 (S);
R3.L = R5.H << 13 (S);
R4.L = R6.H << 14 (S);
R5.L = R7.H << 15 (S);
CHECKREG r0, 0x05017FFF;
CHECKREG r1, 0x05017FFF;
CHECKREG r2, 0x05027FFF;
CHECKREG r3, 0x05037FFF;
CHECKREG r4, 0x05047FFF;
CHECKREG r5, 0x05057FFF;
CHECKREG r6, 0x05067FFF;
CHECKREG r7, 0x05077FFF;
imm32 r0, 0x60019000;
imm32 r1, 0x60019000;
imm32 r2, 0x6002900f;
imm32 r3, 0x60039000;
imm32 r4, 0x60049000;
imm32 r5, 0x60059000;
imm32 r6, 0x60069000;
imm32 r7, 0x60079000;
R7.L = R0.H << 0 (S);
R0.L = R1.H << 1 (S);
R1.L = R2.H << 2 (S);
R2.L = R3.H << 3 (S);
R3.L = R4.H << 4 (S);
R4.L = R5.H << 5 (S);
R5.L = R6.H << 6 (S);
R6.L = R7.H << 7 (S);
CHECKREG r0, 0x60017FFF;
CHECKREG r1, 0x60017FFF;
CHECKREG r2, 0x60027FFF;
CHECKREG r3, 0x60037FFF;
CHECKREG r4, 0x60047FFF;
CHECKREG r5, 0x60057FFF;
CHECKREG r6, 0x60067FFF;
CHECKREG r7, 0x60076001;
imm32 r0, 0x70010001;
imm32 r1, 0x70010001;
imm32 r2, 0x70020002;
imm32 r3, 0x77030010;
imm32 r4, 0x70040004;
imm32 r5, 0x70050005;
imm32 r6, 0x70060006;
imm32 r7, 0x70070007;
R0.L = R0.H << 8 (S);
R1.L = R1.H << 9 (S);
R2.L = R2.H << 10 (S);
R3.L = R3.H << 11 (S);
R4.L = R4.H << 12 (S);
R5.L = R5.H << 13 (S);
R6.L = R6.H << 14 (S);
R7.L = R7.H << 15 (S);
CHECKREG r0, 0x70017FFF;
CHECKREG r1, 0x70017FFF;
CHECKREG r2, 0x70027FFF;
CHECKREG r3, 0x77037FFF;
CHECKREG r4, 0x70047FFF;
CHECKREG r5, 0x70057FFF;
CHECKREG r6, 0x70067FFF;
CHECKREG r7, 0x70077FFF;
// d_hi = lshft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0xa8000000;
imm32 r1, 0xa8000001;
imm32 r2, 0xa8000002;
imm32 r3, 0xa8000003;
imm32 r4, 0xa8000004;
imm32 r5, 0xa8000005;
imm32 r6, 0xa8000006;
imm32 r7, 0xa8000007;
R0.H = R0.L << 0 (S);
R1.H = R1.L << 1 (S);
R2.H = R2.L << 2 (S);
R3.H = R3.L << 3 (S);
R4.H = R4.L << 4 (S);
R5.H = R5.L << 5 (S);
R6.H = R6.L << 6 (S);
R7.H = R7.L << 7 (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x00080002;
CHECKREG r3, 0x00180003;
CHECKREG r4, 0x00400004;
CHECKREG r5, 0x00A00005;
CHECKREG r6, 0x01800006;
CHECKREG r7, 0x03800007;
imm32 r0, 0xf0090001;
imm32 r1, 0xf0090001;
imm32 r2, 0xf0090002;
imm32 r3, 0xf0090003;
imm32 r4, 0xf0090004;
imm32 r5, 0xf0090005;
imm32 r6, 0xf0000006;
imm32 r7, 0xf0000007;
R1.H = R0.L << 8 (S);
R2.H = R1.L << 9 (S);
R3.H = R2.L << 10 (S);
R4.H = R3.L << 11 (S);
R5.H = R4.L << 12 (S);
R6.H = R5.L << 13 (S);
R7.H = R6.L << 14 (S);
R0.H = R7.L << 15 (S);
CHECKREG r1, 0x01000001;
CHECKREG r2, 0x02000002;
CHECKREG r3, 0x08000003;
CHECKREG r4, 0x18000004;
CHECKREG r5, 0x40000005;
CHECKREG r6, 0x7FFF0006;
CHECKREG r7, 0x7FFF0007;
CHECKREG r0, 0x7FFF0001;
imm32 r0, 0x07000001;
imm32 r1, 0x07000001;
imm32 r2, 0x0700000f;
imm32 r3, 0x07000003;
imm32 r4, 0x07000004;
imm32 r5, 0x07000005;
imm32 r6, 0x07000006;
imm32 r7, 0x07000007;
R3.H = R0.L << 0 (S);
R4.H = R1.L << 1 (S);
R5.H = R2.L << 2 (S);
R6.H = R3.L << 3 (S);
R7.H = R4.L << 4 (S);
R0.H = R5.L << 5 (S);
R1.H = R6.L << 6 (S);
R2.H = R7.L << 7 (S);
CHECKREG r0, 0x00A00001;
CHECKREG r1, 0x01800001;
CHECKREG r2, 0x0380000F;
CHECKREG r3, 0x00010003;
CHECKREG r4, 0x00020004;
CHECKREG r5, 0x003C0005;
CHECKREG r6, 0x00180006;
CHECKREG r7, 0x00400007;
imm32 r0, 0x00000501;
imm32 r1, 0x00000501;
imm32 r2, 0x00000502;
imm32 r3, 0x00000510;
imm32 r4, 0x00000504;
imm32 r5, 0x00000505;
imm32 r6, 0x00000506;
imm32 r7, 0x00000507;
R4.H = R0.L << 8 (S);
R5.H = R1.L << 9 (S);
R6.H = R2.L << 10 (S);
R7.H = R3.L << 11 (S);
R0.H = R4.L << 12 (S);
R1.H = R5.L << 13 (S);
R2.H = R6.L << 14 (S);
R3.H = R7.L << 15 (S);
CHECKREG r0, 0x7FFF0501;
CHECKREG r1, 0x7FFF0501;
CHECKREG r2, 0x7FFF0502;
CHECKREG r3, 0x7FFF0510;
CHECKREG r4, 0x7FFF0504;
CHECKREG r5, 0x7FFF0505;
CHECKREG r6, 0x7FFF0506;
CHECKREG r7, 0x7FFF0507;
imm32 r0, 0x00a00800;
imm32 r1, 0x00a10800;
imm32 r2, 0x00a20800;
imm32 r3, 0x00a30800;
imm32 r4, 0x00a40800;
imm32 r5, 0x00a50800;
imm32 r6, 0x00a60800;
imm32 r7, 0x00a70800;
R5.H = R0.H << 0 (S);
R6.H = R1.H << 1 (S);
R7.H = R2.H << 2 (S);
R0.H = R3.H << 3 (S);
R1.H = R4.H << 4 (S);
R2.H = R5.H << 5 (S);
R3.H = R6.H << 6 (S);
R4.H = R7.H << 7 (S);
CHECKREG r0, 0x05180800;
CHECKREG r1, 0x0A400800;
CHECKREG r2, 0x14000800;
CHECKREG r3, 0x50800800;
CHECKREG r4, 0x7FFF0800;
CHECKREG r5, 0x00A00800;
CHECKREG r6, 0x01420800;
CHECKREG r7, 0x02880800;
imm32 r0, 0x0c010000;
imm32 r1, 0x0c010001;
imm32 r2, 0x0c020000;
imm32 r3, 0x0c030000;
imm32 r4, 0x0c040000;
imm32 r5, 0x0c050000;
imm32 r6, 0x0c060000;
imm32 r7, 0x0c070000;
R6.H = R0.H << 8 (S);
R7.H = R1.H << 9 (S);
R0.H = R2.H << 10 (S);
R1.H = R3.H << 11 (S);
R2.H = R4.H << 12 (S);
R3.H = R5.H << 13 (S);
R4.H = R6.H << 14 (S);
R5.H = R7.H << 15 (S);
CHECKREG r0, 0x7FFF0000;
CHECKREG r1, 0x7FFF0001;
CHECKREG r2, 0x7FFF0000;
CHECKREG r3, 0x7FFF0000;
CHECKREG r4, 0x7FFF0000;
CHECKREG r5, 0x7FFF0000;
CHECKREG r6, 0x7FFF0000;
CHECKREG r7, 0x7FFF0000;
imm32 r0, 0x00b10000;
imm32 r1, 0x00b10000;
imm32 r2, 0x00b2000f;
imm32 r3, 0x00b30000;
imm32 r4, 0x00b40000;
imm32 r5, 0x00b50000;
imm32 r6, 0x00b60000;
imm32 r7, 0x00b70000;
R7.L = R0.H << 0 (S);
R0.L = R1.H << 1 (S);
R1.L = R2.H << 2 (S);
R2.L = R3.H << 3 (S);
R3.L = R4.H << 4 (S);
R4.L = R5.H << 5 (S);
R5.L = R6.H << 6 (S);
R6.L = R7.H << 7 (S);
CHECKREG r0, 0x00B10162;
CHECKREG r1, 0x00B102C8;
CHECKREG r2, 0x00B20598;
CHECKREG r3, 0x00B30B40;
CHECKREG r4, 0x00B416A0;
CHECKREG r5, 0x00B52D80;
CHECKREG r6, 0x00B65B80;
CHECKREG r7, 0x00B700B1;
imm32 r0, 0x0a010700;
imm32 r1, 0x0a010700;
imm32 r2, 0x0a020700;
imm32 r3, 0x0a030710;
imm32 r4, 0x0a040700;
imm32 r5, 0x0a050700;
imm32 r6, 0x0a060700;
imm32 r7, 0x0a070700;
R0.H = R0.H << 8 (S);
R1.H = R1.H << 9 (S);
R2.H = R2.H << 10 (S);
R3.H = R3.H << 11 (S);
R4.H = R4.H << 12 (S);
R5.H = R5.H << 13 (S);
R6.H = R6.H << 14 (S);
R7.H = R7.H << 15 (S);
CHECKREG r0, 0x7FFF0700;
CHECKREG r1, 0x7FFF0700;
CHECKREG r2, 0x7FFF0700;
CHECKREG r3, 0x7FFF0710;
CHECKREG r4, 0x7FFF0700;
CHECKREG r5, 0x7FFF0700;
CHECKREG r6, 0x7FFF0700;
CHECKREG r7, 0x7FFF0700;
pass
|
stsp/binutils-ia16
| 2,857
|
sim/testsuite/bfin/c_dsp32mac_dr_a0.s
|
//Original:/testcases/core/c_dsp32mac_dr_a0/c_dsp32mac_dr_a0.dsp
// Spec Reference: dsp32mac dr_a0
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcaba5127;
imm32 r2, 0x13a46705;
imm32 r3, 0x000a0007;
imm32 r4, 0x90abad09;
imm32 r5, 0x10aceadb;
imm32 r6, 0x000c00ad;
imm32 r7, 0x1246700a;
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xb3545abd;
imm32 r1, 0xabbcfec7;
imm32 r2, 0xa1b45679;
imm32 r3, 0x000b0007;
imm32 r4, 0xefbcb569;
imm32 r5, 0x12350b0b;
imm32 r6, 0x000c00bd;
imm32 r7, 0x678e000b;
A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L );
R1 = A0.w;
A1 -= R2.L * R3.L, R2.L = ( A0 = R2.H * R3.L );
R3 = A0.w;
A1 = R4.L * R5.L, R4.L = ( A0 += R4.H * R5.H );
R5 = A0.w;
A1 = R6.L * R7.L, R6.L = ( A0 = R6.L * R7.H );
R7 = A0.w;
CHECKREG r0, 0xB354FF22;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0xA1B4FFFB;
CHECKREG r3, 0xFFFAD7D8;
CHECKREG r4, 0xEFBCFDAB;
CHECKREG r5, 0xFDAA8BB0;
CHECKREG r6, 0x000C0099;
CHECKREG r7, 0x0098E7AC;
imm32 r0, 0xc3545abd;
imm32 r1, 0xacbcfec7;
imm32 r2, 0xa1c45679;
imm32 r3, 0x000c0007;
imm32 r4, 0xefbcc569;
imm32 r5, 0x12350c0b;
imm32 r6, 0x000c00cd;
imm32 r7, 0x678e000c;
A1 = R1.L * R0.H, R0.L = ( A0 = R1.L * R0.L );
R1 = A0.w;
A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L );
R3 = A0.w;
A1 = R4.H * R5.H, R4.L = ( A0 += R4.H * R5.H );
R5 = A0.w;
A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H );
R7 = A0.w;
CHECKREG r0, 0xC354FF22;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0xA1C4FF27;
CHECKREG r3, 0xFF27451E;
CHECKREG r4, 0xEFBCFCD7;
CHECKREG r5, 0xFCD6F8F6;
CHECKREG r6, 0x000CFD7D;
CHECKREG r7, 0xFD7CD262;
imm32 r0, 0xd3545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1d45679;
imm32 r3, 0x000d0007;
imm32 r4, 0xefbcd569;
imm32 r5, 0x12350d0b;
imm32 r6, 0x000c00dd;
imm32 r7, 0x678e000d;
A1 += R1.H * R0.L, R0.L = ( A0 -= R1.L * R0.L );
R1 = A0.w;
A1 = R2.H * R3.H, R2.L = ( A0 -= R2.H * R3.L );
R3 = A0.w;
A1 -= R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H );
R5 = A0.w;
A1 += R6.H * R7.L, R6.L = ( A0 = R6.L * R7.H );
R7 = A0.w;
CHECKREG r0, 0xD354FE5B;
CHECKREG r1, 0xFE5AB48C;
CHECKREG r2, 0xA1D4FE60;
CHECKREG r3, 0xFE5FDAF4;
CHECKREG r4, 0xEFBC00B0;
CHECKREG r5, 0x00B0271C;
CHECKREG r6, 0x000C00B3;
CHECKREG r7, 0x00B2CB2C;
imm32 r0, 0xe3545abd;
imm32 r1, 0xaebcfec7;
imm32 r2, 0xa1e45679;
imm32 r3, 0x000e0007;
imm32 r4, 0xefbce569;
imm32 r5, 0x12350e0b;
imm32 r6, 0x000c00ed;
imm32 r7, 0x678e000e;
A1 = R1.H * R0.H, R0.L = ( A0 = R1.L * R0.L );
R1 = A0.w;
A1 += R2.H * R3.H, R2.L = ( A0 += R2.H * R3.L );
R3 = A0.w;
A1 = R4.H * R5.H, R4.L = ( A0 = R4.H * R5.H );
R5 = A0.w;
A1 = R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H );
R7 = A0.w;
CHECKREG r0, 0xE354FF22;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0xA1E4FF1D;
CHECKREG r3, 0xFF1CF84E;
CHECKREG r4, 0xEFBCFDB0;
CHECKREG r5, 0xFDAFB3D8;
CHECKREG r6, 0x000CFCF0;
CHECKREG r7, 0xFCEFF6EC;
pass
|
stsp/binutils-ia16
| 10,611
|
sim/testsuite/bfin/c_dsp32shift_ahh_s.s
|
//Original:/testcases/core/c_dsp32shift_ahh_s/c_dsp32shift_ahh_s.dsp
// Spec Reference: dsp32shift ashift/ashift s
# mach: bfin
.include "testutils.inc"
start
// ashift/ashift s : positive data, count (+)=left (half reg)
// d_reg = ashift/ashift (d BY d_lo) saturation
// Rx by RLx
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5 = ASHIFT R0 BY R0.L (V , S);
R0 = ASHIFT R1 BY R0.L (V , S);
R1 = ASHIFT R2 BY R0.L (V , S);
R2 = ASHIFT R3 BY R0.L (V , S);
R3 = ASHIFT R4 BY R0.L (V , S);
R4 = ASHIFT R5 BY R0.L (V , S);
R7 = ASHIFT R6 BY R0.L (V , S);
R6 = ASHIFT R7 BY R0.L (V , S);
CHECKREG r0, 0x12345678;
CHECKREG r1, 0x00230067;
CHECKREG r2, 0x00340078;
CHECKREG r3, 0x0045FF89;
CHECKREG r4, 0x00010000;
CHECKREG r5, 0x01230000;
CHECKREG r6, 0x0000FFFF;
CHECKREG r7, 0x0067FFAB;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1.L = 5;
R2 = ASHIFT R0 BY R1.L (V , S);
R3 = ASHIFT R1 BY R1.L (V , S);
R4 = ASHIFT R2 BY R1.L (V , S);
R5 = ASHIFT R3 BY R1.L (V , S);
R6 = ASHIFT R4 BY R1.L (V , S);
R7 = ASHIFT R5 BY R1.L (V , S);
R0 = ASHIFT R6 BY R1.L (V , S);
R1 = ASHIFT R7 BY R1.L (V , S);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF7FFF;
CHECKREG r2, 0x24600040;
CHECKREG r3, 0x7FFF00A0;
CHECKREG r4, 0x7FFF0800;
CHECKREG r5, 0x7FFF1400;
CHECKREG r6, 0x7FFF7FFF;
CHECKREG r7, 0x7FFF7FFF;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2 = 15;
R3 = ASHIFT R0 BY R2.L (V , S);
R4 = ASHIFT R1 BY R2.L (V , S);
R5 = ASHIFT R2 BY R2.L (V , S);
R6 = ASHIFT R3 BY R2.L (V , S);
R7 = ASHIFT R4 BY R2.L (V , S);
R0 = ASHIFT R5 BY R2.L (V , S);
R1 = ASHIFT R6 BY R2.L (V , S);
R2 = ASHIFT R7 BY R2.L (V , S);
CHECKREG r0, 0x00007FFF;
CHECKREG r1, 0x7FFF7FFF;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x00007FFF;
CHECKREG r6, 0x7FFF7FFF;
CHECKREG r7, 0x7FFF7FFF;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R3.L = 16;
R4 = ASHIFT R0 BY R3.L (V , S);
R5 = ASHIFT R1 BY R3.L (V , S);
R6 = ASHIFT R2 BY R3.L (V , S);
R7 = ASHIFT R3 BY R3.L (V , S);
R0 = ASHIFT R4 BY R3.L (V , S);
R1 = ASHIFT R5 BY R3.L (V , S);
R2 = ASHIFT R6 BY R3.L (V , S);
R3 = ASHIFT R7 BY R3.L (V , S);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF7FFF;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x7FFF7FFF;
CHECKREG r6, 0x7FFF7FFF;
CHECKREG r7, 0x7FFF7FFF;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -1;
R0 = ASHIFT R0 BY R4.L (V , S);
R1 = ASHIFT R1 BY R4.L (V , S);
R2 = ASHIFT R2 BY R4.L (V , S);
R3 = ASHIFT R3 BY R4.L (V , S);
R4 = ASHIFT R4 BY R4.L (V , S);
R5 = ASHIFT R5 BY R4.L (V , S);
R6 = ASHIFT R6 BY R4.L (V , S);
R7 = ASHIFT R7 BY R4.L (V , S);
CHECKREG r0, 0x00910001;
CHECKREG r1, 0x091A2B3C;
CHECKREG r2, 0x11A233C4;
CHECKREG r3, 0x1A2B3C4D;
CHECKREG r4, 0x22B3FFFF;
CHECKREG r5, 0x2B3CCD5E;
CHECKREG r6, 0x33C4D5E6;
CHECKREG r7, 0x3C4DDE6F;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -6;
R6 = ASHIFT R0 BY R5.L (V , S);
R7 = ASHIFT R1 BY R5.L (V , S);
R0 = ASHIFT R2 BY R5.L (V , S);
R1 = ASHIFT R3 BY R5.L (V , S);
R2 = ASHIFT R4 BY R5.L (V , S);
R3 = ASHIFT R5 BY R5.L (V , S);
R4 = ASHIFT R6 BY R5.L (V , S);
R5 = ASHIFT R7 BY R5.L (V , S);
CHECKREG r0, 0x008D019E;
CHECKREG r1, 0x00D101E2;
CHECKREG r2, 0x0115FE26;
CHECKREG r3, 0x0159FFFF;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00010005;
CHECKREG r6, 0x00040000;
CHECKREG r7, 0x00480159;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R6.L = -15;
R7 = ASHIFT R0 BY R6.L (V , S);
R0 = ASHIFT R1 BY R6.L (V , S);
R1 = ASHIFT R2 BY R6.L (V , S);
R2 = ASHIFT R3 BY R6.L (V , S);
R3 = ASHIFT R4 BY R6.L (V , S);
R4 = ASHIFT R5 BY R6.L (V , S);
R5 = ASHIFT R6 BY R6.L (V , S);
R6 = ASHIFT R7 BY R6.L (V , S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x0000FFFF;
CHECKREG r4, 0x0000FFFF;
CHECKREG r5, 0x0000FFFF;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7.L = -16;
R0 = ASHIFT R0 BY R7.L (V , S);
R1 = ASHIFT R1 BY R7.L (V , S);
R2 = ASHIFT R2 BY R7.L (V , S);
R3 = ASHIFT R3 BY R7.L (V , S);
R4 = ASHIFT R4 BY R7.L (V , S);
R5 = ASHIFT R5 BY R7.L (V , S);
R6 = ASHIFT R6 BY R7.L (V , S);
R7 = ASHIFT R7 BY R7.L (V , S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x0000FFFF;
CHECKREG r5, 0x0000FFFF;
CHECKREG r6, 0x0000FFFF;
CHECKREG r7, 0x0000FFFF;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R0.L = 4;
//r0 = ashift/ashift (r0 by rl0);
R1 = ASHIFT R1 BY R0.L (V , S);
R2 = ASHIFT R2 BY R0.L (V , S);
R3 = ASHIFT R3 BY R0.L (V , S);
R4 = ASHIFT R4 BY R0.L (V , S);
R5 = ASHIFT R5 BY R0.L (V , S);
R6 = ASHIFT R6 BY R0.L (V , S);
R7 = ASHIFT R7 BY R0.L (V , S);
CHECKREG r0, 0x01230004;
CHECKREG r1, 0x7FFF7FFF;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF8000;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x7FFF8000;
CHECKREG r7, 0x7FFF8000;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1.L = 6;
R0 = ASHIFT R0 BY R1.L (V , S);
//r1 = ashift/ashift (r1 by rl1);
R2 = ASHIFT R2 BY R1.L (V , S);
R3 = ASHIFT R3 BY R1.L (V , S);
R4 = ASHIFT R4 BY R1.L (V , S);
R5 = ASHIFT R5 BY R1.L (V , S);
R6 = ASHIFT R6 BY R1.L (V , S);
R7 = ASHIFT R7 BY R1.L (V , S);
CHECKREG r0, 0x48C00080;
CHECKREG r1, 0x12340006;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF8000;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x7FFF8000;
CHECKREG r7, 0x7FFF8000;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 15;
R0 = ASHIFT R0 BY R2.L (V , S);
R1 = ASHIFT R1 BY R2.L (V , S);
//r2 = ashift/ashift (r2 by rl2) s;
R3 = ASHIFT R3 BY R2.L (V , S);
R4 = ASHIFT R4 BY R2.L (V , S);
R5 = ASHIFT R5 BY R2.L (V , S);
R6 = ASHIFT R6 BY R2.L (V , S);
R7 = ASHIFT R7 BY R2.L (V , S);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF7FFF;
CHECKREG r2, 0x2345000F;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF8000;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x7FFF8000;
CHECKREG r7, 0x7FFF8000;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R3.L = 16;
R0 = ASHIFT R0 BY R3.L (V , S);
R1 = ASHIFT R1 BY R3.L (V , S);
R2 = ASHIFT R2 BY R3.L (V , S);
//r3 = ashift/ashift (r3 by rl3) s;
R4 = ASHIFT R4 BY R3.L (V , S);
R5 = ASHIFT R5 BY R3.L (V , S);
R6 = ASHIFT R6 BY R3.L (V , S);
R7 = ASHIFT R7 BY R3.L (V , S);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF7FFF;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x34560010;
CHECKREG r4, 0x7FFF8000;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x7FFF8000;
CHECKREG r7, 0x7FFF8000;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -9;
R0 = ASHIFT R0 BY R4.L (V , S);
R1 = ASHIFT R1 BY R4.L (V , S);
R2 = ASHIFT R2 BY R4.L (V , S);
R3 = ASHIFT R3 BY R4.L (V , S);
//r4 = ashift/ashift (r4 by rl4) s;
R5 = ASHIFT R5 BY R4.L (V , S);
R6 = ASHIFT R6 BY R4.L (V , S);
R7 = ASHIFT R7 BY R4.L (V , S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x0009002B;
CHECKREG r2, 0x00110033;
CHECKREG r3, 0x001A003C;
CHECKREG r4, 0x4567FFF7;
CHECKREG r5, 0x002BFFCD;
CHECKREG r6, 0x0033FFD5;
CHECKREG r7, 0x003CFFDE;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -14;
R0 = ASHIFT R0 BY R5.L (V , S);
R1 = ASHIFT R1 BY R5.L (V , S);
R2 = ASHIFT R2 BY R5.L (V , S);
R3 = ASHIFT R3 BY R5.L (V , S);
R4 = ASHIFT R4 BY R5.L (V , S);
//r5 = ashift/ashift (r5 by rl5) s;
R6 = ASHIFT R6 BY R5.L (V , S);
R7 = ASHIFT R7 BY R5.L (V , S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x0001FFFE;
CHECKREG r5, 0x5678FFF2;
CHECKREG r6, 0x0001FFFE;
CHECKREG r7, 0x0001FFFE;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R6.L = -15;
R0 = ASHIFT R0 BY R6.L (V , S);
R1 = ASHIFT R1 BY R6.L (V , S);
R2 = ASHIFT R2 BY R6.L (V , S);
R3 = ASHIFT R3 BY R6.L (V , S);
R4 = ASHIFT R4 BY R6.L (V , S);
R5 = ASHIFT R5 BY R6.L (V , S);
//r6 = ashift/ashift (r6 by rl6) s;
R7 = ASHIFT R7 BY R6.L (V , S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x0000FFFF;
CHECKREG r5, 0x0000FFFF;
CHECKREG r6, 0x6789FFF1;
CHECKREG r7, 0x0000FFFF;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7.L = -16;
R0 = ASHIFT R0 BY R7.L (V , S);
R1 = ASHIFT R1 BY R7.L (V , S);
R2 = ASHIFT R2 BY R7.L (V , S);
R3 = ASHIFT R3 BY R7.L (V , S);
R4 = ASHIFT R4 BY R7.L (V , S);
R5 = ASHIFT R5 BY R7.L (V , S);
R6 = ASHIFT R6 BY R7.L (V , S);
R7 = ASHIFT R7 BY R7.L (V , S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x0000ffff;
CHECKREG r5, 0x0000ffff;
CHECKREG r6, 0x0000ffff;
CHECKREG r7, 0x0000ffff;
pass
|
stsp/binutils-ia16
| 1,042
|
sim/testsuite/bfin/m8.s
|
// MAC test program.
// Test result extraction of mac instructions.
// Test basic edge values
// UNSIGNED INTEGER mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80000002
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
// load r5=0xffffffff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
R5 = [ P0 ++ ];
// 0x0002 * 0x0002 = 0x0000000004 -> 0x0004
A1 = A0 = 0;
R5.H = (A1 += R0.L * R0.L), R5.L = (A0 += R0.L * R0.L) (IU);
DBGA ( R5.L , 0x4 );
DBGA ( R5.H , 0x4 );
// 0x7fff * 0x007f = 0x00003f7f81 -> 0xffff
A1 = A0 = 0;
R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IU);
R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IU);
DBGA ( R5.L , 0xffff );
DBGA ( R5.H , 0xffff );
pass
.data;
data0:
.dw 0x0002
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
.dw 0xffff
.dw 0xffff
|
stsp/binutils-ia16
| 4,507
|
sim/testsuite/bfin/c_dsp32shift_af_s.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32shift_af_s/c_dsp32shift_af_s.dsp
// Spec Reference: dsp32shift ashift s
# mach: bfin
.include "testutils.inc"
start
// ashift : mix data, count (+)= (half reg)
// d_reg = ashift (d BY d_lo)
// Rx by RLx
imm32 r0, 0x01230001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R4 = ASHIFT R0 BY R0.L (S);
R5 = ASHIFT R1 BY R0.L (S);
R6 = ASHIFT R2 BY R0.L (S);
R7 = ASHIFT R3 BY R0.L (S);
CHECKREG r4, 0x02460002;
CHECKREG r5, 0x2468ACF0;
CHECKREG r6, 0x468ACF12;
CHECKREG r7, 0x68ACF134;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0xa6789abc;
imm32 r6, 0xb789abcd;
imm32 r7, 0xc89abcde;
R1.L = 5;
R5 = ASHIFT R0 BY R1.L (S);
R6 = ASHIFT R1 BY R1.L (S);
R7 = ASHIFT R2 BY R1.L (S);
R4 = ASHIFT R3 BY R1.L (S);
CHECKREG r4, 0x7FFFFFFF;
CHECKREG r5, 0x24600040;
CHECKREG r6, 0x7FFFFFFF;
CHECKREG r7, 0x7FFFFFFF;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2 = 14;
R6 = ASHIFT R0 BY R2.L (S);
R7 = ASHIFT R1 BY R2.L (S);
R4 = ASHIFT R2 BY R2.L (S);
R5 = ASHIFT R3 BY R2.L (S);
CHECKREG r4, 0x00038000;
CHECKREG r5, 0x7FFFFFFF;
CHECKREG r6, 0x7FFFFFFF;
CHECKREG r7, 0x7FFFFFFF;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0xa56789ab;
imm32 r5, 0xb6789abc;
imm32 r6, 0xc789abcd;
imm32 r7, 0xd89abcde;
R3.L = 15;
R7 = ASHIFT R0 BY R3.L (S);
R6 = ASHIFT R1 BY R3.L (S);
R5 = ASHIFT R2 BY R3.L (S);
R4 = ASHIFT R3 BY R3.L (S);
CHECKREG r4, 0x7FFFFFFF;
CHECKREG r5, 0x7FFFFFFF;
CHECKREG r6, 0x7FFFFFFF;
CHECKREG r7, 0x7FFFFFFF;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -1;
R7 = ASHIFT R0 BY R4.L;
R0 = ASHIFT R1 BY R4.L;
R1 = ASHIFT R2 BY R4.L;
R2 = ASHIFT R3 BY R4.L;
R3 = ASHIFT R4 BY R4.L;
R4 = ASHIFT R5 BY R4.L;
R5 = ASHIFT R6 BY R4.L;
R6 = ASHIFT R7 BY R4.L;
CHECKREG r0, 0x091A2B3C;
CHECKREG r1, 0x11A2B3C4;
CHECKREG r2, 0x1A2B3C4D;
CHECKREG r3, 0x22B3FFFF;
CHECKREG r4, 0x2B3C4D5E;
CHECKREG r5, 0x40000000;
CHECKREG r6, 0x40000000;
CHECKREG r7, 0x00918001;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R5.L = -6;
R6 = ASHIFT R0 BY R5.L (S);
R7 = ASHIFT R1 BY R5.L (S);
R0 = ASHIFT R2 BY R5.L (S);
R1 = ASHIFT R3 BY R5.L (S);
R2 = ASHIFT R4 BY R5.L (S);
R3 = ASHIFT R5 BY R5.L (S);
R4 = ASHIFT R6 BY R5.L (S);
R5 = ASHIFT R7 BY R5.L (S);
CHECKREG r0, 0xFE4D159E;
CHECKREG r1, 0xFE9159E2;
CHECKREG r2, 0xFED59E26;
CHECKREG r3, 0xFF19E3FF;
CHECKREG r4, 0x00001230;
CHECKREG r5, 0xFFF82345;
CHECKREG r6, 0x00048C00;
CHECKREG r7, 0xFE08D159;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R6.L = -15;
R5 = ASHIFT R0 BY R6.L (S);
R0 = ASHIFT R1 BY R6.L (S);
R7 = ASHIFT R2 BY R6.L (S);
R0 = ASHIFT R3 BY R6.L (S);
R1 = ASHIFT R4 BY R6.L (S);
R2 = ASHIFT R5 BY R6.L (S);
R3 = ASHIFT R6 BY R6.L (S);
R6 = ASHIFT R7 BY R6.L (S);
CHECKREG r0, 0x000068AC;
CHECKREG r1, 0x00008ACF;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x0000CF13;
CHECKREG r4, 0x456789AB;
CHECKREG r5, 0x00000246;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x0000468A;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R7.L = -14;
R0 = ASHIFT R0 BY R7.L (S);
R1 = ASHIFT R1 BY R7.L (S);
R2 = ASHIFT R2 BY R7.L (S);
R3 = ASHIFT R3 BY R7.L (S);
R4 = ASHIFT R4 BY R7.L (S);
R5 = ASHIFT R5 BY R7.L (S);
R6 = ASHIFT R6 BY R7.L (S);
R7 = ASHIFT R7 BY R7.L (S);
CHECKREG r0, 0x0000048C;
CHECKREG r1, 0xFFFE08D1;
CHECKREG r2, 0xFFFE4D15;
CHECKREG r3, 0xFFFE9159;
CHECKREG r4, 0xFFFED59E;
CHECKREG r5, 0xFFFF19E2;
CHECKREG r6, 0xFFFF5E26;
CHECKREG r7, 0xFFFFA26B;
pass
|
stsp/binutils-ia16
| 1,468
|
sim/testsuite/bfin/dsp_s1.s
|
/* SHIFT test program.
* Test r0, r1, A0 >>= BITMUX;
*/
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = r0;
// load r0=0x80000009
// load r1=0x10000009
// load r2=0x0000000f
// load r3=0x00000000
// load r4=0x80000008
// load r5=0x00000000
loadsym P0, data0;
loadsym P1, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
R5 = [ P0 ++ ];
// insert two bits, both equal to 1
// A0: 00 0000 000f -> c0 0000 0003
// r0: 8000 0009 -> 4000 0004
// r1: 1000 0009 -> 0800 0004
R0 = [ P1 + 0 ];
R1 = [ P1 + 4 ];
A0.w = R2;
A0.x = R3.L;
BITMUX( R0 , R1, A0) (ASR);
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0003 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0xffc0 );
DBGA ( R0.L , 0x0004 );
DBGA ( R0.H , 0x4000 );
DBGA ( R1.L , 0x0004 );
DBGA ( R1.H , 0x0800 );
// insert two bits, one equal to 1, other to 0
// A0: 00 0000 000f -> 40 0000 0003
// r0: 8000 0009 -> 4000 0004
// r4: 8000 0008 -> 4000 0004
R0 = [ P1 + 0 ];
R4 = [ P1 + 16 ];
A0.w = R2;
A0.x = R3.L;
BITMUX( R0 , R4, A0) (ASR);
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0003 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0040 );
DBGA ( R0.L , 0x0004 );
DBGA ( R0.H , 0x4000 );
DBGA ( R4.L , 0x0004 );
DBGA ( R4.H , 0x4000 );
pass
.data
data0:
.dw 0x0009
.dw 0x8000
.dw 0x0009
.dw 0x1000
.dw 0x000f
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0008
.dw 0x8000
.dw 0x0000
.dw 0x0000
|
stsp/binutils-ia16
| 2,204
|
sim/testsuite/bfin/c_compi2opd_dr_eq_i7_n.s
|
//Original:/testcases/core/c_compi2opd_dr_eq_i7_n/c_compi2opd_dr_eq_i7_n.dsp
// Spec Reference: compi2opd dregs = imm7 negative
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 = -0;
R1 = -1;
R2 = -2;
R3 = -3;
R4 = -4;
R5 = -5;
R6 = -6;
R7 = -7;
CHECKREG r0, -0;
CHECKREG r1, -1;
CHECKREG r2, -2;
CHECKREG r3, -3;
CHECKREG r4, -4;
CHECKREG r5, -5;
CHECKREG r6, -6;
CHECKREG r7, -7;
R0 = -8;
R1 = -9;
R2 = -10;
R3 = -11;
R4 = -12;
R5 = -13;
R6 = -14;
R7 = -15;
CHECKREG r0, -8;
CHECKREG r1, -9;
CHECKREG r2, -10;
CHECKREG r3, -11;
CHECKREG r4, -12;
CHECKREG r5, -13;
CHECKREG r6, -14;
CHECKREG r7, -15;
R0 = -16;
R1 = -17;
R2 = -18;
R3 = -19;
R4 = -20;
R5 = -21;
R6 = -22;
R7 = -23;
CHECKREG r0, -16;
CHECKREG r1, -17;
CHECKREG r2, -18;
CHECKREG r3, -19;
CHECKREG r4, -20;
CHECKREG r5, -21;
CHECKREG r6, -22;
CHECKREG r7, -23;
R0 = -24;
R1 = -25;
R2 = -26;
R3 = -27;
R4 = -28;
R5 = -29;
R6 = -30;
R7 = -31;
CHECKREG r0, -24;
CHECKREG r1, -25;
CHECKREG r2, -26;
CHECKREG r3, -27;
CHECKREG r4, -28;
CHECKREG r5, -29;
CHECKREG r6, -30;
CHECKREG r7, -31;
R0 = -32;
R1 = -33;
R2 = -34;
R3 = -35;
R4 = -36;
R5 = -37;
R6 = -38;
R7 = -39;
CHECKREG r0, -32;
CHECKREG r1, -33;
CHECKREG r2, -34;
CHECKREG r3, -35;
CHECKREG r4, -36;
CHECKREG r5, -37;
CHECKREG r6, -38;
CHECKREG r7, -39;
R0 = -40;
R1 = -41;
R2 = -42;
R3 = -43;
R4 = -44;
R5 = -45;
R6 = -46;
R7 = -47;
CHECKREG r0, -40;
CHECKREG r1, -41;
CHECKREG r2, -42;
CHECKREG r3, -43;
CHECKREG r4, -44;
CHECKREG r5, -45;
CHECKREG r6, -46;
CHECKREG r7, -47;
R0 = -48;
R1 = -49;
R2 = -50;
R3 = -51;
R4 = -52;
R5 = -53;
R6 = -54;
R7 = -55;
CHECKREG r0, -48;
CHECKREG r1, -49;
CHECKREG r2, -50;
CHECKREG r3, -51;
CHECKREG r4, -52;
CHECKREG r5, -53;
CHECKREG r6, -54;
CHECKREG r7, -55;
R0 = -56;
R1 = -57;
R2 = -58;
R3 = -59;
R4 = -60;
R5 = -61;
R6 = -62;
R7 = -63;
CHECKREG r0, -56;
CHECKREG r1, -57;
CHECKREG r2, -58;
CHECKREG r3, -59;
CHECKREG r4, -60;
CHECKREG r5, -61;
CHECKREG r6, -62;
CHECKREG r7, -63;
R0 = -64;
R1 = -64;
R2 = -64;
R3 = -64;
R4 = -64;
R5 = -64;
R6 = -64;
R7 = -64;
CHECKREG r0, -64;
CHECKREG r1, -64;
CHECKREG r2, -64;
CHECKREG r3, -64;
CHECKREG r4, -64;
CHECKREG r5, -64;
CHECKREG r6, -64;
CHECKREG r7, -64;
pass
|
stsp/binutils-ia16
| 2,889
|
sim/testsuite/bfin/byteop16p.s
|
# Blackfin testcase for BYTEOP16P
# mach: bfin
.include "testutils.inc"
start
.macro check_it resL:req, resH:req
imm32 R6, \resL
CC = R4 == R6;
IF !CC JUMP 1f;
imm32 R7, \resH
CC = R5 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop16p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req
dmm32 I0, \i0
dmm32 I1, \i1
(R4, R5) = BYTEOP16P (R1:0, R3:2);
check_it \resL, \resH
(R4, R5) = BYTEOP16P (R1:0, R3:2) (R);
check_it \resLR, \resHR
jump 2f;
1: fail
2:
.endm
imm32 R0, 0x01020304
imm32 R1, 0x10203040
imm32 R2, 0x0a0b0c0d
imm32 R3, 0xa0b0c0d0
test_byteop16p 0, 0, 0x000b000d, 0x000f0011, 0x00b000d0, 0x00f00110
test_byteop16p 0, 1, 0x00d1000c, 0x000e0010, 0x001d00c0, 0x00e00100
test_byteop16p 0, 2, 0x00c100d2, 0x000d000f, 0x001c002d, 0x00d000f0
test_byteop16p 0, 3, 0x00b100c2, 0x00d3000e, 0x001b002c, 0x003d00e0
test_byteop16p 1, 0, 0x004a000c, 0x000e0010, 0x00a400c0, 0x00e00100
test_byteop16p 1, 1, 0x0110000b, 0x000d000f, 0x001100b0, 0x00d000f0
test_byteop16p 1, 2, 0x010000d1, 0x000c000e, 0x0010001d, 0x00c000e0
test_byteop16p 1, 3, 0x00f000c1, 0x00d2000d, 0x000f001c, 0x002d00d0
test_byteop16p 2, 0, 0x003a004b, 0x000d000f, 0x00a300b4, 0x00d000f0
test_byteop16p 2, 1, 0x0100004a, 0x000c000e, 0x001000a4, 0x00c000e0
test_byteop16p 2, 2, 0x00f00110, 0x000b000d, 0x000f0011, 0x00b000d0
test_byteop16p 2, 3, 0x00e00100, 0x00d1000c, 0x000e0010, 0x001d00c0
test_byteop16p 3, 0, 0x002a003b, 0x004c000e, 0x00a200b3, 0x00c400e0
test_byteop16p 3, 1, 0x00f0003a, 0x004b000d, 0x000f00a3, 0x00b400d0
test_byteop16p 3, 2, 0x00e00100, 0x004a000c, 0x000e0010, 0x00a400c0
test_byteop16p 3, 3, 0x00d000f0, 0x0110000b, 0x000d000f, 0x001100b0
imm32 R0, ~0x01020304
imm32 R1, ~0x10203040
imm32 R2, ~0x0a0b0c0d
imm32 R3, ~0xa0b0c0d0
test_byteop16p 0, 0, 0x01f301f1, 0x01ef01ed, 0x014e012e, 0x010e00ee
test_byteop16p 0, 1, 0x012d01f2, 0x01f001ee, 0x01e1013e, 0x011e00fe
test_byteop16p 0, 2, 0x013d012c, 0x01f101ef, 0x01e201d1, 0x012e010e
test_byteop16p 0, 3, 0x014d013c, 0x012b01f0, 0x01e301d2, 0x01c1011e
test_byteop16p 1, 0, 0x01b401f2, 0x01f001ee, 0x015a013e, 0x011e00fe
test_byteop16p 1, 1, 0x00ee01f3, 0x01f101ef, 0x01ed014e, 0x012e010e
test_byteop16p 1, 2, 0x00fe012d, 0x01f201f0, 0x01ee01e1, 0x013e011e
test_byteop16p 1, 3, 0x010e013d, 0x012c01f1, 0x01ef01e2, 0x01d1012e
test_byteop16p 2, 0, 0x01c401b3, 0x01f101ef, 0x015b014a, 0x012e010e
test_byteop16p 2, 1, 0x00fe01b4, 0x01f201f0, 0x01ee015a, 0x013e011e
test_byteop16p 2, 2, 0x010e00ee, 0x01f301f1, 0x01ef01ed, 0x014e012e
test_byteop16p 2, 3, 0x011e00fe, 0x012d01f2, 0x01f001ee, 0x01e1013e
test_byteop16p 3, 0, 0x01d401c3, 0x01b201f0, 0x015c014b, 0x013a011e
test_byteop16p 3, 1, 0x010e01c4, 0x01b301f1, 0x01ef015b, 0x014a012e
test_byteop16p 3, 2, 0x011e00fe, 0x01b401f2, 0x01f001ee, 0x015a013e
test_byteop16p 3, 3, 0x012e010e, 0x00ee01f3, 0x01f101ef, 0x01ed014e
pass
|
stsp/binutils-ia16
| 1,050
|
sim/testsuite/bfin/c_brcc_brf_nbp.s
|
//Original:/testcases/core/c_brcc_brf_nbp/c_brcc_brf_nbp.dsp
// Spec Reference: brcc brf no bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
IF !CC JUMP good1; // branch on false (should branch)
CC = ! CC; // set cc=1
R1 = 1; // if go here, error
good1: IF !CC JUMP good2; // branch on false (should branch)
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; //
IF !CC JUMP bad2; // branch on false (should not branch)
CC = ! CC;
IF !CC JUMP good3; // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF !CC JUMP end; // branch on true (should branch)
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 1,203
|
sim/testsuite/bfin/byteunpack.s
|
# Blackfin testcase for playing with BYTEUNPACK
# mach: bfin
.include "testutils.inc"
start
.macro _bu_pre_test i0:req, src0:req, src1:req
dmm32 I0, \i0
imm32 R0, \src0
imm32 R1, \src1
.endm
.macro _bu_chk_test dst0:req, dst1:req
imm32 R2, \dst0
imm32 R3, \dst1
CC = R5 == R2;
IF !CC jump 1f;
CC = R6 == R3;
IF !CC jump 1f;
.endm
.macro bu_test i0:req, dst0:req, dst1:req, src0:req, src1:req
_bu_pre_test \i0, \src0, \src1
(R6, R5) = BYTEUNPACK R1:0;
_bu_chk_test \dst0, \dst1
.endm
.macro bu_r_test i0:req, dst0:req, dst1:req, src0:req, src1:req
_bu_pre_test \i0, \src0, \src1
(R6, R5) = BYTEUNPACK R1:0 (R);
_bu_chk_test \dst0, \dst1
.endm
# Taken from PRM
bu_test 0, 0x00BA00DD, 0x00BE00EF, 0xBEEFBADD, 0xFEEDFACE
bu_test 1, 0x00EF00BA, 0x00CE00BE, 0xBEEFBADD, 0xFEEDFACE
bu_test 2, 0x00BE00EF, 0x00FA00CE, 0xBEEFBADD, 0xFEEDFACE
bu_test 3, 0x00CE00BE, 0x00ED00FA, 0xBEEFBADD, 0xFEEDFACE
# Taken from PRM
bu_r_test 0, 0x00FA00CE, 0x00FE00ED, 0xBEEFBADD, 0xFEEDFACE
bu_r_test 1, 0x00ED00FA, 0x00DD00FE, 0xBEEFBADD, 0xFEEDFACE
bu_r_test 2, 0x00FE00ED, 0x00BA00DD, 0xBEEFBADD, 0xFEEDFACE
bu_r_test 3, 0x00DD00FE, 0x00EF00BA, 0xBEEFBADD, 0xFEEDFACE
pass
1: fail
|
stsp/binutils-ia16
| 6,136
|
sim/testsuite/bfin/c_dsp32alu_rl_rnd12_p.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_p/c_dsp32alu_rl_rnd12_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x85678011;
imm32 r1, 0x9189a11d;
imm32 r2, 0xa4245235;
imm32 r3, 0xb6637747;
imm32 r4, 0xc67849db;
imm32 r5, 0x6789a5fd;
imm32 r6, 0xe4445565;
imm32 r7, 0x86667707;
R0.L = R0 + R0 (RND12);
R1.L = R0 + R1 (RND12);
R2.L = R0 + R2 (RND12);
R3.L = R0 + R3 (RND12);
R4.L = R0 + R4 (RND12);
R5.L = R0 + R5 (RND12);
R6.L = R0 + R6 (RND12);
R7.L = R0 + R7 (RND12);
CHECKREG r0, 0x85678000;
CHECKREG r1, 0x91898000;
CHECKREG r2, 0xA4248000;
CHECKREG r3, 0xB6638000;
CHECKREG r4, 0xC6788000;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0xE4448000;
CHECKREG r7, 0x86668000;
imm32 r0, 0x75678921;
imm32 r1, 0x2789ab14;
imm32 r2, 0xd4745515;
imm32 r3, 0x4d677767;
imm32 r4, 0x56d8791b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86a6d777;
R0.L = R1 + R0 (RND12);
R1.L = R1 + R1 (RND12);
R2.L = R1 + R2 (RND12);
R3.L = R1 + R3 (RND12);
R4.L = R1 + R4 (RND12);
R5.L = R1 + R5 (RND12);
R6.L = R1 + R6 (RND12);
R7.L = R1 + R7 (RND12);
CHECKREG r0, 0x75677FFF;
CHECKREG r1, 0x27897FFF;
CHECKREG r2, 0xD474bfdd;
CHECKREG r3, 0x4D677fff;
CHECKREG r4, 0x56D87FFF;
CHECKREG r5, 0x678D7FFF;
CHECKREG r6, 0x74447FFF;
CHECKREG r7, 0x86A68000;
imm32 r0, 0x55678911;
imm32 r1, 0x2689ab2d;
imm32 r2, 0x3d44551a;
imm32 r3, 0x469677cd;
imm32 r4, 0xa67a89bb;
imm32 r5, 0x6789bb1d;
imm32 r6, 0x7444d525;
imm32 r7, 0x8666c747;
R0.L = R2 + R0 (RND12);
R1.L = R2 + R1 (RND12);
R2.L = R2 + R2 (RND12);
R3.L = R2 + R3 (RND12);
R4.L = R2 + R4 (RND12);
R5.L = R2 + R5 (RND12);
R6.L = R2 + R6 (RND12);
R7.L = R2 + R7 (RND12);
CHECKREG r0, 0x55677fff;
CHECKREG r1, 0x26897fff;
CHECKREG r2, 0x3D447fff;
CHECKREG r3, 0x46967fff;
CHECKREG r4, 0xA67A8000;
CHECKREG r5, 0x67897fff;
CHECKREG r6, 0x74447fff;
CHECKREG r7, 0x86668000;
imm32 r0, 0xf5678901;
imm32 r1, 0xd789ab7d;
imm32 r2, 0x34445565;
imm32 r3, 0xe6667757;
imm32 r4, 0x5678894b;
imm32 r5, 0x6d89ab3d;
imm32 r6, 0x7444d525;
imm32 r7, 0xe6667b77;
R0.L = R3 + R0 (RND12);
R1.L = R3 + R1 (RND12);
R2.L = R3 + R2 (RND12);
R3.L = R3 + R3 (RND12);
R4.L = R3 + R4 (RND12);
R5.L = R3 + R5 (RND12);
R6.L = R3 + R6 (RND12);
R7.L = R3 + R7 (RND12);
CHECKREG r0, 0xF5678000;
CHECKREG r1, 0xD7898000;
CHECKREG r2, 0x34447FFF;
CHECKREG r3, 0xE6668000;
CHECKREG r4, 0x56787FFF;
CHECKREG r5, 0x6D897FFF;
CHECKREG r6, 0x74447FFF;
CHECKREG r7, 0xE6668000;
imm32 r0, 0xa5678911;
imm32 r1, 0x2b89ab1d;
imm32 r2, 0x34c45515;
imm32 r3, 0x46d67717;
imm32 r4, 0x56e8891b;
imm32 r5, 0x67f9ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86687777;
R0.L = R4 + R0 (RND12);
R1.L = R4 + R1 (RND12);
R2.L = R4 + R2 (RND12);
R3.L = R4 + R3 (RND12);
R4.L = R4 + R4 (RND12);
R5.L = R4 + R5 (RND12);
R6.L = R4 + R6 (RND12);
R7.L = R4 + R7 (RND12);
CHECKREG r0, 0xA567c501;
CHECKREG r1, 0x2B897fff;
CHECKREG r2, 0x34C47FFF;
CHECKREG r3, 0x46D67FFF;
CHECKREG r4, 0x56E87FFF;
CHECKREG r5, 0x67F97FFF;
CHECKREG r6, 0x74447FFF;
CHECKREG r7, 0x86688000;
imm32 r0, 0xe5678911;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x34445535;
imm32 r3, 0xd6667747;
imm32 r4, 0x5ff8895b;
imm32 r5, 0x6789ab8d;
imm32 r6, 0x744e5515;
imm32 r7, 0x8666a7b7;
R0.L = R5 + R0 (RND12);
R1.L = R5 + R1 (RND12);
R2.L = R5 + R2 (RND12);
R3.L = R5 + R3 (RND12);
R4.L = R5 + R4 (RND12);
R5.L = R5 + R5 (RND12);
R6.L = R5 + R6 (RND12);
R7.L = R5 + R7 (RND12);
CHECKREG r0, 0xE5677FFF;
CHECKREG r1, 0x27897FFF;
CHECKREG r2, 0x34447FFF;
CHECKREG r3, 0xD6667FFF;
CHECKREG r4, 0x5FF87fff;
CHECKREG r5, 0x67897FFF;
CHECKREG r6, 0x744E7FFF;
CHECKREG r7, 0x86668000;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ae1d;
imm32 r2, 0x344455e5;
imm32 r3, 0x4666771d;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789abdd;
imm32 r6, 0x74a45515;
imm32 r7, 0x866c77b7;
R0.L = R6 + R0 (RND12);
R1.L = R6 + R1 (RND12);
R2.L = R6 + R2 (RND12);
R3.L = R6 + R3 (RND12);
R4.L = R6 + R4 (RND12);
R5.L = R6 + R5 (RND12);
R6.L = R6 + R6 (RND12);
R7.L = R6 + R7 (RND12);
CHECKREG r0, 0x15677FFF;
CHECKREG r1, 0x27897FFF;
CHECKREG r2, 0x34447FFF;
CHECKREG r3, 0x46667FFF;
CHECKREG r4, 0x56787FFF;
CHECKREG r5, 0x67897FFF;
CHECKREG r6, 0x74A47FFF;
CHECKREG r7, 0x866Cb10f;
imm32 r0, 0x25678931;
imm32 r1, 0x2389ab14;
imm32 r2, 0x34445576;
imm32 r3, 0x46567787;
imm32 r4, 0x5678899b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x7444b515;
imm32 r7, 0xb666a777;
R0.L = R7 + R0 (RND12);
R1.L = R7 + R1 (RND12);
R2.L = R7 + R2 (RND12);
R3.L = R7 + R3 (RND12);
R4.L = R7 + R4 (RND12);
R5.L = R7 + R5 (RND12);
R6.L = R7 + R6 (RND12);
R7.L = R7 + R7 (RND12);
CHECKREG r0, 0x25678000;
CHECKREG r1, 0x23898000;
CHECKREG r2, 0x34448000;
CHECKREG r3, 0x4656cbd2;
CHECKREG r4, 0x56787FFF;
CHECKREG r5, 0x678D7FFF;
CHECKREG r6, 0x74447FFF;
CHECKREG r7, 0xB6668000;
imm32 r0, 0xaa678911;
imm32 r1, 0x27ddab1d;
imm32 r2, 0x344bb515;
imm32 r3, 0x46667717;
imm32 r4, 0x56dd891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444bb15;
imm32 r7, 0x86ff7777;
R6.L = R2 + R3 (RND12);
R1.L = R4 + R5 (RND12);
R5.L = R7 + R2 (RND12);
R3.L = R0 + R0 (RND12);
R0.L = R3 + R4 (RND12);
R2.L = R5 + R7 (RND12);
R7.L = R6 + R7 (RND12);
R4.L = R1 + R6 (RND12);
CHECKREG r0, 0xAA677FFF;
CHECKREG r1, 0x27DD7FFF;
CHECKREG r2, 0x344B8000;
CHECKREG r3, 0x46668000;
CHECKREG r4, 0x56DD7FFF;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0x74447FFF;
CHECKREG r7, 0x86FFb43f;
imm32 r0, 0x95678911;
imm32 r1, 0x2d89ab1d;
imm32 r2, 0x34b45515;
imm32 r3, 0x46c67717;
imm32 r4, 0x567e891b;
imm32 r5, 0x678fab1d;
imm32 r6, 0x744e5515;
imm32 r7, 0x8b66a777;
R3.L = R4 + R0 (RND12);
R1.L = R6 + R3 (RND12);
R4.L = R3 + R2 (RND12);
R6.L = R7 + R1 (RND12);
R2.L = R5 + R4 (RND12);
R7.L = R2 + R7 (RND12);
R0.L = R1 + R6 (RND12);
R5.L = R0 + R5 (RND12);
CHECKREG r0, 0x95677fff;
CHECKREG r1, 0x2D897FFF;
CHECKREG r2, 0x34B47FFF;
CHECKREG r3, 0x46C68000;
CHECKREG r4, 0x567E7FFF;
CHECKREG r5, 0x678Fcf73;
CHECKREG r6, 0x744E8000;
CHECKREG r7, 0x8B668000;
pass
|
stsp/binutils-ia16
| 4,328
|
sim/testsuite/bfin/c_cc2stat_cc_av0.S
|
//Original:/testcases/core/c_cc2stat_cc_av0/c_cc2stat_cc_av0.dsp
// Spec Reference: cc2stat cc av0
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// test CC = AV0 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
CC = AV0; //
R0 = CC; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
CC = AV0; //
R1 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
CC = AV0; //
R2 = CC; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
CC = AV0; //
R3 = CC; //
// test cc |= AV0 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
CC |= AV0; //
R4 = CC; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
CC |= AV0; //
R5 = CC; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 0
CC |= AV0; //
R6 = CC; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
CC |= AV0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _SET;
// test CC &= AV0 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
CC &= AV0; //
R4 = CC; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
CC &= AV0; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
CC &= AV0; //
R6 = CC; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
CC &= AV0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _UNSET;
CHECKREG r7, _SET;
// test CC ^= AV0 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
CC ^= AV0; //
R4 = CC; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
CC ^= AV0; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
CC ^= AV0; //
R6 = CC; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
CC ^= AV0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _UNSET;
// test AV0 = CC 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
AV0 = CC; //
R0 = ASTAT; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
AV0 = CC; //
R1 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
AV0 = CC; //
R2 = ASTAT; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
AV0 = CC; //
R3 = ASTAT; //
// test AV0 |= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
AV0 |= CC; //
R4 = ASTAT; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
AV0 |= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
AV0 |= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
AV0 |= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV0);
CHECKREG r3, (_CC|_AV0);
CHECKREG r4, _UNSET;
CHECKREG r5, _AV0;
CHECKREG r6, (_CC|_AV0);
CHECKREG r7, (_CC|_AV0);
// test AV0 &= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
AV0 &= CC; //
R4 = ASTAT; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
AV0 &= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
AV0 &= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
AV0 &= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV0);
CHECKREG r3, (_CC|_AV0);
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, (_CC);
CHECKREG r7, (_CC|_AV0);
// test AV0 ^= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
AV0 ^= CC; //
R4 = ASTAT; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
AV0 ^= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
AV0 ^= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
AV0 ^= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV0);
CHECKREG r3, (_CC|_AV0);
CHECKREG r4, _UNSET;
CHECKREG r5, _AV0;
CHECKREG r6, (_CC|_AV0);
CHECKREG r7, _CC;
pass
|
stsp/binutils-ia16
| 4,120
|
sim/testsuite/bfin/load.s
|
# Blackfin testcase for register load instructions
# mach: bfin
.include "testutils.inc"
start
.macro load32 num:req, reg0:req, reg1:req
imm32 \reg0 \num
imm32 \reg1 \num
CC = \reg0 == \reg1
if CC jump 2f;
fail
2:
.endm
.macro load32p num:req preg:req
imm32 r0 \num
imm32 \preg \num
r1 = \preg
cc = r0 == r1
if CC jump 3f;
fail
3:
imm32 \preg 0
.endm
.macro load16z num:req reg0:req reg1:req
\reg0 = \num (Z);
imm32 \reg1 \num
CC = \reg0 == \reg1
if CC jump 4f;
fail
4:
.endm
.macro load16zp num:req reg:req
\reg = \num (Z);
imm32 r1 \num;
r0 = \reg;
cc = r0 == r1
if CC jump 5f;
fail
5:
.endm
.macro load16x num:req reg0:req reg1:req
\reg0 = \num (X);
imm32 \reg1, \num
CC = \reg0 == \reg1
if CC jump 6f;
fail
6:
.endm
/* Clobbers R0 */
.macro loadinc preg0:req, preg1:req, dreg:req
loadsym \preg0, _buf
\preg1 = \preg0;
\dreg = \preg0;
[\preg0\()++] = \preg0;
\dreg += 4;
R0 = \preg0;
CC = \dreg == R0;
if CC jump 7f;
fail
7:
R0 = [ \preg1\() ];
\dreg += -4;
CC = \dreg == R0;
if CC jump 8f;
fail
8:
.endm
/* test a bunch of values */
/* load_immediate (Half-Word Load)
* register = constant
* reg_lo = uimm16;
* reg_hi = uimm16;
*/
load32 0 R0 R1
load32 0xFFFFFFFF R0 R1
load32 0x55aaaa55 r0 r1
load32 0x12345678 r0 r1
load32 0x12345678 R0 R2
load32 0x23456789 R0 R3
load32 0x3456789a R0 R4
load32 0x456789ab R0 R5
load32 0x56789abc R0 R6
load32 0x6789abcd R0 R7
load32 0x789abcde R0 R0
load32 0x89abcdef R1 R0
load32 0x9abcdef0 R2 R0
load32 0xabcdef01 R3 R0
load32 0xbcdef012 R4 R0
load32 0xcdef0123 R5 R0
load32 0xdef01234 R6 R0
load32 0xef012345 R7 R0
load32p 0xf0123456 P0
load32p 0x01234567 P1
load32p 0x12345678 P2
.ifndef BFIN_HOST
load32p 0x23456789 P3
.endif
load32p 0x3456789a P4
load32p 0x456789ab P5
load32p 0x56789abc SP
load32p 0x6789abcd FP
load32p 0x789abcde I0
load32p 0x89abcdef I1
load32p 0x9abcdef0 I2
load32p 0xabcdef01 I3
load32p 0xbcdef012 M0
load32p 0xcdef0123 M1
load32p 0xdef01234 M2
load32p 0xef012345 M3
load32p 0xf0123456 B0
load32p 0x01234567 B1
load32p 0x12345678 B2
load32p 0x23456789 B3
load32p 0x3456789a L0
load32p 0x456789ab L1
load32p 0x56789abc L2
load32p 0x6789abcd L3
/* Zero Extended */
load16z 0x1234 R0 R1
load16z 0x2345 R0 R1
load16z 0x3456 R0 R2
load16z 0x4567 R0 R3
load16z 0x5678 R0 R4
load16z 0x6789 R0 R5
load16z 0x789a R0 R6
load16z 0x89ab R0 R7
load16z 0x9abc R1 R0
load16z 0xabcd R2 R0
load16z 0xbcde R3 R0
load16z 0xcdef R4 R0
load16z 0xdef0 R5 R0
load16z 0xef01 R6 R0
load16z 0xf012 R7 R0
load16zp 0x0123 P0
load16zp 0x1234 P1
load16zp 0x1234 p2
.ifndef BFIN_HOST
load16zp 0x2345 p3
.endif
load16zp 0x3456 p4
load16zp 0x4567 p5
load16zp 0x5678 sp
load16zp 0x6789 fp
load16zp 0x789a i0
load16zp 0x89ab i1
load16zp 0x9abc i2
load16zp 0xabcd i3
load16zp 0xbcde m0
load16zp 0xcdef m1
load16zp 0xdef0 m2
load16zp 0xef01 m3
load16zp 0xf012 b0
load16zp 0x0123 b1
load16zp 0x1234 b2
load16zp 0x2345 b3
load16zp 0x3456 l0
load16zp 0x4567 l1
load16zp 0x5678 l2
load16zp 0x6789 l3
/* Sign Extended */
load16x 0x20 R0 R1
load16x 0x3F R0 R1
load16x -0x20 R0 R1
load16x -0x3F R0 R1
load16x 0x1234 R0 R1
load16x 0x2345 R0 R1
load16x 0x3456 R0 R2
load16x 0x4567 R0 R3
load16x 0x5678 R0 R4
load16x 0x6789 R0 R5
load16x 0x789a R0 R6
load16x 0x09ab R0 R7
load16x -0x1abc R1 R0
load16x -0x2bcd R2 R0
load16x -0x3cde R3 R0
load16x -0x4def R4 R0
load16x -0x5ef0 R5 R0
load16x -0x6f01 R6 R0
load16x -0x7012 R7 R0
loadinc P0, P1, R1
loadinc P1, P2, R1
loadinc P2, P1, R2
.ifndef BFIN_HOST
loadinc P3, P4, R3
.endif
loadinc P4, P5, R4
loadinc FP, P0, R7
loadinc P0, I0, R1
loadinc P1, I1, R1
loadinc P2, I2, R1
.ifndef BFIN_HOST
loadinc P3, I0, R1
.endif
loadinc P4, I2, R1
loadinc P5, I3, R1
A1 = A0 = 0;
R0 = 0x01 (Z);
A0.x = R0;
imm32 r4, 0x32e02d1a
A1.x = R4;
A0.w = A1.x;
R3 = A0.w;
R2 = A0.x;
imm32 r0, 0x0000001a
imm32 r1, 0x00000001
CC = R1 == R2;
if CC jump 1f;
fail
1:
CC = R0 == R3
if CC jump 2f;
fail
2:
pass
.data
_buf:
.rept 0x80
.long 0
.endr
|
stsp/binutils-ia16
| 7,130
|
sim/testsuite/bfin/c_ldstpmod_st_dr_lo.s
|
//Original:testcases/core/c_ldstpmod_st_dr_lo/c_ldstpmod_st_dr_lo.dsp
// Spec Reference: c_ldstpmod store dreg lo
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x600f5000;
imm32 r1, 0x700e6001;
imm32 r2, 0x800d7002;
imm32 r3, 0x900c8003;
imm32 r4, 0xa00b9004;
imm32 r5, 0xb00aa005;
imm32 r6, 0xc009b006;
imm32 r7, 0xd008c007;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0x02;
loadsym i1, DATA_ADDR_3, 0x04;
loadsym p4, DATA_ADDR_4, 0x06;
loadsym p5, DATA_ADDR_5, 0x08;
loadsym fp, DATA_ADDR_6, 0x0a;
loadsym i3, DATA_ADDR_7, 0x0c;
P3 = I1; SP = I3;
W [ P1 ] = R1.L;
W [ P2 ] = R2.L;
W [ P3 ] = R3.L;
W [ P4 ] = R4.L;
W [ P5 ] = R5.L;
W [ SP ] = R6.L;
W [ FP ] = R0.L;
R6.L = W [ P1 ];
R5.L = W [ P2 ];
R4.L = W [ P3 ];
R3.L = W [ P4 ];
R2.L = W [ P5 ];
R0.L = W [ SP ];
R1.L = W [ FP ];
CHECKREG r0, 0x600FB006;
CHECKREG r1, 0x700E5000;
CHECKREG r2, 0x800DA005;
CHECKREG r3, 0x900C9004;
CHECKREG r4, 0xA00B8003;
CHECKREG r5, 0xB00A7002;
CHECKREG r6, 0xC0096001;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x0c;
loadsym p2, DATA_ADDR_2, 0x0a;
loadsym i1, DATA_ADDR_3, 0x08;
loadsym p4, DATA_ADDR_4, 0x06;
loadsym p5, DATA_ADDR_5, 0x04;
loadsym fp, DATA_ADDR_6, 0x02;
loadsym i3, DATA_ADDR_7, 0x00;
P3 = I1; SP = I3;
W [ P1 ] = R2.L;
W [ P2 ] = R3.L;
W [ P3 ] = R4.L;
W [ P4 ] = R5.L;
W [ P5 ] = R6.L;
W [ SP ] = R7.L;
W [ FP ] = R1.L;
R1.L = W [ P1 ];
R2.L = W [ P2 ];
R3.L = W [ P3 ];
R4.L = W [ P4 ];
R5.L = W [ P5 ];
R6.L = W [ SP ];
R0.L = W [ FP ];
CHECKREG r0, 0x105F60A1;
CHECKREG r1, 0x204E70A2;
CHECKREG r2, 0x300380A3;
CHECKREG r3, 0x402C90A4;
CHECKREG r4, 0x501BA0A5;
CHECKREG r5, 0x600AB0A6;
CHECKREG r6, 0x7019C0A7;
// initial values
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x10;
loadsym p2, DATA_ADDR_2, 0x02;
loadsym i1, DATA_ADDR_3, 0x00;
loadsym p4, DATA_ADDR_4, 0x08;
loadsym p5, DATA_ADDR_5, 0x04;
loadsym fp, DATA_ADDR_6, 0x06;
loadsym i3, DATA_ADDR_7, 0x02;
P3 = I1; SP = I3;
W [ P1 ] = R5.L;
W [ P2 ] = R6.L;
W [ P3 ] = R7.L;
W [ P4 ] = R0.L;
W [ P5 ] = R1.L;
W [ SP ] = R2.L;
W [ FP ] = R3.L;
R5.L = W [ P1 ];
R4.L = W [ P2 ];
R3.L = W [ P3 ];
R2.L = W [ P4 ];
R1.L = W [ P5 ];
R0.L = W [ SP ];
R6.L = W [ FP ];
CHECKREG r0, 0x10BF70B2;
CHECKREG r1, 0x20BE60B1;
CHECKREG r2, 0x30BD50B0;
CHECKREG r3, 0x40BCC0B7;
CHECKREG r4, 0x55BBB0B6;
CHECKREG r5, 0x60BAA0B5;
CHECKREG r6, 0x70B980B3;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 9,363
|
sim/testsuite/bfin/se_kill_wbbr.S
|
//Original:/proj/frio/dv/testcases/seq/se_kill_wbbr/se_kill_wbbr.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Load RETS
LD32_LABEL(r0, USER_CODE);
RETS = R0;
// Return to Supervisor Code
RAISE 2;
RAISE 5;
RAISE 6;
RAISE 7;
RAISE 8;
RAISE 9;
RAISE 10;
RAISE 11;
RAISE 12;
RAISE 13;
RAISE 14;
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
IF !CC JUMP 2;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
NOP;
IF !CC JUMP 2;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
CSYNC;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
NOP;
CSYNC;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
SSYNC;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
NOP;
SSYNC;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
NOP;
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
NOP;
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
RTI;
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
EXCPT 0x5;
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_2 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_2 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.section MEM_(DATA_ADDR_2 + 0x110) //.data 0x00F00210,"aw"
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 9,029
|
sim/testsuite/bfin/c_ldstiifp_ld_dreg.s
|
//Original:testcases/core/c_ldstiifp_ld_dreg/c_ldstiifp_ld_dreg.dsp
// Spec Reference: c_ldstiifp load dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
P1 = 0x0000;
P2 = 0x0004;
P3 = 0x0004;
P4 = 0x0000;
P5 = 0x0000;
SP = 0x0000;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0xc8;
P3 = I1; SP = I3;
r0 = [ fp + 0 ];
R1 = [ FP + 4 ];
R2 = [ FP + 8 ];
R3 = [ FP + 12 ];
R4 = [ FP + 16 ];
R5 = [ FP + 20 ];
R6 = [ FP + 24 ];
R7 = [ FP + 28 ];
CHECKREG r0, 0x86878889;
CHECKREG r1, 0x80818283;
CHECKREG r2, 0x84858687;
CHECKREG r3, 0x01020304;
CHECKREG r4, 0x05060708;
CHECKREG r5, 0x09101112;
CHECKREG r6, 0x14151617;
R0 = [ FP + 32 ];
R1 = [ FP + 36 ];
R2 = [ FP + 40 ];
R3 = [ FP + 44 ];
R4 = [ FP + 48 ];
R5 = [ FP + 52 ];
R7 = [ FP + 56 ];
CHECKREG r0, 0x22232425;
CHECKREG r1, 0x26272829;
CHECKREG r2, 0x30313233;
CHECKREG r3, 0x34353637;
CHECKREG r4, 0x38394041;
CHECKREG r5, 0x42434445;
CHECKREG r6, 0x14151617;
R0 = [ FP + 56 ];
R1 = [ FP + 60 ];
R2 = [ FP + 64 ];
R3 = [ FP + 68 ];
R4 = [ FP + 72 ];
R5 = [ FP + 76 ];
R6 = [ FP + 80 ];
CHECKREG r0, 0x46474849;
CHECKREG r1, 0x50515253;
CHECKREG r2, 0x54555657;
CHECKREG r3, 0x58596061;
CHECKREG r4, 0x62636465;
CHECKREG r5, 0x66676869;
CHECKREG r6, 0x74555657;
R0 = [ FP + 84 ];
R1 = [ FP + 88 ];
R2 = [ FP + 92 ];
R3 = [ FP + 96 ];
R4 = [ FP + 100 ];
R5 = [ FP + 104 ];
R6 = [ FP + 108 ];
CHECKREG r0, 0x78596067;
CHECKREG r1, 0x72636467;
CHECKREG r2, 0x76676867;
CHECKREG r3, 0x20212223;
CHECKREG r4, 0x24252627;
CHECKREG r5, 0x28292A2B;
CHECKREG r6, 0x2C2D2E2F;
R0 = [ FP + 112 ];
R1 = [ FP + 116 ];
R2 = [ FP + 120 ];
R3 = [ FP + 124 ];
R4 = [ FP + 128 ];
R5 = [ FP + -4 ];
R6 = [ FP + -8 ];
CHECKREG r0, 0x30313233;
CHECKREG r1, 0x34353637;
CHECKREG r2, 0x38393A3B;
CHECKREG r3, 0x3C3D3E3F;
CHECKREG r4, 0x91929394;
CHECKREG r5, 0x82838485;
CHECKREG r6, 0x74757677;
R0 = [ FP + -12 ];
R1 = [ FP + -16 ];
R2 = [ FP + -20 ];
R3 = [ FP + -24 ];
R4 = [ FP + -28 ];
R5 = [ FP + -32 ];
R6 = [ FP + -36 ];
CHECKREG r0, 0x99717273;
CHECKREG r1, 0x55667788;
CHECKREG r2, 0x11223344;
CHECKREG r3, 0x1C1D1E1F;
CHECKREG r4, 0x18191A1B;
CHECKREG r5, 0x14151617;
CHECKREG r6, 0x10111213;
R0 = [ FP + -40 ];
R1 = [ FP + -44 ];
R2 = [ FP + -48 ];
R3 = [ FP + -64 ];
R4 = [ FP + -88 ];
R5 = [ FP + -96 ];
R6 = [ FP + -128 ];
CHECKREG r0, 0x0C0D0E0F;
CHECKREG r1, 0x08090A0B;
CHECKREG r2, 0x04050607;
CHECKREG r3, 0x78596067;
CHECKREG r4, 0x50515253;
CHECKREG r5, 0x42434445;
CHECKREG r6, 0x09101112;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 2,538
|
sim/testsuite/bfin/s30.s
|
// Test signbits40
# mach: bfin
.include "testutils.inc"
start
// positive value in accum, smaller than 1.0
A1 = A0 = 0;
R0.L = 0xffff;
R0.H = 0x0000;
A0.w = R0;
R0.L = 0x0000;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0x8000 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
// neg value in accum, larger than -1.0
A1 = A0 = 0;
R0.L = 0x0000;
R0.H = 0xffff;
A0.w = R0;
R0.L = 0x00ff;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff );
// positive value in accum, larger than 1.0
A1 = A0 = 0;
R0.L = 0xffff;
R0.H = 0xffff;
A0.w = R0;
R0.L = 0x000f;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
// negative value in accum, smaller than -1.0
A1 = A0 = 0;
R0.L = 0x0000;
R0.H = 0x0000;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff );
// no normalization
A1 = A0 = 0;
R0.L = 0xfffa;
R0.H = 0x7fff;
A0.w = R0;
R0.L = 0x0000;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0xfffa );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
// no normalization (-1.0)
A1 = A0 = 0;
R0.L = 0x0000;
R0.H = 0x8000;
A0.w = R0;
R0.L = 0x00ff;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff );
// norm by 1
A1 = A0 = 0;
R0.L = 0x0000;
R0.H = 0x8000;
A0.w = R0;
R0.L = 0x0000;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x4000 ); DBGA ( R4.L , 0x0000 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
// norm by 1
A1 = A0 = 0;
R0.L = 0x0000;
R0.H = 0x0000;
A0.w = R0;
R0.L = 0x00ff;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff );
pass
|
stsp/binutils-ia16
| 6,911
|
sim/testsuite/bfin/random_0022.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2090c600 | _VS | _AC1 | _AQ | _CC | _AN);
dmm32 A0.w, 0xf041e418;
dmm32 A0.x, 0xffffffff;
imm32 R4, 0x51296cc2;
imm32 R7, 0xca05cb74;
R4.L = (A0 += R7.H * R4.L) (TFU);
checkreg R4, 0x5129ffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x2090c600 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x68508090 | _VS | _AV0S | _AC1 | _AC0_COPY);
dmm32 A1.w, 0xf934c2ea;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0x4c8c85a2;
imm32 R1, 0x13507fff;
imm32 R7, 0x1bd0df6a;
R0.H = (A1 += R7.L * R1.L) (TFU);
checkreg R0, 0xffff85a2;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x68508090 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x54e0c200 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0xed4a5c88;
dmm32 A0.x, 0xffffffff;
imm32 R1, 0x1332a428;
imm32 R4, 0x59fd2452;
imm32 R6, 0x001fffc3;
R4.L = (A0 += R1.H * R6.L) (TFU);
checkreg R4, 0x59fdffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x54e0c200 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x70500000 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN);
dmm32 A0.w, 0xb959adf4;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0xffc20000;
imm32 R4, 0x9b83ffff;
R0.L = (A0 += R4.L * R4.H) (TFU);
checkreg R0, 0xffc2ffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x70500000 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x58f04890 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN);
dmm32 A0.w, 0xfd1277cc;
dmm32 A0.x, 0xffffffff;
imm32 R5, 0xfffdffe2;
imm32 R7, 0x1a9bcac8;
R5.L = (A0 += R5.H * R7.L) (TFU);
checkreg R5, 0xfffdffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x58f04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x2840ce90 | _VS | _AV0S | _AC1 | _AC0 | _AC0_COPY);
dmm32 A1.w, 0x1543f138;
dmm32 A1.x, 0xffffffce;
imm32 R3, 0xf4620000;
imm32 R4, 0x80008000;
imm32 R7, 0x0d156000;
R4.H = (A1 -= R3.L * R7.L) (M, TFU);
checkreg R4, 0x80008000;
checkreg A1.w, 0x1543f138;
checkreg A1.x, 0xffffffce;
checkreg ASTAT, (0x2840ce90 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x04000c90 | _AV0S | _AC0 | _AC0_COPY | _AN);
dmm32 A1.w, 0x7c7b42a9;
dmm32 A1.x, 0x00000027;
imm32 R2, 0x28454c31;
imm32 R5, 0xf220f1b0;
imm32 R6, 0x257ab18b;
R2.H = (A1 -= R5.L * R6.L) (M, TFU);
checkreg R2, 0x7fff4c31;
checkreg A1.w, 0x86685819;
checkreg A1.x, 0x00000027;
checkreg ASTAT, (0x04000c90 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x6810ce80 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x00008000;
imm32 R6, 0x5857bcbe;
R6.H = (A1 = R6.L * R0.L) (M, TFU);
checkreg R6, 0xde5fbcbe;
checkreg A1.w, 0xde5f0000;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x6810ce80 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN);
dmm32 ASTAT, (0x78c00c80 | _VS | _V | _AC0 | _V_COPY | _AN);
dmm32 A1.w, 0x63391186;
dmm32 A1.x, 0x0000005e;
imm32 R2, 0x34a8b6ef;
imm32 R7, 0x7c8142e2;
R7.H = (A1 = R2.L * R2.H) (M, TFU);
checkreg R7, 0xf0f842e2;
checkreg A1.w, 0xf0f898d8;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x78c00c80 | _VS | _AC0 | _AN);
dmm32 ASTAT, (0x70704410 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x3fff0001;
dmm32 A1.x, 0x00000000;
imm32 R0, 0xffffffff;
imm32 R7, 0x80007fff;
R7.H = (A1 = R0.L * R7.L) (M, TFU);
checkreg R7, 0xffff7fff;
checkreg A1.w, 0xffff8001;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x70704410 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x00b08610 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0xe75e6c55;
dmm32 A1.x, 0xffffffff;
imm32 R1, 0x5073b60d;
imm32 R3, 0x1c5eecaf;
R1.H = (A1 = R3.L * R3.H) (M, TFU);
checkreg R1, 0xfddcb60d;
checkreg A1.w, 0xfddc0c42;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x00b08610 | _VS | _AV1S | _AV0S | _AV0 | _AQ | _AC0_COPY | _AN);
dmm32 ASTAT, (0x00304690 | _AV1 | _AV0S | _AV0 | _AQ | _AZ);
dmm32 A1.w, 0x2ef1b58e;
dmm32 A1.x, 0xffffffd7;
imm32 R3, 0x37807856;
imm32 R4, 0x2cd7d02c;
imm32 R5, 0x4435ba51;
R4.H = (A1 -= R3.L * R5.L) (M, TFU);
checkreg R4, 0x8000d02c;
checkreg A1.w, 0xd75d2658;
checkreg A1.x, 0xffffffd6;
checkreg ASTAT, (0x00304690 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AZ);
dmm32 ASTAT, (0x74c0c600 | _VS | _AV1 | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0x4325067d;
dmm32 A1.x, 0xffffffee;
imm32 R0, 0x35ca7288;
imm32 R5, 0x5ec6e257;
R0.H = (A1 += R0.L * R5.H) (M, TFU);
checkreg R0, 0x80007288;
checkreg A1.w, 0x6d8b8bad;
checkreg A1.x, 0xffffffee;
checkreg ASTAT, (0x74c0c600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x50704690 | _VS | _AQ);
dmm32 A1.w, 0xd0cea2a8;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0x11b4e24e;
imm32 R2, 0xecd6793c;
imm32 R7, 0x329c2dd6;
R0.H = (A1 -= R7.L * R2.L) (M, TFU);
checkreg R0, 0xbb19e24e;
checkreg A1.w, 0xbb19be80;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x50704690 | _VS | _AQ);
dmm32 ASTAT, (0x10d08000 | _VS | _AC1 | _AN);
dmm32 A1.w, 0x32dd86a1;
dmm32 A1.x, 0xffffffd7;
imm32 R1, 0xb2310000;
imm32 R3, 0xd63992d2;
imm32 R5, 0x2b93b27f;
R5.H = (A1 += R3.L * R1.L) (M, TFU);
checkreg R5, 0x8000b27f;
checkreg A1.w, 0x32dd86a1;
checkreg A1.x, 0xffffffd7;
checkreg ASTAT, (0x10d08000 | _VS | _V | _AC1 | _V_COPY | _AN);
dmm32 ASTAT, (0x3010c600 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0xf99eabd6;
dmm32 A1.x, 0xffffffff;
imm32 R2, 0x0c196618;
imm32 R5, 0x00008000;
imm32 R6, 0x6617ffff;
R5.H = (A1 -= R6.L * R2.L) (M, TFU);
checkreg R5, 0xf99f8000;
checkreg A1.w, 0xf99f11ee;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x3010c600 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _AC0_COPY);
dmm32 ASTAT, (0x30f0ca80 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AN);
dmm32 A0.w, 0x74ea7d56;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0x29abffff;
imm32 R2, 0xade1ffff;
imm32 R7, 0x20ada3b8;
R0.L = (A0 += R2.L * R7.L) (TFU);
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x30f0ca80 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AN);
dmm32 ASTAT, (0x48608210 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN);
dmm32 A0.w, 0x120f0000;
dmm32 A0.x, 0xffffffff;
imm32 R3, 0xfeacf0c4;
R3.L = (A0 += R3.H * R3.H) (TFU);
checkreg R3, 0xfeacffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x48608210 | _VS | _V | _AV1S | _AV0S | _AV0 | _CC | _V_COPY | _AN);
pass
|
stsp/binutils-ia16
| 6,225
|
sim/testsuite/bfin/c_dsp32mult_dr_is.s
|
//Original:/testcases/core/c_dsp32mult_dr_is/c_dsp32mult_dr_is.dsp
// Spec Reference: dsp32mult single dr is
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467028;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (ISS2);
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (ISS2);
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (ISS2);
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (ISS2);
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (ISS2);
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (ISS2);
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (ISS2);
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (ISS2);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF8000;
CHECKREG r2, 0x80007FFF;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x7FFF8000;
CHECKREG r7, 0x7FFF7FFF;
imm32 r0, 0x9923a635;
imm32 r1, 0x6f995137;
imm32 r2, 0x1324b735;
imm32 r3, 0x99060037;
imm32 r4, 0x809bcd39;
imm32 r5, 0xb0a99f3b;
imm32 r6, 0xa00c093d;
imm32 r7, 0x12467093;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (ISS2);
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (ISS2);
R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (ISS2);
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (ISS2);
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (ISS2);
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (ISS2);
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (ISS2);
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (ISS2);
CHECKREG r0, 0x80008000;
CHECKREG r1, 0x7FFF7FFF;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x80008000;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x80007FFF;
CHECKREG r7, 0x80008000;
imm32 r0, 0x19235655;
imm32 r1, 0xc9ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x0a060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00a005d;
imm32 r7, 0x1246a05f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (ISS2);
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (ISS2);
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (ISS2);
R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (ISS2);
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (ISS2);
R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (ISS2);
R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (ISS2);
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (ISS2);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF8000;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x80008000;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x7FFF7FFF;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xe0060066;
imm32 r4, 0x9eab9d69;
imm32 r5, 0x10ecef6b;
imm32 r6, 0x800ee06d;
imm32 r7, 0x12467e6f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (ISS2);
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (ISS2);
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (ISS2);
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (ISS2);
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (ISS2);
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (ISS2);
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (ISS2);
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (ISS2);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x80008000;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x7FFF7FFF;
CHECKREG r6, 0x7FFF7FFF;
CHECKREG r7, 0x7FFF7FFF;
// mix order
imm32 r0, 0xac23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13c46705;
imm32 r3, 0x00060007;
imm32 r4, 0x90accd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000cc00d;
imm32 r7, 0x1246fc0f;
R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (ISS2);
R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (ISS2);
R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (ISS2);
R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (ISS2);
R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (ISS2);
R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (ISS2);
R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (ISS2);
R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (ISS2);
CHECKREG r0, 0x7FFF8000;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x80008000;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x80008000;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x80007FFF;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0xdd246905;
imm32 r3, 0x00d6d007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10aceddb;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (ISS2);
R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (ISS2);
R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (ISS2);
R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (ISS2);
R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (ISS2);
R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (ISS2);
R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (ISS2);
R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (ISS2);
CHECKREG r0, 0x80007FFF;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x80007FFF;
CHECKREG r3, 0x80007FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x80007FFF;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x7FFF8000;
imm32 r0, 0xfb235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13f46705;
imm32 r3, 0x000f0007;
imm32 r4, 0x90abfd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c00fd;
imm32 r7, 0x1246700f;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (ISS2);
R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (ISS2);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (ISS2);
R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (ISS2);
R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (ISS2);
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (ISS2);
R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (ISS2);
R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (ISS2);
CHECKREG r0, 0x7FFF8000;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x80008000;
CHECKREG r4, 0x80008000;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x80007FFF;
imm32 r0, 0xab2d5675;
imm32 r1, 0xcfbad127;
imm32 r2, 0x13246d05;
imm32 r3, 0x000600d7;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a9efdb;
imm32 r6, 0x000c500d;
imm32 r7, 0x1246760f;
R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (ISS2);
R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (ISS2);
R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (ISS2);
R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (ISS2);
R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (ISS2);
R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (ISS2);
R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (ISS2);
R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (ISS2);
CHECKREG r0, 0x80008000;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x80008000;
CHECKREG r4, 0x80008000;
CHECKREG r5, 0x7FFF7FFF;
CHECKREG r6, 0x14287FFF;
CHECKREG r7, 0x80007FFF;
pass
|
stsp/binutils-ia16
| 1,240
|
sim/testsuite/bfin/c_dsp32shiftim_ahh.s
|
//Original:/testcases/core/c_dsp32shiftim_ahh/c_dsp32shiftim_ahh.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: ashift / ashift
imm32 r0, 0x01230abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R0 = R0 << 0 (V);
R1 = R1 << 3 (V);
R2 = R2 << 5 (V);
R3 = R3 << 8 (V);
R4 = R4 << 9 (V);
R5 = R5 << 15 (V);
R6 = R6 << 7 (V);
R7 = R7 << 13 (V);
CHECKREG r0, 0x01230ABC;
CHECKREG r1, 0x91A0B3C0;
CHECKREG r2, 0x68A0F120;
CHECKREG r3, 0x56009A00;
CHECKREG r4, 0xCE005600;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0xC480E680;
CHECKREG r7, 0x4000C000;
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7 = R0 >>> 1 (V);
R0 = R1 >>> 8 (V);
R1 = R2 >>> 14 (V);
R2 = R3 >>> 15 (V);
R3 = R4 >>> 11 (V);
R4 = R5 >>> 4 (V);
R5 = R6 >>> 9 (V);
R6 = R7 >>> 6 (V);
CHECKREG r0, 0x00120056;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x0008FFF1;
CHECKREG r4, 0x0567F9AB;
CHECKREG r5, 0x0033FFD5;
CHECKREG r6, 0x00020000;
CHECKREG r7, 0x00910000;
pass
|
stsp/binutils-ia16
| 2,946
|
sim/testsuite/bfin/c_dspldst_ld_drhi_i.s
|
//Original:/testcases/core/c_dspldst_ld_drhi_i/c_dspldst_ld_drhi_i.dsp
// Spec Reference: c_dspldst ld_drhi_i
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
// Load upper half of Dregs
R0.H = W [ I0 ];
R1.H = W [ I1 ];
R2.H = W [ I2 ];
R3.H = W [ I3 ];
R4.H = W [ I0 ];
R5.H = W [ I1 ];
R6.H = W [ I2 ];
R7.H = W [ I3 ];
CHECKREG r0, 0x02030000;
CHECKREG r1, 0x22230000;
CHECKREG r2, 0x42430000;
CHECKREG r3, 0x62630000;
CHECKREG r4, 0x02030000;
CHECKREG r5, 0x22230000;
CHECKREG r6, 0x42430000;
CHECKREG r7, 0x62630000;
R1.H = W [ I0 ];
R2.H = W [ I1 ];
R3.H = W [ I2 ];
R4.H = W [ I3 ];
R5.H = W [ I0 ];
R6.H = W [ I1 ];
R7.H = W [ I2 ];
R0.H = W [ I3 ];
CHECKREG r0, 0x62630000;
CHECKREG r1, 0x02030000;
CHECKREG r2, 0x22230000;
CHECKREG r3, 0x42430000;
CHECKREG r4, 0x62630000;
CHECKREG r5, 0x02030000;
CHECKREG r6, 0x22230000;
CHECKREG r7, 0x42430000;
R2.H = W [ I0 ];
R3.H = W [ I1 ];
R4.H = W [ I2 ];
R5.H = W [ I3 ];
R6.H = W [ I0 ];
R7.H = W [ I1 ];
R0.H = W [ I2 ];
R1.H = W [ I3 ];
CHECKREG r0, 0x42430000;
CHECKREG r1, 0x62630000;
CHECKREG r2, 0x02030000;
CHECKREG r3, 0x22230000;
CHECKREG r4, 0x42430000;
CHECKREG r5, 0x62630000;
CHECKREG r6, 0x02030000;
CHECKREG r7, 0x22230000;
R3.H = W [ I0 ];
R4.H = W [ I1 ];
R5.H = W [ I2 ];
R6.H = W [ I3 ];
R7.H = W [ I0 ];
R0.H = W [ I1 ];
R1.H = W [ I2 ];
R2.H = W [ I3 ];
CHECKREG r0, 0x22230000;
CHECKREG r1, 0x42430000;
CHECKREG r2, 0x62630000;
CHECKREG r3, 0x02030000;
CHECKREG r4, 0x22230000;
CHECKREG r5, 0x42430000;
CHECKREG r6, 0x62630000;
CHECKREG r7, 0x02030000;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 3,583
|
sim/testsuite/bfin/a0shift.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
// 0xfffffe371c
r0 = 0;
r1 = 0;
r2 = 0;
r3 = 0;
r4 = 0;
r5 = 0;
r6 = 0;
r7 = 0;
a1 = a0 =0;
astat = R0;
R6.L = 0x8000;
R5.H = 0x8000;
// load acc with values;
R0.L = 0xc062;
R0.H = 0xffee;
A0.w = R0;
R0.L = 0xc52c;
A0.x = R0;
R0.L = 0x8d10;
R0.H = 0x34c;
A1.w = R0;
R0.L = 0xe10c;
A1.x = R0;
// load regs with values;
R0.L = 0xe844;
R0.H = 0x4aba;
R1.L = 0xa294;
R1.H = 0x52ea;
R2.L = 0xafda;
R2.H = 0x5c32;
// end load regs and acc;
R0.H = (A1 = R5.L * R6.H), R0.L = (A0 += R5.L * R6.H) (FU);
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY);
CHECKREG R0, 0xffff;
R0 = A1.w
CHECKREG R0, 0;
R0 = A1.x
CHECKREG R0, 0;
R0 = A0.w
CHECKREG R0, 0xffeec062;
R0 = A0.x
CHECKREG R0, 0x2c;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY);
R4 = R6 +|- R5 , R3 = R6 -|+ R5;
CHECKREG R3, 0x80008000;
CHECKREG R4, 0x80008000;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN);
A1 = R7.L * R2.L (M), A0 -= R7.L * R2.H (IS);
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN);
R7.H = R1.H * R3.L (TFU);
CHECKREG R7, 0x29750000;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R7.H = ( A1 -= R2.L * R5.H ), A0 = R2.L * R5.H;
CHECKREG R7, 0xafda0000;
R0 = A1.w
CHECKREG R0, 0xafda0000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0x50260000;
R0 = A0.x
CHECKREG R0, 0x0;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R3 = R7.L * R6.H, R2 = R7.L * R6.H (IS);
CHECKREG R3, 0;
CHECKREG R2, 0;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R1.H = (A1 += R7.L * R4.H) (M), R1.L = (A0 = R7.H * R4.H) (FU);
CHECKREG R1, 0xafda57ed;
P0 = ASTAT;
R0 = A1.w
CHECKREG R0, 0xafda0000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0x57ed0000;
R0 = A0.x
CHECKREG R0, 0x0;
CHECKREG P0, (_VS|_AN);
R3 = R6.H * R5.L (FU);
CHECKREG R3, 0;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R5.H = ( A1 += R3.L * R1.L ) (M), A0 -= R3.H * R1.H (ISS2);
CHECKREG R5, 0x80000000;
R0 = A1.w
CHECKREG R0, 0xafda0000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0x57ed0000;
R0 = A0.x
CHECKREG R0, 0x0;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN);
R3 = R3 +|- R5 , R6 = R3 -|+ R5 (CO);
CHECKREG R3, 0x80000000;
CHECKREG R6, 0x00008000;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
R7 = ( A1 += R4.L * R1.L ) (M), R6 = ( A0 += R4.L * R1.H );
R0 = A1.w
CHECKREG R0, 0x83e38000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0xa8130000;
R0 = A0.x
CHECKREG R0, 0x0;
CHECKREG R6, 0x7fffffff
CHECKREG R7, 0x83e38000
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
IF CC P2 = R1;
R2.H = (A1 = R7.L * R5.H) (M), R2.L = (A0 = R7.L * R5.H) (ISS2);
CHECKREG R2, 0x80007fff
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
R3.H = R4.H * R2.H, R3.L = R4.L * R2.L (T);
CHECKREG R3, 0x7fff8001
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
R7 = ( A1 = R7.H * R1.H ) (M), A0 -= R7.H * R1.H (FU);
CHECKREG R7, 0xaabe7c4e
P0 = ASTAT;
CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ);
R0.H = R7.L * R4.H (M), R0.L = R7.L * R4.H (TFU);
CHECKREG R0, 0x3e273e27
P0 = ASTAT;
CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ);
R5 = ( A1 = R7.L * R7.L ), R4 = ( A0 -= R7.H * R7.H ) (ISS2);
CHECKREG R5, 0x78b74f88
CHECKREG R4, 0xc73635f8
R0 = A1.w
CHECKREG R0, 0x3c5ba7c4;
R0 = A1.x
CHECKREG R0, 0x0;
R0 = A0.w
CHECKREG R0, 0xe39b1afc;
R0 = A0.x
CHECKREG R0, 0xffffffff;
R0 = ASTAT;
CHECKREG r0, (_VS|_AV0S|_AZ|_AN);
A0 = A0 >> 2;
R0 = ASTAT;
checkreg r0, (_VS|_AV0S);
R0 = A0.x;
DBGA (R0.L, 0x3f);
R0 = A0.w;
checkreg r0, 0xF8E6C6BF;
pass
|
stsp/binutils-ia16
| 1,709
|
sim/testsuite/bfin/c_cc_flagdreg_mvbrsft.s
|
//Original:/testcases/core/c_cc_flagdreg_mvbrsft/c_cc_flagdreg_mvbrsft.dsp
// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00740088;
imm32 r5, 0x609950aa;
imm32 r6, 0x20bb06cc;
imm32 r7, 0xd90e108f;
ASTAT = R0;
CC = R1; // cc2dreg
IF CC R1 = R3; // ccmov
CC = ! CC; // cc2dreg
IF CC R3 = R2; // ccmov
CC = R0 < R1; // ccflag
IF CC R4 = R5; // ccmov
CC = R2 == R3;
IF CC R4 = R5; // ccmov
CC = R0; // cc2dreg
IF !CC JUMP LABEL1; // branch on
CC = ! CC;
IF !CC JUMP LABEL2 (BP); // branch on
LABEL1:
R6 = R0 + R2;
JUMP.S END;
LABEL2:
R7 = R5 - R3;
CC = R0 < R1; // ccflag
IF CC JUMP END (BP); // branch on
R4 = R5 + R7;
END:
CHECKREG r0, 0xA08D2311;
CHECKREG r1, 0x07300007;
CHECKREG r2, 0x62B61557;
CHECKREG r3, 0x07300007;
CHECKREG r4, 0x609950AA;
CHECKREG r5, 0x609950AA;
CHECKREG r6, 0x20BB06CC;
CHECKREG r7, 0x596950A3;
imm32 r0, 0x408d2711;
imm32 r1, 0x15124040;
imm32 r2, 0x62661557;
imm32 r3, 0x073b0007;
imm32 r4, 0x01f49088;
imm32 r5, 0x6e2959aa;
imm32 r6, 0xa0b506cc;
imm32 r7, 0x00000002;
CC = R1; // cc2dreg
R2 = ROT R2 BY 1; // dsp32shiftim_rot
CC = ! CC; // cc2dreg
R3 = ROT R0 BY -3; // dsp32shiftim_rot
CC = R0 < R1; // ccflag
R6 = ROT R4 BY 5; // dsp32shiftim_rot
CC = R2 == R3;
IF CC R4 = R5; // ccmov
CC = R0; // cc2dreg
R7 = ROT R6 BY R7.L;
CHECKREG r0, 0x408D2711;
CHECKREG r1, 0x15124040;
CHECKREG r2, 0xC4CC2AAF;
CHECKREG r3, 0x6811A4E2;
CHECKREG r4, 0x01F49088;
CHECKREG r5, 0x6E2959AA;
CHECKREG r6, 0x3E921100;
CHECKREG r7, 0xFA484402;
pass
|
stsp/binutils-ia16
| 1,803
|
sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft.s
|
//Original:/testcases/core/c_cc_regmvlogi_mvbrsft/c_cc_regmvlogi_mvbrsft.dsp
// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000020; // cc=1
imm32 r1, 0x00000000; // cc=0
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00740088;
imm32 r5, 0x609950aa;
imm32 r6, 0x20bb06cc;
imm32 r7, 0xd90e108f;
ASTAT = R0; // cc=1 REGMV
IF CC R1 = R3; // ccmov
ASTAT = R1; // cc=0 REGMV
IF CC R3 = R2; // ccmv
CC = R0 < R1; // ccflag
IF CC R4 = R5; // ccmv
CC = ! BITTST( R0 , 4 ); // cc = 0
IF CC R4 = R5; // ccmv
CC = BITTST ( R1 , 4 ); // cc = 0
IF !CC JUMP LABEL1; // branch
CC = ! CC;
IF !CC JUMP LABEL2 (BP); // branch
LABEL1:
R6 = R0 + R2;
JUMP.S END;
LABEL2:
R7 = R5 - R3;
CC = R0 < R1; // ccflag
IF CC JUMP END (BP); // branch on
R4 = R5 + R7;
END:
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x07300007;
CHECKREG r2, 0x62B61557;
CHECKREG r3, 0x07300007;
CHECKREG r4, 0x609950AA;
CHECKREG r5, 0x609950AA;
CHECKREG r6, 0x62B61577;
CHECKREG r7, 0xD90E108F;
imm32 r0, 0x00000020;
imm32 r1, 0x00000000;
imm32 r2, 0x62661557;
imm32 r3, 0x073b0007;
imm32 r4, 0x01f49088;
imm32 r5, 0x6e2959aa;
imm32 r6, 0xa0b506cc;
imm32 r7, 0x00000002;
ASTAT = R0; // cc=1 REGMV
R2 = ROT R2 BY 1; // dsp32shiftim_rot
ASTAT = R1; // cc=0 REGMV
R3 = ROT R3 BY 1; // dsp32shiftim_rot
CC = ! BITTST( R0 , 4 ); // cc = 0
R6 = ROT R4 BY 5; // dsp32shiftim_rot
CC = BITTST ( R1 , 4 ); // cc = 0
IF CC R4 = R5; // ccmov
CC = BITTST ( R0 , 4 ); // cc = 1
R7 = ROT R6 BY R7.L;
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xC4CC2AAF;
CHECKREG r3, 0x0E76000E;
CHECKREG r4, 0x01F49088;
CHECKREG r5, 0x6E2959AA;
CHECKREG r6, 0x3E921110;
CHECKREG r7, 0xFA484440;
pass
|
stsp/binutils-ia16
| 6,542
|
sim/testsuite/bfin/c_interr_timer_tscale.S
|
//Original:/proj/frio/dv/testcases/core/c_interr_timer_tscale/c_interr_timer_tscale.dsp
// Spec Reference: interrupt on HW TIMER tscale
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL 0xFFE03000
#endif
#ifndef TPERIOD
#define TPERIOD 0xFFE03004
#endif
#ifndef TSCALE
#define TSCALE 0xFFE03008
#endif
#ifndef TCOUNT
#define TCOUNT 0xFFE0300c
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203c
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0x000FF000
#endif
#ifndef PROGRAM_STACK
#define PROGRAM_STACK 0x000FF100
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000300
#endif
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
// CHECK_INIT(p5, 0x00BFFFFC);
// CHECK_INIT(p5, 0xE0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
LD32(sp, 0x000FF200);
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC;
RAISE 15; // after we RTI, INT 15 should be taken
LD32_LABEL(r7, START);
RETI = r7;
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
//.code 0x200
START :
R7 = 0x0;
R6 = 0x1;
[ -- SP ] = RETI; // Enable Nested Interrupts
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state)
WR_MMR(TPERIOD, 0x00000010, p0, r0);
WR_MMR(TCOUNT, 0x00000002, p0, r0);
WR_MMR(TSCALE, 0x00000001, p0, r0);
CSYNC;
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000010);
RD_MMR(TCOUNT, p0, r3);
CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace -seed 8b8db910
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN)
CSYNC;
RD_MMR(TCOUNT, p0, r4);
CHECKREG(r4, 0x00000000);
RD_MMR(TCNTL, p0, r5);
CHECKREG(r5, 0x0000000B);
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
CHECKREG(r7, 0x00000001);
R7 = 0;
NOP;
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
WR_MMR(TPERIOD, 0x00000010, p0, r0);
WR_MMR(TCOUNT, 0x00000003, p0, r0);
WR_MMR(TSCALE, 0x00000128, p0, r0);
WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer
CSYNC;
NOP;
NOP;
label5: R5.H = 0x7777;
R5.L = 0x7888;
JUMP.S label6;
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
label4: R4.H = 0x5555;
R4.L = 0x6666;
NOP;
JUMP.S label5;
R5.L = 0x2222; // Will be killed
R5.H = 0x2222; // Will be killed
NOP;
label6: R3.H = 0x7999;
R3.L = 0x7aaa;
NOP;
// With auto reload
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000010);
RD_MMR(TCNTL , p0, r3);
CHECKREG(r3, 0x0000000b);
CHECKREG(r7, 0x00000001);
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn ON Timer auto-reload
WR_MMR(TPERIOD, 0x00000020, p0, r0);
WR_MMR(TSCALE, 0x00000003, p0, r0);
WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auto-reload
NOP; NOP;
R7 = 0;
CSYNC;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP;
R1 = 1;
R2 = 1;
R3 = 2;
RD_MMR(TCNTL, p0, r5);
CHECKREG(r5, 0x0000000F);
CC = R1 < R7;
IF CC R2 = R3;
CHECKREG(r2, 0x00000002);
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP; NOP; NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
R7 = R7 + R6;
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
R5 = RETI;
P0 = R5;
JUMP ( P0 );
RTI;
.section MEM_DATA_ADDR_1,"aw"
.space (STACKSIZE);
STACK:
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
|
stsp/binutils-ia16
| 4,342
|
sim/testsuite/bfin/c_dsp32shift_a0alr.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32shift_a0alr/c_dsp32shift_a0alr.dsp
// Spec Reference: dsp32shift a0 ashift, lshift, rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x11140000;
imm32 r1, 0x012C003E;
imm32 r2, 0x81359E24;
imm32 r3, 0x81459E24;
imm32 r4, 0xD159E268;
imm32 r5, 0x51626AF2;
imm32 r6, 0x9176AF36;
imm32 r7, 0xE18BFF86;
R0.L = 0;
A0 = 0;
A0.L = R1.L;
A0.H = R1.H;
A0 = ASHIFT A0 BY R0.L; /* a0 = 0x00000000 */
R2 = A0.w; /* r5 = 0x00000000 */
CHECKREG r2, 0x012C003E;
R1.L = 1;
A0.L = R2.L;
A0.H = R2.H;
A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00000000 */
R3 = A0.w; /* r5 = 0x00000000 */
CHECKREG r3, 0x0258007C;
R2.L = 15;
A0.L = R3.L;
A0.H = R3.H;
A0 = ASHIFT A0 BY R2.L; /* a0 = 0x00000000 */
R4 = A0.w; /* r5 = 0x00000000 */
CHECKREG r4, 0x003E0000;
R3.L = 31;
A0.L = R4.L;
A0.H = R4.H;
A0 = ASHIFT A0 BY R3.L; /* a0 = 0x00000000 */
R5 = A0.w; /* r5 = 0x00000000 */
CHECKREG r5, 0x00000000;
R4.L = -1;
A0.L = R5.L;
A0.H = R5.H;
A0 = ASHIFT A0 BY R4.L; /* a0 = 0x00000000 */
R6 = A0.w; /* r5 = 0x00000000 */
CHECKREG r6, 0x00000000;
R5.L = -16;
A0 = 0;
A0.L = R6.L;
A0.H = R6.H;
A0 = ASHIFT A0 BY R5.L; /* a0 = 0x00000000 */
R7 = A0.w; /* r5 = 0x00000000 */
CHECKREG r7, 0x00000000;
R6.L = -31;
A0.L = R7.L;
A0.H = R7.H;
A0 = ASHIFT A0 BY R6.L; /* a0 = 0x00000000 */
R0 = A0.w; /* r5 = 0x00000000 */
CHECKREG r0, 0x00000000;
R7.L = -32;
A0.L = R0.L;
A0.H = R0.H;
A0 = ASHIFT A0 BY R7.L; /* a0 = 0x00000000 */
R1 = A0.w; /* r5 = 0x00000000 */
CHECKREG r1, 0x00000000;
imm32 r0, 0x12340000;
imm32 r1, 0x028C003E;
imm32 r2, 0x82159E24;
imm32 r3, 0x82159E24;
imm32 r4, 0xD259E268;
imm32 r5, 0x52E26AF2;
imm32 r6, 0x9226AF36;
imm32 r7, 0xE26BFF86;
R0.L = 0;
A0 = 0;
A0.L = R1.L;
A0.H = R1.H;
A0 = LSHIFT A0 BY R0.L; /* a0 = 0x00000000 */
R2 = A0.w; /* r5 = 0x00000000 */
CHECKREG r2, 0x028C003E;
R1.L = 1;
A0.L = R2.L;
A0.H = R2.H;
A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00000000 */
R3 = A0.w; /* r5 = 0x00000000 */
CHECKREG r3, 0x0518007C;
R2.L = 15;
A0.L = R3.L;
A0.H = R3.H;
A0 = LSHIFT A0 BY R2.L; /* a0 = 0x00000000 */
R4 = A0.w; /* r5 = 0x00000000 */
CHECKREG r4, 0x003E0000;
R3.L = 31;
A0.L = R4.L;
A0.H = R4.H;
A0 = LSHIFT A0 BY R3.L; /* a0 = 0x00000000 */
R5 = A0.w; /* r5 = 0x00000000 */
CHECKREG r5, 0x00000000;
R4.L = -1;
A0.L = R5.L;
A0.H = R5.H;
A0 = LSHIFT A0 BY R4.L; /* a0 = 0x00000000 */
R6 = A0.w; /* r5 = 0x00000000 */
CHECKREG r6, 0x00000000;
R5.L = -16;
A0 = 0;
A0.L = R6.L;
A0.H = R6.H;
A0 = LSHIFT A0 BY R5.L; /* a0 = 0x00000000 */
R7 = A0.w; /* r5 = 0x00000000 */
CHECKREG r7, 0x00000000;
R6.L = -31;
A0.L = R7.L;
A0.H = R7.H;
A0 = LSHIFT A0 BY R6.L; /* a0 = 0x00000000 */
R0 = A0.w; /* r5 = 0x00000000 */
CHECKREG r0, 0x00000000;
R7.L = -32;
A0.L = R0.L;
A0.H = R0.H;
A0 = LSHIFT A0 BY R7.L; /* a0 = 0x00000000 */
R1 = A0.w; /* r5 = 0x00000000 */
CHECKREG r1, 0x00000000;
imm32 r0, 0x13340000;
imm32 r1, 0x038C003E;
imm32 r2, 0x83159E24;
imm32 r3, 0x83159E24;
imm32 r4, 0xD359E268;
imm32 r5, 0x53E26AF2;
imm32 r6, 0x9326AF36;
imm32 r7, 0xE36BFF86;
R0.L = 0;
A0 = 0;
A0.L = R1.L;
A0.H = R1.H;
A0 = ROT A0 BY R0.L; /* a0 = 0x00000000 */
R2 = A0.w; /* r5 = 0x00000000 */
CHECKREG r2, 0x038C003E;
R1.L = 1;
A0.L = R2.L;
A0.H = R2.H;
A0 = ROT A0 BY R1.L; /* a0 = 0x00000000 */
R3 = A0.w; /* r5 = 0x00000000 */
CHECKREG r3, 0x0718007C;
R2.L = 15;
A0.L = R3.L;
A0.H = R3.H;
A0 = ROT A0 BY R2.L; /* a0 = 0x00000000 */
R4 = A0.w; /* r5 = 0x00000000 */
CHECKREG r4, 0x003E0001;
R3.L = 31;
A0.L = R4.L;
A0.H = R4.H;
A0 = ROT A0 BY R3.L; /* a0 = 0x00000000 */
R5 = A0.w; /* r5 = 0x00000000 */
CHECKREG r5, 0xE3000F80;
R4.L = -1;
A0.L = R5.L;
A0.H = R5.H;
A0 = ROT A0 BY R4.L; /* a0 = 0x00000000 */
R6 = A0.w; /* r5 = 0x00000000 */
CHECKREG r6, 0x718007C0;
R5.L = -16;
A0.L = R6.L;
A0.H = R6.H;
A0 = ROT A0 BY R5.L; /* a0 = 0x00000000 */
R7 = A0.w; /* r5 = 0x00000000 */
CHECKREG r7, 0x80007180;
R6.L = -31;
A0.L = R7.L;
A0.H = R7.H;
A0 = ROT A0 BY R6.L; /* a0 = 0x00000000 */
R0 = A0.w; /* r5 = 0x00000000 */
CHECKREG r0, 0x01C6001F;
R7.L = -32;
A0.L = R0.L;
A0.H = R0.H;
A0 = ROT A0 BY R7.L; /* a0 = 0x00000000 */
R1 = A0.w; /* r5 = 0x00000000 */
CHECKREG r1, 0x8C003E00;
pass
|
stsp/binutils-ia16
| 5,914
|
sim/testsuite/bfin/c_dsp32alu_rl_m.s
|
//Original:/testcases/core/c_dsp32alu_rl_m/c_dsp32alu_rl_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x55678911;
imm32 r1, 0x2759ab1d;
imm32 r2, 0x34455515;
imm32 r3, 0x46665717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789a51d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.L = R0.L - R0.L (NS);
R1.L = R0.L - R1.H (NS);
R2.L = R0.H - R2.L (NS);
R3.L = R0.H - R3.H (NS);
R4.L = R0.L - R4.L (NS);
R5.L = R0.L - R5.H (NS);
R6.L = R0.H - R6.L (NS);
R7.L = R0.H - R7.H (NS);
CHECKREG r4, 0x567876E5;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x74440052;
CHECKREG r7, 0x8666CF01;
CHECKREG r4, 0x567876E5;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x74440052;
CHECKREG r7, 0x8666CF01;
imm32 r0, 0x44678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x344d5515;
imm32 r3, 0x4666d717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789cc1d;
imm32 r6, 0x74445c15;
imm32 r7, 0x86667c77;
R0.L = R1.L - R0.L (NS);
R1.L = R1.L - R1.H (NS);
R2.L = R1.H - R2.L (NS);
R3.L = R1.H - R3.H (NS);
R4.L = R1.L - R4.L (NS);
R5.L = R1.L - R5.H (NS);
R6.L = R1.H - R6.L (NS);
R7.L = R1.H - R7.H (NS);
CHECKREG r4, 0x5678FA79;
CHECKREG r5, 0x67891C0B;
CHECKREG r6, 0x7444CB74;
CHECKREG r7, 0x8666A123;
CHECKREG r4, 0x5678FA79;
CHECKREG r5, 0x67891C0B;
CHECKREG r6, 0x7444CB74;
CHECKREG r7, 0x8666A123;
imm32 r0, 0xcc678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34c45515;
imm32 r3, 0x466c7717;
imm32 r4, 0x5678c91b;
imm32 r5, 0x6789ac1d;
imm32 r6, 0x74445515;
imm32 r7, 0x866677c7;
R0.L = R2.L - R0.L (NS);
R1.L = R2.L - R1.H (NS);
R2.L = R2.H - R2.L (NS);
R3.L = R2.H - R3.H (NS);
R4.L = R2.L - R4.L (NS);
R5.L = R2.L - R5.H (NS);
R6.L = R2.H - R6.L (NS);
R7.L = R2.H - R7.H (NS);
CHECKREG r4, 0x56781694;
CHECKREG r5, 0x67897826;
CHECKREG r6, 0x7444DFAF;
CHECKREG r7, 0x8666AE5E;
CHECKREG r4, 0x56781694;
CHECKREG r5, 0x67897826;
CHECKREG r6, 0x7444DFAF;
CHECKREG r7, 0x8666AE5E;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.L = R3.L - R0.L (NS);
R1.L = R3.L - R1.H (NS);
R2.L = R3.H - R2.L (NS);
R3.L = R3.H - R3.H (NS);
R4.L = R3.L - R4.L (NS);
R5.L = R3.L - R5.H (NS);
R6.L = R3.H - R6.L (NS);
R7.L = R3.H - R7.H (NS);
CHECKREG r4, 0x567876E5;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x7444F151;
CHECKREG r7, 0x8666C000;
CHECKREG r4, 0x567876E5;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x7444F151;
CHECKREG r7, 0x8666C000;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34e45515;
imm32 r3, 0x466e7717;
imm32 r4, 0x5678e91b;
imm32 r5, 0x6789ae1d;
imm32 r6, 0x744455e5;
imm32 r7, 0x8666777e;
R0.L = R4.L - R0.L (NS);
R1.L = R4.L - R1.H (NS);
R2.L = R4.H - R2.L (NS);
R3.L = R4.H - R3.H (NS);
R4.L = R4.L - R4.L (NS);
R5.L = R4.L - R5.H (NS);
R6.L = R4.H - R6.L (NS);
R7.L = R4.H - R7.H (NS);
CHECKREG r4, 0x56780000;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x74440093;
CHECKREG r7, 0x8666D012;
CHECKREG r4, 0x56780000;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x74440093;
CHECKREG r7, 0x8666D012;
imm32 r0, 0xdd678911;
imm32 r1, 0xd789ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46d67717;
imm32 r4, 0x567d891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x74445d15;
imm32 r7, 0x866677d7;
R0.L = R5.L - R0.L (NS);
R1.L = R5.L - R1.H (NS);
R2.L = R5.H - R2.L (NS);
R3.L = R5.H - R3.H (NS);
R4.L = R5.L - R4.L (NS);
R5.L = R5.L - R5.H (NS);
R6.L = R5.H - R6.L (NS);
R7.L = R5.H - R7.H (NS);
CHECKREG r4, 0x567D5202;
CHECKREG r5, 0x67897394;
CHECKREG r6, 0x74440A74;
CHECKREG r7, 0x8666E123;
CHECKREG r4, 0x567D5202;
CHECKREG r5, 0x67897394;
CHECKREG r6, 0x74440A74;
CHECKREG r7, 0x8666E123;
imm32 r0, 0x85678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x38445515;
imm32 r3, 0x46667717;
imm32 r4, 0x568a891b;
imm32 r5, 0x67a9ab1d;
imm32 r6, 0x744a5515;
imm32 r7, 0x8666aa77;
R0.L = R6.L - R0.L (NS);
R1.L = R6.L - R1.H (NS);
R2.L = R6.H - R2.L (NS);
R3.L = R6.H - R3.H (NS);
R4.L = R6.L - R4.L (NS);
R5.L = R6.L - R5.H (NS);
R6.L = R6.H - R6.L (NS);
R7.L = R6.H - R7.H (NS);
CHECKREG r4, 0x568ACBFA;
CHECKREG r5, 0x67A9ED6C;
CHECKREG r6, 0x744A1F35;
CHECKREG r7, 0x8666EDE4;
CHECKREG r4, 0x568ACBFA;
CHECKREG r5, 0x67A9ED6C;
CHECKREG r6, 0x744A1F35;
CHECKREG r7, 0x8666EDE4;
imm32 r0, 0x35678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x34845515;
imm32 r3, 0x466a7717;
imm32 r4, 0x5678a91b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445b15;
imm32 r7, 0x866677b7;
R0.L = R7.L - R0.L (NS);
R1.L = R7.L - R1.H (NS);
R2.L = R7.H - R2.L (NS);
R3.L = R7.H - R3.H (NS);
R4.L = R7.L - R4.L (NS);
R5.L = R7.L - R5.H (NS);
R6.L = R7.H - R6.L (NS);
R7.L = R7.H - R7.H (NS);
CHECKREG r4, 0x5678CE9C;
CHECKREG r5, 0x6789102E;
CHECKREG r6, 0x74442B51;
CHECKREG r7, 0x86660000;
CHECKREG r4, 0x5678CE9C;
CHECKREG r5, 0x6789102E;
CHECKREG r6, 0x74442B51;
CHECKREG r7, 0x86660000;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R6.L = R2.L - R3.L (S);
R1.L = R4.L - R5.H (S);
R5.L = R7.H - R2.L (S);
R3.L = R0.H - R0.H (S);
R0.L = R3.L - R4.L (S);
R2.L = R5.L - R7.H (S);
R7.L = R6.H - R7.L (S);
R4.L = R1.H - R6.H (S);
CHECKREG r4, 0x5678B345;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0x7444DDFE;
CHECKREG r7, 0x8666FCCD;
CHECKREG r4, 0x5678B345;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0x7444DDFE;
CHECKREG r7, 0x8666FCCD;
imm32 r0, 0x1d678911;
imm32 r1, 0x27d9ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x466d7717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789dd1d;
imm32 r6, 0x74445515;
imm32 r7, 0x866677d7;
R3.L = R4.L - R0.L (S);
R1.L = R6.L - R3.H (S);
R4.L = R3.H - R2.L (S);
R6.L = R7.H - R1.H (S);
R2.L = R5.L - R4.L (S);
R7.L = R2.L - R7.H (S);
R0.L = R1.H - R6.L (S);
R5.L = R0.H - R5.H (S);
CHECKREG r4, 0x5678F158;
CHECKREG r5, 0x6789B5DE;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x8666655F;
CHECKREG r4, 0x5678F158;
CHECKREG r5, 0x6789B5DE;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x8666655F;
pass
|
stsp/binutils-ia16
| 11,801
|
sim/testsuite/bfin/se_loop_mv2lt_stall.S
|
//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lt_stall/se_loop_mv2lt_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE 0x00000500
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef IMASK
#define IMASK 0xFFE02104
#endif
#ifndef DMEM_CONTROL
#define DMEM_CONTROL 0xFFE00004
#endif
#ifndef DCPLB_ADDR0
#define DCPLB_ADDR0 0xFFE00100
#endif
#ifndef DCPLB_DATA0
#define DCPLB_DATA0 0xFFE00200
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x3 (Z);
P2 = 0x0100 (Z);
P2.H = 0x00f0;
// Loop 0
LD32_LABEL(r0, L0T);
LD32_LABEL(r1, L0B);
LC0 = p1;
LB0 = r1;
R5 = [ P2 ++ ];
LT0 = r0;
L0T:R3 += 4;
R2 += 3;
R4 += 5;
R5 += 6;
R6 += 7;
L0B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L1T);
LD32_LABEL(r1, L1B);
LB0 = r1;
LC0 = p1;
R5 = [ P2 ++ ];
NOP;
LT0 = r0;
L1T:R4 += 5;
R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
L1B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L2T);
LD32_LABEL(r1, L2B);
LB0 = r1;
LC0 = p1;
R5 = [ P2 ++ ];
NOP;
NOP;
LT0 = r0;
L2T:R5 += 6;
R2 += 3;
R3 += 4;
R4 += 5;
R6 += 7;
L2B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L3T);
LD32_LABEL(r1, L3B);
LB0 = r1;
LC0 = p1;
R5 = [ P2 ++ ];
NOP;
NOP;
NOP;
LT0 = r0;
L3T:R2 += 3;
R5 += 6;
R6 += 7;
R3 += 4;
R4 += 5;
L3B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L4T);
LD32_LABEL(r1, L4B);
LB0 = r1;
LC0 = p1;
R5 = [ P2 ++ ];
NOP;
NOP;
NOP;
NOP;
LT0 = r0;
L4T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
L4B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L5T);
LD32_LABEL(r1, L5B);
[ -- SP ] = R0;
SSYNC;
LB0 = r1;
LC0 = p0;
R5 = [ P2 ++ ];
LT0 = [sp++];
L5T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
L5B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M0T);
LD32_LABEL(r1, M0B);
LB1 = r1;
LC1 = p1;
R5 = [ P2 ++ ];
LT1 = r0;
M0T:R3 += 4;
R2 += 3;
R4 += 5;
R5 += 6;
R6 += 7;
M0B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M1T);
LD32_LABEL(r1, M1B);
LB1 = r1;
LC1 = p1;
R5 = [ P2 ++ ];
NOP;
LT1 = r0;
M1T:R4 += 5;
R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
M1B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M2T);
LD32_LABEL(r1, M2B);
LB1 = r1;
LC1 = p1;
R5 = [ P2 ++ ];
NOP;
NOP;
LT1 = r0;
M2T:R5 += 6;
R2 += 3;
R3 += 4;
R4 += 5;
R6 += 7;
M2B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M3T);
LD32_LABEL(r1, M3B);
LB1 = r1;
LC1 = p1;
R5 = [ P2 ++ ];
NOP;
NOP;
NOP;
LT1 = r0;
M3T:R2 += 3;
R5 += 6;
R6 += 7;
R3 += 4;
R4 += 5;
M3B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M4T);
LD32_LABEL(r1, M4B);
LB1 = r1;
LC1 = p1;
R5 = [ P2 ++ ];
NOP;
NOP;
NOP;
NOP;
LT1 = r0;
M4T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
M4B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M5T);
LD32_LABEL(r1, M5B);
[ -- SP ] = R0;
SSYNC;
LB1 = r1;
LC1 = p0;
R5 = [ P2 ++ ];
LT1 = [sp++];
M5T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
M5B:R7 += 8;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_0x00F00100,"aw"
.dd 0x01010101;
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
.dd 0x05050505;
.dd 0x06060606;
.dd 0x07070707;
.dd 0x08080808;
.dd 0x09090909;
.dd 0x0a0a0a0a;
.dd 0x0b0b0b0b;
.dd 0x0c0c0c0c;
.dd 0x0d0d0d0d;
.dd 0x0e0e0e0e;
.dd 0x0f0f0f0f;
// Define Kernal Stack
.section MEM_0x00F00210,"aw"
.space (STACKSIZE);
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 6,439
|
sim/testsuite/bfin/a11.S
|
// Test ALU RND RND12 RND20
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
R7 = 0;
ASTAT = R7;
// 7ffffff0
// + 00008000
// -> 7fff0000
R0 = 0xfff0 (Z);
R0.H = 0x7fff;
R7.L = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7fff;
CHECKREG R0, (_VS|_V|_V_COPY);
// 7ffffff0
// + 00008000
// -> 7fff0000
R0.L = 0xfff0;
R0.H = 0x7fff;
R7.H = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7fff7fff;
CHECKREG R0, (_VS|_V|_V_COPY);
// 7ff0fff0
// + 00008000
// -> 7ff10000
R0.L = 0xfff0;
R0.H = 0x7ff0;
R7.L = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7fff7ff1
CHECKREG R0, (_VS);
// 7ff0fff0
// + 00008000
// -> 7ff10000
// 7ff0fff0
// + 8000
// -> 7ff1
R0.L = 0xfff0;
R0.H = 0x7ff0;
R7.H = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7ff17ff1
CHECKREG R0, (_VS);
// fffffff0
// + 00008000
// -> 00000000
R0.L = 0xfff0;
R0.H = 0xffff;
R7.L = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7ff10000;
CHECKREG R0, (_VS|_AZ);
// fffffff0
// + 00008000
// -> 00000000
R0.L = 0xfff0;
R0.H = 0xffff;
R7.H = R0 (RND);
R0 = ASTAT;
DBGA ( R7.H , 0 );
CHECKREG R0, (_VS|_AZ);
// 00fffff0
// + 00008000
// -> 0100
R0.L = 0xfff0;
R0.H = 0x00ff;
R7.L = R0 (RND);
R0 = ASTAT;
DBGA ( R7.L , 0x0100 );
CHECKREG R0, (_VS);
// RND12
// 07ffe000
// + 00000000
// = 07ffe000
// + 00000800
// -> 7ffe
R0.L = 0xe000;
R0.H = 0x07ff;
R1 = 0x0000 (Z);
R1.H = 0x0000;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x7ffe );
CHECKREG R0, (_VS);
// 07ffff00
// + 00000000
// = 07ffff00
// + 00000800
// -> 7fff
R0.L = 0xff00;
R0.H = 0x07ff;
R1.L = 0x0000;
R1.H = 0x0000;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x7fff );
CHECKREG R0, (_VS|_V|_V_COPY);
// 07fffc00
// + 00000f00
// = 08000b00
// + 00000800
// -> 7fff
R0.L = 0xfc00;
R0.H = 0x07ff;
R1.L = 0x0f00;
R1.H = 0x0000;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x7fff );
CHECKREG R0, (_VS|_V|_V_COPY);
// 07ff c000
// + 0000 1000
// = 07ff d000
// + 0000 0800
// -> 7ff d
R0.L = 0xc000;
R0.H = 0x07ff;
R1.L = 0x1000;
R1.H = 0x0000;
_DBG ASTAT;
R7.L = R0 + R1 (RND12);
_DBG ASTAT;
R0 = ASTAT;
_DBG R0;
DBGA ( R7.L , 0x7ffd );
CHECKREG R0, (_VS);
// ffff ffea
// + 07ff fe00
// = 107ff fdea
// + 0000 0800
// -> 7ff f
R0.L = 0xffea;
R0.H = 0xffff;
R1.L = 0xfe00;
R1.H = 0x07ff;
_DBG ASTAT;
R7.L = R0 + R1 (RND12);
_DBG ASTAT;
R0 = ASTAT;
_DBG R0;
DBGA ( R7.L , 0x7fff );
CHECKREG R0, (_VS|_V|_V_COPY);
// Small negative plus small negative should give zero
// ffff ffff
// + ffff ffff
// + 0000 0800
// -> 000 0
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0xffff;
R1.H = 0xffff;
_DBG ASTAT;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
_DBG R0;
DBGA ( R7.L , 0x0000 );
CHECKREG R0, (_VS|_AZ);
// Small negative minus small positive should give zero
// ffff ffff
// + 0000 0001
// - 0000 0800
// -> 000 0
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0x0001;
R1.H = 0x0000;
R7.L = R0 - R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x0000 );
CHECKREG R0, (_VS|_AZ);
// Large positive plus large positive should give maxpos
// 07ff ffff
// + 07ff ffff
// + 0000 0800
// -> 7ff f
R0.L = 0xffff;
R0.H = 0x07ff;
R1.L = 0xffff;
R1.H = 0x07ff;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x7fff );
CHECKREG R0, (_VS|_V|_V_COPY);
// Large negative plus large negative should give maxneg
// 0800 0000
// + 0800 0000
// + 0000 0800
// -> 800 0
R0.L = 0x0000;
R0.H = 0x0800;
R1.L = 0x0000;
R1.H = 0x0800;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x7fff );
CHECKREG R0, (_VS|_V|_V_COPY);
// Large positive minus large negative should give maxpos
// 07ff ffff
// - 0800 0000
// + 0000 0800
// -> 800 0
R0.L = 0xffff;
R0.H = 0x07ff;
R1.L = 0x0000;
R1.H = 0x0800;
R7.L = R0 - R1 (RND12);
R0 = ASTAT;
_DBG ASTAT;
DBGA ( R7.L , 0x0 );
CHECKREG R0, (_VS|_AZ);
// Large negative minus large positive should give maxneg
// 0800 0000
// - 07ff ffff
// + 0000 0800
// -> 800 0
R0.L = 0x0000;
R0.H = 0x0800;
R1.L = 0xffff;
R1.H = 0x07ff;
R7.L = R0 - R1 (RND12);
R0 = ASTAT;
_DBG ASTAT;
DBGA ( R7.L , 0x0000 );
CHECKREG R0, (_VS|_AZ);
// cef4 3ed6
// - 56f4 417a
// + 0000 0800
// -> 800 0
R0.L = 0x3ed6;
R0.H = 0xcef4;
R1.L = 0x417a;
R1.H = 0x56f4;
R7.L = R0 - R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x8000 );
CHECKREG R0, (_VS|_V|_V_COPY|_AN);
// RND20
// 00ff 0000
// + 0000 0000
// + 0008 0000
// ->0010
R0.L = 0x0000;
R0.H = 0x00ff;
R1.L = 0x0000;
R1.H = 0x0000;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0010 );
CHECKREG R0, (_VS);
// 00f0 0000
// + 000f 0000
// + 0008 0000
// ->0010
R0.L = 0x0000;
R0.H = 0x00f0;
R1.L = 0x0000;
R1.H = 0x000f;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0010 );
CHECKREG R0, (_VS);
// 7ff0 0000
// + 0000 0000
// + 0008 0000
// ->07ff
R0.L = 0x0000;
R0.H = 0x7ff0;
R1.L = 0x0000;
R1.H = 0x0000;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x07ff );
CHECKREG R0, (_VS);
// 7fff 0000
// + 0000 0000
// + 0008 0000
// ->0800
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0x0000;
R1.H = 0x0000;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0800 );
CHECKREG R0, (_VS);
// ffff 0000
// + 0000 0000
// + 0008 0000
// ->0000
R0.L = 0x0000;
R0.H = 0xffff;
R1.L = 0x0000;
R1.H = 0x0000;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0000 );
DBGA ( R0.H , 0x0200 );
DBGA ( R0.L , 0x0001 );
// ff00 0000
// + 0010 0000
// + 0008 0000
// ->fff1
R0.L = 0x0000;
R0.H = 0xff00;
R1.L = 0x0000;
R1.H = 0x0010;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0xfff1 );
CHECKREG R0, (_VS|_AN);
// ff00 0000
// + 0018 0000
// + 0008 0000
// ->fff2
R0.L = 0x0000;
R0.H = 0xff00;
R1.L = 0x0000;
R1.H = 0x0018;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0xfff2 );
CHECKREG R0, (_VS|_AN);
// Small negative plus small negative should give zero
// ffff ffff
// + ffff ffff
// + 0008 0000
// ->0000
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0xffff;
R1.H = 0xffff;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0000 );
CHECKREG R0, (_VS|_AZ);
// Small negative minus small positive should give zero
// ffff ffff
// + 0000 0010
// + 0008 0000
// ->0000
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0x0010;
R1.H = 0x0000;
R7.L = R0 - R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0000 );
CHECKREG R0, (_VS|_AZ);
pass
|
stsp/binutils-ia16
| 5,570
|
sim/testsuite/bfin/a9.s
|
// ALU test program.
// Test 32 bit MAX, MIN, ABS instructions
# mach: bfin
.include "testutils.inc"
start
// MAX
// first operand is larger, so AN=0
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger, so AN=1
R0.L = 0x0000;
R0.H = 0x0000;
R1.L = 0x0001;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is larger, check correct output with overflow
R0.L = 0xffff;
R0.H = 0x7fff;
R1.L = 0xffff;
R1.H = 0xffff;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger, no overflow here
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0xffff;
R1.H = 0x7fff;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger, overflow
R0.L = 0xffff;
R0.H = 0x800f;
R1.L = 0xffff;
R1.H = 0x7fff;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0S; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1S; R7 = CC; DBGA ( R7.L , 0x0 );
// both operands equal
R0.L = 0x0080;
R0.H = 0x8000;
R1.L = 0x0080;
R1.H = 0x8000;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0x0080 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// MIN
// second operand is smaller
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is smaller
R0.L = 0x0001;
R0.H = 0x8000;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is smaller, overflow
R0.L = 0x0001;
R0.H = 0x8000;
R1.L = 0x0000;
R1.H = 0x0ff0;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// equal operands
R0.L = 0x0001;
R0.H = 0x8000;
R1.L = 0x0001;
R1.H = 0x8000;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// ABS
R0.L = 0x0001;
R0.H = 0x8000;
R7 = ABS R0;
_DBG R7;
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
//CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
//CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
//CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
//CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
//CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
//CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0001;
R0.H = 0x0000;
R7 = ABS R0;
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0000;
R0.H = 0x8000;
R7 = ABS R0;
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xffff;
R0.H = 0xffff;
R7 = ABS R0;
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0000;
R0.H = 0x0000;
R7 = ABS R0;
_DBG R7;
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = VS; R6 = CC; DBGA (R6.L, 0x1);
CC = AZ; R6 = CC; DBGA (R6.L, 0x1);
pass
|
stsp/binutils-ia16
| 5,622
|
sim/testsuite/bfin/c_ldst_ld_d_p_pp_xh.s
|
//Original:testcases/core/c_ldst_ld_d_p_pp_xh/c_ldst_ld_d_p_pp_xh.dsp
// Spec Reference: c_ldst ld d [p++] xh
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// initial values
loadsym p5, DATA_ADDR_1, 0x08;
loadsym p1, DATA_ADDR_2, 0x08;
loadsym p2, DATA_ADDR_3, 0x08;
loadsym p4, DATA_ADDR_5, 0x08;
loadsym fp, DATA_ADDR_6, 0x08;
R4 = W [ P5 ++ ] (X);
R5 = W [ P1 ++ ] (X);
R6 = W [ P2 ++ ] (X);
R0 = W [ P4 ++ ] (X);
R1 = W [ FP ++ ] (X);
CHECKREG r0, 0xFFFF8A8B;
CHECKREG r1, 0x00000A0B;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00002A2B;
CHECKREG r6, 0x00004A4B;
R5 = W [ P5 ++ ] (X);
R6 = W [ P1 ++ ] (X);
R7 = W [ P2 ++ ] (X);
R1 = W [ P4 ++ ] (X);
R2 = W [ FP ++ ] (X);
CHECKREG r1, 0xFFFF8889;
CHECKREG r2, 0x00000809;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00000809;
CHECKREG r6, 0x00002829;
CHECKREG r7, 0x00004849;
R6 = W [ P5 ++ ] (X);
R7 = W [ P1 ++ ] (X);
R0 = W [ P2 ++ ] (X);
R2 = W [ P4 ++ ] (X);
R3 = W [ FP ++ ] (X);
CHECKREG r0, 0x00004E4F;
CHECKREG r2, 0xFFFF8E8F;
CHECKREG r3, 0x00000E0F;
CHECKREG r5, 0x00000809;
CHECKREG r6, 0x00000E0F;
CHECKREG r7, 0x00002E2F;
R7 = W [ P5 ++ ] (X);
R0 = W [ P1 ++ ] (X);
R1 = W [ P2 ++ ] (X);
R3 = W [ P4 ++ ] (X);
R4 = W [ FP ++ ] (X);
CHECKREG r0, 0x00002C2D;
CHECKREG r1, 0x00004C4D;
CHECKREG r3, 0xFFFF8C8D;
CHECKREG r4, 0x00000C0D;
CHECKREG r6, 0x00000E0F;
CHECKREG r7, 0x00000C0D;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 5,702
|
sim/testsuite/bfin/c_dsp32alu_max.s
|
//Original:/testcases/core/c_dsp32alu_max/c_dsp32alu_max.dsp
// Spec Reference: dsp32alu dregs = max ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x85678911;
imm32 r1, 0x9789ab1d;
imm32 r2, 0xa4445b15;
imm32 r3, 0x46667717;
imm32 r4, 0xd567f91b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0 = MAX ( R0 , R0 );
R1 = MAX ( R0 , R1 );
R2 = MAX ( R0 , R2 );
R3 = MAX ( R0 , R3 );
R4 = MAX ( R0 , R4 );
R5 = MAX ( R0 , R5 );
R6 = MAX ( R0 , R6 );
R7 = MAX ( R0 , R7 );
CHECKREG r0, 0x85678911;
CHECKREG r1, 0x9789AB1D;
CHECKREG r2, 0xA4445B15;
CHECKREG r3, 0x46667717;
CHECKREG r4, 0xD567F91B;
CHECKREG r5, 0x6789AB1D;
CHECKREG r6, 0x74445515;
CHECKREG r7, 0x86667777;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = MAX ( R1 , R0 );
R1 = MAX ( R1 , R1 );
R2 = MAX ( R1 , R2 );
R3 = MAX ( R1 , R3 );
R4 = MAX ( R1 , R4 );
R5 = MAX ( R1 , R5 );
R6 = MAX ( R1 , R6 );
R7 = MAX ( R1 , R7 );
CHECKREG r0, 0xA789AB2D;
CHECKREG r1, 0xA789AB2D;
CHECKREG r2, 0xB4445525;
CHECKREG r3, 0xC6667727;
CHECKREG r4, 0xD8889929;
CHECKREG r5, 0xEAAABB2B;
CHECKREG r6, 0xFCCCDD2D;
CHECKREG r7, 0x0EEEFFFF;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r4, 0x456789ab;
imm32 r5, 0x6689abcd;
imm32 r6, 0x47445555;
imm32 r7, 0x68667777;
R0 = MAX ( R2 , R0 );
R1 = MAX ( R2 , R1 );
R2 = MAX ( R2 , R2 );
R3 = MAX ( R2 , R3 );
R4 = MAX ( R2 , R4 );
R5 = MAX ( R2 , R5 );
R6 = MAX ( R2 , R6 );
R7 = MAX ( R2 , R7 );
CHECKREG r0, 0x43445555;
CHECKREG r1, 0x6289ABCD;
CHECKREG r2, 0x43445555;
CHECKREG r3, 0x64667777;
CHECKREG r4, 0x456789AB;
CHECKREG r5, 0x6689ABCD;
CHECKREG r6, 0x47445555;
CHECKREG r7, 0x68667777;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
R0 = MAX ( R3 , R0 );
R1 = MAX ( R3 , R1 );
R2 = MAX ( R3 , R2 );
R3 = MAX ( R3 , R3 );
R4 = MAX ( R3 , R4 );
R5 = MAX ( R3 , R5 );
R6 = MAX ( R3 , R6 );
R7 = MAX ( R3 , R7 );
CHECKREG r0, 0xC6667727;
CHECKREG r1, 0xC6667727;
CHECKREG r2, 0xC6667727;
CHECKREG r3, 0xC6667727;
CHECKREG r4, 0x456789AB;
CHECKREG r5, 0x6689ABCD;
CHECKREG r6, 0x47445555;
CHECKREG r7, 0x68667777;
imm32 r0, 0x5537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x74555535;
imm32 r3, 0x86665747;
imm32 r4, 0x88789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cdd85;
imm32 r7, 0xeeaeff9f;
R0 = MAX ( R4 , R0 );
R1 = MAX ( R4 , R1 );
R2 = MAX ( R4 , R2 );
R3 = MAX ( R4 , R3 );
R4 = MAX ( R4 , R4 );
R5 = MAX ( R4 , R5 );
R6 = MAX ( R4 , R6 );
R7 = MAX ( R4 , R7 );
CHECKREG r0, 0x5537891B;
CHECKREG r1, 0x6759AB2D;
CHECKREG r2, 0x74555535;
CHECKREG r3, 0x88789565;
CHECKREG r4, 0x88789565;
CHECKREG r5, 0xAA8ABB5B;
CHECKREG r6, 0xCC9CDD85;
CHECKREG r7, 0xEEAEFF9F;
imm32 r0, 0x556b89ab;
imm32 r1, 0x69764bcd;
imm32 r2, 0x79736564;
imm32 r3, 0x81278394;
imm32 r4, 0x98876439;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0xcccc1ddd;
imm32 r7, 0x12346fff;
R0 = MAX ( R5 , R0 );
R1 = MAX ( R5 , R1 );
R2 = MAX ( R5 , R2 );
R3 = MAX ( R5 , R3 );
R4 = MAX ( R5 , R4 );
R5 = MAX ( R5 , R5 );
R6 = MAX ( R5 , R6 );
R7 = MAX ( R5 , R7 );
CHECKREG r0, 0x556B89AB;
CHECKREG r1, 0x69764BCD;
CHECKREG r2, 0x79736564;
CHECKREG r3, 0xAAAA0BBB;
CHECKREG r4, 0xAAAA0BBB;
CHECKREG r5, 0xAAAA0BBB;
CHECKREG r6, 0xCCCC1DDD;
CHECKREG r7, 0x12346FFF;
imm32 r0, 0xe56739ab;
imm32 r1, 0xf7694bcd;
imm32 r2, 0xa3456755;
imm32 r3, 0x66666777;
imm32 r4, 0x42345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R0 = MAX ( R6 , R0 );
R1 = MAX ( R6 , R1 );
R2 = MAX ( R6 , R2 );
R3 = MAX ( R6 , R3 );
R4 = MAX ( R6 , R4 );
R5 = MAX ( R6 , R5 );
R6 = MAX ( R6 , R6 );
R7 = MAX ( R6 , R7 );
CHECKREG r0, 0x043290D6;
CHECKREG r1, 0x043290D6;
CHECKREG r2, 0x043290D6;
CHECKREG r3, 0x66666777;
CHECKREG r4, 0x42345699;
CHECKREG r5, 0x45678B6B;
CHECKREG r6, 0x043290D6;
CHECKREG r7, 0x1234567F;
imm32 r0, 0x576789ab;
imm32 r1, 0xd779abcd;
imm32 r2, 0x23456755;
imm32 r3, 0x56789007;
imm32 r4, 0x789ab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0xf9ab1d7d;
imm32 r7, 0xabcd2ff7;
R0 = MAX ( R7 , R0 );
R1 = MAX ( R7 , R1 );
R2 = MAX ( R7 , R2 );
R3 = MAX ( R7 , R3 );
R4 = MAX ( R7 , R4 );
R5 = MAX ( R7 , R5 );
R6 = MAX ( R7 , R6 );
R7 = MAX ( R7 , R7 );
CHECKREG r0, 0x576789AB;
CHECKREG r1, 0xD779ABCD;
CHECKREG r2, 0x23456755;
CHECKREG r3, 0x56789007;
CHECKREG r4, 0x789AB799;
CHECKREG r5, 0xABCD2FF7;
CHECKREG r6, 0xF9AB1D7D;
CHECKREG r7, 0xABCD2FF7;
imm32 r0, 0xe56739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0xd3456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R4 = MAX ( R4 , R7 );
R5 = MAX ( R5 , R5 );
R2 = MAX ( R6 , R3 );
R6 = MAX ( R0 , R4 );
R0 = MAX ( R1 , R6 );
R2 = MAX ( R2 , R1 );
R1 = MAX ( R3 , R0 );
R7 = MAX ( R7 , R4 );
CHECKREG r0, 0x67694BCD;
CHECKREG r1, 0x67694BCD;
CHECKREG r2, 0x67694BCD;
CHECKREG r3, 0x66666777;
CHECKREG r4, 0x12345699;
CHECKREG r5, 0x45678B6B;
CHECKREG r6, 0x12345699;
CHECKREG r7, 0x12345699;
imm32 r0, 0xd76789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0xe3456755;
imm32 r3, 0x56789007;
imm32 r4, 0x789ab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcd2ff7;
R3 = MAX ( R4 , R0 );
R5 = MAX ( R5 , R1 );
R2 = MAX ( R2 , R2 );
R7 = MAX ( R7 , R3 );
R4 = MAX ( R3 , R4 );
R0 = MAX ( R1 , R5 );
R1 = MAX ( R0 , R6 );
R6 = MAX ( R6 , R7 );
CHECKREG r0, 0x6779ABCD;
CHECKREG r1, 0x6779ABCD;
CHECKREG r2, 0xE3456755;
CHECKREG r3, 0x789AB799;
CHECKREG r4, 0x789AB799;
CHECKREG r5, 0x6779ABCD;
CHECKREG r6, 0x789AB799;
CHECKREG r7, 0x789AB799;
pass
|
stsp/binutils-ia16
| 1,131
|
sim/testsuite/bfin/se_all64bitg2opcodes.S
|
/*
* Blackfin testcase for testing illegal/legal 64-bit opcodes (group 2)
* from userspace. we track all instructions which cause some sort of
* exception when run from userspace, this is normally EXCAUSE :
* - 0x22 : illegal instruction combination
* and walk every instruction from 0x0000 to 0xffff
*/
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
#define SE_ALL_BITS 16
#include "se_allopcodes.h"
.macro se_all_load_insn
R2 = W[P5 + 6];
R0 = R2;
.endm
.macro se_all_next_insn
/* increment, and go again. */
R0 = R2;
R0 += 1;
/* finish once we hit the 32bit limit */
imm32 R1, 0x10000;
CC = R1 == R0;
IF CC JUMP pass_lvl;
W[P5 + 6] = R0;
.endm
.macro se_all_insn_init
MNOP || NOP || NOP;
.endm
.macro se_all_insn_table
/* this table must be sorted, and end with zero */
/* start end SEQSTAT */
.dw 0x0001, 0x9bff, 0x22
.dw 0x9c60, 0x9c7f, 0x22
.dw 0x9ce0, 0x9cff, 0x22
.dw 0x9d60, 0x9d7f, 0x22
.dw 0x9e60, 0x9e7f, 0x22
.dw 0x9ee0, 0x9eff, 0x22
.dw 0x9f60, 0x9f7f, 0x22
.dw 0xa000, 0xffff, 0x22
.dw 0x0000, 0x0000, 0x00
.endm
se_all_test
|
stsp/binutils-ia16
| 4,844
|
sim/testsuite/bfin/c_dsp32mult_dr_m_u.s
|
//Original:/testcases/core/c_dsp32mult_dr_m_u/c_dsp32mult_dr_m_u.dsp
// Spec Reference: dsp32mult single dr munop u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm32 r7, 0xd24f702f;
R4.L = R0.H * R0.L (FU);
R5.H = R0.L * R1.L (FU);
R6.L = R1.L * R0.H (FU);
R7.L = R1.L * R1.L (FU);
R0.H = R0.L * R0.L (FU);
R1.L = R0.L * R1.L (FU);
R2.L = R1.H * R0.L (FU);
R3.H = R1.L * R1.L (FU);
CHECKREG r0, 0x1CFD5625;
CHECKREG r1, 0x9FBA1B4F;
CHECKREG r2, 0xA3FF35C0;
CHECKREG r3, 0x02EAF027;
CHECKREG r4, 0xB0AB5482;
CHECKREG r5, 0x1B4FEF2B;
CHECKREG r6, 0xC0FC4F9C;
CHECKREG r7, 0xD24F19BA;
imm32 r0, 0xbb23a635;
imm32 r1, 0x6bba5137;
imm32 r2, 0x13b4b7e5;
imm32 r3, 0x9e0b0037;
imm32 r4, 0x80ebbd39;
imm32 r5, 0xb0aeef3b;
imm32 r6, 0xa00ceb3d;
imm32 r7, 0x12467eb3;
R4.H = R2.L * R2.L (FU);
R5.L = R2.L * R3.H (FU);
R6.L = R3.H * R2.L (FU);
R7.H = R3.L * R3.L (FU);
R2.H = R2.L * R2.H (FU);
R3.L = R2.H * R3.H (FU);
R0.H = R3.L * R2.L (FU);
R1.L = R3.L * R3.L (FU);
CHECKREG r0, 0x0647A635;
CHECKREG r1, 0x6BBA004C;
CHECKREG r2, 0x0E27B7E5;
CHECKREG r3, 0x9E0B08BD;
CHECKREG r4, 0x8419BD39;
CHECKREG r5, 0xB0AE7187;
CHECKREG r6, 0xA00C7187;
CHECKREG r7, 0x00007EB3;
imm32 r0, 0xbd235655;
imm32 r1, 0xc4dd5157;
imm32 r2, 0x6b24d755;
imm32 r3, 0x00b60055;
imm32 r4, 0x90dbc509;
imm32 r5, 0x10adbf5b;
imm32 r6, 0xb00cdb5d;
imm32 r7, 0x12467dbf;
R0.L = R4.L * R4.H (FU);
R1.H = R4.H * R5.L (FU);
R2.L = R5.H * R4.L (FU);
R3.L = R5.L * R5.L (FU);
R4.H = R4.L * R4.H (FU);
R5.L = R4.L * R5.H (FU);
R6.H = R5.H * R4.H (FU);
R7.L = R5.H * R5.H (FU);
CHECKREG r0, 0xBD236F7E;
CHECKREG r1, 0x6C475157;
CHECKREG r2, 0x6B240CD6;
CHECKREG r3, 0x00B68F09;
CHECKREG r4, 0x6F7EC509;
CHECKREG r5, 0x10AD0CD6;
CHECKREG r6, 0x0743DB5D;
CHECKREG r7, 0x12460116;
imm32 r0, 0xcb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x1c248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90cb9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cc06d;
imm32 r7, 0x12467c6f;
// test the unsigned U=1
R0.L = R6.L * R6.L (FU);
R1.H = R6.H * R7.L (FU);
R2.L = R7.L * R6.L (FU);
R3.L = R7.L * R7.L (FU);
R6.L = R6.L * R6.L (FU);
R7.L = R6.L * R7.L (FU);
R4.L = R7.L * R6.L (FU);
R5.L = R7.L * R7.L (FU);
CHECKREG r0, 0xCB2390A4;
CHECKREG r1, 0x3E3D5166;
CHECKREG r2, 0x1C245D88;
CHECKREG r3, 0xF0063C7C;
CHECKREG r4, 0x90CB27B9;
CHECKREG r5, 0x10AC134F;
CHECKREG r6, 0x800C90A4;
CHECKREG r7, 0x1246464E;
// mix order
imm32 r0, 0x8b23a675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13846705;
imm32 r3, 0xe0088807;
imm32 r4, 0x9eabcd09;
imm32 r5, 0x10ecdfdb;
imm32 r6, 0x000e008d;
imm32 r7, 0x1246e008;
R0.H = R0.L * R7.H (FU);
R1.L = R1.H * R6.H (FU);
R2.L = R2.L * R5.L (FU);
R3.H = R3.H * R4.H (FU);
R4.L = R4.L * R3.H (FU);
R5.L = R5.H * R2.H (FU);
R6.H = R6.H * R1.L (FU);
R7.L = R7.L * R0.H (FU);
CHECKREG r0, 0x0BE2A675;
CHECKREG r1, 0xC8BA000B;
CHECKREG r2, 0x13845A15;
CHECKREG r3, 0x8ADB8807;
CHECKREG r4, 0x9EAB6F36;
CHECKREG r5, 0x10EC014A;
CHECKREG r6, 0x0000008D;
CHECKREG r7, 0x12460A66;
imm32 r0, 0x9b235a75;
imm32 r1, 0x7fba5127;
imm32 r2, 0x97246905;
imm32 r3, 0x09777007;
imm32 r4, 0x909bc779;
imm32 r5, 0x10a9e9d7;
imm32 r6, 0x000c9d0d;
imm32 r7, 0x1246790f;
R0.L = R7.L * R0.H (FU);
R1.L = R6.L * R1.L (FU);
R2.H = R5.L * R2.L (FU);
R3.L = R4.H * R3.L (FU);
R4.L = R3.H * R4.H (FU);
R5.H = R2.H * R5.L (FU);
R6.L = R1.H * R6.L (FU);
R7.L = R0.L * R7.L (FU);
CHECKREG r0, 0x9B23495D;
CHECKREG r1, 0x7FBA31C9;
CHECKREG r2, 0x5FEE6905;
CHECKREG r3, 0x09773F48;
CHECKREG r4, 0x909B0559;
CHECKREG r5, 0x57A0E9D7;
CHECKREG r6, 0x000C4E5C;
CHECKREG r7, 0x124622B1;
imm32 r0, 0xa9235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x08060007;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a88fdb;
imm32 r6, 0x000c080d;
imm32 r7, 0x1246708f;
R2.L = R0.L * R6.L (FU);
R3.L = R1.H * R7.H (FU);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.L (FU);
R1.H = R3.L * R4.L (FU);
R4.L = R1.H * R2.L (FU);
R5.L = R5.L * R3.L (FU);
R6.L = R6.L * R4.L (FU);
R7.H = R7.H * R5.L (FU);
CHECKREG r0, 0x00EB0677;
CHECKREG r1, 0x0B7A5127;
CHECKREG r2, 0x132402B8;
CHECKREG r3, 0x08060E54;
CHECKREG r4, 0x908B001F;
CHECKREG r5, 0x10A8080D;
CHECKREG r6, 0x000C0001;
CHECKREG r7, 0x0093708F;
imm32 r0, 0x7b235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x17246705;
imm32 r3, 0x00760007;
imm32 r4, 0x907bcd09;
imm32 r5, 0x10a7efdb;
imm32 r6, 0x000c700d;
imm32 r7, 0x1246770f;
R4.L = R5.L * R2.L (FU);
R6.L = R6.L * R3.H (FU);
R0.H = R7.L * R4.H (FU);
R1.L = R0.H * R5.L (FU);
R2.L = R1.L * R6.L (FU);
R5.L = R2.L * R7.H (FU);
R3.H = R3.H * R0.L (FU);
R7.L = R4.H * R1.H (FU);
CHECKREG r0, 0x43325675;
CHECKREG r1, 0xCFBA3EF5;
CHECKREG r2, 0x1724000D;
CHECKREG r3, 0x00280007;
CHECKREG r4, 0x907B6086;
CHECKREG r5, 0x10A70001;
CHECKREG r6, 0x000C0034;
CHECKREG r7, 0x1246753C;
pass
|
stsp/binutils-ia16
| 7,095
|
sim/testsuite/bfin/c_dsp32shift_lhh.s
|
//Original:/testcases/core/c_dsp32shift_lhh/c_dsp32shift_lhh.dsp
// Spec Reference: dsp32shift lshift/lshift
# mach: bfin
.include "testutils.inc"
start
// lshift/lshift : = (half reg)
// d_reg = lshift/lshift (d BY d_lo)
// Rx by RLx
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1 = LSHIFT R0 BY R0.L (V);
R2 = LSHIFT R1 BY R0.L (V);
R3 = LSHIFT R2 BY R0.L (V);
R4 = LSHIFT R3 BY R0.L (V);
R5 = LSHIFT R4 BY R0.L (V);
R6 = LSHIFT R5 BY R0.L (V);
R7 = LSHIFT R6 BY R0.L (V);
R0 = LSHIFT R7 BY R0.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1.L = 5;
R2 = LSHIFT R0 BY R1.L (V);
R3 = LSHIFT R1 BY R1.L (V);
R4 = LSHIFT R2 BY R1.L (V);
R5 = LSHIFT R3 BY R1.L (V);
R6 = LSHIFT R4 BY R1.L (V);
R7 = LSHIFT R5 BY R1.L (V);
R0 = LSHIFT R6 BY R1.L (V);
R1 = LSHIFT R7 BY R1.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2 = 15;
R3 = LSHIFT R0 BY R2.L (V);
R4 = LSHIFT R1 BY R2.L (V);
R5 = LSHIFT R2 BY R2.L (V);
R6 = LSHIFT R3 BY R2.L (V);
R7 = LSHIFT R4 BY R2.L (V);
R0 = LSHIFT R5 BY R2.L (V);
R1 = LSHIFT R6 BY R2.L (V);
R2 = LSHIFT R7 BY R2.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R3.L = 16;
R4 = LSHIFT R0 BY R3.L (V);
R5 = LSHIFT R1 BY R3.L (V);
R6 = LSHIFT R2 BY R3.L (V);
R7 = LSHIFT R3 BY R3.L (V);
R0 = LSHIFT R4 BY R3.L (V);
R1 = LSHIFT R5 BY R3.L (V);
R2 = LSHIFT R6 BY R3.L (V);
R3 = LSHIFT R7 BY R3.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -1;
R0 = LSHIFT R0 BY R4.L (V);
R1 = LSHIFT R1 BY R4.L (V);
R2 = LSHIFT R2 BY R4.L (V);
R3 = LSHIFT R3 BY R4.L (V);
R4 = LSHIFT R4 BY R4.L (V);
R5 = LSHIFT R5 BY R4.L (V);
R6 = LSHIFT R6 BY R4.L (V);
R7 = LSHIFT R7 BY R4.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -6;
R6 = LSHIFT R0 BY R5.L (V);
R7 = LSHIFT R1 BY R5.L (V);
R0 = LSHIFT R2 BY R5.L (V);
R1 = LSHIFT R3 BY R5.L (V);
R2 = LSHIFT R4 BY R5.L (V);
R3 = LSHIFT R5 BY R5.L (V);
R4 = LSHIFT R6 BY R5.L (V);
R5 = LSHIFT R7 BY R5.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R6.L = -15;
R7 = LSHIFT R0 BY R6.L (V);
R0 = LSHIFT R1 BY R6.L (V);
R1 = LSHIFT R2 BY R6.L (V);
R2 = LSHIFT R3 BY R6.L (V);
R3 = LSHIFT R4 BY R6.L (V);
R4 = LSHIFT R5 BY R6.L (V);
R5 = LSHIFT R6 BY R6.L (V);
R6 = LSHIFT R7 BY R6.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7.L = -16;
R0 = LSHIFT R0 BY R7.L (V);
R1 = LSHIFT R1 BY R7.L (V);
R2 = LSHIFT R2 BY R7.L (V);
R3 = LSHIFT R3 BY R7.L (V);
R4 = LSHIFT R4 BY R7.L (V);
R5 = LSHIFT R5 BY R7.L (V);
R6 = LSHIFT R6 BY R7.L (V);
R7 = LSHIFT R7 BY R7.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R0.L = 4;
//r0 = lshift/lshift (r0 by rl0);
R1 = LSHIFT R1 BY R0.L (V);
R2 = LSHIFT R2 BY R0.L (V);
R3 = LSHIFT R3 BY R0.L (V);
R4 = LSHIFT R4 BY R0.L (V);
R5 = LSHIFT R5 BY R0.L (V);
R6 = LSHIFT R6 BY R0.L (V);
R7 = LSHIFT R7 BY R0.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1.L = 6;
R0 = LSHIFT R0 BY R1.L (V);
//r1 = lshift/lshift (r1 by rl1);
R2 = LSHIFT R2 BY R1.L (V);
R3 = LSHIFT R3 BY R1.L (V);
R4 = LSHIFT R4 BY R1.L (V);
R5 = LSHIFT R5 BY R1.L (V);
R6 = LSHIFT R6 BY R1.L (V);
R7 = LSHIFT R7 BY R1.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 15;
R0 = LSHIFT R0 BY R2.L (V);
R1 = LSHIFT R1 BY R2.L (V);
//r2 = lshift/lshift (r2 by rl2);
R3 = LSHIFT R3 BY R2.L (V);
R4 = LSHIFT R4 BY R2.L (V);
R5 = LSHIFT R5 BY R2.L (V);
R6 = LSHIFT R6 BY R2.L (V);
R7 = LSHIFT R7 BY R2.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R3.L = 16;
R0 = LSHIFT R0 BY R3.L (V);
R1 = LSHIFT R1 BY R3.L (V);
R2 = LSHIFT R2 BY R3.L (V);
//r3 = lshift/lshift (r3 by rl3);
R4 = LSHIFT R4 BY R3.L (V);
R5 = LSHIFT R5 BY R3.L (V);
R6 = LSHIFT R6 BY R3.L (V);
R7 = LSHIFT R7 BY R3.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -9;
R0 = LSHIFT R0 BY R4.L (V);
R1 = LSHIFT R1 BY R4.L (V);
R2 = LSHIFT R2 BY R4.L (V);
R3 = LSHIFT R3 BY R4.L (V);
//r4 = lshift/lshift (r4 by rl4);
R5 = LSHIFT R5 BY R4.L (V);
R6 = LSHIFT R6 BY R4.L (V);
R7 = LSHIFT R7 BY R4.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -14;
R0 = LSHIFT R0 BY R5.L (V);
R1 = LSHIFT R1 BY R5.L (V);
R2 = LSHIFT R2 BY R5.L (V);
R3 = LSHIFT R3 BY R5.L (V);
R4 = LSHIFT R4 BY R5.L (V);
//r5 = lshift/lshift (r5 by rl5);
R6 = LSHIFT R6 BY R5.L (V);
R7 = LSHIFT R7 BY R5.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R6.L = -15;
R0 = LSHIFT R0 BY R6.L (V);
R1 = LSHIFT R1 BY R6.L (V);
R2 = LSHIFT R2 BY R6.L (V);
R3 = LSHIFT R3 BY R6.L (V);
R4 = LSHIFT R4 BY R6.L (V);
R5 = LSHIFT R5 BY R6.L (V);
//r6 = lshift/lshift (r6 by rl6);
R7 = LSHIFT R7 BY R6.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7.L = -16;
R0 = LSHIFT R0 BY R7.L (V);
R1 = LSHIFT R1 BY R7.L (V);
R2 = LSHIFT R2 BY R7.L (V);
R3 = LSHIFT R3 BY R7.L (V);
R4 = LSHIFT R4 BY R7.L (V);
R5 = LSHIFT R5 BY R7.L (V);
R6 = LSHIFT R6 BY R7.L (V);
R7 = LSHIFT R7 BY R7.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 1,817
|
sim/testsuite/bfin/c_regmv_dr_pr.s
|
//Original:/testcases/core/c_regmv_dr_pr/c_regmv_dr_pr.dsp
// Spec Reference: regmv dreg-to-preg
# mach: bfin
.include "testutils.inc"
start
// check R-reg to R-reg move
imm32 r0, 0x20001001;
imm32 r1, 0x20021003;
imm32 r2, 0x20041005;
imm32 r3, 0x20061007;
imm32 r4, 0x20081009;
imm32 r5, 0x200a100b;
imm32 r6, 0x200c100d;
imm32 r7, 0x200e100f;
P1 = R0;
P2 = R0;
P4 = R0;
P5 = R0;
FP = R0;
CHECKREG p1, 0x20001001;
CHECKREG p2, 0x20001001;
CHECKREG p4, 0x20001001;
CHECKREG p5, 0x20001001;
CHECKREG fp, 0x20001001;
P1 = R1;
P2 = R1;
P4 = R1;
P5 = R1;
FP = R1;
CHECKREG p1, 0x20021003;
CHECKREG p2, 0x20021003;
CHECKREG p4, 0x20021003;
CHECKREG p5, 0x20021003;
CHECKREG fp, 0x20021003;
P1 = R2;
P2 = R2;
P4 = R2;
P5 = R2;
FP = R2;
CHECKREG p1, 0x20041005;
CHECKREG p2, 0x20041005;
CHECKREG p4, 0x20041005;
CHECKREG p5, 0x20041005;
CHECKREG fp, 0x20041005;
P1 = R3;
P2 = R3;
P4 = R3;
P5 = R3;
FP = R3;
CHECKREG p1, 0x20061007;
CHECKREG p2, 0x20061007;
CHECKREG p4, 0x20061007;
CHECKREG p5, 0x20061007;
CHECKREG fp, 0x20061007;
P1 = R4;
P2 = R4;
P4 = R4;
P5 = R4;
FP = R4;
CHECKREG p1, 0x20081009;
CHECKREG p2, 0x20081009;
CHECKREG p4, 0x20081009;
CHECKREG p5, 0x20081009;
CHECKREG fp, 0x20081009;
P1 = R5;
P2 = R5;
P4 = R5;
P5 = R5;
FP = R5;
CHECKREG p1, 0x200a100b;
CHECKREG p2, 0x200a100b;
CHECKREG p4, 0x200a100b;
CHECKREG p5, 0x200a100b;
CHECKREG fp, 0x200a100b;
P1 = R6;
P2 = R6;
P4 = R6;
P5 = R6;
FP = R6;
CHECKREG p1, 0x200c100d;
CHECKREG p2, 0x200c100d;
CHECKREG p4, 0x200c100d;
CHECKREG p5, 0x200c100d;
CHECKREG fp, 0x200c100d;
P1 = R7;
P2 = R7;
P4 = R7;
P5 = R7;
FP = R7;
CHECKREG p1, 0x200e100f;
CHECKREG p2, 0x200e100f;
CHECKREG p4, 0x200e100f;
CHECKREG p5, 0x200e100f;
CHECKREG fp, 0x200e100f;
End:
pass
|
stsp/binutils-ia16
| 1,744
|
sim/testsuite/bfin/double_prec_mult.s
|
# mach: bfin
.include "testutils.inc"
start
// This function computes an integer 32x32 multiply,
// and returns the upper 32 bits of the result.
// If the complete 64 bit result is required, one must
// write the partial results as they are computed.
// To change this code for a fractional 32x32, one needs
// to adjust the shifts for magnitude of -15, and use a
// fractional multiply at the end for the upper word halves
// (instead of the integer one).
loadsym P0, input_a;
loadsym P1, input_b;
loadsym P2, output;
P4 = 10;
LSETUP ( loop1 , loop1end ) LC0 = P4;
loop1:
R0 = [ P0 ++ ];
R1 = [ P1 ++ ];
// begin integer double precision routine
// 32 x 32 -> 32
A1 = R0.H * R1.L (M), A0 = R0.L * R1.L (FU);
A1 += R1.H * R0.L (M,IS);
A0 = A0 >>> 16;
A0 += A1;
A0 = A0 >>> 16;
A0 += R0.H * R1.H (IS);
R7 = A0.w;
loop1end:
[ P2 ++ ] = R7; // store 32 bit output
// test results
loadsym P1, output;
R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xab6b );
R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xa627 );
R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xa0e3 );
R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0x9b9f );
pass
.data
input_a:
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.align 4;
input_b:
.dw 0x1000
.dw 0x4010
.dw 0x1000
.dw 0x4011
.dw 0x1000
.dw 0x4012
.dw 0x1000
.dw 0x4013
.dw 0x1000
.dw 0x4014
.dw 0x1000
.dw 0x4015
.dw 0x1000
.dw 0x4016
.dw 0x1000
.dw 0x4017
.dw 0x1000
.dw 0x4018
.dw 0x1000
.dw 0x4019
.align 4;
output:
.space (40);
|
stsp/binutils-ia16
| 10,134
|
sim/testsuite/bfin/random_0036.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x3ce04490 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0x7d8d8272;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xe0004138;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x7d8e7fff;
imm32 R2, 0xffff8001;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A0.w, 0xfd8c0273;
checkreg A0.x, 0x00000000;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x3ce04490 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 ASTAT, (0x70b0c800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0x53931540;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xf07795da;
dmm32 A1.x, 0x0000007f;
imm32 R2, 0x8931da0a;
imm32 R4, 0xffff41eb;
imm32 R5, 0x7fff41eb;
A1 += R5.L * R4.H (M), R2 = (A0 -= R5.L * R4.H) (FU);
checkreg R2, 0x11a8572b;
checkreg A0.w, 0x11a8572b;
checkreg A0.x, 0x00000000;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x70b0c800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY);
dmm32 ASTAT, (0x58100410 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0xaeba0d61;
dmm32 A0.x, 0x00000041;
dmm32 A1.w, 0xbb313d2f;
dmm32 A1.x, 0x0000007f;
imm32 R4, 0x1ea2588d;
imm32 R7, 0xffffffff;
A1 += R4.L * R7.H (M), A0 += R4.L * R7.L (FU);
checkreg A0.w, 0x0746b4d4;
checkreg A0.x, 0x00000042;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x58100410 | _VS | _V | _AV1S | _AV1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x58704200 | _VS | _AV1S | _AV0S);
dmm32 A0.w, 0xb7ab4854;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xe0002429;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0xb7ac8000;
imm32 R2, 0x80008001;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A0.w, 0xf7ab4854;
checkreg A0.x, 0x00000000;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x58704200 | _VS | _AV1S | _AV1 | _AV0S);
dmm32 ASTAT, (0x38d0c800 | _VS | _AV1S | _AV0S);
dmm32 A0.w, 0xfffe0001;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xffff4001;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0xffffffff;
imm32 R2, 0xffffffff;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A0.w, 0xfffc0002;
checkreg A0.x, 0x00000001;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x38d0c800 | _VS | _AV1S | _AV1 | _AV0S);
dmm32 ASTAT, (0x24e0ca80 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY);
dmm32 A0.w, 0x0000000a;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xff5439dc;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x3ea961c5;
imm32 R6, 0xffff0510;
A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x24e0ca80 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY);
dmm32 ASTAT, (0x7800cc80 | _VS | _AC1 | _AC0 | _CC | _AC0_COPY);
dmm32 A0.w, 0xfffe0001;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xffff4001;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0xffffffff;
imm32 R2, 0x0000ffff;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x7800cc80 | _VS | _AV1S | _AV1 | _AC1 | _AC0 | _CC | _AC0_COPY);
dmm32 ASTAT, (0x50200800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY);
dmm32 A0.w, 0x6970968f;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xe0004b47;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x69717fff;
imm32 R2, 0xffff8001;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A0.w, 0xe96f1690;
checkreg A0.x, 0x00000000;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x50200800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY);
dmm32 ASTAT, (0x34704080 | _VS | _AV1S | _AV1 | _AV0S | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0x0839a708;
dmm32 A0.x, 0xffffff80;
dmm32 A1.w, 0xffffffff;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x0c8c109a;
imm32 R2, 0x109a0c8c;
imm32 R5, 0x006dd6ac;
A1 -= R5.L * R0.L (M), R2.L = (A0 += R5.H * R0.L) (FU);
checkreg R2, 0x109affff;
checkreg A0.w, 0x0840b89a;
checkreg A0.x, 0xffffff80;
checkreg ASTAT, (0x34704080 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x78108090 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0x21edde12;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xe0006f08;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x21ee7fff;
imm32 R2, 0xffff8001;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A0.w, 0xa1ec5e13;
checkreg A0.x, 0x00000000;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x78108090 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY);
dmm32 ASTAT, (0x50b08a10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0x00000007;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xf8b109fc;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x27827703;
imm32 R6, 0xffff03ca;
A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x50b08a10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x34e0c800 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY);
dmm32 A0.w, 0xffffffff;
dmm32 A0.x, 0xffffffff;
dmm32 A1.w, 0xefc2be42;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x53574850;
imm32 R6, 0xffff1400;
A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU);
checkreg A0.w, 0xaca95356;
checkreg A0.x, 0xffffffff;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x34e0c800 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY);
dmm32 ASTAT, (0x24608c80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0x0f03f0fc;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xe000787d;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x0f04ffff;
imm32 R2, 0xffff8001;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A0.w, 0x0f01f0fd;
checkreg A0.x, 0x00000001;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x24608c80 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY);
dmm32 ASTAT, (0x58404690 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0x1e65e19a;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xe00070cc;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x1e66ffff;
imm32 R2, 0xffff8001;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A0.w, 0x1e63e19b;
checkreg A0.x, 0x00000001;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x58404690 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x08004a10 | _VS | _AV1S | _AV1 | _AC0 | _CC | _AC0_COPY);
dmm32 A1.w, 0xffffffff;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x293a8000;
imm32 R3, 0xd0e6382b;
A1 += R3.L * R0.H (M, FU);
checkreg ASTAT, (0x08004a10 | _VS | _AV1S | _AV1 | _AC0 | _CC | _AC0_COPY);
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg R0, 0x293a8000;
checkreg R3, 0xd0e6382b;
dmm32 ASTAT, (0x28e00e00 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0xfffe0001;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xffff4001;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0xffffffff;
imm32 R2, 0x0000ffff;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x28e00e00 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY);
dmm32 ASTAT, (0x14004690 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0xffffffff;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x369a8000;
imm32 R3, 0xf023457e;
A1 += R3.L * R0.H (M, FU);
checkreg ASTAT, (0x14004690 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg R0, 0x369a8000;
checkreg R3, 0xf023457e;
dmm32 ASTAT, (0x5c600680 | _VS | _AV1S | _AQ | _CC);
dmm32 A0.w, 0xfffe0001;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xffff4001;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0xffffffff;
imm32 R2, 0xffffffff;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A0.w, 0xfffc0002;
checkreg A0.x, 0x00000001;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x5c600680 | _VS | _AV1S | _AV1 | _AQ | _CC);
dmm32 ASTAT, (0x7cd00800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY);
dmm32 A0.w, 0xfffe0001;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xffff4001;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0xffffffff;
imm32 R2, 0x0000ffff;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x7cd00800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY);
dmm32 ASTAT, (0x78e0cc10 | _VS | _AV1S | _AV0S | _AC1);
dmm32 A0.w, 0xfffe0001;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xffff4001;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0xffffffff;
imm32 R2, 0xffffffff;
A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
checkreg A0.w, 0xfffc0002;
checkreg A0.x, 0x00000001;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x78e0cc10 | _VS | _AV1S | _AV1 | _AV0S | _AC1);
dmm32 ASTAT, (0x1cd04c80 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0x00000015;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xfeeaa91d;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x50246875;
imm32 R6, 0xffff0aab;
A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x1cd04c80 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x18304890 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0xfffffffe;
dmm32 A0.x, 0xffffffff;
dmm32 A1.w, 0xffffca85;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0xffffffff;
imm32 R3, 0xffffdc58;
imm32 R7, 0xffff950a;
A1 -= R7.L * R0.H (M), R3.L = (A0 -= R7.L * R0.H) (FU);
checkreg R3, 0xffffffff;
checkreg A0.w, 0x6af69508;
checkreg A0.x, 0xffffffff;
checkreg A1.w, 0xffffffff;
checkreg A1.x, 0x0000007f;
checkreg ASTAT, (0x18304890 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
pass
|
stsp/binutils-ia16
| 12,557
|
sim/testsuite/bfin/se_illegalcombination.S
|
//Original:/proj/frio/dv/testcases/seq/se_illegalcombination/se_illegalcombination.dsp
// Description: Multi-issue Illegal Combinations
# mach: bfin
# sim: --environment operating
# xfail: "missing a few checks; hardware doesnt seem to match PRM?" *-*
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x100 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
A0 = 0; // reset accumulators
A1 = 0;
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Slot 0 can only be LDST LOAD with search instruction (2 instrs)
.dw 0xcc0d //(R0,R1)=SEARCH R2(GT)||[P0]=R3||NOP;
.dw 0x0210
.dw 0x9303
.dw 0x0000
// (r0,r1) = search r2 gt, nop, r3 = [i0]; // nop supposedly ok
( R0 , R1 ) = SEARCH R2 (GT) || R4 = [ P0 ++ P1 ] || NOP;
// only nop or dspLDST allowed in slot 1 (1 instr)
// a0 = r0, nop, [p0] = r3;
.dw 0xCC09; // can't assemble
.dw 0x2000;
.dw 0x0000;
.dw 0x9303;
// Slot 0 illegal opcodes (1 instr)
// a0 = r0, raise 15, nop;
.dw 0xCC09; // can't assemble
.dw 0x2000;
.dw 0x009F;
.dw 0x0000;
// multiissue with two stores (8 instrs)
.dw 0xcc09 //A0=R0||W[P3]=R5.L||[I0]=R4;
.dw 0x2000
.dw 0x8b5b
.dw 0x9f04
.dw 0xcc09 //A0=R0||[I2]=R2||[I0]=R4;
.dw 0x2000
.dw 0x9f12
.dw 0x9f04
.dw 0xcc09 //A0=R0||[P3]=R0||[I0]=R4;
.dw 0x2000
.dw 0x9318
.dw 0x9f04
.dw 0xcc09 //A0=R0||[P3]=P0||[I0]=R4;
.dw 0x2000
.dw 0x9358
.dw 0x9f04
.dw 0xcc09 //A0=R0||[FP+-36]=R0||[I0]=R4;
.dw 0x2000
.dw 0xbb70
.dw 0x9f04
.dw 0xcc09 //A0=R0||[FP+-48]=P0||[I0]=R4;
.dw 0x2000
.dw 0xbb48
.dw 0x9f04
.dw 0xcc09 //A0=R0||[P3+0x20]=R1||[I0]=R4;
.dw 0x2000
.dw 0xb219
.dw 0x9f04
.dw 0xcc09 //A0=R0||[P3+0x20]=P1||[I0]=R4;
.dw 0x2000
.dw 0xbe19
.dw 0x9f04
// multiissue two instructions can't modify same ireg (6 instrs)
.dw 0xcc09 //A0=R0||I0+=M1(BREV)||R1.L=W[I0++];
.dw 0x2000
.dw 0x9ee4
.dw 0x9c21
.dw 0xcc09 //A0=R0||I1-=M3||R0=[I1++M3];
.dw 0x2000
.dw 0x9e7d
.dw 0x9de8
.dw 0xcc09 //A0=R0||I2+=2||W[I2++]=R0.L;
.dw 0x2000
.dw 0x9f62
.dw 0x9e30
.dw 0xcc09 //A0=R0||I3-=4||[I3++M1]=R7;
.dw 0x2000
.dw 0x9f6f
.dw 0x9fbf
.dw 0xcc09 //A0=R0||R1.L=W[I1++]||W[I1++]=R2.L;
.dw 0x2000
.dw 0x9c29
.dw 0x9e2a
.dw 0xcc09 //A0=R0||[I2++M3]=R7||R6=[I2++M0];
.dw 0x2000
.dw 0x9ff7
.dw 0x9d96
// multiissue two instructions can't load same dreg (9 instrs)
.dw 0xcc09 //A0=R0||R0.L=W[P0++P2]||R0=[I0++];
.dw 0x2000
.dw 0x8210
.dw 0x9c00
.dw 0xcc09 //A0=R0||R1=W[P0++P3](X)||R1.L=W[I2];
.dw 0x2000
.dw 0x8e58
.dw 0x9d31
.dw 0xcc09 //A0=R0||R2=W[P0++P3](X)||R2=[I1++M3];
.dw 0x2000
.dw 0x8e98
.dw 0x9dea
.dw 0xcc09 //A0=R0||R3=[I0++]||R3=[I1++];
.dw 0x2000
.dw 0x9c03
.dw 0x9c0b
.dw 0xcc09 //A0=R0||R4.L=W[I2]||R4.L=W[I3];
.dw 0x2000
.dw 0x9d34
.dw 0x9d3c
.dw 0xcc09 //A0=R0||R5=[I1++M3]||R5.L=W[I2++];
.dw 0x2000
.dw 0x9ded
.dw 0x9c35
.dw 0xcc09 //A0=R0||R6=[P0]||R6=[I0++];
.dw 0x2000
.dw 0x9106
.dw 0x9c06
.dw 0xcc09 //A0=R0||R7=[FP+-56]||R7.L=W[I1];
.dw 0x2000
.dw 0xb927
.dw 0x9d2f
.dw 0xcc09 //A0=R0||R0=W[P1+0x1e](X)||R0=[I0++];
.dw 0x2000
.dw 0xabc8
.dw 0x9c00
// dsp32alu instructions with one dest and slot 0 multi with same dest (1 ins)
.dw 0xcc00 //R0=R2+|+R3||R0=W[P1+0x1e](X)||NOP;
.dw 0x0013
.dw 0xabc8
.dw 0x0000
// other slot 0 dreg cases already covered
// dsp32alu one dest and slot 1 multi with same dest (1 ins)
.dw 0xcc18 //R1=BYTEPACK(R4,R5)||NOP||R1.L=W[I2];
.dw 0x0225
.dw 0x0000
.dw 0x9d31
// other slot 1 dreg dest cases already covered
// dsp32alu dual dests and slot 0 multi with either same dest (2 instrs)
.dw 0xcc18 //(R2,R3)=BYTEUNPACKR1:0||R2=W[P0++P3](X)||NOP;
.dw 0x4680
.dw 0x8e98
.dw 0x0000
.dw 0xcc01 //R2=R2+|+R3,R3=R2-|-R3||R3=[P3]||NOP;
.dw 0x0693
.dw 0x911b
.dw 0x0000
// dsp32alu dual dests and slot 1 multi with either same dest (2 instrs)
.dw 0xcc18 //(R4,R5)=BYTEUNPACKR1:0||NOP||R4=[I1++M3];
.dw 0x4b00
.dw 0x0000
.dw 0x9dec
.dw 0xcc01 //R4=R2+|+R3,R5=R2-|-R3||NOP||R5.L=W[I2++];
.dw 0x0b13
.dw 0x0000
.dw 0x9c35
// dsp32shift one dest and slot 0 multi with same dest (1 instruction)
.dw 0xce0d //R6=ALIGN8(R4,R5)||R6=[P0]||NOP;
.dw 0x0c2c
.dw 0x9106
.dw 0x0000
// dsp32shift one dest and slot 1 multi with same dest (1 instruction)
.dw 0xce00 //R7.L=ASHIFTR0.HBYR7.L||NOP||R7.L=W[I1];
.dw 0x1e38
.dw 0x0000
.dw 0x9d2f
// dsp32shift two dests and slot 0 multi with either same dest (2 instrs)
.dw 0xce08 //BITMUX(R0,R1,A0)(ASR)||R0.L=W[P0++P2]||NOP;
.dw 0x0001
.dw 0x8210
.dw 0x0000
.dw 0xce08 //BITMUX(R2,R3,A0)(ASL)||R3=[I0++]||NOP;
.dw 0x4013
.dw 0x9c03
.dw 0x0000
// dsp32shift two dests and slot 1 multi with either same dest (2 instrs)
.dw 0xce08 //BITMUX(R4,R5,A0)(ASR)||NOP||R4.H=W[I3];
.dw 0x0025
.dw 0x0000
.dw 0x9d5c
.dw 0xce08 //BITMUX(R6,R7,A0)(ASL)||NOP||R7.L=W[I1];
.dw 0x4037
.dw 0x0000
.dw 0x9d2f
// dsp32shiftimm one dest and slot 0 with same dest (1 instr)
.dw 0xce80 //R1.L=R0.H<<0x7||R1=W[P0++P3](X)||NOP;
.dw 0x1238
.dw 0x8e58
.dw 0x0000
// dsp32shiftimm one dest and slot 1 with same dest (1 instr)
.dw 0xce81 //R5=R2<<0x9(V)||NOP||R5.L=W[I2++];
.dw 0x0a4a
.dw 0x0000
.dw 0x9c35
// dsp32mac one dest and slot 0 multi with same dest (1 inst)
.dw 0xc805 //A0+=R1.H*R0.L,R6.H=(A1+=R1.L*R0.H)||R6=W[P0++P3](X)||NOP;
.dw 0x4d88
.dw 0x8f98
.dw 0x0000
// dsp32mult one dest and slot 0 multi with same dest (1 inst)
.dw 0xca04 //R7.H=R3.L*R4.H||R7=[FP+-56]||NOP;
.dw 0x41dc
.dw 0xb927
.dw 0x0000
// dsp32 mac one dest and slot 1 multi with same dest (1 inst)
.dw 0xc805 //A0+=R1.H*R0.L,R0.H=(A1+=R1.L*R0.H)||NOP||R0=[I0++];
.dw 0x4c08
.dw 0x0000
.dw 0x9c00
// dsp32mult one dest and slot 1 multi with same dest (1 inst)
.dw 0xca04 //R1.H=R3.L*R4.H||NOP||R1.H=W[I1];
.dw 0x405c
.dw 0x0000
.dw 0x9d49
// dsp32mac write to register pair and slot 0 same dest - even (1 instr)
.dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||R2=W[P0++P3](X)||NOP;
.dw 0x6c88
.dw 0x8e98
.dw 0x0000
// dsp32mult write to register pair and slot 0 same dest - even (1 instr)
.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R4=[P0++P1]||NOP;
.dw 0x6508
.dw 0x8108
.dw 0x0000
// dsp32mac write to register pair and slot 1 same dest - even (1 instr)
.dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||NOP||R2=[I1++M3];
.dw 0x6c88
.dw 0x0000
.dw 0x9dea
// dsp32mult write to register pair and slot 1 same dest - even (1 instr)
.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R4=[I1++M3];
.dw 0x6508
.dw 0x0000
.dw 0x9dec
// dsp32mac write to register pair and slot 0 same dest - odd (1 instr)
.dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||R3=W[P0++P3](X)||NOP;
.dw 0x4c88
.dw 0x8ed8
.dw 0x0000
// dsp32mult write to register pair and slot 0 same dest - odd (1 instr)
.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R5=[P0++P1]||NOP;
.dw 0x6508
.dw 0x8148
.dw 0x0000
// dsp32mac write to register pair and slot 1 same dest - odd (1 instr)
.dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||NOP||R3=[I1++M3];
.dw 0x4c88
.dw 0x0000
.dw 0x9deb
// dsp32mult write to register pair and slot 1 same dest - odd (1 instr)
.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R5=[I1++M3];
.dw 0x6508
.dw 0x0000
.dw 0x9ded
// CHECKER
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
// Xhandler counts all EXCAUSE = 0x22;
CHECKREG(r5, 53); // count of all Illegal Combination Exceptions.
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
// 16 bit illegal opcode handler - skips bad instruction
[ -- SP ] = ASTAT; // save what we damage
[ -- SP ] = ( R7:6 );
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x22; // EXCAUSE 0x22 means I-Fetch Undefined Instruction
CC = r7 == r6;
IF CC JUMP ILLEGALCOMBINATION; // If EXCAUSE != 0x22 then leave
dbg_fail;
JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop
ILLEGALCOMBINATION:
R7 = RETX; // Fix up return address
R7 += 8; // skip offending 64 bit instruction
RETX = r7; // and put back in RETX
R5 += 1; // Increment global counter
OUT:
( R7:6 ) = [ SP ++ ];
ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 8,703
|
sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn.s
|
//Original:/testcases/core/c_dsp32shiftim_ahalf_rn/c_dsp32shiftim_ahalf_rn.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = R0.L >>> 10;
R1.L = R1.L >>> 10;
R2.L = R2.L >>> 10;
R3.L = R3.L >>> 10;
R4.L = R4.L >>> 10;
R5.L = R5.L >>> 10;
R6.L = R6.L >>> 10;
R7.L = R7.L >>> 10;
CHECKREG r0, 0x0000FFFF;
CHECKREG r1, 0x0000FFE0;
CHECKREG r2, 0x0000FFE0;
CHECKREG r3, 0x0000FFE0;
CHECKREG r4, 0x0000FFE0;
CHECKREG r5, 0x0000FFE0;
CHECKREG r6, 0x0000FFE0;
CHECKREG r7, 0x0000FFE0;
imm32 r0, 0x02008020;
imm32 r0, 0x02008021;
imm32 r2, 0x02008022;
imm32 r3, 0x02008023;
imm32 r4, 0x02008024;
imm32 r5, 0x02008025;
imm32 r6, 0x02008026;
imm32 r7, 0x02008027;
R0.L = R0.L >>> 11;
R1.L = R1.L >>> 11;
R2.L = R2.L >>> 11;
R3.L = R3.L >>> 11;
R4.L = R4.L >>> 11;
R5.L = R5.L >>> 11;
R6.L = R6.L >>> 11;
R7.L = R7.L >>> 11;
CHECKREG r0, 0x0200FFF0;
CHECKREG r1, 0x0000FFFF;
CHECKREG r2, 0x0200FFF0;
CHECKREG r3, 0x0200FFF0;
CHECKREG r4, 0x0200FFF0;
CHECKREG r5, 0x0200FFF0;
CHECKREG r6, 0x0200FFF0;
CHECKREG r7, 0x0200FFF0;
imm32 r0, 0x00308001;
imm32 r1, 0x00308001;
R2.L = -15;
imm32 r3, 0x00308003;
imm32 r4, 0x00308004;
imm32 r5, 0x00308005;
imm32 r6, 0x00308006;
imm32 r7, 0x00308007;
R0.L = R0.L >>> 12;
R1.L = R1.L >>> 12;
R2.L = R2.L >>> 12;
R3.L = R3.L >>> 12;
R4.L = R4.L >>> 12;
R5.L = R5.L >>> 12;
R6.L = R6.L >>> 12;
R7.L = R7.L >>> 12;
CHECKREG r0, 0x0030FFF8;
CHECKREG r1, 0x0030FFF8;
CHECKREG r2, 0x0200FFFF;
CHECKREG r3, 0x0030FFF8;
CHECKREG r4, 0x0030FFF8;
CHECKREG r5, 0x0030FFF8;
CHECKREG r6, 0x0030FFF8;
CHECKREG r7, 0x0030FFF8;
imm32 r0, 0x00008401;
imm32 r1, 0x00008401;
imm32 r2, 0x00008402;
R3.L = -16;
imm32 r4, 0x00008404;
imm32 r5, 0x00008405;
imm32 r6, 0x00008406;
imm32 r7, 0x00008407;
R0.L = R0.L >>> 3;
R1.L = R1.L >>> 3;
R2.L = R2.L >>> 3;
R3.L = R3.L >>> 3;
R4.L = R4.L >>> 3;
R5.L = R5.L >>> 3;
R6.L = R6.L >>> 3;
R7.L = R7.L >>> 3;
CHECKREG r0, 0x0000F080;
CHECKREG r1, 0x0000F080;
CHECKREG r2, 0x0000F080;
CHECKREG r3, 0x0030FFFE;
CHECKREG r4, 0x0000F080;
CHECKREG r5, 0x0000F080;
CHECKREG r6, 0x0000F080;
CHECKREG r7, 0x0000F080;
// d_lo = ashift (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x05000500;
imm32 r1, 0x85010500;
imm32 r2, 0x85020500;
imm32 r3, 0x85030500;
imm32 r4, 0x85040500;
imm32 r5, 0x85050500;
imm32 r6, 0x85060500;
imm32 r7, 0x85070500;
R0.L = R0.H >>> 10;
R1.L = R1.H >>> 10;
R2.L = R2.H >>> 10;
R3.L = R3.H >>> 10;
R4.L = R4.H >>> 10;
R5.L = R5.H >>> 10;
R6.L = R6.H >>> 10;
R7.L = R7.H >>> 10;
CHECKREG r0, 0x05000001;
CHECKREG r1, 0x8501FFE1;
CHECKREG r2, 0x8502FFE1;
CHECKREG r3, 0x8503FFE1;
CHECKREG r4, 0x8504FFE1;
CHECKREG r5, 0x8505FFE1;
CHECKREG r6, 0x8506FFE1;
CHECKREG r7, 0x8507FFE1;
imm32 r0, 0x80610000;
R1.L = -1;
imm32 r2, 0x80620000;
imm32 r3, 0x80630000;
imm32 r4, 0x80640000;
imm32 r5, 0x80650000;
imm32 r6, 0x80660000;
imm32 r7, 0x80670000;
R0.L = R0.H >>> 11;
R1.L = R1.H >>> 11;
R2.L = R2.H >>> 11;
R3.L = R3.H >>> 11;
R4.L = R4.H >>> 11;
R5.L = R5.H >>> 11;
R6.L = R6.H >>> 11;
R7.L = R7.H >>> 11;
CHECKREG r0, 0x8061FFF0;
CHECKREG r1, 0x8501FFF0;
CHECKREG r2, 0x8062FFF0;
CHECKREG r3, 0x8063FFF0;
CHECKREG r4, 0x8064FFF0;
CHECKREG r5, 0x8065FFF0;
CHECKREG r6, 0x8066FFF0;
CHECKREG r7, 0x8067FFF0;
imm32 r0, 0xa0010070;
imm32 r1, 0xa0010070;
R2.L = -15;
imm32 r3, 0xa0030070;
imm32 r4, 0xa0040070;
imm32 r5, 0xa0050070;
imm32 r6, 0xa0060070;
imm32 r7, 0xa0070070;
R0.L = R0.H >>> 12;
R1.L = R1.H >>> 12;
R2.L = R2.H >>> 12;
R3.L = R3.H >>> 12;
R4.L = R4.H >>> 12;
R5.L = R5.H >>> 12;
R6.L = R6.H >>> 12;
R7.L = R7.H >>> 12;
CHECKREG r0, 0xA001FFFA;
CHECKREG r1, 0xA001FFFA;
CHECKREG r2, 0x8062FFF8;
CHECKREG r3, 0xA003FFFA;
CHECKREG r4, 0xA004FFFA;
CHECKREG r5, 0xA005FFFA;
CHECKREG r6, 0xA006FFFA;
CHECKREG r7, 0xA007FFFA;
imm32 r0, 0xb8010001;
imm32 r1, 0xb8010001;
imm32 r2, 0xb8020002;
R3.L = -16;
imm32 r4, 0xb8040004;
imm32 r5, 0xb8050005;
imm32 r6, 0xb8060006;
imm32 r7, 0xb8070007;
R0.L = R0.H >>> 13;
R1.L = R1.H >>> 13;
R2.L = R2.H >>> 13;
R3.L = R3.H >>> 13;
R4.L = R4.H >>> 13;
R5.L = R5.H >>> 13;
R6.L = R6.H >>> 13;
R7.L = R7.H >>> 13;
CHECKREG r0, 0xB801FFFD;
CHECKREG r1, 0xB801FFFD;
CHECKREG r2, 0xB802FFFD;
CHECKREG r3, 0xA003FFFD;
CHECKREG r4, 0xB804FFFD;
CHECKREG r5, 0xB805FFFD;
CHECKREG r6, 0xB806FFFD;
CHECKREG r7, 0xB807FFFD;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00009001;
imm32 r1, 0x00009001;
imm32 r2, 0x00009002;
imm32 r3, 0x00009003;
imm32 r4, 0x00009000;
imm32 r5, 0x00009005;
imm32 r6, 0x00009006;
imm32 r7, 0x00009007;
R0.H = R0.L >>> 14;
R1.H = R1.L >>> 14;
R2.H = R2.L >>> 14;
R3.H = R3.L >>> 14;
R4.H = R4.L >>> 14;
R5.H = R5.L >>> 14;
R6.H = R6.L >>> 14;
R7.H = R7.L >>> 14;
CHECKREG r0, 0xFFFE9001;
CHECKREG r1, 0xFFFE9001;
CHECKREG r2, 0xFFFE9002;
CHECKREG r3, 0xFFFE9003;
CHECKREG r4, 0xFFFE9000;
CHECKREG r5, 0xFFFE9005;
CHECKREG r6, 0xFFFE9006;
CHECKREG r7, 0xFFFE9007;
imm32 r0, 0xa0008001;
imm32 r1, 0xa0008001;
imm32 r2, 0xa0008002;
imm32 r3, 0xa0008003;
imm32 r4, 0xa0008004;
R5.L = -1;
imm32 r6, 0xa0008006;
imm32 r7, 0xa0008007;
R0.H = R0.L >>> 5;
R1.H = R1.L >>> 5;
R2.H = R2.L >>> 5;
R3.H = R3.L >>> 5;
R4.H = R4.L >>> 5;
R5.H = R5.L >>> 5;
R6.H = R6.L >>> 5;
R7.H = R7.L >>> 5;
CHECKREG r0, 0xFC008001;
CHECKREG r1, 0xFC008001;
CHECKREG r2, 0xFC008002;
CHECKREG r3, 0xFC008003;
CHECKREG r4, 0xFC008004;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFC008006;
CHECKREG r7, 0xFC008007;
imm32 r0, 0x00009b01;
imm32 r1, 0x00009b01;
imm32 r2, 0x00009b02;
imm32 r3, 0x00009b03;
imm32 r4, 0x00009b04;
imm32 r5, 0x00009b05;
R6.L = -15;
imm32 r7, 0x00009007;
R0.H = R0.L >>> 6;
R1.H = R1.L >>> 6;
R2.H = R2.L >>> 6;
R3.H = R3.L >>> 6;
R4.H = R4.L >>> 6;
R5.H = R5.L >>> 6;
R6.H = R6.L >>> 6;
R7.H = R7.L >>> 6;
CHECKREG r0, 0xFE6C9B01;
CHECKREG r1, 0xFE6C9B01;
CHECKREG r2, 0xFE6C9B02;
CHECKREG r3, 0xFE6C9B03;
CHECKREG r4, 0xFE6C9B04;
CHECKREG r5, 0xFE6C9B05;
CHECKREG r6, 0xFFFFFFF1;
CHECKREG r7, 0xFE409007;
imm32 r0, 0x0000a0c1;
imm32 r1, 0x0000a0c1;
imm32 r2, 0x0000a0c2;
imm32 r3, 0x0000a0c3;
imm32 r4, 0x0000a0c4;
imm32 r5, 0x0000a0c5;
imm32 r6, 0x0000a0c6;
R7.L = -16;
R0.H = R0.L >>> 7;
R1.H = R1.L >>> 7;
R2.H = R2.L >>> 7;
R3.H = R3.L >>> 7;
R4.H = R4.L >>> 7;
R5.H = R5.L >>> 7;
R6.H = R6.L >>> 7;
R7.H = R7.L >>> 7;
CHECKREG r0, 0xFF41A0C1;
CHECKREG r1, 0xFF41A0C1;
CHECKREG r2, 0xFF41A0C2;
CHECKREG r3, 0xFF41A0C3;
CHECKREG r4, 0xFF41A0C4;
CHECKREG r5, 0xFF41A0C5;
CHECKREG r6, 0xFF41A0C6;
CHECKREG r7, 0xFFFFFFF0;
imm32 r0, 0x80010d00;
imm32 r1, 0x80010d00;
imm32 r2, 0x80020d00;
imm32 r3, 0x80030d00;
R4.L = -1;
imm32 r5, 0x80050d00;
imm32 r6, 0x80060d00;
imm32 r7, 0x80070d00;
R0.H = R0.H >>> 14;
R1.H = R1.H >>> 14;
R2.H = R2.H >>> 14;
R3.H = R3.H >>> 14;
R4.H = R4.H >>> 14;
R5.H = R5.H >>> 14;
R6.H = R6.H >>> 14;
R7.H = R7.H >>> 14;
CHECKREG r0, 0xFFFE0D00;
CHECKREG r1, 0xFFFE0D00;
CHECKREG r2, 0xFFFE0D00;
CHECKREG r3, 0xFFFE0D00;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFE0D00;
CHECKREG r6, 0xFFFE0D00;
CHECKREG r7, 0xFFFE0D00;
imm32 r0, 0x8d010000;
imm32 r1, 0x8d010000;
imm32 r2, 0x8d020000;
imm32 r3, 0x8d030000;
imm32 r4, 0x8d040000;
R5.L = -1;
imm32 r6, 0x8d060000;
imm32 r7, 0x8d070000;
R0.H = R0.H >>> 15;
R1.H = R1.H >>> 15;
R2.H = R2.H >>> 15;
R3.H = R3.H >>> 15;
R4.H = R4.H >>> 15;
R5.H = R5.H >>> 15;
R6.H = R6.H >>> 15;
R7.H = R7.H >>> 15;
CHECKREG r0, 0xFFFF0000;
CHECKREG r1, 0xFFFF0000;
CHECKREG r2, 0xFFFF0000;
CHECKREG r3, 0xFFFF0000;
CHECKREG r4, 0xFFFF0000;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFF0000;
CHECKREG r7, 0xFFFF0000;
imm32 r0, 0xde010000;
imm32 r1, 0xde010000;
imm32 r2, 0xde020000;
imm32 r3, 0xde030000;
imm32 r4, 0xde040000;
imm32 r5, 0xde050000;
R6.L = -15;
imm32 r7, 0xd0070000;
R0.L = R0.H >>> 10;
R1.L = R1.H >>> 10;
R2.L = R2.H >>> 10;
R3.L = R3.H >>> 10;
R4.L = R4.H >>> 10;
R5.L = R5.H >>> 10;
R6.L = R6.H >>> 10;
R7.L = R7.H >>> 10;
CHECKREG r0, 0xDE01FFF7;
CHECKREG r1, 0xDE01FFF7;
CHECKREG r2, 0xDE02FFF7;
CHECKREG r3, 0xDE03FFF7;
CHECKREG r4, 0xDE04FFF7;
CHECKREG r5, 0xDE05FFF7;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xD007FFF4;
imm32 r0, 0x9f010c00;
imm32 r1, 0xaf010c00;
imm32 r2, 0xbf020c00;
imm32 r3, 0xcf030c00;
imm32 r4, 0xdf040c00;
imm32 r5, 0xef050c00;
imm32 r6, 0xff060c00;
R7.L = -16;
R0.H = R0.H >>> 5;
R1.H = R1.H >>> 5;
R2.H = R2.H >>> 5;
R3.H = R3.H >>> 5;
R4.H = R4.H >>> 5;
R5.H = R5.H >>> 5;
R6.H = R6.H >>> 5;
R7.H = R7.H >>> 5;
CHECKREG r0, 0xFCF80C00;
CHECKREG r1, 0xFD780C00;
CHECKREG r2, 0xFDF80C00;
CHECKREG r3, 0xFE780C00;
CHECKREG r4, 0xFEF80C00;
CHECKREG r5, 0xFF780C00;
CHECKREG r6, 0xFFF80C00;
CHECKREG r7, 0xFE80FFF0;
pass
|
stsp/binutils-ia16
| 2,876
|
sim/testsuite/bfin/c_dsp32mac_dr_a0_tu.s
|
//Original:/testcases/core/c_dsp32mac_dr_a0_tu/c_dsp32mac_dr_a0_tu.dsp
// Spec Reference: dsp32mac dr a0 tu (truncate unsigned fraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xf3545abd;
imm32 r1, 0x7fbcfec7;
imm32 r2, 0xc7fff679;
imm32 r3, 0xd0799007;
imm32 r4, 0xefb79f69;
imm32 r5, 0xcd35700b;
imm32 r6, 0xe00c87fd;
imm32 r7, 0xf78e909f;
A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (TFU);
R1 = A0.w;
A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (TFU);
R3 = A0.w;
A1 += R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ) (TFU);
R5 = A0.w;
A1 += R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (TFU);
R7 = A0.w;
CHECKREG r0, 0xF3545A4E;
CHECKREG r1, 0x5A4E0EEB;
CHECKREG r2, 0xC7FF0000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xEFB70000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0xE00C8380;
CHECKREG r7, 0x83808956;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0xc5548abd;
imm32 r1, 0x9b5cfec7;
imm32 r2, 0xa9b55679;
imm32 r3, 0xb09b5007;
imm32 r4, 0xcfb9b5c9;
imm32 r5, 0x52359b5c;
imm32 r6, 0xe50c5098;
imm32 r7, 0x675e7509;
R0.L = ( A0 = R1.L * R0.L ) (TFU);
R1 = A0.w;
R2.L = ( A0 += R2.L * R3.H ) (TFU);
R3 = A0.w;
R4.L = ( A0 = R4.H * R5.L ) (TFU);
R5 = A0.w;
R6.L = ( A0 -= R6.H * R7.H ) (TFU);
R7 = A0.w;
CHECKREG r0, 0xC5548A13;
CHECKREG r1, 0x8A135EEB;
CHECKREG r2, 0xA9B5C5BA;
CHECKREG r3, 0xC5BAEA2E;
CHECKREG r4, 0xCFB97E0F;
CHECKREG r5, 0x7E0FA97C;
CHECKREG r6, 0xE50C2193;
CHECKREG r7, 0x2193BB14;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x4b54babd;
imm32 r1, 0x12346ec7;
imm32 r2, 0xa4bbe679;
imm32 r3, 0x8abdb707;
imm32 r4, 0x9f4b7b69;
imm32 r5, 0xa234877b;
imm32 r6, 0xb00c4887;
imm32 r7, 0xc78ea4b8;
R0.L = ( A0 -= R1.L * R0.L ) (TFU);
R1 = A0.w;
R2.L = ( A0 = R2.H * R3.L ) (TFU);
R3 = A0.w;
R4.L = ( A0 -= R4.H * R5.H ) (TFU);
R5 = A0.w;
R6.L = ( A0 += R6.L * R7.H ) (TFU);
R7 = A0.w;
CHECKREG r0, 0x4B540000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xA4BB75C6;
CHECKREG r3, 0x75C62E1D;
CHECKREG r4, 0x9F4B10D8;
CHECKREG r5, 0x10D85CE1;
CHECKREG r6, 0xB00C4961;
CHECKREG r7, 0x496188C3;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x1a545abd;
imm32 r1, 0x42fcfec7;
imm32 r2, 0xc53f5679;
imm32 r3, 0x9c64f007;
imm32 r4, 0xafc7ec69;
imm32 r5, 0xd23c891b;
imm32 r6, 0xc00cc602;
imm32 r7, 0x678edc7e;
A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (TFU);
R3 = A0.w;
A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (TFU);
R7 = A0.w;
A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (TFU);
R5 = A0.w;
A1 -= R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (TFU);
R1 = A0.w;
CHECKREG r0, 0x1A5498EA;
CHECKREG r1, 0x98EA3745;
CHECKREG r2, 0xC53FA3AF;
CHECKREG r3, 0xA3AF97AE;
CHECKREG r4, 0xAFC7905A;
CHECKREG r5, 0x905A70A4;
CHECKREG r6, 0xC00C2ED1;
CHECKREG r7, 0x2ED15DDC;
pass
|
stsp/binutils-ia16
| 3,683
|
sim/testsuite/bfin/max_min_flags.s
|
// Check Flag Settings for MAX/MIN
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
r0=1;
r1= -1;
r2=min(r1,r0);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x2);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0xffff);
dbga (r2.h, 0xffff);
r2=min(r0,r1);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x2);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0xffff);
dbga (r2.h, 0xffff);
r2=max(r1,r0);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x0);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x1);
dbga (r2.h, 0x0);
r2=max(r0,r1);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x0);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x1);
dbga (r2.h, 0x0);
r0.h=1;
r2=min(r1,r0) (v);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x2);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0xffff);
dbga (r2.h, 0xffff);
r2=min(r0,r1) (v);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x2);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0xffff);
dbga (r2.h, 0xffff);
r2=max(r1,r0) (v);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x0);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x1);
dbga (r2.h, 0x1);
r2=max(r0,r1) (v);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x0);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x1);
dbga (r2.h, 0x1);
r0=0;
r2=max(r1,r0);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x1);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 1);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x0);
dbga (r2.h, 0x0);
r0.h=1;
r2=max(r1,r0) (v);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x1);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 1);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x0);
dbga (r2.h, 0x1);
pass
|
stsp/binutils-ia16
| 12,527
|
sim/testsuite/bfin/c_ldstidxl_st_preg.s
|
//Original:testcases/core/c_ldstidxl_st_preg/c_ldstidxl_st_preg.dsp
// Spec Reference: c_ldstidxl store preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
P3 = 0x0123 (X);
P4 = 0x4567 (X);
P5 = 0x79ab (X);
FP = 0x6def (X);
SP = 0x1ace (X);
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x0000;
loadsym p2, DATA_ADDR_2, 0x00c8;
P3 = I1; SP = I3;
[ P1 + 0x1004 ] = P5;
[ P1 + 0x1008 ] = P3;
[ P1 + 0x1014 ] = P4;
[ P1 + 0x1018 ] = P3;
[ P2 + -0x1020 ] = P4;
[ P2 + -0x1024 ] = P5;
[ P2 + -0x1028 ] = SP;
[ P2 + -0x1034 ] = FP;
R6 = [ P1 + 0x1004 ];
R5 = [ P1 + 0x1008 ];
R4 = [ P1 + 0x1014 ];
R3 = [ P1 + 0x1018 ];
R2 = [ P2 + -0x1020 ];
R7 = [ P2 + -0x1024 ];
R0 = [ P2 + -0x1028 ];
R1 = [ P2 + -0x1034 ];
CHECKREG r0, 0x00001ACE;
CHECKREG r1, 0x00006DEF;
CHECKREG r2, 0x00004567;
CHECKREG r3, 0x00000123;
CHECKREG r4, 0x00004567;
CHECKREG r5, 0x00000123;
CHECKREG r6, 0x000079AB;
CHECKREG r7, 0x000079AB;
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
P1 = 0x3456 (X);
P2 = 0x1234 (X);
P5 = 0x5e23 (X);
FP = 0x2ac5 (X);
SP = 0x6378 (X);
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i1, DATA_ADDR_1, 0x0000;
loadsym p4, DATA_ADDR_2, 0x00c8;
P3 = I1; SP = I3;
[ P3 + 0x1034 ] = P2;
[ P3 + 0x1040 ] = P1;
[ P3 + 0x1044 ] = P2;
[ P3 + 0x1048 ] = P1;
[ P4 + -0x1054 ] = P2;
[ P4 + -0x1058 ] = P5;
[ P4 + -0x1060 ] = SP;
[ P4 + -0x1064 ] = FP;
R3 = [ P3 + 0x1034 ];
R4 = [ P3 + 0x1040 ];
R0 = [ P3 + 0x1044 ];
R1 = [ P3 + 0x1048 ];
R2 = [ P4 + -0x1054 ];
R5 = [ P4 + -0x1058 ];
R6 = [ P4 + -0x1060 ];
R7 = [ P4 + -0x1064 ];
CHECKREG r0, 0x00001234;
CHECKREG r1, 0x00003456;
CHECKREG r2, 0x00001234;
CHECKREG r3, 0x00001234;
CHECKREG r4, 0x00003456;
CHECKREG r5, 0x00005E23;
CHECKREG r6, 0x00006378;
CHECKREG r7, 0x00002AC5;
// initial values
imm32 r0, 0x10cf50c0;
imm32 r1, 0x20ce60c1;
imm32 r2, 0x30c370c2;
imm32 r3, 0x40cc80c3;
imm32 r4, 0x50cb90c4;
imm32 r5, 0x60caa0c5;
imm32 r6, 0x70c9b0c6;
imm32 r7, 0xd0c8c0c7;
P1 = 0x2125 (X);
P2 = 0x7345 (X);
P3 = 0x3230 (X);
P4 = 0x5789 (X);
FP = 0x5bcd (X);
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x0000;
loadsym i3, DATA_ADDR_2, 0x00c8;
P3 = I1; SP = I3;
[ P5 + 0x1004 ] = P2;
[ P5 + 0x1008 ] = P1;
[ P5 + 0x1014 ] = P2;
[ P5 + 0x1018 ] = P3;
[ SP + -0x1020 ] = P4;
[ SP + -0x1024 ] = P2;
[ SP + -0x1028 ] = P3;
[ SP + -0x1034 ] = FP;
R6 = [ P5 + 0x1004 ];
R5 = [ P5 + 0x1008 ];
R4 = [ P5 + 0x1014 ];
R3 = [ P5 + 0x1018 ];
R2 = [ SP + -0x1020 ];
R0 = [ SP + -0x1024 ];
R7 = [ SP + -0x1028 ];
R1 = [ SP + -0x1034 ];
CHECKREG r0, 0x00007345;
CHECKREG r1, 0x00005BCD;
CHECKREG r2, 0x00005789;
CHECKREG r3, 0x00003230;
CHECKREG r4, 0x00007345;
CHECKREG r5, 0x00002125;
CHECKREG r6, 0x00007345;
CHECKREG r7, 0x00003230;
// initial values
imm32 r0, 0x60df50d0;
imm32 r1, 0x70de60d1;
imm32 r2, 0x80dd70d2;
imm32 r3, 0x90dc80d3;
imm32 r4, 0xa0db90d4;
imm32 r5, 0xb0daa0d5;
imm32 r6, 0xc0d9b0d6;
imm32 r7, 0xd0d8c0d7;
P1 = 0x5bcd (X);
P2 = 0x1122 (X);
P3 = 0x3455 (X);
P4 = 0x6677 (X);
P5 = 0x58ab (X);
SP = 0x1ace (X);
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0x0010;
P3 = I1; SP = I3;
[ FP + 0x1034 ] = P1;
[ FP + 0x2040 ] = P1;
[ FP + 0x1144 ] = P2;
[ FP + 0x2048 ] = P3;
[ FP + 0x1050 ] = P4;
[ FP + 0x2058 ] = P5;
[ FP + 0x1160 ] = P2;
[ FP + 0x2064 ] = SP;
R3 = [ FP + 0x1034 ];
R4 = [ FP + 0x2040 ];
R0 = [ FP + 0x1144 ];
R1 = [ FP + 0x2048 ];
R2 = [ FP + 0x1050 ];
R5 = [ FP + 0x2058 ];
R6 = [ FP + 0x1160 ];
R7 = [ FP + 0x2064 ];
CHECKREG r0, 0x00001122;
CHECKREG r1, 0x00003455;
CHECKREG r2, 0x00006677;
CHECKREG r3, 0x00005BCD;
CHECKREG r4, 0x00005BCD;
CHECKREG r5, 0x000058AB;
CHECKREG r6, 0x00001122;
CHECKREG r7, 0x00001ace;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
// Make sure there is space between the text and data sections
.space (0x2000);
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_2:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
// Make sure there is space for us to scribble
.space (0x2000);
|
stsp/binutils-ia16
| 11,605
|
sim/testsuite/bfin/dbg_jmp_src_kill.S
|
//Original:/proj/frio/dv/testcases/debug/dbg_jmp_src_kill/dbg_jmp_src_kill.dsp
// Description: This test checks that the trace buffer keeps track of a JUMP
// source instruction getting killed at each stage in the pipe. The test
// consists of 8 instances of an EXCPT instruction followed by 0 to 7 NOPs
// and a JUMP, with the trace buffer enabled.
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000020
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
// Save all the registers used in the ISR
[ -- SP ] = R0;
[ -- SP ] = R1;
[ -- SP ] = P0;
[ -- SP ] = P1;
[ -- SP ] = LC0;
[ -- SP ] = LB0;
[ -- SP ] = LT0;
[ -- SP ] = ASTAT;
// Get EXCAUSE bits out of SEQSTAT
R0 = SEQSTAT;
R0 = R0 << 26;
R0 = R0 >> 26;
// Check for Trace Exception
// Load r1 with EXCAUSE for Trace Exception
R1 = 0x0011 (Z);
// Check for Trace Exception
CC = R0 == R1;
// Branch to OUT if the EXCAUSE is not TRACE.
IF !CC JUMP OUT;
// Read out the Trace Buffer.
LD32(p0, TBUFSTAT);
// Read TBUFSTAT MMR
P1 = [ P0 ];
// if p1 is zero skip the loop.
CC = P1 == 0;
IF CC JUMP OUT;
// Read out the Entire Trace Buffer.
LD32(p0, TBUF);
LSETUP ( l0s , l0e ) LC0 = P1;
l0s:R0 = [ P0 ];
l0e:R0 = [ P0 ];
OUT:
// Check for other exception, if any.
// Restore all saved registers.
ASTAT = [ SP ++ ];
LT0 = [ SP ++ ];
LB0 = [ SP ++ ];
LC0 = [ SP ++ ];
P1 = [ SP ++ ];
P0 = [ SP ++ ];
R1 = [ SP ++ ];
R0 = [ SP ++ ];
// Return
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow
CSYNC; // Wait for MMR write to complete
EXCPT 1;
JUMP 4; // Jump gets killed in WB stage
NOP;
NOP;
EXCPT 2;
NOP;
JUMP 4; // Jump gets killed in EX3 stage
NOP;
NOP;
EXCPT 3;
NOP;
NOP;
JUMP 4; // Jump gets killed in EX2 stage
NOP;
NOP;
EXCPT 4;
NOP;
NOP;
NOP;
JUMP 4; // Jump gets killed in EX1 stage
NOP;
NOP;
EXCPT 5;
NOP;
NOP;
NOP;
NOP;
JUMP 4; // Jump gets killed in AC stage
NOP;
NOP;
EXCPT 6;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP 4; // Jump gets killed in DEC stage
NOP;
NOP;
EXCPT 7;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP 4; // Jump gets killed in IF2 stage
NOP;
NOP;
EXCPT 8;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP 4; // Jump gets killed in IF1 stage
NOP;
NOP;
// Read out the Rest of the Trace Buffer.
LD32(p0, TBUFSTAT);
// Read TBUFSTAT MMR
P1 = [ P0 ];
// if p1 is zero skip the loop.
CC = P1 == 0;
IF CC JUMP OUT1;
// Read out the Entire Trace Buffer.
LD32(p0, TBUF);
LSETUP ( l1s , l1e ) LC0 = P1;
l1s:R0 = [ P0 ];
l1e:R0 = [ P0 ];
// Don't RTI if you never wish to go to User Mode
// use END_TEST instead.
OUT1:
dbg_pass;
// rti;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
// YOUR USER CODE GOES HERE.
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0x01010101;
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
.dd 0x05050505;
.dd 0x06060606;
.dd 0x07070707;
.dd 0x08080808;
.dd 0x09090909;
.dd 0x0a0a0a0a;
.dd 0x0b0b0b0b;
.dd 0x0c0c0c0c;
.dd 0x0d0d0d0d;
.dd 0x0e0e0e0e;
.dd 0x0f0f0f0f;
// Define Kernal Stack
.section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw"
.space (STACKSIZE);
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 6,433
|
sim/testsuite/bfin/c_mode_user_superivsor.S
|
//Original:/proj/frio/dv/testcases/core/c_mode_user_superivsor/c_mode_user_superivsor.dsp
// Spec Reference: mode_user_supervisor
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
//
////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI; // execute this instr put us in USER mode
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// USER MODE & go to different RAISE in USER mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
RAISE 2; // RTN
RAISE 5; // RTI
RAISE 6; // RTI
RAISE 7; // RTI
RAISE 8; // RTI
RAISE 9; // RTI
RAISE 10; // RTI
RAISE 11; // RTI
RAISE 12; // RTI
RAISE 13; // RTI
RAISE 14; // RTI
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG(r0, 0x00000018);
CHECKREG(r1, 0x00000018);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000018);
CHECKREG(r4, 0x00000000);
CHECKREG(r5, 0x00000000);
CHECKREG(r6, 0x00000000);
CHECKREG(r7, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = RETN;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 += 2;
RETN = r0;
RTN;
XHANDLE: // Exception Handler 3
R0 = RETX;
I0 += 2;
I1 += 2;
I3 += 2;
R0 += 2;
RETX = r0;
RTX;
HWHANDLE: // HW Error Handler 5
R0 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
R0 += 2;
RETI = r0;
RTI;
THANDLE: // Timer Handler 6
R0 = RETI;
R0 += 2;
RETI = r0;
RTI;
I7HANDLE: // IVG 7 Handler
R0 = RETI;
I0 += 2;
I1 += 2;
I3 += 2;
R0 += 2;
RETI = r0;
RTI;
I8HANDLE: // IVG 8 Handler
R0 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
M0 = I0;
M1 = I1;
M2 = I2;
M3 = I3;
R0 += 2;
RETI = r0;
RTI;
I9HANDLE: // IVG 9 Handler
R0 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 += 2;
RETI = r0;
RTI;
I10HANDLE: // IVG 10 Handler
R0 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 += 2;
RETI = r0;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
M0 = R4;
R0 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 += 2;
RETI = r0;
RTI;
I12HANDLE: // IVG 12 Handler
R0 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 += 2;
RETI = r0;
RTI;
I13HANDLE: // IVG 13 Handler
R0 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 += 2;
RETI = r0;
RTI;
I14HANDLE: // IVG 14 Handler
R0 = RETI;
I1 += 2;
I2 += 2;
I3 += 2;
R0 += 2;
RETI = r0;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
I1 += 2;
I2 += 2;
RTI;
// nop;nop;nop;nop;nop;nop;nop; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
// .space (STACKSIZE); // adding this may solve the problem
|
stsp/binutils-ia16
| 10,386
|
sim/testsuite/bfin/c_dsp32shift_ahalf_rn_s.s
|
//Original:/testcases/core/c_dsp32shift_ahalf_rn_s/c_dsp32shift_ahalf_rn_s.dsp
// Spec Reference: dsp32shift ashift s
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
//rl0 = ashift (rl0 by rl0);
R1.L = ASHIFT R1.L BY R0.L (S);
R2.L = ASHIFT R2.L BY R0.L (S);
R3.L = ASHIFT R3.L BY R0.L (S);
R4.L = ASHIFT R4.L BY R0.L (S);
R5.L = ASHIFT R5.L BY R0.L (S);
R6.L = ASHIFT R6.L BY R0.L (S);
R7.L = ASHIFT R7.L BY R0.L (S);
//CHECKREG r0, 0x00000000;
CHECKREG r1, 0x0000c000;
CHECKREG r2, 0x0000c001;
CHECKREG r3, 0x0000c001;
CHECKREG r4, 0x0000c002;
CHECKREG r5, 0x0000c002;
CHECKREG r6, 0x0000c003;
CHECKREG r7, 0x0000c003;
imm32 r0, 0x00008001;
R1.L = -1;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R1.L (S);
//rl1 = ashift (rl1 by rl1);
R2.L = ASHIFT R2.L BY R1.L (S);
R3.L = ASHIFT R3.L BY R1.L (S);
R4.L = ASHIFT R4.L BY R1.L (S);
R5.L = ASHIFT R5.L BY R1.L (S);
R6.L = ASHIFT R6.L BY R1.L (S);
R7.L = ASHIFT R7.L BY R1.L (S);
CHECKREG r0, 0x0000c000;
//CHECKREG r1, 0x00000001;
CHECKREG r2, 0x0000c001;
CHECKREG r3, 0x0000c001;
CHECKREG r4, 0x0000c002;
CHECKREG r5, 0x0000c002;
CHECKREG r6, 0x0000c003;
CHECKREG r7, 0x0000c003;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
R2.L = -15;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R2.L (S);
R1.L = ASHIFT R1.L BY R2.L (S);
//rl2 = ashift (rl2 by rl2);
R3.L = ASHIFT R3.L BY R2.L (S);
R4.L = ASHIFT R4.L BY R2.L (S);
R5.L = ASHIFT R5.L BY R2.L (S);
R6.L = ASHIFT R6.L BY R2.L (S);
R7.L = ASHIFT R7.L BY R2.L (S);
CHECKREG r0, 0x0000ffff;
CHECKREG r1, 0x0000ffff;
//CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x0000ffff;
CHECKREG r4, 0x0000ffff;
CHECKREG r5, 0x0000ffff;
CHECKREG r6, 0x0000ffff;
CHECKREG r7, 0x0000ffff;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
R3.L = -16;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R3.L (S);
R1.L = ASHIFT R1.L BY R3.L (S);
R2.L = ASHIFT R2.L BY R3.L (S);
//rl3 = ashift (rl3 by rl3);
R4.L = ASHIFT R4.L BY R3.L (S);
R5.L = ASHIFT R5.L BY R3.L (S);
R6.L = ASHIFT R6.L BY R3.L (S);
R7.L = ASHIFT R7.L BY R3.L (S);
CHECKREG r0, 0x0000ffff;
CHECKREG r1, 0x0000ffff;
CHECKREG r2, 0x0000ffff;
//CHECKREG r3, 0x00000010;
CHECKREG r4, 0x0000ffff;
CHECKREG r5, 0x0000ffff;
CHECKREG r6, 0x0000ffff;
CHECKREG r7, 0x0000ffff;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.L = ASHIFT R0.H BY R0.L (S);
R1.L = ASHIFT R1.H BY R0.L (S);
R2.L = ASHIFT R2.H BY R0.L (S);
R3.L = ASHIFT R3.H BY R0.L (S);
R4.L = ASHIFT R4.H BY R0.L (S);
R5.L = ASHIFT R5.H BY R0.L (S);
R6.L = ASHIFT R6.H BY R0.L (S);
R7.L = ASHIFT R7.H BY R0.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x80018001;
CHECKREG r2, 0x80028002;
CHECKREG r3, 0x80038003;
CHECKREG r4, 0x80048004;
CHECKREG r5, 0x80058005;
CHECKREG r6, 0x80068006;
CHECKREG r7, 0x80078007;
imm32 r0, 0x80010000;
R1.L = -1;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.L = ASHIFT R0.H BY R1.L (S);
//rl1 = ashift (rh1 by rl1);
R2.L = ASHIFT R2.H BY R1.L (S);
R3.L = ASHIFT R3.H BY R1.L (S);
R4.L = ASHIFT R4.H BY R1.L (S);
R5.L = ASHIFT R5.H BY R1.L (S);
R6.L = ASHIFT R6.H BY R1.L (S);
R7.L = ASHIFT R7.H BY R1.L (S);
CHECKREG r0, 0x8001c000;
//CHECKREG r1, 0x00010001;
CHECKREG r2, 0x8002c001;
CHECKREG r3, 0x8003c001;
CHECKREG r4, 0x8004c002;
CHECKREG r5, 0x8005c002;
CHECKREG r6, 0x8006c003;
CHECKREG r7, 0x8007c003;
imm32 r0, 0xa0010000;
imm32 r1, 0xa0010000;
R2.L = -15;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.L = ASHIFT R0.H BY R2.L (S);
R1.L = ASHIFT R1.H BY R2.L (S);
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L (S);
R4.L = ASHIFT R4.H BY R2.L (S);
R5.L = ASHIFT R5.H BY R2.L (S);
R6.L = ASHIFT R6.H BY R2.L (S);
R7.L = ASHIFT R7.H BY R2.L (S);
CHECKREG r0, 0xa001ffff;
CHECKREG r1, 0xa001ffff;
//CHECKREG r2, 0x2002000f;
CHECKREG r3, 0xa003ffff;
CHECKREG r4, 0xa004ffff;
CHECKREG r5, 0xa005ffff;
CHECKREG r6, 0xa006ffff;
CHECKREG r7, 0xa007ffff;
imm32 r0, 0xb0010001;
imm32 r1, 0xb0010001;
imm32 r2, 0xb0020002;
R3.L = -16;
imm32 r4, 0xb0040004;
imm32 r5, 0xb0050005;
imm32 r6, 0xb0060006;
imm32 r7, 0xb0070007;
R0.L = ASHIFT R0.H BY R3.L (S);
R1.L = ASHIFT R1.H BY R3.L (S);
R2.L = ASHIFT R2.H BY R3.L (S);
//rl3 = ashift (rh3 by rl3);
R4.L = ASHIFT R4.H BY R3.L (S);
R5.L = ASHIFT R5.H BY R3.L (S);
R6.L = ASHIFT R6.H BY R3.L (S);
R7.L = ASHIFT R7.H BY R3.L (S);
CHECKREG r0, 0xb001ffff;
CHECKREG r1, 0xb001ffff;
CHECKREG r2, 0xb002ffff;
//CHECKREG r3, 0x30030010;
CHECKREG r4, 0xb004ffff;
CHECKREG r5, 0xb005ffff;
CHECKREG r6, 0xb006ffff;
CHECKREG r7, 0xb007ffff;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000000;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R4.L (S);
R1.H = ASHIFT R1.L BY R4.L (S);
R2.H = ASHIFT R2.L BY R4.L (S);
R3.H = ASHIFT R3.L BY R4.L (S);
//rh4 = ashift (rl4 by rl4);
R5.H = ASHIFT R5.L BY R4.L (S);
R6.H = ASHIFT R6.L BY R4.L (S);
R7.H = ASHIFT R7.L BY R4.L (S);
CHECKREG r0, 0x00010001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
//CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
R5.L = -1;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.H = ASHIFT R0.L BY R5.L (S);
R1.H = ASHIFT R1.L BY R5.L (S);
R2.H = ASHIFT R2.L BY R5.L (S);
R3.H = ASHIFT R3.L BY R5.L (S);
R4.H = ASHIFT R4.L BY R5.L (S);
//rh5 = ashift (rl5 by rl5);
R6.H = ASHIFT R6.L BY R5.L (S);
R7.H = ASHIFT R7.L BY R5.L (S);
CHECKREG r0, 0xc0008001;
CHECKREG r1, 0xc0008001;
CHECKREG r2, 0xc0018002;
CHECKREG r3, 0xc0018003;
CHECKREG r4, 0xc0028004;
//CHECKREG r5, 0x00020005;
CHECKREG r6, 0xc0038006;
CHECKREG r7, 0xc0038007;
imm32 r0, 0x00009001;
imm32 r1, 0x00009001;
imm32 r2, 0x00009002;
imm32 r3, 0x00009003;
imm32 r4, 0x00009004;
imm32 r5, 0x00009005;
R6.L = -15;
imm32 r7, 0x00009007;
R0.H = ASHIFT R0.L BY R6.L (S);
R1.H = ASHIFT R1.L BY R6.L (S);
R2.H = ASHIFT R2.L BY R6.L (S);
R3.H = ASHIFT R3.L BY R6.L (S);
R4.H = ASHIFT R4.L BY R6.L (S);
R5.H = ASHIFT R5.L BY R6.L (S);
//rh6 = ashift (rl6 by rl6);
R7.H = ASHIFT R7.L BY R6.L;
CHECKREG r0, 0xffff9001;
CHECKREG r1, 0xffff9001;
CHECKREG r2, 0xffff9002;
CHECKREG r3, 0xffff9003;
CHECKREG r4, 0xffff9004;
CHECKREG r5, 0xffff9005;
//CHECKREG r6, 0x00006006;
CHECKREG r7, 0xffff9007;
imm32 r0, 0x0000a001;
imm32 r1, 0x0000a001;
imm32 r2, 0x0000a002;
imm32 r3, 0x0000a003;
imm32 r4, 0x0000a004;
imm32 r5, 0x0000a005;
imm32 r6, 0x0000a006;
R7.L = -16;
R0.H = ASHIFT R0.L BY R7.L (S);
R1.H = ASHIFT R1.L BY R7.L (S);
R2.H = ASHIFT R2.L BY R7.L (S);
R3.H = ASHIFT R3.L BY R7.L (S);
R4.H = ASHIFT R4.L BY R7.L (S);
R5.H = ASHIFT R5.L BY R7.L (S);
R6.H = ASHIFT R6.L BY R7.L (S);
R7.H = ASHIFT R7.L BY R7.L (S);
CHECKREG r0, 0xffffa001;
CHECKREG r1, 0xffffa001;
CHECKREG r2, 0xffffa002;
CHECKREG r3, 0xffffa003;
CHECKREG r4, 0xffffa004;
CHECKREG r5, 0xffffa005;
CHECKREG r6, 0xffffa006;
//CHECKREG r7, 0x00007007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x80010000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
R4.L = -1;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.H = ASHIFT R0.H BY R4.L (S);
R1.H = ASHIFT R1.H BY R4.L (S);
R2.H = ASHIFT R2.H BY R4.L (S);
R3.H = ASHIFT R3.H BY R4.L (S);
//rh4 = ashift (rh4 by rl4);
R5.H = ASHIFT R5.H BY R4.L (S);
R6.H = ASHIFT R6.H BY R4.L (S);
R7.H = ASHIFT R7.H BY R4.L (S);
CHECKREG r0, 0xc0000000;
CHECKREG r1, 0xc0000000;
CHECKREG r2, 0xc0010000;
CHECKREG r3, 0xc0010000;
//CHECKREG r4, 0x00020000;
CHECKREG r5, 0xc0020000;
CHECKREG r6, 0xc0030000;
CHECKREG r7, 0xc0030000;
imm32 r0, 0x80010000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
R5.L = -1;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.H = ASHIFT R0.H BY R5.L (S);
R1.H = ASHIFT R1.H BY R5.L (S);
R2.H = ASHIFT R2.H BY R5.L (S);
R3.H = ASHIFT R3.H BY R5.L (S);
R4.H = ASHIFT R4.H BY R5.L (S);
//rh5 = ashift (rh5 by rl5);
R6.H = ASHIFT R6.H BY R5.L (S);
R7.H = ASHIFT R7.H BY R5.L (S);
CHECKREG r0, 0xc0000000;
CHECKREG r1, 0xc0000000;
CHECKREG r2, 0xc0010000;
CHECKREG r3, 0xc0010000;
CHECKREG r4, 0xc0020000;
//CHECKREG r5, 0x28020000;
CHECKREG r6, 0xc0030000;
CHECKREG r7, 0xc0030000;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030000;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
R6.L = -15;
imm32 r7, 0xd0070000;
R0.L = ASHIFT R0.H BY R6.L (S);
R1.L = ASHIFT R1.H BY R6.L (S);
R2.L = ASHIFT R2.H BY R6.L (S);
R3.L = ASHIFT R3.H BY R6.L (S);
R4.L = ASHIFT R4.H BY R6.L (S);
R5.L = ASHIFT R5.H BY R6.L (S);
//rl6 = ashift (rh6 by rl6);
R7.L = ASHIFT R7.H BY R6.L;
CHECKREG r0, 0xd001ffff;
CHECKREG r1, 0xd001ffff;
CHECKREG r2, 0xd002ffff;
CHECKREG r3, 0xd003ffff;
CHECKREG r4, 0xd004ffff;
CHECKREG r5, 0xd005ffff;
//CHECKREG r6, 0x60060000;
CHECKREG r7, 0xd007ffff;
imm32 r0, 0xe0010000;
imm32 r1, 0xe0010000;
imm32 r2, 0xe0020000;
imm32 r3, 0xe0030000;
imm32 r4, 0xe0040000;
imm32 r5, 0xe0050000;
imm32 r6, 0xe0060000;
R7.L = -16;
R0.H = ASHIFT R0.H BY R7.L (S);
R1.H = ASHIFT R1.H BY R7.L (S);
R2.H = ASHIFT R2.H BY R7.L (S);
R3.H = ASHIFT R3.H BY R7.L (S);
R4.H = ASHIFT R4.H BY R7.L (S);
R5.H = ASHIFT R5.H BY R7.L (S);
R6.H = ASHIFT R6.H BY R7.L (S);
//rh7 = ashift (rh7 by rl7);
CHECKREG r0, 0xffff0000;
CHECKREG r1, 0xffff0000;
CHECKREG r2, 0xffff0000;
CHECKREG r3, 0xffff0000;
CHECKREG r4, 0xffff0000;
CHECKREG r5, 0xffff0000;
CHECKREG r6, 0xffff0000;
//CHECKREG r7, -16;
pass
|
stsp/binutils-ia16
| 4,303
|
sim/testsuite/bfin/c_cc2stat_cc_av1.S
|
//Original:/testcases/core/c_cc2stat_cc_av1/c_cc2stat_cc_av1.dsp
// Spec Reference: cc2stat cc av1
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// test CC = AV1 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
CC = AV1; //
R0 = CC; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
CC = AV1; //
R1 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
CC = AV1; //
R2 = CC; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
CC = AV1; //
R3 = CC; //
// test cc |= AV1 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
CC |= AV1; //
R4 = CC; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
CC |= AV1; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
CC |= AV1; //
R6 = CC; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
CC |= AV1; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _SET;
// test CC &= AV1 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
CC &= AV1; //
R4 = CC; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
CC &= AV1; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
CC &= AV1; //
R6 = CC; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
CC &= AV1; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _UNSET;
CHECKREG r7, _SET;
// test CC ^= AV1 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
CC ^= AV1; //
R4 = CC; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
CC ^= AV1; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
CC ^= AV1; //
R6 = CC; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
CC ^= AV1; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _UNSET;
// test AV1 = CC 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
AV1 = CC; //
R0 = ASTAT; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
AV1 = CC; //
R1 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
AV1 = CC; //
R2 = ASTAT; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
AV1 = CC; //
R3 = ASTAT; //
// test AV1 |= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
AV1 |= CC; //
R4 = ASTAT; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
AV1 |= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
AV1 |= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
AV1 |= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV1);
CHECKREG r3, (_CC|_AV1);
CHECKREG r4, _UNSET;
CHECKREG r5, _AV1;
CHECKREG r6, (_CC|_AV1);
CHECKREG r7, (_CC|_AV1);
// test AV1 &= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
AV1 &= CC; //
R4 = ASTAT; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
AV1 &= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
AV1 &= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
AV1 &= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV1);
CHECKREG r3, (_CC|_AV1);
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _CC;
CHECKREG r7, (_CC|_AV1);
// test AV1 ^= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
AV1 ^= CC; //
R4 = ASTAT; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
AV1 ^= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
AV1 ^= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
AV1 ^= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV1);
CHECKREG r3, (_CC|_AV1);
CHECKREG r4, _UNSET;
CHECKREG r5, _AV1;
CHECKREG r6, (_CC|_AV1);
CHECKREG r7, _CC;
pass
|
stsp/binutils-ia16
| 5,483
|
sim/testsuite/bfin/c_regmv_pr_imlb.s
|
//Original:/testcases/core/c_regmv_pr_imlb/c_regmv_pr_imlb.dsp
// Spec Reference: regmv preg-to-imlb reg
# mach: bfin
.include "testutils.inc"
start
// check R-reg to imlb-reg move
imm32 r0, 0x00000001;
imm32 p1, 0x00020003;
imm32 p2, 0x00040005;
imm32 p3, 0x00060007;
imm32 p4, 0x00080009;
imm32 p5, 0x000a000b;
imm32 sp, 0x000c000d;
imm32 fp, 0x000e000f;
I0 = P1;
I1 = P1;
I2 = P1;
I3 = P1;
M0 = P1;
M1 = P1;
M2 = P1;
M3 = P1;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00020003;
CHECKREG r1, 0x00020003;
CHECKREG r2, 0x00020003;
CHECKREG r3, 0x00020003;
CHECKREG r4, 0x00020003;
CHECKREG r5, 0x00020003;
CHECKREG r6, 0x00020003;
CHECKREG r7, 0x00020003;
imm32 p2, 0x00040005;
I0 = P2;
I1 = P2;
I2 = P2;
I3 = P2;
M0 = P2;
M1 = P2;
M2 = P2;
M3 = P2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00040005;
CHECKREG r1, 0x00040005;
CHECKREG r2, 0x00040005;
CHECKREG r3, 0x00040005;
CHECKREG r4, 0x00040005;
CHECKREG r5, 0x00040005;
CHECKREG r6, 0x00040005;
CHECKREG r7, 0x00040005;
imm32 p3, 0x00060007;
I0 = P3;
I1 = P3;
I2 = P3;
I3 = P3;
M0 = P3;
M1 = P3;
M2 = P3;
M3 = P3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00060007;
CHECKREG r1, 0x00060007;
CHECKREG r2, 0x00060007;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0x00060007;
CHECKREG r5, 0x00060007;
CHECKREG r6, 0x00060007;
CHECKREG r7, 0x00060007;
imm32 p4, 0x00080009;
I0 = P4;
I1 = P4;
I2 = P4;
I3 = P4;
M0 = P4;
M1 = P4;
M2 = P4;
M3 = P4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00080009;
CHECKREG r1, 0x00080009;
CHECKREG r2, 0x00080009;
CHECKREG r3, 0x00080009;
CHECKREG r4, 0x00080009;
CHECKREG r5, 0x00080009;
CHECKREG r6, 0x00080009;
CHECKREG r7, 0x00080009;
imm32 p5, 0x000a000b;
I0 = P5;
I1 = P5;
I2 = P5;
I3 = P5;
M0 = P5;
M1 = P5;
M2 = P5;
M3 = P5;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x000a000b;
CHECKREG r1, 0x000a000b;
CHECKREG r2, 0x000a000b;
CHECKREG r3, 0x000a000b;
CHECKREG r4, 0x000a000b;
CHECKREG r5, 0x000a000b;
CHECKREG r6, 0x000a000b;
CHECKREG r7, 0x000a000b;
imm32 sp, 0x000c000d;
I0 = SP;
I1 = SP;
I2 = SP;
I3 = SP;
M0 = SP;
M1 = SP;
M2 = SP;
M3 = SP;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x000c000d;
CHECKREG r1, 0x000c000d;
CHECKREG r2, 0x000c000d;
CHECKREG r3, 0x000c000d;
CHECKREG r4, 0x000c000d;
CHECKREG r5, 0x000c000d;
CHECKREG r6, 0x000c000d;
CHECKREG r7, 0x000c000d;
imm32 fp, 0x000e000f;
I0 = FP;
I1 = FP;
I2 = FP;
I3 = FP;
M0 = FP;
M1 = FP;
M2 = FP;
M3 = FP;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x000e000f;
CHECKREG r1, 0x000e000f;
CHECKREG r2, 0x000e000f;
CHECKREG r3, 0x000e000f;
CHECKREG r4, 0x000e000f;
CHECKREG r5, 0x000e000f;
CHECKREG r6, 0x000e000f;
CHECKREG r7, 0x000e000f;
imm32 p1, 0x00020003;
L0 = P1;
L1 = P1;
L2 = P1;
L3 = P1;
B0 = P1;
B1 = P1;
B2 = P1;
B3 = P1;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00020003;
CHECKREG r1, 0x00020003;
CHECKREG r2, 0x00020003;
CHECKREG r3, 0x00020003;
CHECKREG r4, 0x00020003;
CHECKREG r5, 0x00020003;
CHECKREG r6, 0x00020003;
CHECKREG r7, 0x00020003;
imm32 p2, 0x00040005;
L0 = P2;
L1 = P2;
L2 = P2;
L3 = P2;
B0 = P2;
B1 = P2;
B2 = P2;
B3 = P2;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00040005;
CHECKREG r1, 0x00040005;
CHECKREG r2, 0x00040005;
CHECKREG r3, 0x00040005;
CHECKREG r4, 0x00040005;
CHECKREG r5, 0x00040005;
CHECKREG r6, 0x00040005;
CHECKREG r7, 0x00040005;
imm32 p3, 0x00060007;
L0 = P3;
L1 = P3;
L2 = P3;
L3 = P3;
B0 = P3;
B1 = P3;
B2 = P3;
B3 = P3;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00060007;
CHECKREG r1, 0x00060007;
CHECKREG r2, 0x00060007;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0x00060007;
CHECKREG r5, 0x00060007;
CHECKREG r6, 0x00060007;
CHECKREG r7, 0x00060007;
imm32 p4, 0x00080009;
L0 = P4;
L1 = P4;
L2 = P4;
L3 = P4;
B0 = P4;
B1 = P4;
B2 = P4;
B3 = P4;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00080009;
CHECKREG r1, 0x00080009;
CHECKREG r2, 0x00080009;
CHECKREG r3, 0x00080009;
CHECKREG r4, 0x00080009;
CHECKREG r5, 0x00080009;
CHECKREG r6, 0x00080009;
CHECKREG r7, 0x00080009;
imm32 p5, 0x000a000b;
L0 = P5;
L1 = P5;
L2 = P5;
L3 = P5;
B0 = P5;
B1 = P5;
B2 = P5;
B3 = P5;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x000a000b;
CHECKREG r1, 0x000a000b;
CHECKREG r2, 0x000a000b;
CHECKREG r3, 0x000a000b;
CHECKREG r4, 0x000a000b;
CHECKREG r5, 0x000a000b;
CHECKREG r6, 0x000a000b;
CHECKREG r7, 0x000a000b;
imm32 sp, 0x000c000d;
L0 = SP;
L1 = SP;
L2 = SP;
L3 = SP;
B0 = SP;
B1 = SP;
B2 = SP;
B3 = SP;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x000c000d;
CHECKREG r1, 0x000c000d;
CHECKREG r2, 0x000c000d;
CHECKREG r3, 0x000c000d;
CHECKREG r4, 0x000c000d;
CHECKREG r5, 0x000c000d;
CHECKREG r6, 0x000c000d;
CHECKREG r7, 0x000c000d;
imm32 fp, 0x000e000f;
L0 = FP;
L1 = FP;
L2 = FP;
L3 = FP;
B0 = FP;
B1 = FP;
B2 = FP;
B3 = FP;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x000e000f;
CHECKREG r1, 0x000e000f;
CHECKREG r2, 0x000e000f;
CHECKREG r3, 0x000e000f;
CHECKREG r4, 0x000e000f;
CHECKREG r5, 0x000e000f;
CHECKREG r6, 0x000e000f;
CHECKREG r7, 0x000e000f;
pass
|
stsp/binutils-ia16
| 8,604
|
sim/testsuite/bfin/random_0027.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2850c890 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY);
dmm32 A1.w, 0xa605868e;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x56dd0982;
imm32 R4, 0x50e37862;
imm32 R5, 0x597fc81a;
R4.H = (A1 -= R5.L * R1.L) (M, IS);
checkreg R4, 0x7fff7862;
checkreg A1.w, 0xa818ff5a;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x2850c890 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x08100a00 | _VS | _AC1 | _AC0 | _CC);
dmm32 A1.w, 0xeb710132;
dmm32 A1.x, 0xffffffcf;
imm32 R4, 0x750d92cc;
imm32 R7, 0xf9a22cee;
R4.H = (A1 -= R7.L * R7.H) (M, IS);
checkreg R4, 0x800092cc;
checkreg A1.w, 0xbfa11496;
checkreg A1.x, 0xffffffcf;
checkreg ASTAT, (0x08100a00 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY);
dmm32 ASTAT, (0x44e00410 | _VS | _AV0S | _AQ | _AN);
dmm32 A1.w, 0x95489ea8;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x360dca41;
imm32 R4, 0x7fffe848;
imm32 R7, 0x278abda8;
R7 = (A1 -= R4.L * R1.L) (M, IS);
checkreg R7, 0x7fffffff;
checkreg A1.w, 0xa805d460;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x44e00410 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x0480c800 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0xcfa4f43b;
dmm32 A1.x, 0x0000006c;
imm32 R3, 0x0903dd55;
imm32 R7, 0x7fffc2b1;
A1 -= R3.L * R7.L (M, IS);
checkreg A1.w, 0xea028276;
checkreg A1.x, 0x0000006c;
checkreg ASTAT, (0x0480c800 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x3c204410 | _VS | _AV0S | _AN);
dmm32 A1.w, 0x928b984e;
dmm32 A1.x, 0xffffffd5;
imm32 R5, 0x00003ddd;
imm32 R7, 0x8000ffff;
A1 += R5.L * R7.L (M, IS);
checkreg A1.w, 0xd0685a71;
checkreg A1.x, 0xffffffd5;
checkreg ASTAT, (0x3c204410 | _VS | _AV0S | _AN);
dmm32 ASTAT, (0x4840c890 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN);
dmm32 A1.w, 0x8837abf1;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x10c90000;
imm32 R7, 0x7fffe6b8;
A1 += R7.L * R3.H (M, IS);
checkreg A1.w, 0x868f5269;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x4840c890 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN);
dmm32 ASTAT, (0x78604a80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY);
dmm32 A1.w, 0xdca875cf;
dmm32 A1.x, 0x0000002c;
imm32 R3, 0x4c0892ef;
imm32 R5, 0x001fea98;
R5.H = (A1 += R5.L * R3.H) (M, IS);
checkreg R5, 0x7fffea98;
checkreg A1.w, 0xd64cea8f;
checkreg A1.x, 0x0000002c;
checkreg ASTAT, (0x78604a80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x00a04210 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0xec5ef880;
dmm32 A1.x, 0xfffffffe;
imm32 R0, 0x229657d6;
imm32 R7, 0xedd48000;
A1 += R0.L * R7.L (M, IS);
checkreg A1.w, 0x1849f880;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x00a04210 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x0840ce80 | _VS | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 A1.w, 0xe4a5a6e1;
dmm32 A1.x, 0x00000078;
imm32 R0, 0xf059329d;
imm32 R7, 0x7fff7512;
A1 += R7.L * R0.L (M, IS);
checkreg A1.w, 0xfbcaf6eb;
checkreg A1.x, 0x00000078;
checkreg ASTAT, (0x0840ce80 | _VS | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 ASTAT, (0x60100810 | _VS | _AV0S | _AQ | _AC0_COPY | _AZ);
dmm32 A1.w, 0xd56a8232;
dmm32 A1.x, 0x00000033;
imm32 R0, 0x09b22c69;
imm32 R7, 0x434f1d64;
A1 -= R0.L * R7.L (M, IS);
checkreg A1.w, 0xd051442e;
checkreg A1.x, 0x00000033;
checkreg ASTAT, (0x60100810 | _VS | _AV0S | _AQ | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x58e08410 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x86c9a59e;
dmm32 A1.x, 0xffffff9a;
imm32 R1, 0x22573f31;
imm32 R6, 0x2d0c0155;
A1 += R1.L * R6.H (M, IS);
checkreg A1.w, 0x91e838ea;
checkreg A1.x, 0xffffff9a;
checkreg ASTAT, (0x58e08410 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 ASTAT, (0x64a0c690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0xc5c840aa;
dmm32 A1.x, 0x00000000;
imm32 R4, 0xffff7fff;
imm32 R7, 0x658e833f;
A1 -= R7.L * R4.H (M, IS);
checkreg A1.w, 0x4288c3e9;
checkreg A1.x, 0x00000001;
checkreg ASTAT, (0x64a0c690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
dmm32 ASTAT, (0x08804610 | _VS | _V | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AN);
dmm32 A1.w, 0xf1000000;
dmm32 A1.x, 0x00000040;
imm32 R3, 0x0cd4edf1;
imm32 R6, 0x4dfc08b8;
R6.H = (A1 += R6.L * R3.H) (M, IS);
checkreg R6, 0x7fff08b8;
checkreg A1.w, 0xf16fd860;
checkreg A1.x, 0x00000040;
checkreg ASTAT, (0x08804610 | _VS | _V | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x7c004690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0xd4deb886;
dmm32 A1.x, 0x00000001;
imm32 R1, 0x80008000;
imm32 R6, 0x22fb6e50;
imm32 R7, 0x3fcb147f;
R1.H = (A1 -= R7.L * R6.L) (M, IS);
checkreg R1, 0x7fff8000;
checkreg A1.w, 0xcc09bed6;
checkreg A1.x, 0x00000001;
checkreg ASTAT, (0x7c004690 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x40a00400 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
dmm32 A1.w, 0x9698e35b;
dmm32 A1.x, 0xfffffffc;
imm32 R5, 0x8000038c;
imm32 R6, 0x3152ffff;
A1 -= R6.L * R5.L (M, IS);
checkreg A1.w, 0x9698e6e7;
checkreg A1.x, 0xfffffffc;
checkreg ASTAT, (0x40a00400 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x54c00810 | _VS | _V | _AC1 | _CC | _V_COPY | _AN | _AZ);
dmm32 A1.w, 0x9b02b9c6;
dmm32 A1.x, 0xffffffd4;
imm32 R2, 0xff020105;
imm32 R3, 0xa8ff8000;
R3.H = (A1 -= R2.L * R3.L) (M, IS);
checkreg R3, 0x80008000;
checkreg A1.w, 0x9a8039c6;
checkreg A1.x, 0xffffffd4;
checkreg ASTAT, (0x54c00810 | _VS | _V | _AC1 | _CC | _V_COPY | _AN | _AZ);
dmm32 ASTAT, (0x58808680 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0x990456b2;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x2b76c7b2;
imm32 R3, 0x659803c8;
imm32 R7, 0x7fffffff;
R3.H = (A1 += R7.L * R0.L) (M, IS);
checkreg R3, 0x7fff03c8;
checkreg A1.w, 0x99038f00;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x58808680 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3ce04690 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY);
dmm32 A1.w, 0x95d1d45a;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x4331b012;
imm32 R5, 0x7fff8000;
A1 -= R0.L * R5.H (M, IS);
checkreg A1.w, 0xbdc8846c;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x3ce04690 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY);
dmm32 ASTAT, (0x30e04410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC);
dmm32 A1.w, 0xcf49e4c9;
dmm32 A1.x, 0x00000000;
imm32 R1, 0xe968a740;
imm32 R3, 0xd7383cd5;
imm32 R6, 0x5a87c89b;
R1 = (A1 += R3.L * R6.H) (M, IS);
checkreg R1, 0x7fffffff;
checkreg A1.w, 0xe4ccdb1c;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x30e04410 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x2cb04890 | _VS | _AC1 | _AQ | _AC0_COPY);
dmm32 A1.w, 0x8bdaf471;
dmm32 A1.x, 0xffffffbd;
imm32 R3, 0x728d99b1;
imm32 R7, 0x181d83c2;
A1 -= R7.L * R3.L (M, IS);
checkreg A1.w, 0xd671e94f;
checkreg A1.x, 0xffffffbd;
checkreg ASTAT, (0x2cb04890 | _VS | _AC1 | _AQ | _AC0_COPY);
dmm32 ASTAT, (0x20908680 | _VS | _AV0S | _AC1 | _AQ | _CC | _AZ);
dmm32 A1.w, 0xc1cb8a00;
dmm32 A1.x, 0x00000000;
imm32 R1, 0xc1e98ea8;
imm32 R7, 0x0000961f;
A1 -= R7.L * R1.L (M, IS);
checkreg A1.w, 0xfccbd3a8;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x20908680 | _VS | _AV0S | _AC1 | _AQ | _CC | _AZ);
dmm32 ASTAT, (0x64a0cc80 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AZ);
dmm32 A1.w, 0xfb328cb4;
dmm32 A1.x, 0xffffff9b;
imm32 R2, 0x8000ffff;
imm32 R3, 0x64d21863;
imm32 R6, 0x3b7618a6;
R2.H = (A1 += R3.L * R6.H) (M, IS);
checkreg A1.w, 0x00dc9b56;
checkreg A1.x, 0xffffff9c;
checkreg ASTAT, (0x64a0cc80 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AZ);
dmm32 ASTAT, (0x3c00ca90 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0xbfb4c632;
dmm32 A1.x, 0x00000044;
imm32 R1, 0x7fffffff;
imm32 R3, 0xf3e9182e;
imm32 R5, 0x3c94d844;
R5.H = (A1 += R1.L * R3.H) (M, IS);
checkreg R5, 0x7fffd844;
checkreg A1.w, 0xbfb3d249;
checkreg A1.x, 0x00000044;
checkreg ASTAT, (0x3c00ca90 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x48c0cc10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
dmm32 A1.w, 0x83144651;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x04d0ffff;
imm32 R4, 0x9dc8f8d8;
imm32 R7, 0x23180d75;
R3 = (A1 += R4.L * R7.L) (M, IS);
checkreg R3, 0x7fffffff;
checkreg A1.w, 0x82b3f909;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x48c0cc10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
pass
|
stsp/binutils-ia16
| 7,992
|
sim/testsuite/bfin/c_comp3op_dr_and_dr.s
|
//Original:/testcases/core/c_comp3op_dr_and_dr/c_comp3op_dr_and_dr.dsp
// Spec Reference: comp3op dregs & dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 r7, 0x12345678;
R0 = R0 & R0;
R1 = R0 & R1;
R2 = R0 & R2;
R3 = R0 & R3;
R4 = R0 & R4;
R5 = R0 & R5;
R6 = R0 & R6;
R7 = R0 & R7;
CHECKREG r0, 0x01234567;
CHECKREG r1, 0x01234567;
CHECKREG r2, 0x00200024;
CHECKREG r3, 0x00200024;
CHECKREG r4, 0x01014001;
CHECKREG r5, 0x00010145;
CHECKREG r6, 0x00224422;
CHECKREG r7, 0x00204460;
imm32 r0, 0x01231567;
imm32 r1, 0x89ab1def;
imm32 r2, 0x56781abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23451899;
imm32 r5, 0x78911345;
imm32 r6, 0x98761432;
imm32 r7, 0x12341678;
R0 = R1 & R0;
R1 = R1 & R1;
R2 = R1 & R2;
R3 = R1 & R3;
R4 = R1 & R4;
R5 = R1 & R5;
R6 = R1 & R6;
R7 = R1 & R7;
CHECKREG r0, 0x01231567;
CHECKREG r1, 0x89AB1DEF;
CHECKREG r2, 0x002818AC;
CHECKREG r3, 0x88A01024;
CHECKREG r4, 0x01011889;
CHECKREG r5, 0x08811145;
CHECKREG r6, 0x88221422;
CHECKREG r7, 0x00201468;
imm32 r0, 0x01234527;
imm32 r1, 0x89abcd2f;
imm32 r2, 0x56789a2c;
imm32 r3, 0xdef01224;
imm32 r4, 0x23456829;
imm32 r5, 0x78912325;
imm32 r6, 0x98765422;
imm32 r7, 0x12345628;
R0 = R2 & R0;
R1 = R2 & R1;
R2 = R2 & R2;
R3 = R2 & R3;
R4 = R2 & R4;
R5 = R2 & R5;
R6 = R2 & R6;
R7 = R2 & R7;
CHECKREG r0, 0x00200024;
CHECKREG r1, 0x0028882C;
CHECKREG r2, 0x56789A2C;
CHECKREG r3, 0x56701224;
CHECKREG r4, 0x02400828;
CHECKREG r5, 0x50100224;
CHECKREG r6, 0x10701020;
CHECKREG r7, 0x12301228;
imm32 r0, 0x01234563;
imm32 r1, 0x89abcde3;
imm32 r2, 0x56789ab3;
imm32 r3, 0xdef01233;
imm32 r4, 0x23456893;
imm32 r5, 0x78912343;
imm32 r6, 0x98765433;
imm32 r7, 0x12345673;
R0 = R3 & R0;
R1 = R3 & R1;
R2 = R3 & R2;
R3 = R3 & R3;
R4 = R3 & R4;
R5 = R3 & R5;
R6 = R3 & R6;
R7 = R3 & R7;
CHECKREG r0, 0x00200023;
CHECKREG r1, 0x88A00023;
CHECKREG r2, 0x56701233;
CHECKREG r3, 0xDEF01233;
CHECKREG r4, 0x02400013;
CHECKREG r5, 0x58900203;
CHECKREG r6, 0x98701033;
CHECKREG r7, 0x12301233;
imm32 r0, 0x41234567;
imm32 r1, 0x49abcdef;
imm32 r2, 0x46789abc;
imm32 r3, 0x4ef01234;
imm32 r4, 0x43456899;
imm32 r5, 0x48912345;
imm32 r6, 0x48765432;
imm32 r7, 0x42345678;
R0 = R4 & R0;
R1 = R4 & R1;
R2 = R4 & R2;
R3 = R4 & R3;
R4 = R4 & R4;
R5 = R4 & R5;
R6 = R4 & R6;
R7 = R4 & R7;
CHECKREG r0, 0x41014001;
CHECKREG r1, 0x41014889;
CHECKREG r2, 0x42400898;
CHECKREG r3, 0x42400010;
CHECKREG r4, 0x43456899;
CHECKREG r5, 0x40012001;
CHECKREG r6, 0x40444010;
CHECKREG r7, 0x42044018;
imm32 r0, 0x05234567;
imm32 r1, 0x85abcdef;
imm32 r2, 0x55789abc;
imm32 r3, 0xd5f01234;
imm32 r4, 0x25456899;
imm32 r5, 0x75912345;
imm32 r6, 0x95765432;
imm32 r7, 0x15345678;
R0 = R5 & R0;
R1 = R5 & R1;
R2 = R5 & R2;
R3 = R5 & R3;
R4 = R5 & R4;
R5 = R5 & R5;
R6 = R5 & R6;
R7 = R5 & R7;
CHECKREG r0, 0x05010145;
CHECKREG r1, 0x05810145;
CHECKREG r2, 0x55100204;
CHECKREG r3, 0x55900204;
CHECKREG r4, 0x25012001;
CHECKREG r5, 0x75912345;
CHECKREG r6, 0x15100000;
CHECKREG r7, 0x15100240;
imm32 r0, 0x01264567;
imm32 r1, 0x89a6cdef;
imm32 r2, 0x56769abc;
imm32 r3, 0xdef61234;
imm32 r4, 0x23466899;
imm32 r5, 0x78962345;
imm32 r6, 0x98765432;
imm32 r7, 0x12365678;
R0 = R6 & R0;
R1 = R6 & R1;
R2 = R6 & R2;
R3 = R6 & R3;
R4 = R6 & R4;
R5 = R6 & R5;
R6 = R6 & R6;
R7 = R6 & R7;
CHECKREG r0, 0x00264422;
CHECKREG r1, 0x88264422;
CHECKREG r2, 0x10761030;
CHECKREG r3, 0x98761030;
CHECKREG r4, 0x00464010;
CHECKREG r5, 0x18160000;
CHECKREG r6, 0x98765432;
CHECKREG r7, 0x10365430;
imm32 r0, 0x01237567;
imm32 r1, 0x89ab7def;
imm32 r2, 0x56787abc;
imm32 r3, 0xdef07234;
imm32 r4, 0x23457899;
imm32 r5, 0x78917345;
imm32 r6, 0x98767432;
imm32 r7, 0x12345678;
R0 = R7 & R0;
R1 = R7 & R1;
R2 = R7 & R2;
R3 = R7 & R3;
R4 = R7 & R4;
R5 = R7 & R5;
R6 = R7 & R6;
R7 = R7 & R7;
CHECKREG r0, 0x00205460;
CHECKREG r1, 0x00205468;
CHECKREG r2, 0x12305238;
CHECKREG r3, 0x12305230;
CHECKREG r4, 0x02045018;
CHECKREG r5, 0x10105240;
CHECKREG r6, 0x10345430;
CHECKREG r7, 0x12345678;
imm32 r0, 0x11234567;
imm32 r1, 0x81abcdef;
imm32 r2, 0x56189abc;
imm32 r3, 0xdef11234;
imm32 r4, 0x23451899;
imm32 r5, 0x78912145;
imm32 r6, 0x98765412;
imm32 r7, 0x12345671;
R0 = R1 & R0;
R1 = R2 & R0;
R2 = R3 & R0;
R3 = R4 & R0;
R4 = R5 & R0;
R5 = R6 & R0;
R6 = R7 & R0;
R7 = R0 & R0;
CHECKREG r0, 0x01234567;
CHECKREG r1, 0x00000024;
CHECKREG r2, 0x00210024;
CHECKREG r3, 0x01010001;
CHECKREG r4, 0x00010145;
CHECKREG r5, 0x00224402;
CHECKREG r6, 0x00204461;
CHECKREG r7, 0x01234567;
imm32 r0, 0x01231567;
imm32 r1, 0x29ab1def;
imm32 r2, 0x52781abc;
imm32 r3, 0xde201234;
imm32 r4, 0x23421899;
imm32 r5, 0x78912345;
imm32 r6, 0x98761232;
imm32 r7, 0x12341628;
R0 = R2 & R1;
R1 = R3 & R1;
R2 = R4 & R1;
R3 = R5 & R1;
R4 = R6 & R1;
R5 = R7 & R1;
R6 = R0 & R1;
R7 = R1 & R1;
CHECKREG r0, 0x002818AC;
CHECKREG r1, 0x08201024;
CHECKREG r2, 0x00001000;
CHECKREG r3, 0x08000004;
CHECKREG r4, 0x08201020;
CHECKREG r5, 0x00201020;
CHECKREG r6, 0x00201024;
CHECKREG r7, 0x08201024;
imm32 r0, 0x03234527;
imm32 r1, 0x893bcd2f;
imm32 r2, 0x56739a2c;
imm32 r3, 0x3ef03224;
imm32 r4, 0x23456329;
imm32 r5, 0x78312335;
imm32 r6, 0x98735423;
imm32 r7, 0x12343628;
R0 = R4 & R2;
R1 = R5 & R2;
R2 = R6 & R2;
R3 = R7 & R2;
R4 = R0 & R2;
R5 = R1 & R2;
R6 = R2 & R2;
R7 = R3 & R2;
CHECKREG r0, 0x02410228;
CHECKREG r1, 0x50310224;
CHECKREG r2, 0x10731020;
CHECKREG r3, 0x10301020;
CHECKREG r4, 0x00410020;
CHECKREG r5, 0x10310020;
CHECKREG r6, 0x10731020;
CHECKREG r7, 0x10301020;
imm32 r0, 0x04234563;
imm32 r1, 0x894bcde3;
imm32 r2, 0x56749ab3;
imm32 r3, 0x4ef04233;
imm32 r4, 0x24456493;
imm32 r5, 0x78412344;
imm32 r6, 0x98745434;
imm32 r7, 0x12344673;
R0 = R5 & R3;
R1 = R6 & R3;
R2 = R7 & R3;
R3 = R0 & R3;
R4 = R1 & R3;
R5 = R2 & R3;
R6 = R3 & R3;
R7 = R4 & R3;
CHECKREG r0, 0x48400200;
CHECKREG r1, 0x08704030;
CHECKREG r2, 0x02304233;
CHECKREG r3, 0x48400200;
CHECKREG r4, 0x08400000;
CHECKREG r5, 0x00000200;
CHECKREG r6, 0x48400200;
CHECKREG r7, 0x08400000;
imm32 r0, 0x41235567;
imm32 r1, 0x49abc5ef;
imm32 r2, 0x46789a5c;
imm32 r3, 0x4ef01235;
imm32 r4, 0x53456899;
imm32 r5, 0x45912345;
imm32 r6, 0x48565432;
imm32 r7, 0x42355678;
R0 = R6 & R4;
R1 = R7 & R4;
R2 = R0 & R4;
R3 = R1 & R4;
R4 = R2 & R4;
R5 = R3 & R4;
R6 = R4 & R4;
R7 = R5 & R4;
CHECKREG r0, 0x40444010;
CHECKREG r1, 0x42054018;
CHECKREG r2, 0x40444010;
CHECKREG r3, 0x42054018;
CHECKREG r4, 0x40444010;
CHECKREG r5, 0x40044010;
CHECKREG r6, 0x40444010;
CHECKREG r7, 0x40044010;
imm32 r0, 0x05264567;
imm32 r1, 0x85ab6def;
imm32 r2, 0x657896bc;
imm32 r3, 0xd6f01264;
imm32 r4, 0x25656896;
imm32 r5, 0x75962345;
imm32 r6, 0x95766432;
imm32 r7, 0x15345678;
R0 = R7 & R5;
R1 = R0 & R5;
R2 = R1 & R5;
R3 = R2 & R5;
R4 = R3 & R5;
R5 = R4 & R5;
R6 = R5 & R5;
R7 = R6 & R5;
CHECKREG r0, 0x15140240;
CHECKREG r1, 0x15140240;
CHECKREG r2, 0x15140240;
CHECKREG r3, 0x15140240;
CHECKREG r4, 0x15140240;
CHECKREG r5, 0x15140240;
CHECKREG r6, 0x15140240;
CHECKREG r7, 0x15140240;
imm32 r0, 0x01764567;
imm32 r1, 0x89a7cdef;
imm32 r2, 0x56767abc;
imm32 r3, 0xdef61734;
imm32 r4, 0x73466879;
imm32 r5, 0x77962347;
imm32 r6, 0x98765432;
imm32 r7, 0x12375678;
R0 = R7 & R6;
R1 = R0 & R6;
R2 = R1 & R6;
R3 = R2 & R6;
R4 = R3 & R6;
R5 = R4 & R6;
R6 = R5 & R6;
R7 = R6 & R6;
CHECKREG r0, 0x10365430;
CHECKREG r1, 0x10365430;
CHECKREG r2, 0x10365430;
CHECKREG r3, 0x10365430;
CHECKREG r4, 0x10365430;
CHECKREG r5, 0x10365430;
CHECKREG r6, 0x10365430;
CHECKREG r7, 0x10365430;
imm32 r0, 0x81238567;
imm32 r1, 0x88ab78ef;
imm32 r2, 0x56887a8c;
imm32 r3, 0x8ef87238;
imm32 r4, 0x28458899;
imm32 r5, 0x78817845;
imm32 r6, 0x98787482;
imm32 r7, 0x12348678;
R0 = R1 & R7;
R1 = R2 & R7;
R2 = R3 & R7;
R3 = R4 & R7;
R4 = R5 & R7;
R5 = R6 & R7;
R6 = R7 & R7;
R7 = R0 & R7;
CHECKREG r0, 0x00200068;
CHECKREG r1, 0x12000208;
CHECKREG r2, 0x02300238;
CHECKREG r3, 0x00048018;
CHECKREG r4, 0x10000040;
CHECKREG r5, 0x10300400;
CHECKREG r6, 0x12348678;
CHECKREG r7, 0x00200068;
pass
|
stsp/binutils-ia16
| 8,629
|
sim/testsuite/bfin/c_dsp32shiftim_lhalf_rp.s
|
//Original:/testcases/core/c_dsp32shiftim_lhalf_rp/c_dsp32shiftim_lhalf_rp.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x90000001;
imm32 r2, 0x90000002;
imm32 r3, 0x90000003;
imm32 r4, 0x90000004;
imm32 r5, 0x90000005;
imm32 r6, 0x90000006;
imm32 r7, 0x90000007;
R0.L = R0.L << 0;
R1.L = R1.L >> 1;
R2.L = R2.L >> 2;
R3.L = R3.L >> 3;
R4.L = R4.L >> 4;
R5.L = R5.L >> 5;
R6.L = R6.L >> 6;
R7.L = R7.L >> 7;
CHECKREG r0, 0x0000FFFF;
CHECKREG r1, 0x90000000;
CHECKREG r2, 0x90000000;
CHECKREG r3, 0x90000000;
CHECKREG r4, 0x90000000;
CHECKREG r5, 0x90000000;
CHECKREG r6, 0x90000000;
CHECKREG r7, 0x90000000;
imm32 r0, 0x00001001;
R1.L = -1;
imm32 r2, 0xa0002002;
imm32 r3, 0xa0003003;
imm32 r4, 0xa0004004;
imm32 r5, 0xa0005005;
imm32 r6, 0xa0006006;
imm32 r7, 0xa0007007;
R0.L = R0.L >> 1;
R1.L = R1.L >> 1;
R2.L = R2.L >> 1;
R3.L = R3.L >> 1;
R4.L = R4.L >> 1;
R5.L = R5.L >> 1;
R6.L = R6.L >> 1;
R7.L = R7.L >> 1;
CHECKREG r0, 0x00000800;
CHECKREG r1, 0x90007FFF;
CHECKREG r2, 0xA0001001;
CHECKREG r3, 0xA0001801;
CHECKREG r4, 0xA0002002;
CHECKREG r5, 0xA0002802;
CHECKREG r6, 0xA0003003;
CHECKREG r7, 0xA0003803;
imm32 r0, 0xb0001001;
imm32 r1, 0xb0001001;
R2.L = -15;
imm32 r3, 0xb0003003;
imm32 r4, 0xb0004004;
imm32 r5, 0xb0005005;
imm32 r6, 0xb0006006;
imm32 r7, 0xb0007007;
R0.L = R0.L >> 15;
R1.L = R1.L >> 15;
R2.L = LSHIFT R2.L BY R2.L;
R3.L = R3.L >> 15;
R4.L = R4.L >> 15;
R5.L = R5.L >> 15;
R6.L = R6.L >> 15;
R7.L = R7.L >> 15;
CHECKREG r0, 0xb0000000;
CHECKREG r1, 0xb0000000;
CHECKREG r2, 0xA0000001;
CHECKREG r3, 0xB0000000;
CHECKREG r4, 0xb0000000;
CHECKREG r5, 0xb0000000;
CHECKREG r6, 0xb0000000;
CHECKREG r7, 0xB0000000;
imm32 r0, 0xc0001001;
imm32 r1, 0xc0001001;
imm32 r2, 0xc0002002;
R3.L = -16;
imm32 r4, 0xc0004004;
imm32 r5, 0xc0005005;
imm32 r6, 0xc0006006;
imm32 r7, 0xc0007007;
R0.L = R0.L >> 13;
R1.L = R1.L >> 13;
R2.L = R2.L >> 13;
R3.L = R3.L >> 13;
R4.L = R4.L >> 13;
R5.L = R5.L >> 13;
R6.L = R6.L >> 13;
R7.L = R7.L >> 13;
CHECKREG r0, 0xc0000000;
CHECKREG r1, 0xc0000000;
CHECKREG r2, 0xC0000001;
CHECKREG r3, 0xB0000007;
CHECKREG r4, 0xC0000002;
CHECKREG r5, 0xC0000002;
CHECKREG r6, 0xC0000003;
CHECKREG r7, 0xC0000003;
// RHx by RLx
imm32 r0, 0x0000c000;
imm32 r1, 0x0001c000;
imm32 r2, 0x0002c000;
imm32 r3, 0x0003c000;
imm32 r4, 0x0004c000;
imm32 r5, 0x0005c000;
imm32 r6, 0x0006c000;
imm32 r7, 0x0007c000;
R0.L = R0.H << 0;
R1.L = R1.H << 0;
R2.L = R2.H << 0;
R3.L = R3.H << 0;
R4.L = R4.H << 0;
R5.L = R5.H << 0;
R6.L = R6.H << 0;
R7.L = R7.H << 0;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x10010000;
R1.L = -1;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
imm32 r6, 0x60060000;
imm32 r7, 0x70070000;
R0.L = R0.H >> 1;
R1.L = R1.H >> 1;
R2.L = R2.H >> 1;
R3.L = R3.H >> 1;
R4.L = R4.H >> 1;
R5.L = R5.H >> 1;
R6.L = R6.H >> 1;
R7.L = R7.H >> 1;
CHECKREG r0, 0x10010800;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x20021001;
CHECKREG r3, 0x30031801;
CHECKREG r4, 0x40042002;
CHECKREG r5, 0x50052802;
CHECKREG r6, 0x60063003;
CHECKREG r7, 0x70073803;
imm32 r0, 0x1001e000;
imm32 r1, 0x1001e000;
R2.L = -15;
imm32 r3, 0x3003e000;
imm32 r4, 0x4004e000;
imm32 r5, 0x5005e000;
imm32 r6, 0x6006e000;
imm32 r7, 0x7007e000;
R0.L = R0.H >> 15;
R1.L = R1.H >> 15;
R2.L = R2.H >> 15;
R3.L = R3.H >> 15;
R4.L = R4.H >> 15;
R5.L = R5.H >> 15;
R6.L = R6.H >> 15;
R7.L = R7.H >> 15;
CHECKREG r0, 0x10010000;
CHECKREG r1, 0x10010000;
CHECKREG r2, 0x20020000;
CHECKREG r3, 0x30030000;
CHECKREG r4, 0x40040000;
CHECKREG r5, 0x50050000;
CHECKREG r6, 0x60060000;
CHECKREG r7, 0x70070000;
imm32 r0, 0x1001f001;
imm32 r1, 0x1001f001;
imm32 r2, 0x2002f002;
R3.L = -16;
imm32 r4, 0x4004f004;
imm32 r5, 0x5005f005;
imm32 r6, 0x6006f006;
imm32 r7, 0x7007f007;
R0.L = R0.H >> 13;
R1.L = R1.H >> 13;
R2.L = R2.H >> 13;
R3.L = R3.H >> 13;
R4.L = R4.H >> 13;
R5.L = R5.H >> 13;
R6.L = R6.H >> 13;
R7.L = R7.H >> 13;
CHECKREG r0, 0x10010000;
CHECKREG r1, 0x10010000;
CHECKREG r2, 0x20020001;
CHECKREG r3, 0x30030001;
CHECKREG r4, 0x40040002;
CHECKREG r5, 0x50050002;
CHECKREG r6, 0x60060003;
CHECKREG r7, 0x70070003;
// RLx by RLx
imm32 r0, 0x00001001;
imm32 r1, 0x00001001;
imm32 r2, 0x00001002;
imm32 r3, 0x00001003;
imm32 r4, 0x00001000;
imm32 r5, 0x00001005;
imm32 r6, 0x00001006;
imm32 r7, 0x00001007;
R0.H = R0.L >> 14;
R1.H = R1.L >> 14;
R2.H = R2.L >> 14;
R3.H = R3.L >> 14;
R4.H = R4.L >> 14;
R5.H = R5.L >> 14;
R6.H = R6.L >> 14;
R7.H = R7.L >> 14;
CHECKREG r0, 0x00001001;
CHECKREG r1, 0x00001001;
CHECKREG r2, 0x00001002;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00001000;
CHECKREG r5, 0x00001005;
CHECKREG r6, 0x00001006;
CHECKREG r7, 0x00001007;
imm32 r0, 0x00002001;
imm32 r1, 0x00002001;
imm32 r2, 0x00002002;
imm32 r3, 0x00002003;
imm32 r4, 0x00002004;
R5.L = -1;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = R0.L >> 5;
R1.H = R1.L >> 5;
R2.H = R2.L >> 5;
R3.H = R3.L >> 5;
R4.H = R4.L >> 5;
R5.H = R5.L >> 5;
R6.H = R6.L >> 5;
R7.H = R7.L >> 5;
CHECKREG r0, 0x01002001;
CHECKREG r1, 0x01002001;
CHECKREG r2, 0x01002002;
CHECKREG r3, 0x01002003;
CHECKREG r4, 0x01002004;
CHECKREG r5, 0x07FFFFFF;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
imm32 r0, 0x30001001;
imm32 r1, 0x30001001;
imm32 r1, 0x30002002;
imm32 r3, 0x30003003;
imm32 r4, 0x30004004;
imm32 r5, 0x30005005;
R6.L = -15;
imm32 r7, 0x00007007;
R0.H = R0.L >> 15;
R1.H = R1.L >> 15;
R2.H = R2.L >> 15;
R3.H = R3.L >> 15;
R4.H = R4.L >> 15;
R5.H = R5.L >> 15;
R6.H = R6.L >> 15;
R7.H = R7.L >> 15;
CHECKREG r0, 0x00001001;
CHECKREG r1, 0x00002002;
CHECKREG r2, 0x00002002;
CHECKREG r3, 0x00003003;
CHECKREG r4, 0x00004004;
CHECKREG r5, 0x00005005;
CHECKREG r6, 0x0001FFF1;
CHECKREG r7, 0x00007007;
imm32 r0, 0x40001001;
imm32 r1, 0x40002001;
imm32 r2, 0x40002002;
imm32 r3, 0x40003003;
imm32 r4, 0x40004004;
imm32 r5, 0x40005005;
imm32 r6, 0x40006006;
R7.L = -16;
R0.H = R0.L >> 7;
R1.H = R1.L >> 7;
R2.H = R2.L >> 7;
R3.H = R3.L >> 7;
R4.H = R4.L >> 7;
R5.H = R5.L >> 7;
R6.H = R6.L >> 7;
R7.H = R7.L >> 7;
CHECKREG r0, 0x00201001;
CHECKREG r1, 0x00402001;
CHECKREG r2, 0x00402002;
CHECKREG r3, 0x00603003;
CHECKREG r4, 0x00804004;
CHECKREG r5, 0x00A05005;
CHECKREG r6, 0x00C06006;
CHECKREG r7, 0x01FFFFF0;
// RHx by RLx
imm32 r0, 0x50010000;
imm32 r1, 0x50010000;
imm32 r2, 0x50020000;
imm32 r3, 0x50030000;
R4.L = -1;
imm32 r5, 0x50050000;
imm32 r6, 0x50060000;
imm32 r7, 0x50070000;
R0.H = R0.H >> 1;
R1.H = R1.H >> 1;
R2.H = R2.H >> 1;
R3.H = R3.H >> 1;
R4.H = R4.H >> 1;
R5.H = R5.H >> 1;
R6.H = R6.H >> 1;
R7.H = R7.H >> 1;
CHECKREG r0, 0x28000000;
CHECKREG r1, 0x28000000;
CHECKREG r2, 0x28010000;
CHECKREG r3, 0x28010000;
CHECKREG r4, 0x0040FFFF;
CHECKREG r5, 0x28020000;
CHECKREG r6, 0x28030000;
CHECKREG r7, 0x28030000;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
R5.L = -1;
imm32 r6, 0x60060000;
imm32 r7, 0x70070000;
R0.H = R0.H >> 5;
R1.H = R1.H >> 5;
R2.H = R2.H >> 5;
R3.H = R3.H >> 5;
R4.H = R4.H >> 5;
R5.H = R5.H >> 5;
R6.H = R6.H >> 5;
R7.H = R7.H >> 5;
CHECKREG r0, 0x00800000;
CHECKREG r1, 0x00800000;
CHECKREG r2, 0x01000000;
CHECKREG r3, 0x01800000;
CHECKREG r4, 0x02000000;
CHECKREG r5, 0x0140FFFF;
CHECKREG r6, 0x03000000;
CHECKREG r7, 0x03800000;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
R6.L = -15;
imm32 r7, 0x70070000;
R0.L = R0.H >> 6;
R1.L = R1.H >> 6;
R2.L = R2.H >> 6;
R3.L = R3.H >> 6;
R4.L = R4.H >> 6;
R5.L = R5.H >> 6;
R6.L = R6.H >> 6;
R7.L = R7.H >> 6;
CHECKREG r0, 0x10010040;
CHECKREG r1, 0x10010040;
CHECKREG r2, 0x20020080;
CHECKREG r3, 0x300300C0;
CHECKREG r4, 0x40040100;
CHECKREG r5, 0x50050140;
CHECKREG r6, 0x0300000C;
CHECKREG r7, 0x700701C0;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r2, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
imm32 r6, 0x60060000;
R7.L = -16;
R0.H = R0.H >> 15;
R1.H = R1.H >> 15;
R2.H = R2.H >> 15;
R3.H = R3.H >> 15;
R4.H = R4.H >> 15;
R5.H = R5.H >> 15;
R6.H = R6.H >> 15;
R7.H = R7.H >> 15;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x000000C0;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x0000FFF0;
pass
|
stsp/binutils-ia16
| 10,550
|
sim/testsuite/bfin/c_ldst_st_p_d_mm.s
|
//Original:testcases/core/c_ldst_st_p_d_mm/c_ldst_st_p_d_mm.dsp
// Spec Reference: c_ldst st_p++/p--
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
loadsym i3, DATA_ADDR_7;
P3 = I1; SP = I3;
[ P5 ++ ] = R0;
[ P1 ++ ] = R1;
[ P2 ++ ] = R2;
[ P3 ++ ] = R3;
[ P4 ++ ] = R4;
[ FP ++ ] = R5;
[ SP ++ ] = R6;
[ P5 ++ ] = R2;
[ P1 ++ ] = R3;
[ P2 ++ ] = R4;
[ P3 ++ ] = R5;
[ P4 ++ ] = R6;
[ FP ++ ] = R7;
[ SP ++ ] = R0;
[ P5 ++ ] = R5;
[ P1 ++ ] = R6;
[ P2 ++ ] = R7;
[ P3 ++ ] = R0;
[ P4 ++ ] = R1;
[ FP ++ ] = R2;
[ SP ++ ] = R3;
[ P5 ++ ] = R7;
[ P1 ++ ] = R0;
[ P2 ++ ] = R1;
[ P3 ++ ] = R2;
[ P4 ++ ] = R3;
[ FP ++ ] = R4;
[ SP ++ ] = R5;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
loadsym i3, DATA_ADDR_7;
P3 = I1; SP = I3;
R0 = [ P1 ++ ];
R1 = [ P2 ++ ];
R2 = [ P3 ++ ];
R3 = [ P4 ++ ];
R4 = [ P5 ++ ];
R5 = [ FP ++ ];
R6 = [ SP ++ ];
CHECKREG r0, 0x1B342618;
CHECKREG r1, 0x2C453729;
CHECKREG r2, 0x3D56483A;
CHECKREG r3, 0x4E67594B;
CHECKREG r4, 0x0A231507;
CHECKREG r5, 0x5F786A5C;
CHECKREG r6, 0x60897B6D;
CHECKREG r7, 0x719A8C7E;
R0 = [ P1 ++ ];
R1 = [ P2 ++ ];
R2 = [ P3 ++ ];
R3 = [ P4 ++ ];
R4 = [ P5 ++ ];
R5 = [ FP ++ ];
R6 = [ SP ++ ];
CHECKREG r0, 0x3D56483A;
CHECKREG r1, 0x4E67594B;
CHECKREG r2, 0x5F786A5C;
CHECKREG r3, 0x60897B6D;
CHECKREG r4, 0x2C453729;
CHECKREG r5, 0x719A8C7E;
CHECKREG r6, 0x0A231507;
CHECKREG r7, 0x719A8C7E;
R1 = [ P1 ++ ];
R2 = [ P2 ++ ];
R3 = [ P3 ++ ];
R4 = [ P4 ++ ];
R5 = [ P5 ++ ];
R6 = [ FP ++ ];
R7 = [ SP ++ ];
CHECKREG r0, 0x3D56483A;
CHECKREG r1, 0x60897B6D;
CHECKREG r2, 0x719A8C7E;
CHECKREG r3, 0x0A231507;
CHECKREG r4, 0x1B342618;
CHECKREG r5, 0x5F786A5C;
CHECKREG r6, 0x2C453729;
CHECKREG r7, 0x3D56483A;
R3 = [ P1 ++ ];
R4 = [ P2 ++ ];
R5 = [ P3 ++ ];
R6 = [ P4 ++ ];
R7 = [ P5 ++ ];
R0 = [ FP ++ ];
R1 = [ SP ++ ];
CHECKREG r0, 0x4E67594B;
CHECKREG r1, 0x5F786A5C;
CHECKREG r2, 0x719A8C7E;
CHECKREG r3, 0x0A231507;
CHECKREG r4, 0x1B342618;
CHECKREG r5, 0x2C453729;
CHECKREG r6, 0x3D56483A;
CHECKREG r7, 0x719A8C7E;
// reset values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x20;
loadsym p1, DATA_ADDR_2, 0x20;
loadsym p2, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym p4, DATA_ADDR_5, 0x20;
loadsym fp, DATA_ADDR_6, 0x20;
loadsym i3, DATA_ADDR_7, 0x20;
P3 = I1; SP = I3;
[ P5 -- ] = R0;
[ P1 -- ] = R1;
[ P2 -- ] = R2;
[ P3 -- ] = R3;
[ P4 -- ] = R4;
[ FP -- ] = R5;
[ SP -- ] = R6;
[ P5 -- ] = R2;
[ P1 -- ] = R3;
[ P2 -- ] = R4;
[ P3 -- ] = R5;
[ P4 -- ] = R6;
[ FP -- ] = R7;
[ SP -- ] = R0;
[ P5 -- ] = R5;
[ P1 -- ] = R6;
[ P2 -- ] = R7;
[ P3 -- ] = R0;
[ P4 -- ] = R1;
[ FP -- ] = R2;
[ SP -- ] = R3;
[ P5 -- ] = R6;
[ P1 -- ] = R7;
[ P2 -- ] = R0;
[ P3 -- ] = R1;
[ P4 -- ] = R2;
[ FP -- ] = R3;
[ SP -- ] = R4;
[ P1 -- ] = R0;
[ P2 -- ] = R1;
[ P3 -- ] = R2;
[ P4 -- ] = R3;
[ FP -- ] = R4;
[ SP -- ] = R5;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x20;
loadsym p1, DATA_ADDR_2, 0x20;
loadsym p2, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym p4, DATA_ADDR_5, 0x20;
loadsym fp, DATA_ADDR_6, 0x20;
loadsym i3, DATA_ADDR_7, 0x20;
P3 = I1; SP = I3;
R0 = [ P1 -- ];
R1 = [ P2 -- ];
R2 = [ P3 -- ];
R3 = [ P4 -- ];
R4 = [ P5 -- ];
R5 = [ FP -- ];
R6 = [ SP -- ];
CHECKREG r0, 0x5F786A5C;
CHECKREG r1, 0x719A8C7E;
CHECKREG r2, 0x0A231507;
CHECKREG r3, 0x1B342618;
CHECKREG r4, 0x4E67594B;
CHECKREG r5, 0x2C453729;
CHECKREG r6, 0x3D56483A;
CHECKREG r7, 0x719A8C7E;
R2 = [ P1 -- ];
R3 = [ P2 -- ];
R4 = [ P3 -- ];
R5 = [ P4 -- ];
R6 = [ P5 -- ];
R7 = [ FP -- ];
R0 = [ SP -- ];
CHECKREG r0, 0x4E67594B;
CHECKREG r1, 0x719A8C7E;
CHECKREG r2, 0x0A231507;
CHECKREG r3, 0x1B342618;
CHECKREG r4, 0x2C453729;
CHECKREG r5, 0x3D56483A;
CHECKREG r6, 0x719A8C7E;
R3 = [ P1 -- ];
R4 = [ P2 -- ];
R5 = [ P3 -- ];
R6 = [ P4 -- ];
R7 = [ P5 -- ];
R0 = [ FP -- ];
R1 = [ SP -- ];
CHECKREG r0, 0x719A8C7E;
CHECKREG r1, 0x0A231507;
CHECKREG r2, 0x0A231507;
CHECKREG r3, 0x3D56483A;
CHECKREG r4, 0x719A8C7E;
CHECKREG r5, 0x4E67594B;
CHECKREG r6, 0x5F786A5C;
CHECKREG r7, 0x2C453729;
R5 = [ P1 -- ];
R6 = [ P2 -- ];
R7 = [ P3 -- ];
R0 = [ P4 -- ];
R1 = [ P5 -- ];
R2 = [ FP -- ];
R3 = [ SP -- ];
CHECKREG r0, 0x719A8C7E;
CHECKREG r1, 0x3D56483A;
CHECKREG r2, 0x0A231507;
CHECKREG r3, 0x1B342618;
CHECKREG r4, 0x719A8C7E;
CHECKREG r5, 0x719A8C7E;
CHECKREG r6, 0x4E67594B;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
|
stsp/binutils-ia16
| 5,551
|
sim/testsuite/bfin/random_0030.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x00a0cc80 | _VS | _AV1S | _AQ | _CC | _AN);
dmm32 A1.w, 0x8f7fea28;
dmm32 A1.x, 0x00000005;
imm32 R2, 0x000014f2;
imm32 R4, 0x7fff7fff;
imm32 R7, 0x14d3a258;
R7.H = (A1 -= R4.L * R2.H) (M, T);
checkreg R7, 0x7fffa258;
checkreg A1.w, 0x8f7fea28;
checkreg A1.x, 0x00000005;
checkreg ASTAT, (0x00a0cc80 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x7c90c410 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
dmm32 A1.w, 0xbfed6ffc;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x7fffffff;
imm32 R5, 0x00000000;
imm32 R6, 0xf70a7fff;
R0.H = (A1 -= R5.L * R6.L) (M, T);
checkreg ASTAT, (0x7c90c410 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
checkreg A1.w, 0xbfed6ffc;
checkreg A1.x, 0x00000000;
checkreg R0, 0x7fffffff;
checkreg R5, 0x00000000;
checkreg R6, 0xf70a7fff;
dmm32 ASTAT, (0x2c508a10 | _VS | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 A1.w, 0xfffd8001;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x00018000;
imm32 R4, 0x7fff8000;
imm32 R5, 0x7fff0002;
R3.H = (A1 += R5.L * R4.L) (M, T);
checkreg R3, 0x7fff8000;
checkreg A1.w, 0xfffe8001;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x2c508a10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY);
dmm32 ASTAT, (0x28408c90 | _VS | _AV1S | _AC0 | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0x842fbc0a;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x04c44422;
imm32 R3, 0x40f67fff;
imm32 R7, 0x448c0856;
R7.H = (A1 -= R3.L * R0.H) (M, T);
checkreg R7, 0x7fff0856;
checkreg A1.w, 0x81cdc0ce;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x28408c90 | _VS | _V | _AV1S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x44708c10 | _AV1S | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0xaa016cf5;
dmm32 A1.x, 0xffffffdb;
imm32 R2, 0x25908079;
imm32 R5, 0x46eabfcd;
imm32 R7, 0x67066230;
R2.H = (A1 += R5.L * R7.H) (M, T);
checkreg R2, 0x80008079;
checkreg A1.w, 0x902b66c3;
checkreg A1.x, 0xffffffdb;
checkreg ASTAT, (0x44708c10 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3c604090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x8eef28b0;
dmm32 A1.x, 0x00000023;
imm32 R0, 0x000156b2;
imm32 R1, 0xfc1a8000;
imm32 R5, 0x7fff7fff;
R5.H = (A1 += R1.L * R0.H) (M, T);
checkreg A1.w, 0x8eeea8b0;
checkreg A1.x, 0x00000023;
checkreg ASTAT, (0x3c604090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x74208e00 | _VS | _AV0S | _AC0 | _AQ | _AC0_COPY);
dmm32 A1.w, 0xed3c9973;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x80000000;
imm32 R1, 0x7fff8000;
imm32 R2, 0x00000000;
R1.H = (A1 -= R2.L * R0.H) (M, T);
checkreg ASTAT, (0x74208e00 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY);
checkreg A1.w, 0xed3c9973;
checkreg A1.x, 0x00000000;
checkreg R0, 0x80000000;
checkreg R1, 0x7fff8000;
checkreg R2, 0x00000000;
dmm32 ASTAT, (0x10308800 | _VS | _AV0S | _AC0 | _AC0_COPY);
dmm32 A1.w, 0x8b345e6e;
dmm32 A1.x, 0x00000000;
imm32 R3, 0xc40c1663;
imm32 R4, 0xd0347fff;
imm32 R7, 0x4249da20;
R3.H = (A1 += R4.L * R7.H) (M, T);
checkreg R3, 0x7fff1663;
checkreg A1.w, 0xac589c25;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x10308800 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x1c104880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AZ);
dmm32 A1.w, 0xa333ecbc;
dmm32 A1.x, 0xffffffea;
imm32 R2, 0x7fffffff;
imm32 R3, 0x72ea7fff;
imm32 R4, 0x07348ad1;
R4.H = (A1 += R2.L * R3.L) (M, T);
checkreg R4, 0x80008ad1;
checkreg A1.w, 0xa3336cbd;
checkreg A1.x, 0xffffffea;
checkreg ASTAT, (0x1c104880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AZ);
dmm32 ASTAT, (0x44904e00 | _VS);
dmm32 A1.w, 0x90202372;
dmm32 A1.x, 0xffffffc4;
imm32 R2, 0x138ac9fc;
imm32 R3, 0x720a427f;
imm32 R4, 0x800000f5;
R3.H = (A1 += R4.L * R2.H) (M, T);
checkreg R3, 0x8000427f;
checkreg A1.w, 0x9032d684;
checkreg A1.x, 0xffffffc4;
checkreg ASTAT, (0x44904e00 | _VS | _V | _V_COPY);
dmm32 ASTAT, (0x48f04c90 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
dmm32 A1.w, 0xe9c97364;
dmm32 A1.x, 0xffffffef;
imm32 R2, 0x001dffe9;
imm32 R3, 0x50f06d20;
imm32 R6, 0x6179b75b;
R6.H = (A1 -= R3.L * R2.L) (M, T);
checkreg R6, 0x8000b75b;
checkreg A1.w, 0x7cb34144;
checkreg A1.x, 0xffffffef;
checkreg ASTAT, (0x48f04c90 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x68d00e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0xf3d34812;
dmm32 A1.x, 0xffffff95;
imm32 R1, 0xf7419a18;
imm32 R6, 0x0fdf83b3;
imm32 R7, 0x0b831070;
R7.H = (A1 -= R6.L * R1.H) (M, T);
checkreg R7, 0x80001070;
checkreg A1.w, 0x6be1229f;
checkreg A1.x, 0xffffff96;
checkreg ASTAT, (0x68d00e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3060ce80 | _VS | _AV1S | _AC1 | _CC | _AN);
dmm32 A1.w, 0xe0c1fc60;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x00e97fff;
imm32 R7, 0x3fff0001;
R1.H = (A1 += R1.L * R7.H) (M, T);
checkreg R1, 0x7fff7fff;
checkreg A1.w, 0x00c13c61;
checkreg A1.x, 0x00000001;
checkreg ASTAT, (0x3060ce80 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x3c80c000 | _VS | _AV0S | _AC0_COPY | _AN);
dmm32 A1.w, 0xb0e43973;
dmm32 A1.x, 0xffffffbc;
imm32 R0, 0x511a6fe3;
imm32 R1, 0x43fe2c80;
imm32 R2, 0x424b5c19;
R0.H = (A1 -= R2.L * R1.H) (M, T);
checkreg R0, 0x80006fe3;
checkreg A1.w, 0x986e4da5;
checkreg A1.x, 0xffffffbc;
checkreg ASTAT, (0x3c80c000 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AN);
pass
|
stsp/binutils-ia16
| 2,624
|
sim/testsuite/bfin/c_ldimmhalf_lz_ibml.s
|
//Original:/testcases/core/c_ldimmhalf_lz_ibml/c_ldimmhalf_lz_ibml.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: ldimmhalf lz ibml
I0 = 0x2001 (Z);
I1 = 0x2003 (Z);
I2 = 0x2005 (Z);
I3 = 0x2007 (Z);
L0 = 0x2009 (Z);
L1 = 0x200b (Z);
L2 = 0x200d (Z);
L3 = 0x200f (Z);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x00002001;
CHECKREG r1, 0x00002003;
CHECKREG r2, 0x00002005;
CHECKREG r3, 0x00002007;
CHECKREG r4, 0x00002009;
CHECKREG r5, 0x0000200b;
CHECKREG r6, 0x0000200d;
CHECKREG r7, 0x0000200f;
I0 = 0x0111 (Z);
I1 = 0x1111 (Z);
I2 = 0x2222 (Z);
I3 = 0x3333 (Z);
L0 = 0x4444 (Z);
L1 = 0x5555 (Z);
L2 = 0x6666 (Z);
L3 = 0x7777 (Z);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x00000111;
CHECKREG r1, 0x00001111;
CHECKREG r2, 0x00002222;
CHECKREG r3, 0x00003333;
CHECKREG r4, 0x00004444;
CHECKREG r5, 0x00005555;
CHECKREG r6, 0x00006666;
CHECKREG r7, 0x00007777;
I0 = 0x8888 (Z);
I1 = 0x9aaa (Z);
I2 = 0xabbb (Z);
I3 = 0xbccc (Z);
L0 = 0xcddd (Z);
L1 = 0xdeee (Z);
L2 = 0xefff (Z);
L3 = 0xf111 (Z);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x00008888;
CHECKREG r1, 0x00009aaa;
CHECKREG r2, 0x0000abbb;
CHECKREG r3, 0x0000bccc;
CHECKREG r4, 0x0000cddd;
CHECKREG r5, 0x0000deee;
CHECKREG r6, 0x0000efff;
CHECKREG r7, 0x0000f111;
B0 = 0x3001 (Z);
B1 = 0x3003 (Z);
B2 = 0x3005 (Z);
B3 = 0x3007 (Z);
M0 = 0x3009 (Z);
M1 = 0x300b (Z);
M2 = 0x300d (Z);
M3 = 0x300f (Z);
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00003001;
CHECKREG r1, 0x00003003;
CHECKREG r2, 0x00003005;
CHECKREG r3, 0x00003007;
CHECKREG r4, 0x00003009;
CHECKREG r5, 0x0000300B;
CHECKREG r6, 0x0000300d;
CHECKREG r7, 0x0000300f;
B0 = 0x0110 (Z);
B1 = 0x1110 (Z);
B2 = 0x2220 (Z);
B3 = 0x3330 (Z);
M0 = 0x4440 (Z);
M1 = 0x5550 (Z);
M2 = 0x6660 (Z);
M3 = 0x7770 (Z);
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00000110;
CHECKREG r1, 0x00001110;
CHECKREG r2, 0x00002220;
CHECKREG r3, 0x00003330;
CHECKREG r4, 0x00004440;
CHECKREG r5, 0x00005550;
CHECKREG r6, 0x00006660;
CHECKREG r7, 0x00007770;
B0 = 0xf880 (Z);
B1 = 0xfaa0 (Z);
B2 = 0xfbb0 (Z);
B3 = 0xfcc0 (Z);
M0 = 0xfdd0 (Z);
M1 = 0xfee0 (Z);
M2 = 0xfff0 (Z);
M3 = 0xf110 (Z);
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x0000f880;
CHECKREG r1, 0x0000faa0;
CHECKREG r2, 0x0000fbb0;
CHECKREG r3, 0x0000fcc0;
CHECKREG r4, 0x0000fdd0;
CHECKREG r5, 0x0000fee0;
CHECKREG r6, 0x0000fff0;
CHECKREG r7, 0x0000f110;
pass
|
stsp/binutils-ia16
| 1,217
|
sim/testsuite/bfin/c_ccmv_cc_dr_pr.s
|
//Original:/proj/frio/dv/testcases/core/c_ccmv_cc_dr_pr/c_ccmv_cc_dr_pr.dsp
// Spec Reference: ccmv cc dpreg = dpreg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x138d2301;
imm32 r1, 0x20421053;
imm32 r2, 0x3f051405;
imm32 r3, 0x40b66507;
imm32 r4, 0x50487709;
imm32 r5, 0x6005908b;
imm32 r6, 0x7a0c6609;
imm32 r7, 0x890e108f;
imm32 p1, 0x9d021053;
imm32 p2, 0xafb41405;
imm32 p3, 0xb0bf1507;
imm32 p4, 0xd0483609;
imm32 p5, 0xe005d00b;
imm32 sp, 0xfa0c667d;
imm32 fp, 0xc90e108f;
IF CC R0 = P0;
IF CC P1 = R3;
IF CC R2 = P5;
IF CC P2 = R2;
CC = ! CC;
IF CC P3 = R6;
IF CC R5 = P1;
IF CC P4 = R7;
CC = ! CC;
IF CC R7 = P4;
IF CC P5 = R3;
IF CC R6 = SP;
IF CC R3 = P2;
CC = ! CC;
IF CC SP = R6;
IF CC R1 = P5;
IF CC FP = R4;
CC = ! CC;
IF CC R3 = P3;
CHECKREG r0, 0x138D2301;
CHECKREG r1, 0xE005D00B;
CHECKREG r2, 0x3F051405;
CHECKREG r3, 0x40B66507;
CHECKREG r4, 0x50487709;
CHECKREG r5, 0x9D021053;
CHECKREG r6, 0x7A0C6609;
CHECKREG r7, 0x890E108F;
CHECKREG p1, 0x9D021053;
CHECKREG p2, 0xAFB41405;
CHECKREG p3, 0x7A0C6609;
CHECKREG p4, 0x890E108F;
CHECKREG p5, 0xE005D00B;
CHECKREG sp, 0x7A0C6609;
CHECKREG fp, 0x50487709;
pass
|
stsp/binutils-ia16
| 1,700
|
sim/testsuite/bfin/c_dsp32mac_pair_mix.s
|
//Original:/testcases/core/c_dsp32mac_pair_mix/c_dsp32mac_pair_mix.dsp
// Spec Reference: dsp32mac pair mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00060007;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
A0 = 0;
ASTAT = R0;
// The result accumulated in A0 and A1, and stored to a reg pair
imm32 r0, 0x00120034;
imm32 r1, 0x00050006;
R3 = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
R5 = ( A1 = R1.L * R0.H );
R7 = ( A1 = R1.L * R0.H ) (M), A0 = R1.H * R0.L;
CHECKREG r2, 0x00040005;
CHECKREG r3, 0x000000d8;
CHECKREG r4, 0x00080009;
CHECKREG r5, 0x000000d8;
CHECKREG r6, 0x000C000D;
CHECKREG r7, 0x0000006c;
A1 = R1.L * R0.H, R2 = ( A0 += R1.H * R0.L );
A1 = R1.L * R0.H (M), R6 = ( A0 -= R1.H * R0.L );
CHECKREG r2, 0x00000410;
CHECKREG r3, 0x000000d8;
CHECKREG r4, 0x00080009;
CHECKREG r5, 0x000000d8;
CHECKREG r6, 0x00000208;
CHECKREG r7, 0x0000006c;
R3 = ( A1 = R1.L * R0.H ), R2 = ( A0 += R1.H * R0.L ) (S2RND);
R5 = ( A1 = R1.L * R0.H ) (M), R4 = ( A0 -= R1.H * R0.L ) (S2RND);
CHECKREG r2, 0x00000820;
CHECKREG r3, 0x000001B0;
CHECKREG r4, 0x00000410;
CHECKREG r5, 0x000000D8;
imm32 r0, 0x12345678;
imm32 r1, 0x34567897;
imm32 r2, 0x0acb1234;
imm32 r3, 0x456acb07;
imm32 r4, 0x421dbc09;
imm32 r5, 0x89acbd0b;
imm32 r6, 0x5adbcd0d;
imm32 r7, 0x9abc230f;
A1 += R7.L * R5.H, R2 = ( A0 = R7.H * R5.L );
A1 -= R1.H * R2.L (M), R6 = ( A0 += R1.L * R2.H ) (S2RND);
CHECKREG r0, 0x12345678;
CHECKREG r1, 0x34567897;
CHECKREG r2, 0x34F8E428;
CHECKREG r3, 0x456ACB07;
CHECKREG r4, 0x421DBC09;
CHECKREG r5, 0x89ACBD0B;
CHECKREG r6, 0x7FFFFFFF;
CHECKREG r7, 0x9ABC230F;
pass
|
stsp/binutils-ia16
| 1,158
|
sim/testsuite/bfin/c_dsp32shiftim_lf.s
|
//Original:/testcases/core/c_dsp32shiftim_lf/c_dsp32shiftim_lf.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm lshift: lshift
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8912cde;
R0 = R0 << 0;
R1 = R1 << 3;
R2 = R2 << 7;
R3 = R3 << 8;
R4 = R4 << 15;
R5 = R5 << 24;
R6 = R6 << 31;
R7 = R7 << 20;
CHECKREG r0, 0xA1230001;
CHECKREG r1, 0xD9A2B3C0;
CHECKREG r2, 0xE2B3C480;
CHECKREG r3, 0xD6789A00;
CHECKREG r4, 0xC4D58000;
CHECKREG r5, 0xBC000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0xCDE00000;
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8912cde;
R6 = R0 >> 1;
R7 = R1 >> 3;
R0 = R2 >> 7;
R1 = R3 >> 8;
R2 = R4 >> 15;
R3 = R5 >> 24;
R4 = R6 >> 31;
R5 = R7 >> 20;
CHECKREG r0, 0x00478ACF;
CHECKREG r1, 0x0034D678;
CHECKREG r2, 0x00010B4F;
CHECKREG r3, 0x00000096;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000036;
CHECKREG r6, 0x50918000;
CHECKREG r7, 0x03668ACF;
pass
|
stsp/binutils-ia16
| 1,791
|
sim/testsuite/bfin/c_progctrl_except_rtx.S
|
//Original:/proj/frio/dv/testcases/core/c_progctrl_except_rtx/c_progctrl_except_rtx.dsp
// Spec Reference: c_progctrl_except_rtx
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
// load address of exception handler
P0 = 0x200C (Z); // 0xFFE0200C EVT3 EXCEPTION
P0.H = 0xFFE0;
R0 = exception_handler (Z); // wr address of exception handler to MMR EVT3
R0.H = exception_handler;
[ P0 ] = R0;
// Jump to User mode and enable exceptions
R0 = MidUserCode (Z);
R0.H = MidUserCode;
RETI = R0;
RTI; // cause it to go to Midusercode, .dd cause exception
BeginUserCode:
P1 = 1;
P2 = 2;
P3 = 3;
P4 = 4;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000001);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000003);
CHECKREG(r5, 0x00000000);
CHECKREG(r6, 0x00000000);
CHECKREG(r7, 0x00000000);
CHECKREG(p1, 0x00000001);
CHECKREG(p2, 0x00000002);
CHECKREG(p3, 0x00000003);
CHECKREG(p4, 0x00000004);
dbg_pass;
//jump 2;
//jump -2;
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
//dbg_pass;
MidUserCode:
.dd 0xFFFFFFFF
R0 = 0;
R1 = 1;
R2 = 2;
R3 = 3;
CC = R0;
IF !CC JUMP BeginUserCode;
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
exception_handler:
R4 = RETX; // error handler: RETX has the address of the same Illegal instr
R1 += 1;
R2 += 2;
R3 += 3;
R1 += 1;
R4 += 4; // we have to add 4 to point to next instr after return
RETX = R4;
RTX; // return from exception
.section MEM_DATA_ADDR_1,"aw"
.dd 0xDEADBEEF
.dd 0xBAD00BAD
|
stsp/binutils-ia16
| 5,300
|
sim/testsuite/bfin/c_ldst_ld_p_p.s
|
//Original:/testcases/core/c_ldst_ld_p_p/c_ldst_ld_p_p.dsp
// Spec Reference: c_ldst ld p [p]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
P2 = [ P1 ];
P4 = [ P1 ];
P5 = [ P1 ];
FP = [ P1 ];
CHECKREG p2, 0x78910213;
CHECKREG p4, 0x78910213;
CHECKREG p5, 0x78910213;
CHECKREG fp, 0x78910213;
loadsym p2, DATA_ADDR_2;
P1 = [ P2 ];
P4 = [ P2 ];
P5 = [ P2 ];
FP = [ P2 ];
CHECKREG p1, 0x20212223;
CHECKREG p4, 0x20212223;
CHECKREG p5, 0x20212223;
CHECKREG fp, 0x20212223;
loadsym p4, DATA_ADDR_4;
P1 = [ P4 ];
P2 = [ P4 ];
P5 = [ P4 ];
FP = [ P4 ];
CHECKREG p1, 0x60616263;
CHECKREG p2, 0x60616263;
CHECKREG p5, 0x60616263;
CHECKREG fp, 0x60616263;
loadsym p5, DATA_ADDR_5;
P1 = [ P5 ];
P2 = [ P5 ];
P4 = [ P5 ];
FP = [ P5 ];
CHECKREG p1, 0x8A8B8C8D;
CHECKREG p2, 0x8A8B8C8D;
CHECKREG p4, 0x8A8B8C8D;
CHECKREG fp, 0x8A8B8C8D;
loadsym fp, DATA_ADDR_7;
P1 = [ FP ];
P2 = [ FP ];
P4 = [ FP ];
P5 = [ FP ];
CHECKREG p1, 0x80818283;
CHECKREG p2, 0x80818283;
CHECKREG p4, 0x80818283;
CHECKREG p5, 0x80818283;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x78910213
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x8A8B8C8D
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 3,526
|
sim/testsuite/bfin/c_dsp32mac_dr_a1_tu.s
|
//Original:/testcases/core/c_dsp32mac_dr_a1_tu/c_dsp32mac_dr_a1_tu.dsp
// Spec Reference: dsp32mac dr_a1 tu (truncate signed fraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd0069007;
imm32 r4, 0xefbc4569;
imm32 r5, 0xcd35500b;
imm32 r6, 0xe00c800d;
imm32 r7, 0xf78e900f;
R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (TFU);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (TFU);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (TFU);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (TFU);
R7 = A1.w;
CHECKREG r0, 0x5A4E5ABD;
CHECKREG r1, 0x5A4E0EEB;
CHECKREG r2, 0x00008679;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x4AF54569;
CHECKREG r5, 0x4AF50D14;
CHECKREG r6, 0xFFFF800D;
CHECKREG r7, 0x239CE7BC;
// The result accumulated in A1, and stored to a reg half (MNOP)
imm32 r0, 0x63548abd;
imm32 r1, 0x7dbcfec7;
imm32 r2, 0xC5885679;
imm32 r3, 0xC5880000;
imm32 r4, 0xcfbc4569;
imm32 r5, 0xd235c00b;
imm32 r6, 0xe00ca00d;
imm32 r7, 0x678e700f;
R0.H = ( A1 = R1.L * R0.L ) (TFU);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (TFU);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (TFU);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (TFU);
R7 = A1.w;
CHECKREG r0, 0x8A138ABD;
CHECKREG r1, 0x8A135EEB;
CHECKREG r2, 0xCCCC5679;
CHECKREG r3, 0xCCCC6C33;
CHECKREG r4, 0x30F64569;
CHECKREG r5, 0x30F67F1F;
CHECKREG r6, 0x5AA1A00D;
CHECKREG r7, 0x5AA11AA8;
// The result accumulated in A1 , and stored to a reg half (MNOP)
imm32 r0, 0x5354babd;
imm32 r1, 0x6dbcdec7;
imm32 r2, 0x7124e679;
imm32 r3, 0x80067007;
imm32 r4, 0x9fbc4569;
imm32 r5, 0xa235900b;
imm32 r6, 0xb00c300d;
imm32 r7, 0xc78ea00f;
R0.H = A1 , A0 -= R1.L * R0.L (TFU);
R1 = A1.w;
R2.H = A1 , A0 += R2.H * R3.L (TFU);
R3 = A1.w;
R4.H = A1 , A0 -= R4.H * R5.H (TFU);
R5 = A1.w;
R6.H = A1 , A0 = R6.L * R7.H (TFU);
R7 = A1.w;
CHECKREG r0, 0x5AA1BABD;
CHECKREG r1, 0x5AA11AA8;
CHECKREG r2, 0x5AA1E679;
CHECKREG r3, 0x5AA11AA8;
CHECKREG r4, 0x5AA14569;
CHECKREG r5, 0x5AA11AA8;
CHECKREG r6, 0x5AA1300D;
CHECKREG r7, 0x5AA11AA8;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71245679;
imm32 r3, 0x90060007;
imm32 r4, 0xafbc4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00ca00d;
imm32 r7, 0x678ed00f;
R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (TFU);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (TFU);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (TFU);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (TFU);
R7 = A1.w;
CHECKREG r0, 0xFF915ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x30375679;
CHECKREG r3, 0x303725C1;
CHECKREG r4, 0x5D604569;
CHECKREG r5, 0x5D60D8AD;
CHECKREG r6, 0x4382A00D;
CHECKREG r7, 0x43823355;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x92005ABD;
imm32 r1, 0x09300000;
imm32 r2, 0x56749679;
imm32 r3, 0x30A95000;
imm32 r4, 0xa0009669;
imm32 r5, 0x01000970;
imm32 r6, 0xdf45609D;
imm32 r7, 0x12345679;
R0.H = ( A1 += R1.L * R0.L ) (M,TFU);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M,TFU);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ) (M,TFU);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (M,TFU);
R7 = A1.w;
CHECKREG r0, 0x43825ABD;
CHECKREG r1, 0x43823355;
CHECKREG r2, 0x57919679;
CHECKREG r3, 0x57912D74;
CHECKREG r4, 0xFC769669;
CHECKREG r5, 0xFC760000;
CHECKREG r6, 0xFEC9609D;
CHECKREG r7, 0xFEC9CBFC;
pass
|
stsp/binutils-ia16
| 10,413
|
sim/testsuite/bfin/se_loop_ppm.S
|
//Original:/proj/frio/dv/testcases/seq/se_loop_ppm/se_loop_ppm.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
LSETUP ( l0s , l0s ) LC0 = P0;
l0s:[ -- SP ] = ( R7:5 );
LSETUP ( l1s , l1e ) LC0 = P0;
l1s:R5 += 1;
l1e:[ -- SP ] = ( R7:5 );
LSETUP ( l2s , l2e ) LC0 = P0;
l2s:R5 += 1;
R6 += 2;
l2e:[ -- SP ] = ( R7:5 );
LSETUP ( l3s , l3e ) LC0 = P0;
l3s:R5 += 1;
R6 += 2;
R7 += 3;
l3e:[ -- SP ] = ( R7:5 );
LSETUP ( l4s , l4e ) LC0 = P0;
l4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
l4e:[ -- SP ] = ( R7:4 );
LSETUP ( l5s , l5e ) LC0 = P0;
l5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
l5e:[ -- SP ] = ( R7:4 );
LSETUP ( l6s , l6e ) LC1 = P0;
l6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
l6e:[ -- SP ] = ( R7:4 );
NOP;
LSETUP ( m0s , m0s ) LC1 = P0;
m0s:[ -- SP ] = ( R7:5 );
LSETUP ( m1s , m1e ) LC1 = P0;
m1s:R5 += 1;
m1e:[ -- SP ] = ( R7:5 );
LSETUP ( m2s , m2e ) LC1 = P0;
m2s:R5 += 1;
R6 += 2;
m2e:[ -- SP ] = ( R7:5 );
LSETUP ( m3s , m3e ) LC1 = P0;
m3s:R5 += 1;
R6 += 2;
R7 += 3;
m3e:[ -- SP ] = ( R7:5 );
LSETUP ( m4s , m4e ) LC1 = P0;
m4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
m4e:[ -- SP ] = ( R7:4 );
LSETUP ( m5s , m5e ) LC1 = P0;
m5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
m5e:[ -- SP ] = ( R7:4 );
LSETUP ( m6s , m6e ) LC1 = P0;
m6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
m6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 1,691
|
sim/testsuite/bfin/c_dagmodim_lnz_imltbl.s
|
//Original:/testcases/core/c_dagmodim_lnz_imltbl/c_dagmodim_lnz_imltbl.dsp
// Spec Reference: dagmodim l not zero & i+m < b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x0000110e;
imm32 b1, 0x0000110c;
imm32 b2, 0x0000110a;
imm32 b3, 0x00001108;
imm32 l0, 0x000000a1;
imm32 l1, 0x000000b2;
imm32 l2, 0x000000c3;
imm32 l3, 0x000000d4;
imm32 m0, 0x00000005;
imm32 m1, 0x00000004;
imm32 m2, 0x00000003;
imm32 m3, 0x00000002;
I0 += M0;
I1 += M1;
I2 += M2;
I3 += M3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += M1;
I1 += M2;
I2 += M3;
I3 += M0;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001005;
CHECKREG r1, 0x00001104;
CHECKREG r2, 0x00001013;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00001009;
CHECKREG r5, 0x00001107;
CHECKREG r6, 0x00001015;
CHECKREG r7, 0x00001008;
I0 -= M2;
I1 -= M3;
I2 -= M0;
I3 -= M1;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 -= M3;
I1 -= M2;
I2 -= M1;
I3 -= M0;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x000010A7;
CHECKREG r1, 0x000011B7;
CHECKREG r2, 0x000010D3;
CHECKREG r3, 0x000010D8;
CHECKREG r4, 0x00001146;
CHECKREG r5, 0x000011B4;
CHECKREG r6, 0x00001192;
CHECKREG r7, 0x000011A7;
I0 += M3 (BREV);
I1 += M0 (BREV);
I2 += M1 (BREV);
I3 += M2 (BREV);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += M2 (BREV);
I1 += M3 (BREV);
I2 += M0 (BREV);
I3 += M1 (BREV);
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001145;
CHECKREG r1, 0x000011B3;
CHECKREG r2, 0x00001196;
CHECKREG r3, 0x000011A5;
CHECKREG r4, 0x00001146;
CHECKREG r5, 0x000011B0;
CHECKREG r6, 0x00001190;
CHECKREG r7, 0x000011A3;
pass
|
stsp/binutils-ia16
| 9,187
|
sim/testsuite/bfin/c_ldstii_ld_dreg.s
|
//Original:testcases/core/c_ldstii_ld_dreg/c_ldstii_ld_dreg.dsp
// Spec Reference: c_ldstii load dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0x04;
loadsym i1, DATA_ADDR_3, 0x04;
loadsym p4, DATA_ADDR_1, 0x00;
loadsym p5, DATA_ADDR_2, 0x00;
loadsym fp, DATA_ADDR_3, 0x00;
loadsym i3, DATA_ADDR_4, 0x00;
P3 = I1; SP = I3;
R0 = [ P1 + 0 ];
R1 = [ P1 + 4 ];
R2 = [ P1 + 8 ];
R3 = [ P1 + 12 ];
R4 = [ P1 + 16 ];
R5 = [ P1 + 20 ];
R6 = [ P1 + 24 ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x04050607;
CHECKREG r2, 0x08090A0B;
CHECKREG r3, 0x0C0D0E0F;
CHECKREG r4, 0x10111213;
CHECKREG r5, 0x14151617;
CHECKREG r6, 0x18191A1B;
R0 = [ P2 + 28 ];
R1 = [ P2 + 32 ];
R2 = [ P2 + 36 ];
R3 = [ P2 + 40 ];
R4 = [ P2 + 44 ];
R5 = [ P2 + 48 ];
R6 = [ P2 + 52 ];
CHECKREG r0, 0x91929394;
CHECKREG r1, 0x95969798;
CHECKREG r2, 0x99A1A2A3;
CHECKREG r3, 0xA5A6A7A8;
CHECKREG r4, 0xA9B0B1B2;
CHECKREG r5, 0xB3B4B5B6;
CHECKREG r6, 0xB7B8B9C0;
R0 = [ P3 + 56 ];
R1 = [ P3 + 60 ];
R2 = [ P3 + 64 ];
R3 = [ P3 + 60 ];
R4 = [ P3 + 56 ];
R5 = [ P3 + 52 ];
R6 = [ P3 + 48 ];
CHECKREG r0, 0x91E899EA;
CHECKREG r1, 0x92E899EA;
CHECKREG r2, 0x93E899EA;
CHECKREG r3, 0x92E899EA;
CHECKREG r4, 0x91E899EA;
CHECKREG r5, 0xE3E4E5E6;
CHECKREG r6, 0xDFE0E1E2;
R0 = [ P4 + 44 ];
R1 = [ P4 + 40 ];
R2 = [ P4 + 36 ];
R3 = [ P4 + 32 ];
R4 = [ P4 + 28 ];
R5 = [ P4 + 24 ];
R6 = [ P4 + 20 ];
CHECKREG r0, 0x74757677;
CHECKREG r1, 0x99717273;
CHECKREG r2, 0x55667788;
CHECKREG r3, 0x11223344;
CHECKREG r4, 0x1C1D1E1F;
CHECKREG r5, 0x18191A1B;
CHECKREG r6, 0x14151617;
R0 = [ P5 + 16 ];
R1 = [ P5 + 12 ];
R2 = [ P5 + 8 ];
R3 = [ P5 + 4 ];
R4 = [ P5 + 0 ];
R5 = [ P5 + 4 ];
R6 = [ P5 + 8 ];
CHECKREG r0, 0x30313233;
CHECKREG r1, 0x2C2D2E2F;
CHECKREG r2, 0x28292A2B;
CHECKREG r3, 0x24252627;
CHECKREG r4, 0x20212223;
CHECKREG r5, 0x24252627;
CHECKREG r6, 0x28292A2B;
R0 = [ FP + 12 ];
R1 = [ FP + 16 ];
R2 = [ FP + 20 ];
R3 = [ FP + 24 ];
R4 = [ FP + 28 ];
R5 = [ FP + 32 ];
R6 = [ FP + 36 ];
CHECKREG r0, 0x4C4D4E4F;
CHECKREG r1, 0x50515253;
CHECKREG r2, 0x54555657;
CHECKREG r3, 0x58595A5B;
CHECKREG r4, 0xC5C6C7C8;
CHECKREG r5, 0xC9CACBCD;
CHECKREG r6, 0xCFD0D1D2;
R0 = [ SP + 40 ];
R1 = [ SP + 44 ];
R2 = [ SP + 48 ];
R3 = [ SP + 52 ];
R4 = [ SP + 56 ];
R5 = [ SP + 60 ];
R6 = [ SP + 64 ];
CHECKREG r0, 0xF7F8F9FA;
CHECKREG r1, 0xFBFCFDFE;
CHECKREG r2, 0xFF000102;
CHECKREG r3, 0x03040506;
CHECKREG r4, 0x0708090A;
CHECKREG r5, 0x0B0CAD0E;
CHECKREG r6, 0xAB0CAD01;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 5,504
|
sim/testsuite/bfin/saatest.s
|
# mach: bfin
.include "testutils.inc"
start
I0 = 0 (X);
I1 = 0 (X);
A0 = A1 = 0;
init_r_regs 0;
ASTAT = R0;
// This section of code will test the SAA instructions and sum of accumulators;
loadsym I0, tstvecI;
R0 = [ I0 ++ ];
R2 = [ I0 ++ ];
// +++++++++++++++ TG11.001 +++++++++++++ //
// //
// HH HL LH LL //
// Input: r0 ==> 15 15 15 15 //
// r1 ==> 0 0 0 0 //
// //
// Output:r2 ==> 0 0 0 30 //
// r3 ==> 0 0 0 30 //
// ++++++++++++++++++++++++++++++++++++++++++ //
SAA ( R1:0 , R3:2 );
R6 = A1.L + A1.H, R7 = A0.L + A0.H;
DBGA ( R6.L , 0x001e );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x001e );
DBGA ( R7.H , 0x0000 );
A1 = A0 = 0;
// +++++++++++++++ TG11.002 +++++++++++++ //
// //
// HH HL LH LL //
// Input: r0 ==> 15 15 15 15 //
// r1 ==> 0 0 0 0 //
// //
// Output:r2 ==> 0 0 0 30 //
// r3 ==> 0 0 0 30 //
// ++++++++++++++++++++++++++++++++++++++++++ //
SAA ( R1:0 , R3:2 );
R6 = A1.L + A1.H, R7 = A0.L + A0.H;
DBGA ( R6.L , 0x001e );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x001e );
DBGA ( R7.H , 0x0000 );
A1 = A0 = 0;
// +++++++++++++++ TG11.003 +++++++++++++ //
// //
// HH HL LH LL //
// Input: r0 ==> 240 240 240 240 //
// r1 ==> 0 0 0 0 //
// //
// Output:r2 ==> 0 480 //
// r3 ==> 0 480 //
// ++++++++++++++++++++++++++++++++++++++++++ //
R0 = [ I0 ++ ];
R2 = [ I0 ++ ];
SAA ( R3:2 , R1:0 );
R6 = A1.L + A1.H, R7 = A0.L + A0.H;
DBGA ( R6.L , 0x01e0 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x01e0 );
DBGA ( R7.H , 0x0000 );
A1 = A0 = 0;
// +++++++++++++++ TG11.004 +++++++++++++ //
// //
// HH HL LH LL //
// Input: r0 ==> 240 240 240 240 //
// r1 ==> 0 0 0 0 //
// //
// Output:r2 ==> 0 480 //
// r3 ==> 0 480 //
// ++++++++++++++++++++++++++++++++++++++++++ //
SAA ( R1:0 , R3:2 );
R6 = A1.L + A1.H, R7 = A0.L + A0.H;
DBGA ( R6.L , 0x01e0 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x01e0 );
DBGA ( R7.H , 0x0000 );
A1 = A0 = 0;
// +++++++++++++++ TG11.005 +++++++++++++ //
// //
// HH HL LH LL //
// Input: r0 ==> 0 0 0 0 //
// r1 ==> 0 0 0 0 //
// //
// Output:r2 ==> 0 0 //
// r3 ==> 0 0 //
// ++++++++++++++++++++++++++++++++++++++++++ //
R0 = [ I0 ++ ];
R2 = [ I0 ++ ];
SAA ( R1:0 , R3:2 );
R6 = A1.L + A1.H, R7 = A0.L + A0.H;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
// +++++++++++++++ TG11.006 +++++++++++++ //
// //
// HH HL LH LL //
// Input: r0 ==> 255 255 255 255 //
// r1 ==> 255 255 255 255 //
// //
// Output:r2 ==> 0 0 //
// r3 ==> 0 0 //
// ++++++++++++++++++++++++++++++++++++++++++ //
SAA ( R3:2 , R1:0 );
R6 = A1.L + A1.H, R7 = A0.L + A0.H;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
A1 = A0 = 0;
// +++++++++++++++ TG12.001 +++++++++++++ //
// //
// HH HL LH LL //
// Input: r0 ==> 255 255 255 255 //
// r1 ==> 255 255 255 255 //
// //
// Output:r2 ==> 0 0 //
// r3 ==> 0 0 //
// ++++++++++++++++++++++++++++++++++++++++++ //
loadsym I0, tstvecK;
B0 = I0;
L0.L = 4;
loadsym I1, tstvecJ;
B1 = I1;
L1.L = 4;
P0 = 64 (X);
R0 = [ I0 ++ ];
R2 = [ I1 ++ ];
LSETUP ( l$1 , l$1 ) LC0 = P0;
l$1:
SAA ( R1:0 , R3:2 ) || R0 = [ I0 ++ ] || R1 = [ I1 ++ ];
R2 = A1.L + A1.H, R3 = A0.L + A0.H;
R7 = R2 + R3 (NS);
DBGA ( R7.L , 0xff00 );
DBGA ( R7.H , 0x0000 );
R5.L = 0xfffa;
A1 = R5;
R5.H = 0xfff0;
A0 = R5;
loadsym I0, tstvecI;
R0 = [ I0 ++ ];
R2 = [ I0 ++ ];
SAA ( R1:0 , R3:2 );
R6 = A1.L + A1.H, R7 = A0.L + A0.H;
DBGA ( R6.L , 0x000e );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0xfffe );
DBGA ( R7.H , 0xffff );
pass
.data
tstvecI:
.dw 0x0000
.dw 0x0000
.dw 0x0f0f
.dw 0x0f0f
.dw 0x0000
.dw 0x0000
.dw 0xf0f0
.dw 0xf0f0
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0xffff
.dw 0xffff
.dw 0xffff
.dw 0xffff
.data
tstvecJ:
.dw 0xffff
.dw 0xffff
.dw 0xffff
.dw 0xffff
.dw 0xffff
.dw 0xffff
.dw 0xffff
.dw 0xffff
.data
tstvecK:
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
|
stsp/binutils-ia16
| 8,498
|
sim/testsuite/bfin/c_seq_ex3_ls_brcc_mvp.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_brcc_mvp/c_seq_ex3_ls_brcc_mvp.dsp
// Spec Reference: sequencer stage ex3 (ldst + brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
R0 = 0;
ASTAT = R0;
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
[ -- SP ] = ( R7:0 );
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
//LD32(p2, DATA_ADDR_1);
loadsym p2, DATA;
LD32(r0, 0x55552345);
// RAISE 2; // RTN
// r0 = [p2++];
R1 = [ P1 ];
IF !CC JUMP LABEL1 (BP);
P3 = R7;
R4 = P3;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
// RAISE 5; // RTI
// r2 = [p2++];
R3 = [ P1 ];
IF CC JUMP LABEL2 (BP); // not taken
P4 = R6;
R4 = P4;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
// wrt-rd EVT5 = 0xFFE02034
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
// RAISE 6; // RTI
// r4 = [p2++];
R5 = [ P1 ];
IF !CC JUMP LABEL2 (BP);
P3 = R3;
R6 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
CSYNC;
CHECKREG(r0, 0x55552345);
//CHECKREG(r1, 0x000002B8);
CHECKREG(r2, 0x00000023);
CHECKREG(r3, 0x00000024);
CHECKREG(r4, 0x00000025);
//CHECKREG(r5, 0x000002B8);
// RAISE 7; // RTI
// r0 = [p2++];
R1 = [ P1 ];
P4 = R4;
R2 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x55552345);
//CHECKREG(r1, 0x000002B8);
CHECKREG(r2, 0x00000003);
//CHECKREG(r3, 0x000002B8);
CHECKREG(r4, 0x00000007);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
// wrt-rd EVT13 = 0xFFE02034
LD32(p1, 0xFFE02034);
// RAISE 8; // RTI
// r0 = [p2++];
R1 = [ P1 ];
IF !CC JUMP LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
CSYNC;
CHECKREG(r0, 0x55552345);
//CHECKREG(r1, 0x000002B8);
// RAISE 9; // RTI
P3 = R6;
R7 = P3;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.section MEM_DATA_ADDR_1,"aw"
DATA:
// .space (0x10);
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
.section MEM_DATA_ADDR_2,"aw"
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
|
stsp/binutils-ia16
| 3,054
|
sim/testsuite/bfin/c_pushpopmultiple_dreg.s
|
//Original:/testcases/core/c_pushpopmultiple_dreg/c_pushpopmultiple_dreg.dsp
// Spec Reference: pushpopmultiple dreg
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
[ -- SP ] = ( R7:0 );
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
( R7:0 ) = [ SP ++ ];
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000003;
CHECKREG r3, 0x00000004;
CHECKREG r4, 0x00000005;
CHECKREG r5, 0x00000006;
CHECKREG r6, 0x00000007;
CHECKREG r7, 0x00000008;
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
[ -- SP ] = ( R7:1 );
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
( R7:1 ) = [ SP ++ ];
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x00000013;
CHECKREG r3, 0x00000014;
CHECKREG r4, 0x00000015;
CHECKREG r5, 0x00000016;
CHECKREG r6, 0x00000017;
CHECKREG r7, 0x00000018;
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
[ -- SP ] = ( R7:2 );
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
( R7:2 ) = [ SP ++ ];
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x00000023;
CHECKREG r3, 0x00000024;
CHECKREG r4, 0x00000025;
CHECKREG r5, 0x00000026;
CHECKREG r6, 0x00000027;
CHECKREG r7, 0x00000028;
R3 = 0x34;
R4 = 0x35;
R5 = 0x36;
R6 = 0x37;
R7 = 0x38;
[ -- SP ] = ( R7:3 );
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
( R7:3 ) = [ SP ++ ];
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x00000023;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000035;
CHECKREG r5, 0x00000036;
CHECKREG r6, 0x00000037;
CHECKREG r7, 0x00000038;
R4 = 0x45 (X);
R5 = 0x46 (X);
R6 = 0x47 (X);
R7 = 0x48 (X);
[ -- SP ] = ( R7:4 );
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
( R7:4 ) = [ SP ++ ];
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x00000023;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000045;
CHECKREG r5, 0x00000046;
CHECKREG r6, 0x00000047;
CHECKREG r7, 0x00000048;
R5 = 0x56 (X);
R6 = 0x57 (X);
R7 = 0x58 (X);
[ -- SP ] = ( R7:5 );
R5 = 0;
R6 = 0;
R7 = 0;
( R7:5 ) = [ SP ++ ];
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x00000023;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000045;
CHECKREG r5, 0x00000056;
CHECKREG r6, 0x00000057;
CHECKREG r7, 0x00000058;
R6 = 0x67 (X);
R7 = 0x68 (X);
[ -- SP ] = ( R7:6 );
R6 = 0;
R7 = 0;
( R7:6 ) = [ SP ++ ];
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x00000023;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000045;
CHECKREG r5, 0x00000056;
CHECKREG r6, 0x00000067;
CHECKREG r7, 0x00000068;
R7 = 0x78 (X);
[ -- SP ] = ( R7:7 );
R7 = 0;
( R7:7 ) = [ SP ++ ];
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x00000023;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000045;
CHECKREG r5, 0x00000056;
CHECKREG r6, 0x00000067;
CHECKREG r7, 0x00000078;
pass
|
stsp/binutils-ia16
| 1,775
|
sim/testsuite/bfin/c_regmv_pr_pr.s
|
//Original:/testcases/core/c_regmv_pr_pr/c_regmv_pr_pr.dsp
// Spec Reference: regmv preg-to-preg
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
P1 = P1;
P2 = P1;
P4 = P1;
P5 = P1;
FP = P1;
CHECKREG p1, 0x20021003;
CHECKREG p2, 0x20021003;
CHECKREG p4, 0x20021003;
CHECKREG p5, 0x20021003;
CHECKREG fp, 0x20021003;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
P1 = P2;
P2 = P2;
P4 = P2;
P5 = P2;
FP = P2;
CHECKREG p1, 0x20041005;
CHECKREG p2, 0x20041005;
CHECKREG p4, 0x20041005;
CHECKREG p5, 0x20041005;
CHECKREG fp, 0x20041005;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
P1 = P4;
P2 = P4;
P4 = P4;
P5 = P4;
FP = P4;
CHECKREG p1, 0x20081009;
CHECKREG p2, 0x20081009;
CHECKREG p4, 0x20081009;
CHECKREG p5, 0x20081009;
CHECKREG fp, 0x20081009;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
P1 = P5;
P2 = P5;
P4 = P5;
P5 = P5;
FP = P5;
CHECKREG p1, 0x200a100b;
CHECKREG p2, 0x200a100b;
CHECKREG p4, 0x200a100b;
CHECKREG p5, 0x200a100b;
CHECKREG fp, 0x200a100b;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
P1 = FP;
P2 = FP;
P4 = FP;
P5 = FP;
FP = FP;
CHECKREG p1, 0x200e100f;
CHECKREG p2, 0x200e100f;
CHECKREG p4, 0x200e100f;
CHECKREG p5, 0x200e100f;
CHECKREG fp, 0x200e100f;
pass
|
stsp/binutils-ia16
| 4,199
|
sim/testsuite/bfin/c_logi2op_log_l_shft.s
|
//Original:/testcases/core/c_logi2op_log_l_shft/c_logi2op_log_l_shft.dsp
// Spec Reference: Logi2op <<=
# mach: bfin
.include "testutils.inc"
start
// Logical <<= : negative data
// bit 0-7
imm32 r0, 0x81111111;
imm32 r1, 0x81111111;
imm32 r2, 0x81111111;
imm32 r3, 0x81111111;
imm32 r4, 0x81111111;
imm32 r5, 0x81111111;
imm32 r6, 0x81111111;
imm32 r7, 0x81111111;
R0 <<= 0; /* r0 = 0x81111111 */
R1 <<= 1; /* r1 = 0x40888888 */
R2 <<= 2; /* r2 = 0x20444444 */
R3 <<= 3; /* r3 = 0x10222222 */
R4 <<= 4; /* r4 = 0x08111111 */
R5 <<= 5; /* r5 = 0x04088888 */
R6 <<= 6; /* r6 = 0x02044444 */
R7 <<= 7; /* r7 = 0x01022222 */
CHECKREG r0, 0x81111111;
CHECKREG r1, 0x02222222;
CHECKREG r2, 0x04444444;
CHECKREG r3, 0x08888888;
CHECKREG r4, 0x11111110;
CHECKREG r5, 0x22222220;
CHECKREG r6, 0x44444440;
CHECKREG r7, 0x88888880;
// bit 8-15
imm32 r0, 0x82222222;
imm32 r1, 0x82222222;
imm32 r2, 0x82222222;
imm32 r3, 0x82222222;
imm32 r4, 0x82222222;
imm32 r5, 0x82222222;
imm32 r6, 0x82222222;
imm32 r7, 0x82222222;
R0 <<= 8;
R1 <<= 9;
R2 <<= 10;
R3 <<= 11;
R4 <<= 12;
R5 <<= 13;
R6 <<= 14;
R7 <<= 15;
CHECKREG r0, 0x22222200;
CHECKREG r1, 0x44444400;
CHECKREG r2, 0x88888800;
CHECKREG r3, 0x11111000;
CHECKREG r4, 0x22222000;
CHECKREG r5, 0x44444000;
CHECKREG r6, 0x88888000;
CHECKREG r7, 0x11110000;
// bit 16-23
imm32 r0, 0x83333333;
imm32 r1, 0x83333333;
imm32 r2, 0x83333333;
imm32 r3, 0x83333333;
imm32 r4, 0x83333333;
imm32 r5, 0x83333333;
imm32 r6, 0x83333333;
imm32 r7, 0x83333333;
R0 <<= 16;
R1 <<= 17;
R2 <<= 18;
R3 <<= 19;
R4 <<= 20;
R5 <<= 21;
R6 <<= 22;
R7 <<= 23;
CHECKREG r0, 0x33330000;
CHECKREG r1, 0x66660000;
CHECKREG r2, 0xCCCC0000;
CHECKREG r3, 0x99980000;
CHECKREG r4, 0x33300000;
CHECKREG r5, 0x66600000;
CHECKREG r6, 0xCCC00000;
CHECKREG r7, 0x99800000;
// bit 24-31
imm32 r0, 0x84444444;
imm32 r1, 0x84444444;
imm32 r2, 0x84444444;
imm32 r3, 0x84444444;
imm32 r4, 0x84444444;
imm32 r5, 0x84444444;
imm32 r6, 0x84444444;
imm32 r7, 0x84444444;
R0 <<= 24;
R1 <<= 25;
R2 <<= 26;
R3 <<= 27;
R4 <<= 28;
R5 <<= 29;
R6 <<= 30;
R7 <<= 31;
CHECKREG r0, 0x44000000;
CHECKREG r1, 0x88000000;
CHECKREG r2, 0x10000000;
CHECKREG r3, 0x20000000;
CHECKREG r4, 0x40000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// Arithmetic <<= : positive data
// bit 0-7
imm32 r0, 0x41111111;
imm32 r1, 0x41111111;
imm32 r2, 0x41111111;
imm32 r3, 0x41111111;
imm32 r4, 0x41111111;
imm32 r5, 0x41111111;
imm32 r6, 0x41111111;
imm32 r7, 0x41111111;
R0 <<= 0;
R1 <<= 1;
R2 <<= 2;
R3 <<= 3;
R4 <<= 4;
R5 <<= 5;
R6 <<= 6;
R7 <<= 7;
CHECKREG r0, 0x41111111;
CHECKREG r1, 0x82222222;
CHECKREG r2, 0x04444444;
CHECKREG r3, 0x08888888;
CHECKREG r4, 0x11111110;
CHECKREG r5, 0x22222220;
CHECKREG r6, 0x44444440;
CHECKREG r7, 0x88888880;
// bit 8-15
imm32 r0, 0x42222222;
imm32 r1, 0x42222222;
imm32 r2, 0x42222222;
imm32 r3, 0x42222222;
imm32 r4, 0x42222222;
imm32 r5, 0x42222222;
imm32 r6, 0x42222222;
imm32 r7, 0x42222222;
R0 <<= 8;
R1 <<= 9;
R2 <<= 10;
R3 <<= 11;
R4 <<= 12;
R5 <<= 13;
R6 <<= 14;
R7 <<= 15;
CHECKREG r0, 0x22222200;
CHECKREG r1, 0x44444400;
CHECKREG r2, 0x88888800;
CHECKREG r3, 0x11111000;
CHECKREG r4, 0x22222000;
CHECKREG r5, 0x44444000;
CHECKREG r6, 0x88888000;
CHECKREG r7, 0x11110000;
// bit 16-23
imm32 r0, 0x43333333;
imm32 r1, 0x43333333;
imm32 r2, 0x43333333;
imm32 r3, 0x43333333;
imm32 r4, 0x43333333;
imm32 r5, 0x43333333;
imm32 r6, 0x43333333;
imm32 r7, 0x43333333;
R0 <<= 16;
R1 <<= 17;
R2 <<= 18;
R3 <<= 19;
R4 <<= 20;
R5 <<= 21;
R6 <<= 22;
R7 <<= 23;
CHECKREG r0, 0x33330000;
CHECKREG r1, 0x66660000;
CHECKREG r2, 0xCCCC0000;
CHECKREG r3, 0x99980000;
CHECKREG r4, 0x33300000;
CHECKREG r5, 0x66600000;
CHECKREG r6, 0xCCC00000;
CHECKREG r7, 0x99800000;
// bit 24-31
imm32 r0, 0x44444444;
imm32 r1, 0x44444444;
imm32 r2, 0x44444444;
imm32 r3, 0x44444444;
imm32 r4, 0x44444444;
imm32 r5, 0x44444444;
imm32 r6, 0x44444444;
imm32 r7, 0x44444444;
R0 <<= 24;
R1 <<= 25;
R2 <<= 26;
R3 <<= 27;
R4 <<= 28;
R5 <<= 29;
R6 <<= 30;
R7 <<= 31;
CHECKREG r0, 0x44000000;
CHECKREG r1, 0x88000000;
CHECKREG r2, 0x10000000;
CHECKREG r3, 0x20000000;
CHECKREG r4, 0x40000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 1,135
|
sim/testsuite/bfin/c_dsp32alu_abs.s
|
//Original:/testcases/core/c_dsp32alu_abs/c_dsp32alu_abs.dsp
// Spec Reference: dsp32alu dregs = abs ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0 = ABS R0;
R1 = ABS R1;
R2 = ABS R2;
R3 = ABS R3;
R4 = ABS R4;
R5 = ABS R5;
R6 = ABS R6;
R7 = ABS R7;
CHECKREG r0, 0x15678911;
CHECKREG r1, 0x2789AB1D;
CHECKREG r2, 0x34445515;
CHECKREG r3, 0x46667717;
CHECKREG r4, 0x5567891B;
CHECKREG r5, 0x6789AB1D;
CHECKREG r6, 0x74445515;
CHECKREG r7, 0x79998889;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = ABS R7;
R1 = ABS R6;
R2 = ABS R5;
R3 = ABS R4;
R4 = ABS R3;
R5 = ABS R2;
R6 = ABS R1;
R7 = ABS R0;
CHECKREG r0, 0x0EEEFFFF;
CHECKREG r1, 0x033322D3;
CHECKREG r2, 0x155544D5;
CHECKREG r3, 0x277766D7;
CHECKREG r4, 0x277766D7;
CHECKREG r5, 0x155544D5;
CHECKREG r6, 0x033322D3;
CHECKREG r7, 0x0EEEFFFF;
pass
|
stsp/binutils-ia16
| 6,260
|
sim/testsuite/bfin/c_dspldst_st_drlo_ipp.s
|
//Original:testcases/core/c_dspldst_st_drlo_ipp/c_dspldst_st_drlo_ipp.dsp
// Spec Reference: c_dspldst st_drlo_ipp
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// Half reg 16 bit mem store
imm32 r0, 0x0a123456;
imm32 r1, 0x11b12345;
imm32 r2, 0x222c1234;
imm32 r3, 0x3344d012;
imm32 r4, 0x5566e012;
imm32 r5, 0x789abf01;
imm32 r6, 0xabcd0123;
imm32 r7, 0x01234567;
// initial values
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
W [ I0 ++ ] = R0.L;
W [ I1 ++ ] = R1.L;
W [ I2 ++ ] = R2.L;
W [ I3 ++ ] = R3.L;
W [ I0 ++ ] = R1.L;
W [ I1 ++ ] = R2.L;
W [ I2 ++ ] = R3.L;
W [ I3 ++ ] = R4.L;
W [ I0 ++ ] = R3.L;
W [ I1 ++ ] = R4.L;
W [ I2 ++ ] = R5.L;
W [ I3 ++ ] = R6.L;
W [ I0 ++ ] = R4.L;
W [ I1 ++ ] = R5.L;
W [ I2 ++ ] = R6.L;
W [ I3 ++ ] = R7.L;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 = [ I2 ++ ];
R3 = [ I3 ++ ];
R4 = [ I0 ++ ];
R5 = [ I1 ++ ];
R6 = [ I2 ++ ];
R7 = [ I3 ++ ];
CHECKREG r0, 0x23453456;
CHECKREG r1, 0x12342345;
CHECKREG r2, 0xD0121234;
CHECKREG r3, 0xE012D012;
CHECKREG r4, 0xE012D012;
CHECKREG r5, 0xBF01E012;
CHECKREG r6, 0x0123BF01;
CHECKREG r7, 0x45670123;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 = [ I2 ++ ];
R3 = [ I3 ++ ];
R4 = [ I0 ++ ];
R5 = [ I1 ++ ];
R6 = [ I2 ++ ];
R7 = [ I3 ++ ];
CHECKREG r0, 0x08090A0B;
CHECKREG r1, 0x28292A2B;
CHECKREG r2, 0x48494A4B;
CHECKREG r3, 0x68696A6B;
CHECKREG r4, 0x0C0D0E0F;
CHECKREG r5, 0x2C2D2E2F;
CHECKREG r6, 0x4C4D4E4F;
CHECKREG r7, 0x6C6D6E6F;
// initial values
imm32 r0, 0x01b2c3d4;
imm32 r1, 0x10145618;
imm32 r2, 0xa2016729;
imm32 r3, 0xbb30183a;
imm32 r4, 0xdec4014b;
imm32 r5, 0x5f7d501c;
imm32 r6, 0x3089eb01;
imm32 r7, 0x719abf70;
loadsym i0, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym i2, DATA_ADDR_5, 0x20;
loadsym i3, DATA_ADDR_6, 0x20;
W [ I0 -- ] = R0.L;
W [ I1 -- ] = R1.L;
W [ I2 -- ] = R2.L;
W [ I3 -- ] = R3.L;
W [ I0 -- ] = R1.L;
W [ I1 -- ] = R2.L;
W [ I2 -- ] = R3.L;
W [ I3 -- ] = R4.L;
W [ I0 -- ] = R3.L;
W [ I1 -- ] = R4.L;
W [ I2 -- ] = R5.L;
W [ I3 -- ] = R6.L;
W [ I0 -- ] = R4.L;
W [ I1 -- ] = R5.L;
W [ I2 -- ] = R6.L;
W [ I3 -- ] = R7.L;
loadsym i0, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym i2, DATA_ADDR_5, 0x20;
loadsym i3, DATA_ADDR_6, 0x20;
R0 = [ I0 -- ];
R1 = [ I1 -- ];
R2 = [ I2 -- ];
R3 = [ I3 -- ];
R4 = [ I0 -- ];
R5 = [ I1 -- ];
R6 = [ I2 -- ];
R7 = [ I3 -- ];
CHECKREG r0, 0x0000C3D4;
CHECKREG r1, 0x00005618;
CHECKREG r2, 0x00006729;
CHECKREG r3, 0x0000183A;
CHECKREG r4, 0x5618183A;
CHECKREG r5, 0x6729014B;
CHECKREG r6, 0x183A501C;
CHECKREG r7, 0x014BEB01;
R0 = [ I0 -- ];
R1 = [ I1 -- ];
R2 = [ I2 -- ];
R3 = [ I3 -- ];
R4 = [ I0 -- ];
R5 = [ I1 -- ];
R6 = [ I2 -- ];
R7 = [ I3 -- ];
CHECKREG r0, 0x014B1A1B;
CHECKREG r1, 0x501C3A3B;
CHECKREG r2, 0xEB015A5B;
CHECKREG r3, 0xBF707A7B;
CHECKREG r4, 0x14151617;
CHECKREG r5, 0x34353637;
CHECKREG r6, 0x54555657;
CHECKREG r7, 0x74757677;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
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