repo_id
stringlengths 5
115
| size
int64 590
5.01M
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|---|---|---|---|
afska/beat-beast
| 2,482
|
butano/hw/src/bn_hw_bg_blocks.s
|
/*
* Copyright (c) 2020-2023 Gustavo Valiente gustavo.valiente@protonmail.com
* zlib License, see LICENSE file.
*/
/*
void bn_hw_bg_blocks_commit_half_words(
const uint16_t* source_data_ptr, unsigned half_words, uint16_t offset, uint16_t* destination_vram_ptr)
{
for(unsigned index = 0; index < half_words; ++index)
{
destination_vram_ptr[index] = source_data_ptr[index] + offset;
}
}
*/
.section .iwram, "ax", %progbits
.align 2
.arm
.global bn_hw_bg_blocks_commit_half_words
.type bn_hw_bg_blocks_commit_half_words, STT_FUNC
bn_hw_bg_blocks_commit_half_words:
.half_words_loop:
ldrh r12, [r0], #2
add r12, r2, r12
strh r12, [r3], #2
subs r1, #1
bne .half_words_loop
bx lr
/*
void bn_hw_bg_blocks_commit_words(
const unsigned* source_data_ptr, unsigned words, unsigned word_offset, unsigned* destination_vram_ptr)
{
for(unsigned index = 0; index < words; ++index)
{
destination_vram_ptr[index] = source_data_ptr[index] + word_offset;
}
}
*/
.section .iwram, "ax", %progbits
.align 2
.arm
.global bn_hw_bg_blocks_commit_words
.type bn_hw_bg_blocks_commit_words, STT_FUNC
bn_hw_bg_blocks_commit_words:
.words_loop:
ldr r12, [r0], #4
add r12, r2, r12
str r12, [r3], #4
subs r1, #1
bne .words_loop
bx lr
/*
void bn_hw_bg_blocks_commit_blocks(
const unsigned* source_data_ptr, unsigned blocks, unsigned word_offset, unsigned* destination_vram_ptr)
{
while(blocks)
{
for(int index = 0; index < 8; ++index)
{
*destination_vram_ptr = *source_data_ptr + word_offset;
++source_data_ptr;
++destination_vram_ptr;
}
--blocks;
}
}
*/
.section .iwram, "ax", %progbits
.align 2
.arm
.global bn_hw_bg_blocks_commit_blocks
.type bn_hw_bg_blocks_commit_blocks, STT_FUNC
bn_hw_bg_blocks_commit_blocks:
push {r4-r10}
.blocks_loop:
ldmia r0!, {r4-r10, r12}
add r4, r4, r2
add r5, r5, r2
add r6, r6, r2
add r7, r7, r2
add r8, r8, r2
add r9, r9, r2
add r10, r10, r2
add r12, r12, r2
stmia r3!, {r4-r10, r12}
subs r1, #1
bne .blocks_loop
pop {r4-r10}
bx lr
|
afska/beat-beast
| 1,152
|
butano/hw/src/bn_hw_palettes_asm.s
|
/*
* Copyright (c) 2020-2023 Gustavo Valiente gustavo.valiente@protonmail.com
* zlib License, see LICENSE file.
*/
/*
unsigned bn_hw_palettes_different_words(
unsigned four_words_count, const unsigned* color_words, const unsigned* stored_color_words)
{
while(four_words_count)
{
for(int index = 0; index < 4; ++index)
{
if(*color_words != *stored_color_words) [[unlikely]]
{
return four_words_count;
}
++color_words;
++stored_color_words;
}
--four_words_count;
}
return four_words_count;
}
*/
.section .iwram, "ax", %progbits
.align 2
.arm
.global bn_hw_palettes_different_words
.type bn_hw_palettes_different_words, STT_FUNC
bn_hw_palettes_different_words:
push {r4-r9}
.loop:
ldmia r1!, {r3-r6}
ldmia r2!, {r7-r9, r12}
cmp r3, r7
cmpeq r4, r8
cmpeq r5, r9
cmpeq r6, r12
bne .exit
subs r0, #1
bne .loop
.exit:
pop {r4-r9}
bx lr
|
afska/beat-beast
| 2,992
|
butano/hw/src/bn_hw_hblank_effects.s
|
@
@ Copyright (c) 2021 João Baptista de Paula e Silva jbaptistapsilva@yahoo.com.br
@ zlib License, see LICENSE file.
@
#include "../../include/bn_config_hbes.h"
#define SIZEOF_ENTRY 8
@ bn::hw::hblank_effects::_intr()
.section .iwram, "ax", %progbits
.align 2
.arm
.global _ZN2bn2hw14hblank_effects5_intrEv
.type _ZN2bn2hw14hblank_effects5_intrEv STT_FUNC
_ZN2bn2hw14hblank_effects5_intrEv: @ That's the mangled name of bn::hw::hblank_effects::_intr()
mov r0, #0x4000000 @ build REG_VCOUNT
ldrh r0, [r0, #6] @ load REG_VCOUNT into r0
@ this implement if (vcount < 159) vcount++; else if (vcount > 226) vcount = 0; else return;
cmp r0, #226 @ if it's > 226, set it to -1
movhi r0, #-1 @ now vcount = -1 or original vcount
add r0, r0, #1 @ add 1 to it (r0 = vcount+1 or 0)
cmp r0, #160 @ if vcount + 1 >= 160
bxhs lr @ bail out
mov r0, r0, lsl #1 @ now r0 = vcount*2
@ bn::hw::hblank_effects::data, which is below
ldr r3, _ZN2bn2hw14hblank_effects4dataE @ load data (entries*)
ldr r2, [r3], #4 @ load the 16-bit entries count
add r3, r3, r2, lsl #3 @ offset the register
adr r1, .dataTransferEnd16 @ pick up the label address
add r2, r2, r2, lsl #1 @ multiply the count by 3
sub pc, r1, r2, lsl #2 @ and set pc = label - count*12
@ generate the instruction copying
.rept BN_CFG_HBES_MAX_ITEMS
ldmdb r3!, {r1, r2} @ r1 = src (const uint16_t*), r2 = dest (volatile uint16_t*)
ldrh r1, [r1, r0] @ r1 = src[vcount]
strh r1, [r2] @ *dest = r1
.endr
.dataTransferEnd16:
@ now for the 32-bit data
add r3, r3, #(BN_CFG_HBES_MAX_ITEMS*SIZEOF_ENTRY) @ offset the pointer
ldr r2, [r3], #4 @ load the 32-bit count
add r3, r3, r2, lsl #3 @ offset the register
adr r1, .dataTransferEnd32 @ pick up the address
add r2, r2, r2, lsl #1 @ multiply the count by 3
sub pc, r1, r2, lsl #2 @ and set pc = label - count*12
.rept 4
ldmdb r3!, {r1, r2} @ r1 = src (const uint32_t*), r2 = dest (volatile uint32_t*)
ldr r1, [r1, r0, lsl #1] @ r1 = src[vcount] (r0 = vcount*2, r0, lsl #1 = vcount*4)
str r1, [r2] @ *dest = r1
.endr
.dataTransferEnd32:
bx lr @ we are done here, but tbh I really need to test this routine
.global _ZN2bn2hw14hblank_effects4dataE
_ZN2bn2hw14hblank_effects4dataE: @ entries* bn::hw::hblank_effects::data
.word 0
|
afska/beat-beast
| 2,308
|
butano/hw/3rd_party/cult-of-gba-bios/src/huffman.s
|
.section .iwram, "ax", %progbits
.align 2
.arm
.global swi_HuffUnCompReadNormal
.type swi_HuffUnCompReadNormal STT_FUNC
swi_HuffUnCompReadNormal:
stmfd sp!, { r2-r11 }
ldr r3, [r0], #4 @ src_len << 8
@ check for invalid decompression parameters (slightly different from others)
movs r2, r3, lsr #8
movnes r2, r0, lsr #25 @ == 0 if and only if src_addr < 0x02000000
beq .huff_uncomp_return
and r2, r3, #0xf @ data_size
lsr r3, #8 @ decomp_len
ldrb r4, [r0], #1 @ (tree_length / 2) - 1; r0 now contains tree_ptr
add r4, r0, r4, lsl #1 @ data_stream_ptr
add r4, #1
mov r5, #0 @ buffer
mov r6, #0 @ unit_counter; instead of adding 1 and comparing to units_per_word, we just add data_size and compare to 32
mov r7, r0 @ working copy of tree_ptr (current address)
.huff_uncomp_word_loop:
mov r8, #32 @ bit counter
ldr r9, [r4], #4 @ data
.huff_uncomp_node_loop:
subs r8, #1
blt .huff_uncomp_word_loop
ldrb r10, [r7] @ node
and r11, r10, #0x3f
add r11, #1 @ next_node_offset
bic r7, #1
lsls r9, #1 @ data_bit in carry flag
adc r7, r11, lsl #1 @ next_node_ptr
lslcs r10, #1 @ node_shifted
tst r10, #0x80
beq .huff_uncomp_node_loop @ we did not change src_len here, so we don't need to check it
@ next node is data
ldrb r7, [r7] @ we have to reset r7 (node_ptr) to tree_ptr after this anyway
orr r5, r7, lsl r6 @ buffer |= next_node << unit_counter
mov r7, r0
add r6, r2 @ unit_counter += data_size
ands r6, #31 @ the original algorithm would go wrong if the unit_counter is 4 or 8 anyway
bne .huff_uncomp_node_loop
str r5, [r1], #4 @ store buffer
mov r5, #0
subs r3, #4 @ decomp_len -= 4
bgt .huff_uncomp_node_loop
.huff_uncomp_return:
ldmfd sp!, { r2-r11 }
bx lr
|
afska/beat-beast
| 4,762
|
butano/hw/3rd_party/cult-of-gba-bios/src/running_length.s
|
.section .iwram, "ax", %progbits
.align 2
.arm
.global swi_RLUnCompReadNormalWrite8bit
.type swi_RLUnCompReadNormalWrite8bit STT_FUNC
swi_RLUnCompReadNormalWrite8bit:
stmfd sp!, { r2-r4 }
ldr r2, [r0], #4
lsr r2, #8 @ decomp_len
@ check for invalid decompression parameters
@ check_invalid_decomp r2, r3, r0, .rl_uncomp_read_normal_write_8bit_return
.rl_uncomp_read_normal_write_8bit_check_skip: @ used in boot_screen
.rl_uncomp_read_normal_write_8bit_loop:
ldrb r3, [r0], #1
lsls r3, #0x19 @ carry flag = uncomp/comp flag
lsr r3, #0x19
bcc .rl_uncomp_read_normal_write_8bit_uncompressed
.rl_uncomp_read_normal_write_8bit_compressed:
ldrb r4, [r0], #1 @ data
add r3, #3 @ expand_length += 3
sub r2, r3 @ decomp_len -= expand_length
.rl_uncomp_read_normal_write_8bit_compressed_loop:
strb r4, [r1], #1
subs r3, #1
bgt .rl_uncomp_read_normal_write_8bit_compressed_loop
b .rl_uncomp_read_normal_write_8bit_loop_end
.rl_uncomp_read_normal_write_8bit_uncompressed:
add r3, #1 @ expand_length += 1
sub r2, r3 @ decomp_len -= expand_length
.rl_uncomp_read_normal_write_8bit_uncompressed_loop:
ldrb r4, [r0], #1
strb r4, [r1], #1
subs r3, #1
bgt .rl_uncomp_read_normal_write_8bit_uncompressed_loop
.rl_uncomp_read_normal_write_8bit_loop_end:
cmp r2, #0
bgt .rl_uncomp_read_normal_write_8bit_loop
.rl_uncomp_read_normal_write_8bit_return:
ldmfd sp!, { r2-r4 }
bx lr
.section .iwram, "ax", %progbits
.align 2
.arm
.global swi_RLUnCompReadNormalWrite16bit
.type swi_RLUnCompReadNormalWrite16bit STT_FUNC
swi_RLUnCompReadNormalWrite16bit:
@ basically the same thing as above, except we buffer the bytes and write them 2 at a time
@ in the original BIOS, any leftover byte (if the uncompressed length is not divisible by 2) is NOT written
stmfd sp!, { r2-r6 }
ldr r2, [r0], #4
lsr r2, #8 @ decomp_len
@ check for invalid decompression parameters
@ check_invalid_decomp r2, r3, r0, .rl_uncomp_read_normal_write_16bit_return
mov r5, #0 @ keep track of upper/lower byte
mov r6, #0 @ write buffer
.rl_uncomp_read_normal_write_16bit_loop:
ldrb r3, [r0], #1
lsls r3, #0x19 @ carry flag = uncomp/comp flag
lsr r3, #0x19
bcc .rl_uncomp_read_normal_write_16bit_uncompressed
.rl_uncomp_read_normal_write_16bit_compressed:
ldrb r4, [r0], #1 @ data
add r3, #3 @ expand_length += 3
sub r2, r3 @ decomp_len -= expand_length
.rl_uncomp_read_normal_write_16bit_compressed_loop:
subs r3, #1
blt .rl_uncomp_read_normal_write_16bit_loop_end
orr r6, r4, lsl r5
eors r5, #8
@ store only if it's an even byte we are checking
bne .rl_uncomp_read_normal_write_16bit_compressed_loop
strh r6, [r1], #2
mov r6, #0 @ clear buffer
b .rl_uncomp_read_normal_write_16bit_compressed_loop
.rl_uncomp_read_normal_write_16bit_uncompressed:
add r3, #1 @ expand_length += 1
sub r2, r3 @ decomp_len -= expand_length
.rl_uncomp_read_normal_write_16bit_uncompressed_loop:
subs r3, #1
blt .rl_uncomp_read_normal_write_16bit_loop_end
ldrb r4, [r0], #1
orr r6, r4, lsl r5
eors r5, #8
@ store only if it's an even byte we are checking
bne .rl_uncomp_read_normal_write_16bit_uncompressed_loop
strh r6, [r1], #2 @ last byte is not stored for misaligned decomp_len
mov r6, #0 @ clear buffer
b .rl_uncomp_read_normal_write_16bit_uncompressed_loop
.rl_uncomp_read_normal_write_16bit_loop_end:
cmp r2, #0
bgt .rl_uncomp_read_normal_write_16bit_loop
.rl_uncomp_read_normal_write_16bit_return:
ldmfd sp!, { r2-r6 }
bx lr
|
afska/beat-beast
| 7,120
|
butano/hw/3rd_party/cult-of-gba-bios/src/lz77.s
|
@-------------------------------------------------------------
@ Original code by fleroviux, distributed under the MIT License:
@ Link: https://github.com/Cult-of-GBA/BIOS
@ Copyright 2020 - 2021 DenSinH fleroviux
@ Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
@ The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
@ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@-------------------------------------------------------------
@ Speed optimizations by Lorenzooone - 2024
@ 8bit version not included because the optimized 16bit version is faster.
@ Works fine even with 1 as the window offset (fixes LZ77 VRAM bug).
@-------------------------------------------------------------
.arm
.align
.global swi_LZ77UnCompWrite16bit
.global swi_LZ77UnCompWrite8bit
.type swi_LZ77UnCompWrite16bit,function
.type swi_LZ77UnCompWrite8bit,function
#ifdef __NDS__
.section .itcm, "ax", %progbits
#else
.section .iwram, "ax", %progbits
#endif
@ALIGNMENT_FIX has an impact of around 0.25% on performance, but it prevents
@alignment warnings (which wouldn't affect real hardware).
#define ALIGNMENT_FIX
@OVERRUN_PROTECTION has an impact of around 0.9% on performance, but it
@prevents overrunning the buffer by up to 2 extra bytes if the compressed data
@has issues. Apparently, the regular BIOS functions lack any kind of overrun
@protection. So instead of potentially writing 2 extra bytes, they could
@write way more...
@#define OVERRUN_PROTECTION
@PREVENT_OOB_READS has an impact of around 2% on performance. It prevents
@the LZ77 window from going to an address before the initial destination one.
@Such LZ77 data is badly formed, and this shouldn't be enabled at all
@unless you don't trust the data coming in...
@#define PREVENT_OOB_READS
swi_LZ77UnCompWrite16bit:
swi_LZ77UnCompWrite8bit:
stmfd sp!, {r3 - r8}
@ Read header word:
@ bit0-3: reserved
@ bit4-7: compressed type (1 for LZ77)
@ bit8-31: size of compressed data
ldr r2, [r0], #4
lsrs r2, r2, #8
@ ignore zero-length decompression requests
beq .lz77_16bit_done
@ Cover un-aligned destination
tst r1, #1
ldrneb r7, [r1, #-1]
#ifdef PREVENT_OOB_READS
@ Store the initial address in r8
movs r8, r1
#endif
.lz77_16bit_loop:
@ read encoder byte, shift to MSB for easier access.
ldrb r3, [r0], #1
orr r3, #0x01000000
.lz77_16bit_encoder_loop:
tst r3, #0x80
bne .lz77_16bit_copy_window
.lz77_16bit_copy_byte:
@ copy byte from current source to current destination
ldrb r4, [r0], #1
tst r1, #1
moveq r7, r4
orrne r7, r4, lsl #8
strneh r7, [r1, #-1]
add r1, #1
@ check if decompressed length has been reached.
subs r2, #1
beq .lz77_16bit_done
@ read next encoder or process next block
lsls r3, #1
bcc .lz77_16bit_encoder_loop
@ read encoder byte, shift to MSB for easier access.
ldrb r3, [r0], #1
orr r3, #0x01000000
tst r3, #0x80
beq .lz77_16bit_copy_byte
.lz77_16bit_copy_window:
@ read window tuple {displacement, size}
ldrb r4, [r0], #1
ldrb r5, [r0], #1
@ r5 = window displacement
orr r5, r5, r4, lsl #8
bic r5, #0xF000
add r5, #1
@ r4 = window size
lsr r4, #4
add r4, #3
cmp r4, r2
movgt r4, r2
subs r2, r4
subs r5, r1, r5
#ifdef PREVENT_OOB_READS
subs r6, r5, r8
cmp r6, #0
blt .lz77_16bit_done
#endif
@ About 50% of the time, the two addresses will be aligned. Abuse this...
eor r6, r1, r5
tst r6, #1
bne .lz77_16bit_copy_window_not_aligned_check
tst r1, #1
beq .lz77_optimized_16bit_copy_window_pre_loop
ldrb r6, [r5], #1
orr r7, r6, lsl #8
#ifdef ALIGNMENT_FIX
subs r1, #1
strh r7, [r1], #2
#else
strh r7, [r1], #1
#endif
subs r4, #1
.lz77_optimized_16bit_copy_window_pre_loop:
#ifdef OVERRUN_PROTECTION
cmp r4, #1
ble .lz77_optimized_16bit_copy_window_after_loop
#endif
.lz77_optimized_16bit_copy_window_loop:
ldrh r6, [r5], #2
strh r6, [r1], #2
subs r4, #2
cmp r4, #1
bgt .lz77_optimized_16bit_copy_window_loop
.lz77_optimized_16bit_copy_window_after_loop:
@ copy byte from window to current destination
ldreqb r7, [r5]
addeq r1, #1
@ check if decompressed length has been reached
cmp r2, #0
beq .lz77_16bit_done
@ read next encoder or process next block
lsls r3, #1
bcc .lz77_16bit_encoder_loop
b .lz77_16bit_loop
.lz77_16bit_copy_window_not_aligned_check:
subs r1, #1
cmp r1, r5
beq .set_previous_byte
tst r5, #1
ldrneb r7, [r5], #1
addne r1, #1
subne r4, #1
#ifdef OVERRUN_PROTECTION
cmp r4, #1
ble .lz77_16bit_copy_window_not_aligned_after_loop
#endif
.lz77_16bit_copy_window_not_aligned_loop:
ldrh r6, [r5], #2
orr r7, r6, lsl #8
strh r7, [r1], #2
lsr r7, #16
subs r4, #2
cmp r4, #1
bgt .lz77_16bit_copy_window_not_aligned_loop
.lz77_16bit_copy_window_not_aligned_after_loop:
@ copy byte from window to current destination
ldreqb r6, [r5]
orreq r7, r6, lsl #8
streqh r7, [r1], #1
add r1, #1
@ check if decompressed length has been reached
cmp r2, #0
beq .lz77_16bit_done
@ read next encoder or process next block
lsls r3, #1
bcc .lz77_16bit_encoder_loop
b .lz77_16bit_loop
.set_previous_byte:
tst r1, #1
beq .got_byte_in_r7
ldrb r7, [r1], #1
movs r6, r7
orr r7, r6, lsl #8
b .pre_set_loop
.got_byte_in_r7:
movs r6, r7
orr r7, r6, lsl #8
strh r7, [r1], #2
subs r4, #1
.pre_set_loop:
#ifdef OVERRUN_PROTECTION
cmp r4, #1
ble .set_after_loop
#endif
.set_loop:
strh r7, [r1], #2
subs r4, #2
cmp r4, #1
bgt .set_loop
.set_after_loop:
@ copy byte from window to current destination
lsreq r7, #8
addeq r1, #1
@ check if decompressed length has been reached
cmp r2, #0
beq .lz77_16bit_done
@ read next encoder or process next block
lsls r3, #1
bcc .lz77_16bit_encoder_loop
b .lz77_16bit_loop
.lz77_16bit_done:
@ Cover un-aligned end
tst r1, #1
ldrneb r6, [r1]
orrne r7, r6, lsl #8
strneh r7, [r1, #-1]
ldmfd sp!, {r3 - r8}
bx lr
|
afska/beat-beast
| 2,014
|
butano/hw/3rd_party/libtonc/asm/clr_blend_fast.s
|
//
// Color blend with 33 alpha levels
//
//! \file tonc_memcpy.s
//! \author J Vijn
//! \date 20071130 - 20090801
#include "../include/tonc_asminc.h"
#ifndef CLR_ROUND
#define CLR_ROUND 1
#endif
/*
void clr_blend_fast(COLOR *srca, COLOR *srcb, COLOR *dst,
int nclrs, u32 alpha) IWRAM_CODE;
*/
//! Blends color arrays \a srca and \a srcb into \a dst.
/*! \param srca Source array A.
\param srcb Source array B
\param dst Destination array.
\param nclrs Number of colors.
\param alpha Blend weight (range: 0-32).
\note u32 version, 2 clrs/loop. Loop: 18i/32c, Barrel shifter FTW.
\note Properly rounds the blending. If you don't want that, remove
the references to lr.
*/
BEGIN_FUNC_ARM(clr_blend_fast, CSEC_IWRAM)
movs r3, r3, lsr #1 @ adjust nclrs for u32 run
bxeq lr @ quit on nclrs=0
ldr r12, [sp] @ get alpha from stack
stmfd sp!, {r4-r10, lr}
#if(CLR_ROUND==1)
ldr lr, =0x00200401 @ -1-|1-1
rsb r7, lr, lr, lsl #5 @ MASKLO: -g-|b-r
#else
ldr r7, =0x03E07C1F @ MASKLO: -g-|b-r
#endif
mov r6, r7, lsl #5 @ MASKHI: g-|b-r-
.Lbld_fast_loop:
ldr r8, [r0], #4 @ a= *pa++
ldr r9, [r1], #4 @ b= *pb++
@ --- -g-|b-r
and r4, r6, r8, lsl #5 @ x/32: (-g-|b-r)
and r5, r7, r9 @ y: -g-|b-r
sub r5, r5, r4, lsr #5 @ z: y-x
mla r4, r5, r12, r4 @ z: (y-x)*w + x*32
#if(CLR_ROUND==1)
add r4, r4, lr, lsl #4 @ round
#endif
and r10, r7, r4, lsr #5 @ blend(-g-|b-r)
@ --- b-r|-g- (rotated by 16 for great awesome)
and r4, r6, r8, ror #11 @ x/32: -g-|b-r (ror16)
and r5, r7, r9, ror #16 @ y: -g-|b-r (ror16)
sub r5, r5, r4, lsr #5 @ z: y-x
mla r4, r5, r12, r4 @ z: (y-x)*w + x*32
#if(CLR_ROUND==1)
add r4, r4, lr, lsl #4 @ round
#endif
and r4, r7, r4, lsr #5 @ blend(-g-|b-r (ror16))
@ --- mix -g-|b-r and b-r|-g-
orr r10, r10, r4, ror #16
@ --- write blended, loop
str r10, [r2], #4 @ *dst++= c
subs r3, r3, #1
bgt .Lbld_fast_loop
ldmfd sp!, {r4-r10, lr}
bx lr
END_FUNC(clr_blend_fast)
@ EOF
|
afska/beat-beast
| 1,980
|
butano/hw/3rd_party/libtonc/asm/clr_fade_fast.s
|
//
// Color fade with 33 alpha levels
//
//! \file tonc_memcpy.s
//! \author J Vijn
//! \date 20071130 - 20071130
#include "../include/tonc_asminc.h"
#ifndef CLR_ROUND
#define CLR_ROUND 1
#endif
/*
void clr_fade_fast(COLOR *src, COLOR clr, COLOR *dst,
int nclrs, u32 alpha) IWRAM_CODE;
*/
//! Fades color arrays \a srca to \a clr into \a dst.
/*! \param src Source array.
* \param clr Final color (at alpha=32).
* \param dst Destination array.
* \param nclrs Number of colors.
* \param alpha Blend weight (range: 0-32).
* \note u32 version, 2 clrs/loop. Loop: 18i/32c, Barrel shifter FTW.
*/
.section .iwram,"ax", %progbits
.align 2
.arm
.global clr_fade_fast
clr_fade_fast:
movs r3, r3, lsr #1 @ adjust nclrs for u32 run
bxeq lr @ quit on nclrs=0
ldr r12, [sp] @ get alpha from stack
stmfd sp!, {r4-r10, lr}
#if(CLR_ROUND==1)
ldr lr, =0x00200401 @ -1-|1-1
rsb r7, lr, lr, lsl #5 @ MASKLO: -g-|b-r
#else
ldr r7, =0x03E07C1F @ MASKLO: -g-|b-r
#endif
mov r6, r7, lsl #5 @ MASKHI: g-|b-r-
@ Precalc y1 and y2
orr r1, r1, r1, lsl #16
and r9, r7, r1, ror #16 @ precalc: y2= -g-|b-r (ror16)
and r1, r7, r1 @ precalc: y1= -g-|b-r
.Lfade_fast_loop:
ldr r8, [r0], #4 @ a= *pa++
@ --- -g-|b-r
and r4, r6, r8, lsl #5 @ x/32: (-g-|b-r)
sub r5, r1, r4, lsr #5 @ z: y1-x
mla r4, r5, r12, r4 @ z: (y1-x)*w + x*32
#if(CLR_ROUND==1)
add r4, r4, lr, lsl #4 @ round
#endif
and r10, r7, r4, lsr #5 @ blend(-g-|b-r)
@ --- b-r|-g- (rotated by 16 for great awesome)
and r4, r6, r8, ror #11 @ x/32: -g-|b-r (ror16)
sub r5, r9, r4, lsr #5 @ z: y2-x
mla r4, r5, r12, r4 @ z: (y2-x)*w + x*32
#if(CLR_ROUND==1)
add r4, r4, lr, lsl #4 @ round
#endif
and r4, r7, r4, lsr #5 @ blend(-g-|b-r (ror16))
@ --- mix -g-|b-r and b-r|-g-
orr r10, r10, r4, ror #16
@ --- write faded, loop
str r10, [r2], #4 @ *dst++= c
subs r3, r3, #1
bgt .Lfade_fast_loop
ldmfd sp!, {r4-r10, lr}
bx lr
@ EOF
|
afska/beat-beast
| 1,401
|
butano/hw/3rd_party/libtonc/asm/tonc_nocash.s
|
//
// No$gba debugger messaging
//
//! \file tonc_nocash.s
//! \author J Vijn
//! \date 20080422 - 20080422
#include "../include/tonc_asminc.h"
/* DECLARATIONS:
int nocash_puts(const char *str);
EWRAM_CODE void nocash_message();
extern EWRAM_DATA char nocash_buffer[80];
*/
.global nocash_puts
.global nocash_message
.global nocash_buffer
BEGIN_FUNC_THUMB(nocash_puts, CSEC_TEXT)
push {r4, lr}
ldr r4,=nocash_message @ Get messenger address
ldr r1,=nocash_buffer @ Get buffer address
mov r2, #0
mov r12, r2
@ Iterate over loop parts
.Lmsg_loop:
mov r2, #0
@ Copy up to 80 chars and print
.Lmsg_cpy: @ for(ii=0; ii<80; ii++)
ldrb r3, [r0, r2] @ if((dst[ii]=src[ii]) == '\0')
strb r3, [r1, r2] @ break;
cmp r3, #0
beq .Lmsg_print
add r2, #1
cmp r2, #80
bne .Lmsg_cpy
@ Print message
.Lmsg_print:
bl .Lmsg_far_call
@ If not at end, continue with next part of string
add r0, r2
add r12, r2
cmp r3, #0
bne .Lmsg_loop
@ Full string done. Set result and return
mov r0, r12
pop {r4}
pop {r1}
bx r1
.Lmsg_far_call:
bx r4
END_FUNC(nocash_puts)
BEGIN_FUNC_THUMB(nocash_message, CSEC_EWRAM)
mov r12, r12 @ first ID
b .Lmsg_end @ skip the text section
.hword 0x6464 @ second ID
.hword 0 @ flags
nocash_buffer:
.space 82 @ Message buffer
.Lmsg_end:
bx lr
END_FUNC(nocash_message)
@ EOF
|
afska/beat-beast
| 7,509
|
butano/hw/3rd_party/libtonc/asm/tonc_bios.s
|
//
// Main GBA BIOS functions.
//
//! \file tonc_bios.s
//! \author J Vijn
//! \date 20071130 - 20090801
#include "../include/tonc_asminc.h"
@ === SoftReset [00h] =================================================
@ DECL: void SoftReset();
@ DESC:
BEGIN_FUNC_THUMB(SoftReset, CSEC_TEXT)
swi 0x00
bx lr
END_FUNC(SoftReset)
@ === RegisterRamReset [01h] ==========================================
@ DECL: void RegisterRamReset(u32 flags);
@ DESC:
BEGIN_FUNC_THUMB(RegisterRamReset, CSEC_TEXT)
swi 0x01
bx lr
END_FUNC(RegisterRamReset)
@ === Halt [02h] ======================================================
@ DECL: void Halt();
@ DESC:
BEGIN_FUNC_THUMB(Halt, CSEC_TEXT)
swi 0x02
bx lr
END_FUNC(Halt)
@ === Stop [03h] ======================================================
@ DECL: void Stop();
@ DESC:
BEGIN_FUNC_THUMB(Stop, CSEC_TEXT)
swi 0x03
bx lr
END_FUNC(Stop)
@ === IntrWait [04h] ==================================================
@ DECL: void IntrWait(u32 flagClear, u32 irq);
@ DESC:
BEGIN_FUNC_THUMB(IntrWait, CSEC_TEXT)
swi 0x04
bx lr
END_FUNC(IntrWait)
@ === VBlankIntrWait [05h] ============================================
@ DECL: void VBlankIntrWait();
@ DESC:
BEGIN_FUNC_THUMB(VBlankIntrWait, CSEC_TEXT)
swi 0x05
bx lr
END_FUNC(VBlankIntrWait)
@ === Div [06h] =======================================================
@ DECL: s32 Div(s32 num, s32 den);
@ DESC:
BEGIN_FUNC_THUMB(Div, CSEC_TEXT)
swi 0x06
bx lr
END_FUNC(Div)
@ === DivArm [07h] ====================================================
@ DECL: s32 DivArm(s32 den, s32 num);
@ DESC:
BEGIN_FUNC_THUMB(DivArm, CSEC_TEXT)
swi 0x07
bx lr
END_FUNC(DivArm)
@ === Sqrt [08h] ======================================================
@ DECL: u32 Sqrt(u32 num);
@ DESC:
BEGIN_FUNC_THUMB(Sqrt, CSEC_TEXT)
swi 0x08
bx lr
END_FUNC(Sqrt)
@ === ArcTan [09h] ====================================================
@ DECL: s16 ArcTan(s16 dydx);
@ DESC:
BEGIN_FUNC_THUMB(ArcTan, CSEC_TEXT)
swi 0x09
bx lr
END_FUNC(ArcTan)
@ === ArcTan2 [0Ah] ===================================================
@ DECL: s16 ArcTan2(s16 x, s16 y);
@ DESC:
BEGIN_FUNC_THUMB(ArcTan2, CSEC_TEXT)
swi 0x0A
bx lr
END_FUNC(ArcTan2)
@ === CpuSet [0Bh] ====================================================
@ DECL: void CpuSet(const void *src, void *dst, u32 mode);
@ DESC:
BEGIN_FUNC_THUMB(CpuSet, CSEC_TEXT)
swi 0x0B
bx lr
END_FUNC(CpuSet)
@ === CpuFastSet [0Ch] ================================================
@ DECL: void CpuFastSet(const void *src, void *dst, u32 mode);
@ DESC:
BEGIN_FUNC_THUMB(CpuFastSet, CSEC_TEXT)
swi 0x0C
bx lr
END_FUNC(CpuFastSet)
@ === BiosCheckSum [0Dh] ================================================
@ DECL: u32 BiosCheckSum();
@ DESC:
BEGIN_FUNC_THUMB(BiosCheckSum, CSEC_TEXT)
swi 0x0D
bx lr
END_FUNC(BiosCheckSum)
@ === BgAffineSet [0Eh] ===============================================
@ DECL: void ObjAffineSet(const ObjAffineSource *src, void *dst, s32 num, s32 offset);
@ DESC:
BEGIN_FUNC_THUMB(BgAffineSet, CSEC_TEXT)
swi 0x0E
bx lr
END_FUNC(BgAffineSet)
@ === ObjAffineSet [0Fh] ==============================================
@ DECL: void BgAffineSet(const BGAffineSource *src, BGAffineDest *dst, s32 num);
@ DESC:
BEGIN_FUNC_THUMB(ObjAffineSet, CSEC_TEXT)
swi 0x0F
bx lr
END_FUNC(ObjAffineSet)
@ === BitUnPack [10h] =================================================
@ DECL: void BitUnPack(const void *src, void *dst, BUP *bup);
@ DESC:
BEGIN_FUNC_THUMB(BitUnPack, CSEC_TEXT)
swi 0x10
bx lr
END_FUNC(BitUnPack)
@ === LZ77UnCompWram [11h] ============================================
@ DECL: void LZ77UnCompWram(const void *src, void *dst);
@ DESC:
BEGIN_FUNC_THUMB(LZ77UnCompWram, CSEC_TEXT)
swi 0x11
bx lr
END_FUNC(LZ77UnCompWram)
@ === LZ77UnCompVram [12h] ============================================
@ DECL: void LZ77UnCompVram(const void *src, void *dst);
@ DESC:
BEGIN_FUNC_THUMB(LZ77UnCompVram, CSEC_TEXT)
swi 0x12
bx lr
END_FUNC(LZ77UnCompVram)
@ === HuffUnComp [13h] ================================================
@ DECL: void HuffUnComp(const void *src, void *dst);
@ DESC:
BEGIN_FUNC_THUMB(HuffUnComp, CSEC_TEXT)
swi 0x13
bx lr
END_FUNC(HuffUnComp)
@ === RLUnCompWram [14h] ==============================================
@ DECL: void RLUnCompWram(const void *src, void *dst);
@ DESC:
BEGIN_FUNC_THUMB(RLUnCompWram, CSEC_TEXT)
swi 0x14
bx lr
END_FUNC(RLUnCompWram)
@ === RLUnCompVram [15h] ==============================================
@ DECL: void RLUnCompVram(const void *src, void *dst);
@ DESC:
BEGIN_FUNC_THUMB(RLUnCompVram, CSEC_TEXT)
swi 0x15
bx lr
END_FUNC(RLUnCompVram)
@ === Diff8bitUnFilterWram [16h] ======================================
@ DECL: void Diff8bitUnFilterWram(const void *src, void *dst);
@ DESC:
BEGIN_FUNC_THUMB(Diff8bitUnFilterWram, CSEC_TEXT)
swi 0x16
bx lr
END_FUNC(Diff8bitUnFilterWram)
@ === Diff8bitUnFilterVram [17h] ======================================
@ DECL: void Diff8bitUnFilterVram(const void *src, void *dst);
@ DESC:
BEGIN_FUNC_THUMB(Diff8bitUnFilterVram, CSEC_TEXT)
swi 0x17
bx lr
END_FUNC(Diff8bitUnFilterVram)
@ === Diff16bitUnFilter [18h] =========================================
@ DECL: void Diff16bitUnFilter(const void *src, void *dst);
@ DESC:
BEGIN_FUNC_THUMB(Diff16bitUnFilter, CSEC_TEXT)
swi 0x18
bx lr
END_FUNC(Diff16bitUnFilter)
@ === SoundBias [19h] =================================================
@ DECL: void SoundBias(u32 bias);
@ DESC:
BEGIN_FUNC_THUMB(SoundBias, CSEC_TEXT)
swi 0x19
bx lr
END_FUNC(SoundBias)
@ === SoundDriverInit [1Ah] ===========================================
@ DECL: void SoundDriverInit(void *src);
@ DESC:
BEGIN_FUNC_THUMB(SoundDriverInit, CSEC_TEXT)
swi 0x1A
bx lr
END_FUNC(SoundDriverInit)
@ === SoundDriverMode [1Bh] ===========================================
@ DECL: void SoundDriverMode(u32 mode);
@ DESC:
BEGIN_FUNC_THUMB(SoundDriverMode, CSEC_TEXT)
swi 0x1B
bx lr
END_FUNC(SoundDriverMode)
@ === SoundDriverMain [1Ch] ===========================================
@ DECL: void SoundDriverMain();
@ DESC:
BEGIN_FUNC_THUMB(SoundDriverMain, CSEC_TEXT)
swi 0x1C
bx lr
END_FUNC(SoundDriverMain)
@ === SoundDriverVSync [1Dh] ==========================================
@ DECL: void SoundDriverVSync();
@ DESC:
BEGIN_FUNC_THUMB(SoundDriverVSync, CSEC_TEXT)
swi 0x1D
bx lr
END_FUNC(SoundDriverVSync)
@ === SoundChannelClear [1Eh] =========================================
@ DECL: void SoundChannelClear();
@ DESC:
BEGIN_FUNC_THUMB(SoundChannelClear, CSEC_TEXT)
swi 0x1E
bx lr
END_FUNC(SoundChannelClear)
@ === MidiKey2Freq [1Fh] ==============================================
@ DECL: u32 MidiKey2Freq(void *wa, u8 mk, u8 fp);
@ DESC:
BEGIN_FUNC_THUMB(MidiKey2Freq, CSEC_TEXT)
swi 0x1F
bx lr
END_FUNC(MidiKey2Freq)
@ === MultiBoot [25h] =================================================
@ DECL: int MultiBoot(MultiBootParam* mb, u32 mode);
@ DESC:
BEGIN_FUNC_THUMB(MultiBoot, CSEC_TEXT)
swi 0x25
bx lr
END_FUNC(MultiBoot)
@ === SoundDriverVSyncOff [28h] =======================================
@ DECL: void SoundDriverVSyncOff();
@ DESC:
BEGIN_FUNC_THUMB(SoundDriverVSyncOff, CSEC_TEXT)
swi 0x28
bx lr
END_FUNC(SoundDriverVSyncOff)
@ === SoundDriverVSyncOn [29h] ========================================
@ DECL: void SoundDriverVSyncOn();
@ DESC:
BEGIN_FUNC_THUMB(SoundDriverVSyncOn, CSEC_TEXT)
swi 0x29
bx lr
END_FUNC(SoundDriverVSyncOn)
|
afska/beat-beast
| 3,115
|
butano/hw/3rd_party/libtonc/asm/tonc_memset.s
|
//
// Alignment-safe and fast memset routines
//
//! \file tonc_memcpy.s
//! \author J Vijn
//! \date 20060508 - 20090801
//
// === NOTES ===
@ * 20050924: Lower overhead for all; reduced i-count for u16 loops.
@ * These are 16/32bit memset and memcpy. The 32bit versions are in
@ iwram for maximum effect and pretty much do what CpuFastSet does,
@ except that it'll work for non multiples of 8 words too. Speed
@ is as good as CpuFastSet, but with a little less overhead.
@ * The 16bit versions call the 32bit ones if possible and/or desirable.
@ They are thumb/ROM functions but did them in asm anyway because
@ GCC goes haywire with the use of registers resulting in a much
@ higher overhead (i.e., detrimental for low counts)
@ * Crossover with inline while(nn--) loops (not for(ii++), which are
@ much slower):
@ memset32: ~5
@ memset16: ~8
.file "tonc_memset.s"
#include "../include/tonc_asminc.h"
@ === void memset32(void *dst, u32 src, u32 wdn); =====================
/*! \fn void memset32(void *dst, u32 src, u32 wdn) IWRAM_CODE;
\brief Fast-fill by words.
\param dst Destination address.
\param src Fill word (not address).
\param wdn Number of words to fill.
\note \a dst <b>must</b> be word aligned.
\note \a r0 returns as \a dst + \a wdn.
*/
/* Reglist:
r0, r1: dst, src
r2: wdn, then wdn>>3
r3-r10: data buffer
r12: wdn&7
*/
BEGIN_FUNC_ARM(memset32, CSEC_IWRAM)
and r12, r2, #7
movs r2, r2, lsr #3
beq .Lres_set32
push {r4-r9}
@ set 32byte chunks with 8fold xxmia
mov r3, r1
mov r4, r1
mov r5, r1
mov r6, r1
mov r7, r1
mov r8, r1
mov r9, r1
.Lmain_set32:
stmia r0!, {r1, r3-r9}
subs r2, r2, #1
bhi .Lmain_set32
pop {r4-r9}
@ residual 0-7 words
.Lres_set32:
subs r12, r12, #1
stmhsia r0!, {r1}
bhi .Lres_set32
bx lr
END_FUNC(memset32)
@ === void memset16(void *dst, u16 src, u32 hwn); =====================
/*! \fn void memset16(void *dst, u16 src, u32 hwn);
\brief Fill for halfwords.
Uses <code>memset32()</code> if \a hwn>5
\param dst Destination address.
\param src Source halfword (not address).
\param wdn Number of halfwords to fill.
\note \a dst <b>must</b> be halfword aligned.
\note \a r0 returns as \a dst + \a hwn.
*/
/* Reglist:
r0, r1: dst, src
r2, r4: wdn
r3: tmp; and data buffer
*/
BEGIN_FUNC_THUMB(memset16, CSEC_TEXT)
push {r4, lr}
@ under 6 hwords -> std set
cmp r2, #5
bls .Ltail_set16
@ dst not word aligned: copy 1 hword and align
lsl r3, r0, #31
bcc .Lmain_set16
strh r1, [r0]
add r0, #2
sub r2, r2, #1
@ Again, memset32 does the real work
.Lmain_set16:
lsl r4, r1, #16
orr r1, r4
lsl r4, r2, #31
lsr r2, r2, #1
ldr r3, =memset32
bl .Llong_bl
@ NOTE: r0 is altered by memset32, but in exactly the right
@ way, so we can use is as is. r1 is now doubled though.
lsr r2, r4, #31
beq .Lend_set16
lsr r1, #16
.Ltail_set16:
sub r2, #1
bcc .Lend_set16 @ r2 was 0, bug out
lsl r2, r2, #1
.Lres_set16:
strh r1, [r0, r2]
sub r2, r2, #2
bcs .Lres_set16
.Lend_set16:
pop {r4}
pop {r3}
.Llong_bl:
bx r3
END_FUNC(memset16)
@ EOF
|
afska/beat-beast
| 12,296
|
butano/hw/3rd_party/libtonc/src/font/verdana9.s
|
@{{BLOCK(verdana9)
@ Verdana 9, ' ' to '', 1bpp
.section .rodata
.align 2
.global verdana9Font
verdana9Font:
.word verdana9Glyphs, verdana9Widths, 0
.hword 32, 224
.byte 8, 12
.byte 8, 16
.hword 16
.byte 1, 0
.section .rodata
.align 2
.global verdana9Glyphs @ 3584 unsigned chars
verdana9Glyphs:
.word 0x00000000,0x00000000,0x00000000,0x00000000,0x01000000,0x01010101,0x00000100,0x00000000
.word 0x05050000,0x00000005,0x00000000,0x00000000,0x00000000,0x1F0A1F0A,0x0000000A,0x00000000
.word 0x04040000,0x0C06051E,0x04040F14,0x00000000,0x22000000,0x542A1515,0x00002254,0x00000000
.word 0x06000000,0x29260909,0x00002E11,0x00000000,0x01010000,0x00000001,0x00000000,0x00000000
.word 0x02040000,0x01010101,0x04020101,0x00000000,0x02010000,0x04040404,0x01020404,0x00000000
.word 0x0E150400,0x00000415,0x00000000,0x00000000,0x00000000,0x041F0404,0x00000004,0x00000000
.word 0x00000000,0x00000000,0x00010202,0x00000000,0x00000000,0x00070000,0x00000000,0x00000000
.word 0x00000000,0x00000000,0x00000202,0x00000000,0x08080000,0x02020404,0x00010102,0x00000000
.word 0x0E000000,0x11111111,0x00000E11,0x00000000,0x04000000,0x04040406,0x00000E04,0x00000000
.word 0x0E000000,0x04081011,0x00001F02,0x00000000,0x0E000000,0x100C1011,0x00000E11,0x00000000
.word 0x08000000,0x1F090A0C,0x00000808,0x00000000,0x1F000000,0x10100F01,0x00000E11,0x00000000
.word 0x0C000000,0x110F0102,0x00000E11,0x00000000,0x1F000000,0x04080810,0x00000404,0x00000000
.word 0x0E000000,0x110E1111,0x00000E11,0x00000000,0x0E000000,0x101E1111,0x00000608,0x00000000
.word 0x00000000,0x00020200,0x00000202,0x00000000,0x00000000,0x00020200,0x00010202,0x00000000
.word 0x00000000,0x0C030C10,0x00000010,0x00000000,0x00000000,0x1F001F00,0x00000000,0x00000000
.word 0x00000000,0x06180601,0x00000001,0x00000000,0x07000000,0x02040808,0x00000200,0x00000000
.word 0x7C000000,0xA5A5B982,0x007C0259,0x00000000,0x0C000000,0x3F12120C,0x00002121,0x00000000
.word 0x07000000,0x110F0909,0x00000F11,0x00000000,0x1C000000,0x01010122,0x00001C22,0x00000000
.word 0x0F000000,0x21212111,0x00000F11,0x00000000,0x1F000000,0x010F0101,0x00001F01,0x00000000
.word 0x1F000000,0x010F0101,0x00000101,0x00000000,0x1C000000,0x21390122,0x00001C22,0x00000000
.word 0x21000000,0x213F2121,0x00002121,0x00000000,0x07000000,0x02020202,0x00000702,0x00000000
.word 0x06000000,0x04040404,0x00000304,0x00000000,0x11000000,0x05030509,0x00001109,0x00000000
.word 0x01000000,0x01010101,0x00001F01,0x00000000,0x63000000,0x49555563,0x00004149,0x00000000
.word 0x21000000,0x31292523,0x00002121,0x00000000,0x1C000000,0x41414122,0x00001C22,0x00000000
.word 0x0F000000,0x0F111111,0x00000101,0x00000000,0x1C000000,0x41414122,0x60101C22,0x00000000
.word 0x0F000000,0x050F1111,0x00001109,0x00000000,0x0E000000,0x100E0111,0x00000E11,0x00000000
.word 0x7F000000,0x08080808,0x00000808,0x00000000,0x21000000,0x21212121,0x00001E21,0x00000000
.word 0x21000000,0x12122121,0x00000C0C,0x00000000,0x41000000,0x55554949,0x00002222,0x00000000
.word 0x11000000,0x0A040A11,0x00001111,0x00000000,0x11000000,0x040A0A11,0x00000404,0x00000000
.word 0x1F000000,0x02040810,0x00001F01,0x00000000,0x01030000,0x01010101,0x03010101,0x00000000
.word 0x01010000,0x04020202,0x00080804,0x00000000,0x02030000,0x02020202,0x03020202,0x00000000
.word 0x04000000,0x0000110A,0x00000000,0x00000000,0x00000000,0x00000000,0x1F000000,0x00000000
.word 0x04020000,0x00000000,0x00000000,0x00000000,0x00000000,0x0E080600,0x00000E09,0x00000000
.word 0x01010000,0x09090701,0x00000709,0x00000000,0x00000000,0x01010E00,0x00000E01,0x00000000
.word 0x08080000,0x09090E08,0x00000E09,0x00000000,0x00000000,0x0F090600,0x00000E01,0x00000000
.word 0x020C0000,0x02020702,0x00000202,0x00000000,0x00000000,0x09090E00,0x06080E09,0x00000000
.word 0x01010000,0x09090701,0x00000909,0x00000000,0x01000000,0x01010100,0x00000101,0x00000000
.word 0x04000000,0x04040600,0x03040404,0x00000000,0x01010000,0x03050901,0x00000905,0x00000000
.word 0x01010000,0x01010101,0x00000301,0x00000000,0x00000000,0x49493700,0x00004949,0x00000000
.word 0x00000000,0x09090700,0x00000909,0x00000000,0x00000000,0x09090600,0x00000609,0x00000000
.word 0x00000000,0x09090700,0x01010709,0x00000000,0x00000000,0x09090E00,0x08080E09,0x00000000
.word 0x00000000,0x01030500,0x00000101,0x00000000,0x00000000,0x06010E00,0x00000708,0x00000000
.word 0x00000000,0x02020F02,0x00000C02,0x00000000,0x00000000,0x09090900,0x00000E09,0x00000000
.word 0x00000000,0x09090900,0x00000606,0x00000000,0x00000000,0x15151100,0x00000A0A,0x00000000
.word 0x00000000,0x06090900,0x00000909,0x00000000,0x00000000,0x09090900,0x02020406,0x00000000
.word 0x00000000,0x02040700,0x00000701,0x00000000,0x04180000,0x03040404,0x18040404,0x00000000
.word 0x02020000,0x02020202,0x02020202,0x00000000,0x04030000,0x18040404,0x03040404,0x00000000
.word 0x00000000,0x0D160000,0x00000000,0x00000000,0x00000000,0x0F0F0F0F,0x00000F0F,0x00000000
.word 0x1C000000,0x0F020F02,0x00001C02,0x00000000,0x03000000,0x03030303,0x00000303,0x00000000
.word 0x00000000,0x00000000,0x00010202,0x00000000,0x30000000,0x041E0808,0x03040404,0x00000000
.word 0x00000000,0x00000000,0x00050A0A,0x00000000,0x00000000,0x00000000,0x00001500,0x00000000
.word 0x04040000,0x0404041F,0x00000004,0x00000000,0x04040000,0x041F041F,0x00000004,0x00000000
.word 0x05020000,0x00000000,0x00000000,0x00000000,0x15250200,0xA952040A,0x000050A8,0x00000000
.word 0x1C000814,0x201C0222,0x00001C22,0x00000000,0x00000000,0x02020400,0x00000004,0x00000000
.word 0xFE000000,0x11F11111,0x0000FE11,0x00000000,0x03000000,0x03030303,0x00000303,0x00000000
.word 0x1F00040A,0x02040810,0x00001F01,0x00000000,0x03000000,0x03030303,0x00000303,0x00000000
.word 0x03000000,0x03030303,0x00000303,0x00000000,0x01010000,0x00000002,0x00000000,0x00000000
.word 0x02020000,0x00000001,0x00000000,0x00000000,0x05050000,0x0000000A,0x00000000,0x00000000
.word 0x0A0A0000,0x00000005,0x00000000,0x00000000,0x00000000,0x07070700,0x00000000,0x00000000
.word 0x00000000,0x1F000000,0x00000000,0x00000000,0x00000000,0x7F000000,0x00000000,0x00000000
.word 0x0D0B0000,0x00000000,0x00000000,0x00000000,0x4F000000,0x00004A7A,0x00000000,0x00000000
.word 0x08140000,0x0C021C00,0x00000E10,0x00000000,0x00000000,0x04040200,0x00000002,0x00000000
.word 0x00000000,0x79493600,0x00007609,0x00000000,0x03000000,0x03030303,0x00000303,0x00000000
.word 0x02050000,0x02040700,0x00000701,0x00000000,0x11001100,0x040A0A11,0x00000404,0x00000000
.word 0x00000000,0x00000000,0x00000000,0x00000000,0x01000000,0x01010100,0x00000101,0x00000000
.word 0x04000000,0x05051E04,0x04041E05,0x00000000,0x1C000000,0x020F0202,0x00001F02,0x00000000
.word 0x00000000,0x0E0A0E11,0x00000011,0x00000000,0x11000000,0x1F040A11,0x00000404,0x00000000
.word 0x02020000,0x00000202,0x02020202,0x00000000,0x0E000000,0x09090601,0x00070806,0x00000000
.word 0x09000000,0x00000000,0x00000000,0x00000000,0x3C000000,0x8585B942,0x003C42B9,0x00000000
.word 0x07000000,0x0E090E08,0x00000000,0x00000000,0x00000000,0x0A0A1400,0x00000014,0x00000000
.word 0x00000000,0x101F0000,0x00000010,0x00000000,0x00000000,0x000E0000,0x00000000,0x00000000
.word 0x3C000000,0x9DA59D42,0x003C42A5,0x00000000,0x003F0000,0x00000000,0x00000000,0x00000000
.word 0x06000000,0x00060909,0x00000000,0x00000000,0x00000000,0x041F0404,0x0000001F,0x00000000
.word 0x07000000,0x00070204,0x00000000,0x00000000,0x07000000,0x00070402,0x00000000,0x00000000
.word 0x02040000,0x00000000,0x00000000,0x00000000,0x00000000,0x09090900,0x01010F09,0x00000000
.word 0x1E000000,0x14161717,0x00141414,0x00000000,0x00000000,0x02020000,0x00000000,0x00000000
.word 0x00000000,0x00000000,0x02040000,0x00000000,0x02000000,0x00070203,0x00000000,0x00000000
.word 0x06000000,0x06090909,0x00000000,0x00000000,0x00000000,0x14140A00,0x0000000A,0x00000000
.word 0x12230200,0x2932040A,0x00002078,0x00000000,0x12230200,0x4172040A,0x00007020,0x00000000
.word 0x14220700,0x2932040B,0x00002078,0x00000000,0x04000000,0x01020400,0x00000E01,0x00000000
.word 0x0C000804,0x3F12120C,0x00002121,0x00000000,0x0C000404,0x3F12120C,0x00002121,0x00000000
.word 0x0C000A04,0x3F12120C,0x00002121,0x00000000,0x0C001A16,0x3F12120C,0x00002121,0x00000000
.word 0x0C001200,0x3F12120C,0x00002121,0x00000000,0x24241800,0x24241818,0x0000427E,0x00000000
.word 0xF8000000,0x1EF21414,0x0000F111,0x00000000,0x1C000000,0x01010122,0x04081C22,0x00000000
.word 0x1F000402,0x010F0101,0x00001F01,0x00000000,0x1F000408,0x010F0101,0x00001F01,0x00000000
.word 0x1F000A04,0x010F0101,0x00001F01,0x00000000,0x1F001200,0x010F0101,0x00001F01,0x00000000
.word 0x07000201,0x02020202,0x00000702,0x00000000,0x07000204,0x02020202,0x00000702,0x00000000
.word 0x0E000A04,0x04040404,0x00000E04,0x00000000,0x0E001100,0x04040404,0x00000E04,0x00000000
.word 0x1E000000,0x424F4222,0x00001E22,0x00000000,0x21001A16,0x31292523,0x00002121,0x00000000
.word 0x1C000804,0x41414122,0x00001C22,0x00000000,0x1C000810,0x41414122,0x00001C22,0x00000000
.word 0x1C001408,0x41414122,0x00001C22,0x00000000,0x1C00342C,0x41414122,0x00001C22,0x00000000
.word 0x1C002200,0x41414122,0x00001C22,0x00000000,0x00000000,0x040A1100,0x0000110A,0x00000000
.word 0x5C000000,0x45495122,0x00001D22,0x00000000,0x21000804,0x21212121,0x00001E21,0x00000000
.word 0x21000408,0x21212121,0x00001E21,0x00000000,0x21000A04,0x21212121,0x00001E21,0x00000000
.word 0x21001200,0x21212121,0x00001E21,0x00000000,0x11000408,0x040A0A11,0x00000404,0x00000000
.word 0x01000000,0x1111110F,0x0000010F,0x00000000,0x09060000,0x09090509,0x00000509,0x00000000
.word 0x04020000,0x0E080600,0x00000E09,0x00000000,0x04080000,0x0E080600,0x00000E09,0x00000000
.word 0x0A040000,0x0E080600,0x00000E09,0x00000000,0x1A160000,0x0E080600,0x00000E09,0x00000000
.word 0x0A000000,0x0E080600,0x00000E09,0x00000000,0x0E0A0E00,0x0E080600,0x00000E09,0x00000000
.word 0x00000000,0x7E483600,0x00007609,0x00000000,0x00000000,0x01010E00,0x02040E01,0x00000000
.word 0x04020000,0x0F090600,0x00000E01,0x00000000,0x04080000,0x0F090600,0x00000E01,0x00000000
.word 0x0A040000,0x0F090600,0x00000E01,0x00000000,0x09000000,0x0F090600,0x00000E01,0x00000000
.word 0x02010000,0x02020200,0x00000202,0x00000000,0x01020000,0x01010100,0x00000101,0x00000000
.word 0x05020000,0x02020200,0x00000202,0x00000000,0x05000000,0x02020200,0x00000202,0x00000000
.word 0x0C000000,0x111E100A,0x00000E11,0x00000000,0x0D0B0000,0x09090700,0x00000909,0x00000000
.word 0x04020000,0x09090600,0x00000609,0x00000000,0x04080000,0x09090600,0x00000609,0x00000000
.word 0x0A040000,0x09090600,0x00000609,0x00000000,0x0D0B0000,0x09090600,0x00000609,0x00000000
.word 0x09000000,0x09090600,0x00000609,0x00000000,0x00000000,0x001F0004,0x00000004,0x00000000
.word 0x00000000,0x12121C20,0x00010E12,0x00000000,0x04020000,0x09090900,0x00000E09,0x00000000
.word 0x04080000,0x09090900,0x00000E09,0x00000000,0x0A040000,0x09090900,0x00000E09,0x00000000
.word 0x09000000,0x09090900,0x00000E09,0x00000000,0x04080000,0x09090900,0x02020406,0x00000000
.word 0x01010000,0x09090701,0x01010709,0x00000000,0x09000000,0x09090900,0x02020406,0x00000000
.section .rodata
.align 2
.global verdana9Widths @ 224 unsigned chars
verdana9Widths:
.byte 0x03,0x02,0x04,0x06,0x06,0x08,0x07,0x02,0x04,0x04,0x06,0x06,0x03,0x04,0x03,0x05
.byte 0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x03,0x03,0x06,0x06,0x06,0x05
.byte 0x08,0x07,0x06,0x07,0x07,0x06,0x06,0x07,0x07,0x04,0x04,0x06,0x06,0x08,0x07,0x08
.byte 0x06,0x08,0x06,0x06,0x07,0x07,0x07,0x08,0x06,0x06,0x06,0x03,0x05,0x03,0x06,0x06
.byte 0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x02,0x04,0x05,0x02,0x08,0x05,0x05
.byte 0x05,0x05,0x04,0x05,0x05,0x05,0x05,0x06,0x05,0x05,0x04,0x06,0x04,0x06,0x06,0x05
.byte 0x06,0x03,0x03,0x07,0x05,0x06,0x06,0x06,0x04,0x08,0x07,0x04,0x08,0x03,0x06,0x03
.byte 0x03,0x03,0x03,0x05,0x05,0x04,0x06,0x08,0x05,0x08,0x06,0x04,0x08,0x03,0x04,0x06
.byte 0x03,0x02,0x06,0x06,0x06,0x06,0x04,0x05,0x06,0x08,0x05,0x06,0x06,0x05,0x08,0x06
.byte 0x05,0x06,0x04,0x04,0x05,0x05,0x06,0x03,0x04,0x04,0x05,0x06,0x08,0x08,0x08,0x05
.byte 0x07,0x07,0x07,0x07,0x07,0x08,0x08,0x07,0x06,0x06,0x06,0x06,0x04,0x04,0x05,0x05
.byte 0x08,0x07,0x08,0x08,0x08,0x08,0x08,0x06,0x08,0x07,0x07,0x07,0x07,0x06,0x06,0x05
.byte 0x05,0x05,0x05,0x05,0x05,0x05,0x08,0x05,0x05,0x05,0x05,0x05,0x03,0x02,0x03,0x03
.byte 0x06,0x05,0x05,0x05,0x05,0x05,0x05,0x06,0x06,0x05,0x05,0x05,0x05,0x05,0x05,0x05
@}}BLOCK(verdana9)
|
afska/beat-beast
| 17,045
|
butano/hw/3rd_party/maxmod/source/mm_effect.s
|
/****************************************************************************
* __ *
* ____ ___ ____ __ ______ ___ ____ ____/ / *
* / __ `__ \/ __ `/ |/ / __ `__ \/ __ \/ __ / *
* / / / / / / /_/ /> </ / / / / / /_/ / /_/ / *
* /_/ /_/ /_/\__,_/_/|_/_/ /_/ /_/\____/\__,_/ *
* *
* Sound Effect System *
* *
* Copyright (c) 2008, Mukunda Johnson (mukunda@maxmod.org) *
* *
* Permission to use, copy, modify, and/or distribute this software for any *
* purpose with or without fee is hereby granted, provided that the above *
* copyright notice and this permission notice appear in all copies. *
* *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES *
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR *
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES *
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN *
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. *
****************************************************************************/
#include "../asm_include/mm_gba_setup.inc"
#include "../asm_include/mp_defs.inc"
#include "../asm_include/mp_mas.inc"
#include "../asm_include/mp_mas_structs.inc"
#include "../asm_include/mp_format_mas.inc"
#include "../asm_include/mp_macros.inc"
#ifdef SYS_GBA
#include "../asm_include/mp_mixer_gba.inc"
#endif
#ifdef SYS_NDS
#include "../asm_include/mp_mixer_ds.inc"
#endif
/***********************************************************************
*
* Definitions
*
***********************************************************************/
.struct 0 // mm_sound_effect
MM_SFX_SOURCE: .space 4 // word: source
MM_SFX_RATE: .space 2 // hword: rate
MM_SFX_HANDLE: .space 2 // byte: handle
MM_SFX_VOLUME: .space 1 // byte: volume
MM_SFX_PANNING: .space 1 // byte: panning
MM_SFX_SIZE: // 8 bytes total
.equ channelCount, 16
.equ releaseLevel, 200
/***********************************************************************
*
* Memory
*
***********************************************************************/
.BSS
.ALIGN 2
.GLOBAL mm_sfx_bitmask, mm_sfx_clearmask
mm_sfx_mastervolume: .space 4
mm_sfx_channels: .space 2*channelCount
mm_sfx_bitmask: .space 4
mm_sfx_clearmask: .space 4
mm_sfx_counter: .space 1
/***********************************************************************
*
* Program
*
***********************************************************************/
.TEXT
.THUMB
.ALIGN 2
/***********************************************************************
* mmResetEffects
***********************************************************************/
.global mmResetEffects
.thumb_func
mmResetEffects:
mov r0, #0
mov r1, #channelCount
ldr r2,=mm_sfx_channels
1: strh r0, [r2]
add r2, #2
sub r1, #1
bne 1b
ldr r2,=mm_sfx_bitmask
str r0, [r2]
bx lr
/***********************************************************************
* mmGetFreeEffectChannel()
*
* Return index to free effect channel
***********************************************************************/
.thumb_func
mmGetFreeEffectChannel:
ldr r0,=mm_sfx_bitmask // r0 = bitmask
ldr r0, [r0] //
mov r1, #1 // r1 = channel counter
.channel_search: // shift out bits until we find a cleared one
lsr r0, #1 //
bcc .found_channel //
add r1, #1 // r1 = index value
b .channel_search //
.found_channel:
cmp r1, #channelCount+1 // if r1 == cc+1 then r1 = 0 (no handles avail.)
bne .found_valid_channel //
mov r1, #0 //
.found_valid_channel: //
mov r0, r1 // return value
bx lr //
/***********************************************************************
* mmEffect( id )
*
* Play sound effect with default parameters
***********************************************************************/
.global mmEffect
.thumb_func
mmEffect:
push {lr}
// r0 = ssssssss
mov r1, #1 // r1 = hhhhrrrr
lsl r1, #10 //
ldr r2,=0x000080FF // r2 = ----ppvv
push {r0-r2} // mmEffectEx( sound )
mov r0, sp //
bl mmEffectEx //
add sp, #12 //
pop {r3} //
bx r3 //
/***********************************************************************
* mmEffectEx( sound )
*
* Play sound effect with specified parameters
***********************************************************************/
.global mmEffectEx
.thumb_func
mmEffectEx:
push {r4-r6, lr}
mov r4, r0
ldrh r5, [r4, #MM_SFX_HANDLE] // test if handle was given
cmp r5, #255
bne 1f
mov r5, #0
b .got_handle
1: cmp r5, #0 //
beq .generate_new_handle //
lsl r1, r5, #24 // check if channel is in use
lsr r1, #23 //
sub r1, #2 //
ldr r0,=mm_sfx_channels //
ldrb r0, [r0, r1] //
cmp r0, #0 //
beq .got_handle // [valid handle otherwise]
mov r0, r5
bl mmEffectCancel // attempt to stop active channel
cmp r0, #0 //
bne .got_handle //
// failure: generate new handle
.generate_new_handle:
bl mmGetFreeEffectChannel // generate handle
mov r5, r0 //
beq .got_handle //-(no available channels)
//
ldr r0,=mm_sfx_counter // (counter = ((counter+1) & 255))
ldrb r1, [r0] //
add r1, #1 //
strb r1, [r0] //
lsl r1, #8
orr r5, r1
lsl r5, #16
lsr r5, #16
.got_handle:
ldr r1,=mmAllocChannel // allocate new channel
bl mpp_call_r1 //
cmp r0, #255 //
bge .no_available_channels //
mov r6, r0
cmp r5, #0
beq 1f
ldr r1,=mm_sfx_channels // register data
sub r2, r5, #1 // r3 = bit
lsl r2, #24 //
lsr r2, #24 //
mov r3, #1 //
lsl r3, r2 //
lsl r2, #1 //
add r1, r2 //
add r2, r0, #1 //
strb r2, [r1, #0] //
lsr r2, r5, #8 //
strb r2, [r1, #1] //
ldr r1,=mm_sfx_bitmask // set bit
ldr r2, [r1] //
orr r2, r3 //
str r2, [r1] //
1:
ldr r1,=mm_achannels // setup channel
ldr r1, [r1] //
mov r2, #MCA_SIZE //
mul r2, r0 //
add r1, r2 //
//
mov r2, #releaseLevel //
strb r2, [r1, #MCA_FVOL] //
cmp r5, #0 //
bne 1f //
mov r2, #ACHN_BACKGROUND //
b 2f //
1: mov r2, #ACHN_CUSTOM //
2: //
strb r2, [r1, #MCA_TYPE] //
mov r2, #MCAF_EFFECT //
strb r2, [r1, #MCA_FLAGS] //
GET_MIXCH r1 // setup voice
mov r2, #MIXER_CHN_SIZE //
mul r2, r0 //
add r3, r1, r2 //
#ifdef SYS_GBA
ldr r0,=mp_solution // set sample data address
ldr r0, [r0] //
ldrh r1, [r4, #MM_SFX_SOURCE] //
lsl r1, #2 //
add r1, #12 //
ldr r1, [r0, r1] //
add r1, r0 //
ldrh r2, [r1, #8+C_SAMPLEC_DFREQ] //
add r1, #8+C_SAMPLE_DATA //
str r1, [r3, #MIXER_CHN_SRC] //
ldrh r0, [r4, #MM_SFX_RATE] // set pitch to original * pitch
mul r2, r0 //
lsr r2, #10-2 //
str r2, [r3, #MIXER_CHN_FREQ] //
mov r1, #0 // reset read position
str r1, [r3, #MIXER_CHN_READ] //
ldrb r0, [r4, #MM_SFX_VOLUME] // set volume
ldr r1,=mm_sfx_mastervolume
ldr r1, [r1]
mul r0, r1
lsr r0, #10
strb r0, [r3, #MIXER_CHN_VOL] //
ldrb r0, [r4, #MM_SFX_PANNING] // set panning
strb r0, [r3, #MIXER_CHN_PAN] //
#else
ldr r1, [r4, #MM_SFX_SOURCE] // set sample address
lsr r0, r1, #16 // > 0x10000 = external sample
bne 1f //
ldr r0,=mmSampleBank // ID# otherwise
ldr r0, [r0] //
lsl r1, #2 //
ldr r1, [r0, r1] //
lsl r1, #8 //
lsr r1, #8 //
beq .invalid_sample
add r1, #8 //
ldr r0,=0x2000000 //
add r1, r0 //
1: //
str r1, [r3, #MIXER_CHN_SAMP] //
ldrh r0, [r4, #MM_SFX_RATE] // set pitch to original * pitch
ldrh r1, [r1, #C_SAMPLEC_DFREQ] //
mul r1, r0 //
lsr r1, #10 //
strh r1, [r3, #MIXER_CHN_FREQ] //
mov r1, #0 // clear sample offset
str r1, [r3, #MIXER_CHN_READ] //
ldrb r1, [r4, #MM_SFX_PANNING] // set panning + startbit
lsr r1, #1 //
add r1, #0x80 //
strb r1, [r3, #MIXER_CHN_CNT] //
ldrb r1, [r4, #MM_SFX_VOLUME] // set volume
ldr r0,=mm_sfx_mastervolume
ldr r0, [r0]
mul r1, r0
// lsr r0, #10
lsr r2, r1, #2
// lsl r2, r1, #8
strh r2, [r3, #MIXER_CHN_VOL] //
b .valid_sample
.invalid_sample:
mov r0, #0
str r0, [r3, #MIXER_CHN_SAMP]
.valid_sample:
#endif
mov r0, r5 // return handle
pop {r4-r6} //
ret1 //
.no_available_channels:
mov r0, #0 // return bad
pop {r4-r6} //
ret1 //
/***********************************************************************
* mme_get_channel_index
*
* Test handle and return mixing channel index
***********************************************************************/
.thumb_func
mme_get_channel_index:
lsl r1, r0, #24 // mask and test channel#
lsr r1, #24-1 //
cmp r1, #0 //
beq .invalid_handle //
cmp r1, #channelCount*2 //
bgt .invalid_handle //
ldr r2,=mm_sfx_channels-2 // check if instances match
ldrh r3, [r2, r1] //
lsr r1, r3, #8 //
lsr r2, r0, #8 //
cmp r1, r2 //
bne .invalid_handle //
lsl r3, #24 // mask channel#
lsr r3, #24 //
sub r3, #1 //
bx lr //
.invalid_handle: // return invalid handle
mov r3, #0 //
mvn r3, r3 //
bx lr //
/***********************************************************************
* mmEffectActive( handle )
*
* Indicates if a sound effect is active or not
***********************************************************************/
.global mmEffectActive
.thumb_func
mmEffectActive:
push {lr} //
bl mme_get_channel_index //
cmp r3, #0 // if r3 >= 0, it is active
bge .active //
mov r0, #0 // return false
pop {r3} //
bx r3 //
.active: //
mov r0, #1 // return true
pop {r3} //
bx r3 //
/***********************************************************************
* mme_clear_channel(ch)
*
* Clear channel entry and bitmask
* r3 preserved
***********************************************************************/
.thumb_func
mme_clear_channel:
mov r1, #0
ldr r2,=mm_sfx_channels // clear effect channel
lsl r0, #1 //
strh r1, [r2, r0] //
mov r1, #1 // clear effect bitmask
lsr r0, #1 //
lsl r1, r0 //
ldr r2,=mm_sfx_bitmask //
ldr r0, [r2, #4]
orr r0, r1
str r0, [r2, #4]
ldr r0, [r2] //
bic r0, r1 //
str r0, [r2] //
bx lr
/***********************************************************************
* mmEffectVolume( handle, volume )
*
* Set effect volume
*
* volume 0..255
***********************************************************************/
.global mmEffectVolume
.thumb_func
mmEffectVolume:
push {r1, lr}
bl mme_get_channel_index
pop {r1}
bmi 1f
ldr r0,=mm_sfx_mastervolume
ldr r0, [r0]
mul r1, r0
#ifdef SYS_NDS
lsr r1, #2
#endif
#ifdef SYS_GBA
lsr r1, #10
#endif
mov r0, r3
bl mmMixerSetVolume
1: ret0
/***********************************************************************
* mmEffectPanning( handle, panning )
*
* Set effect panning
*
* panning 0..255
***********************************************************************/
.global mmEffectPanning
.thumb_func
mmEffectPanning:
push {r1, lr}
bl mme_get_channel_index
pop {r1}
bmi 1f
mov r0, r3
bl mmMixerSetPan
1: ret0
/***********************************************************************
* mmEffectRate( handle, rate )
*
* Set effect playback rate
***********************************************************************/
.global mmEffectRate
.thumb_func
mmEffectRate:
push {r1, lr}
bl mme_get_channel_index
pop {r1}
bmi 1f
mov r0, r3
bl mmMixerSetFreq
1: ret0
/***********************************************************************
* mmEffectCancel( handle )
*
* Stop sound effect
***********************************************************************/
.global mmEffectCancel
.thumb_func
mmEffectCancel:
push {r0, lr}
bl mme_get_channel_index
pop {r0}
bmi 1f
mov r1, #MCA_SIZE // free achannel
mul r1, r3 //
ldr r2,=mm_achannels //
ldr r2, [r2] //
add r2, r1 //
mov r1, #ACHN_BACKGROUND //
strb r1, [r2, #MCA_TYPE] //
mov r1, #0 //
strb r1, [r2, #MCA_FVOL] // clear volume for channel allocator
lsl r0, #24
lsr r0, #24
sub r0, #1
bl mme_clear_channel
mov r1, #0 // zero voice volume
mov r0, r3 //
bl mmMixerSetVolume //
mov r0, #1
ret1
1:
mov r0, #0
ret1
/***********************************************************************
* mmEffectRelease( channel )
*
* Release sound effect (allow interruption)
***********************************************************************/
.global mmEffectRelease
.thumb_func
mmEffectRelease:
push {r0, lr}
bl mme_get_channel_index
pop {r0}
bmi 1f
mov r1, #MCA_SIZE // release achannel
mul r1, r3 //
ldr r2,=mm_achannels //
ldr r2, [r2] //
add r2, r1 //
mov r1, #ACHN_BACKGROUND //
strb r1, [r2, #MCA_TYPE] //
lsl r0, #24
lsr r0, #24
sub r0, #1
bl mme_clear_channel
1: ret0
/***********************************************************************
* mmEffectScaleRate( channel, factor )
*
* Scale sampling rate by 6.10 factor
***********************************************************************/
.global mmEffectScaleRate
.thumb_func
mmEffectScaleRate:
push {r1,lr}
bl mme_get_channel_index
pop {r1}
bmi 1f
mov r0, r3
bl mmMixerMulFreq
1: ret0
/***********************************************************************
* mmSetEffectsVolume( volume )
*
* set master volume scale, 0->1024
***********************************************************************/
.global mmSetEffectsVolume
.thumb_func
mmSetEffectsVolume:
lsr r1, r0, #10
beq 1f
mov r0, #1
lsl r0, #10
1: ldr r1,=mm_sfx_mastervolume
str r0, [r1]
bx lr
/***********************************************************************
* mmEffectCancelAll()
*
* Stop all sound effects
***********************************************************************/
.global mmEffectCancelAll
.thumb_func
mmEffectCancelAll:
push {r4-r7,lr}
ldr r4,=mm_sfx_bitmask
ldr r4, [r4]
ldr r6,=mm_sfx_channels
mov r5, #0
lsr r4, #1
bcc .mmeca_next
.mmeca_process:
ldrb r7, [r6, r5]
sub r7, #1
bmi .mmeca_next
mov r0, r7
mov r1, #0
bl mmMixerSetVolume
ldr r0,=mm_achannels // free achannel
ldr r0, [r0] //
mov r1, #MCA_SIZE //
mul r1, r7 //
add r0, r1 //
mov r1, #ACHN_BACKGROUND //
strb r1, [r0, #MCA_TYPE] //
mov r1, #0
strb r1, [r0, #MCA_FVOL] //
.mmeca_next:
add r5, #2
lsr r4, #1
bcs .mmeca_process
bne .mmeca_next
bl mmResetEffects
POP {r4-r7}
pop {r3}
bx r3
/***********************************************************************
* mmUpdateEffects()
*
* Update sound effects
***********************************************************************/
.global mmUpdateEffects
.thumb_func
mmUpdateEffects:
push {r4-r6,lr}
ldr r4,=mm_sfx_bitmask
ldr r4, [r4]
ldr r6,=mm_sfx_channels
mov r5, #0
lsr r4, #1
bcc .next_channel
.process_channel:
ldrb r0, [r6, r5] // get channel index
sub r0, #1 //
bmi .next_channel //
GET_MIXCH r1
mov r2, #MIXER_CHN_SIZE // get mixing channel pointer
mul r2, r0 //
add r1, r2 //
#ifdef SYS_NDS // test if channel is still active
//
ldr r2, [r1, #MIXER_CHN_SAMP] //
lsl r2, #8 //
bne .next_channel //
//
#else //
//
ldr r2, [r1, #MIXER_CHN_SRC] //
asr r2, #31 //
beq .next_channel //
//
#endif //
ldr r1,=mm_achannels // free achannel
ldr r1, [r1] //
mov r2, #MCA_SIZE //
mul r2, r0 //
add r1, r2 //
mov r0, #0 //
strb r0, [r1, #MCA_TYPE] //
strb r0, [r1, #MCA_FLAGS] //
strb r0, [r6, r5]
.next_channel:
add r5, #2 // look for another set bit
lsr r4, #1 //
bcs .process_channel //
add r5, #2 //
lsr r4, #1 //
bcs .process_channel //
bne .next_channel //
mov r4, #0
mov r5, #1
lsl r5, #32-channelCount
ldr r6,=mm_sfx_channels
.build_new_bitmask:
ldrb r0, [r6]
add r6, #2
cmp r0, #0
beq 1f
orr r4, r5
1: lsl r5, #1
bne .build_new_bitmask
lsr r4, #32-channelCount
ldr r0,=mm_sfx_bitmask
ldr r1, [r0] // r1 = bits that change from 1->0
mov r2, r1
eor r1, r4
and r1, r2
str r4, [r0]
ldr r4, [r0, #4]
orr r4, r1
str r4, [r0, #4] // write 1->0 mask
pop {r4-r6,pc}
.pool
.end
|
afska/beat-beast
| 114,997
|
butano/hw/3rd_party/maxmod/source/mm_mas.s
|
/****************************************************************************
* __ *
* ____ ___ ____ __ ______ ___ ____ ____/ / *
* / __ `__ \/ __ `/ |/ / __ `__ \/ __ \/ __ / *
* / / / / / / /_/ /> </ / / / / / /_/ / /_/ / *
* /_/ /_/ /_/\__,_/_/|_/_/ /_/ /_/\____/\__,_/ *
* *
* Module Processing *
* *
* Copyright (c) 2008, Mukunda Johnson (mukunda@maxmod.org) *
* *
* Permission to use, copy, modify, and/or distribute this software for any *
* purpose with or without fee is hereby granted, provided that the above *
* copyright notice and this permission notice appear in all copies. *
* *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES *
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR *
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES *
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN *
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. *
****************************************************************************/
#include "../asm_include/mm_gba_setup.inc"
#include "../asm_include/mp_format_mas.inc"
#include "../asm_include/mp_mas_structs.inc"
#include "../asm_include/mp_defs.inc"
#include "../asm_include/mp_macros.inc"
//-----------------------------------------------------------------------------
#ifdef SYS_GBA
//-----------------------------------------------------------------------------
#include "../asm_include/mp_mixer_gba.inc"
#include "../asm_include/swi_gba.inc"
//-----------------------------------------------------------------------------
#endif
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
#ifdef SYS_NDS
//-----------------------------------------------------------------------------
#include "../asm_include/mp_mixer_ds.inc"
#include "../asm_include/swi_nds.inc"
//-----------------------------------------------------------------------------
#endif
//-----------------------------------------------------------------------------
.equ S3M_FREQ_DIVIDER ,57268224 // (s3m,xm,it)
.equ MOD_FREQ_DIVIDER_PAL ,56750314 // (mod)
.equ MOD_FREQ_DIVIDER_NTSC ,57272724 // (---)
/******************************************************************************
*
* Memory
*
******************************************************************************/
.BSS
.ALIGN 2
/******************************************************************************
* mmLayerMain
*
* Layer data for module playback.
******************************************************************************/
.global mmLayerMain
mmLayerMain: .space MPL_SIZE
/******************************************************************************
* mmLayerSub
*
* Layer data for jingle playback.
******************************************************************************/
.global mmLayerSub
mmLayerSub: .space MPL_SIZE
/******************************************************************************
* mpp_vars
*
* Holds intermediate data during the module processing.
******************************************************************************/
.global mpp_vars
mpp_vars: .space MPV_SIZE
.ALIGN 2
/******************************************************************************
* mpp_layerp
*
* Pointer to layer data during processing.
******************************************************************************/
.global mpp_layerp
mpp_layerp: .space 4
/******************************************************************************
* mpp_channels
*
* Pointer to channel array during processing
******************************************************************************/
.global mpp_channels
mpp_channels: .space 4
/******************************************************************************
* mpp_resolution
*
* Speed divider for DS timing.
******************************************************************************/
mpp_resolution: .space 4
/******************************************************************************
* mm_mastertempo
*
* Master tempo scaler.
******************************************************************************/
mm_mastertempo: .space 4
/******************************************************************************
* mm_masterpitch
*
* Master pitch scaler.
******************************************************************************/
mm_masterpitch: .space 4
/******************************************************************************
* mpp_nchannels
*
* Number of channels in layer
******************************************************************************/
.global mpp_nchannels
mpp_nchannels: .space 1
/******************************************************************************
* mpp_clayer
*
* Layer selection, 0 = main, 1 = sub
******************************************************************************/
.global mpp_clayer
mpp_clayer: .space 1
/******************************************************************************
* mm_achannels, mm_pchannels, mm_num_mch, mm_num_ach, mm_schannels
*
* Channel data/sizes, don't move these around--see mmInit first
******************************************************************************/
.ALIGN 2
.global mm_achannels, mm_pchannels, mm_num_mch, mm_num_ach, mm_schannels
mm_achannels: .space 4
mm_pchannels: .space 4
mm_num_mch: .space 4
mm_num_ach: .space 4
mm_schannels: .space MP_SCHANNELS*MCH_SIZE
/******************************************************************************
*
* Macros
*
******************************************************************************/
/******************************************************************************
* mpp_InstrumentPointer
*
* Calculate instrument address.
* Requires r8 = layer
* Returns in r0
* Trashes r1, r2
******************************************************************************/
.macro mpp_InstrumentPointer
mov r1, r8
ldr r2,[r1,#MPL_SONGADR]
ldr r1,[r1,#MPL_INSTTABLE]
lsl r0, #2
ldr r0,[r1,r0]
add r0, r2
.endm
/******************************************************************************
* mpp_SamplePointer
*
* Calculate sample address.
* Requires r8 = layer
* Returns in r0
* Trashes r1, r2
******************************************************************************/
.macro mpp_SamplePointer
mov r1, r8
ldr r2,[r1,#MPL_SONGADR]
ldr r1,[r1,#MPL_SAMPTABLE]
lsl r0, #2
ldr r0,[r1,r0]
add r0, r2
.endm
/******************************************************************************
*
* Program
*
******************************************************************************/
.TEXT
.ALIGN 2
/******************************************************************************
* mpp_resetchannels(...)
*
* Reset channel data, and any active channels linked to the layer.
* Requires r5 = layer, r6 = channels, r7 = #channels
******************************************************************************/
.thumb_func
mpp_resetchannels:
push {r4-r6}
mov r0, r6 // clear channel data to 0
mov r1, #MCH_SIZE/4 //
mul r1, r7 //
mov r2, #0 //
1: stmia r0!, {r2} //
sub r1, #1 //
bne 1b //
mov r0, r6 // reset channel indexes
sub r0, #MCH_SIZE-MCH_ALLOC //
mov r1, #MCH_SIZE //
mul r1, r7 //
mov r2, #255 //
1: strb r2, [r0, r1] //
sub r1, #MCH_SIZE //
bne 1b //
GET_MIXCH r4 // reset active channels linked to this layer
ldr r6,=mpp_clayer //
ldrb r6, [r6] //
#ifdef SYS_GBA // disabled status differs between systems
ldr r5,=1<<31 //
#endif //
#ifdef SYS_NDS //
mov r5, #0 //
#endif //
ldr r0,=mm_achannels // r0 = achannels
ldr r0, [r0] //
ldr r1,=mm_num_ach // r1 = #achannels
ldr r1, [r1] //
mov r2, #0 // r2 = 0 (for clearing)
.mpic_loop3:
ldrb r3, [r0, #MCA_FLAGS] // test if layer matches
lsr r3, #6 //
cmp r3, r6 //
bne .mpic_l3_skip //
mov r3, #MCA_SIZE-4 // clear achannel data to zero
.mpic_loop4: //
str r2, [r0, r3] //
sub r3, r3, #4 //
bpl .mpic_loop4 //
str r5, [r4] // disable mixer channel
.mpic_l3_skip:
add r0, #MCA_SIZE // increment stuff and loop
add r4, #MIXER_CHN_SIZE //
//
sub r1, #1 //
bne .mpic_loop3 //
pop {r4-r6}
bx lr
#ifdef SYS_NDS
/******************************************************************************
* mm_reset_channels()
*
* Reset all channels.
******************************************************************************/
.global mm_reset_channels
.thumb_func
mm_reset_channels:
push {lr}
ldr r0,=mm_achannels // clear active channel data
ldr r0, [r0] //
mov r1, #0 //
ldr r2,=MCA_SIZE*32/4 //
//
1: stmia r0!, {r1} //
sub r2, #1 //
bne 1b //
ldr r0,=mm_pchannels // reset channel allocation
ldr r0, [r0] //
mov r1, #255 //
mov r2, #32 //
//
1: strb r1, [r0, #MCH_ALLOC] //
add r0, #MCH_SIZE //
sub r2, #1 //
bne 1b //
ldr r0,=mm_schannels // reset channel allocation
mov r2, #4 //
//
1: strb r1, [r0, #MCH_ALLOC] //
add r0, #MCH_SIZE //
sub r2, #1 //
bne 1b //
bl mmResetEffects
pop {r3}
bx r3
#endif
/******************************************************************************
* mpp_suspend()
*
* Suspend main module and associated channels.
******************************************************************************/
.thumb_func
mpp_suspend:
push {r4,lr}
ldr r0,=mm_achannels
ldr r0, [r0]
GET_MIXCH r1
ldr r2,=mm_num_ach
ldr r2, [r2]
mov r4, #0
.mpps_loop:
ldrb r3, [r0, #MCA_FLAGS]
lsr r3, #6
bne .mpps_next
#ifdef SYS_GBA
str r4, [r1, #MIXER_CHN_FREQ]
#else
strh r4, [r1, #MIXER_CHN_FREQ]
strh r4, [r1, #MIXER_CHN_VOL]
#endif
.mpps_next:
add r0, #MCA_SIZE
add r1, #MIXER_CHN_SIZE
sub r2, #1
bne .mpps_loop
pop {r4, pc}
/******************************************************************************
*
* NDS System
*
******************************************************************************/
//-----------------------------------------------------------------------------
#ifdef SYS_NDS
//-----------------------------------------------------------------------------
/******************************************************************************
* mmStart( module_ID, mode )
*
* Start module playback.
*
* module_ID : Index of module.
* mode : Playback mode.
******************************************************************************/
.global mmStart
.thumb_func
mmStart:
mov r2, #0
.mpps_backdoor:
lsl r0, #2
ldr r3,=mmModuleBank
ldr r3, [r3]
ldr r0, [r3, r0]
cmp r0, #0
beq 1f
add r0, #8
b mmPlayModule
1: bx lr
/******************************************************************************
* mmJingle( module_ID )
*
* Play module as jingle.
*
* module_ID : Index of module
******************************************************************************/
.global mmJingle
.thumb_func
mmJingle:
mov r2, #1
mov r1, #MPP_PLAY_ONCE
b .mpps_backdoor
//-----------------------------------------------------------------------------
#endif
//-----------------------------------------------------------------------------
/******************************************************************************
*
* GBA System
*
******************************************************************************/
//-----------------------------------------------------------------------------
#ifdef SYS_GBA
//-----------------------------------------------------------------------------
/******************************************************************************
* mmStart( module_ID, mode )
*
* Start module playback
*
* module_ID : id of module
* mode : mode of playback
******************************************************************************/
.global mmStart
.thumb_func
mmStart:
mov r2, #0
.mpps_backdoor:
push {r2}
ldr r2,=mp_solution @ resolve song address
ldr r2, [r2]
ldrh r3, [r2, #0]
lsl r3, #2
add r3, #12
add r3, r2
lsl r0, #2
add r0, r3
ldr r0, [r0]
add r0, r2
pop {r2}
add r0, #8
b mmPlayModule
1: bx lr
/******************************************************************************
* mmJingle( module_ID )
*
* Start jingle playback
*
* module_ID : index of module
******************************************************************************/
.global mmJingle
.thumb_func
mmJingle:
mov r2, #1
mov r1, #MPP_PLAY_ONCE
b .mpps_backdoor
//-----------------------------------------------------------------------------
#endif
//-----------------------------------------------------------------------------
/******************************************************************************
* mmPlayModule( address, mode, layer )
*
* Start playing module.
******************************************************************************/
.global mmPlayModule
.thumb_func
mmPlayModule:
push {lr}
push {r4-r7}
ldr r3,=mpp_clayer
strb r2, [r3]
cmp r2, #0
bne 1f
ldr r5,=mmLayerMain
@ldr r6,=mpp_pchannels
ldr r6,=mm_pchannels
ldr r6,[r6]
@mov r7, #MP_MCHANNELS
ldr r7,=mm_num_mch
ldr r7,[r7]
b 2f
1: ldr r5,=mmLayerSub
ldr r6,=mm_schannels
mov r7, #MP_SCHANNELS
2:
// push {r2}
mov r2, #MPL_MODE
strb r1, [r5, r2]
mov r4, r0
str r4, [r5, #MPL_SONGADR]
bl mpp_resetchannels
ldrb r3, [r4, #C_MAS_INSTN]
ldrb r2, [r4, #C_MAS_SAMPN]
lsl r3, #2
lsl r2, #2
mov r0, r4
add r0, #255
add r0, #C_MAS_TABLES-255
str r0, [r5, #MPL_INSTTABLE] @ setup instrument table
add r0, r3
str r0, [r5, #MPL_SAMPTABLE] @ setup sample table
add r0, r2
str r0, [r5, #MPL_PATTTABLE] @ setup pattern table
mov r0, #0 @ set pattern to 0
@ldr r1,=mpp_setposition
@bl mpp_call_r1
bl mpp_setposition
ldrb r0, [r4, #C_MAS_TEMPO] @ load initial tempo
bl mpp_setbpm
ldrb r0, [r4, #C_MAS_GV] @ load initial global volume
strb r0, [r5, #MPL_GV]
ldrb r0, [r4, #C_MAS_FLAGS] @ read song flags
strb r0, [r5, #MPL_FLAGS] @ save
lsl r0, #32-2
lsr r0, #32-2+1
strb r0, [r5, #MPL_OLDEFFECTS]
ldrb r0, [r4, #C_MAS_SPEED] @ speed
strb r0, [r5, #MPL_SPEED] @ and set
mov r0, #1 // mpp_playing=true
strb r0, [r5, #MPL_ISPLAYING]
mov r1, #MPL_VALID // set valid flag
strb r0, [r5, r1] //
bl mpp_resetvars
@ setup channel volumes
mov r0, r6
add r0, #MCH_CVOLUME
mov r3, r7
add r4, #C_MAS_CHANVOL
.cvol_setup:
ldrb r1, [r4]
strb r1, [r0]
add r0, #MCH_SIZE
add r4, #1
sub r3, #1
bne .cvol_setup
add r4, #32
sub r4, r7
mov r0, r6
add r0, #MCH_PANNING
mov r3, r7
.cpan_setup:
ldrb r1, [r4]
strb r1, [r0]
add r0, #MCH_SIZE
add r4, #1
sub r3, #1
bne .cpan_setup
// pop {r2} @ <-- FIX.2 WHY WAS THIS PRESERVED
pop {r4-r7}
pop {r0} @ return
bx r0 @
.pool
/******************************************************************************
* mmPause()
*
* Pause module playback.
******************************************************************************/
.global mmPause
.thumb_func
mmPause:
push {lr}
push {r5}
ldr r5,=mmLayerMain
mov r0, #MPL_VALID
ldrb r0, [r5, r0]
cmp r0, #0
beq 1f
mov r0, #0
strb r0, [r5, #MPL_ISPLAYING]
bl mpp_suspend
1: pop {r5}
ret0
/******************************************************************************
* mmResume()
*
* Resume module playback.
******************************************************************************/
.global mmResume
.thumb_func
mmResume:
ldr r1,=mmLayerMain
mov r0, #MPL_VALID
ldrb r0, [r1, r0]
cmp r0, #0
beq 1f
mov r0, #1
strb r0, [r1, #MPL_ISPLAYING]
1: bx lr
/******************************************************************************
* mmActive()
*
* Returns true if module is playing.
******************************************************************************/
.global mmActive
.thumb_func
mmActive:
ldr r0,=mmLayerMain
ldrb r0, [r0, #MPL_ISPLAYING]
bx lr
/******************************************************************************
* mmActiveSub()
*
* Returns true if a jingle is playing.
******************************************************************************/
.global mmActiveSub
.thumb_func
mmActiveSub:
ldr r0,=mmLayerSub
ldrb r0, [r0, #MPL_ISPLAYING]
bx lr
/******************************************************************************
* mmSetModuleVolume( volume )
*
* Set master module volume.
*
* volume : 0->1024
******************************************************************************/
.global mmSetModuleVolume
.thumb_func
mmSetModuleVolume:
@ clamp volume 0->1024
lsr r1, r0, #10
beq 1f
mov r0, #1
lsl r0, #10
@ set volume
1: ldr r1,=mmLayerMain
mov r2, #MPL_VOLUME
strh r0, [r1, r2]
bx lr
/******************************************************************************
* mmSetJingleVolume( volume )
*
* Set master jingle volume.
*
* volume : 0->1024
******************************************************************************/
.global mmSetJingleVolume
.thumb_func
mmSetJingleVolume:
@ clamp volume 0->1024
lsr r1, r0, #10
beq 1f
mov r0, #1
lsl r0, #10
@ set volume
1: ldr r1,=mmLayerSub @mpp_layerB
mov r2, #MPL_VOLUME
strh r0, [r1, r2]
bx lr
/******************************************************************************
* mppStop() [[internal function]]
*
* Stop module playback.
******************************************************************************/
.thumb_func
mppStop:
push {lr}
ldr r0,=mpp_clayer
ldrb r0, [r0]
cmp r0, #0
beq 1f
ldr r5,=mmLayerSub
ldr r6,=mm_schannels
mov r7, #MP_SCHANNELS
b 2f
1: ldr r5,=mmLayerMain
@ldr r6,=mpp_pchannels
ldr r6,=mm_pchannels
ldr r6,[r6]
@mov r7, #MP_MCHANNELS
ldr r7,=mm_num_mch
ldr r7,[r7]
2:
mov r0, #0
strb r0, [r5, #MPL_ISPLAYING]
mov r1, #MPL_VALID
strb r0, [r5, r1]
bl mpp_resetchannels
pop {r0}
bx r0
/******************************************************************************
* mmGetPositionTick()
*
* Get current number of elapsed ticks in the row being played.
******************************************************************************/
.global mmGetPositionTick
.thumb_func
mmGetPositionTick:
ldr r0,=mmLayerMain
ldrb r0, [r0, #MPL_TICK]
bx lr
/******************************************************************************
* mmGetPositionRow()
*
* Get current row being played.
******************************************************************************/
.global mmGetPositionRow
.thumb_func
mmGetPositionRow:
ldr r0,=mmLayerMain
ldrb r0, [r0, #MPL_ROW]
bx lr
/******************************************************************************
* mmGetPosition()
*
* Get current pattern order being played.
******************************************************************************/
.global mmGetPosition
.thumb_func
mmGetPosition:
ldr r1,=mmLayerMain
ldrb r0, [r1, #MPL_POSITION]
bx lr
/******************************************************************************
* mmPosition( position )
*
* Set playback position
******************************************************************************/
.global mmPosition
.thumb_func
mmPosition:
push {r4-r7,lr}
ldr r5,=mmLayerMain
ldr r6,=mm_pchannels
ldr r6,[r6]
ldr r7,=mm_num_mch
ldr r7, [r7]
push {r0}
// bl mpp_resetchannels
pop {r0}
bl mpp_setposition
pop {r4-r7}
pop {r3}
bx r3
/******************************************************************************
* mmSetModuleTempo( tempo )
*
* Set master tempo
*
* tempo : x.10 fixed point tempo, 0.5->2.0
******************************************************************************/
.global mmSetModuleTempo
.thumb_func
mmSetModuleTempo:
push {r5,lr}
mov r1, #1 // clamp value: 512->2048
lsl r1, #11 //
cmp r0, r1 //
ble 1f //
mov r0, r1 //
1: mov r1, #1 //
lsl r1, #9 //
cmp r0, r1 //
bge 1f //
mov r0, r1 //
1:
ldr r1,=mm_mastertempo
str r0, [r1]
ldr r5,=mmLayerMain
ldr r0,=mpp_clayer
mov r1, #0
strb r1, [r0]
ldrb r0, [r5, #MPL_BPM]
cmp r0, #0
beq 1f
bl mpp_setbpm
1: pop {r5}
pop {r3}
bx r3
/******************************************************************************
* mmSetModulePitch( pitch )
*
* Set master pitch
*
* pitch : x.10 fixed point value, range = 0.5->2.0
******************************************************************************/
.global mmSetModulePitch
.thumb_func
mmSetModulePitch:
push {r5,lr}
mov r1, #1 // clamp value: 512->2048
lsl r1, #11 //
cmp r0, r1 //
ble 1f //
mov r0, r1 //
1: mov r1, #1 //
lsl r1, #9 //
cmp r0, r1 //
bge 1f //
mov r0, r1 //
1:
ldr r1,=mm_masterpitch
str r0, [r1]
1: pop {r5}
pop {r3}
bx r3
.pool
//-----------------------------------------------------------------------------
#ifdef SYS_NDS7
//-----------------------------------------------------------------------------
/******************************************************************************
* mmSetResolution( divider )
*
* Set update resolution
******************************************************************************/
.global mmSetResolution
.thumb_func
mmSetResolution:
push {r5, lr}
ldr r1,=mpp_resolution
str r0, [r1]
ldr r5,=mmLayerMain
ldr r0,=mpp_clayer
mov r1, #0
strb r1, [r0]
ldrb r0, [r5, #MPL_BPM]
cmp r0, #0
beq 1f
bl mpp_setbpm
1: ldr r5,=mmLayerSub
ldr r0,=mpp_clayer
mov r1, #1
strb r1, [r0]
ldrb r0, [r5, #MPL_BPM]
cmp r0, #0
beq 1f
bl mpp_setbpm
1: pop {r5}
pop {r3}
bx r3
#endif
/******************************************************************************
* mmStop()
*
* Stop module playback.
******************************************************************************/
.global mmStop
.thumb_func
mmStop:
push {r4-r7,lr}
ldr r1,=mpp_clayer
mov r0, #0
strb r0, [r1]
bl mppStop
pop {r4-r7}
ret3
/******************************************************************************
* mpp_resetvars()
*
* Reset pattern variables
* Input r5 = layer
******************************************************************************/
.thumb_func
mpp_resetvars:
mov r0, #255
strb r0, [r5, #MPL_PATTJUMP]
mov r0, #0
strb r0, [r5, #MPL_PATTJUMP_ROW]
bx lr
/******************************************************************************
* mpp_setbpm( bpm )
*
* Set BPM. bpm = 32..255
* Input r5 = layer
******************************************************************************/
.thumb_func
mpp_setbpm:
strb r0, [r5, #MPL_BPM]
#ifdef SYS_GBA
ldr r1,=mpp_clayer
ldrb r1, [r1]
cmp r1, #0
bne 1f
ldr r1,=mm_mastertempo // multiply by master tempo
ldr r1, [r1] //
mul r1, r0 //
lsr r1, #10 //
ldr r0,=mm_bpmdv @ samples per tick ~= mixfreq / (bpm/2.5) ~= mixfreq*2.5/bpm
ldr r0,[r0]
swi SWI_DIVIDE @ SWI 07h, divide r1/r0
lsr r0, #1 @ multiple of two
lsl r0, #1 @ ---------------
mov r1, #MPL_TICKRATE
strh r0, [r5, r1] @
mov r1, #MPL_SAMPCOUNT
// mov r0, #0
// strh r0, [r5, r1]
bx lr @ return
1: @ SUB LAYER, time using vsync (rate = bpm/2.5 / 59.7)
lsl r0, #15
mov r1, #149
swi SWI_DIVIDE
mov r1, #MPL_TICKRATE
strh r0, [r5, r1]
bx lr
#endif
#ifdef SYS_NDS
@ vsync = ~59.8261 HZ (says GBATEK)
@ divider = hz * 2.5 * 64
ldr r1,=mpp_clayer
ldrb r1, [r1]
cmp r1, #0
bne 1f
ldr r1,=mm_mastertempo // multiply by master tempo
ldr r1, [r1] //
mul r0, r1 //
// lsr r1, #10 //
lsl r0, #16+6-10
b 2f
1:
lsl r0, #16+6
2:
@ using 60hz vsync for timing
// lsl r0, #16+6
ldr r1,=mpp_resolution
ldr r1, [r1]
swi SWI_DIVIDE
lsr r0, #1
mov r1, #MPL_TICKRATE
strh r0, [r5, r1]
bx lr
#endif
.pool
/******************************************************************************
* mpp_setposition( position )
*
* Set sequence position.
* Input r5 = layer
******************************************************************************/
.thumb_func
mpp_setposition:
push {lr}
mpp_setpositionA:
strb r0, [r5, #MPL_POSITION]
ldr r1, [r5, #MPL_SONGADR]
mov r3, r1
add r1, #C_MAS_ORDER @ get sequence entry
ldrb r1, [r1, r0] @
cmp r1, #254
bne .mpsp_skippatt
add r0, #1
b mpp_setpositionA
.mpsp_skippatt:
cmp r1, #255
bne .mpsp_endsong
@ END OF SONG!!! WOOPHEE!!!!
mov r0, #MPL_MODE @mpp_playmode
ldrb r0, [r5, r0]
cmp r0, #MPP_PLAY_ONCE
bge 1f
@ @ its looping:
b 3f
1: @ its playing once:
bl mppStop
mov r0, #MPCB_SONGFINISHED
ldr r2,=mmCallback
ldr r2,[r2]
cmp r2, #0
beq 3f
ldr r1,=mpp_clayer
ldrb r1, [r1]
bl mpp_call_r2
3:
ldrb r0, [r5, #MPL_ISPLAYING]
cmp r0, #0
bne 1f
pop {pc}
1:
ldr r0, [r5, #MPL_SONGADR] @ set position to 'restart'
ldrb r0, [r0, #C_MAS_REP]
b mpp_setpositionA
.mpsp_endsong:
mov r0, r1
ldr r1, [r5, #MPL_PATTTABLE]
lsl r0, #2
@ r1 = pattern address( in table )
ldr r1, [r1, r0]
add r1, r3 @ add song address
@ r1 = pattern address
ldrb r2, [r1] @ set pattern size
strb r2, [r5, #MPL_NROWS] @
mov r2, #0 @ reset tick/row
strh r2, [r5, #MPL_TICK]
strb r2, [r5, #MPL_FPATTDELAY]
strb r2, [r5, #MPL_PATTDELAY]
mov r0, #MPL_PATTREAD
add r1, #1
str r1, [r5, r0] @ store pattern data address
mov r0, #MPL_PLOOP_ADR @ reset pattern loop
str r1, [r5, r0]
mov r0, #0
strb r0, [r5, #MPL_PLOOP_ROW]
strb r0, [r5, #MPL_PLOOP_TIMES]
pop {pc}
//-----------------------------------------------------------------------------
#ifdef SYS_NDS
//-----------------------------------------------------------------------------
/******************************************************************************
* mppUpdateLayer( layer )
*
* Update module layer
******************************************************************************/
.thumb_func
mppUpdateLayer:
push {lr}
ldr r1,=mpp_layerp
str r0, [r1]
mov r1, #MPL_TICKRATE
ldrh r1, [r0, r1]
mov r2, #MPL_TICKFRAC
ldrh r3, [r0, r2]
lsl r1, #1
add r3, r1
strh r3, [r0, r2]
lsr r3, #16
beq 1f
2: push {r3}
bl mppProcessTick
pop {r3}
sub r3, #1
bne 2b
1: pop {pc}
/******************************************************************************
* mmPulse()
*
* NDS Work Routine
******************************************************************************/
.global mmPulse
.thumb_func
mmPulse:
push {lr}
ldr r0,=mpp_channels // update main layer
ldr r1,=mm_pchannels //
ldr r1,[r1] //
str r1, [r0] //
ldr r0,=mpp_nchannels //
ldr r1,=mm_num_mch //
ldr r1,[r1] //
strb r1, [r0] //
ldr r0,=mpp_clayer //
mov r1, #0 //
strb r1, [r0] //
//
ldr r0,=mmLayerMain //
bl mppUpdateLayer //
ldr r0,=mpp_channels // update sub layer
ldr r1,=mm_schannels //
str r1, [r0] //
ldr r0,=mpp_nchannels //
mov r1, #MP_SCHANNELS //
strb r1, [r0] //
ldr r0,=mpp_clayer //
mov r1, #1 //
strb r1, [r0] //
//
ldr r0,=mmLayerSub //
bl mppUpdateLayer //
pop {pc}
//-----------------------------------------------------------------------------
#endif
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
#ifdef SYS_GBA
//-----------------------------------------------------------------------------
/******************************************************************************
* mppUpdateSub()
*
* Update sub-module/jingle, this is bad for some reason...
******************************************************************************/
.global mppUpdateSub
.thumb_func
mppUpdateSub:
ldr r0,=mmLayerSub
ldrb r0, [r0, #MPL_ISPLAYING]
cmp r0, #0
bne .mppus_update
bx lr
.mppus_update:
ldr r0,=mpp_channels
ldr r1,=mm_schannels
str r1, [r0]
ldr r0,=mpp_nchannels
mov r1, #MP_SCHANNELS
strb r1, [r0]
ldr r0,=mpp_clayer
mov r1, #1
strb r1, [r0]
push {lr}
ldr r0,=mmLayerSub
ldr r1,=mpp_layerp
str r0, [r1]
mov r1, #MPL_TICKRATE
ldrh r1, [r0, r1]
mov r2, #MPL_TICKFRAC
ldrh r3, [r0, r2]
lsl r1, #1
add r3, r1
strh r3, [r0, r2]
lsr r3, #16
beq 1f
2: push {r3}
ldr r1,=mppProcessTick
bl mpp_call_r1
pop {r3}
sub r3, #1
bgt 2b
1: pop {pc}
//-----------------------------------------------------------------------------
#endif
//-----------------------------------------------------------------------------
.pool
//-----------------------------------------------------------------------------
// IWRAM CODE
//-----------------------------------------------------------------------------
#ifdef USE_IWRAM
.SECTION ".iwram", "ax", %progbits
.ALIGN 2
#endif
//-----------------------------------------------------------------------------
/******************************************************************************
* mppProcessTick()
*
* Process module tick.
******************************************************************************/
.global mppProcessTick @@@@@@@@@@@@@@@@@@
.thumb_func @@@@ @@@ @@
@@@ @@ @@@@@@ @@
mppProcessTick: @@ @@@ @ @@
@@ @@@@@@@ @@@
@@@@@@@@@@@@@@@@@
add r0,pc,#0 // switch to ARM to preserve regs
bx r0 //
.arm //
stmfd sp!, {lr} //
stmfd sp!, {r4-r10} //
add r0,pc,#1 // switch back to THUMB
bx r0
.thumb
ldr r0,=mpp_layerp // test if module is playing
ldr r0, [r0] //
mov r8, r0 //
ldrb r1, [r0, #MPL_ISPLAYING] //
cmp r1, #0 //
bne 1f //
ldr r1,=.mppt_exit //
mov pc,r1 //
1:
@---------------------------------------------------
@ read pattern data
@---------------------------------------------------
ldrb r1, [r0, #MPL_PATTDELAY]
cmp r1, #0
bne .mpp_pt_skippatternread
ldrb r0, [r0, #MPL_TICK]
cmp r0, #0
bne .mpp_pt_skippatternread
PROF_START
fjump2 mmReadPattern
//bl mpp_ReadPattern
PROF_END 4
@-----------------------------------------
.mpp_pt_skippatternread:
mov r0, r8
mov r4, #MPL_MCH_UPDATE
ldr r4, [r0, r4]
@---------------------------------------------------
@ loop through module channels
@---------------------------------------------------
ldr r7,=mpp_channels
ldr r7, [r7]
mov r0, #0
mov r10, r0 @ use r10 as channel counter
mov r0, r8
ldrb r0, [r0, #MPL_TICK]
cmp r0, #0
bne pchannel_loop_other
@---------------------------------------------------
pchannel_loop_first:
@---------------------------------------------------
lsr r4, #1
bcc pchannel_empty
fjump2 mmUpdateChannel_T0
pchannel_empty:
mov r0, #1
add r10, r0
add r7, #MCH_SIZE
cmp r4, #0
bne pchannel_loop_first
b pchannel_loop_finished
@---------------------------------------------------
pchannel_loop_other:
@---------------------------------------------------
lsr r4, #1
bcc pchannel_empty2
#ifdef FOO_UC
bl mpp_Update_Channel
#else
fjump2 mmUpdateChannel_TN
#endif
pchannel_empty2:
mov r0, #1
add r10, r0
add r7, #MCH_SIZE
cmp r4, #0
bne pchannel_loop_other
pchannel_loop_finished:
@---------------------------------------------------
@ loop through active channels
@---------------------------------------------------
PROF_START
ldr r6,=mm_achannels
ldr r6, [r6]
@ldr r6,=mpp_achannels
mov r4, #0
@---------------------------------------------------
.mpp_pt_achn_loop:
@---------------------------------------------------
ldrb r0, [r6, #MCA_TYPE]
cmp r0, #ACHN_DISABLED
beq .mpp_pt_achn_disabled
ldr r0,=mpp_clayer
ldrb r0, [r0]
ldrb r1, [r6, #MCA_FLAGS]
lsr r1, #6
cmp r1, r0
bne .mpp_pt_achn_next
ldr r1,=mpp_vars
ldrb r0, [r6, #MCA_VOLUME]
strb r0, [r1, #MPV_AFVOL]
mov r0, #0
strh r0, [r1, #MPV_PANPLUS]
ldr r5, [r6, #MCA_PERIOD]
bl mpp_Update_ACHN
b .mpp_pt_achn_next
@---------------------------------------------------
.mpp_pt_achn_disabled:
@ mov r0, r4
@ bl mp_Mixer_StopChannel
@---------------------------------------------------
.mpp_pt_achn_next:
@---------------------------------------------------
ldrb r0, [r6, #MCA_FLAGS]
mov r1, #MCAF_UPDATED
bic r0, r1
strb r0, [r6, #MCA_FLAGS]
add r6, #MCA_SIZE
add r4, #1
ldr r0,=mm_num_ach
ldr r0,[r0]
cmp r4, r0
@ cmp r4, #MP_NCHANNELS
bne .mpp_pt_achn_loop
@---------------------------------------------------
PROF_END 6
ldr r1,=mppProcessTick_incframe
mov pc,r1
.pool
//-----------------------------------------------------------------------------
// TEXT Code
//-----------------------------------------------------------------------------
.TEXT
.THUMB
.ALIGN 2
//-----------------------------------------------------------------------------
/******************************************************************************
* mppProcessTick_incframe [[internal]]
******************************************************************************/
.thumb_func
mppProcessTick_incframe:
@---------------------------------------------------
@ update tick/row/position
@---------------------------------------------------
mov r5, r8 @ get tick#
ldrb r1, [r5, #MPL_TICK] @ ..
add r1, #1 @ increment
ldrb r2, [r5, #MPL_SPEED] @ compare with speed
cmp r1, r2 @ ..
blt .mppt_continuerow @ if less than, continue this row
ldrb r2, [r5, #MPL_FPATTDELAY]
cmp r2, #0
beq .mppt_nofpd
sub r2, #1
strb r2, [r5, #MPL_FPATTDELAY]
b .mppt_continuerow
.mppt_nofpd:
mov r1, #0 @ .. otherwise clear tick count
b .mppt_nextrow @ and advance to next row
.mppt_continuerow: @ continue current row:
strb r1, [r5, #MPL_TICK] @ save tick#
b .mppt_exit @ exit
.mppt_nextrow: @ advance row
ldrb r2, [r5, #MPL_PATTDELAY]
cmp r2, #0
beq .mppt_nopd
sub r2, #1
strb r2, [r5, #MPL_PATTDELAY]
beq .mppt_nopd
b .mppt_continuerow
.mppt_nopd:
strb r1, [r5, #MPL_TICK] @ save tick# (0)
ldrb r1, [r5, #MPL_PATTJUMP]
cmp r1, #255
beq .mppt_no_pj
mov r2, #255
strb r2, [r5, #MPL_PATTJUMP]
mov r0, r1
bl mpp_setposition
ldrb r1, [r5, #MPL_PATTJUMP_ROW]
cmp r1, #0
beq .mppt_pj_no_offset
mov r2, #0
strb r2, [r5, #MPL_PATTJUMP_ROW]
bl mpph_FastForward
.mppt_pj_no_offset:
b .mppt_exit
.mppt_no_pj:
mov r3, #MPL_PLOOP_JUMP
ldrb r1, [r5, r3]
cmp r1, #0
beq .mppt_no_ploop
mov r1, #0
strb r1, [r5, r3]
ldrb r1, [r5, #MPL_PLOOP_ROW]
strb r1, [r5, #MPL_ROW]
mov r3, #MPL_PLOOP_ADR
ldr r1, [r5, r3]
mov r3, #MPL_PATTREAD
str r1, [r5, r3]
b .mppt_exit
.mppt_no_ploop:
ldrb r1, [r5, #MPL_ROW] @ ..
add r1, #1 @ increment
ldrb r2, [r5, #MPL_NROWS] @
add r2, #1
cmp r1, r2 @ check with #rows for pattern
bne .mppt_continuepattern @ if !=, then continue playing this pattern
.mppt_nextposition: @ advance position
ldrb r0, [r5, #MPL_POSITION] @ increment position
add r0, #1
bl mpp_setposition
b .mppt_exit
.mppt_continuepattern:
strb r1, [r5, #MPL_ROW] @ save row count
.thumb_func
.mppt_exit:
@ switch to arm
ldr r0,=.mppt_exita
bx r0
.arm
.align 2
.mppt_exita:
ldmfd sp!, {r4-r10}
ldmfd sp!, {r0}
bx r0
.thumb
.pool
//-----------------------------------------------------------------------------
// IWRAM CODE
//-----------------------------------------------------------------------------
#ifdef USE_IWRAM
.SECTION ".iwram", "ax", %progbits
.ALIGN 2
#endif
//-----------------------------------------------------------------------------
/******************************************************************************
* mpp_Channel_NewNote()
*
* Process new note.
* Input r7 = pchannel address
******************************************************************************/
.global mpp_Channel_NewNote
.thumb_func
mpp_Channel_NewNote:
@ r7 = pchannel address
push {r4,lr}
ldrb r0, [r7, #MCH_INST] @ get instrument#
sub r0, #1
bcc .mppt_skipnna
bl mpp_Channel_GetACHN
cmp r6, #0
beq .mppt_alloc_channel
ldrb r0, [r7, #MCH_INST] @ get instrument#
sub r0, #1
mpp_InstrumentPointer
ldrb r1, [r7, #MCH_BFLAGS] @ fetch NNA
lsr r1, #6
beq .mppt_NNA_CUT @ skip if zero
ldrb r1, [r0, #C_MASI_DCT] @ otherwise check duplicate check type
lsl r1, #32-2
lsr r1, #32-2
lsl r1, #1 @ jump to mppt_DCT_TABLE[dct]
add r1, pc
mov pc, r1
.mppt_DCT_TABLE:
b .mppt_DCNA
b .mppt_DCT_NOTE
b .mppt_DCT_SAMP
b .mppt_DCT_INST
.mppt_DCT_NOTE: @ DCT note ---------------------
ldrb r1, [r7, #MCH_PNOTE] @ get pattern note
lsl r1, #1 @ translate to real note
add r1, #C_MASI_MAP @ with note/sample map
ldrb r1, [r0, r1] @ r1 = real note
ldrb r2, [r7, #MCH_NOTE] @ compare with last note
cmp r1, r2 @
beq .mppt_DCA @ equal? perform DCA
b .mppt_DCNA @ otherwise skip
.mppt_DCT_SAMP: @ DCT sample -------------------
// **WARNING: code not functional with new instrument table
ldrb r1, [r7, #MCH_PNOTE] @ get pattern note
lsl r1, #1 @ translate to sample#
add r1, #C_MASI_MAP+1 @ with note/sample map
ldrb r1, [r0, r1] @ r1 = sample#
ldrb r2, [r6, #MCA_SAMPLE] @ compare with achn's sample
cmp r1, r2 @
beq .mppt_DCA @ equal? perform DCA
b .mppt_DCNA @ otherwise skip
.mppt_DCT_INST: @ DCT instrument ---------------
ldrb r1, [r7, #MCH_INST] @ load instrument
ldrb r2, [r6, #MCA_INST] @ compare with active inst
cmp r1, r2 @
bne .mppt_DCNA @ not equal? skip DCA
.mppt_DCA: @ DUPLICATE CHECK ACTION -------
ldrb r1, [r0, #C_MASI_DCA] @ read type
cmp r1, #IT_DCA_CUT @ cut?
beq .mppt_NNA_CUT @ branch
cmp r1, #IT_DCA_OFF @ note-off?
beq .mppt_NNA_OFF @ branch
b .mppt_NNA_FADE @ note-fade otherwise
.mppt_DCNA:
ldrb r1, [r7, #MCH_BFLAGS]
lsr r1, #6 @ get NNA
lsl r1, #1 @ and jump to
add r1, pc @ NNA_TABLE[NNA]
mov pc, r1
.mppt_NNA_TABLE:
b .mppt_NNA_CUT
b .mppt_NNA_CONTINUE
b .mppt_NNA_OFF
b .mppt_NNA_FADE
@---------------------------------------------------------------------------------
.mppt_NNA_CUT:
@---------------------------------------------------------------------------------
#ifdef SYS_NDS // nds supports volume ramping
ldrb r1, [r6, #MCA_TYPE]
cmp r1, #0
BEQ .mppt_samechannel
mov r1, #ACHN_BACKGROUND
strb r1, [r6, #MCA_TYPE]
mov r1, #0
strb r1, [r6, #MCA_VOLUME]
b .mppt_NNA_FINISHED
#else
b .mppt_samechannel
#endif
@---------------------------------------------------------------------------------
.mppt_NNA_CONTINUE:
@---------------------------------------------------------------------------------
mov r1, #ACHN_BACKGROUND @ use different channel
strb r1, [r6, #MCA_TYPE] @ set active channel to "background"
b .mppt_NNA_FINISHED @ finished
@---------------------------------------------------------------------------------
.mppt_NNA_OFF:
@---------------------------------------------------------------------------------
ldrb r1, [r6, #MCA_FLAGS] @ clear KEYON in flags byte
mov r2, #MCAF_KEYON
bic r1, r2
strb r1, [r6, #MCA_FLAGS]
mov r1, #ACHN_BACKGROUND @ set type to "background"
strb r1, [r6, #MCA_TYPE]
b .mppt_NNA_FINISHED @ finished
@---------------------------------------------------------------------------------
.mppt_NNA_FADE:
@---------------------------------------------------------------------------------
ldrb r1, [r6, #MCA_FLAGS] @ set NOTE FADE in flags byte
mov r2, #MCAF_FADE
orr r1, r2
strb r1, [r6, #MCA_FLAGS]
mov r1, #ACHN_BACKGROUND @ set type to "background"
strb r1, [r6, #MCA_TYPE] @
.mppt_NNA_FINISHED:
.mppt_alloc_channel:
mov r4, r6
ldr r1,=mmAllocChannel
jump1 @ find new active channel
strb r0, [r7, #MCH_ALLOC] @ save number
#ifdef SYS_NDS
cmp r4, #0
beq .mppt_samechannel
mov r1, #MCA_SIZE @ copy data from previous channel
mul r0, r1 @ (for volume ramping wierdness)
ldr r1,=mm_achannels @
ldr r1,[r1] @
add r0, r1 @
@
mov r2, #MCA_SIZE/4
1: ldmia r4!, {r1}
stmia r0!, {r1}
sub r2, #1
bne 1b
/* ldr r1, [r4, #MCA_FADE] @
str r1, [r0, #MCA_FADE] @
ldr r1, [r4, #MCA_ENVC_PAN] @
str r1, [r0, #MCA_ENVC_PAN] @
ldr r1, [r4, #MCA_AVIB_DEP] @
str r1, [r0, #MCA_AVIB_DEP] @
ldrb r1, [r4, #MCA_FLAGS] @
strb r1, [r0, #MCA_FLAGS] @
ldrb r1, [r4, #MCA_VOLUME]
strb r1, [r0, #MCA_VOLUME]
ldrb r1, [r4, #MCA_PANNING]
strb r1, [r0, #MCA_PANNING]
ldrb r1, [r4, #MCA_SAMPLE]
strb r1, [r0, #MCA_SAMPLE]
ldrb r1, [r4, #MCA_INST]
strb r1, [r0, #MCA_INST]*/
#endif
.mppt_samechannel:
.mppt_skipnna:
pop {r4}
pop {r3}
bx r3
.pool
.align 2
.thumb_func
@------------------------------------------------------------------------------------------------------
mpp_Channel_GetACHN:
@------------------------------------------------------------------------------------------------------
@ gets the active channel pointer
@ and stores in r6
@ gives 0 if N/A
ldrb r0, [r7, #MCH_ALLOC]
cmp r0, #255
bge 1f
ldr r6,=mm_achannels
ldr r6,[r6]
mov r1, #MCA_SIZE
mul r0, r1
add r6, r0
bx lr
1: mov r6, #0
bx lr
.pool
.align 2
.thumb_func
@----------------------------------------------------------------------------------------------------
mpp_Update_ACHN:
@----------------------------------------------------------------------------------------------------
@ r5 = affected period
@ r6 = achannel address
push {lr} @ enter subroutine
@ check updated flag & exit if already updated
ldrb r0, [r6, #MCA_FLAGS]
mov r1, #MCAF_UPDATED
tst r0, r1
beq .mpp_achn_update
pop {pc}
@--------------------------------------------
.global mpp_Update_ACHN_notest
.thumb_func
@----------------------------------------------------------------------------------------------------
mpp_Update_ACHN_notest:
@----------------------------------------------------------------------------------------------------
push {lr}
.mpp_achn_update:
@------------------------------------------------------------------------
@ Envelope Processing
@------------------------------------------------------------------------
ldrb r0, [r6, #MCA_INST]
sub r0, #1
bCS 1f
b .mppt_achn_noinst
1: mpp_InstrumentPointer
@ get envelope flags
mov r1, r0
ldrb r2, [r1, #C_MASI_ENVFLAGS]
add r1, #C_MASI_ENVELOPES
lsr r2, #1 @ shift out volume envelope bit
bcc .mppt_no_volenv
ldrb r3, [r6, #MCA_FLAGS]
lsr r3, #6
bcs .mppt_achn_ve_enabled
ldrb r0, [r1]
add r1, r0
b .mppt_no_volenv
.mppt_achn_ve_enabled:
push {r1, r2}
ldrh r0, [r6, #MCA_ENVC_VOL]
mov r2, r1
ldrb r1, [r6, #MCA_ENVN_VOL]
bl mpph_ProcessEnvelope
strb r1, [r6, #MCA_ENVN_VOL]
strh r0, [r6, #MCA_ENVC_VOL]
mov r1, r3
cmp r2, #1
bne .mpph_volenv_notend
ldrb r0, [r6, #MCA_FLAGS]
mov r3, r8 @ stupid xm doesn't fade out at envelope end
ldrb r3, [r3, #MPL_FLAGS]
lsr r3, #C_FLAGS_XS
mov r3, #MCAF_ENVEND
bcs 1f
mov r3, #MCAF_ENVEND+MCAF_FADE
1:
orr r0, r3
strb r0, [r6, #MCA_FLAGS]
.mpph_volenv_notend:
cmp r2, #1
blt .mpph_volenv_normal
@ check keyon and turn on fade...
ldrb r0, [r6, #MCA_FLAGS]
mov r2, #MCAF_KEYON
tst r0, r2
bne .mpph_volenv_normal
.mpph_volenv_notefade:
mov r2, #MCAF_FADE
orr r0, r2
strb r0, [r6, #MCA_FLAGS]
.mpph_volenv_normal:
ldr r0,=mpp_vars
ldrb r2, [r0, #MPV_AFVOL]
mul r2, r1
lsr r2, #6+6
strb r2, [r0, #MPV_AFVOL]
pop {r1, r2}
ldrb r0, [r1]
add r1, r0
b .mppt_has_volenv
.mppt_no_volenv:
ldrb r0, [r6, #MCA_FLAGS]
mov r3, #MCAF_ENVEND
orr r0, r3
mov r3, #MCAF_KEYON
tst r0, r3
bne .mppt_has_volenv
mov r3, #MCAF_FADE
orr r0, r3
strb r0, [r6, #MCA_FLAGS]
mov r0, r8 @ check XM MODE and cut note
ldrb r0, [r0, #MPL_FLAGS]
lsr r0, #C_FLAGS_XS
bcc .mppt_has_volenv
mov r0, #0
strh r0, [r6, #MCA_FADE]
.mppt_has_volenv:
lsr r2, #1
bcc .mppt_no_panenv
push {r1, r2}
ldrh r0, [r6, #MCA_ENVC_PAN]
mov r2, r1
ldrb r1, [r6, #MCA_ENVN_PAN]
bl mpph_ProcessEnvelope
strb r1, [r6, #MCA_ENVN_PAN]
strh r0, [r6, #MCA_ENVC_PAN]
mov r1, r3
ldr r0,=mpp_vars
mov r3, #MPV_PANPLUS
ldrsh r2, [r0,r3]
lsr r1, #4
sub r1, #128
add r2, r1
strh r2, [r0,r3]
pop {r1, r2}
.mppt_no_panenv:
lsr r2, #1
bcc .mppt_no_pitchenv
ldrb r0, [r1, #C_MASIE_FILTER]
cmp r0, #0
bne .mppt_no_pitchenv
push {r1, r2}
ldrh r0, [r6, #MCA_ENVC_PIC]
mov r2, r1
ldrb r1, [r6, #MCA_ENVN_PIC]
bl mpph_ProcessEnvelope
strb r1, [r6, #MCA_ENVN_PIC]
strh r0, [r6, #MCA_ENVC_PIC]
mov r1, r3
lsr r1, #3
sub r1, #255
mov r0, r5
sub r1, #1
bmi .mppt_pitchenv_minus
#ifdef USE_IWRAM
ldr r2,=mpph_LinearPitchSlide_Up
jump2
#else
bl mpph_LinearPitchSlide_Up
#endif
b .mppt_pitchenv_plus
.mppt_pitchenv_minus:
neg r1, r1
#ifdef USE_IWRAM
ldr r2,=mpph_LinearPitchSlide_Down
jump2
#else
bl mpph_LinearPitchSlide_Down
#endif
.mppt_pitchenv_plus:
mov r5, r0
pop {r1, r2}
.mppt_no_pitchenv:
ldrb r0, [r6, #MCA_FLAGS]
mov r1, #MCAF_FADE
tst r0, r1
beq .mppt_achn_nofade
ldrb r0, [r6, #MCA_INST]
sub r0, #1
mpp_InstrumentPointer
ldrb r0, [r0, #C_MASI_FADE]
ldrh r1, [r6, #MCA_FADE]
sub r1, r0
bcs .mppt_achn_fadeout_clip
mov r1, #0
.mppt_achn_fadeout_clip:
strh r1, [r6, #MCA_FADE]
.mppt_achn_nofade:
.mppt_achn_keyon:
@----------------------------------------------------------------------------------
@ *** PROCESS AUTO VIBRATO
@----------------------------------------------------------------------------------
ldrb r0, [r6, #MCA_SAMPLE]
sub r0, #1
bcc .mppt_achn_nostart @ no sample!!
@bl mpp_SamplePointer
mpp_SamplePointer
ldrh r1, [r0, #C_MASS_VIR] @ get av-rate
cmp r1, #0 @ 0?
beq .mppt_av_disabled @ if 0 then its disabled
ldrh r2, [r6, #MCA_AVIB_DEP] @ get depth counter
add r2, r1 @ add rate
lsr r1, r2, #15 @ check for 15-bit overflow
beq .mppt_av_depclip @ ..
ldr r2,=32768 @ and clamp to 32768
.mppt_av_depclip:
strh r2, [r6, #MCA_AVIB_DEP] @ save depth counter
ldrb r1, [r0, #C_MASS_VID] @ get av-depth
mul r1, r2 @ multiply
ldrb r3, [r6, #MCA_AVIB_POS] @ get table position
ldrb r2, [r0, #C_MASS_VIS] @ get av-speed
add r3, r2 @ add to position
lsl r3, #32-8 @ wrap position to 0->255
lsr r3, #32-8 @ ..
strb r3, [r6, #MCA_AVIB_POS] @ save position
ldr r2,=mpp_TABLE_FineSineData @ get table pointer
ldrsb r2, [r2, r3] @ load table value at position
mul r2, r1 @ multiply with depth
asr r2, #23 @ shift value
bmi .mppt_av_minus @ and perform slide...
.mppt_av_plus: @ --slide up
mov r1, r2 @ r1 = slide value
mov r0, r5 @ r0 = frequency
#ifdef USE_IWRAM
fjump2 mpph_PitchSlide_Up
#else
bl mpph_PitchSlide_Up @ pitch slide
#endif
b .mppt_av_finished @
.mppt_av_minus: @ --slide down
neg r1, r2 @ r1 = slide value
mov r0, r5 @ r0 = frequency
#ifdef USE_IWRAM
ldr r2,=mpph_PitchSlide_Down
jump2
#else
bl mpph_PitchSlide_Down @ pitch slide
#endif
.mppt_av_finished:
mov r5, r0 @ affect frequency
.mppt_av_disabled:
@---------------------------------------------------------------------------------
.mppt_achn_noinst:
push {r4}
mov r0, #MIXER_CHN_SIZE
mul r4, r0
@ldr r0,=mp_channels
@ ldr r0,=mm_mixchannels
@ ldr r0,[r0]
GET_MIXCH r0
add r4, r0
@ *** UPDATE MIXING INFORMATION
ldrb r0, [r6, #MCA_FLAGS] @ read flags
mov r1, #MCAF_START @ test start bit
tst r0, r1 @ ..
beq .mppt_achn_nostart @
.mppt_achn_start: @ START NOTE
bic r0, r1 @ clear bit
strb r0, [r6, #MCA_FLAGS] @ save flags
ldrb r0, [r6, #MCA_SAMPLE] @ get sample #
sub r0, #1 @ ..
bcc .mppt_achn_nostart @ quit if invalid
@bl mpp_SamplePointer @ get sample address
mpp_SamplePointer
ldrh r3, [r0, #C_MASS_MSLID]
add r1,r3,#1 @ msl id == 0xFFFF?
lsr r1, #17
bcc .mppt_achn_msl_sample
.mppt_achn_direct_sample: @ then sample follows
add r0, #12
//------------------------------------------------
#ifdef SYS_GBA
// ldr r1, [r0,#C_SAMPLE_LEN] @ setup mixer (GBA)
// lsl r1, #MP_SAMPFRAC
// str r1, [r4,#MIXER_CHN_LEN]
// ldr r1, [r0,#C_SAMPLE_LOOP]
// str r1, [r4,#MIXER_CHN_LOOP]
add r0, #C_SAMPLE_DATA
str r0, [r4,#MIXER_CHN_SRC]
#else
//-------------------------------------------
ldr r1,=0x2000000
sub r0, r1
str r0, [r4, #MIXER_CHN_SAMP]
ldrb r1, [r4, #MIXER_CHN_CNT]
mov r0, #MIXER_CF_START
orr r1, r0
strb r1, [r4, #MIXER_CHN_CNT]
#endif
//-------------------
b .mppt_achn_gotsample
.mppt_achn_msl_sample: @ otherwise get from solution
#ifdef SYS_GBA
ldr r2,=mp_solution
ldr r2, [r2]
mov r1, r2
add r1, #12
lsl r3, #2
ldr r1, [r1, r3]
add r1, #8
add r0, r1, r2
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ NOTICE, USE LDM HERE
// ldr r1, [r0,#C_SAMPLE_LEN] @ setup mixer (GBA)
// lsl r1, #MP_SAMPFRAC
// str r1, [r4,#MIXER_CHN_LEN]
// ldr r1, [r0,#C_SAMPLE_LOOP]
// str r1, [r4,#MIXER_CHN_LOOP]
add r0, #C_SAMPLE_DATA
str r0, [r4,#MIXER_CHN_SRC]
#endif
#ifdef SYS_NDS
ldr r2,=mmSampleBank @ get samplebank pointer
ldr r2, [r2]
lsl r3, #2 @ add msl_id *4
ldr r1, [r2, r3]
lsl r1, #8 @ mask out counter value
lsr r1, #8
add r1, #8
str r1, [r4,#MIXER_CHN_SAMP]
ldrb r1, [r4,#MIXER_CHN_CNT] // read control **CNT was cleared, no need to read it
mov r0, #MIXER_CF_START // set start bit
orr r1, r0
strb r1, [r4,#MIXER_CHN_CNT] // save control
#endif
.mppt_achn_gotsample:
ldr r1,=mpp_vars
ldrb r1, [r1, #MPV_SAMPOFF]
#ifdef SYS_GBA
lsl r1, #MP_SAMPFRAC+8
str r1, [r4, #MIXER_CHN_READ]
#else
str r1, [r4, #MIXER_CHN_READ]
#endif
.mppt_achn_nostart:
@ set pitch
ldrb r0, [r6, #MCA_SAMPLE] @ get sample#
sub r0, #1 @ ..
bcc .mppt_achn_setvolumeA
@bl mpp_SamplePointer @ quit if invalid
mpp_SamplePointer
push {r0}
mov r1, r8
ldrb r1, [r1, #MPL_FLAGS]
lsr r1, #C_FLAGS_SS
bcc .mppt_achn_amigafreqs
.mppt_achn_linearfreqs:
ldrh r0, [r0, #C_MASS_FREQ] @ get C5SPEED
LSL R0, #2
lsr r1, r5, #8 @ do some stuff...
mul r1, r0 @ ... period * freq?
lsr r1, #8
ldr r0,=mpp_clayer
ldrb r0, [r0]
cmp r0, #0
bne 1f
ldr r0,=mm_masterpitch
ldr r0, [r0]
mul r1, r0
lsr r1, #10
1:
#ifdef SYS_GBA
// ldr r0,=mm_freqscalar
// ldr r0, [r0]
ldr r0,=(4096*65536)/15768
mul r0, r1
lsr r0, #16
str r0, [r4, #MIXER_CHN_FREQ]
#else
ldr r0,=MIXER_SCALE
mul r0, r1
lsr r0, #16+1
strh r0, [r4, #MIXER_CHN_FREQ]
//strh r1, [r4, #MIXER_CHN_FREQ]
#endif
b .mppt_achn_setvolume
.mppt_achn_amigafreqs:
ldr r0,=MOD_FREQ_DIVIDER_PAL
movs r1, r5
beq .mppt_achn_setvolume @ 0 is a bad period
swi SWI_DIVIDE
ldr r1,=mpp_clayer
ldrb r1, [r1]
cmp r1, #0
bne 1f
ldr r1,=mm_masterpitch
ldr r1, [r1]
mul r0, r1
lsr r0, #10
1:
#ifdef SYS_GBA
// ldr r1,=mm_freqscalar
// ldr r1,[r1]
ldr r1,=(4096*65536)/15768
mul r0, r1
lsr r0, #16
str r0, [r4, #MIXER_CHN_FREQ]
#else
// mov r1, r0
// ldr r0,=16756991 @ calculate ds mixer timing
// swi SWI_DIVIDE
// neg r0,r0
//lsr r0, #5
ldr r1,=MIXER_SCALE
mul r0, r1
lsr r0, #16+1
strh r0, [r4, #MIXER_CHN_FREQ]
#endif
@----------------------------------------------------------------------------------------------------
.mppt_achn_setvolume:
@----------------------------------------------------------------------------------------------------
@ set volume
pop {r0}
@ <-- stepped oct 28, 3:27pm
ldrb r3, [r0, #C_MASS_GV] @ SV, 6-bit
ldrb r0, [r6, #MCA_INST]
sub r0, #1
bcs 1f
.thumb_func
.mppt_achn_setvolumeA:
mov r1, #0
b .mppt_achn_badinstrument
1:
mpp_InstrumentPointer
ldrb r0, [r0, #C_MASI_GVOL] @ IV, 7-bit
mul r3, r0
ldr r1,=mpp_vars
ldrb r0, [r1, #MPV_AFVOL] @ ((CV*VOL)/32*VEV/64) 7-bit
mul r3, r0
mov r1, r8 @ get global vollume
ldrb r0, [r1, #MPL_FLAGS]
lsr r0, #4
ldrb r0, [r1, #MPL_GV] @ .. 7-bit
bcc 1f
lsl r0, #1 @ xm mode global volume is only 0->64, shift to 0->128
1: mul r3, r0 @ multiply
lsr r3, #10
ldrh r0, [r6, #MCA_FADE]
mul r3, r0
lsr r3, r3, #10
mov r0, r8
mov r1, #MPL_VOLUME
ldrh r0, [r0, r1]
mul r3, r0
//------------------------------------------------
#ifdef SYS_NDS
lsr r1, r3, #19-3-5 ///#19-3 (new 16-bit levels!)
ldr r3,=65535 //2047
cmp r1, r3 @ clip values over 255
blt 1f
mov r1, r3
1:
.mppt_achn_badinstrument:
// lsr r3, r1, #3 (new 16-bit levels!)
lsr r3, r1, #8
strb r3, [r6, #MCA_FVOL]
#else
lsr r1, r3, #19
cmp r1, #255 @ clip values over 255
blt 1f
mov r1, #255
1:
.mppt_achn_badinstrument:
strb r1, [r6, #MCA_FVOL]
#endif
cmp r1, #0
bne .mppt_achn_audible
#ifdef SYS_NDS // nds has volume ramping!
ldrb r3, [r6, #MCA_TYPE]
cmp r3, #ACHN_BACKGROUND
bne 1f
ldrb r3, [r6, #MCA_VOLUME]
cmp r3, #0
bne 1f
ldrh r3, [r4, #MIXER_CHN_CVOL]
cmp r3, #0
beq .mppt_achn_not_audible
#endif
1: ldrb r3, [r6, #MCA_FLAGS]
mov r2, #MCAF_ENVEND
tst r3, r2
beq .mppt_achn_audible
mov r2, #MCAF_KEYON
tst r3, r2
bne .mppt_achn_audible
// #ifdef SYS_NDS
// ldrh r3, [r4, #MIXER_CHN_CVOL] // nds has volume ramping!!
// cmp r3, #0
// bne .mppt_achn_audible
// #endif
.mppt_achn_not_audible:
@ STOP CHANNEL
#ifdef SYS_GBA
ldr r0,=1<<31
str r0,[r4,#MIXER_CHN_SRC] @ stop mixer channel
#else
mov r0,#0
str r0,[r4,#MIXER_CHN_SAMP] @ stop mixer channel
#endif
ldrb r3, [r6, #MCA_TYPE]
cmp r3, #ACHN_FOREGROUND
bne .mpp_achn_noparent
ldrb r1, [r6, #MCA_PARENT]
mov r3, #MCH_SIZE
mul r1, r3
ldr r0,=mpp_channels
ldr r0, [r0]
add r0, r1
mov r1, #255
strb r1, [r0, #MCH_ALLOC]
.mpp_achn_noparent:
mov r1, #ACHN_DISABLED
strb r1, [r6, #MCA_TYPE]
b .mpp_achn_updated
.mppt_achn_audible:
#ifdef SYS_NDS
strh r1, [r4, #MIXER_CHN_VOL]
#else
strb r1, [r4, #MIXER_CHN_VOL]
#endif
#ifdef SYS_GBA // check if mixer channel has ended
ldr r0, [r4, #MIXER_CHN_SRC]
asr r0, #31
beq 1f
#else
ldr r0, [r4, #MIXER_CHN_SAMP]
lsl r0, #8
bne 1f
#endif
ldrb r3, [r6, #MCA_TYPE]
cmp r3, #ACHN_FOREGROUND
bne 2f
ldrb r1, [r6, #MCA_PARENT] // stop channel if channel ended
mov r3, #MCH_SIZE
mul r1, r3
ldr r0,=mpp_channels
ldr r0, [r0]
add r0, r1
mov r1, #255
strb r1, [r0, #MCH_ALLOC]
2:
#ifdef SYS_GBA
ldr r0,=1<<31
str r0,[r4,#MIXER_CHN_SRC] @ stop mixer channel
#else
mov r0,#0
str r0,[r4,#MIXER_CHN_SAMP] @ stop mixer channel
#endif
mov r1, #ACHN_DISABLED
strb r1, [r6, #MCA_TYPE]
b .mpp_achn_updated
@ set panning
1: ldr r1,=mpp_vars
mov r3, #MPV_PANPLUS
ldrsh r0, [r1,r3]
ldrb r1, [r6, #MCA_PANNING]
add r1, r0
cmp r1, #0
bge .mpp_achn_clippan1
mov r1, #0
.mpp_achn_clippan1:
cmp r1, #255
ble .mpp_achn_clippan2
mov r1, #255
.mpp_achn_clippan2:
#ifdef SYS_NDS
lsr r1, #1
ldrb r0, [r4, #MIXER_CHN_CNT]
lsr r0, #7
lsl r0, #7
orr r0, r1
strb r0, [r4, #MIXER_CHN_CNT]
#endif
#ifdef SYS_GBA
strb r1, [r4, #MIXER_CHN_PAN]
#endif
.mpp_achn_updated:
pop {r4}
pop {r0}
bx r0
//pop {pc} @ exit
.pool
.align 2
.thumb_func
@-------------------------------------------------------------------------
mpph_ProcessEnvelope: @ params={count,node,address}
@-------------------------------------------------------------------------
@ processes the envelope at <address>
@ returns:
@ r0=count
@ r1=node
@ r2=exit_code
@ r3=value*64
push {r4,r5}
@ get node and base
lsl r4, r1, #2
add r4, #C_MASIE_NODES
add r4, r2
ldrh r3, [r4, #2]
lsl r3, #32-7
lsr r3, #32-7-6
@ check for zero count
cmp r0, #0
bne .mpph_pe_between
.mpph_pe_new:
@ process envelope loop
ldrb r5, [r2, #C_MASIE_LEND]
cmp r1, r5
bne 1f
ldrb r1, [r2, #C_MASIE_LSTART]
mov r2, #2
b .mpph_pe_exit
@ process envelope sustain loop
1: ldrb r5, [r6, #MCA_FLAGS]
lsr r5, #1 @ locked
bcc 1f
ldrb r5, [r2, #C_MASIE_SEND]
cmp r1, r5
bne 1f
ldrb r1, [r2, #C_MASIE_SSTART]
mov r2, #0
b .mpph_pe_exit
@ check for end
1: ldrb r5, [r2, #C_MASIE_NODEC]
sub r5, #1
cmp r1, r5
bne .mpph_count
mov r2, #2
b .mpph_pe_exit
.mpph_pe_between:
@ delta * count
@ formula : y = base*2^6 + -----------------
@ 2^3
mov r5, #0
ldrsh r5, [r4,r5]
mul r5, r0
asr r5, #3
add r3, r5
.mpph_count:
@ increment count and check if == read count
add r0, #1
ldrh r5, [r4, #2]
lsr r5, #7
cmp r0, r5
bne .mpph_pe_exit
@ increment node and reset counter
mov r0, #0
add r1, #1
.mpph_pe_exit:
pop {r4,r5}
bx lr
.pool
/*
.align 2
.thumb_func
@--------------------------------------------------------------------------------------------
mpp_Alloc_Channel:
@--------------------------------------------------------------------------------------------
@ find a channel to use
@ returns invalid channel if none available
push {r4,r5} @ preserve reg(s)
ldr r5,=mm_ch_mask
ldr r5, [r5]
@ldr r1,=mpp_achannels @ load pointer
ldr r1,=mm_achannels
ldr r1,[r1]
mov r0, #0 @ load counter
mov r2, #255 @ r2 = MAXVOL+1 (highest)
add r2, #1
mov r3, #255 @ r3 = 255 (none found)
b .mppac_start
.mppac_next:
add r1, #MCA_SIZE @ change pointer
add r0, #1 @ count
.mppac_start:
lsr r5, #1
bcs .mppac_check
bne .mppac_next
.mppac_end:
mov r0, r3 @ if no disabled channels are found, use lowest volume channel
.mppac_found:
pop {r4,r5}
bx lr
.mppac_check:
ldrb r4, [r1, #MCA_TYPE] @ check active channel type
cmp r4, #ACHN_DISABLED @ disabled?
beq .mppac_found @ if so, use this channel
cmp r4, #ACHN_BACKGROUND @ check if its a background channel
bne .mppac_next
ldrb r4, [r1, #MCA_FVOL] @ compare volumes
cmp r4, r2 @
bge .mppac_next
mov r3, r0 @ save channel#
mov r2, r4 @ and volume
b .mppac_next
*/
.pool
@........................................................................................
.thumb_func
mpp_PatternPointer:
mov r1, r8
ldr r2,[r1,#MPL_SONGADR]
ldr r1,[r1,#MPL_PATTTABLE]
lsl r0, #2
ldr r0,[r1,r0]
add r0, r2
bx lr
.pool
#ifdef FOO_UC
.align 2
.thumb_func
mpp_GetPeriod:
@ r0 = note
@ r2 = tuning
@ CLOBBERS R1,R3
@ RETURN
@ r0 = IT/S3M PERIOD
mov r1, r8
ldrb r1, [r1, #MPL_FLAGS]
lsr r1, #C_FLAGS_SS
bcs .mpp_gp_linear
.mpp_gp_amiga:
mov r3, r0
ldr r0,=note_table_mod
ldrb r1, [r0, r3]
sub r0, #3*10
lsr r3, #2
ldrb r0, [r0, r3]
@ r0 = octave
@ r1 = note
lsl r1, #1
ldr r3,=ST3_FREQTABLE
ldrh r1, [r3, r1]
ldr r3,=133808
mul r1, r3
lsr r1, r0
lsr r0, r1, #3
mov r1, r2
swi SWI_DIVIDE
lsl r0, #3
bx lr
.mpp_gp_linear:
ldr r1,=IT_PitchTable
lsl r0, #2
ldr r0, [r1, r0]
bx lr
#endif
@=============================================================================
@ EFFECT MEMORY
@=============================================================================
.text
mpp_effect_memmap_xm:
.byte 0,0,0,0,2,3,4,0,0,5,0,6,7,0,0,8,9,10,11,0,0,0,0,12,0,0,0,0,0,0,13
@ /,A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,Q, R, S,T,U,V,W, X,Y,Z,0,1,2,3
.equ MPP_XM_VFX_MEM_VS, 12 @ $ud
.equ MPP_XM_VFX_MEM_FVS, 13 @ $ud
.equ MPP_XM_VFX_MEM_GLIS, 14 @ $0x
.equ MPP_XM_VFX_MEM_PANSL, 7 @ $lr
mpp_effect_memmap_it:
.byte 0,0,0,0,2,3,3,0,0,4,5,2,2,0,6,7,8,9,10,11,12,0,0,13,0,14,0
@ /,A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,Q,R, S, T, U,V,W, X,Y, Z
mpp_veffect_memmap_it:
.equ MPP_IT_VFX_MEM, 14
.equ MPP_GLIS_MEM, 0
.equ MPP_IT_PORTAMEM, 2
@ 0 means custom behavior, or disabled
.align 2
.thumb_func
@-----------------------------------------------------------------------------
mpp_Channel_ExchangeMemory:
@-----------------------------------------------------------------------------
@ r0 = effect#
@ r1 = param
@ check flags for XM mode
mov r2, r8
ldrb r2, [r2, #MPL_FLAGS]
lsr r2, #C_FLAGS_XS
bcs 1f
@ IT effects
ldr r2,=mpp_effect_memmap_it
b 2f
1:
@ XM effects
ldr r2,=mpp_effect_memmap_xm
2: ldrb r2, [r2, r0]
sub r2, #1
bcc 3f
@ if param=0 then load memory value, otherwise save param to memory
add r2, #MCH_MEMORY
cmp r1, #0
bne 1f
ldrb r1, [r7, r2]
strb r1, [r7, #MCH_PARAM]
1: strb r1, [r7, r2]
3: bx lr
@----------------------------------------------------------
mpp_Channel_ExchangeGxx:
@----------------------------------------------------------
@ r1 = param
/******************************************************************************
*
* Volume Commands
*
******************************************************************************/
/******************************************************************************
* mpp_Process_VolumeCommand()
*
* Process volume command
******************************************************************************/
.global mpp_Process_VolumeCommand
.thumb_func
mpp_Process_VolumeCommand:
mov r0, r8
ldrb r2, [r0, #MPL_TICK]
ldr r0, [r0, #MPL_SONGADR]
ldrb r0, [r0, #C_MAS_FLAGS]
lsr r0, #4
ldrb r0, [r7, #MCH_VOLCMD]
bcc .mppuv_it
b .mppuv_xm
.mppuv_it:
@ determine which command to use
cmp r0, #64
ble .mppuv_setvol
cmp r0, #84
ble .mppuv_fvol
cmp r0, #104
ble .mppuv_volslide
cmp r0, #124
ble .mppuv_porta
cmp r0, #192
ble .mppuv_panning
cmp r0, #202
ble .mppuv_glissando
cmp r0, #212
ble .mppuv_vibrato
.mppuv_exit1:
bx lr
.align 2
@-----------------------------------------------------------------------------------
.mppuv_setvol: @ SET VOLUME
@-----------------------------------------------------------------------------------
@ sets volume on tick0
cmp r2, #0
bne .mppuv_setvol_exit
strb r0, [r7, #MCH_VOLUME]
.mppuv_setvol_exit:
bx lr @ exit
.align 2
@-----------------------------------------------------------------------------------
.mppuv_fvol: @ FINE VOLUME SLIDE UP/DOWN
@-----------------------------------------------------------------------------------
cmp r2, #0 @ only slide on tick0
bne .mppuv_exit1 @ ..
ldrb r1, [r7, #MCH_VOLUME] @ load channel volume
mov r2, #MCH_MEMORY+MPP_IT_VFX_MEM
cmp r0, #75 @ check slide direction
bge .mppuv_fvoldown @ jump to slide down if value is 75+ (75-84 is slide down)
.mppuv_fvolup: @ ------ slide up ----------
sub r0, #65 @ 65->74 , 0->9
.mppuv_volup: @ ** entry for volume slide up
bne 1f @ is value 0?
ldrb r0, [r7, r2] @ then fetch value from memory
1: strb r0, [r7, r2] @ save value
.mppuv_volupA:
add r1, r0 @ add to volume
cmp r1, #64 @ clamp to 0->64
blt .mppuv_fvol_exit @ ..
mov r1, #64 @ ..
b .mppuv_fvol_exit @ ..
.mppuv_fvoldown: @ ------ slide down --------
sub r0, #75 @ 75->84 , 0->9
.mppuv_voldown: @ ** entry for volume slide down
bne 1f @ is value 0?
ldrb r0, [r7, r2] @ then fetch value from memory
1: strb r0, [r7, r2] @ save value
.mppuv_voldownA:
sub r1, r0 @ subtract from volume
bcs .mppuv_fvol_exit @ check overflow and clamp
mov r1, #0 @ ..
.mppuv_fvol_exit: @ ..
strb r1, [r7, #MCH_VOLUME] @ store volume
.mppuv_exit2:
bx lr @ exit function
.align 2
@----------------------------------------------------------------------------------
.mppuv_volslide: @ VOLUME SLIDE UP/DOWN
@----------------------------------------------------------------------------------
cmp r2, #0 @ only slide on other ticks
beq .mppuv_exit1 @ ..
ldrb r1, [r7, #MCH_VOLUME] @ get volume
cmp r0, #95 @ check slide direction
bge .mppuv_vs_down
.mppuv_vs_up: @ slide up...
mov r2, #MCH_MEMORY+MPP_IT_VFX_MEM
sub r0, #85 @ 85->94 , 0->9
b .mppuv_volup @ branch to function (use fvol code)
.mppuv_vs_down: @ slide down...
mov r2, #MCH_MEMORY+MPP_IT_VFX_MEM
sub r0, #95 @ 95->104 , 0->9
b .mppuv_voldown @ branch to function (use fvol code)
.align 2
@---------------------------------------------------------------------------------------
.mppuv_porta: @ PORTAMENTO UP/DOWN
@---------------------------------------------------------------------------------------
cmp r2, #0 @ only slide on other ticks
beq .mppuv_exit2
push {lr} @ save return address
mov r1, r0 @ get period value
mov r0, #MCH_PERIOD
ldr r0, [r7, r0]
cmp r1, #115 @ check slide direction
bge .mppuv_porta_up
.mppuv_porta_down:
sub r1, #105 @ map value 0->9
lsl r1, #2 @ volume command slides are
bne 1f
ldrb r1, [r7, #MCH_MEMORY+MPP_IT_PORTAMEM]
1: strb r1, [r7, #MCH_MEMORY+MPP_IT_PORTAMEM]
bl mpph_PitchSlide_Down @ equal to normal slides *4
b .mppuv_porta_set
.mppuv_porta_up:
sub r1, #115 @ slide up...
lsl r1, #2
bne 1f
ldrb r1, [r7, #MCH_MEMORY+MPP_IT_PORTAMEM]
1: strb r1, [r7, #MCH_MEMORY+MPP_IT_PORTAMEM]
bl mpph_PitchSlide_Up
.mppuv_porta_set:
mov r2, #MCH_PERIOD @ store new period
ldr r1, [r7, r2]
str r0, [r7, r2]
sub r0, r1 @ and edit temp period
add r5, r0
pop {r0}
bx r0
// pop {pc} @ exit
.align 2
@---------------------------------------------------------------------------------------
.mppuv_panning: @ SET PANNING
@---------------------------------------------------------------------------------------
cmp r2, #0 @ only set on tick 0
bne .mppuv_exit1 @ ..
sub r0, #128 @ map to 0->64
lsl r0, #2
cmp r0, #255
blt .mppuv_p_store
mov r0, #255
.mppuv_p_store:
strb r0, [r7, #MCH_PANNING] @ save to active channel
.mppuv_p_exit:
bx lr @ exit
.align 2
@---------------------------------------------------------------------------------------
.mppuv_glissando: @ GLISSANDO
@---------------------------------------------------------------------------------------
cmp r2, #0
beq .mppuv_p_exit
sub r0, #193
ldr r1,=vcmd_glissando_table
ldrb r0, [r1, r0]
mov r1, r8
ldrb r1, [r1, #MPL_FLAGS]
lsr r1, #C_FLAGS_GS
bcs 2f
@ single gxx
cmp r0, #0
beq 1f
ldrb r0, [r7, #MCH_MEMORY+MPP_GLIS_MEM]
1: strb r0, [r7, #MCH_MEMORY+MPP_GLIS_MEM]
b .mppe_glis_ot
2: @ shared gxx
cmp r0, #0
beq 1f
ldrb r0, [r7, #MCH_MEMORY+MPP_IT_PORTAMEM]
1: strb r0, [r7, #MCH_MEMORY+MPP_IT_PORTAMEM]
strb r0, [r7, #MCH_MEMORY+MPP_GLIS_MEM]
b .mppe_glis_ot
.pool
vcmd_glissando_table:
.byte 0,1,4,8,16,32,64,96,128,255
.align 2
@---------------------------------------------------------------------------------------
.mppuv_vibrato: @ VIBRATO (SPEED)
@---------------------------------------------------------------------------------------
@ vibrato... sets speed
cmp r2, #0
beq .mppuv_vib_exit
sub r0, #203
beq 1f
lsl r0, #2
strb r0, [r7, #MCH_VIBSPD]
1: b mppe_DoVibrato
.mppuv_vib_exit:
bx lr
/******************************************************************************
*
* XM Volume Commands
*
******************************************************************************/
.align 2
.thumb_func
@---------------------------------------------------------------------------------------
.mppuv_xm:
@---------------------------------------------------------------------------------------
@ determine command type
cmp r0, #0 @ 0 = none
beq .mppuv_exit4
cmp r0, #0x50
ble .mppuv_xm_setvol
cmp r0, #0x80
blt .mppuv_xm_volslide
cmp r0, #0xA0
blt .mppuv_xm_fvolslide
cmp r0, #0xC0
blt .mppuv_xm_vibrato
cmp r0, #0xD0
blt .mppuv_xm_panning
cmp r0, #0xF0
blt .mppuv_xm_panslide
b .mppuv_xm_toneporta
.align 2
.thumb_func
@----------------------------------------------------------------------------------------
.mppuv_xm_setvol: @ Set Volume
@----------------------------------------------------------------------------------------
cmp R2, #0
bne .mppuv_exit4
sub r0, #0x10
strb r0, [r7, #MCH_VOLUME]
.mppuv_exit4:
bx lr
.align 2
.thumb_func
@----------------------------------------------------------------------------------------
.mppuv_xm_volslide: @ Volume Slide
@----------------------------------------------------------------------------------------
cmp r2, #0
beq .mppuv_exit2
ldrb r1, [r7, #MCH_VOLUME]
mov r3, #MCH_MEMORY+MPP_XM_VFX_MEM_VS
ldrb r2, [r7, r3]
cmp r0, #0x70
bge .mppuv_xm_volslide_up
sub r0, #0x60
.mppuv_xm_volslide_dn_check:
bne 1f
mov r0, r2
lsl r0, #32-4
lsr r0, #32-4
b 2f
1: lsr r2, #4
lsl r2, #4
orr r2, r0
strb r2, [r7, r3]
2: b .mppuv_voldownA
.mppuv_xm_volslide_up:
sub r0, #0x70
.mppuv_xm_volslide_up_check:
bne 1f
mov r0, r2
lsr r0, #4
b 2f
1: lsl r2, #32-4
lsr r2, #32-4
lsl r0, #4
orr r2, r0
lsr r0, #4
strb r2, [r7, r3]
2: b .mppuv_volupA
.align 2
.thumb_func
@----------------------------------------------------------------------------------------
.mppuv_xm_fvolslide: @ Fine Volume Slide
@----------------------------------------------------------------------------------------
cmp r2, #0
bne .mppuv_exit4
ldrb r1, [r7, #MCH_VOLUME]
mov r3, #MCH_MEMORY+MPP_XM_VFX_MEM_FVS
ldrb r2, [r7, r3]
cmp r0, #0x90
bge .mppuv_xm_fvolslide_up
sub r0, #0x80
b .mppuv_xm_volslide_dn_check
.mppuv_xm_fvolslide_up:
sub r0, #0x90
b .mppuv_xm_volslide_up_check
.align 2
.thumb_func
@----------------------------------------------------------------------------------------
.mppuv_xm_vibrato: @ Vibrato
@----------------------------------------------------------------------------------------
@ xm vibrato
@ sets speed or depth
cmp r2, #0
beq .mppuv_xm_vibexit
cmp r0, #0xB0
bge .mppuv_xm_vibdepth
.mppuv_xm_vibspd:
sub r0, #0xA0
lsl r0, #2
beq 1f
strb r0, [r7, #MCH_VIBSPD]
1: b mppe_DoVibrato
.mppuv_xm_vibdepth:
sub r0, #0xB0
lsl r0, #3
beq 1f
strb r0, [r7, #MCH_VIBDEP]
1: b mppe_DoVibrato
.mppuv_xm_vibexit:
bx lr
.align 2
.thumb_func
@----------------------------------------------------------------------------------------
.mppuv_xm_panning: @ Panning
@----------------------------------------------------------------------------------------
cmp r2, #0
bne .mppuv_exit3
sub r0, #0xC0
lsl r0, #4
cmp r0, #240
beq .mppuv_xm_panhack
strb r0, [r7, #MCH_PANNING]
bx lr
.mppuv_xm_panhack:
mov r0, #255
strb r0, [r7, #MCH_PANNING]
.mppuv_exit3:
bx lr
.align 2
.thumb_func
@----------------------------------------------------------------------------------------
.mppuv_xm_panslide: @ Panning Slide
@----------------------------------------------------------------------------------------
cmp r2, #0
beq .mppuv_exit3
ldrb r2, [r7, #MCH_PANNING]
ldrb r3, [r7, #MCH_MEMORY + MPP_XM_VFX_MEM_PANSL]
cmp r0, #0xE0
bge .mppuv_xm_panslide_right
sub r0, #0xD0
bne 1f
lsr r0, r3, #4
b 2f
1: lsl r3, #32-4
lsr r3, #32-4
lsl r0, #4
orr r3, r0
lsr r0, #4
strb r3, [r7, #MCH_MEMORY + MPP_XM_VFX_MEM_PANSL]
2: lsl r0, #2
sub r2, r0
bcs .mppuv_xm_panslide_set
mov r2, #0
b .mppuv_xm_panslide_set
.mppuv_xm_panslide_right:
sub r0, #0xE0
bne 1f
lsl r0, r3, #32-4
lsr r0, #32-4
b 2f
1: lsr r3, #4
lsl r3, #4
orr r3, r0
strb r3, [r7, #MCH_MEMORY + MPP_XM_VFX_MEM_PANSL]
2: lsl r0, #2
add r2, r0
cmp r2, #255
blt .mppuv_xm_panslide_set
mov r2, #255
.mppuv_xm_panslide_set:
strb r2, [r7, #MCH_PANNING]
bx lr
.align 2
.thumb_func
@-------------------------------------------------------------------------------------
.mppuv_xm_toneporta: @ Glissando
@-------------------------------------------------------------------------------------
@ glissando...
@ on nonzero ticks, do a regular glissando slide at speed * 16
cmp r2, #0
beq 1f
sub r0, #0xF0
lsl r0, #4
beq 2f
mov r1, #MCH_MEMORY+MPP_XM_VFX_MEM_GLIS
strb r0, [r7, r1]
2: ldrb r0, [r7, r1]
mov r1, r0
b .mppe_glis_backdoor
1: bx lr
/******************************************************************************
*
* Module Effects
*
******************************************************************************/
/******************************************************************************
* mpp_ProcessEffect()
*
* Process pattern effect.
******************************************************************************/
.global mpp_Process_Effect
.thumb_func
mpp_Process_Effect:
push {lr}
ldrb r0, [r7, #MCH_EFFECT] @ get effect#
ldrb r1, [r7, #MCH_PARAM] @ r1 = param
bl mpp_Channel_ExchangeMemory
lsl r0, #1
pop {r2}
mov lr, r2
mov r2, r8
ldrb r2, [r2, #MPL_TICK] @ r2 = tick#
cmp r2, #0 @ Z flag = tick0 :)
add r0, pc
mov pc, r0
b mppe_todo
b mppe_SetSpeed
b mppe_PositionJump
b mppe_PatternBreak
b mppe_VolumeSlide
b mppe_Portamento
b mppe_Portamento
b mppe_Glissando
b mppe_Vibrato
b mppe_todo
b mppe_Arpeggio
b mppe_VibratoVolume
b mppe_PortaVolume
b mppe_ChannelVolume
b mppe_ChannelVolumeSlide
b mppe_SampleOffset
b mppe_todo
b mppe_Retrigger
b mppe_Tremolo @ tremolo
b mppe_Extended
b mppe_SetTempo
b mppe_FineVibrato
b mppe_SetGlobalVolume
b mppe_GlobalVolumeSlide
b mppe_SetPanning
b mppe_Panbrello
b mppe_ZXX
b mppe_SetVolume
b mppe_KeyOff
b mppe_EnvelopePos
b mppe_OldTremor
.pool
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_SetSpeed: @ EFFECT Axy: SET SPEED
@---------------------------------------------------------------------------------
bne .mppe_ss_exit @ dont set on nonzero ticks
cmp r1, #0
beq .mppe_ss_exit
mov r0, r8
strb r1, [r0, #MPL_SPEED]
.mppe_ss_exit:
.thumb_func
mppe_todo:
bx lr @ exit
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_PositionJump: @ EFFECT Bxy: SET POSITION
@---------------------------------------------------------------------------------
bne .mppe_pj_exit @ skip nonzero ticks
mov r0, r8
strb r1, [r0, #MPL_PATTJUMP]
.mppe_pj_exit:
bx lr @ exit
.pool
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_PatternBreak: @ EFFECT Cxy: PATTERN BREAK
@---------------------------------------------------------------------------------
bne .mppe_pb_exit @ skip nonzero ticks
mov r0, r8 @ get variables
strb r1, [r0, #MPL_PATTJUMP_ROW] @ save param to row value
ldrb r1, [r0, #MPL_PATTJUMP] @ check if pattjump=empty
cmp r1, #255 @ 255=empty
bne .mppe_pb_exit @ ...
ldrb r1, [r0, #MPL_POSITION] @ if empty, set pattjump=position+1
add r1, #1
strb r1, [r0, #MPL_PATTJUMP]
.mppe_pb_exit:
bx lr @ finished
.pool
.align 2
.thumb_func
@------------------------------------------------------------------------------------------
mppe_VolumeSlide: @ EFFECT Dxy: VOLUME SLIDE
@------------------------------------------------------------------------------------------
push {lr}
ldrb r0, [r7, #MCH_VOLUME] @ load volume
bl mpph_VolumeSlide64
strb r0, [r7, #MCH_VOLUME] @ save volume
.mppe_vs_zt:
pop {r0}
bx r0
// pop {pc} @ exit
.align 2
.thumb_func
@----------------------------------------------------------------------------------
mppe_Portamento: @ EFFECT Exy/Fxy: Portamento
@----------------------------------------------------------------------------------
push {lr}
.mppe_pd_ot:
mov r3, #0
mov r0, r1
lsr r0, #4 @ test for Ex param (Extra fine slide)
cmp r0, #0xE @ ..
.mppe_pd_checkE: @ ..
bne .mppe_pd_checkF @ ..
cmp r2, #0 @ Extra fine slide: only slide on tick0
bne .mppe_pd_exit @ ..
lsl r1, #32-4 @ mask out slide value
lsr r1, #32-4 @ ..
mov r3, #1
b .mppe_pd_otherslide @ skip the *4 multiplication
.mppe_pd_checkF: @ ------------------------------------
cmp r0, #0xF @ test for Fx param (Fine slide)
bne .mppe_pd_regslide @ ..
cmp r2, #0 @ Fine slide: only slide on tick0
bne .mppe_pd_exit @ ..
lsl r1, #32-4 @ mask out slide value
lsr r1, #32-4 @ ..
b .mppe_pd_otherslide
.mppe_pd_regslide:
cmp r2, #0
beq .mppe_pd_exit
.mppe_pd_otherslide:
ldrb r0, [r7, #MCH_EFFECT] @ check slide direction
mov r2, #MCH_PERIOD
cmp r0, #5 @ .. (5 = portamento down)
ldr r0, [r7, r2] @ get period
bne .mppe_pd_slideup @ branch to function
.mppe_pd_slidedown: @ -------SLIDE DOWN-------
cmp r3, #0
bne .mppe_pd_fineslidedown
bl mpph_PitchSlide_Down
b .mppe_pd_store @ store & exit
.mppe_pd_fineslidedown:
bl mpph_FinePitchSlide_Down
b .mppe_pd_store
.mppe_pd_slideup: @ ---------SLIDE UP---------
cmp r3, #0
bne .mppe_pd_fineslideup
bl mpph_PitchSlide_Up
b .mppe_pd_store
.mppe_pd_fineslideup:
bl mpph_FinePitchSlide_Up
.mppe_pd_store:
mov r2, #MCH_PERIOD
ldr r1, [r7, #MCH_PERIOD]
str r0, [r7, #MCH_PERIOD]
sub r0, r1
add r5, r0
.mppe_pd_exit:
pop {r0}
bx r0 @ exit
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_Glissando: @ EFFECT Gxy: Glissando
@---------------------------------------------------------------------------------
bne .mppe_glis_ot
mov r0, r8
ldrb r0, [r0, #MPL_FLAGS]
lsr r0, #C_FLAGS_GS
bcc 2f
@ gxx is shared, IT MODE ONLY!!
cmp r1, #0
bne 3f
ldrb r1, [r7, #MCH_MEMORY+MPP_IT_PORTAMEM]
strb r1, [r7, #MCH_PARAM]
3: strb r1, [r7, #MCH_MEMORY+MPP_IT_PORTAMEM]
strb r1, [r7, #MCH_MEMORY+MPP_GLIS_MEM] @ for simplification later
b .mppe_glis_ot
2: @ gxx is separate
cmp r1, #0
bne 3f
ldrb r1, [r7, #MCH_MEMORY+MPP_GLIS_MEM]
strb r1, [r7, #MCH_PARAM]
3: strb r1, [r7, #MCH_MEMORY+MPP_GLIS_MEM]
bx lr
// b .mppe_glis_exit
.mppe_glis_ot:
push {lr} // save return address
ldrb r1, [r7, #MCH_MEMORY+MPP_GLIS_MEM]
.mppe_glis_backdoor:
push {r1}
cmp r6, #0 // exit if no active channel
bne 1f //
pop {r1,r3} //
bx r3 //
1: //
ldrb r0, [r6, #MCA_SAMPLE] // get target period
sub r0, #1 //
mpp_SamplePointer //
ldrh r1, [r0, #C_MASS_FREQ] //
LSL R1, #2 //
ldrb r2, [r7, #MCH_NOTE] //
ldr r3,=mmGetPeriod //
bl mpp_call_r3 //
pop {r1} // r1 = parameter
push {r0} //
mov r3, r0 // r3 = target period
mov r2, #MCH_PERIOD // r0 = current period
ldr r0, [r7, r2] //
mov r2, r8 // test S flag
ldrb r2, [r2, #MPL_FLAGS] //
lsr r2, #C_FLAGS_SS //
bCC .mppe_glis_amiga
cmp r0, r3
blt .mppe_glis_slideup
bgt .mppe_glis_slidedown
.mppe_glis_noslide:
pop {r0}
pop {r3}
bx r3
.mppe_glis_slideup:
bl mpph_PitchSlide_Up
pop {r1}
cmp r0, r1
blt .mppe_glis_store
mov r0, r1
b .mppe_glis_store
.mppe_glis_slidedown:
bl mpph_PitchSlide_Down
pop {r1}
cmp r0, r1
bgt .mppe_glis_store
mov r0, r1
.mppe_glis_store:
mov r2, #MCH_PERIOD
ldr r1, [r7, r2] @#MCA_PERIOD]
str r0, [r7, r2] @#MCA_PERIOD]
sub r0, r1
add r5, r0
.mppe_glis_exit:
pop {r3}
bx r3
//bx lr
.mppe_glis_amiga:
cmp r0, r3
blt .mppe_glis_amiga_up
bgt .mppe_glis_amiga_down
pop {r0}
pop {r3}
bx r3
.mppe_glis_amiga_down:
bl mpph_PitchSlide_Up
pop {r1}
cmp r0, r1
bgt .mppe_glis_store
mov r0, r1
b .mppe_glis_store
.mppe_glis_amiga_up:
bl mpph_PitchSlide_Down
pop {r1}
cmp r0, r1
blt .mppe_glis_store
mov r0, r1
b .mppe_glis_store
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_Vibrato: @ EFFECT Hxy: Vibrato
@---------------------------------------------------------------------------------
bne .mppe_v_ot
lsr r0, r1, #4 @ if (x != 0) {
beq .mppe_v_nospd @ speed = 4*x;
lsl r0, #2 @ ..
strb r0, [r7, #MCH_VIBSPD] @ ..
.mppe_v_nospd:
lsl r0, r1, #32-4 @ if (y != 0) {
beq .mppe_v_nodep @ ..
lsr r0, #32-6 @ depth = y * 4;
mov r1, r8
ldrb r1, [r1, #MPL_OLDEFFECTS] @ if(OldEffects)
lsl r0, r1 @ depth <<= 1;
strb r0, [r7, #MCH_VIBDEP] @
b mppe_DoVibrato
.mppe_v_nodep:
BX LR
.align 2
.thumb_func
@-------------------------------------------------------
mppe_DoVibrato:
@-------------------------------------------------------
.mppe_v_ot:
mov r0, r8
ldrb r1, [r0, #MPL_TICK]
ldrb r0, [r0, #MPL_OLDEFFECTS]
cmp r0, #0
beq .mppe_dv_update
cmp r1, #0
bne .mppe_dv_update
push {lr}
ldrb r1, [r7, #MCH_VIBPOS]
b .mppe_dv_notupdate
.mppe_dv_update:
push {lr}
ldrb r0, [r7, #MCH_VIBSPD]
ldrb r1, [r7, #MCH_VIBPOS]
add r1, r0
lsl r1, #32-8
lsr r1, #32-8
strb r1, [r7, #MCH_VIBPOS]
.mppe_dv_notupdate:
ldr r2,=mpp_TABLE_FineSineData
ldrsb r1, [r2, r1]
ldrb r0, [r7, #MCH_VIBDEP]
mul r1, r0
asr r1, #8
mov r0, r5
cmp r1, #0
blt .mppe_dv_negative
bl mpph_PitchSlide_Up
b .mppe_dv_store
.mppe_dv_negative:
neg r1, r1
bl mpph_PitchSlide_Down
.mppe_dv_store:
mov r5, r0
pop {r0}
bx r0
// pop {pc} @ return THUMB
.pool
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_Tremor: @ EFFECT Ixy: Tremor
@---------------------------------------------------------------------------------
bx lr
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_Arpeggio: @ EFFECT Jxy: Arpeggio
@---------------------------------------------------------------------------------
bne .mppe_arp_ot
mov r0, #0
strb r0, [r7, #MCH_FXMEM]
.mppe_arp_ot:
cmp r6, #0
beq 1f
ldrb r0, [r7, #MCH_FXMEM]
// ldrb r3, [r6, #MCA_SAMPLE] ? ???
cmp r0, #1
bgt .mppe_arp_2
beq .mppe_arp_1
.mppe_arp_0:
mov r0, #1
strb r0, [r7, #MCH_FXMEM]
@ do nothing! :)
1: bx lr
.mppe_arp_1:
mov r0, #2 @ set next tick to '2'
strb r0, [r7, #MCH_FXMEM] @ save...
mov r0, r5
lsr r1, #4 @ mask out high nibble of param
.mppe_arp_others:
mov r2, r5
cmp r1, #12 @ see if its >= 12
blt .mppea1_12 @ ..
add r2, r5 @ add period if so... (octave higher)
.mppea1_12: @ ..
lsl r1, #4 @ *16*hword
mov r0, r5
push {lr}
bl mpph_LinearPitchSlide_Up
mov r5, r0
pop {r0}
bx r0
// pop {pc}
.mppe_arp_2:
mov r0, #0
strb r0, [r7, #MCH_FXMEM]
mov r0, r5
lsl r1, #32-4
lsr r1, #32-4
b .mppe_arp_others
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_VibratoVolume: @ EFFECT Kxy: Vibrato+Volume Slide
@---------------------------------------------------------------------------------
push {lr}
push {r1,r2}
bl mppe_DoVibrato
pop {r1,r2}
cmp r2, #0
bl mppe_VolumeSlide
pop {r0}
bx r0
// pop {pc}
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_PortaVolume: @ EFFECT Lxy: Portamento+Volume Slide
@---------------------------------------------------------------------------------
push {lr}
push {r1,r2}
ldrb r1, [r7, #MCH_MEMORY+MPP_GLIS_MEM]
bl mppe_Glissando
pop {r1, r2}
cmp r2, #0
bl mppe_VolumeSlide
pop {r0}
bx r0
// pop {pc}
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_ChannelVolume: @ EFFECT Mxy: Set Channel Volume
@---------------------------------------------------------------------------------
bne .mppe_cv_exit @ quite simple...
cmp r1, #0x40
bgt .mppe_cv_exit @ ignore command if parameter is > 0x40
strb r1, [r7, #MCH_CVOLUME]
.mppe_cv_exit:
bx lr
.align 2
.thumb_func
@------------------------------------------------------------------------------------
mppe_ChannelVolumeSlide: @ EFFECT Nxy: Channel Volume Slide
@------------------------------------------------------------------------------------
push {lr}
ldrb r0, [r7, #MCH_CVOLUME] @ load volume
bl mpph_VolumeSlide64
strb r0, [r7, #MCH_CVOLUME] @ save volume
pop {r0}
bx r0
// pop {pc} @ exit
.align 2
.thumb_func
@----------------------------------------------------------------------------------
mppe_SampleOffset: @ EFFECT Oxy Sample Offset
@----------------------------------------------------------------------------------
bne .mppe_so_exit @ skip on other ticks
ldr r0,=mpp_vars
strb r1, [r0, #MPV_SAMPOFF] @ set offset
.mppe_so_exit:
bx lr
.pool
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_PanningSlide: @ EFFECT Pxy Panning Slide
@---------------------------------------------------------------------------------
push {lr}
mov r0, #255
push {r0}
ldrb r0, [r7, #MCH_PANNING] @ load panning
bl mpph_VolumeSlide
strb r0, [r7, #MCH_PANNING] @ save panning
pop {r0}
bx r0
// pop {pc} @ exit
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_Retrigger: @ EFFECT Qxy Retrigger Note
@---------------------------------------------------------------------------------
ldrb r0, [r7, #MCH_FXMEM]
cmp r0, #0
bne .mppe_retrig_refillN
.mppe_retrig_refill:
lsl r0, r1, #32-4
lsr r0, #32-4
add r0, #1
.mppe_retrig_exitcount:
strb r0, [r7, #MCH_FXMEM]
bx lr
.mppe_retrig_refillN:
sub r0, #1
cmp r0, #1
bne .mppe_retrig_exitcount
.mppe_retrig_fire:
ldrb r2, [r7, #MCH_VOLUME]
lsr r0, r1, #4
beq .mppe_retrig_v_change0
cmp r0, #5
ble .mppe_retrig_v_change_sub
cmp r0, #6
beq .mppe_retrig_v_change_23
cmp r0, #7
beq .mppe_retrig_v_change_12
cmp r0, #8
beq .mppe_retrig_v_change0
cmp r0, #0xD
ble .mppe_retrig_v_change_add
cmp r0, #0xE
beq .mppe_retrig_v_change_32
cmp r0, #0xF
beq .mppe_retrig_v_change_21
.mppe_retrig_v_change_21:
lsl r2, #1
cmp r2, #64
blt .mppe_retrig_finish
mov r2, #64
.mppe_retrig_v_change0:
b .mppe_retrig_finish
.mppe_retrig_v_change_sub:
sub r0, #1
mov r3, #1
lsl r3, r0
sub r2, r3
bcs .mppe_retrig_finish
mov r2, #0
b .mppe_retrig_finish
.mppe_retrig_v_change_23:
mov r0, #171
mul r2, r0
lsr r2, #8
b .mppe_retrig_finish
.mppe_retrig_v_change_12:
lsr r2, #1
b .mppe_retrig_finish
.mppe_retrig_v_change_add:
sub r0, #9
mov r3, #1
lsl r3, r0
add r2, r3
cmp r2, #64
blt .mppe_retrig_finish
mov r2, #64
b .mppe_retrig_finish
.mppe_retrig_v_change_32:
mov r0, #192
mul r2, r0
lsr r2, #7
.mppe_retrig_finish:
strb r2, [r7, #MCH_VOLUME]
cmp r6, #0
beq .mppe_retrig_refill
ldrb r0, [r6, #MCA_FLAGS]
mov r2, #MCAF_START
orr r0, r2
strb r0, [r6, #MCA_FLAGS]
b .mppe_retrig_refill
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_Tremolo: @ EFFECT Rxy: Tremolo
@---------------------------------------------------------------------------------
@ r1 = param
@ Z = tick0
beq .mppe_trem_zt @ skip this part on tick0
.mppe_trem_ot:
@ X = speed, Y = depth
ldrb r0, [r7, #MCH_FXMEM] @ get sine position
lsr r3, r1, #4 @ mask out SPEED
lsl r3, #2 @ speed*4 to compensate for larger sine table
add r0, r3 @ add to position
strb r0, [r7, #MCH_FXMEM] @ save (value & 255)
.mppe_trem_zt:
ldrb r0, [r7, #MCH_FXMEM] @ get sine position
ldr r3,=mpp_TABLE_FineSineData @ load sine table value
ldrsb r0, [r3, r0]
lsl r1, #32-4 @ mask out DEPTH
lsr r1, #32-4
mul r0, r1 @ SINE*DEPTH / 64
asr r0, #6
mov r1, r8
ldrb r1, [r1, #MPL_FLAGS]
lsr r1, #C_FLAGS_XS
bcs 1f
asr r0, #1
1: ldr r1,=mpp_vars @ set volume addition variable
strb r0, [r1, #MPV_VOLPLUS]
bx lr
.pool
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_Extended: @ EFFECT Sxy: Extended Effects
@---------------------------------------------------------------------------------
lsr r0, r1, #4
lsl r0, #1
cmp r2, #0
add r0, pc
mov pc, r0
@ branch table...
b mppex_XM_FVolSlideUp @ S0x
b mppex_XM_FVolSlideDown @ S1x
b mppex_OldRetrig @ S2x
b mppex_VibForm @ S3x
b mppex_TremForm @ S4x
b mppex_PanbForm @ S5x
b mppex_FPattDelay @ S6x
b mppex_InstControl @ S7x
b mppex_SetPanning @ S8x
b mppex_SoundControl @ S9x
b mppex_HighOffset @ SAx
b mppex_PatternLoop @ SBx
b mppex_NoteCut @ SCx
b mppex_NoteDelay @ SDx
b mppex_PatternDelay @ SEy
b mppex_SongMessage @ SFx
.mppe_ex_quit:
@-------------------------------------------
.thumb_func
mppex_Unused:
bx lr
@-------------------------------------------
.thumb_func
mppex_XM_FVolSlideUp:
bne 2f
ldrb r0, [r7, #MCH_VOLUME]
lsl r1, #32-4
lsr r1, #32-4
add r0, r1
cmp r0, #64
blt 1f
mov r0, #64
1: strb r0, [r7, #MCH_VOLUME]
2: bx lr
.thumb_func
mppex_XM_FVolSlideDown:
bne 2f
ldrb r0, [r7, #MCH_VOLUME]
lsl r1, #32-4
lsr r1, #32-4
sub r0, r1
bcs 1f
mov r0, #0
1: strb r0, [r7, #MCH_VOLUME]
2: bx lr
@-------------------------------------------
.thumb_func
mppex_OldRetrig:
bne 1f
lsl r1, #32-4
lsr r1, #32-4
strb r1, [r7, #MCH_FXMEM]
bx lr
1: ldrb r0, [r7, #MCH_FXMEM]
sub r0, #1
bne 1f
lsl r0, r1, #32-4
lsr r0, #32-4
strb r0, [r7, #MCH_FXMEM]
cmp r6, #0
beq 1f
ldrb r1, [r6, #MCA_FLAGS]
mov r2, #MCAF_START
orr r1, r2
strb r1, [r6, #MCA_FLAGS]
1: strb r0, [r7, #MCH_FXMEM]
bx lr
@-------------------------------------------
.thumb_func
mppex_VibForm:
bx lr
@-------------------------------------------
.thumb_func
mppex_TremForm:
bx lr
@-------------------------------------------
.thumb_func
mppex_PanbForm:
bx lr
@-------------------------------------------
.thumb_func
mppex_FPattDelay:
bne .mppex_fpd_exit
lsl r1, #32-4
lsr r1, #32-4
mov r0, r8
strb r1, [r0, #MPL_FPATTDELAY]
.mppex_fpd_exit:
bx lr
@-------------------------------------------
.thumb_func
mppex_InstControl:
bne .mppex_ic_exit
lsl r1, #32-4
lsr r1, #32-4
cmp r1, #2
ble .mppex_ic_pastnotes
cmp r1, #6
ble .mppex_ic_nna
cmp r1, #8
ble .mppex_ic_envelope
bx lr
.mppex_ic_pastnotes:
@ todo...
bx lr
.mppex_ic_nna:
@ overwrite NNA
sub r1, #3
ldrb r2, [r7, #MCH_BFLAGS]
lsl r2, #32-6
lsr r2, #32-6
lsl r1, #6
orr r2, r1
strb r2, [r7, #MCH_BFLAGS]
bx lr
.mppex_ic_envelope:
cmp r6, #0
beq .mppex_ic_exit
ldrb r2, [r6, #MCA_FLAGS]
mov r0, #32
bic r2, r0
sub r1, #7
lsl r1, #5
orr r2, r1
strb r2, [r6, #MCA_FLAGS]
.mppex_ic_exit:
bx lr
@-------------------------------------------
.thumb_func
mppex_SetPanning:
lsl r1, #4
strb r1, [r7, #MCH_PANNING]
bx lr
@-------------------------------------------
.thumb_func
mppex_SoundControl:
cmp r1, #0x91
beq .mppex_sc_surround
bx lr
.mppex_sc_surround:
@ set surround
bx lr
@-------------------------------------------
.thumb_func
mppex_HighOffset:
@ todo...
bx lr
@-------------------------------------------
.thumb_func
mppex_PatternLoop:
bne .mppex_pl_exit @ dont update on nonzero ticks
mov r2, r8
lsl r1, #32-4 @ mask low nibble of parameter
lsr r1, #32-4 @ ...
bne .mppex_pl_not0 @ is zero?
ldrb r1, [r2, #MPL_ROW] @ ...
strb r1, [r2, #MPL_PLOOP_ROW] @ ...
ldr r1,=mpp_vars @ ....
ldr r1, [r1, #MPV_PATTREAD_P] @ .. ...
mov r3, #MPL_PLOOP_ADR
str r1, [r2, r3] @ ... ...
bx lr @ ... ...
.mppex_pl_not0: @ otherwise...
ldrb r0, [r2, #MPL_PLOOP_TIMES] @ get pattern loop counter
cmp r0, #0 @ zero?
bne .mppex_pl_active @ if not then its already active
strb r1, [r2, #MPL_PLOOP_TIMES] @ zero: save parameter to counter
b .mppex_pl_exit_enable @ exit & enable jump
.mppex_pl_active: @ nonzero:
sub r0, #1 @ decrement counter
strb r0, [r2, #MPL_PLOOP_TIMES] @ save
beq .mppex_pl_exit @ enable jump if not 0
.mppex_pl_exit_enable:
mov r0, #1 @ enable jump
mov r3, #MPL_PLOOP_JUMP
strb r0, [r2, r3] @ ..
.mppex_pl_exit: @ exit
bx lr @ ....
.pool
@-------------------------------------------
.thumb_func
mppex_NoteCut:
lsl r1, #32-4 @ mask parameter
lsr r1, #32-4 @ ..
cmp r1, r2 @ compare with tick#
bne .mppex_nc_exit @ if equal:
mov r0, #0 @ cut volume
strb r0, [r7, #MCH_VOLUME] @ ..
.mppex_nc_exit: @ exit
bx lr @ ..
@-------------------------------------------
.thumb_func
mppex_NoteDelay:
mov r0, r8
ldrb r2, [r0, #MPL_TICK]
lsl r1, #32-4
lsr r1, #32-4
cmp r2, r1
bge 1f
ldr r0,=mpp_vars
strb r1, [r0, #MPV_NOTEDELAY]
1: bx lr
@-------------------------------------------
.thumb_func
mppex_PatternDelay:
bne .mppex_pd_quit @ update on tick0
lsl r1, #32-4 @ mask parameter
lsr r1, #32-4 @ ..
mov r0, r8
ldrb r2, [r0, #MPL_PATTDELAY] @ get patterndelay
cmp r2, #0 @ only update if it's 0
bne .mppex_pd_quit @ ..
add r1, #1 @ set to param+1
strb r1, [r0, #MPL_PATTDELAY] @ ..
.mppex_pd_quit: @ exit
bx lr @ ..
@-------------------------------------------
.thumb_func
mppex_SongMessage:
bne .mppex_pd_quit @ update on tick0
push {lr} @ save return address
lsl r1, #32-4 @ mask parameter
lsr r1, #32-4 @ ..
ldr r2,=mmCallback
ldr r2, [r2]
cmp r2, #0
beq 1f
mov r0, #MPCB_SONGMESSAGE
bl mpp_call_r2
@jump2
1: //pop {pc}
pop {r0}
bx r0
.pool
.align 2
.thumb_func
@----------------------------------------------------------------------------------------
mppe_SetTempo: @ EFFECT Txy: Set Tempo / Tempo Slide
@----------------------------------------------------------------------------------------
@ 0x = slide down
@ 1x = slide up
@ 2x+ = set
// BUGGED???
// not using setbpm for slides???
cmp r1, #0x20
bge .mppe_st_set
cmp r2, #0
beq .mppe_st_exit
mov r0, r8
ldrb r2, [r0, #MPL_BPM]
cmp r1, #0x10
bge .mppe_st_slideup
.mppe_st_slidedown:
sub r2, r1
cmp r2, #32
bge .mppe_st_save
mov r2, #32
.mppe_st_save:
mov r0, r2
b .mppe_st_set2
.mppe_st_slideup:
lsl r1, #32-4
lsr r1, #32-4
add r2, r1
cmp r2, #255
blt .mppe_st_save
mov r2, #255
b .mppe_st_save
.mppe_st_set:
cmp r2, #0
bne .mppe_st_exit
mov r0, r1
.mppe_st_set2:
push {r5,lr}
mov r5, r8
ldr r1,=mpp_setbpm
bl mpp_call_r1
@jump1
pop {r5}
pop {r3}
bx r3
.mppe_st_exit:
bx lr
.pool
.align 2
.thumb_func
@----------------------------------------------------------------------------------------
mppe_FineVibrato: @ EFFECT Uxy: Fine Vibrato
@----------------------------------------------------------------------------------------
bne .mppe_fv_ot
lsr r0, r1, #4
beq .mppe_fv_nospd
lsl r0, #2
strb r0, [r7, #MCH_VIBSPD]
.mppe_fv_nospd:
lsl r0, r1, #32-4
beq .mppe_fv_nodep
// lsr r0, #32 heh...
lsr r0, #32-4
mov r1, r8
ldrb r1, [r1, #MPL_OLDEFFECTS]
lsl r0, r1
strb r0, [r7, #MCH_VIBDEP]
.mppe_fv_nodep:
.mppe_fv_ot:
b mppe_DoVibrato
.pool
.align 2
.thumb_func
@------------------------------------------------------------------------------------
mppe_SetGlobalVolume: @ EFFECT Vxy: Set Global Volume
@------------------------------------------------------------------------------------
bne .mppe_sgv_exit @ on tick0:
mov r0, r8
ldrb r2, [r0, #MPL_FLAGS]
mov r3, #(1<<(C_FLAGS_XS-1))+(1<<(C_FLAGS_LS-1))
tst r2, r3
beq 1f
mov r2, #0x40
b 2f
1: mov r2, #0x80
2:
cmp r1, r2
blt 1f
mov r1, r2
1: strb r1, [r0, #MPL_GV] @ save param to global volume
.mppe_sgv_exit:
bx lr
.pool
.align 2
.thumb_func
@----------------------------------------------------------------------------------
mppe_GlobalVolumeSlide: @ EFFECT Wxy: Global Volume Slide
@----------------------------------------------------------------------------------
push {lr}
.mppe_gvs_ot:
mov r0, r8
ldrb r0, [r0, #MPL_FLAGS]
lsr r0, #C_FLAGS_XS
bcs 1f
mov r0, #128
b 2f
1: mov r0, #64
2: push {r0}
mov r0, r8
ldrb r0, [r0, #MPL_GV] @ load global volume
bl mpph_VolumeSlide @ slide..
mov r1, r8
strb r0, [r1, #MPL_GV] @ save global volume
pop {r0}
bx r0
// pop {pc} @ exit
.pool
.align 2
.thumb_func
@---------------------------------------------------------------------------------------
mppe_SetPanning: @ EFFECT Xxy: Set Panning
@---------------------------------------------------------------------------------------
bne .mppe_sp_exit @ on tick0:
strb r1, [r7, #MCH_PANNING] @ set panning=param
.mppe_sp_exit:
bx lr
.pool
.align 2
.thumb_func
@---------------------------------------------------------------------------------------
mppe_Panbrello: @ EFFECT Yxy: Panbrello
@---------------------------------------------------------------------------------------
@ todo
bx lr
.align 2
.thumb_func
@---------------------------------------------------------------------------------
mppe_ZXX: @ EFFECT Zxy: Set Filter
@---------------------------------------------------------------------------------
@ ZXX IS NOT SUPPORTED
bx lr @ exit
.pool
@=======================================================================================
@ OLD EFFECTS
@=======================================================================================
.align 2
.thumb_func
@-----------------------------------------------------------------------------------
mppe_SetVolume: @ EFFECT 0xx: Set Volume
@-----------------------------------------------------------------------------------
bne .mppe_sv_exit @ on tick0:
strb r1, [r7, #MCH_VOLUME] @ set volume=param
.mppe_sv_exit:
bx lr
.align 2
.thumb_func
@-----------------------------------------------------------------------------------
mppe_KeyOff: @ EFFECT 1xx: Key Off
@-----------------------------------------------------------------------------------
cmp r1, r2 @ if tick=param:
bne .mppe_ko_exit @
cmp r6, #0
beq .mppe_ko_exit
ldrb r0, [r6, #MCA_FLAGS] @ clear keyon from flags
mov r1, #MCAF_KEYON @
bic r0, r1 @
strb r0, [r6, #MCA_FLAGS] @
.mppe_ko_exit:
bx lr @ finished
.pool
.align 2
.thumb_func
@-----------------------------------------------------------------------------------
mppe_EnvelopePos: @ EFFECT 1xx: Envelope Position
@-----------------------------------------------------------------------------------
bne .mppe_ep_ot @ on tick0:
cmp r6, #0
beq .mppe_ep_ot
@ - NOT SUPPORTED ANYMORE -
@ strh r1, [r6, #MCA_ENVP_VOL] @ set volume envelope position
@ strh r1, [r6, #MCA_ENVP_PAN] @ set panning envelope positin
@ pitch envelope wasn't invented yet
.mppe_ep_ot:
bx lr @ finished
.align 2
.thumb_func
@-----------------------------------------------------------------------------------
mppe_OldTremor: @ EFFECT 3xy: Old Tremor
@-----------------------------------------------------------------------------------
bne .mppe_ot_ot
bx lr
.mppe_ot_ot:
ldrb r0, [r7, #MCH_FXMEM]
cmp r0, #0
bne .mppe_ot_old
.mppe_ot_new:
ldrb r0, [r7, #MCH_BFLAGS+1]
mov r3, #0b110
eor r0, r3
strb r0, [r7, #MCH_BFLAGS+1]
lsr r0, #3
bcc .mppe_ot_low
lsr r1, #4
add r1, #1
strb r1, [r7, #MCH_FXMEM]
b .mppe_ot_apply
.mppe_ot_low:
lsl r1, #32-4
lsr r1, #32-4
add r1, #1
strb r1, [r7, #MCH_FXMEM]
b .mppe_ot_apply
.mppe_ot_old:
sub r0, #1
strb r0, [r7, #MCH_FXMEM]
.mppe_ot_apply:
ldrb r2, [r7, #MCH_BFLAGS+1]
lsr r2, #3
bcs .mppe_ot_cut
mov r1, #-64&255
ldr r2,=mpp_vars
strb r1, [r2, #MPV_VOLPLUS]
.mppe_ot_cut:
bx lr
@===============================================================================
@ FUNCTIONS!!
@===============================================================================
.align 2
.thumb_func
@--------------------------------------------------------------------------
mpph_PitchSlide_Down: @ Linear/Amiga slide down
@--------------------------------------------------------------------------
@ r0 = period
@ r1 = slide value (/4)
mov r2, r8
ldrb r2, [r2, #MPL_FLAGS]
lsr r2, #C_FLAGS_SS
bcc .mpph_psd_amiga
b .mpph_psd
.thumb_func
@--------------------------------------------------------------------------
mpph_LinearPitchSlide_Down: @ Linear slide down
@--------------------------------------------------------------------------
mov r2, r8
ldrb r2, [r2, #MPL_FLAGS]
lsr r2, #C_FLAGS_SS
bcc .mpph_psu
.mpph_psd:
ldr r2,=mpp_TABLE_LinearSlideDownTable
.mpph_psd_fine:
lsl r1, #1
ldrh r1, [r2, r1]
lsr r0, #5
mul r0, r1
lsr r0, #16 -5
.mpph_psd_clip:
cmp r0, #0
bge .mpph_psd_clipdone
mov r0, #0
.mpph_psd_clipdone:
bx lr
.mpph_psd_amiga:
lsl r1, #4
.mpph_psd_amiga_fine:
add r0, r1
lsr r1, r0, #16+5
beq .mpph_psd_clipdone
mov r0, #1
lsl r0, #16+5
b .mpph_psd_clip
.align 2
.thumb_func
@--------------------------------------------------------------------------
mpph_PitchSlide_Up: @ Linear/Amiga slide up
@--------------------------------------------------------------------------
@ r0 = period
@ r1 = slide value (/4)
mov r2, r8
ldrb r2, [r2, #MPL_FLAGS]
lsr r2, #C_FLAGS_SS
bcc .mpph_psu_amiga
b .mpph_psu
.thumb_func
mpph_LinearPitchSlide_Up: @ Linear slide up
mov r2, r8
ldrb r2, [r2, #MPL_FLAGS]
lsr r2, #C_FLAGS_SS
bcc .mpph_psd
.mpph_psu:
ldr r2,=mpp_TABLE_LinearSlideUpTable
mov r3, r0
cmp r1, #192
blt .mpph_psu_notdouble
add r3, r3
.mpph_psu_notdouble:
.mpph_psu_fine:
lsl r1, #1
ldrh r1, [r2, r1]
lsr r0, #5
mul r0, r1
lsr r0, #16-5
add r0, r3
.mpph_psu_clip:
mov r1, r0
lsr r1, #16+5
beq .mpph_psu_clipped
mov r0, #1
lsl r0, #16+5
.mpph_psu_clipped:
bx lr
.mpph_psu_amiga:
lsl r1, #4
.mpph_psu_amiga_fine:
sub r0, r1
bcs .mpph_psu_clipped
mov r0, #0
bx lr
.align 2
.thumb_func
@---------------------------------------------------------------------------
mpph_FinePitchSlide_Up:
@---------------------------------------------------------------------------
@ r0 = period
@ r1 = slide value (0-15)
mov r2, r8
ldrb r2, [r2, #MPL_FLAGS]
lsr r2, #C_FLAGS_SS
bcc .mpph_fpsu_amiga
ldr r2,=mpp_TABLE_FineLinearSlideUpTable
mov r3, r0
b .mpph_psu_fine
.mpph_fpsu_amiga:
lsl r1, #2
b .mpph_psu_amiga_fine
.align 2
.thumb_func
@-----------------------------------------------------------------------------------
mpph_FinePitchSlide_Down:
@-----------------------------------------------------------------------------------
@ r0 = period
@ r1 = slide value (0-15)
mov r2, r8
ldrb r2, [r2, #MPL_FLAGS]
lsr r2, #C_FLAGS_SS
bcc .mpph_fpsd_amiga
ldr r2,=mpp_TABLE_FineLinearSlideDownTable
b .mpph_psd_fine
.mpph_fpsd_amiga:
lsl r1, #2
b .mpph_psd_amiga_fine
.pool
@-----------------------------------------------------------------------------------
.text
.align 2
.thumb_func
@-----------------------------------------------------------------------------------
mpph_FastForward:
@-----------------------------------------------------------------------------------
@ r1 = #rows to skip
cmp r1, #0
bne .mpph_ff
.mpph_ff_exitf:
bx lr
.mpph_ff:
mov r0, r8
ldrb r2, [r0, #MPL_NROWS]
add r2, #1
cmp r1, r2
bge .mpph_ff_exitf
strb r1, [r0, #MPL_ROW]
push {r7,lr}
ldr r7,=mmReadPattern //mpp_ReadPattern
.mpph_ff_loop:
push {r1,r7}
bl mpp_call_r7
pop {r1,r7}
sub r1, #1
bne .mpph_ff_loop
pop {r7}
pop {r0}
bx r0
// pop {pc}
.pool
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@ IWRAM CODE @
@ @
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
.align 2
.thumb_func
@-----------------------------------------------------------------------------
mpph_VolumeSlide64:
@-----------------------------------------------------------------------------
mov r3, #64
push {r3}
.thumb_func
@-----------------------------------------------------------------------------
mpph_VolumeSlide:
@-----------------------------------------------------------------------------
@ r0 = volume
@ r1 = paramter
@ r2 = tick#
@ stack:1 = max volume
mov r3, r8
ldrb r3, [r3, #MPL_FLAGS]
lsr r3, #C_FLAGS_XS
bcs .mpph_vs_XM
cmp r1, #0x0F @ is value 15?
bne .mpph_vs_hack1 @ then only slide on tick0
b .mpph_vs_fsub
.mpph_vs_hack1:
cmp r1, #0xF0 @ is value 15?
bne .mpph_vs_hack2 @ then only slide on tick0
cmp r2, #0 @ ..
bne .mpph_vs_exit @ ..
b .mpph_vs_fadd
.mpph_vs_hack2:
mov r3, r1 @ test for Dx0
lsl r3, #32-4 @ ..
bne .mpph_vs_next1 @ ..
.mpph_vs_add: @ Dx0: (used for DxF too)
cmp r2, #0
beq .mpph_vs_exit
.mpph_vs_fadd:
lsr r1, #4 @ fix value
add r0, r1 @ add to volume
pop {r1}
cmp r0, r1 @ clip values past 64
blt .mpph_vs_exit2 @ ..
mov r0, r1 @ ..
b .mpph_vs_exit2 @ ..
.mpph_vs_next1: @---------------------
mov r3, r1 @ test for D0x
lsr r3, #4 @ ..
bne .mpph_vs_next2 @ ..
.mpph_vs_sub: @ D0x:
cmp r2, #0
beq .mpph_vs_exit
.mpph_vs_fsub:
lsl r1, #32-4 @ mask value
lsr r1, #32-4 @ ..
sub r0, r1 @ subtract from volume
bcs .mpph_vs_exit @ clip values under 0
mov r0, #0 @ ..
b .mpph_vs_exit @ ..
.mpph_vs_next2: @---------------------
cmp r2, #0 @ fine slides now... only slide on tick0
bne .mpph_vs_exit @ ..
mov r3, r1 @ test for DxF
lsl r3, #32-4 @ ..
lsr r3, #32-4
cmp r3, #0x0F @ ..
beq .mpph_vs_fadd @ branch
mov r3, r1 @ test for DFx
lsr r3, #4 @ ..
cmp r3, #0x0F @ ..
beq .mpph_vs_fsub @ branch
.mpph_vs_exit:
pop {r1}
.mpph_vs_exit2:
bx lr @ exit if all fail
.mpph_vs_XM:
cmp r2, #0
beq .mpph_vs_exit
lsr r3, r1, #4
lsl r1, #32-4
lsr r1, #32-4
sub r3, r1
add r0, r3
pop {r1}
cmp r0, r1
blt .mpph_vsxm_testlow
mov r0, r1
.mpph_vsxm_testlow:
cmp r0, #0
bgt .mpph_vs_exit2
mov r0, #0
bx lr
.pool
@==========================================================================================
@ TABLES
@==========================================================================================
.TEXT
.align 2
/******************************************************************************
* ST3_FREQTABLE
*
* LUT for amiga periods.
******************************************************************************/
.global ST3_FREQTABLE
ST3_FREQTABLE:
.hword 1712*8, 1616*8, 1524*8, 1440*8, 1356*8, 1280*8, 1208*8, 1140*8, 1076*8, 1016*8, 960*8, 907*8 @ MORE ACCURACY SCALARS
@middle octave is 4.
@
@ 133808 * ( period(NOTE) >> octave )
@ note_st3period = --------------------------------------------
@ middle_c_finetunevalue(INSTRUMENT)
@
.align 2
@-------------------------------------------------------------------------------------------
mpp_TABLE_LinearSlideUpTable: @ value = 2^(val/192), 16.16 fixed
@-------------------------------------------------------------------------------------------
.hword 0, 237, 475, 714, 953 @ 0->4 @ ADD 1.0
.hword 1194, 1435, 1677, 1920, 2164 @ 5->9
.hword 2409, 2655, 2902, 3149, 3397 @ 10->14
.hword 3647, 3897, 4148, 4400, 4653 @ 15->19
.hword 4907, 5157, 5417, 5674, 5932 @ 20->24
.hword 6190, 6449, 6710, 6971, 7233 @ 25->29
.hword 7496, 7761, 8026, 8292, 8559 @ 30->34
.hword 8027, 9096, 9366, 9636, 9908 @ 35->39
.hword 10181, 10455, 10730, 11006, 11283 @ 40->44
.hword 11560, 11839, 12119, 12400, 12682 @ 45->49
.hword 12965, 13249, 13533, 13819, 14106 @ 50->54
.hword 14394, 14684, 14974, 15265, 15557 @ 55->59
.hword 15850, 16145, 16440, 16737, 17034 @ 60->64
.hword 17333, 17633, 17933, 18235, 18538 @ 65->69
.hword 18842, 19147, 19454, 19761, 20070 @ 70->74
.hword 20379, 20690, 21002, 21315, 21629 @ 75->79
.hword 21944, 22260, 22578, 22897, 23216 @ 80->84
.hword 23537, 23860, 24183, 24507, 24833 @ 85->89
.hword 25160, 25488, 25817, 26148, 26479 @ 90->94
.hword 26812, 27146, 27481, 27818, 28155 @ 95->99
.hword 28494, 28834, 29175, 29518, 29862 @ 100->104
.hword 30207, 30553, 30900, 31248, 31599 @ 105->109
.hword 31951, 32303, 32657, 33012, 33369 @ 110->114
.hword 33726, 34085, 34446, 34807, 35170 @ 115->119
.hword 35534, 35900, 36267, 36635, 37004 @ 120->124
.hword 37375, 37747, 38121, 38496, 38872 @ 125->129
.hword 39250, 39629, 40009, 40391, 40774 @ 130->134
.hword 41158, 41544, 41932, 42320, 42710 @ 135->139
.hword 43102, 43495, 43889, 44285, 44682 @ 140->144
.hword 45081, 45481, 45882, 46285, 46690 @ 145->149
.hword 47095, 47503, 47917, 48322, 48734 @ 150->154
.hword 49147, 49562, 49978, 50396, 50815 @ 155->159
.hword 51236, 51658, 52082, 52507, 52934 @ 160->164
.hword 53363, 53793, 54224, 54658, 55092 @ 165->169
.hword 55529, 55966, 56406, 56847, 57289 @ 170->174
.hword 57734, 58179, 58627, 59076, 59527 @ 175->179
.hword 59979, 60433, 60889, 61346, 61805 @ 180->184
.hword 62265, 62727, 63191, 63657, 64124 @ 185->189
.hword 64593, 65064, 0, 474, 950 @ 190->194 @ ADD 2.0 w/ 192+
.hword 1427, 1906, 2387, 2870, 3355 @ 195->199
.hword 3841, 4327, 4818, 5310, 5803 @ 200->204
.hword 6298, 6795, 7294, 7794, 8296 @ 205->209
.hword 8800, 9306, 9814, 10323, 10835 @ 210->214
.hword 11348, 11863, 12380, 12899, 13419 @ 215->219
.hword 13942, 14467, 14993, 15521, 16051 @ 220->224
.hword 16583, 17117, 17653, 18191, 18731 @ 225->229
.hword 19273, 19817, 20362, 20910, 21460 @ 230->234
.hword 22011, 22565, 23121, 23678, 24238 @ 235->239
.hword 24800, 25363, 25929, 25497, 27067 @ 240->244
.hword 27639, 28213, 28789, 29367, 29947 @ 245->249
.hword 30530, 31114, 31701, 32289, 32880 @ 250->254
.hword 33473, 34068 @ 255->256
.align 2
@-------------------------------------------------------------------------------------
mpp_TABLE_LinearSlideDownTable: @ value = 2^(-val/192), 16.16 fixed
@-------------------------------------------------------------------------------------
.hword 65535, 65300, 65065, 64830, 64596, 64364, 64132, 63901 @ 0->7
.hword 63670, 63441, 63212, 62984, 62757, 62531, 62306, 62081 @ 8->15
.hword 61858, 61635, 61413, 61191, 60971, 60751, 60532, 60314 @ 16->23
.hword 60097, 59880, 59664, 59449, 59235, 59022, 58809, 58597 @ 24->31
.hword 58386, 58176, 57966, 57757, 57549, 57341, 57135, 56929 @ 32->39
.hword 56724, 56519, 56316, 56113, 55911, 55709, 55508, 55308 @ 40->47
.hword 55109, 54910, 54713, 54515, 54319, 54123, 53928, 53734 @ 48->55
.hword 53540, 53347, 53155, 52963, 52773, 52582, 52393, 52204 @ 56->63
.hword 52016, 51829, 51642, 51456, 51270, 51085, 50901, 50718 @ 64->71
.hword 50535, 50353, 50172, 49991, 49811, 49631, 49452, 49274 @ 72->79
.hword 49097, 48920, 48743, 48568, 48393, 48128, 48044, 47871 @ 80->87
.hword 47699, 47527, 47356, 47185, 47015, 46846, 46677, 46509 @ 88->95
.hword 46341, 46174, 46008, 45842, 45677, 45512, 45348, 45185 @ 96->103
.hword 45022, 44859, 44698, 44537, 44376, 44216, 44057, 43898 @104->111
.hword 43740, 43582, 43425, 43269, 43113, 42958, 42803, 42649 @112->119
.hword 42495, 42342, 42189, 42037, 41886, 41735, 41584, 41434 @120->127
.hword 41285, 41136, 40988, 40840, 40639, 40566, 40400, 40253 @128->135
.hword 40110, 39965, 39821, 39678, 39535, 39392, 39250, 39109 @136->143
.hword 38968, 38828, 38688, 38548, 38409, 38271, 38133, 37996 @144->151
.hword 37859, 37722, 37586, 37451, 37316, 37181, 37047, 36914 @152->159
.hword 36781, 36648, 36516, 36385, 36254, 36123, 35993, 35863 @160->167
.hword 35734, 35605, 35477, 35349, 35221, 35095, 34968, 34842 @168->175
.hword 34716, 34591, 34467, 34343, 34219, 34095, 33973, 33850 @176->183
.hword 33728, 33607, 33486, 33365, 33245, 33125, 33005, 32887 @184->191
.hword 32768, 32650, 32532, 32415, 32298, 32182, 32066, 31950 @192->199
.hword 31835, 31720, 31606, 31492, 31379, 31266, 31153, 31041 @200->207
.hword 30929, 30817, 30706, 30596, 30485, 30376, 30226, 30157 @208->215
.hword 30048, 29940, 29832, 29725, 29618, 29511, 29405, 29299 @216->223
.hword 29193, 29088, 28983, 28879, 28774, 28671, 28567, 28464 @224->231
.hword 28362, 28260, 28158, 28056, 27955, 27855, 27754, 27654 @232->239
.hword 27554, 27455, 27356, 27258, 27159, 27062, 26964, 26867 @240->247
.hword 26770, 26674, 26577, 26482, 26386, 26291, 26196, 26102 @248->255
.hword 26008 @ 256
/******************************************************************************
* IT_PitchTable
*
* LUT for linear periods.
******************************************************************************/
.global IT_PitchTable
.align 2
IT_PitchTable:
.hword 2048, 0, 2170, 0, 2299, 0, 2435, 0, 2580, 0, 2734, 0 @ C-0
.hword 2896, 0, 3069, 0, 3251, 0, 3444, 0, 3649, 0, 3866, 0 @>B-0
.hword 4096, 0, 4340, 0, 4598, 0, 4871, 0, 5161, 0, 5468, 0 @ C-1
.hword 5793, 0, 6137, 0, 6502, 0, 6889, 0, 7298, 0, 7732, 0 @>B-1
.hword 8192, 0, 8679, 0, 9195, 0, 9742, 0, 10321, 0, 10935, 0 @ octave 2
.hword 11585, 0, 12274, 0, 13004, 0, 13777, 0, 14596, 0, 15464, 0
.hword 16384, 0, 17358, 0, 18390, 0, 19484, 0, 20643, 0, 21870, 0 @ octave 3
.hword 23170, 0, 24548, 0, 26008, 0, 27554, 0, 29193, 0, 30929, 0
.hword 32768, 0, 34716, 0, 36781, 0, 38968, 0, 41285, 0, 43740, 0 @ octave 4
.hword 46341, 0, 49097, 0, 52016, 0, 55109, 0, 58386, 0, 61858, 0
.hword 0, 1, 3897, 1, 8026, 1, 12400, 1, 17034, 1, 21944, 1 @ octave 5
.hword 27146, 1, 32657, 1, 38496, 1, 44682, 1, 51236, 1, 58179, 1
.hword 0, 2, 7794, 2, 16051, 2, 24800, 2, 34068, 2, 43888, 2 @ octave 6
.hword 54292, 2, 65314, 2, 11456, 3, 23828, 3, 36936, 3, 50823, 3
.hword 0, 4, 15588, 4, 32103, 4, 49600, 4, 2601, 5, 22240, 5 @ octave 7
.hword 43048, 5, 65092, 5, 22912, 6, 47656, 6, 8336, 7, 36110, 7
.hword 0, 8, 31176, 8, 64205, 8, 33663, 9, 5201, 10, 44481, 10 @ octave 8
.hword 20559, 11, 64648, 11, 45823, 12, 29776, 13, 16671, 14, 6684, 15
.hword 0, 16, 62352, 16, 62875, 17, 1790, 19, 10403, 20, 23425, 21 @ octave 9
.hword 41118, 22, 63761, 23, 26111, 25, 59552, 26, 33342, 28, 13368, 30
.align 2
@-------------------------------------------------------------------------------------
mpp_TABLE_FineLinearSlideUpTable:
@-------------------------------------------------------------------------------------
.hword 0, 59, 118, 178, 237 @ 0->4 ADD 1x
.hword 296, 356, 415, 475, 535 @ 5->9
.hword 594, 654, 714, 773, 833 @ 10->14
.hword 893 @ 15
.align 2
@-------------------------------------------------------------------------------------
mpp_TABLE_FineLinearSlideDownTable:
@-------------------------------------------------------------------------------------
.hword 65535, 65477, 65418, 65359, 65300, 65241, 65182, 65359 @ 0->7
.hword 65065, 65006, 64947, 64888, 64830, 64772, 64713, 64645 @ 8->15
@-------------------------------------------------------------------------------------
mpp_TABLE_FineSineData:
@-------------------------------------------------------------------------------------
.byte 0, 2, 3, 5, 6, 8, 9, 11, 12, 14, 16, 17, 19, 20, 22, 23
.byte 24, 26, 27, 29, 30, 32, 33, 34, 36, 37, 38, 39, 41, 42, 43, 44
.byte 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 56, 57, 58, 59
.byte 59, 60, 60, 61, 61, 62, 62, 62, 63, 63, 63, 64, 64, 64, 64, 64
.byte 64, 64, 64, 64, 64, 64, 63, 63, 63, 62, 62, 62, 61, 61, 60, 60
.byte 59, 59, 58, 57, 56, 56, 55, 54, 53, 52, 51, 50, 49, 48, 47, 46
.byte 45, 44, 43, 42, 41, 39, 38, 37, 36, 34, 33, 32, 30, 29, 27, 26
.byte 24, 23, 22, 20, 19, 17, 16, 14, 12, 11, 9, 8, 6, 5, 3, 2
.byte 0, -2, -3, -5, -6, -8, -9,-11,-12,-14,-16,-17,-19,-20,-22,-23
.byte -24,-26,-27,-29,-30,-32,-33,-34,-36,-37,-38,-39,-41,-42,-43,-44
.byte -45,-46,-47,-48,-49,-50,-51,-52,-53,-54,-55,-56,-56,-57,-58,-59
.byte -59,-60,-60,-61,-61,-62,-62,-62,-63,-63,-63,-64,-64,-64,-64,-64
.byte -64,-64,-64,-64,-64,-64,-63,-63,-63,-62,-62,-62,-61,-61,-60,-60
.byte -59,-59,-58,-57,-56,-56,-55,-54,-53,-52,-51,-50,-49,-48,-47,-46
.byte -45,-44,-43,-42,-41,-39,-38,-37,-36,-34,-33,-32,-30,-29,-27,-26
.byte -24,-23,-22,-20,-19,-17,-16,-14,-12,-11, -9, -8, -6, -5, -3, -2
.end
|
afska/beat-beast
| 17,963
|
butano/hw/3rd_party/maxmod/source/mm_mas_arm.s
|
/****************************************************************************
* __ *
* ____ ___ ____ __ ______ ___ ____ ____/ / *
* / __ `__ \/ __ `/ |/ / __ `__ \/ __ \/ __ / *
* / / / / / / /_/ /> </ / / / / / /_/ / /_/ / *
* /_/ /_/ /_/\__,_/_/|_/_/ /_/ /_/\____/\__,_/ *
* *
* Module Processing (ARM segment) *
* *
* Copyright (c) 2008, Mukunda Johnson (mukunda@maxmod.org) *
* *
* Permission to use, copy, modify, and/or distribute this software for any *
* purpose with or without fee is hereby granted, provided that the above *
* copyright notice and this permission notice appear in all copies. *
* *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES *
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR *
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES *
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN *
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. *
****************************************************************************/
@=============================================================
@ DEFINITIONS
@=============================================================
#include "../asm_include/mm_gba_setup.inc"
#include "../asm_include/mp_format_mas.inc"
#include "../asm_include/mp_mas_structs.inc"
#include "../asm_include/mp_defs.inc"
#include "../asm_include/mp_macros.inc"
#ifdef SYS_GBA
#include "../asm_include/mp_mixer_gba.inc"
#include "../asm_include/swi_gba.inc"
#endif
#ifdef SYS_NDS
#include "../asm_include/mp_mixer_ds.inc"
#include "../asm_include/swi_nds.inc"
#endif
__SECTION_IWRAM
.arm
.align 2
.global mmAllocChannel
@********************************************************
mmAllocChannel:
@********************************************************
// finds a channel to use
// returns invalid channel [255] if none available
push {r4,r5,r6} // preserve regs
ldr r5,=mm_ch_mask // read channel mask
ldr r5, [r5]
ldr r1,=mm_achannels // pointer to active channels
ldr r1, [r1]
add r1, #MCA_FVOL
mov r0, #0 // r0 = counter
mov r2, #0x80000000 // r2 = min vol
mov r3, #255 // r3 = best channel [255=none]
mov r6, #ACHN_BACKGROUND
b .mppac_start
.mppac_skip:
add r1, #MCA_SIZE
.mppac_next_test:
cmp r5, #0
.mppac_next_notest:
beq .mppac_finished
add r0, #1
.mppac_start:
movs r5, r5, lsr#1 // 1 shift out channel bit
bcc .mppac_skip // 1/3 skip if cleared
ldrh r4, [r1], #MCA_SIZE // 5 read type setting & increment pointer
cmp r6, r4, lsr #8 // 1 compare background/disabled
blt .mppac_next_test // 1/3 if > background then its important, dont use this channel
bgt .mppac_found // 1/3 if < background then its disabled, use this channel
cmp r2, r4, lsl#23 // 1 compare volume with our record
bls .mppac_next_test // 1/3 goto next if not less
mov r3, r0 // 1 otherwise save this channel
movs r2, r4, lsl#23 // 1 and volume level
// beq .mppac_finished // 1/3 exit immediately if volume is zero
b .mppac_next_test // 3 loop
// 17
.mppac_finished:
mov r0, r3
// cmp r0, #255 //trap
// 5: bge 5b
.mppac_found:
pop {r4,r5,r6}
bx lr
.global mmReadPattern
@****************************************************
mmReadPattern:
@****************************************************
push {r10-r12}
ldr r11, [r8, #MPL_SONGADR]
ldrb r12, [r11, #C_MAS_INSTN] // read instr count
ldrb r11, [r8, #MPL_FLAGS] // read flags
mov r10, #1 // for various things
ldr r0,=mpp_channels
ldr r9, [r0]
ldr r7, [r8, #MPL_PATTREAD]
ldr r0,=mpp_vars
str r7, [r0, #MPV_PATTREAD_P]
mov r1, #0
@----------------------------------------------------------------
readpattern:
@----------------------------------------------------------------
mov r5, #0 // clear flags
ldrb r3, [r7], #1 // read pattern byte
movs r3, r3, lsl#32-7 // mask channel#
beq end_of_row // 0 = end of row
rsb r3, r10, r3, lsr#32-7 // get channel number
orr r1, r10, lsl r3
mov r0, #MCH_SIZE
mla r6, r3, r0, r9 // get channel pointer
ldrcsb r2, [r7], #1 // read new maskvariable if bit was set
strcsb r2, [r6, #MCH_CFLAGS] // and save it
ldrccb r2, [r6, #MCH_CFLAGS] // otherwise read previous flags
tst r2, #1 // test note bit
beq no_note
ldrb r0, [r7], #1 // read note value
cmp r0, #254 // test if < 254
strltb r0, [r6, #MCH_PNOTE] // [most common result]
blt no_note
orreq r5, #MF_NOTECUT // 254 is note-cut
orrgt r5, #MF_NOTEOFF // 255 is note-off
no_note:
tst r2, #2 // shift out instrument bit
beq no_instrument
ldrb r0, [r7], #1 // read instrument value
tst r5, #MF_NOTEOFF|MF_NOTECUT
bne no_instrument // skip if note-off or cut is set
cmp r0, r12 // check if value > max instruments
movgt r0, #0 // zero if so
ldrb r3, [r6, #MCH_INST] // test if instrument is the same
cmp r0, r3
beq same_instrument
movs r3, r11, lsr#C_FLAGS_LS // shift out 'mod/s3m' flag
orrcs r5, #MF_START // set start flag if old
orr r5, #MF_NEWINSTR // set new instrument flag
same_instrument:
strb r0, [r6, #MCH_INST]
no_instrument:
tst r10, r2, lsr#3 // test volume & effect bits
ldrcsb r0, [r7], #1 // copy vcmd
strcsb r0, [r6, #MCH_VOLCMD]
no_vcmd:
beq no_effect
ldrb r0, [r7], #1 // copy effect
ldrb r3, [r7], #1 // copy param
orr r0, r3, lsl#8
strh r0, [r6, #MCH_EFFECT] // write effect+param
no_effect:
orr r5, r2, lsr#4 // orr in the new flags
strb r5, [r6, #MCH_FLAGS] // save flags
b readpattern // loop
end_of_row:
str r7, [r8, #MPL_PATTREAD] // save read position
str r1, [r8, #MPL_MCH_UPDATE] // save update bits
pop {r10-r12}
bx lr // return
.macro get_channel branch
ldrb r0, [r7, #MCH_ALLOC] // get channel
cmp r0, #255 //
bge \branch // no channel!
ldr r6,=mm_achannels //
ldr r6, [r6] //
mov r1, #MCA_SIZE //
mla r6, r0, r1, r6 //
.endm
.global mmUpdateChannel_T0, mmUpdateChannel_TN
@***************************************************************************
mmUpdateChannel_T0: // for tick 0
@***************************************************************************
push {lr}
ldrb r5, [r7, #MCH_FLAGS] // read channel flags
tst r5, #MF_START // test start flag
beq dont_start_channel // skip section if cleared
tst r5, #MF_HASFX // test effect flag
beq no_channel_effect
ldrh r0, [r7, #MCH_EFFECT] // read effect
and r1, r0, #0xFF
// cmp r1, #19 // test for 'SDx' (note delay)
// lsreq r2, r0, #12
// cmpeq r2, #0xD
// beq dont_start_channel // dont start channel if delayed
// test for glissando
tst r5, #MF_NEWINSTR
bne start_channel // always start channel if it's a new instrument
cmp r1, #0x7 // test if effect is Gxx
beq glissando_affected
no_channel_effect:
tst r5, #MF_NEWINSTR // copeee
bne start_channel // always start channel if it's a new instrument
tst r5, #MF_HASVCMD // test for volume commmand
beq start_channel // none = start channel
ldrb r0, [r8, #MPL_FLAGS] // read mod flags
movs r0, r0, lsr#C_FLAGS_XS // test for XM mode
ldrb r0, [r7, #MCH_VOLCMD] // read volume command
bcs xm_vcmd // branch
it_vcmd: // using IT effects:
cmp r0, #193 // glissando is 193..202
blt start_channel
cmp r0, #202
bgt start_channel
b glissando_affected
xm_vcmd: // using XM effects:
cmp r0, #0xF0 // glissando is Fx
bge glissando_affected
b start_channel
no_channel_vcmd:
glissando_affected:
get_channel start_channel
/* ldrb r0, [r7, #MCH_ALLOC] // if channel is invalid
cmp r0, #255 // then skip this
bge start_channel
ldr r6,=mm_achannels // get channel
ldr r6, [r6] //
mov r1, #MCA_SIZE //
mla r6, r0, r1, r6 //
*/
bl mmChannelStartACHN // start achn
bic r5, #MF_START // clear start flag
strb r5, [r7, #MCH_FLAGS]
b dont_start_channel
start_channel: // ok start channel...
ldr r2,=mpp_Channel_NewNote
mov lr, pc
bx r2
get_channel mmUpdateChannel_TN_
// cmp r6, #0
// beq mmUpdateChannel_TN_
bl mmChannelStartACHN // start achn
//----------------------------------------------
// r2 = note, calculate period
ldrb r0, [r6, #MCA_SAMPLE]
subs r0, #1
bcc no_sample_to_make_period
ldrb r1, [r8, #MPL_FLAGS]
lsrs r1, #C_FLAGS_SS
bcs linear_periods
ldr r3, [r8, #MPL_SONGADR] // read song addr
ldr r1, [r8, #MPL_SAMPTABLE]// get sample table
ldr r0, [r1, r0, lsl#2] // get sample address
add r0, r3 // add module base
ldrh r1, [r0, #C_MASS_FREQ] // read tuning freq
lsl r1, #2 // shift ...
// mov r0, r2 // move this.
bl get_amiga_period
b got_period
linear_periods:
LDR R1,=IT_PitchTable
LDR R0, [R1, R2, LSL#2]
//bl get_linear_period
got_period:
//--------------------------------
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
str r0, [r7, #MCH_PERIOD] // save period
ldrb r0, [r6, #MCA_FLAGS] // set start flag
orr r0, #MCAF_START
strb r0, [r6, #MCA_FLAGS]
no_sample_to_make_period:
//----------------------------------------------------
b channel_started
dont_start_channel:
get_channel mmUpdateChannel_TN___
channel_started:
tst r5, #MF_DVOL
beq dvol_skip
ldrb r0, [r7, #MCH_INST]
subs r0, #1
bcc dvol_no_instrument
ldr r2, [r8, #MPL_SONGADR] // get instrument pointer
ldr r1, [r8, #MPL_INSTTABLE]
ldr r0, [r1, r0, lsl#2]
add r0, r2
ldr r1, [r0, #C_MASI_NNA] // read nna,envflags,pan
ldrb r2, [r7, #MCH_BFLAGS] // read bflags
bic r2, #0b11000000 // clear old nna
orr r2, r1, lsl#6 // set new nna
strb r2, [r7, #MCH_BFLAGS]
ldrb r2, [r6, #MCA_FLAGS] // read achn flags
bic r2, #MCAF_VOLENV
tst r1, #ENVFLAG_A<<8
orrne r2, #MCAF_VOLENV
strb r2, [r6, #MCA_FLAGS]
movs r1, r1, lsl#8+1 // shift out panning MSB
movcs r1, r1, lsr#24 // if set, use new panning value
strcsb r1, [r7, #MCH_PANNING]
dvol_no_instrument:
ldrb r0, [r6, #MCA_SAMPLE] // read sample#
subs r0, #1
bcc dvol_no_sample // exit if invalid
ldr r2, [r8, #MPL_SONGADR] // get sample address
ldr r1, [r8, #MPL_SAMPTABLE]
ldr r0, [r1, r0, lsl#2]
//add r0, r2
ldrh r1, [r0, r2]
//ldrh r1, [r0, #C_MASS_DV] // read dvol & pan
strb r1, [r7, #MCH_VOLUME] // copy volume
movs r1, r1, lsl#24-7
mov r1, r1, lsr#24
strcsb r1, [r7, #MCH_PANNING]
dvol_skip:
dvol_no_sample:
tst r5, #MF_START|MF_DVOL
beq dont_reset_volume
ldrb r0, [r8, #MPL_FLAGS]
tst r0, #C_FLAGS_X
beq 1f
tst r5, #MF_DVOL
beq dont_reset_volume // xm stuff
1:
reset_volume:
mov r0, #(1<<10) // [1]
mov r1, #0 // [1]
mov r2, #0 // [1]
add r12, r6, #MCA_FADE // [1]
stmia r12, {r0-r2} // [19]
// [23]
strh r1, [r6, #MCA_ENVN_VOL]
strb r1, [r6, #MCA_ENVN_PIC]
// the last bit of code sets fade to (1<<10)
// and clears ENVC_VOL,ENVC_PAN,ENVC_PIC,
// AVIB_DEP, and AVIB_POS
// second bit clears ENVN vars
strb r1, [r7, #MCH_FXMEM] // clear fx memory
ldrb r1, [r6, #MCA_FLAGS] // set keyon
orr r1, #MCAF_KEYON // and clear envend+fade
bic r1, #MCAF_ENVEND | MCAF_FADE
strb r1, [r6, #MCA_FLAGS]
dont_reset_volume:
tst r5, #MF_NOTEOFF // test noteoff bit
beq skip_noteoff
ldrb r1, [r6, #MCA_FLAGS] // read flags
bic r1, #MCAF_KEYON // clear key-on
ldrb r0, [r8, #MPL_FLAGS] // read mod flags
tst r0, #C_FLAGS_X // test xm mode
orrne r1, #MCAF_FADE // XM starts fade immediately on note-off
strb r1, [r6, #MCA_FLAGS]
skip_noteoff:
tst r5, #MF_NOTECUT // test notecut bit
movne r0, #0 // clear volume
strneb r0, [r7, #MCH_VOLUME] // on note-cut
bic r5, #MF_START // clear start flag
strb r5, [r7, #MCH_FLAGS] // save flags
b mmUpdateChannel_TN_
@************************************************************
mmUpdateChannel_TN: // for other ticks
@************************************************************
push {lr}
mmUpdateChannel_TN_:
ldrb r0, [r7, #MCH_ALLOC] // get channel
cmp r0, #255 //
bge mmUpdateChannel_TN___ // no channel!
ldr r6,=mm_achannels //
ldr r6, [r6] //
mov r1, #MCA_SIZE //
mla r6, r0, r1, r6 //
mmUpdateChannel_TN___:
movge r6, #0
ldr r5, [r7, #MCH_PERIOD] // r5 will be used to hold the period
ldr r1,=mpp_vars
mov r0, #0
strb r0, [r1, #MPV_SAMPOFF] // clear variables
strb r0, [r1, #MPV_VOLPLUS]
strb r0, [r1, #MPV_PANPLUS]
strb r0, [r1, #MPV_NOTEDELAY]
//---------------------------------------------
// Update Volume Commands
//---------------------------------------------
ldrb r0, [r7, #MCH_FLAGS]
tst r0, #MF_HASVCMD
ldrne r1,=mpp_Process_VolumeCommand
movne lr, pc
bxne r1
//blne mpp_Process_VolumeCommand
//---------------------------------------------
// Update Effects
//---------------------------------------------
ldrb r0, [r7, #MCH_FLAGS]
tst r0, #MF_HASFX
ldrne r1,=mpp_Process_Effect
movne lr, pc
bxne r1
//blne mpp_Process_Effect
//---------------------------------------------
cmp r6, #0
beq no_achn
ldrh r0, [r7, #MCH_VOLUME] // read volume & cvolume
and r1, r0, #255 // mask volume
mov r0, r0, lsr#8 // mask cvolume
mul r0, r1, r0 // multiply together
mov r0, r0, lsr#5 // shift
strb r0, [r6, #MCA_VOLUME] // save in achn volume
ldr r1,=mpp_vars //
ldrsb r2, [r1, #MPV_VOLPLUS] // read volume addition
adds r0, r2, lsl#3 // add to volume
movmi r0, #0
cmp r0, #129
movcs r0, #128
strb r0, [r1, #MPV_AFVOL] // store in immediate vol
ldrb r0, [r1, #MPV_NOTEDELAY]// read note delay
cmp r0, #0 // dont update if nonzero
beq channel_update_achn
ldrb r0, [r6, #MCA_FLAGS]
orr r0, #MCAF_UPDATED
strb r0, [r6, #MCA_FLAGS]
b no_achn
channel_update_achn:
ldrb r0, [r7, #MCH_PANNING] // copy panning
strb r0, [r6, #MCA_PANNING]
ldr r0, [r7, #MCH_PERIOD] // copy period
str r0, [r6, #MCA_PERIOD]
mov r0, #0
strh r0, [r1, #MPV_PANPLUS] // WHAT IS THIS??? "@ <---- RESERVED FOR LATER USE, CLEAR TO ZERO TEMPORARILY"
ldrb r0, [r6, #MCA_FLAGS]
orr r0, #MCAF_UPDATED
strb r0, [r6, #MCA_FLAGS]
push {r4}
ldrb r4, [r7, #MCH_ALLOC]
ldr r1,=mpp_Update_ACHN_notest
mov lr, pc
bx r1
pop {r4}
no_achn:
pop {lr}
bx lr
@***********************************************************
mmChannelStartACHN: // returns r2=note
@***********************************************************
ldrb r2, [r7, #MCH_BFLAGS+1] // clear tremor/cutvol
bic r2, #0b110
strb r2, [r7, #MCH_BFLAGS+1]
cmp r6, #0 // achn==0?
beq 1f // then skip this part
mov r0, #ACHN_FOREGROUND // set foreground type
strb r0, [r6, #MCA_TYPE]
ldrb r0, [r6, #MCA_FLAGS] // read flags
bic r0, #0b11000000 // clear SUB, EFFECT
ldr r1,=mpp_clayer // get layer
ldrb r1, [r1]
orr r0, r1, lsl#6 // orr into flags
orr r0, r10, r0, lsl#8 // orr PARENT
strh r0, [r6, #MCA_PARENT] // store parent/flags
ldrb r0, [r7, #MCH_INST] // copy instrument
strb r0, [r6, #MCA_INST]
1: ldreqb r0, [r7, #MCH_INST]
subs r0, #1
bcc invalid_instrument
ldr r2, [r8, #MPL_SONGADR] // get instrument pointer
ldr r1, [r8, #MPL_INSTTABLE]
ldr r0, [r1, r0, lsl#2]
add r0, r2
ldrb r2, [r7, #MCH_PNOTE] // get pattern note
ldrh r1, [r0, #C_MASI_MAP] // read notemap offset
tst r1, #0x8000 // test MSB
beq full_notemap // if set: notemap doesnt exist!
// use single entry
cmp r6, #0 // if channel is valid
strneb r1, [r6, #MCA_SAMPLE] // write sample value
strb r2, [r7, #MCH_NOTE] // write note value (without notemap, all entries == PNOTE)
bx lr // return
full_notemap:
add r0, r2, lsl#1 // add note offset
ldrh r2, [r0, r1] // read notemap entry [instr+note*2+notemap_offset]
strb r2, [r7, #MCH_NOTE] // write note value
cmp r6, #0 // if channel is valid
mov r0, r2, lsr#8 // write sample value
strneb r0, [r6, #MCA_SAMPLE] // ..
and r2, #255
invalid_instrument:
bx lr // return
/**********
cmp r6, #0 // read notemap [sample]
ldrneb r2, [r0, #C_MASI_MAP+1]
strneb r2, [r6, #MCA_SAMPLE]
//invalid_instrument: // BUG???
ldrb r2, [r0, #C_MASI_MAP] // read notemap [note]
strb r2, [r7, #MCH_NOTE]
invalid_instrument:
bx lr
**************/
.global mmGetPeriod
@***********************************************************
mmGetPeriod:
@***********************************************************
ldrb r0, [r8, #MPL_FLAGS]
lsrs r0, #C_FLAGS_SS
bcs get_linear_period // tuning not used here with linear periods
get_amiga_period:
adr r3, note_table_mod // get octave/mod from note
ldrb r0, [r3, r2]
sub r3, #3*10
ldrb r2, [r3, r2, lsr#2]
// r0 = (note mod 12) << 1
// r1 = tuning
// r2 = (note / 12)
ldr r3,=ST3_FREQTABLE // read st3 table entry
ldrh r0, [r3, r0]
mov r3, #0x00AB0 // r3 = 133808
orr r3, #0x20000
mul r0, r3, r0 // multiply by magic number...
mov r0, r0, lsr r2 // shift by octave
cmp r1, #0
beq 1f
swi SWI_DIVIDE<<16 // divide value / tuning
1: bx lr
.global note_table_oct // remove this, make this static
.global note_table_mod // remove this, make this staic
note_table_oct:
.byte 0,0,0,1,1,1,2,2,2,3,3,3,4,4,4,5,5,5, 6,6,6 ,7,7,7,8,8,8,9,9,9
note_table_mod:
.byte 0,2,4,6,8,10,12,14,16,18,20,22,0,2,4,6,8,10,12,14,16,18,20,22,0,2,4,6,8,10,12,14,16,18,20,22,0,2,4,6,8,10,12,14,16,18,20,22,0,2,4,6,8,10,12,14,16,18,20,22,0,2,4,6,8,10,12,14,16,18,20,22,0,2,4,6,8,10,12,14,16,18,20,22,0,2,4,6,8,10,12,14,16,18,20,22,0,2,4,6,8,10,12,14,16,18,20,22,0
.align 2
get_linear_period:
ldr r1,=IT_PitchTable
ldr r0, [r1, r2, lsl#2]
bx lr
.pool
|
afska/beat-beast
| 4,700
|
butano/hw/3rd_party/maxmod/source/mm_main.s
|
/****************************************************************************
* __ *
* ____ ___ ____ __ ______ ___ ____ ____/ / *
* / __ `__ \/ __ `/ |/ / __ `__ \/ __ \/ __ / *
* / / / / / / /_/ /> </ / / / / / /_/ / /_/ / *
* /_/ /_/ /_/\__,_/_/|_/_/ /_/ /_/\____/\__,_/ *
* *
* Copyright (c) 2008, Mukunda Johnson (mukunda@maxmod.org) *
* *
* Permission to use, copy, modify, and/or distribute this software for any *
* purpose with or without fee is hereby granted, provided that the above *
* copyright notice and this permission notice appear in all copies. *
* *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES *
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR *
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES *
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN *
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. *
****************************************************************************/
/******************************************************************************
*
* Definitions
*
******************************************************************************/
#include "../asm_include/mm_gba_setup.inc"
#include "../asm_include/mp_defs.inc"
#include "../asm_include/mp_mas.inc"
#include "../asm_include/mp_mas_structs.inc"
#include "../asm_include/mp_macros.inc"
/******************************************************************************
*
* Memory
*
******************************************************************************/
.BSS
.ALIGN 2
/******************************************************************************
* mmCallback
*
* Function pointer to user event handler
******************************************************************************/
.global mmCallback
mmCallback: .space 4
/******************************************************************************
* mm_ch_mask
*
* Bitmask to select which hardware/software channels can be used
******************************************************************************/
.global mm_ch_mask
mm_ch_mask: .space 4
/******************************************************************************
*
* Program
*
******************************************************************************/
/******************************************************************************
* mpp_call_*
*
* Functions to branch to a register
******************************************************************************/
//-----------------------------------------------------------------------------
.TEXT
.THUMB
.ALIGN 2
//-----------------------------------------------------------------------------
.global mpp_call_r7, mpp_call_r1, mpp_call_r2, mpp_call_r3
.thumb_func
@------------------------------------------------------------------------------
mpp_call_r7: bx r7
@------------------------------------------------------------------------------
.thumb_func
@------------------------------------------------------------------------------
mpp_call_r1: bx r1
@------------------------------------------------------------------------------
.thumb_func
@------------------------------------------------------------------------------
mpp_call_r2: bx r2
@------------------------------------------------------------------------------
.thumb_func
@------------------------------------------------------------------------------
mpp_call_r3: bx r3
@------------------------------------------------------------------------------
/******************************************************************************
* mmSetEventHandler
*
* Set function for handling playback events
******************************************************************************/
.global mmSetEventHandler
.thumb_func
mmSetEventHandler:
ldr r1,=mmCallback
str r0, [r1]
bx lr
//-----------------------------------------------------------------------------
.end
//-----------------------------------------------------------------------------
|
afska/beat-beast
| 7,647
|
butano/hw/3rd_party/maxmod/source_gba/mm_main_gba.s
|
/****************************************************************************
* __ *
* ____ ___ ____ __ ______ ___ ____ ____/ / *
* / __ `__ \/ __ `/ |/ / __ `__ \/ __ \/ __ / *
* / / / / / / /_/ /> </ / / / / / /_/ / /_/ / *
* /_/ /_/ /_/\__,_/_/|_/_/ /_/ /_/\____/\__,_/ *
* *
* Copyright (c) 2008, Mukunda Johnson (mukunda@maxmod.org) *
* *
* Permission to use, copy, modify, and/or distribute this software for any *
* purpose with or without fee is hereby granted, provided that the above *
* copyright notice and this permission notice appear in all copies. *
* *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES *
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR *
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES *
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN *
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. *
****************************************************************************/
/******************************************************************************
*
* Definitions
*
******************************************************************************/
#include "../asm_include/mm_gba_setup.inc"
#include "../asm_include/mp_defs.inc"
#include "../asm_include/mp_mas.inc"
#include "../asm_include/mp_mas_structs.inc"
#include "../asm_include/mp_macros.inc"
#include "../asm_include/mp_mixer_gba.inc"
/******************************************************************************
*
* Memory
*
******************************************************************************/
.BSS
.ALIGN 2
/******************************************************************************
* mm_vblank_function
*
* Pointer to a user function to be called during the vblank irq
******************************************************************************/
.global mm_vblank_function
mm_vblank_function: .space 4
/******************************************************************************
*
* Program
*
******************************************************************************/
/******************************************************************************
* mpp_call_*
*
* Functions to branch to a register
******************************************************************************/
.section ".iwram", "ax", %progbits
.thumb
.align 2
.global mpp_call_r7i, mpp_call_r2i, mpp_call_r1i
.thumb_func
//-----------------------------------------------------------------------------
mpp_call_r7i: bx r7
//-----------------------------------------------------------------------------
.thumb_func
//-----------------------------------------------------------------------------
mpp_call_r2i: bx r2
//-----------------------------------------------------------------------------
.thumb_func
//-----------------------------------------------------------------------------
mpp_call_r1i: bx r1
//-----------------------------------------------------------------------------
.BSS
.ALIGN 2
/******************************************************************************
* mp_solution
*
* Address of soundbank in memory/rom
******************************************************************************/
.global mp_solution
mp_solution: .space 4
.TEXT
.THUMB
.ALIGN 2
/******************************************************************************
* mmInit(system)
*
* Initialize maxmod
******************************************************************************/
.global mmInit
.thumb_func
mmInit:
push {lr}
ldr r2,=mp_solution
mov r1, #MM_GBA_SYSTEM_SOUNDBANK
ldr r1, [r0,r1]
str r1, [r2]
ldr r2,=mm_achannels
ldr r1, [r0,#MM_GBA_SYSTEM_ACTCH]
str r1, [r2]
ldr r1, [r0,#MM_GBA_SYSTEM_MODCH]
str r1, [r2,#4]
ldr r1, [r0,#MM_GBA_SYSTEM_MCH_COUNT]
str r1, [r2,#8]
ldr r1, [r0,#MM_GBA_SYSTEM_ACH_COUNT]
str r1, [r2,#12]
bl mmMixerInit @ initialize software/hardware mixer
ldr r1,=mm_num_ach
ldr r1,[r1]
mov r0,#1
lsl r0, r1
sub r0,#1
ldr r1,=mm_ch_mask
str r0, [r1]
ldr r0,=0x400 //
bl mmSetModuleVolume
ldr r0,=0x400 //
bl mmSetJingleVolume
ldr r0,=0x400 //
bl mmSetEffectsVolume //
ldr r0,=0x400
bl mmSetModuleTempo
ldr r0,=0x400
bl mmSetModulePitch
bl mmResetEffects
ret0
/******************************************************************************
* mmSetVBlankHandler
*
* Set function to be called during the vblank IRQ
******************************************************************************/
.global mmSetVBlankHandler
.thumb_func
mmSetVBlankHandler:
ldr r1,=mm_vblank_function
str r0, [r1]
bx lr
/******************************************************************************
* mmFrame()
*
* Work routine, user _must_ call this every frame.
******************************************************************************/
.global mmFrame
.thumb_func
mmFrame:
push {lr}
push {r4-r7}
@ update effects
ldr r7,=mmUpdateEffects
bl _call_via_r7
@ update sub layer
@ sub layer has 60hz accuracy
ldr r7,=mppUpdateSub
bl _call_via_r7
@ update main layer and mix samples.
@ main layer is sample-accurate.
ldr r0,=mpp_channels @ copy channels
ldr r1,=mm_pchannels
ldr r1,[r1]
str r1, [r0]
ldr r0,=mpp_nchannels @ copy #channels
ldr r1,=mm_num_mch
ldr r1,[r1]
strb r1, [r0]
ldr r0,=mpp_clayer @ layer=0 (main)
mov r1, #0
strb r1, [r0]
ldr r0,=mmLayerMain @mpp_layerA @ copy layer pointer
ldr r1,=mpp_layerp
str r0, [r1]
ldr r4,=mm_mixlen
ldr r4,[r4]
@ mixlen is divisible by 2
ldrb r1, [r0, #MPL_ISPLAYING] @ check if main layer is active
cmp r1, #0
beq .mpf_no_mainlayer @ skip processing if disabled (and just mix samples)
.mpf_mix_advr:
ldr r0,=mpp_layerp @ get layer
ldr r0, [r0]
mov r1, #MPL_TICKRATE @ get samples/tick
ldrh r5, [r0, r1]
mov r1, #MPL_SAMPCOUNT @ get sample count
ldrh r6, [r0,r1]
sub r5, r6 @ calc tickrate-counter
cmp r5, #0
bge 1f
mov r5, #0
1: cmp r5, r4 @ > mixlen?
blt .mpf_mix_adv @ no, mix and process tick
b .mpf_mix @ yes, mix the rest of samples
.mpf_mix_adv:
mov r1, #MPL_SAMPCOUNT @ reset sample counter
mov r7, #0 @
strh r7, [r0,r1] @
sub r4, r5 @ subtract from #samples to mix
PROF_START
mov r0, r5
ldr r7,=mmMixerMix @ mix samples
bl _call_via_r7
PROF_END 0
ldr r7,=mppProcessTick
bl _call_via_r7
b .mpf_mix_advr @ process more samples
.mpf_mix:
@ add samples remaining to SAMPCOUNT
@ and mix more samples
mov r1, #MPL_SAMPCOUNT
add r6, r4
strh r6, [r0, r1]
mov r0, r4
PROF_START
ldr r1,=mmMixerMix
bl _call_via_r1
PROF_END 0
pop {r4-r7}
ret1 @ return to user
.mpf_no_mainlayer:
@ main layer isn't active,
@ mix full amount
mov r0, r4
PROF_START
ldr r1,=mmMixerMix
bl _call_via_r1
PROF_END 0
pop {r4-r7}
ret1
.pool
//-----------------------------------------------------------------------------
.end
//-----------------------------------------------------------------------------
|
afska/beat-beast
| 3,334
|
butano/hw/3rd_party/maxmod/source_gba/mm_init_default.s
|
/****************************************************************************
* __ *
* ____ ___ ____ __ ______ ___ ____ ____/ / *
* / __ `__ \/ __ `/ |/ / __ `__ \/ __ \/ __ / *
* / / / / / / /_/ /> </ / / / / / /_/ / /_/ / *
* /_/ /_/ /_/\__,_/_/|_/_/ /_/ /_/\____/\__,_/ *
* *
* Nintendo DS & Gameboy Advance Sound System *
* *
* Copyright (c) 2008, Mukunda Johnson (mukunda@maxmod.org) *
* *
* Permission to use, copy, modify, and/or distribute this software for any *
* purpose with or without fee is hereby granted, provided that the above *
* copyright notice and this permission notice appear in all copies. *
* *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES *
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR *
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES *
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN *
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. *
****************************************************************************/
.global mmInitDefault
@----------------------------------------------------------------------------
#include "../asm_include/mm_gba_setup.inc"
#include "../asm_include/mp_defs.inc"
.equ mixlen, 1056 // 16khz
.bss
.align 2
__mixbuffer:
.space mixlen
.text
.thumb
.align 2
#define MM_SIZEOF_MODCH 40
#define MM_SIZEOF_ACTCH 28
#define MM_SIZEOF_MIXCH 24
/****************************************************************************
* mmInitDefault( soundbank, #channels )
*
* Init maxmod with default settings.
****************************************************************************/
.thumb_func
mmInitDefault:
push {r0,r4,r5,r6,r7,lr} // preserve regs, push soundbank
//0 mode (3)
//1 mchcount (#channels)
//2 achcount (#channels)
//3 modch
//4 actch
//5 mixch
//6 mixmem (__mixbuffer)
//7 wavemem
mov r6, r1 // r6=#channels
ldr r0,=MM_SIZEOF_MODCH+MM_SIZEOF_ACTCH+MM_SIZEOF_MIXCH
mul r0, r6
ldr r4,=mixlen
add r0, r4
bl malloc
mov r7, r0 // wavemem = beginning of buffer
add r3, r0, r4 // split up buffer into addresses [r3,r4,r5]
mov r0, #MM_SIZEOF_MODCH //
mul r0, r6 //
add r4, r3, r0 //
mov r0, #MM_SIZEOF_ACTCH //
mul r0, r6 //
add r5, r4, r0 //
mov r0, #3 //
mov r1, r6 //
mov r2, r6 //
ldr r6,=__mixbuffer // r6 = mixbuffer (iwram)
push {r0-r7}
mov r0, sp // init maxmod, pass init struct
bl mmInit //
add sp, #MM_GBA_SYSTEM_SIZE // restore stack
pop {r4-r7} // return
pop {r0} //
bx r0 //
.pool
|
afska/beat-beast
| 36,515
|
butano/hw/3rd_party/maxmod/source_gba/mm_mixer_gba.s
|
/****************************************************************************
* __ *
* ____ ___ ____ __ ______ ___ ____ ____/ / *
* / __ `__ \/ __ `/ |/ / __ `__ \/ __ \/ __ / *
* / / / / / / /_/ /> </ / / / / / /_/ / /_/ / *
* /_/ /_/ /_/\__,_/_/|_/_/ /_/ /_/\____/\__,_/ *
* *
* GBA Audio System *
* *
* Copyright (c) 2008, Mukunda Johnson (mukunda@maxmod.org) *
* *
* Permission to use, copy, modify, and/or distribute this software for any *
* purpose with or without fee is hereby granted, provided that the above *
* copyright notice and this permission notice appear in all copies. *
* *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES *
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR *
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES *
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN *
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. *
****************************************************************************/
#include "../asm_include/mm_gba_setup.inc"
@ DEFINITIONS
#include "../asm_include/mp_macros.inc"
#include "../asm_include/mp_format_mas.inc"
#include "../asm_include/mp_defs.inc"
@ timer freq = 2^24 / mixfreq
@ mixlen ~= mixfreq * 0.01673
@ recommended mixing frequencies: 5734,7884,10512,13379,15768,18157,21024,26758,31536,36314,40137,42048
@ other mixing frequencies may cause clicks
@ mixlen must be divisible by 2
@==================================================================
@ GLOBAL SYMBOLS
@==================================================================
.global mmVBlank
.type mmVBlank STT_FUNC
.global mmMixerMix
.type mmMixerMix STT_FUNC
.global mmMixerSetSource
.type mmMixerSetSource STT_FUNC
.global mmMixerSetRead
.type mmMixerSetRead STT_FUNC
.global mmMixerSetFreq
.type mmMixerSetFreq STT_FUNC
.global mmMixerStopChannel
.type mmMixerStopChannel STT_FUNC
.global mmMixerInit
.type mmMixerInit STT_FUNC
.global mmMixerChannelActive
.type mmMixerChannelActive STT_FUNC
.global mmMixerMulFreq
.type mmMixerMulFreq STT_FUNC
.global mmMixerSetVolume
.type mmMixerSetVolume STT_FUNC
.global mmMixerSetPan
.type mmMixerSetPan STT_FUNC
// .global mm_freqscalar
.global mm_mixlen
.global mm_bpmdv
.global mp_mix_seg
.global mp_writepos
.global mm_mixchannels
@===============================================
@ more definitions
@===============================================
.EQU REG_SOUNDCNT_L, 0x4000080
.EQU REG_SOUNDCNT_H, 0x4000082
.EQU REG_SOUNDCNT_X, 0x4000084
.EQU REG_TM0CNT, 0x4000100
.EQU REG_DMA1SAD, 0x40000BC
.EQU REG_DMA1DAD, 0x40000C0
.EQU REG_DMA1CNT, 0x40000C4
.EQU REG_DMA2SAD, 0x40000C8
.EQU REG_DMA2DAD, 0x40000CC
.EQU REG_DMA2CNT, 0x40000D0
.EQU REG_DMA3SAD, 0x40000D4
.EQU REG_DMA3DAD, 0x40000D8
.EQU REG_DMA3CNT, 0x40000DC
.EQU REG_SGFIFOA, 0x40000A0
.EQU REG_SGFIFOB, 0x40000A4
.EQU REG_VCOUNT, 0x4000006
@ MIXER CHANNEL FORMAT
.equ CHN_SIZE, 24
.equ CHN_SRC,0
.equ CHN_READ,4
.equ CHN_VOL,8
.equ CHN_PAN,9
// 10
// 11
.equ CHN_FREQ,12
.equ CHN_SIZE,16
/////////////////////.equ CHN_LOOP,8
/////////////////////.equ CHN_LEN,16
@-------------------------------------
.equ FETCH_SIZE, 384
.equ FETCH_THRESHOLD, (6016)//7040 // frequency threshold (dont use fetch for high freqs!)
@======================================================================
@ MEMORY
@======================================================================
.section .bss
.align 2
mp_writepos: .space 4 @ wavebuffer write position
mm_mixbuffer: .space 4 @ dont move (see init)
mm_mixchannels: .space 4 @ dont move
mm_wavebuffer: .space 4 @ dont move
mm_mixlen: .space 4 @ dont move
mm_mixch_count: .space 4 @ dont move
mm_mixch_end: .space 4 @ dont move
mm_ratescale: .space 4 @ dont move
mm_timerfreq: .space 4 @ dont move
mm_bpmdv: .space 4
mp_mix_seg: .space 1 @ mixing segment select
.align 2
mm_fetch: .space FETCH_SIZE+16
@ 11-bit mixed sample buffer
@ data is interleaved
@ left,left,right,right,left,left,etc...
@===========================================================================
@ PROGRAM
@===========================================================================
.section .iwram, "ax", %progbits
.ARM
.ALIGN 2
mpm_nullsample:
.byte 128
.align 2
@-----------------------------------------------------------------------------------------------------
mmVBlank: @ vblank wrapper, used to reset dma...HIGH PRIORITY PLEASE!
@-----------------------------------------------------------------------------------------------------
b .mpvb_disabled @ disable until ready.. (overwrite this area with NOP)
ldr r0,=mp_mix_seg @ swap mixing segmentl
ldrsb r1, [r0]
mvns r1, r1
strb r1, [r0]
beq .mpvb_exit
ldr r1,=0x040000c6 @ dma control RESTART DMA
ldr r0,=0x0440 @ disable dma
strh r0, [r1]
strh r0, [r1,#12]
ldr r0,=0xB600 @ restart dma
strh r0, [r1]
strh r0, [r1,#12]
b .mpvb_dontreset
.mpvb_exit:
ldr r0,=mp_writepos @ restart write position
@ ldr r1,=mp_playbuffer_l @ ...
ldr r1,=mm_wavebuffer
ldr r1, [r1]
str r1, [r0] @ ...
.mpvb_dontreset:
.mpvb_disabled:
ldr r0,=0x3007FF8 @ acknowledge interrupt
ldrh r2, [r0]
orr r2, r2, #0x1
strh r2, [r0]
ldr r0,=mm_vblank_function
ldr r0, [r0]
cmp r0, #0
bxeq lr
bx r0
.pool
.align 2
@-------------------------------------------------------------------------
mmMixerMix: @ params={ samples_count }
@-------------------------------------------------------------------------
@ exit function if samples == 0
@ it will malfunction.
cmp r0, #0
bne .mp_zerocheck
bx lr
.mp_zerocheck:
@ preserve registers
stmfd sp!, {r4-r11,lr}
stmfd sp!, {r0} @ preserve mixing count
@------------------------------------------------------------------------
@ SECTOR 0, INITIALIZATION
@------------------------------------------------------------------------
@ clear mixing buffers
and r10, r0, #7
mov r2, r0, lsr#3 @ clearing samps*2*2 bytes (hword*stereo) 32 bytes at a time
ldr r0,=mm_mixbuffer
ldr r0,[r0]
mov r1, #0 @ zero variable
mov r3, r1
mov r4, r1
mov r5, r1
mov r6, r1
mov r7, r1
mov r8, r1
mov r9, r1
cmp r2, #0
beq 2f
@ clear 32 bytes/write
1: stmia r0!, {r1,r3-r9}
subs r2, r2, #1
bne 1b
2:
@ clear remainder
cmp r10, #0
beq 2f
1: str r1, [r0], #4
subs r10, r10, #1
bne 1b
2:
@----------------------------------------------------------------------------------
@ BEGIN MIXING ROUTINE
@----------------------------------------------------------------------------------
ldr r12,=mm_mixchannels
ldr r12,[r12]
mov r11, #0 @ volume addition
@--------------------
.mpm_cloop:
@--------------------
@----------------------------------------------------------------------
@ SECTOR 1, CALCULATIONS
@----------------------------------------------------------------------
@ aliases
#define rchan r12
#define rvolA r11
#define rsrc r10
#define rfreq r9
#define rmixb r8
#define rread r7
#define rvolL r5
#define rvolR r6
#define rmixc r4
#define rmixcc r3
@ read source address
ldr rsrc, [rchan, #CHN_SRC]
cmp rsrc, #0
bmi .mpm_next @ EXIT if MSB is set ------------>
@ read frequency value
ldr rfreq, [rchan, #CHN_FREQ]
cmp rfreq, #0
beq .mpm_next @ EXIT if zero ----------------=->
ldr r0,=mm_ratescale
ldr r0, [r0]
mul rfreq, r0
lsr rfreq, #14
@ load mixing buffers
ldr rmixb,=mm_mixbuffer
ldr rmixb,[rmixb]
@ get read position
ldr rread, [rchan, #CHN_READ]
@ calculate volume
ldrb rvolR,[rchan, #CHN_VOL] @ volume = 0-255
ldrb r0, [rchan, #CHN_PAN] @ pan = 0-255
rsb r0, r0, #256
mul rvolL, r0, rvolR @ (vol*pan) = right volume
mov rvolL, rvolL, lsr#8
add rvolA, rvolA, rvolL @ add to volume counter
rsb r0, r0, #256
mul rvolR, r0, rvolR @ calc left volume (256-pan)*vol
mov rvolR, rvolR, lsr#8
add rvolA, rvolA, rvolR, lsl#16
ldr rmixc, [sp] @ get mix count
@****************************************************************
.mpm_remix_test:
@****************************************************************
mov r2, #0
mul r1, rmixc, rfreq // get number of samples that will be read
cmp rfreq, #FETCH_THRESHOLD
bge 1f
cmp r1, #FETCH_SIZE<<12 // check if its > fetch size
movhi r1, #FETCH_SIZE<<12 // if so: clamp to fetch size and set flag
movhi r2, #1
1:
// ldr r0, [rchan, #CHN_LEN] // now subtract length - read to get # samples remaining
ldr r0, [rsrc, #-C_SAMPLE_DATA+C_SAMPLE_LEN]
rsb r0, rread, r0, lsl#SAMPFRAC
// sub r0, r0, rread // in the source
cmp r1, r0 // clamp mix count
movhi r1, r0
bhi .calc_mix
cmp r2, #0
beq .mpm_mix_full
.calc_mix:
push {r1} // preserve sample count
//--------------------------------
.macro DIV_ITER shift
//--------------------------------
cmp r0, rfreq, lsl#\shift
subcs r0, rfreq, lsl#\shift
addcs r2, #1<<\shift
.endm
//--------------------------------
.macro DIVIDER shift
//--------------------------------
DIV_ITER \shift
.if \shift != 0
DIVIDER (\shift-1)
.endif
.endm
//--------------------------------
mov r0, r1 // divide samples / frequency (24bit/16bit)
mov r2, #0
1: subs r0, rfreq, lsl#16 // divide top part
addcs r2, #1<<16
bcs 1b
add r0, rfreq, lsl#16
DIVIDER 15 // divide the rest...
cmp r0, #1 // round up result
adc r0, r2, #0
// mov r0,r1
// mov r1,rfreq
// swi 0x060000
// cmp r1, #0
// addne r0, #1
pop {r1} // restore sample count
sub rmixc, r0 // subtract from mixcount
mov rmixcc, r0
b .mpm_mix_short
@------------------------------------------------------------------------
@ SECTOR 2, MIXING
@------------------------------------------------------------------------
@-----------------------------------------
.mpm_mix_full:
@-----------------------------------------
@ mix all samples
mov rmixcc, rmixc @ <-- move mixing count
mov rmixc, #0 @ clear mixing count
.mpm_mix_short:
@------------------------------------------------------
.mpm_remix:
@------------------------------------------------------
@ mix samples...
@ preserve registers
stmfd sp!, {rmixc,rvolA,rchan}
@ zero mixing count??
cmp rmixcc, #0
beq .mpm_mix_complete @ exit -------->
cmp rfreq, #FETCH_THRESHOLD
bge .dont_use_fetch
/*
ldr r0,=mm_fetch // transfer samples from ROM to RAM
add r1, #2<<14 // add threshold for safety
ldr r2,=REG_DMA3SAD
str r0, [r2, #4]
add r0, r10, rread, lsr#12
bic r0, #0b11
str r0, [r2, #0]
mov r0, #(1<<31)+(1<<26)
add r0, r1, lsr#14
str r0, [r2, #8]
b fooo
*/
// [cycle timings assume 3,1 ROM waitstates]
push {r3-r12}
// r10 is SRC!
ldr r0,=mm_fetch // destination
add r10, r10, rread, lsr#12 // add read offset to source
bic r10, #0b11 // align to 32 bits
add r1, #4<<12 // add safety threshold
subs r1, #40<<12 // subtract 36
bcc .exit_fetch // skip large fetch if negative
.fetch: ldmia r10!, {r2-r9,r11,r14} // read 40 samples [44 cycles]
stmia r0!, {r2-r9,r11,r14} // write 40 samples [11 cycles]
subs r1, #40<<12 // count [1 cycle ]
bcc .exit_fetch // exit if done [1 cycle ]
ldmia r10!, {r2-r9,r11,r14} // read 40 samples [44 cycles]
stmia r0!, {r2-r9,r11,r14} // write 40 samples [11 cycles]
subs r1, #40<<12 // count [1 cycle ]
bcc .exit_fetch // exit if done [1 cycle ]
ldmia r10!, {r2-r9,r11,r14} // read 40 samples [44 cycles]
stmia r0!, {r2-r9,r11,r14} // write 40 samples [11 cycles]
subs r1, #40<<12 // count [1 cycle ]
bcs .fetch // loop if remaining [3 cycles]
// [173 cycles/120 samples]
.exit_fetch:
adds r1, #(40<<12)-(24<<12)
bmi .end_medfetch
.medfetch:
ldmia r10!, {r2-r7} // read 24 samples [26]
stmia r0!, {r2-r7} // write 24 samples [7 ]
subs r1, #24<<12 // count [1 ]
bcc .end_medfetch // exit if done [1 ]
ldmia r10!, {r2-r7} // read 24 samples [26]
stmia r0!, {r2-r7} // write 24 samples [7 ]
subs r1, #24<<12 // count [1 ]
bcc .end_medfetch // exit if done [1 ]
ldmia r10!, {r2-r7} // read 24 samples [26]
stmia r0!, {r2-r7} // write 24 samples [7 ]
subs r1, #24<<12 // count [1 ]
bcs .medfetch // loop [3 ]
.end_medfetch: // [107]
adds r1, #24<<12 // add 24 back
bmi .end_fetch // exit if <= 0
.fetchsmall:
ldr r2, [r10], #4 // read 4 samples [8]
str r2, [r0], #4 // write 4 samples [2]
subs r1, #4<<12 // count [1]
ble .end_fetch // exit maybe [1]
ldr r2, [r10], #4 // read 4 samples [8]
str r2, [r0], #4 // write 4 samples [2]
subs r1, #4<<12 // count [1]
bgt .fetchsmall // exit maybe [3]
.end_fetch:
pop {r3-r12} // restore regs
fooo:
mov r0, rread, lsr#12 // get read integer
push {r0, rsrc} // preserve regs
bic rread, r0, lsl#12 // clear integer
and r0, #0b11 // mask low bits
ldr rsrc,=mm_fetch //
add rsrc, rsrc, r0 // offset source (fetch is word aligned!)
.dont_use_fetch:
tst rmixb, #0b11 // test alignment of work output
beq .mpm_aligned
#define rsamp1 r1
#define rsampa r0
#define rsampb r2
@ routine to WORD align mixing sector
ldrb rsampa, [rsrc, rread, lsr#SAMPFRAC] @ load sample
add rread, rread, rfreq @ add frequency
mul rsampb, rsampa, rvolL @ multiply by left volume
ldrh rsamp1, [rmixb] @ add to mixing buffer (left)
add rsamp1, rsamp1, rsampb, lsr#5
strh rsamp1, [rmixb], #4
mul rsampb, rsampa, rvolR @ multiply by right volume
ldrh rsamp1, [rmixb] @ add to mixing buffer (right)
add rsamp1, rsamp1, rsampb, lsr#5
strh rsamp1, [rmixb], #2
sub rmixcc, rmixcc, #1 @ decrement mix count
#undef rsamp1
#undef rsampa
#undef rsampb
.mpm_aligned:
// determine mixing mode
cmp rvolL, rvolR // if volume_left == volume_right then assume 'center' mixing
beq .mpm_mix_ac
cmp rvolL, #0 // if left volume is zero, do 'right' mixing
beq .mpm_mix_ar
cmp rvolR, #0 // if right volume is zero, do 'left' mixing
beq .mpm_mix_al
b mmMix_ArbPanning // otherwise do arb mixing
.mpm_mix_al:
b mmMix_HardLeft
.mpm_mix_ar:
b mmMix_HardRight
@ center mixing------------
.mpm_mix_ac:
cmp rvolL, #0 // check if volume is zero
bne mmMix_CenteredPanning // mix samples if not zero
b mmMix_Skip // skip samples if zero
.mpm_mix_complete:
cmp rfreq, #FETCH_THRESHOLD
poplt {r0, rsrc} // restore regs
addlt rread, rread, r0, lsl#12 // add old integer to read
ldmfd sp!, {rmixc,rvolA,rchan} // restore more regs
ldr r1, [rsrc, #-C_SAMPLE_DATA+C_SAMPLE_LEN]
lsl r1, #SAMPFRAC
//ldr r1, [rchan, #CHN_LEN] // check length against position
cmp r1, rread
bgt .mpm_channelfinished
// ldr r1, [rchan, #CHN_LOOP] // read channel loop
ldr r1, [rsrc, #-C_SAMPLE_DATA+C_SAMPLE_LOOP]
cmp r1, #0
// movs r1, r1, lsl#8 // mask out high byte (that is VOLUME)
bmi .mpm_channel_stop // MSB = no loop, stop channel ->
sub rread,rread,r1,lsl#(SAMPFRAC) // subtract loop length (<<SAMPFRAC) from position
cmp rmixc, #0 // mix more samples?
ble .mpm_channelfinished // no ->
b .mpm_remix_test // yes: loop
@----------------------------------------------------------------
.mpm_channel_stop:
@----------------------------------------------------------------
@ *** END OF SAMPLE
mov r1, #1<<31 // disable channel
str r1, [rchan, #CHN_SRC]
@ mix zero into the rest of the buffer
ldr rsrc,=mpm_nullsample // mix zero into the rest of the buffer
mov rfreq, #0 // zero freq
mov rread, #0 // zero freq
movs rmixcc, rmixc // mix remaining amount
ble .mpm_channelfinished // (exit if zero)
mov rmixc, #0
mov r1, #0
b .mpm_remix // mix 'zero' into the rest of the data
@---------------------------------------------------------------
.mpm_channelfinished:
@---------------------------------------------------------------
cmp rmixc, #0 // mix more samples?
bne .mpm_remix_test // yes: loop
@ *** END OF MIXING ***
str rread, [rchan, #CHN_READ] // save read position
@-----------------------
.mpm_next:
@-----------------------
add rchan, rchan, #CHN_SIZE // seek to next channel
ldr r0,=mm_mixch_end // compare with ending
ldr r0,[r0]
cmp rchan, r0
bne .mpm_cloop // loop if !=
@----------------------------------------------------------------------------------
@ SECTOR 3, POST-PROCESSING
@----------------------------------------------------------------------------------
#define prmixl r0
#define prwritel r2
#define prwriter r3
#define prcount r4
#define prvolR r12
#define prvolL r11
#define prsamp1 r6
#define prsamp2 r5
#define prsamp3 r7
ldr prmixl,=mm_mixbuffer
ldr prmixl,[prmixl]
ldr prwritel,=mp_writepos
ldr prwritel, [prwritel]
ldr prwriter,=mm_mixlen
ldr prwriter, [prwriter]
add prwriter, prwritel, prwriter, lsl#1 @#MP_MIXLEN*2
ldmfd sp!, {prcount}
@ get volume accumulators
mov prvolR, rvolA, lsr#16+1
mov prvolR, prvolR, lsl#3
mov prvolL, rvolA, lsl#16
mov prvolL, prvolL, lsr#16+1
mov prvolL, prvolL, lsl#3
subs prcount, prcount, #1
ble .mpm_copy2_end
@--------------------------------------------------
.mpm_copy2:
@--------------------------------------------------
@ ***************** LEFT OUTPUT ******************
ldr prsamp1, [prmixl], #4 @ get 2 mixed samples
sub prsamp2, prsamp1, prvolL @ convert to signed
mov prsamp2, prsamp2, lsl#16 @ mask low hword with sign extension
movs prsamp2, prsamp2, asr#16+3 @ and convert 11-bit to 8-bit
cmp prsamp2, #-128 @ clamp
movlt prsamp2, #-128 @
cmp prsamp2, #127 @
movgt prsamp2, #127 @
@ next sample...
rsbs prsamp3, prvolL, prsamp1,lsr#16 @ convert to signed
movs prsamp3, prsamp3, asr#3 @ convert 11-bit to 8-bit
cmp prsamp3, #-128 @ clamp
movlt prsamp3, #-128 @
cmp prsamp3, #127 @
movgt prsamp3, #127 @
and prsamp2, prsamp2, #255 @ write to output
orr prsamp2, prsamp3, lsl#8 @
strh prsamp2, [prwritel], #2 @
@ **************** RIGHT OUTPUT ******************
ldr prsamp1, [prmixl], #4 @ get 2 mixed samples
sub prsamp2, prsamp1, prvolR @ convert to signed
mov prsamp2, prsamp2, lsl#16 @ mask low hword and convert 11-bit to 8-bit
movs prsamp2, prsamp2, asr#16+3 @
cmp prsamp2, #-128 @ clamp value
movlt prsamp2, #-128 @
cmp prsamp2, #127 @
movgt prsamp2, #127 @
@ next sample...
rsbs prsamp3, prvolR, prsamp1,lsr#16 @ convert to signed
movs prsamp3, prsamp3, asr#3 @ convert 11-bit to 8-bit
cmp prsamp3, #-128 @ clamp value
movlt prsamp3, #-128 @
cmp prsamp3, #127 @
movgt prsamp3, #127 @
and prsamp2, prsamp2, #255 @ write to output
orr prsamp2, prsamp3, lsl#8 @
strh prsamp2, [prwriter], #2 @
subs prcount, prcount, #2 @ loop
bgt .mpm_copy2 @
@------------------------------------------------------------------
.mpm_copy2_end:
ldr r0,=mp_writepos @ store new write position
str prwritel, [r0]
@------------------------------------------------------------------
ldmfd sp!, {r4-r11,lr} // restore registers
bx lr // phew!
.pool
@================================================================================
@ MIXING ROUTINES
@================================================================================
.macro READ_AND_INCREMENT reg
ldrb \reg, [rsrc, rread, lsr#SAMPFRAC]
add rread, rread, rfreq
.endm
.macro READ_D reg, tmp
READ_AND_INCREMENT \reg
READ_AND_INCREMENT \tmp
orr \reg, \tmp, lsl#16
.endm
.macro MIX_D vol, tmp1, tmp2
READ_D \tmp1, \tmp2 // load&combine 2 samples
mul \tmp2, \tmp1, \vol // multiply by volume
bic \tmp2, \tmp2, #0x1F0000 // prepare for shift
.endm
.macro MIX_DA vol, target, tmp1, tmp2
MIX_D \vol, \tmp1, \tmp2
add \target, \target, \tmp2, lsr#5 // add 11-bit values
.endm
.macro MIX_DC vol, target_a, target_b, tmp1, tmp2
MIX_D \vol, \tmp1, \tmp2
add \target_a, \target_a, \tmp2, lsr#5 // add 11-bit values
add \target_b, \target_b, \tmp2, lsr#5
.endm
.macro MIX_DB vol_l, vol_r, target_a, target_b, tmp1, tmp2
READ_D \tmp1, \tmp2
.if \target_a != 0
mul \tmp2, \tmp1, \vol_l // multiply by volume
bic \tmp2, \tmp2, #0x1F0000 // prepare for shift
add \target_a, \target_a, \tmp2, lsr#5 // add 11-bit values
.endif
.if \target_b != 0
mul \tmp2, \tmp1, \vol_r // multiply by volume
bic \tmp2, \tmp2, #0x1F0000 // prepare for shift
add \target_b, \target_b, \tmp2, lsr#5 // add 11-bit values
.endif
.endm
@-----------------------------------------------------------------------------------
mmMix_Skip:
@-----------------------------------------------------------------------------------
@ mix nothing
mul r0, rmixcc, rfreq @ read += samples * frequency
add rread, rread, r0
b .mpm_mix_complete
@-----------------------------------------------------------------------------------
mmMix_HardLeft:
@-----------------------------------------------------------------------------------
@ mix hard panned left
bl mmMix_SingleChannel // mix left channel
bgt mmMix_Remainder // mix remaining amount
b .mpm_mix_complete // return
@-----------------------------------------------------------------------------------
mmMix_HardRight:
@-----------------------------------------------------------------------------------
@ hard panned right
mov rvolL, rvolR // move volume
add rmixb, rmixb, #4 // offset to 'right' data
bl mmMix_SingleChannel // mix routine
mov rvolL, #0 // clear left volume again
sub rmixb, rmixb, #4 // remove offet
bgt mmMix_Remainder // mix remaining count
b .mpm_mix_complete // return
@----------------------------------------
mmMix_SingleChannel:
@----------------------------------------
#define rsamp1 r1
#define rsamp2 r2
#define rsamp3 r11
#define rsamp4 r12
#define rsampa r0
#define rsampb r4
@ hard panned mixing (single channel mono)
@ interleaving really cuts this method's effectiveness :(
@ mix 8 samples/loop
subs rmixcc, rmixcc, #8
bmi .mpmah_8e
.mpmah_8:
ldmia rmixb, {rsamp1, rsamp2, rsamp3} // load data [2nd word not used]
MIX_DA rvolL, rsamp1, rsampa, rsampb // mix data
str rsamp1, [rmixb], #8 // store mixed word
MIX_DA rvolL, rsamp3, rsampa, rsampb // mix data
str rsamp3, [rmixb], #8 // store mixed word
ldmia rmixb, {rsamp1, rsamp2, rsamp3} // load data [2nd word not used]
MIX_DA rvolL, rsamp1, rsampa, rsampb // mix data
str rsamp1, [rmixb], #8 // store mixed word
MIX_DA rvolL, rsamp3, rsampa, rsampb // mix data
str rsamp3, [rmixb], #8 // store mixed word
subs rmixcc, rmixcc, #8 // decrement 8 samples
bpl .mpmah_8 // loop if >= 0
.mpmah_8e:
@ mix remainder samples
adds rmixcc, rmixcc, #8 // fix mixing count
bx lr // return
#undef rsamp1
#undef rsamp2
#undef rsamp3
#undef rsamp4
#undef rsampa
#undef rsampb
@----------------------------------------------------------
mmMix_CenteredPanning:
@----------------------------------------------------------
#define rsamp1 r1
#define rsamp2 r2
#define rsamp3 r4
#define rsamp4 r6
#define rsamp5 r11
#define rsamp6 r12
#define rsampa r0
#define rsampb lr
@ mix center panning (double channel mono)
subs rmixcc, rmixcc, #6
bmi .mpmac_6e
.mpmac_6:
ldmia rmixb, {rsamp1,rsamp2,rsamp3,rsamp4,rsamp5,rsamp6} // read words
MIX_DC rvolL, rsamp1, rsamp2, rsampa, rsampb // mix data
MIX_DC rvolL, rsamp3, rsamp4, rsampa, rsampb
MIX_DC rvolL, rsamp5, rsamp6, rsampa, rsampb
stmia rmixb!, {rsamp1,rsamp2,rsamp3,rsamp4,rsamp5,rsamp6} // write words
subs rmixcc, rmixcc, #6 // count
bpl .mpmac_6 // loop
.mpmac_6e:
mov rvolR, rvolL // restore right volume (same as left)
adds rmixcc, rmixcc, #6 // fix mix count
bgt mmMix_Remainder // mix remaining amount
b .mpm_mix_complete // finished mixing segment
#undef rsamp1
#undef rsamp2
#undef rsamp3
#undef rsamp4
#undef rsamp5
#undef rsamp6
#undef rsampa
#undef rsampb
@---------------------------------------------------
mmMix_ArbPanning: // SLOWEST!
@---------------------------------------------------
#define rsamp1 r1
#define rsamp2 r2
#define rsamp3 r4
#define rsamp4 r11
#define rsampa r0
#define rsampb r12
#define rsamp5 r14
subs r3, r3, #10
bmi .mpmaa_10e
.mpmaa_10:
ldmia rmixb, {rsamp1,rsamp2,rsamp3,rsamp4,rsamp5} // load bufferdata
MIX_DB rvolL, rvolR, rsamp1, rsamp2, rsampa, rsampb // mix
MIX_DB rvolL, rvolR, rsamp3, rsamp4, rsampa, rsampb // mix
MIX_DB rvolL, rvolR, rsamp5, 0, rsampa, rsampb // mix half
stmia rmixb!, {rsamp1,rsamp2,rsamp3,rsamp4,rsamp5} // store bufferdata
ldmia rmixb, {rsamp1,rsamp2,rsamp3,rsamp4,rsamp5} // load bufferdata
mul rsampb, rsampa, rvolR // mix other half
bic rsampb, rsampb, #0x1F0000 // ..
add rsamp1, rsamp1, rsampb, lsr#5 // ..
MIX_DB rvolL, rvolR, rsamp2, rsamp3, rsampa, rsampb // mix
MIX_DB rvolL, rvolR, rsamp4, rsamp5, rsampa, rsampb // mix
stmia rmixb!, {rsamp1,rsamp2,rsamp3,rsamp4,rsamp5} // store bufferdata
subs rmixcc, rmixcc, #10 // count
bpl .mpmaa_10 // loop
.mpmaa_10e:
adds rmixcc, rmixcc, #10
bgt mmMix_Remainder
b .mpm_mix_complete
.pool
#undef rsamp1
#undef rsamp2
#undef rsamp3
#undef rsamp4
#undef rsampa
#undef rsampb
//---------------------------------------------------------------------------
mmMix_Remainder:
//---------------------------------------------------------------------------
// (slow function to mix remaining amount of samples)
// assumes mix count isn't zero!
#define rsamp1 r1
#define rsamp2 r2
#define rvol r11
#define rsampa r0
#define rsampb r4
orr rvol, rvolL, rvolR, lsl#16
.mix_remaining:
/* ldrb rsampa, [rsrc, rread, lsr#SAMPFRAC] @ 3 load sample
add rread, rread, rfreq @ 1 add frequency
mul rsampb, rsampa, rvolL @ 2 multiply by volume
ldrh rsamp1, [rmixb] @ 3 load mix buffer entry
add rsamp1, rsamp1, rsampb, lsr#5 @ 1 add
strh rsamp1, [rmixb], #2 @ 2 store
ldrh rsamp1, [rmixb, #2] @ 3
mul rsampb, rsampa, rvolR @ 2
add rsamp1, rsamp1, rsampb, lsr#5 @ 1
strh rsamp1, [rmixb, #2] @ 2
*/
ldrb rsampa, [rsrc, rread, lsr#SAMPFRAC] @ 3 load sample
add rread, rread, rfreq @ 1 add frequency
mul rsampb, rvol, rsampa @ 2 multiply by volume
ldrh rsamp1, [rmixb] @ 3 load mix buffer entry (left)
bic rsamp2, rsampb, #0xFF0000 @ 1 prep for shift
add rsamp1, rsamp1, rsamp2, lsr#5 @ 1 add
strh rsamp1, [rmixb], #2 @ 2 store (left)
ldrh rsamp1, [rmixb, #2] @ 3 load (right)
add rsamp1, rsamp1, rsampb, lsr#16+5 @ 1 add values
strh rsamp1, [rmixb, #2] @ 2 store (right)
subs rmixcc, rmixcc, #2 @ 2
blt .end_mix_remaining @ 1/exit
/* ldrb rsampa, [rsrc, rread, lsr#SAMPFRAC] @ load sample
add rread, rread, rfreq @ add frequency
mul rsampb, rsampa, rvolL @ multiply by volume
ldrh rsamp1, [rmixb] @ load mix buffer entry
add rsamp1, rsamp1, rsampb, lsr#5 @ add
strh rsamp1, [rmixb], #4 @ store
ldrh rsamp1, [rmixb]
mul rsampb, rsampa, rvolR
add rsamp1, rsamp1, rsampb, lsr#5
strh rsamp1, [rmixb], #2
*/
ldrb rsampa, [rsrc, rread, lsr#SAMPFRAC] @ 3 load sample
add rread, rread, rfreq @ 1 add frequency
mul rsampb, rvol, rsampa @ 2 multiply by volume
ldrh rsamp1, [rmixb] @ 3 load mix buffer entry (left)
bic rsamp2, rsampb, #0xFF0000 @ 1 prep for shift
add rsamp1, rsamp1, rsamp2, lsr#5 @ 1 add
strh rsamp1, [rmixb], #4 @ 2 store (left)
ldrh rsamp1, [rmixb] @ 3 load (right)
add rsamp1, rsamp1, rsampb, lsr#16+5 @ 1 add values
strh rsamp1, [rmixb], #2 @ 2 store (right)
bgt .mix_remaining
.end_mix_remaining:
b .mpm_mix_complete
#undef rsamp1
#undef rsamp2
#undef rvol
#undef rsampa
#undef rsampb
@============================================================================
@ END OF MIXER
@============================================================================
.TEXT
.THUMB
.ALIGN 2
/****************************************************************************
* mmMixerSetSource( channel, p_sample )
*
* Set channel source
****************************************************************************/
.thumb_func
mmMixerSetSource:
mov r2, #CHN_SIZE // get channel pointer from index
mul r0, r2 //
ldr r2,=mm_mixchannels //
ldr r2, [r2] //
add r0, r2 //
add r1, #C_SAMPLE_DATA // set sample data address
str r1, [r0, #CHN_SRC] //
mov r1, #0 // reset read position
str r1, [r0, #CHN_READ] //
bx lr
/****************************************************************************
* mmMixerSetRead( channel, value )
*
* Set channel read position
****************************************************************************/
.thumb_func
mmMixerSetRead:
mov r2, #CHN_SIZE // get channel pointer from index
mul r0, r2 //
ldr r2,=mm_mixchannels //
ldr r2,[r2] //
add r0, r2 //
str r1, [r0, #CHN_READ] // store new offset
bx lr //
/****************************************************************************
* mmMixerSetFreq
*
* Set channel mixing rate
****************************************************************************/
.thumb_func
mmMixerSetFreq:
// push {r3, r4} // FIXME: why would you preserve r3?
mov r2, #CHN_SIZE // get channel pointer from index
mul r0, r2, r0 //
ldr r2,=mm_mixchannels //
ldr r2,[r2] //
add r0, r0, r2 //
lsl r1, #2 // ...
strh r1, [r0, #CHN_FREQ]
bx lr
/*
ldr r4,=mm_freqscalar // r4=scale
ldr r4,[r4] //
add r2, pc, #0 // switch to arm for a nice long multiply
bx r2
.ARM
//------------------------------------
// fix frequency to match mixing rate
// a = specified frequency
// hz = a*2y13 / pr
//------------------------------------
umull r3, r2, r1, r4 // long multiply
add r3, r3, #32768 // shift, etc..
mov r3, r3, lsr#16 //
orr r3, r3, r2, lsl#16 //
str r3, [r0, #CHN_FREQ] // set chan frequency
ldmfd sp!, {r3,r4} // pop registers
bx lr // return
*/
.THUMB
/****************************************************************************
* mmMixerMulFreq( channel, value )
*
* Scale mixing frequency
****************************************************************************/
.thumb_func
mmMixerMulFreq:
mov r2, #CHN_SIZE // get channel pointer from index
mul r0, r2 //
ldr r2,=mm_mixchannels //
ldr r2, [r2] //
add r0, r2 //
ldr r3, [r0, #CHN_FREQ] // scale
mul r3, r1 //
lsr r3, #10 //
str r3, [r0, #CHN_FREQ] //
bx lr
/****************************************************************************
* mmMixerStopChannel( channel )
*
* Stop mixing channel
****************************************************************************/
.thumb_func
mmMixerStopChannel:
mov r1, #CHN_SIZE // get channel pointer from index
mul r0, r1 //
ldr r1,=mm_mixchannels //
ldr r1,[r1] //
add r0, r1 //
mov r1, #1 // set MSB (disable) of source
lsl r1, #31 //
str r1, [r0] //
bx lr
/****************************************************************************
* mmMixerChannelActive( channel )
*
* Test if mixing channel is active
****************************************************************************/
.thumb_func
mmMixerChannelActive:
mov r1, #CHN_SIZE // get channel pointer from index
mul r0, r1 //
ldr r1,=mm_mixchannels //
ldr r1,[r1] //
add r0, r1 //
mp_Mixer_ChannelEnabledA:
ldr r0, [r0, #CHN_SRC] // nonzero (-1) = enabled
asr r0, #31 // zero = disabled
mvn r0, r0 //
bx lr
/****************************************************************************
* mmMixerSetVolume( channel, volume )
*
* Set channel volume
****************************************************************************/
.thumb_func
mmMixerSetVolume:
mov r2, #CHN_SIZE // get channel pointer from index
mul r0, r2 //
ldr r2,=mm_mixchannels //
ldr r2,[r2] //
add r0, r2 //
strb r1, [r0, #CHN_VOL] // set volume
bx lr
/****************************************************************************
* mmMixerSetPan( channel, panning )
*
* Set channel panning
****************************************************************************/
.thumb_func
mmMixerSetPan:
mov r2, #CHN_SIZE // get channel pointer from index
mul r0, r2 //
ldr r2,=mm_mixchannels //
ldr r2,[r2] //
add r0, r2 //
strb r1, [r0, #CHN_PAN] // set panning
bx lr
/****************************************************************************
* mmMixerInit( system )
*
* Initialize mixer
****************************************************************************/
.thumb_func
mmMixerInit:
ldr r2,=mm_mixbuffer
ldr r1, [r0,#MM_GBA_SYSTEM_ACH_COUNT]
str r1, [r2,#16]
mov r3, #CHN_SIZE
mul r1, r3
ldr r3, [r0,#MM_GBA_SYSTEM_MIXCH]
str r3, [r2,#4]
add r3, r1
str r3, [r2,#20]
ldr r1, [r0,#MM_GBA_SYSTEM_MIXMEM]
str r1, [r2,#0]
ldr r1, [r0,#MM_GBA_SYSTEM_WAVEMEM]
str r1, [r2,#8]
ldr r1, [r0,#MM_GBA_SYSTEM_MODE]
lsl r1, #1
adr r3, mp_mixing_lengths
ldrh r3, [r3,r1]
str r3, [r2,#12]
adr r3, mp_rate_scales
ldrh r3, [r3, r1]
str r3, [r2, #24]
adr r3, mp_timing_sheet
ldrh r3, [r3, r1]
str r3, [r2, #28]
adr r3, mp_bpm_divisors
lsl r1, #1
ldr r3, [r3,r1]
ldr r2,=mm_bpmdv
str r3, [r2,#0]
ldr r0,=mm_wavebuffer @ clear wave buffer
ldr r0,[r0]
ldr r1,=mm_mixlen
ldr r1, [r1]
mov r2, #0 @ ..
.mpi_loop1: @ ..
stmia r0!, {r2} @ ..
sub r1, r1, #1 @ ..
bne .mpi_loop1 @ ..
ldr r0,=mp_mix_seg @ reset mixing segment
strb r2, [r0] @ ..
ldr r0,=mm_mixchannels @ disable mixing channels
ldr r1,[r0,#12]@ nchannels
ldr r0,[r0]
ldr r3,=1<<31
.mpi_loop2:
str r3, [r0, #CHN_SRC]
add r0, #CHN_SIZE
sub r1, #1
bne .mpi_loop2
ldr r0,=mmVBlank @ enable vblank routine
ldr r1,=0xE1A00000 @ ..
str r1, [r0] @ ..
ldr r0,=REG_SGFIFOA @ clear fifo data
str r2, [r0] @ ..
str r2, [r0, #4] @ ..
ldr r0,=REG_SOUNDCNT_H @ reset direct sound
strh r2, [r0] @ ..
ldr r1,=0x9A0C @ setup sound [DIRECT SOUND A/B reset,timer0,A=left,B=right,volume=100%]
strh r1, [r0] @ ..
ldr r0,=REG_DMA1SAD @ setup DMA source addresses (playback buffers)
ldr r1,=mm_wavebuffer
ldr r2, [r1, #4]@mixlen
ldr r1, [r1]
@ldr r1,=mp_playbuffer_l @ ..
str r1, [r0] @ ..
add r1,r2
add r1,r2
@ ldr r1,=mp_playbuffer_r @ ..
str r1, [r0, #12] @ ..
ldr r1,=REG_SGFIFOA @ setup DMA destination (sound fifo)
str r1, [r0, #4] @ ..
add r1, #4 @ ..
str r1, [r0, #16] @ ..
ldr r1,=0xB6000000 @ enable DMA (enable,fifo request,32-bit,repeat)
str r1, [r0, #8] @ ..
str r1, [r0, #20] @ ..
ldr r0,=REG_SOUNDCNT_X @ master sound enable
mov r1, #0x80 @ ..
strh r1, [r0] @ ..
ldr r0,=REG_VCOUNT @ wait for new frame
.mpi_vsync: @ ..
ldrh r1, [r0] @ skip current vblank period
cmp r1, #160 @ ..
bge .mpi_vsync @ ..
.mpi_vsync2:
ldrh r1, [r0] @ wait for new one
cmp r1, #160 @ ..
blt .mpi_vsync2 @ ..
.mpi_vsync_2: @ pass#2
ldrh r1, [r0] @ skip current vblank period
cmp r1, #160 @ ..
bge .mpi_vsync_2 @ ..
.mpi_vsync2_2:
ldrh r1, [r0] @ wait for new one
cmp r1, #160 @ ..
blt .mpi_vsync2_2 @ ..
ldr r0,=REG_TM0CNT @ enable sampling timer
ldr r1,=mm_timerfreq
ldr r1,[r1]
mov r2, #0x80
lsl r2, #16
orr r1, r2
@ldr r1,=(-MP_TIMERFREQ&0xFFFF) | (0x80<<16) @ ..
str r1, [r0] @ ..
bx lr @ finished
// round(rate / 59.737)
.align 2
mp_mixing_lengths:
.hword 136, 176, 224, 264, 304, 352, 448, 528
@ 8khz,10khz,13khz,16khz,18khz,21khz,27khz,32khz
.align 2
//mp_freq_scales: @ (16khz -> real)
// .hword 33056, 25536, 20064, 17024, 14784, 12768
// 15768*16384 / rate
mp_rate_scales:
.hword 31812, 24576, 19310, 16384, 14228, 12288, 9655, 8192
@ 8khz, 10khz, 13khz, 16khz, 18khz, 21khz, 27khz, 32khz
@ 8121, 10512, 13379, 15768, 18157, 21024, 26758, 31536,
.align 2
// gbaclock / rate
mp_timing_sheet:
.hword -2066,-1596,-1254,-1064, -924, -798, -627, -532
@ 8khz,10khz,13khz,16khz,18khz,21khz,27khz,32khz
.align 2
// rate * 2.5
mp_bpm_divisors:
.word 20302,26280,33447,39420,45393,52560,66895,78840
.end
|
afska/beat-beast
| 5,740
|
butano/hw/3rd_party/libugba/src/irq_handler.s
|
// SPDX-License-Identifier: MIT
//
// Copyright (c) 2020-2022 Antonio Niño Díaz
.section .iwram, "ax", %progbits
.code 32
.set MEM_IO_ADDR, 0x04000000
.set OFFSET_IE, 0x200
.set OFFSET_IF, 0x202
.set OFFSET_IME, 0x208
.global IRQ_GlobalInterruptHandler
IRQ_GlobalInterruptHandler:
// Get the pending interrupts that the user actually cares about. If
// something isn't set in IE, ignore it.
mov r0, #MEM_IO_ADDR // r0 = MEM_IO_ADDR
ldr r1, [r0, #OFFSET_IE] // r1 = REG_IE | (REG_IF << 16)
and r1, r1, r1, lsr #16 // r1 = REG_IE & REG_IF
// Iterate from BIT(0) to BIT(13)
.extern IRQ_VectorTable
// Notes on the default priority of interrupts:
//
// - HBLANK is first because it's very short, so saving a few cycles is
// important, specially because it is called every scanline.
// - VCOUNT is second because it's similar to HBLANK, but it is triggered
// less often. However, it needs higher priority than VBL because they
// are both triggered at the same time when VBL starts, and VBL is much
// longer.
ldr r3, =IRQ_VectorTable + 4
mov r2, #(1 << 1) // HBLANK
tst r1, r2
bne interrupt_found
# add r3, r3, #4
# mov r2, #(1 << 2) // VCOUNT
# tst r1, r2
# bne interrupt_found
# sub r3, r3, #8
sub r3, r3, #4
mov r2, #(1 << 0) // VBLANK
tst r1, r2
bne interrupt_found
add r3, r3, #12
mov r2, #(1 << 3) // TIMER0
tst r1, r2
bne interrupt_found
add r3, r3, #4
mov r2, #(1 << 4) // TIMER1
tst r1, r2
bne interrupt_found
# add r3, r3, #4
# mov r2, #(1 << 5) // TIMER2
# tst r1, r2
# bne interrupt_found
# add r3, r3, #4
# mov r2, #(1 << 6) // TIMER3
# tst r1, r2
# bne interrupt_found
# add r3, r3, #4
add r3, r3, #12
mov r2, #(1 << 7) // SERIAL
tst r1, r2
bne interrupt_found
# add r3, r3, #4
# mov r2, #(1 << 8) // DMA0
# tst r1, r2
# bne interrupt_found
# add r3, r3, #4
add r3, r3, #8
mov r2, #(1 << 9) // DMA1
tst r1, r2
bne interrupt_found
add r3, r3, #4
mov r2, #(1 << 10) // DMA2
tst r1, r2
bne interrupt_found
# add r3, r3, #4
# mov r2, #(1 << 11) // DMA3
# tst r1, r2
# bne interrupt_found
# add r3, r3, #4
add r3, r3, #8
mov r2, #(1 << 12) // KEYPAD
tst r1, r2
bne interrupt_found
# add r3, r3, #4
# mov r2, #(1 << 13) // GAMEPAK
# tst r1, r2
# bne interrupt_found
// If no interrupt flag is set, fall to the next section of code.
// If no interrupt handlers have to be called, clear all bits in the IF and
// BIOS flags register.
add r3, r0, #(OFFSET_IF & 0xFF00)
orr r3, r3, #(OFFSET_IF & 0xFF)
ldrh r1, [r3]
strh r1, [r3]
ldrh r2, [r0, #-8] // The BIOS register is mirrored at 0x03FFFFF8
orr r2, r2, r1
strh r2, [r0, #-8]
bx lr
// This point is reached if there is at least one bit set in IF & IE
interrupt_found:
// r0 = REG_BASE
// r2 = IRQ bit of the current vector
// r3 = Pointer to vector to jump to
// Write bit to IF and the BIOS register to acknowledge this interrupt, but
// leave the others alone.
add r1, r0, #(OFFSET_IF & 0xFF00)
orr r1, r1, #(OFFSET_IF & 0xFF)
strh r2, [r1]
// The BIOS register (BIOS_INTR_FLAGS) is mirrored at 0x03FFFFF8
ldrh r1, [r0, #-8]
orr r1, r1, r2
strh r1, [r0, #-8]
// If the interrupt handler is null, exit handler
ldr r3, [r3]
cmp r3, #0
bxeq lr
// If this point is reached, there is a valid interrupt handler
// r0 = REG_BASE
// r3 = Vector to jump to
// Clear IME so that we don't get any nested interrupt during the handler of
// the current one. At the same time, the old value is preserved so that it
// can be restored after the end of the interrupt handler. Note that it is
// safe to access IME in 32-bit accesses.
add r2, r0, #(OFFSET_IME & 0xFF00)
orr r2, r2, #(OFFSET_IME & 0xFF)
mov r1, #0
swp r1, r1, [r2]
// Get current spsr
mrs r2, spsr
// Push old IME, spsr and lr
stmfd sp!, {r1-r2, lr}
.equ MODE_IRQ, 0x12
.equ MODE_SYSTEM, 0x1F
.equ MODE_MASK, 0x1F
.equ FLAG_IRQ_DISABLE, 1 << 7
// Set CPU mode to system (like user, but privileged, so we can go back to
// mode IRQ later). Re-enable the master IRQ bit in CPSR so that the
// interrupt handler can re-enable interrupts by setting IME to 1.
mrs r2, cpsr
//bic r2, r2, #MODE_MASK // Not needed for MODE_SYSTEM
bic r2, r2, #FLAG_IRQ_DISABLE
orr r2, r2, #MODE_SYSTEM
msr cpsr, r2
// Call interrupt handler
push {lr}
mov lr, pc
bx r3
pop {lr}
// Disable interrupts while switching modes
mov r0, #MEM_IO_ADDR
str r0, [r0, #OFFSET_IME]
// Set CPU mode to IRQ. Disable interrupts so that setting IME to 1
// afterwards doesn't let the CPU jump to the interrupt handler.
mrs r2, cpsr
bic r2, r2, #MODE_MASK
orr r2, r2, #(MODE_IRQ | FLAG_IRQ_DISABLE)
msr cpsr, r2
// Pop old IME, spsr and lr
ldmfd sp!, {r1-r2, lr}
// Restore spsr
msr spsr, r2
// Restore old IME
str r1, [r0, #OFFSET_IME]
bx lr
.end
|
afska/beat-beast
| 13,341
|
butano/hw/3rd_party/posprintf/src/posprintf.s
|
/*
posprintf - a condensed version of sprintf for Thumb, esp. GBA
Copyright (C) 2003 Dan Posluns
The person or persons who have associated work with this document (the "Dedicator" or "Certifier") hereby either (a) certifies that, to the best of his knowledge, the work of authorship identified is in the public domain of the country from which the work is published, or (b) hereby dedicates whatever copyright the dedicators holds in the work of authorship identified below (the "Work") to the public domain. A certifier, moreover, dedicates any copyright interest he may have in the associated work, and for these purposes, is described as a "dedicator" below.
A certifier has taken reasonable steps to verify the copyright status of this work. Certifier recognizes that his good faith efforts may not shield him from liability if in fact the work certified is not in the public domain.
Dedicator makes this dedication for the benefit of the public at large and to the detriment of the Dedicator's heirs and successors. Dedicator intends this dedication to be an overt act of relinquishment in perpetuity of all present and future rights under copyright law, whether vested or contingent, in the Work. Dedicator understands that such relinquishment of all rights includes the relinquishment of all rights to enforce (by lawsuit or otherwise) those copyrights in the Work.
Dedicator recognizes that, once placed in the public domain, the Work may be freely reproduced, distributed, transmitted, used, modified, built upon, or otherwise exploited by anyone for any purpose, commercial or non-commercial, and in any way, including by methods that have not yet been invented or conceived.
Author contact e-mail: dan at danposluns dot com
register map:
MAIN LOOP: PROCESS16:
r0 <- dest string address r0 <- d0
r1 <- source string address r1 <- d1
r2 <- integer to print r2 <- d2
r3 <- r3 <- d3
r4 <- current char r4 <- d4
r5 <- r5 <- work register
r6 <- r6 <- work register
r7 <- r7 <- dest string address
r8 <- number of digits to print r8 <- number of digits to print
r9 <- leading char (' ' or '0') r9 <- leading char (' ' or '0')
r10 <- current parameter pointer r10 <- current parameter ptr
r11 <- r11 <-
r12 <- r12 <- source string address
r14 <- r14 <- lr
Function parameters:
r0 <- destination string address
r1 <- source string address
r2 <- param1
r3 <- param2
*/
.thumb
.thumb_func
.align
____thumb_aeabi_uidiv:
ldr r3, =__aeabi_uidiv
bx r3
.thumb
.thumb_func
.align
.global posprintf
.type posprintf,function
posprintf:
push {r3} @ push our second and third parameters
push {r2} @ onto the stack in reverse order
mov r12, sp @ r12 <- first parameter pointer
push {r4-r7} @ save clobbered registers
mov r4, r8
mov r5, r9
mov r6, r10
push {r4-r6, lr}
mov r10, r12 @ r10 <- first parameter pointer
.L_STRINGLOOP:
ldrb r4, [r1] @ load a char from r1
add r1, #1 @ advance pointer to next char
cmp r4, #'%' @ if char == '%' then
beq .L_FORMATENTRY @ handle the format specifier
strb r4, [r0] @ store the char back to memory
add r0, #1 @ advance pointer to next char
cmp r4, #0 @ if char != 0 then
bne .L_STRINGLOOP @ repeat for next char
@ cleanup and exit
pop {r4-r7} @ restore clobbered registers
mov r8, r4
mov r9, r5
mov r10, r6
mov lr, r7
pop {r4-r7}
add sp, #8 @ remove parameters from stack
bx lr @ return from subroutine
.L_FORMATENTRY:
mov r5, #0 @ assume no leading character for numbers
mov r6, #' ' @ assume print spaces if we do print leads
mov r8, r5
mov r9, r6
.L_FORMATSPEC:
ldrb r4, [r1] @ load the next char from r1
add r1, #1 @ advance pointer to next char
cmp r4, #'d' @ if char == 'd'
beq .L_PRINT16 @ print 16-bit number
cmp r4, #'s' @ if char == 's'
beq .L_PRINTSTR @ print string
cmp r4, #'0' @ if char == '0'
beq .L_SETLEAD @ print with leading zeros
cmp r4, #'%' @ if char == '%'
beq .L_PRINTSYMBOL @ print '%' character
cmp r4, #'l' @ if char == 'l'
beq .L_PRINT29 @ print 29-bit number
cmp r4, #'X' @ if char == 'X'
beq .L_PRINTHEXUC @ print hexadecimal uppercase
cmp r4, #'x' @ if char == 'x'
beq .L_PRINTHEXLC @ print hexadecimal lowercase
@ we now assume that we are choosing a number of leading digits to display
sub r4, #'0'
mov r8, r4 @ r8 <- char - '0'
b .L_FORMATSPEC
.L_SETLEAD:
mov r6, #'0'
mov r9, r6 @ print leading zeros instead of spaces
b .L_FORMATSPEC
.L_PRINTSYMBOL:
strb r4, [r0] @ store '%' symbol to memory
add r0, #1 @ advance pointer to next char
b .L_STRINGLOOP
.L_PRINTSTR:
mov r4, r10 @ r4 <- current parameter pointer
ldr r2, [r4] @ r2 <- address of string to print
add r4, #4
mov r10, r4 @ increase parameter pointer
.L_PRINTSTRLOOP:
ldrb r4, [r2] @ load a char from r2
add r2, #1 @ advance pointer to next char
cmp r4, #0 @ if char == 0
beq .L_STRINGLOOP @ then we are done
strb r4, [r0] @ store the char back to memory
add r0, #1 @ advance pointer to next char
b .L_PRINTSTRLOOP
.L_PRINT16:
mov r7, r0 @ r7 <- dest string address
mov r4, r10 @ r4 <- current parameter pointer
ldr r0, [r4] @ r0 <- 16-bit integer to print
add r4, #4
mov r10, r4 @ increase parameter pointer
mov r3, #0 @ temp marker for L_PRINTSIGN
cmp r0, #0 @ if integer to print is negative
blt .L_PRINTSIGN @ print the sign and adjust
.L_SIGNDONE:
mov lr, pc @ save this location
bl .L_PROCESS16 @ process a 16-bit number
b .L_STRINGLOOP @ return when done
.L_PRINTSIGN:
mov r4, #'-'
strb r4, [r7] @ print '-' character
add r7, #1 @ advance pointer to next char
neg r0, r0 @ r2 is now positive
mov r4, r8
sub r4, #1 @ print one fewer character
mov r8, r4 @ r8 <- new value
cmp r3, #0 @ check to see who called us
beq .L_SIGNDONE
b .L_SIGN29DONE
.L_PRINT29:
mov r7, r0 @ r7 <- dest string address
mov r4, r10 @ r4 <- current parameter pointer
ldr r0, [r4] @ r0 <- 16-bit integer to print
add r4, #4
mov r10, r4 @ increase parameter pointer
mov r3, #1 @ temp marker for L_PRINTSIGN
cmp r0, #0 @ if integer to print is negative
blt .L_PRINTSIGN @ print the sign and adjust
.L_SIGN29DONE:
mov r12, r1
mov r1, #0x27
lsl r1, r1, #8
add r1, #0x10 @ r1 <- 0x2710 == 10000
bl ____thumb_aeabi_uidiv @ split number by dividing by 10000
mov r3, #0
sub r3, #4
add r8, r3 @ subtract 4 from digits to display
cmp r0, #0 @ if the first chunk is empty
beq .L_P29SKIP @ then skip it
push {r1} @ save the second number to display
mov r1, r12
mov lr, pc @ save this location
bl .L_PROCESS16 @ process a 16-bit number
mov r12, r1
pop {r1} @ load in the second number
mov r3, #0
mov r8, r3 @ print leading symbols now!
mov r3, #'0'
mov r9, r3 @ make sure they are zeros!
.L_P29SKIP:
mov r0, r1 @ get ready to print second number
mov r1, #4
add r8, r1 @ add 4 back on to digits
mov r1, r12
mov lr, pc @ save this location
bl .L_PROCESS16 @ process a 16-bit number
b .L_STRINGLOOP
.L_PRINTHEXLC:
mov r7, #39
mov r12, r7 @ lowercase offset
b .L_PRINTHEX
.L_PRINTHEXUC:
mov r7, #7
mov r12, r7 @ uppercase offset
.L_PRINTHEX:
mov r4, r10 @ r4 <- current parameter pointer
ldr r2, [r4] @ r2 <- integer to print
add r4, #4
mov r10, r4 @ increase parameter pointer
mov r4, #28 @ r4 <- 8 digits to cycle through
mov r6, #0xF @ r6 <- nibble mask
mov r7, #0 @ r7 <- print flag
.L_PRINTHEXLOOP:
mov r3, r2
lsr r3, r4
and r3, r6 @ r3 <- (n >> (cycle * 4)) & 0xF
orr r7, r3 @ if we have not encountered a digit
beq .L_PH_LEADZERO @ then it is a leading zero
add r3, #'0'
mov r5, r12 @ get ready to print a letter
cmp r3, #'9' @ if the digit is in the alpha range
bgt .L_PH_ALPHA @ then print a letter
mov r5, #0 @ else do nothing
.L_PH_ALPHA:
add r3, r5 @ add offset to correct letter
strb r3, [r0] @ store the char in memory
add r0, #1 @ advance pointer to next char
sub r4, #4 @ advance to next digit
bge .L_PRINTHEXLOOP @ loop until done
b .L_STRINGLOOP
.L_PH_LEADZERO:
lsr r5, r4, #2 @ r5 <- which digit we are on
sub r4, #4 @ if this is our last digit
blt .L_PH_FINAL @ then print a zero for sure
cmp r8, r5 @ if r8 < current digit
ble .L_PRINTHEXLOOP @ then keep looping
mov r5, r9 @ r5 <- leading symbol to print
strb r5, [r0] @ store the char in memory
add r0, #1 @ advance pointer to next char
b .L_PRINTHEXLOOP
.L_PH_FINAL:
mov r3, #'0' @ if n == 0, print at least one 0
strb r3, [r0]
add r0, #1
b .L_STRINGLOOP
.L_PROCESS16:
mov r12, r1 @ free up registers
mov r5, #0xF
lsr r1, r0, #4
lsr r2, r0, #8
lsr r3, r0, #12
and r0, r5 @ r0 <- n & 0xF
and r1, r5 @ r1 <- (n >> 4) & 0xF
and r2, r5 @ r2 <- (n >> 8) & 0xF
and r3, r5 @ r3 <- (n >> 12) & 0xF
mov r6, r3
add r6, r2
add r6, r1
lsl r5, r6, #2
lsl r6, r6, #1
add r0, r6
add r0, r5 @ r0 <- 6 * (d3 + d2 + d1) + d0
@ divide by ten: multiply by 0x19A shifted right by 12
lsr r5, r0, #2
add r5, r0
lsr r5, r5, #1 @ r5 <- ((d0 >> 2) + i) >> 1
add r5, r0
lsr r5, r5, #3 @ r5 = (r5 + d0) >> 3
add r5, r0
lsr r5, r5, #1 @ r5 = (r5 + d0) >> 1
add r5, r0
lsr r5, r5, #4 @ r5 <- d0 / 10
@ calculate remainder as d0
lsl r6, r5, #2
add r6, r5
lsl r6, r6, #1 @ r6 <- q * 10
sub r0, r6 @ r0 <- d0 - (q * 10)
@ finished with d0, now calculate d1
lsl r6, r3, #3
add r5, r6
add r5, r3 @ r5 <- q + 9 * d3
lsl r6, r2, #2
add r5, r6
add r5, r2 @ r5 <- q + 9 * d3 + 5 * d2
add r1, r5 @ r1 <- d1 + r5
beq .L_LEAD_D1
@ divide d1 by ten: multiply by 0x19A shifted right by 12
lsr r5, r1, #2
add r5, r1
lsr r5, r5, #1
add r5, r1
lsr r5, r5, #3
add r5, r1
lsr r5, r5, #1
add r5, r1
lsr r5, r5, #4 @ r5 <- d1 / 10
@ calculate remainder as d1
lsl r6, r5, #2
add r6, r5
lsl r6, r6, #1
sub r1, r6 @ r1 <- d1 - (q * 10)
@ finished with d1, now calculate d2
lsl r2, r2, #1
add r2, r5 @ r2 <- 2 * d2 + q
mov r5, r2
orr r5, r3 @ if (!d2) && (!d3)
beq .L_LEAD_D2 @ then skip
@ divide d2 by ten: multiply by 0x1A >> 8 is sufficient
lsr r5, r2, #2
add r5, r2
lsr r5, r5, #1
add r5, r2
lsr r5, r5, #4 @ r5 <- d2 / 10
@ calculate remainder as d2
lsl r6, r5, #2
add r6, r5
lsl r6, r6, #1
sub r2, r6 @ r2 <- d2 - (q * 10)
@ finished with d2, now calculate d3
lsl r3, r3, #2
add r3, r5
beq .L_LEAD_D3
@ divide d3 by ten: multiply by 0x1A >> 8 is sufficient
lsr r5, r3, #2
add r5, r3
lsr r5, r5, #1
add r5, r3
lsr r5, r5, #4 @ r5 <- d3 / 10
@ calculate remainder as d3
lsl r6, r5, #2
add r6, r5
lsl r6, r6, #1
sub r3, r6 @ r3 <- d3 - (q * 10)
@ finished with d3, d4 will automatically be quotient
mov r4, r5
beq .L_LEAD_D4
@ now print any leading digits if we are using all five
mov r5, r8
mov r6, r9
sub r5, #4 @ already printed five digits
.L_EXTRA_LEAD_LOOP:
sub r5, #1
ble .L_DONE_EXTRA_LEAD
strb r6, [r7] @ print a leading character
add r7, #1
b .L_EXTRA_LEAD_LOOP
.L_DONE_EXTRA_LEAD:
@ now print the fifth digit (d4)
add r4, #'0' @ r4 <- d4 + '0'
strb r4, [r7] @ store a character
add r7, #1 @ advance string pointer
.L_DONE_D4:
add r3, #'0'
strb r3, [r7]
add r7, #1
.L_DONE_D3:
add r2, #'0'
strb r2, [r7]
add r7, #1
.L_DONE_D2:
add r1, #'0'
strb r1, [r7]
add r7, #1
.L_DONE_D1:
add r0, #'0'
strb r0, [r7]
add r7, #1
@ Done at last! Clean up and return to calling routine
mov r0, r7 @ restore r0 <- dest string address
mov r1, r12 @ restore r1 <- source string address
mov pc, lr @ return from subroutine
.L_LEAD_D4:
mov r5, r9 @ r5 <- leading character
mov r6, r8
sub r6, #4 @ r6 <- # of chars to print
ble .L_DONE_D4
.L_IN_D4:
strb r5, [r7] @ store a character
add r7, #1 @ advance string pointer
sub r6, #1 @ if chars to print > 0
bgt .L_IN_D4 @ then loop
b .L_DONE_D4
.L_LEAD_D3:
mov r5, r9 @ r5 <- leading character
mov r6, r8
sub r6, #3 @ r6 <- # of chars to print
ble .L_DONE_D3
.L_IN_D3:
strb r5, [r7] @ store a character
add r7, #1 @ advance string pointer
sub r6, #1 @ if chars to print > 0
bgt .L_IN_D3 @ then loop
b .L_DONE_D3
.L_LEAD_D2:
mov r5, r9 @ r5 <- leading character
mov r6, r8
sub r6, #2 @ r6 <- # of chars to print
ble .L_DONE_D2
.L_IN_D2:
strb r5, [r7] @ store a character
add r7, #1 @ advance string pointer
sub r6, #1 @ if chars to print > 0
bgt .L_IN_D2 @ then loop
b .L_DONE_D2
.L_LEAD_D1:
mov r5, r9 @ r5 <- leading character
mov r6, r8
sub r6, #1 @ r6 <- # of chars to print
ble .L_DONE_D1
.L_IN_D1:
strb r5, [r7] @ store a character
add r7, #1 @ advance string pointer
sub r6, #1 @ if chars to print > 0
bgt .L_IN_D1 @ then loop
b .L_DONE_D1
|
afska/beat-beast
| 2,827
|
butano/hw/3rd_party/gba-modern/src/sqrt32.s
|
@--------------------------------------------------------------------------------
@ sqrt32.s
@--------------------------------------------------------------------------------
@ Provides an implementation of a square root algorithm for 32-bits
@--------------------------------------------------------------------------------
@ Source code taken from http://www.pertinentdetail.org/sqrt
@ The actual function
@ u32 isqrt32(u32 x) // so x is in r0
.section .iwram, "ax", %progbits
.align 2
.arm
.global isqrt32
.type isqrt32 STT_FUNC
isqrt32:
@ Registers: r0 = root, r2 = x, r3 = offset
mov r2, r0 @ move x to r2 first
isqrt32direct: @ shortcut used by isqrt64
mov r3, #3 << 30 @ initialize offset
mov r0, #1 << 30 @ initialize the first root
@ short-circuit to special cases where some cycles can be shaved off
movs r1, r2, lsr #8 @ if the last three bytes are 0
beq .sqrt8 @ move to the 8-bit chunk
movs r1, r2, lsr #16 @ if the last two bytes are 0
beq .sqrt16 @ move to the 16-bit chunk
movs r1, r2, lsr #24 @ if the last byte is 0
beq .sqrt24 @ move to the 24-bit chunk
@ now, 16 times, we will do the "simulation" loop
cmp r2, r0
subhs r2, r2, r0
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #2
subhs r2, r2, r0, ror #2
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #4
subhs r2, r2, r0, ror #4
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #6
subhs r2, r2, r0, ror #6
adc r0, r3, r0, lsl #1
.sqrt24:
cmp r2, r0, ror #8
subhs r2, r2, r0, ror #8
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #10
subhs r2, r2, r0, ror #10
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #12
subhs r2, r2, r0, ror #12
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #14
subhs r2, r2, r0, ror #14
adc r0, r3, r0, lsl #1
.sqrt16:
cmp r2, r0, ror #16
subhs r2, r2, r0, ror #16
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #18
subhs r2, r2, r0, ror #18
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #20
subhs r2, r2, r0, ror #20
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #22
subhs r2, r2, r0, ror #22
adc r0, r3, r0, lsl #1
.sqrt8:
cmp r2, r0, ror #24
subhs r2, r2, r0, ror #24
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #26
subhs r2, r2, r0, ror #26
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #28
subhs r2, r2, r0, ror #28
adc r0, r3, r0, lsl #1
cmp r2, r0, ror #30
subhs r2, r2, r0, ror #30
adc r0, r3, r0, lsl #1
bic r0, r0, #3 << 30
bx lr
|
afska/beat-beast
| 1,759
|
butano/hw/3rd_party/gba-modern/src/clz.s
|
@--------------------------------------------------------------------------------
@ clz.s
@--------------------------------------------------------------------------------
@ Provides an implementation of the count-leading-zeros routine utilized
@ in the std::sort algorithm
@--------------------------------------------------------------------------------
@ Source code taken from http://bit.ly/2rmLz0w
@ r0: the number we want to clz
@ returns the number of leading zeros
.section .iwram, "ax", %progbits
.align 2
.arm
.global __clzsi2
.type __clzsi2 STT_FUNC
__clzsi2:
@ Our initial guess (why 24? Well, it's better to check the comment in that same page)
movs r1, #24
.insideClz:
@ Skip if no zeros in high 16 bits
movs r2, r0, lsr #16
beq .skip16
sub r1, r1, #16
mov r0, r2
.skip16:
movs r2, r0, lsr #8
beq .skip8
sub r1, r1, #8
mov r0, r2
.skip8:
adr r2, .clztable
ldrb r0, [r2, r0]
add r0, r0, r1
bx lr
@ r0:r1: the number we want to clz
@ returns the number of leading zeros
.section .iwram, "ax", %progbits
.align 2
.arm
.global __clzdi2
.type __clzdi2 STT_FUNC
__clzdi2:
@ if the high side is nonzero, just clz it
cmp r1, #0
movne r0, r1
bne __clzsi2
@ otherwise, it's 32 + clz(low)
@ Here, we jump "inside" clz routine with r1 already ready for the 64-bit case
mov r1, #56
b .insideClz
@ Generate the lookup table
.macro reptb byte,count
.rept \count
.byte \byte
.endr
.endm
.clztable:
reptb 8,1
reptb 7,1
reptb 6,2
reptb 5,4
reptb 4,8
reptb 3,16
reptb 2,32
reptb 1,64
reptb 0,128
|
afska/beat-beast
| 1,821
|
butano/hw/3rd_party/gba-modern/src/sdiv32.s
|
@--------------------------------------------------------------------------------
@ sdiv32.s
@--------------------------------------------------------------------------------
@ Provides an implementation of 32-bit/32-bit signed division
@--------------------------------------------------------------------------------
@ refer to the unsigned division
.extern __aeabi_uidivmod
.extern __aeabi_uidiv
@ r0: the numerator / r1: the denominator
@ after it, r0 has the quotient and r1 has the modulo
.section .iwram, "ax", %progbits
.align 2
.arm
.global __aeabi_idivmod
.type __aeabi_idivmod STT_FUNC
__aeabi_idivmod:
.section .iwram, "ax", %progbits
.align 2
.arm
.global __aeabi_idiv
.type __aeabi_idiv STT_FUNC
__aeabi_idiv:
@ Test division by zero
cmp r1, #0
beq __aeabi_idiv0
@ Move the lr to r12 and make the numbers positive
mov r12, lr
@ bit 28 is whether the numerator is negative
cmp r0, #0
rsblt r0, r0, #0
orrlt r12, #1 << 28
@ bit 31 is whether the denominator is negative
cmp r1, #0
rsblt r1, r1, #0
orrlt r12, #1 << 31
@ Call the unsigned division
.extern udiv32pastzero
bl udiv32pastzero
@ This moves "numerator is negative" to overflow flag and
@ "denominator is negative" to sign flag
msr cpsr_f, r12
@ The quotient should be negated only if exactly one (but not zero or two)
@ of the numerator and/or denominator were negative, so that means N!=V
@ that's why we use the lt condition here
rsblt r0, r0, #0
@ The modulo should only be negated if the numerator was negative, so if V=1
rsbvs r1, r1, #0
@ Erase the sign bits from the return address, and return
bic r12, #0xF << 28
bx r12
|
afska/beat-beast
| 2,450
|
butano/hw/3rd_party/gba-modern/src/udiv32.s
|
@--------------------------------------------------------------------------------
@ udiv32.s
@--------------------------------------------------------------------------------
@ Provides an implementation of 32-bit/32-bit unsigned division
@--------------------------------------------------------------------------------
@ Source code taken from https://www.chiark.greenend.org.uk/~theom/riscos/docs/ultimate/a252div.txt
@ r0: the numerator / r1: the denominator
@ after it, r0 has the quotient and r1 has the modulo
.section .iwram, "ax", %progbits
.align 2
.arm
.global __aeabi_uidivmod
.type __aeabi_uidivmod STT_FUNC
__aeabi_uidivmod:
.section .iwram, "ax", %progbits
.align 2
.arm
.global __aeabi_uidiv
.type __aeabi_uidiv STT_FUNC
__aeabi_uidiv:
@ Check for division by zero
cmp r1, #0
beq __aeabi_idiv0
.global udiv32pastzero
udiv32pastzero:
@ If n < d, just bail out as well
cmp r0, r1 @ n, d
movlo r1, r0 @ mod = n
movlo r0, #0 @ quot = 0
bxlo lr
@ Move the denominator to r2 and start to build a counter that
@ counts the difference on the number of bits on each numerator
@ and denominator
@ From now on: r0 = quot/num, r1 = mod, r2 = -denom, r3 = counter
rsb r2, r1, #0
mov r3, #28 @ first guess on difference
mov r1, r0, lsr #4 @ r1 = num >> 4
@ Iterate three times to get the counter up to 4-bit precision
cmn r2, r1, lsr #12 @ if denom <= (r1 >> 12)
subge r3, r3, #16 @ then -denom >= -(r1 >> 12)
movge r1, r1, lsr #16
cmn r2, r1, lsr #4
subge r3, r3, #8
movge r1, r1, lsr #8
cmn r2, r1
subge r3, r3, #4
movge r1, r1, lsr #4
@ shift the numerator by the counter
mov r0, r0, lsl r3
adds r0, r0, r0 @ bump r0 a first time
@ dynamically jump to the exact copy of the iteration
add r3, r3, r3, lsl #1 @ counter *= 3
add pc, pc, r3, lsl #2 @ jump
mov r0, r0 @ pipelining issues
@ here, r0 = num << (r3 + 1), r1 = num >> (32-r3), r2 = -denom
@ now, the real iteration part
.global div32Iteration
div32Iteration:
.rept 32
adcs r1, r2, r1, lsl #1
subcc r1, r1, r2
adcs r0, r0, r0
.endr
@ and then finally quit
@ r0 = quotient, r1 = remainder
bx lr
|
afska/beat-beast
| 3,060
|
butano/hw/3rd_party/agbabi/src/memset.s
|
@===============================================================================
@
@ ABI:
@ __aeabi_memclr, __aeabi_memclr4, __aeabi_memclr8,
@ __aeabi_memset, __aeabi_memset4, __aeabi_memset8
@ Standard:
@ memset
@ Support:
@ __agbabi_wordset4, __agbabi_lwordset4, __agbabi_memset1
@
@ Copyright (C) 2021-2023 agbabi contributors
@ For conditions of distribution and use, see copyright notice in LICENSE.md
@
@===============================================================================
.syntax unified
#include "macros.inc"
.arm
.align 2
.section .iwram.__aeabi_memclr, "ax", %progbits
.global __aeabi_memclr
.type __aeabi_memclr, %function
__aeabi_memclr:
mov r2, #0
b __aeabi_memset
.global __aeabi_memclr8
.type __aeabi_memclr8, %function
__aeabi_memclr8:
.global __aeabi_memclr4
.type __aeabi_memclr4, %function
__aeabi_memclr4:
mov r2, #0
b __agbabi_wordset4
.section .iwram.__aeabi_memset, "ax", %progbits
.global __aeabi_memset
.type __aeabi_memset, %function
__aeabi_memset:
@ < 8 bytes probably won't be aligned: go byte-by-byte
cmp r1, #8
blt __agbabi_memset1
@ Copy head to align to next word
rsb r3, r0, #4
joaobapt_test r3
strbmi r2, [r0], #1
submi r1, r1, #1
strbcs r2, [r0], #1
strbcs r2, [r0], #1
subcs r1, r1, #2
.global __aeabi_memset8
.type __aeabi_memset8, %function
__aeabi_memset8:
.global __aeabi_memset4
.type __aeabi_memset4, %function
__aeabi_memset4:
lsl r2, r2, #24
orr r2, r2, r2, lsr #8
orr r2, r2, r2, lsr #16
.global __agbabi_wordset4
.type __agbabi_wordset4, %function
__agbabi_wordset4:
mov r3, r2
.global __agbabi_lwordset4
.type __agbabi_lwordset4, %function
__agbabi_lwordset4:
@ 16 words is roughly the threshold when lwordset is slower
cmp r1, #64
blt .Lset_2_words
@ 8 word set
push {r4-r9}
mov r4, r2
mov r5, r3
mov r6, r2
mov r7, r3
mov r8, r2
mov r9, r3
.Lset_8_words:
subs r1, r1, #32
stmiage r0!, {r2-r9}
bgt .Lset_8_words
pop {r4-r9}
bxeq lr
@ Fixup remaining
add r1, r1, #32
.Lset_2_words:
subs r1, r1, #8
stmiage r0!, {r2-r3}
bgt .Lset_2_words
bxeq lr
@ Test for remaining word
adds r1, r1, #4
strge r2, [r0], #4
bxeq lr
@ Set tail
joaobapt_test r1
strhcs r2, [r0], #2
strbmi r2, [r0], #1
bx lr
.section .iwram.__agbabi_memset1, "ax", %progbits
.global __agbabi_memset1
.type __agbabi_memset1, %function
__agbabi_memset1:
subs r1, r1, #1
strbge r2, [r0], #1
bgt __agbabi_memset1
bx lr
.section .iwram.memset, "ax", %progbits
.global memset
.type memset, %function
memset:
mov r3, r1
mov r1, r2
mov r2, r3
push {r0, lr}
bl __aeabi_memset
pop {r0, lr}
bx lr
|
afska/beat-beast
| 1,515
|
butano/hw/3rd_party/agbabi/src/memmove.s
|
@===============================================================================
@
@ ABI:
@ __aeabi_memmove, __aeabi_memmove4, __aeabi_memmove8
@ Standard:
@ memmove
@
@ Copyright (C) 2021-2023 agbabi contributors
@ For conditions of distribution and use, see copyright notice in LICENSE.md
@
@===============================================================================
.syntax unified
.arm
.align 2
.section .iwram.__aeabi_memmove, "ax", %progbits
.global __aeabi_memmove
.type __aeabi_memmove, %function
__aeabi_memmove:
cmp r0, r1
.extern __agbabi_rmemcpy
bgt __agbabi_rmemcpy
.extern __aeabi_memcpy
b __aeabi_memcpy
.section .iwram.__aeabi_memmove8, "ax", %progbits
.global __aeabi_memmove8
.type __aeabi_memmove8, %function
__aeabi_memmove8:
.global __aeabi_memmove4
.type __aeabi_memmove4, %function
__aeabi_memmove4:
cmp r0, r1
.extern __agbabi_rmemcpy
bgt __agbabi_rmemcpy
.extern __aeabi_memcpy4
b __aeabi_memcpy4
.section .iwram.__agbabi_memmove1, "ax", %progbits
.global __agbabi_memmove1
.type __agbabi_memmove1, %function
__agbabi_memmove1:
cmp r0, r1
.extern __agbabi_rmemcpy1
bgt __agbabi_rmemcpy1
.extern __agbabi_memcpy1
b __agbabi_memcpy1
.section .iwram.memmove, "ax", %progbits
.global memmove
.type memmove, %function
memmove:
push {r0, lr}
bl __aeabi_memmove
pop {r0, lr}
bx lr
|
afska/beat-beast
| 2,100
|
butano/hw/3rd_party/agbabi/src/atan2.s
|
/*
===============================================================================
Support:
__agbabi_atan2
Taken from https://www.coranac.com/documents/arctangent/ by Jasper "cearn" Vijn
Modified for libagbabi
===============================================================================
*/
#define BAM_BITS ( 16 )
.arm
.align 2
.section .iwram.__agbabi_atan2, "ax", %progbits
.global __agbabi_atan2
__agbabi_atan2:
subs r3, r1, #0
mov r1, r0
bne .Latan2_octantify
// Convert sign bit to pi
lsr r1, r0, #31
lsl r0, r1, #(BAM_BITS - 1)
bx lr
.Latan2_octantify:
push {r4, lr}
// Fallthough flags from previous subs
rsblt r1, r0, #0 // x = -x
rsblt r3, r3, #0 // y = -y
movlt r2, #6
movge r2, #2
movlt r4, #4
movge r4, #0
cmp r1, #0
rsble r0, r1, #0 // t = -x
movle r1, r3 // x = y
movle r3, r0 // y = t
movle r4, r2
cmp r1, r3
suble r2, r3, r1 // t = y - x
addle r1, r1, r3 // x = x + y
movle r3, r2 // y = t
addle r4, r4, #1
// t = y / x
lsl r0, r3, #15
bl __aeabi_idiv
// t2 = ((-t) * t) >> 15
rsb r2, r0, #0
mul r2, r0, r2
asr r2, r2, #15
add r3, r2, r2, lsl #3
rsb r3, r2, r3, lsl #3
asr r3, r3, #0x000B
add r3, r3, #0x1000
add r3, r3, #0x0029
mul r3, r2, r3
asr r3, r3, #0x000F
add r3, r3, #0x1F00
add r3, r3, #0x000B
mul r3, r2, r3
asr r3, r3, #0x000F
add r3, r3, #0x3640
add r3, r3, #0x000C
mul r3, r2, r3
asr r3, r3, #0x000F
add r3, r3, #0xA200
add r3, r3, #0x00FC
mul r3, r0, r3
asr r3, r3, #15
// octant *= pi/4
lsl r1, r4, #(BAM_BITS - 3)
// +0.5 rounds to nearest integer
add r3, r3, #(1 << (17 - BAM_BITS))
add r0, r1, r3, asr #(18 - BAM_BITS)
// Clear sign bit
bic r0, r0, #(1 << BAM_BITS)
pop {r4, lr}
bx lr
|
afska/beat-beast
| 2,451
|
butano/hw/3rd_party/agbabi/src/rmemcpy.s
|
@===============================================================================
@
@ Support:
@ __agbabi_rmemcpy, __agbabi_rmemcpy1
@
@ Copyright (C) 2021-2023 agbabi contributors
@ For conditions of distribution and use, see copyright notice in LICENSE.md
@
@===============================================================================
.syntax unified
#include "macros.inc"
.arm
.align 2
.section .iwram.__agbabi_rmemcpy, "ax", %progbits
.global __agbabi_rmemcpy
.type __agbabi_rmemcpy, %function
__agbabi_rmemcpy:
@ >6-bytes is roughly the threshold when byte-by-byte copy is slower
cmp r2, #6
ble __agbabi_rmemcpy1
align_switch r0, r1, r3, __agbabi_rmemcpy1, .Lcopy_halves
@ Check if end needs word aligning
add r3, r0, r2
joaobapt_test r3
@ Copy byte tail to align
submi r2, r2, #1
ldrbmi r3, [r1, r2]
strbmi r3, [r0, r2]
@ r2 is now half aligned
@ Copy half tail to align
subcs r2, r2, #2
ldrhcs r3, [r1, r2]
strhcs r3, [r0, r2]
@ r2 is now word aligned
cmp r2, #32
blt .Lcopy_words
@ Word aligned, 32-byte copy
push {r0-r1, r4-r10}
add r0, r0, r2
add r1, r1, r2
.Lloop_32:
subs r2, r2, #32
ldmdbge r1!, {r3-r10}
stmdbge r0!, {r3-r10}
bgt .Lloop_32
pop {r0-r1, r4-r10}
bxeq lr
@ < 32 bytes remaining to be copied
add r2, r2, #32
.Lcopy_words:
subs r2, r2, #4
ldrge r3, [r1, r2]
strge r3, [r0, r2]
bgt .Lcopy_words
bxeq lr
@ Copy byte & half head
joaobapt_test_into r3, r2
@ Copy half
addcs r2, r2, #2
ldrhcs r3, [r1, r2]
strhcs r3, [r0, r2]
@ Copy byte
ldrbmi r3, [r1]
strbmi r3, [r0]
bx lr
.Lcopy_halves:
@ Copy byte tail to align
add r3, r0, r2
tst r3, #1
subne r2, r2, #1
ldrbne r3, [r1, r2]
strbne r3, [r0, r2]
@ r2 is now half aligned
.Lloop_2:
subs r2, r2, #2
ldrhge r3, [r1, r2]
strhge r3, [r0, r2]
bgt .Lloop_2
bxeq lr
@ Copy byte head
ldrb r3, [r1]
strb r3, [r0]
bx lr
.section .iwram.__agbabi_rmemcpy1, "ax", %progbits
.global __agbabi_rmemcpy1
.type __agbabi_rmemcpy1, %function
__agbabi_rmemcpy1:
subs r2, r2, #1
ldrbge r3, [r1, r2]
strbge r3, [r0, r2]
bgt __agbabi_rmemcpy1
bx lr
|
afska/beat-beast
| 2,088
|
butano/hw/3rd_party/agbabi/src/fiq_memcpy.s
|
@===============================================================================
@
@ Support:
@ __agbabi_fiq_memcpy4, __agbabi_fiq_memcpy4x4
@
@ Copyright (C) 2021-2023 agbabi contributors
@ For conditions of distribution and use, see copyright notice in LICENSE.md
@
@===============================================================================
.syntax unified
#include "macros.inc"
.arm
.align 2
.section .iwram.__agbabi_fiq_memcpy4, "ax", %progbits
.global __agbabi_fiq_memcpy4
.type __agbabi_fiq_memcpy4, %function
__agbabi_fiq_memcpy4:
cmp r2, #48
blt .Lcopy_words
push {r4-r7}
mrs r3, cpsr
@ Enter FIQ mode
bic r12, r3, #0x1f
orr r12, #0x11
msr cpsr, r12
msr spsr, r3
.Lloop_48:
subs r2, r2, #48
ldmiage r1!, {r3-r14}
stmiage r0!, {r3-r14}
bgt .Lloop_48
@ Exit FIQ mode
mrs r3, spsr
msr cpsr, r3
pop {r4-r7}
adds r2, r2, #48
bxeq lr
.Lcopy_words:
subs r2, r2, #4
ldrge r3, [r1], #4
strge r3, [r0], #4
bgt .Lcopy_words
bxeq lr
@ Copy byte & half tail
joaobapt_test r2
@ Copy half
ldrhcs r3, [r1], #2
strhcs r3, [r0], #2
@ Copy byte
ldrbmi r3, [r1]
strbmi r3, [r0]
bx lr
.section .iwram.__agbabi_fiq_memcpy4x4, "ax", %progbits
.global __agbabi_fiq_memcpy4x4
.type __agbabi_fiq_memcpy4x4, %function
__agbabi_fiq_memcpy4x4:
push {r4-r10}
cmp r2, #48
blt .Lcopy_tail_4x4
@ Enter FIQ mode
mrs r3, cpsr
bic r12, r3, #0x1f
orr r12, #0x11
msr cpsr, r12
msr spsr, r3
.Lloop_48_4x4:
subs r2, r2, #48
ldmiage r1!, {r3-r14}
stmiage r0!, {r3-r14}
bgt .Lloop_48_4x4
@ Exit FIQ mode
mrs r3, spsr
msr cpsr, r3
.Lcopy_tail_4x4:
@ JoaoBapt test 48-bytes
joaobapt_test_lsl r2, #27
ldmiacs r1!, {r3-r10}
stmiacs r0!, {r3-r10}
ldmiami r1!, {r3-r6}
stmiami r0!, {r3-r6}
pop {r4-r10}
bx lr
|
afska/beat-beast
| 1,714
|
butano/hw/3rd_party/agbabi/src/coroutine_asm.s
|
@===============================================================================
@
@ Support:
@ __agbabi_coro_resume, __agbabi_coro_yield, __agbabi_coro_pop
@
@ Copyright (C) 2021-2023 agbabi contributors
@ For conditions of distribution and use, see copyright notice in LICENSE.md
@
@===============================================================================
.syntax unified
.arm
.align 2
.section .iwram.__agbabi_coro_resume, "ax", %progbits
.global __agbabi_coro_resume
.type __agbabi_coro_resume, %function
__agbabi_coro_resume:
push {r4-r11, lr}
mov r1, sp
ldr r2, [r0]
bic r2, r2, #0x80000000
mov sp, r2
pop {r4-r11, lr}
str r1, [r0]
bx lr
.section .iwram.__agbabi_coro_yield, "ax", %progbits
.global __agbabi_coro_yield
.type __agbabi_coro_yield, %function
__agbabi_coro_yield:
push {r4-r11, lr}
mov r2, sp
ldr sp, [r0]
pop {r4-r11, lr}
str r2, [r0]
@ Move yield value into r0 and return
mov r0, r1
bx lr
.section .iwram.__agbabi_coro_pop, "ax", %progbits
.global __agbabi_coro_pop
.type __agbabi_coro_pop, %function
__agbabi_coro_pop:
ldr r1, [sp, #4]
mov lr, pc
bx r1
ldr r1, [sp]
@ r0 contains return value
@ r1 points to agbabi_coro_t*
@ Allocate space for storing r4-r12, lr
sub r2, sp, #40
ldr r3, =__agbabi_coro_pop
str r3, [r2, #36] @ Next resume will call __agbabi_coro_pop
@ Load suspend context
ldr sp, [r1]
pop {r4-r11, lr}
@ Set "joined" flag
orr r2, r2, #0x80000000
str r2, [r1]
bx lr
|
afska/beat-beast
| 2,980
|
butano/hw/3rd_party/agbabi/src/memcpy.s
|
@===============================================================================
@
@ ABI:
@ __aeabi_memcpy, __aeabi_memcpy4, __aeabi_memcpy8
@ Standard:
@ memcpy
@ Support:
@ __agbabi_memcpy2, __agbabi_memcpy1
@
@ Copyright (C) 2021-2023 agbabi contributors
@ For conditions of distribution and use, see copyright notice in LICENSE.md
@
@===============================================================================
.syntax unified
#include "macros.inc"
.arm
.align 2
.section .iwram.__aeabi_memcpy, "ax", %progbits
.global __aeabi_memcpy
.type __aeabi_memcpy, %function
__aeabi_memcpy:
@ >6-bytes is roughly the threshold when byte-by-byte copy is slower
cmp r2, #6
ble __agbabi_memcpy1
align_switch r0, r1, r3, __agbabi_memcpy1, .Lcopy_halves
@ Check if r0 (or r1) needs word aligning
rsbs r3, r0, #4
joaobapt_test r3
@ Copy byte head to align
ldrbmi r3, [r1], #1
strbmi r3, [r0], #1
submi r2, r2, #1
@ r0, r1 are now half aligned
@ Copy half head to align
ldrhcs r3, [r1], #2
strhcs r3, [r0], #2
subcs r2, r2, #2
@ r0, r1 are now word aligned
.global __aeabi_memcpy8
.type __aeabi_memcpy8, %function
__aeabi_memcpy8:
.global __aeabi_memcpy4
.type __aeabi_memcpy4, %function
__aeabi_memcpy4:
cmp r2, #32
blt .Lcopy_words
@ Word aligned, 32-byte copy
push {r4-r10}
.Lloop_32:
subs r2, r2, #32
ldmiage r1!, {r3-r10}
stmiage r0!, {r3-r10}
bgt .Lloop_32
pop {r4-r10}
bxeq lr
@ < 32 bytes remaining to be copied
add r2, r2, #32
.Lcopy_words:
cmp r2, #4
blt .Lcopy_halves
.Lloop_4:
subs r2, r2, #4
ldrge r3, [r1], #4
strge r3, [r0], #4
bgt .Lloop_4
bxeq lr
@ Copy byte & half tail
@ This test still works when r2 is negative
joaobapt_test r2
@ Copy half
ldrhcs r3, [r1], #2
strhcs r3, [r0], #2
@ Copy byte
ldrbmi r3, [r1]
strbmi r3, [r0]
bx lr
.Lcopy_halves:
@ Copy byte head to align
tst r0, #1
ldrbne r3, [r1], #1
strbne r3, [r0], #1
subne r2, r2, #1
@ r0, r1 are now half aligned
.global __agbabi_memcpy2
.type __agbabi_memcpy2, %function
__agbabi_memcpy2:
subs r2, r2, #2
ldrhge r3, [r1], #2
strhge r3, [r0], #2
bgt __agbabi_memcpy2
bxeq lr
@ Copy byte tail
adds r2, r2, #2
ldrbne r3, [r1]
strbne r3, [r0]
bx lr
.section .iwram.__agbabi_memcpy1, "ax", %progbits
.global __agbabi_memcpy1
.type __agbabi_memcpy1, %function
__agbabi_memcpy1:
subs r2, r2, #1
ldrbge r3, [r1], #1
strbge r3, [r0], #1
bgt __agbabi_memcpy1
bx lr
.section .iwram.memcpy, "ax", %progbits
.global memcpy
.type memcpy, %function
memcpy:
push {r0, lr}
bl __aeabi_memcpy
pop {r0, lr}
bx lr
|
afska/beat-beast
| 1,504
|
butano/hw/3rd_party/agbabi/src/lmul.s
|
@===============================================================================
@
@ ABI:
@ __aeabi_lmul, __aeabi_llsl, __aeabi_llsr, __aeabi_lasr
@
@ Copyright (C) 2021-2023 agbabi contributors
@ For conditions of distribution and use, see copyright notice in LICENSE.md
@
@===============================================================================
.syntax unified
.arm
.align 2
.section .iwram.__aeabi_lmul, "ax", %progbits
.global __aeabi_lmul
.type __aeabi_lmul, %function
__aeabi_lmul:
mul r3, r0, r3
mla r1, r2, r1, r3
umull r0, r3, r2, r0
add r1, r1, r3
bx lr
.section .iwram.__aeabi_llsl, "ax", %progbits
.global __aeabi_llsl
.type __aeabi_llsl, %function
__aeabi_llsl:
subs r3, r2, #32
rsb r12, r2, #32
lslmi r1, r1, r2
lslpl r1, r0, r3
orrmi r1, r1, r0, lsr r12
lsl r0, r0, r2
bx lr
.section .iwram.__aeabi_llsr, "ax", %progbits
.global __aeabi_llsr
.type __aeabi_llsr, %function
__aeabi_llsr:
subs r3, r2, #32
rsb r12, r2, #32
lsrmi r0, r0, r2
lsrpl r0, r1, r3
orrmi r0, r0, r1, lsl r12
lsr r1, r1, r2
bx lr
.section .iwram.__aeabi_lasr, "ax", %progbits
.global __aeabi_lasr
.type __aeabi_lasr, %function
__aeabi_lasr:
subs r3, r2, #32
rsb r12, r2, #32
lsrmi r0, r0, r2
asrpl r0, r1, r3
orrmi r0, r0, r1, lsl r12
asr r1, r1, r2
bx lr
|
agatti/hopper-plugins
| 3,914
|
test/TMS1000/tms1000opcodes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
CPU tms1000
; 0xh
COMX
A8AAC
YNEA
TAM
TAMZA
A10AAC
A6AAC
DAN
TKA
KNEZ
TDO
CLO
RSTR
SETR
IA
RETN
; 1xh
LDP 0
LDP 1
LDP 2
LDP 3
LDP 4
LDP 5
LDP 6
LDP 7
LDP 8
LDP 9
LDP 10
LDP 11
LDP 12
LDP 13
LDP 14
LDP 15
; 2xh
TAMIY
TMA
TMY
TYA
TAY
AMAAC
MNEZ
SAMAN
IMAC
ALEM
DMAN
IYC
DYN
CPAIZ
XMA
CLA
; 3xh
SBIT 0
SBIT 1
SBIT 2
SBIT 3
RBIT 0
RBIT 1
RBIT 2
RBIT 3
TBIT1 0
TBIT1 1
TBIT1 2
TBIT1 3
LDX 0
LDX 1
LDX 2
LDX 3
; 4xh
TCY 0
TCY 1
TCY 2
TCY 3
TCY 4
TCY 5
TCY 6
TCY 7
TCY 8
TCY 9
TCY 10
TCY 11
TCY 12
TCY 13
TCY 14
TCY 15
; 5xh
YNEC 0
YNEC 1
YNEC 2
YNEC 3
YNEC 4
YNEC 5
YNEC 6
YNEC 7
YNEC 8
YNEC 9
YNEC 10
YNEC 11
YNEC 12
YNEC 13
YNEC 14
YNEC 15
; 6xh
TCMIY 0
TCMIY 1
TCMIY 2
TCMIY 3
TCMIY 4
TCMIY 5
TCMIY 6
TCMIY 7
TCMIY 8
TCMIY 9
TCMIY 10
TCMIY 11
TCMIY 12
TCMIY 13
TCMIY 14
TCMIY 15
; 7xh
ALEC 0
ALEC 1
ALEC 2
ALEC 3
ALEC 4
ALEC 5
ALEC 6
ALEC 7
ALEC 8
ALEC 9
ALEC 10
ALEC 11
ALEC 12
ALEC 13
ALEC 14
ALEC 15
; 8xh
BR 00h
BR 01h
BR 02h
BR 03h
BR 04h
BR 05h
BR 06h
BR 07h
BR 08h
BR 09h
BR 0Ah
BR 0Bh
BR 0Ch
BR 0Dh
BR 0Eh
BR 0Fh
; 9xh
BR 10h
BR 11h
BR 12h
BR 13h
BR 14h
BR 15h
BR 16h
BR 17h
BR 18h
BR 19h
BR 1Ah
BR 1Bh
BR 1Ch
BR 1Dh
BR 1Eh
BR 1Fh
; Axh
BR 20h
BR 21h
BR 22h
BR 23h
BR 24h
BR 25h
BR 26h
BR 27h
BR 28h
BR 29h
BR 2Ah
BR 2Bh
BR 2Ch
BR 2Dh
BR 2Eh
BR 2Fh
; Bxh
BR 30h
BR 31h
BR 32h
BR 33h
BR 34h
BR 35h
BR 36h
BR 37h
BR 38h
BR 39h
BR 3Ah
BR 3Bh
BR 3Ch
BR 3Dh
BR 3Eh
BR 3Fh
; Cxh
CALL 00h
CALL 01h
CALL 02h
CALL 03h
CALL 04h
CALL 05h
CALL 06h
CALL 07h
CALL 08h
CALL 09h
CALL 0Ah
CALL 0Bh
CALL 0Ch
CALL 0Dh
CALL 0Eh
CALL 0Fh
; Dxh
CALL 10h
CALL 11h
CALL 12h
CALL 13h
CALL 14h
CALL 15h
CALL 16h
CALL 17h
CALL 18h
CALL 19h
CALL 1Ah
CALL 1Bh
CALL 1Ch
CALL 1Dh
CALL 1Eh
CALL 1Fh
; Exh
CALL 20h
CALL 21h
CALL 22h
CALL 23h
CALL 24h
CALL 25h
CALL 26h
CALL 27h
CALL 28h
CALL 29h
CALL 2Ah
CALL 2Bh
CALL 2Ch
CALL 2Dh
CALL 2Eh
CALL 2Fh
; Fxh
CALL 30h
CALL 31h
CALL 32h
CALL 33h
CALL 34h
CALL 35h
CALL 36h
CALL 37h
CALL 38h
CALL 39h
CALL 3Ah
CALL 3Bh
CALL 3Ch
CALL 3Dh
CALL 3Eh
CALL 3Fh
|
agatti/hopper-plugins
| 3,899
|
test/TMS1000/tms1100opcodes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
CPU tms1100
; 0xh
MNEA
ALEM
YNEA
XMA
DYN
IYC
AMAAC
DMAN
TKA
COMX
TDO
COMC
RSTR
SETR
KNEZ
RETN
; 1xh
LDP 0
LDP 1
LDP 2
LDP 3
LDP 4
LDP 5
LDP 6
LDP 7
LDP 8
LDP 9
LDP 10
LDP 11
LDP 12
LDP 13
LDP 14
LDP 15
; 2xh
TAY
TMA
TMY
TYA
TAMDYN
TAMIYC
TAMZA
TAM
LDX 0
LDX 1
LDX 2
LDX 3
LDX 4
LDX 5
LDX 6
LDX 7
; 3xh
SBIT 0
SBIT 1
SBIT 2
SBIT 3
RBIT 0
RBIT 1
RBIT 2
RBIT 3
TBIT1 0
TBIT1 1
TBIT1 2
TBIT1 3
SAMAN
CPAIZ
IMAC
MNEZ
; 4xh
TCY 0
TCY 1
TCY 2
TCY 3
TCY 4
TCY 5
TCY 6
TCY 7
TCY 8
TCY 9
TCY 10
TCY 11
TCY 12
TCY 13
TCY 14
TCY 15
; 5xh
YNEC 0
YNEC 1
YNEC 2
YNEC 3
YNEC 4
YNEC 5
YNEC 6
YNEC 7
YNEC 8
YNEC 9
YNEC 10
YNEC 11
YNEC 12
YNEC 13
YNEC 14
YNEC 15
; 6xh
TCMIY 0
TCMIY 1
TCMIY 2
TCMIY 3
TCMIY 4
TCMIY 5
TCMIY 6
TCMIY 7
TCMIY 8
TCMIY 9
TCMIY 10
TCMIY 11
TCMIY 12
TCMIY 13
TCMIY 14
TCMIY 15
; 7xh
IAC
A9AAC
A5AAC
A13AAC
A3AAC
A11AAC
A7AAC
DAN
A2AAC
A10AAC
A6AAC
A14AAC
A4AAC
A12AAC
A8AAC
CLA
; 8xh
BR 00h
BR 01h
BR 02h
BR 03h
BR 04h
BR 05h
BR 06h
BR 07h
BR 08h
BR 09h
BR 0Ah
BR 0Bh
BR 0Ch
BR 0Dh
BR 0Eh
BR 0Fh
; 9xh
BR 10h
BR 11h
BR 12h
BR 13h
BR 14h
BR 15h
BR 16h
BR 17h
BR 18h
BR 19h
BR 1Ah
BR 1Bh
BR 1Ch
BR 1Dh
BR 1Eh
BR 1Fh
; Axh
BR 20h
BR 21h
BR 22h
BR 23h
BR 24h
BR 25h
BR 26h
BR 27h
BR 28h
BR 29h
BR 2Ah
BR 2Bh
BR 2Ch
BR 2Dh
BR 2Eh
BR 2Fh
; Bxh
BR 30h
BR 31h
BR 32h
BR 33h
BR 34h
BR 35h
BR 36h
BR 37h
BR 38h
BR 39h
BR 3Ah
BR 3Bh
BR 3Ch
BR 3Dh
BR 3Eh
BR 3Fh
; Cxh
CALL 00h
CALL 01h
CALL 02h
CALL 03h
CALL 04h
CALL 05h
CALL 06h
CALL 07h
CALL 08h
CALL 09h
CALL 0Ah
CALL 0Bh
CALL 0Ch
CALL 0Dh
CALL 0Eh
CALL 0Fh
; Dxh
CALL 10h
CALL 11h
CALL 12h
CALL 13h
CALL 14h
CALL 15h
CALL 16h
CALL 17h
CALL 18h
CALL 19h
CALL 1Ah
CALL 1Bh
CALL 1Ch
CALL 1Dh
CALL 1Eh
CALL 1Fh
; Exh
CALL 20h
CALL 21h
CALL 22h
CALL 23h
CALL 24h
CALL 25h
CALL 26h
CALL 27h
CALL 28h
CALL 29h
CALL 2Ah
CALL 2Bh
CALL 2Ch
CALL 2Dh
CALL 2Eh
CALL 2Fh
; Fxh
CALL 30h
CALL 31h
CALL 32h
CALL 33h
CALL 34h
CALL 35h
CALL 36h
CALL 37h
CALL 38h
CALL 39h
CALL 3Ah
CALL 3Bh
CALL 3Ch
CALL 3Dh
CALL 3Eh
CALL 3Fh
|
agatti/hopper-plugins
| 1,499
|
test/8x300/jump.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
CPU 8x300
ORG $0
; Test jump within bounds.
JMP target
NOP
NOP
target NOP
; Test jump outside bounds.
JMP *+$10
|
agatti/hopper-plugins
| 1,444
|
test/8x300/synthetic8x305.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 8x305
org $0
nop
xml $10
nop
xml $20
nop
halt
|
agatti/hopper-plugins
| 1,799
|
test/8x300/opcodes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
CPU 8x300
ORG $0
; Test ADD opcode.
ADD R1,R1
ADD R2(1),R2
ADD 4,R3
; Test AND opcode.
AND R2,R2
AND R3(1),R3
AND 3,R2
; Test MOVE opcode.
MOVE R1,IVL
MOVE R5(4),R1
MOVE 3,R3
; Test NZT opcode.
NZT R4,*
NZT LIV1,*
; Test XEC opcode.
XEC $0(R4)
XEC $1(R1)
XEC $1(liv2),2
; Test XMIT opcode.
XMIT 1,R1
XMIT 0,R2
XMIT -1,R3
; Test XOR opcode.
XOR R4,R1
XOR R5(1),R6
|
agatti/hopper-plugins
| 1,483
|
test/8x300/switch.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 8x300
org $0
xec jumptable(r1)
jmp *
jumptable jmp $0010
jmp $0020
jmp $0030
jmp $0040
|
agatti/hopper-plugins
| 1,411
|
test/8x300/synthetic8x300.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 8x300
org $0
nop
halt
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700table42a16i8.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:0
assume x:1
include "m7700table42.inc"
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700opcodesa8i16.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:1
assume x:0
include "m7700opcodes.inc"
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700opcodesa16i8.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:0
assume x:1
include "m7700opcodes.inc"
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700table42a8i16.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:1
assume x:0
include "m7700table42.inc"
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700table42a8i8.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:1
assume x:1
include "m7700table42.inc"
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700table89a16i8.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:0
assume x:1
include "m7700table89.inc"
|
agatti/hopper-plugins
| 1,702
|
test/65816/65816width.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 65816
page 0
org $1000
; Switch to 8/8
SEP #$30
assume m:1
assume x:1
LDA #$55
; Switch to 8/16
REP #$10
assume m:1
assume x:0
CPX #$5555
; Switch to 16/16
REP #$20
assume m:0
assume x:0
CPX #$5555
LDA #$5555
; Switch to 16/8
SEP #$10
assume m:0
assume x:1
LDA #$5555
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700table89a8i8.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:1
assume x:1
include "m7700table89.inc"
|
agatti/hopper-plugins
| 6,237
|
test/65816/65816opcodes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 65816
org $1000
ZEROPAGE_0 equ $0
ZEROPAGE_1 equ $1
ZEROPAGE_2 equ $2
ZEROPAGE_3 equ $3
ZEROPAGE_4 equ $4
ZEROPAGE_5 equ $5
ZEROPAGE_6 equ $6
ZEROPAGE_7 equ $7
ZEROPAGE_8 equ $8
ZEROPAGE_9 equ $9
ZEROPAGE_A equ $A
ZEROPAGE_B equ $B
ZEROPAGE_C equ $C
ZEROPAGE_D equ $D
ZEROPAGE_E equ $E
ZEROPAGE_F equ $F
assume m:1
assume x:1
row_0 BRK
ORA (ZEROPAGE_0,X)
COP #$00
ORA ZEROPAGE_0,S
TSB ZEROPAGE_0
ORA ZEROPAGE_0
ASL ZEROPAGE_0
ORAL (ZEROPAGE_0)
PHP
ORA #$00
ASL
PHD
TSB datablockabs
ORA datablockabs
ASL datablockabs
ORA $FF0000
JMP row_1
row_1 BPL row_1_target
ORA (ZEROPAGE_1),Y
row_1_target ORA (ZEROPAGE_1)
ORA (ZEROPAGE_1,S),Y
TRB ZEROPAGE_1
ORA ZEROPAGE_1,X
ASL ZEROPAGE_1,X
ORAL (ZEROPAGE_1),Y
CLC
ORA datablockabs,Y
INC
TCS
TRB datablockabs
ORA datablockabs,X
ASL datablockabs,X
ORA $FF1111,X
JMP row_2
row_2 JSR farcode
AND (ZEROPAGE_2,X)
JSR $FF2222
AND ZEROPAGE_2,S
BIT ZEROPAGE_2
AND ZEROPAGE_2
ROL ZEROPAGE_2
ANDL (ZEROPAGE_2)
PLP
AND #$22
ROL
PLD
BIT datablockabs
AND datablockabs
ROL datablockabs
AND $FF2222
JMP row_3
row_3 BMI row_3_target
AND (ZEROPAGE_3),Y
row_3_target AND (ZEROPAGE_3)
AND (ZEROPAGE_3,S),Y
BIT ZEROPAGE_3,X
AND ZEROPAGE_3,X
ROL ZEROPAGE_3,X
ANDL (ZEROPAGE_3),Y
SEC
AND datablockabs,Y
DEC
TSC
BIT datablockabs,X
AND datablockabs,X
ROL datablockabs,X
AND $FF3333,X
JMP row_4
row_4 RTI
EOR (ZEROPAGE_4,X)
BYT $42 ; WDM
EOR ZEROPAGE_3,S
MVP $440000, $440000
EOR ZEROPAGE_4
LSR ZEROPAGE_4
EORL (ZEROPAGE_4)
PHA
EOR #$44
LSR
PHK
JMP farcode
EOR datablockabs
LSR datablockabs
EOR $FF4444
JMP row_5
row_5 BVC row_5_target
EOR (ZEROPAGE_5),Y
row_5_target EOR (ZEROPAGE_5)
EOR (ZEROPAGE_5,S),Y
MVN $550000, $550000
EOR ZEROPAGE_5,X
LSR ZEROPAGE_5,X
EORL (ZEROPAGE_5),Y
CLI
EOR datablockabs,Y
PHY
TCD
JMP $FF5555
EOR datablockabs,X
LSR datablockabs,X
EOR $FF5555,X
JMP row_6
row_6 RTS
ADC (ZEROPAGE_6,X)
PER datablockabs
ADC ZEROPAGE_6,S
STZ ZEROPAGE_6
ADC ZEROPAGE_6
ROR ZEROPAGE_6
ADCL (ZEROPAGE_6)
PLA
ADC #$66
ROR
RTL
JMP (datablockabs)
ADC datablockabs
ROR datablockabs
ADC $FF6666
JMP row_7
row_7 BVS row_7_target
ADC (ZEROPAGE_7),Y
row_7_target ADC (ZEROPAGE_7)
ADC (ZEROPAGE_7,S),Y
STZ ZEROPAGE_7,X
ADC ZEROPAGE_7,X
ROR ZEROPAGE_7,X
ADCL (ZEROPAGE_7),Y
SEI
ADC datablockabs,Y
PLY
TDC
JMP (datablockabs,X)
ADC datablockabs,X
ROR datablockabs,X
ADC $FF7777,X
JMP row_8
row_8 BRA row_8_target
STA (ZEROPAGE_8,X)
row_8_target BRL datablockabs
STA ZEROPAGE_8,S
STY ZEROPAGE_8
STA ZEROPAGE_8
STX ZEROPAGE_8
STAL (ZEROPAGE_8)
DEY
BIT #$88
TXA
PHB
STY datablockabs
STA datablockabs
STX datablockabs
STA $FF8888
JMP row_9
row_9 BCC row_9_target
STA (ZEROPAGE_9),Y
row_9_target STA (ZEROPAGE_9)
STA (ZEROPAGE_9,S),Y
STY ZEROPAGE_9,X
STA ZEROPAGE_9,X
STX ZEROPAGE_9,Y
STAL (ZEROPAGE_9),Y
TYA
STA datablockabs,Y
TXS
TXY
STA datablockabs,X
STZ datablockabs,X
STA $FF9999,X
JMP row_a
row_a LDY #$AA
LDA (ZEROPAGE_A,X)
LDX #$AA
LDA ZEROPAGE_A,S
LDY ZEROPAGE_A
LDA ZEROPAGE_A
LDX ZEROPAGE_A
LDAL (ZEROPAGE_A)
TAY
LDA #$AA
TAX
PLB
LDY datablockabs
LDA datablockabs
LDX datablockabs
LDA $FFAAAA
JMP row_b
row_b BCS row_b_target
LDA (ZEROPAGE_B),Y
row_b_target LDA (ZEROPAGE_B)
LDA (ZEROPAGE_B,S),Y
LDY ZEROPAGE_B,X
LDA ZEROPAGE_B,X
LDX ZEROPAGE_B,Y
LDAL (ZEROPAGE_B),Y
CLV
LDA datablockabs,Y
TSX
TYX
LDY datablockabs,X
LDA datablockabs,X
LDX datablockabs,Y
LDA $FFBBBB,X
JMP row_c
row_c CPY #$CC
CMP (ZEROPAGE_C,X)
REP #$CC
CMP ZEROPAGE_C,S
CPY ZEROPAGE_C
CMP ZEROPAGE_C
DEC ZEROPAGE_C
CMPL (ZEROPAGE_C)
INY
CMP #$CC
DEX
WAI
CPY datablockabs
CMP datablockabs
DEC datablockabs
CMP $FFCCCC
JMP row_d
row_d BNE row_d_target
CMP (ZEROPAGE_D),Y
row_d_target CMP (ZEROPAGE_D)
CMP (ZEROPAGE_D,S),Y
PEI (ZEROPAGE_D)
CMP ZEROPAGE_D,X
DEC ZEROPAGE_D,X
CMPL (ZEROPAGE_D),Y
CLD
CMP datablockabs,Y
PHX
STP
JML datablockabs
CMP datablockabs,X
DEC datablockabs,X
CMP $FFDDDD,X
JMP row_e
row_e CPX #$EE
SBC (ZEROPAGE_E,X)
SEP #$EE
SBC ZEROPAGE_E,S
CPX ZEROPAGE_E
SBC ZEROPAGE_E
INC ZEROPAGE_E
SBCL (ZEROPAGE_E)
INX
SBC #$EE
NOP
XBA
CPX datablockabs
SBC datablockabs
INC datablockabs
SBC $FFEEEE
JMP row_f
row_f BEQ row_f_target
SBC (ZEROPAGE_F),Y
row_f_target SBC (ZEROPAGE_F)
SBC (ZEROPAGE_F,S),Y
PEA $1000
SBC ZEROPAGE_F,X
INC ZEROPAGE_F,X
SBCL (ZEROPAGE_F),Y
SED
SBC datablockabs,Y
PLX
XCE
JSR (datablockabs,X)
SBC datablockabs,X
INC datablockabs,X
SBC $FFFFFF,X
JMP end
end RTS
datablockabs ADR $1234
farcode RTI
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700opcodesa16i16.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:0
assume x:0
include "m7700opcodes.inc"
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700opcodesa8i8.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:1
assume x:1
include "m7700opcodes.inc"
|
agatti/hopper-plugins
| 1,576
|
test/65816/65816per.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 65816
org $1000
per_same PER per_same
per_back_one NOP
PER per_back_one
NOP
NOP
NOP
per_backwards NOP
NOP
PER per_backwards
PER per_forward
NOP
NOP
NOP
NOP
per_forward NOP
RTS
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700table42a16i16.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:0
assume x:0
include "m7700table42.inc"
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700table89a16i16.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:0
assume x:0
include "m7700table89.inc"
|
agatti/hopper-plugins
| 1,440
|
test/65816/m7700table89a8i16.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps7700
assume m:1
assume x:0
include "m7700table89.inc"
|
agatti/hopper-plugins
| 2,087
|
test/65816/65816modes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 65816
page 0
org $1000
assume m:1
assume x:1
ADC #$11
AND #$22
BIT #$33
CMP #$44
CPX #$55
CPY #$66
EOR #$77
LDA #$88
LDX #$99
LDY #$AA
ORA #$BB
SBC #$CC
assume m:0
assume x:1
ADC #$1111
AND #$2222
BIT #$3333
CMP #$4444
CPX #$55
CPY #$66
EOR #$7777
LDA #$8888
LDX #$99
LDY #$AA
ORA #$BBBB
SBC #$CCCC
assume m:1
assume x:0
ADC #$11
AND #$22
BIT #$33
CMP #$44
CPX #$5555
CPY #$6666
EOR #$77
LDA #$88
LDX #$9999
LDY #$AAAA
ORA #$BB
SBC #$CC
assume m:0
assume x:0
ADC #$1111
AND #$2222
BIT #$3333
CMP #$4444
CPX #$5555
CPY #$6666
EOR #$7777
LDA #$8888
LDX #$9999
LDY #$AAAA
ORA #$BBBB
SBC #$CCCC
|
agatti/hopper-plugins
| 2,732
|
test/6502/6502jumps.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 6502
org $1000
farjumps JMP $7FFF
JMP $8000
JMP $8001
JMP $FFFE
JMP $FFFF
jumpstart NOP
NOP
JMP jumpstart
NOP
NOP
loop JMP loop
NOP
BCC bcc_forward
NOP
bcc_forward NOP
NOP
NOP
NOP
bcc_backwards NOP
NOP
NOP
NOP
BCC bcc_backwards
NOP
BCS bcs_forward
NOP
bcs_forward NOP
NOP
NOP
NOP
bcs_backwards NOP
NOP
NOP
NOP
BCS bcs_backwards
NOP
BEQ beq_forward
NOP
beq_forward NOP
NOP
NOP
NOP
beq_backwards NOP
NOP
NOP
NOP
BEQ beq_backwards
NOP
BMI bmi_forward
NOP
bmi_forward NOP
NOP
NOP
NOP
bmi_backwards NOP
NOP
NOP
NOP
BMI bmi_backwards
NOP
BNE bne_forward
NOP
bne_forward NOP
NOP
NOP
NOP
bne_backwards NOP
NOP
NOP
NOP
BNE bne_backwards
NOP
BPL bpl_forward
NOP
bpl_forward NOP
NOP
NOP
NOP
bpl_backwards NOP
NOP
NOP
NOP
BPL bpl_backwards
NOP
BVC bvc_forward
NOP
bvc_forward NOP
NOP
NOP
NOP
bvc_backwards NOP
NOP
NOP
NOP
BVC bvc_backwards
NOP
BVS bvs_forward
NOP
bvs_forward NOP
NOP
NOP
NOP
bvs_backwards NOP
NOP
NOP
NOP
BVS bvs_backwards
NOP
JMP jmp_forward
NOP
jmp_forward NOP
NOP
NOP
NOP
jmp_backwards NOP
NOP
NOP
NOP
JMP jmp_backwards
NOP
JSR jsr_forward
NOP
jsr_forward NOP
NOP
NOP
NOP
jsr_backwards NOP
NOP
NOP
NOP
JSR jsr_backwards
NOP
RTS
|
agatti/hopper-plugins
| 4,532
|
test/6502/6502opcodes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 6502
org $1000
ZEROPAGE_0 equ $0
ZEROPAGE_1 equ $1
ZEROPAGE_2 equ $2
ZEROPAGE_3 equ $3
ZEROPAGE_4 equ $4
ZEROPAGE_5 equ $5
ZEROPAGE_6 equ $6
ZEROPAGE_7 equ $7
ZEROPAGE_8 equ $8
ZEROPAGE_9 equ $9
ZEROPAGE_A equ $A
ZEROPAGE_B equ $B
ZEROPAGE_C equ $C
ZEROPAGE_D equ $D
ZEROPAGE_E equ $E
ZEROPAGE_F equ $F
row_0 BRK
ORA (ZEROPAGE_0,X)
ORA ZEROPAGE_0
ASL ZEROPAGE_0
PHP
ORA $00
ASL
ORA datablockabs
ASL datablockabs
JMP row_1
row_1 BPL row_1_target
ORA (ZEROPAGE_1),Y
row_1_target ORA ZEROPAGE_1,X
ASL ZEROPAGE_1,X
CLC
ORA datablockabs,Y
ORA datablockabs,X
ASL datablockabs,X
JMP row_2
row_2 JSR farcode
AND (ZEROPAGE_2,X)
BIT ZEROPAGE_2
AND ZEROPAGE_2
ROL ZEROPAGE_2
PLP
AND #$22
ROL
BIT datablockabs
AND datablockabs
ROL datablockabs
JMP row_3
row_3 BMI row_3_target
AND (ZEROPAGE_3),Y
row_3_target AND ZEROPAGE_3,X
ROL ZEROPAGE_3,X
SEC
AND datablockabs,Y
AND datablockabs,X
ROL datablockabs,X
JMP row_4
row_4 RTI
EOR (ZEROPAGE_4,X)
EOR ZEROPAGE_4
LSR ZEROPAGE_4
PHA
EOR #$44
LSR
JMP farcode
EOR datablockabs
LSR datablockabs
JMP row_5
row_5 BVC row_5_target
EOR (ZEROPAGE_5),Y
row_5_target EOR ZEROPAGE_5,X
LSR ZEROPAGE_5,X
CLI
EOR datablockabs,Y
EOR datablockabs,X
LSR datablockabs,X
JMP row_6
row_6 RTS
ADC (ZEROPAGE_6,X)
ADC ZEROPAGE_6
ROR ZEROPAGE_6
PLA
ADC #$66
ROR
JMP (farcode)
ADC datablockabs
ROR datablockabs
JMP row_7
row_7 BVS row_7_target
ADC (ZEROPAGE_7),Y
row_7_target ADC ZEROPAGE_7,X
ROR ZEROPAGE_7,X
SEI
ADC datablockabs,Y
ADC datablockabs,X
ROR datablockabs,X
JMP row_8
row_8 STA (ZEROPAGE_8,X)
STY ZEROPAGE_8
STA ZEROPAGE_8
STX ZEROPAGE_8
DEY
TXA
STY datablockabs
STA datablockabs
STX datablockabs
JMP row_9
row_9 BCC row_9_target
STA (ZEROPAGE_9),Y
row_9_target STY ZEROPAGE_9,X
STA ZEROPAGE_9,X
STX ZEROPAGE_9,Y
TYA
STA datablockabs,Y
TXS
STA datablockabs,X
JMP row_a
row_a LDY #$AA
LDA (ZEROPAGE_A,X)
LDX #$AA
LDY ZEROPAGE_A
LDA ZEROPAGE_A
LDX ZEROPAGE_A
TAY
LDA #$AA
TAX
LDY datablockabs
LDA datablockabs
LDX datablockabs
JMP row_b
row_b BCS row_b_target
LDA (ZEROPAGE_B),Y
row_b_target LDY ZEROPAGE_B,X
LDA ZEROPAGE_B,X
LDX ZEROPAGE_B,Y
CLV
LDA datablockabs,Y
TSX
LDY datablockabs,X
LDA datablockabs,X
LDX datablockabs,Y
JMP row_c
row_c CPY #$CC
CMP (ZEROPAGE_C,X)
CPY ZEROPAGE_C
CMP ZEROPAGE_C
DEC ZEROPAGE_C
INY
CMP #$CC
DEX
CPY datablockabs
CMP datablockabs
DEC datablockabs
JMP row_d
row_d BNE row_d_target
CMP (ZEROPAGE_D),Y
row_d_target CMP ZEROPAGE_D,X
DEC ZEROPAGE_D,X
CLD
CMP datablockabs,Y
CMP datablockabs,X
DEC datablockabs,X
JMP row_e
row_e CPX #$EE
SBC (ZEROPAGE_E,X)
CPX ZEROPAGE_E
SBC ZEROPAGE_E
INC ZEROPAGE_E
INX
SBC #$EE
NOP
CPX datablockabs
SBC datablockabs
INC datablockabs
JMP row_f
row_f BEQ row_f_target
SBC (ZEROPAGE_F),Y
row_f_target SBC ZEROPAGE_F,X
INC ZEROPAGE_F,X
SED
SBC datablockabs,Y
SBC datablockabs,X
INC datablockabs,X
JMP end
end RTS
datablockabs ADR $1234
farcode RTI
|
agatti/hopper-plugins
| 2,853
|
test/6502/65c02jumps.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 65c02
org $1000
farjumps JMP $7FFF
JMP $8000
JMP $8001
JMP $FFFE
JMP $FFFF
jumpstart NOP
NOP
JMP jumpstart
NOP
NOP
loop JMP loop
NOP
BCC bcc_forward
NOP
bcc_forward NOP
NOP
NOP
NOP
bcc_backwards NOP
NOP
NOP
NOP
BCC bcc_backwards
NOP
BCS bcs_forward
NOP
bcs_forward NOP
NOP
NOP
NOP
bcs_backwards NOP
NOP
NOP
NOP
BCS bcs_backwards
NOP
BEQ beq_forward
NOP
beq_forward NOP
NOP
NOP
NOP
beq_backwards NOP
NOP
NOP
NOP
BEQ beq_backwards
NOP
BMI bmi_forward
NOP
bmi_forward NOP
NOP
NOP
NOP
bmi_backwards NOP
NOP
NOP
NOP
BMI bmi_backwards
NOP
BNE bne_forward
NOP
bne_forward NOP
NOP
NOP
NOP
bne_backwards NOP
NOP
NOP
NOP
BNE bne_backwards
NOP
BPL bpl_forward
NOP
bpl_forward NOP
NOP
NOP
NOP
bpl_backwards NOP
NOP
NOP
NOP
BPL bpl_backwards
NOP
BVC bvc_forward
NOP
bvc_forward NOP
NOP
NOP
NOP
bvc_backwards NOP
NOP
NOP
NOP
BVC bvc_backwards
NOP
BVS bvs_forward
NOP
bvs_forward NOP
NOP
NOP
NOP
bvs_backwards NOP
NOP
NOP
NOP
BVS bvs_backwards
NOP
JMP jmp_forward
NOP
jmp_forward NOP
NOP
NOP
NOP
jmp_backwards NOP
NOP
NOP
NOP
JMP jmp_backwards
NOP
JSR jsr_forward
NOP
jsr_forward NOP
NOP
NOP
NOP
jsr_backwards NOP
NOP
NOP
NOP
JSR jsr_backwards
NOP
BRA bra_forward
NOP
bra_forward NOP
NOP
NOP
NOP
bra_backwards NOP
NOP
NOP
NOP
BRA bra_backwards
NOP
RTS
|
agatti/hopper-plugins
| 4,951
|
test/6502/65c02opcodes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 65c02
org $1000
ZEROPAGE_0 equ $0
ZEROPAGE_1 equ $1
ZEROPAGE_2 equ $2
ZEROPAGE_3 equ $3
ZEROPAGE_4 equ $4
ZEROPAGE_5 equ $5
ZEROPAGE_6 equ $6
ZEROPAGE_7 equ $7
ZEROPAGE_8 equ $8
ZEROPAGE_9 equ $9
ZEROPAGE_A equ $A
ZEROPAGE_B equ $B
ZEROPAGE_C equ $C
ZEROPAGE_D equ $D
ZEROPAGE_E equ $E
ZEROPAGE_F equ $F
row_0 BRK
ORA (ZEROPAGE_0,X)
TSB ZEROPAGE_0
ORA ZEROPAGE_0
ASL ZEROPAGE_0
PHP
ORA $00
ASL
TSB datablockabs
ORA datablockabs
ASL datablockabs
JMP row_1
row_1 BPL row_1_target
ORA (ZEROPAGE_1),Y
row_1_target ORA (ZEROPAGE_1)
TRB ZEROPAGE_1
ORA ZEROPAGE_1,X
ASL ZEROPAGE_1,X
CLC
ORA datablockabs,Y
INC
TRB datablockabs
ORA datablockabs,X
ASL datablockabs,X
JMP row_2
row_2 JSR farcode
AND (ZEROPAGE_2,X)
BIT ZEROPAGE_2
AND ZEROPAGE_2
ROL ZEROPAGE_2
PLP
AND #$22
ROL
BIT datablockabs
AND datablockabs
ROL datablockabs
JMP row_3
row_3 BMI row_3_target
AND (ZEROPAGE_3),Y
row_3_target AND (ZEROPAGE_3)
BIT ZEROPAGE_3,X
AND ZEROPAGE_3,X
ROL ZEROPAGE_3,X
SEC
AND datablockabs,Y
DEC
BIT datablockabs,X
AND datablockabs,X
ROL datablockabs,X
JMP row_4
row_4 RTI
EOR (ZEROPAGE_4,X)
EOR ZEROPAGE_4
LSR ZEROPAGE_4
PHA
EOR #$44
LSR
JMP farcode
EOR datablockabs
LSR datablockabs
JMP row_5
row_5 BVC row_5_target
EOR (ZEROPAGE_5),Y
row_5_target EOR ZEROPAGE_5,X
LSR ZEROPAGE_5,X
CLI
EOR datablockabs,Y
PHY
EOR datablockabs,X
LSR datablockabs,X
JMP row_6
row_6 RTS
ADC (ZEROPAGE_6,X)
STZ ZEROPAGE_6
ADC ZEROPAGE_6
ROR ZEROPAGE_6
PLA
ADC #$66
ROR
JMP farcode
ADC datablockabs
ROR datablockabs
JMP row_7
row_7 BVS row_7_target
ADC (ZEROPAGE_7),Y
row_7_target ADC (ZEROPAGE_7)
STZ ZEROPAGE_7,X
ADC ZEROPAGE_7,X
ROR ZEROPAGE_7,X
SEI
ADC datablockabs,Y
PLY
JMP (datablockabs,X)
ADC datablockabs,X
ROR datablockabs,X
JMP row_8
row_8 BRA row_8_target
STA (ZEROPAGE_8,X)
row_8_target STY ZEROPAGE_8
STA ZEROPAGE_8
STX ZEROPAGE_8
DEY
BIT #$88
TXA
STY datablockabs
STA datablockabs
STX datablockabs
JMP row_9
row_9 BCC row_9_target
STA (ZEROPAGE_9),Y
row_9_target STA (ZEROPAGE_9)
STY ZEROPAGE_9,X
STA ZEROPAGE_9,X
STX ZEROPAGE_9,Y
TYA
STA datablockabs,Y
TXS
STZ datablockabs
STA datablockabs,X
STZ datablockabs,X
JMP row_a
row_a LDY #$AA
LDA (ZEROPAGE_A,X)
LDX #$AA
LDY ZEROPAGE_A
LDA ZEROPAGE_A
LDX ZEROPAGE_A
TAY
LDA #$AA
TAX
LDY datablockabs
LDA datablockabs
LDX datablockabs
JMP row_b
row_b BCS row_b_target
LDA (ZEROPAGE_B),Y
row_b_target LDA (ZEROPAGE_B)
LDY ZEROPAGE_B,X
LDA ZEROPAGE_B,X
LDX ZEROPAGE_B,Y
CLV
LDA datablockabs,Y
TSX
LDY datablockabs,X
LDA datablockabs,X
LDX datablockabs,Y
JMP row_c
row_c CPY #$CC
CMP (ZEROPAGE_C,X)
CPY ZEROPAGE_C
CMP ZEROPAGE_C
DEC ZEROPAGE_C
INY
CMP #$CC
DEX
CPY datablockabs
CMP datablockabs
DEC datablockabs
JMP row_d
row_d BNE row_d_target
CMP (ZEROPAGE_D),Y
row_d_target CMP (ZEROPAGE_D)
CMP ZEROPAGE_D,X
DEC ZEROPAGE_D,X
CLD
CMP datablockabs,Y
PHX
CMP datablockabs,X
DEC datablockabs,X
JMP row_e
row_e CPX #$EE
SBC (ZEROPAGE_E,X)
CPX ZEROPAGE_E
SBC ZEROPAGE_E
INC ZEROPAGE_E
INX
SBC #$EE
NOP
CPX datablockabs
SBC datablockabs
INC datablockabs
JMP row_f
row_f BEQ row_f_target
SBC (ZEROPAGE_F),Y
row_f_target SBC (ZEROPAGE_F)
SBC ZEROPAGE_F,X
INC ZEROPAGE_F,X
SED
SBC datablockabs,Y
PLX
SBC datablockabs,X
INC datablockabs,X
JMP end
end RTS
datablockabs ADR $1234
farcode RTI
|
agatti/hopper-plugins
| 5,616
|
test/6502/r65c02opcodes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 65c02
org $1000
ZEROPAGE_0 equ $0
ZEROPAGE_1 equ $1
ZEROPAGE_2 equ $2
ZEROPAGE_3 equ $3
ZEROPAGE_4 equ $4
ZEROPAGE_5 equ $5
ZEROPAGE_6 equ $6
ZEROPAGE_7 equ $7
ZEROPAGE_8 equ $8
ZEROPAGE_9 equ $9
ZEROPAGE_A equ $A
ZEROPAGE_B equ $B
ZEROPAGE_C equ $C
ZEROPAGE_D equ $D
ZEROPAGE_E equ $E
ZEROPAGE_F equ $F
row_0 BRK
ORA (ZEROPAGE_0,X)
TSB ZEROPAGE_0
ORA ZEROPAGE_0
ASL ZEROPAGE_0
RMB0 ZEROPAGE_0
PHP
ORA $00
ASL
TSB datablockabs
ORA datablockabs
ASL datablockabs
BBR0 ZEROPAGE_0,row_1
JMP row_1
row_1 BPL row_1_target
ORA (ZEROPAGE_1),Y
row_1_target ORA (ZEROPAGE_1)
TRB ZEROPAGE_1
ORA ZEROPAGE_1,X
ASL ZEROPAGE_1,X
RMB1 ZEROPAGE_1
CLC
ORA datablockabs,Y
INC
TRB datablockabs
ORA datablockabs,X
ASL datablockabs,X
BBR1 ZEROPAGE_1,row_2
JMP row_2
row_2 JSR farcode
AND (ZEROPAGE_2,X)
BIT ZEROPAGE_2
AND ZEROPAGE_2
ROL ZEROPAGE_2
RMB2 ZEROPAGE_2
PLP
AND #$22
ROL
BIT datablockabs
AND datablockabs
ROL datablockabs
BBR2 ZEROPAGE_2,row_3
JMP row_3
row_3 BMI row_3_target
AND (ZEROPAGE_3),Y
row_3_target AND (ZEROPAGE_3)
BIT ZEROPAGE_3,X
AND ZEROPAGE_3,X
ROL ZEROPAGE_3,X
RMB3 ZEROPAGE_3
SEC
AND datablockabs,Y
DEC
BIT datablockabs,X
AND datablockabs,X
ROL datablockabs,X
BBR3 ZEROPAGE_3,row_4
JMP row_4
row_4 RTI
EOR (ZEROPAGE_4,X)
EOR ZEROPAGE_4
LSR ZEROPAGE_4
RMB4 ZEROPAGE_4
PHA
EOR #$44
LSR
JMP farcode
EOR datablockabs
LSR datablockabs
BBR4 ZEROPAGE_4,row_5
JMP row_5
row_5 BVC row_5_target
EOR (ZEROPAGE_5),Y
row_5_target EOR ZEROPAGE_5,X
LSR ZEROPAGE_5,X
RMB5 ZEROPAGE_5
CLI
EOR datablockabs,Y
PHY
EOR datablockabs,X
LSR datablockabs,X
BBR5 ZEROPAGE_5,row_6
JMP row_6
row_6 RTS
ADC (ZEROPAGE_6,X)
STZ ZEROPAGE_6
ADC ZEROPAGE_6
ROR ZEROPAGE_6
RMB6 ZEROPAGE_6
PLA
ADC #$66
ROR
JMP farcode
ADC datablockabs
ROR datablockabs
BBR6 ZEROPAGE_6,row_7
JMP row_7
row_7 BVS row_7_target
ADC (ZEROPAGE_7),Y
row_7_target ADC (ZEROPAGE_7)
STZ ZEROPAGE_7,X
ADC ZEROPAGE_7,X
ROR ZEROPAGE_7,X
RMB7 ZEROPAGE_7
SEI
ADC datablockabs,Y
PLY
JMP (farcode,X)
ADC datablockabs,X
ROR datablockabs,X
BBR7 ZEROPAGE_7,row_8
JMP row_8
row_8 BRA row_8_target
STA (ZEROPAGE_8,X)
row_8_target STY ZEROPAGE_8
STA ZEROPAGE_8
STX ZEROPAGE_8
SMB0 ZEROPAGE_8
DEY
BIT #$88
TXA
STY datablockabs
STA datablockabs
STX datablockabs
BBS0 ZEROPAGE_8,row_9
JMP row_9
row_9 BCC row_9_target
STA (ZEROPAGE_9),Y
row_9_target STA (ZEROPAGE_9)
STY ZEROPAGE_9,X
STA ZEROPAGE_9,X
STX ZEROPAGE_9,Y
SMB1 ZEROPAGE_9
TYA
STA datablockabs,Y
TXS
STZ datablockabs
STA datablockabs,X
STZ datablockabs,X
BBS1 ZEROPAGE_9,row_a
JMP row_a
row_a LDY #$AA
LDA (ZEROPAGE_A,X)
LDX #$AA
LDY ZEROPAGE_A
LDA ZEROPAGE_A
LDX ZEROPAGE_A
SMB2 ZEROPAGE_A
TAY
LDA #$AA
TAX
LDY datablockabs
LDA datablockabs
LDX datablockabs
BBS2 ZEROPAGE_A,row_b
JMP row_b
row_b BCS row_b_target
LDA (ZEROPAGE_B),Y
row_b_target LDA (ZEROPAGE_B)
LDY ZEROPAGE_B,X
LDA ZEROPAGE_B,X
LDX ZEROPAGE_B,Y
SMB3 ZEROPAGE_B
CLV
LDA datablockabs,Y
TSX
LDY datablockabs,X
LDA datablockabs,X
LDX datablockabs,Y
BBS3 ZEROPAGE_B,row_c
JMP row_c
row_c CPY #$CC
CMP (ZEROPAGE_C,X)
CPY ZEROPAGE_C
CMP ZEROPAGE_C
DEC ZEROPAGE_C
SMB4 ZEROPAGE_C
INY
CMP #$CC
DEX
CPY datablockabs
CMP datablockabs
DEC datablockabs
BBS4 ZEROPAGE_C,row_d
JMP row_d
row_d BNE row_d_target
CMP (ZEROPAGE_D),Y
row_d_target CMP (ZEROPAGE_D)
CMP ZEROPAGE_D,X
DEC ZEROPAGE_D,X
SMB5 ZEROPAGE_D
CLD
CMP datablockabs,Y
PHX
CMP datablockabs,X
DEC datablockabs,X
BBS5 ZEROPAGE_D,row_e
JMP row_e
row_e CPX #$EE
SBC (ZEROPAGE_E,X)
CPX ZEROPAGE_E
SBC ZEROPAGE_E
INC ZEROPAGE_E
SMB6 ZEROPAGE_E
INX
SBC #$EE
NOP
CPX datablockabs
SBC datablockabs
INC datablockabs
BBS6 ZEROPAGE_E,row_f
JMP row_f
row_f BEQ row_f_target
SBC (ZEROPAGE_F),Y
row_f_target SBC (ZEROPAGE_F)
SBC ZEROPAGE_F,X
INC ZEROPAGE_F,X
SMB7 ZEROPAGE_F
SED
SBC datablockabs,Y
PLX
SBC datablockabs,X
INC datablockabs,X
BBS7 ZEROPAGE_F,end
JMP end
end RTS
datablockabs ADR $1234
farcode RTI
|
agatti/hopper-plugins
| 5,940
|
test/6502/m37450opcodes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps740
org $1000
ZEROPAGE_0 equ $0
ZEROPAGE_1 equ $1
ZEROPAGE_2 equ $2
ZEROPAGE_3 equ $3
ZEROPAGE_4 equ $4
ZEROPAGE_5 equ $5
ZEROPAGE_6 equ $6
ZEROPAGE_7 equ $7
ZEROPAGE_8 equ $8
ZEROPAGE_9 equ $9
ZEROPAGE_A equ $A
ZEROPAGE_B equ $B
ZEROPAGE_C equ $C
ZEROPAGE_D equ $D
ZEROPAGE_E equ $E
ZEROPAGE_F equ $F
; $0x
row_0 BRK
ORA (ZEROPAGE_0,X)
JSR (ZEROPAGE_0)
BBS 0,A,row_0
;
ORA ZEROPAGE_0
ASL ZEROPAGE_0
BBS 0,ZEROPAGE_0,row_0
PHP
ORA #$0
ASL
SEB 0,A
;
ORA datablockabs
ASL datablockabs
SEB 0,ZEROPAGE_0
; $1x
row_1 BPL row_1_target
ORA (ZEROPAGE_1),Y
row_1_target CLT
BBC 0,A,row_1
;
ORA ZEROPAGE_1,X
ASL ZEROPAGE_1,X
BBC 0,ZEROPAGE_1,row_1
CLC
ORA datablockabs,Y
DEC
CLB 0,A
;
ORA datablockabs,X
ASL datablockabs,X
CLB 0,ZEROPAGE_1
; $2x
row_2 JSR farcode
AND (ZEROPAGE_2,X)
JSR \$E0
BBS 1,A,row_2
BIT ZEROPAGE_2
AND ZEROPAGE_2
ROL ZEROPAGE_2
BBS 1,ZEROPAGE_2,row_2
PLP
AND #$22
ROL
SEB 1,A
BIT datablockabs
AND datablockabs
ROL datablockabs
SEB 1,ZEROPAGE_2
; $3x
row_3 BMI row_3_target
AND (ZEROPAGE_3),Y
row_3_target SET
BBC 1,A,row_3
;
AND ZEROPAGE_3,X
ROL ZEROPAGE_3,X
BBC 1,ZEROPAGE_3,row_3
SEC
AND datablockabs,Y
INC
CLB 1,A
LDM #$33,ZEROPAGE_3
AND datablockabs,X
ROL datablockabs,X
CLB 1,ZEROPAGE_3
; $4x
row_4 RTI
EOR (ZEROPAGE_4,X)
STP
BBS 2,A,row_4
COM ZEROPAGE_4
EOR ZEROPAGE_4
LSR ZEROPAGE_4
BBS 2,ZEROPAGE_4,row_4
PHA
EOR #$44
LSR
SEB 2,A
JMP farcode
EOR datablockabs
LSR datablockabs
SEB 2,ZEROPAGE_4
; $5x
row_5 BVC row_5_target
EOR (ZEROPAGE_5),Y
;
row_5_target BBC 2,A,row_5
;
EOR ZEROPAGE_5,X
LSR ZEROPAGE_5,X
BBC 2,ZEROPAGE_5,row_5
CLI
EOR datablockabs,Y
;
CLB 2,A
;
EOR datablockabs,X
LSR datablockabs,X
CLB 2,ZEROPAGE_5
; $6x
row_6 RTS
ADC (ZEROPAGE_6,X)
MUL ZEROPAGE_6,X
BBS 3,A,row_6
TST ZEROPAGE_6
ADC ZEROPAGE_6
ROR ZEROPAGE_6
BBS 3,ZEROPAGE_6,row_6
PLA
ADC #$66
ROR
SEB 3,A
JMP (datablockabs)
ADC datablockabs
ROR datablockabs
SEB 3,ZEROPAGE_6
; $7x
row_7 BVS row_7_target
ADC (ZEROPAGE_7),Y
;
row_7_target BBC 3,A,row_7
;
ADC ZEROPAGE_7,X
ROR ZEROPAGE_7,X
BBC 3,ZEROPAGE_7,row_7
SEI
ADC datablockabs,Y
;
CLB 3,A
;
ADC datablockabs,X
ROR datablockabs,X
CLB 3,ZEROPAGE_7
; $8x
row_8 BRA row_8_target
STA (ZEROPAGE_8,X)
row_8_target RRF ZEROPAGE_8
BBS 4,A,row_8
STY ZEROPAGE_8
STA ZEROPAGE_8
STX ZEROPAGE_8
BBS 4,ZEROPAGE_8,row_8
DEY
;
TXA
SEB 4,A
STY datablockabs
STA datablockabs
STX datablockabs
SEB 4,ZEROPAGE_8
; $9x
row_9 BCC row_9_target
STA (ZEROPAGE_9),Y
;
row_9_target BBC 4,A,row_9
STY ZEROPAGE_9,X
STA ZEROPAGE_9,X
STX ZEROPAGE_9,Y
BBC 4,ZEROPAGE_9,row_9
TYA
STA datablockabs,Y
TXS
CLB 4,A
;
STA datablockabs,X
;
CLB 4,ZEROPAGE_9
; $Ax
row_a LDY #$AA
LDA (ZEROPAGE_A,X)
LDX #$AA
BBS 5,A,row_a
LDY ZEROPAGE_A
LDA ZEROPAGE_A
LDX ZEROPAGE_A
BBS 5,ZEROPAGE_A,row_a
TAY
LDA #$AA
TAX
SEB 5,A
LDY datablockabs
LDA datablockabs
LDX datablockabs
SEB 5,ZEROPAGE_A
; $Bx
row_b BCS row_b_target
LDA (ZEROPAGE_B),Y
row_b_target JMP (ZEROPAGE_B)
BBC 5,A,row_b
LDY ZEROPAGE_B,X
LDA ZEROPAGE_B,X
LDX ZEROPAGE_B,Y
BBC 5,ZEROPAGE_B,row_b
CLV
LDA datablockabs,Y
TSX
CLB 5,A
LDY datablockabs,X
LDA datablockabs,X
LDX datablockabs,Y
CLB 5,ZEROPAGE_B
; $Cx
row_c CPY #$CC
CMP (ZEROPAGE_C,X)
WIT
BBS 6,A,row_c
CPY ZEROPAGE_C
CMP ZEROPAGE_C
DEC ZEROPAGE_C
BBS 6,ZEROPAGE_C,row_c
INY
CMP #$CC
DEX
SEB 6,A
CPY datablockabs
CMP datablockabs
DEC datablockabs
SEB 6,ZEROPAGE_C
; $Dx
row_d BNE row_d_target
CMP (ZEROPAGE_D),Y
;
row_d_target BBC 6,A,row_d
;
CMP ZEROPAGE_D,X
DEC ZEROPAGE_D,X
BBC 6,ZEROPAGE_D,row_d
CLD
CMP datablockabs,Y
;
CLB 6,A
;
CMP datablockabs,X
DEC datablockabs,X
CLB 7,ZEROPAGE_D
; $Ex
row_e CPX #$EE
SBC (ZEROPAGE_E,X)
DIV ZEROPAGE_E,X
BBS 7,A,row_e
CPX ZEROPAGE_E
SBC ZEROPAGE_E
INC ZEROPAGE_E
BBS 7,ZEROPAGE_E,row_e
INX
SBC #$EE
NOP
SEB 7,A
CPX datablockabs
SBC datablockabs
INC datablockabs
SEB 7,ZEROPAGE_E
; $Fx
row_f BEQ row_f_target
SBC (ZEROPAGE_F),Y
;
row_f_target BBC 7,A,row_f
;
SBC ZEROPAGE_F,X
INC ZEROPAGE_F,X
BBC 7,ZEROPAGE_F,row_f
SED
SBC datablockabs,Y
;
CLB 7,A
;
SBC datablockabs,X
INC datablockabs,X
CLB 7,ZEROPAGE_7
end RTS
datablockabs ADR $1234
farcode RTI
|
agatti/hopper-plugins
| 5,910
|
test/6502/m740opcodes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu melps740
org $1000
ZEROPAGE_0 equ $0
ZEROPAGE_1 equ $1
ZEROPAGE_2 equ $2
ZEROPAGE_3 equ $3
ZEROPAGE_4 equ $4
ZEROPAGE_5 equ $5
ZEROPAGE_6 equ $6
ZEROPAGE_7 equ $7
ZEROPAGE_8 equ $8
ZEROPAGE_9 equ $9
ZEROPAGE_A equ $A
ZEROPAGE_B equ $B
ZEROPAGE_C equ $C
ZEROPAGE_D equ $D
ZEROPAGE_E equ $E
ZEROPAGE_F equ $F
; $0x
row_0 BRK
ORA (ZEROPAGE_0,X)
JSR (ZEROPAGE_0)
BBS 0,A,row_0
;
ORA ZEROPAGE_0
ASL ZEROPAGE_0
BBS 0,ZEROPAGE_0,row_0
PHP
ORA #$0
ASL
SEB 0,A
;
ORA datablockabs
ASL datablockabs
SEB 0,ZEROPAGE_0
; $1x
row_1 BPL row_1_target
ORA (ZEROPAGE_1),Y
row_1_target CLT
BBC 0,A,row_1
;
ORA ZEROPAGE_1,X
ASL ZEROPAGE_1,X
BBC 0,ZEROPAGE_1,row_1
CLC
ORA datablockabs,Y
DEC
CLB 0,A
;
ORA datablockabs,X
ASL datablockabs,X
CLB 0,ZEROPAGE_1
; $2x
row_2 JSR farcode
AND (ZEROPAGE_2,X)
JSR \$E0
BBS 1,A,row_2
BIT ZEROPAGE_2
AND ZEROPAGE_2
ROL ZEROPAGE_2
BBS 1,ZEROPAGE_2,row_2
PLP
AND #$22
ROL
SEB 1,A
BIT datablockabs
AND datablockabs
ROL datablockabs
SEB 1,ZEROPAGE_2
; $3x
row_3 BMI row_3_target
AND (ZEROPAGE_3),Y
row_3_target SET
BBC 1,A,row_3
;
AND ZEROPAGE_3,X
ROL ZEROPAGE_3,X
BBC 1,ZEROPAGE_3,row_3
SEC
AND datablockabs,Y
INC
CLB 1,A
LDM #$33,ZEROPAGE_3
AND datablockabs,X
ROL datablockabs,X
CLB 1,ZEROPAGE_3
; $4x
row_4 RTI
EOR (ZEROPAGE_4,X)
STP
BBS 2,A,row_4
COM ZEROPAGE_4
EOR ZEROPAGE_4
LSR ZEROPAGE_4
BBS 2,ZEROPAGE_4,row_4
PHA
EOR #$44
LSR
SEB 2,A
JMP farcode
EOR datablockabs
LSR datablockabs
SEB 2,ZEROPAGE_4
; $5x
row_5 BVC row_5_target
EOR (ZEROPAGE_5),Y
;
row_5_target BBC 2,A,row_5
;
EOR ZEROPAGE_5,X
LSR ZEROPAGE_5,X
BBC 2,ZEROPAGE_5,row_5
CLI
EOR datablockabs,Y
;
CLB 2,A
;
EOR datablockabs,X
LSR datablockabs,X
CLB 2,ZEROPAGE_5
; $6x
row_6 RTS
ADC (ZEROPAGE_6,X)
;
BBS 3,A,row_6
TST ZEROPAGE_6
ADC ZEROPAGE_6
ROR ZEROPAGE_6
BBS 3,ZEROPAGE_6,row_6
PLA
ADC #$66
ROR
SEB 3,A
JMP (datablockabs)
ADC datablockabs
ROR datablockabs
SEB 3,ZEROPAGE_6
; $7x
row_7 BVS row_7_target
ADC (ZEROPAGE_7),Y
;
row_7_target BBC 3,A,row_7
;
ADC ZEROPAGE_7,X
ROR ZEROPAGE_7,X
BBC 3,ZEROPAGE_7,row_7
SEI
ADC datablockabs,Y
;
CLB 3,A
;
ADC datablockabs,X
ROR datablockabs,X
CLB 3,ZEROPAGE_7
; $8x
row_8 BRA row_8_target
STA (ZEROPAGE_8,X)
row_8_target RRF ZEROPAGE_8
BBS 4,A,row_8
STY ZEROPAGE_8
STA ZEROPAGE_8
STX ZEROPAGE_8
BBS 4,ZEROPAGE_8,row_8
DEY
;
TXA
SEB 4,A
STY datablockabs
STA datablockabs
STX datablockabs
SEB 4,ZEROPAGE_8
; $9x
row_9 BCC row_9_target
STA (ZEROPAGE_9),Y
;
row_9_target BBC 4,A,row_9
STY ZEROPAGE_9,X
STA ZEROPAGE_9,X
STX ZEROPAGE_9,Y
BBC 4,ZEROPAGE_9,row_9
TYA
STA datablockabs,Y
TXS
CLB 4,A
;
STA datablockabs,X
;
CLB 4,ZEROPAGE_9
; $Ax
row_a LDY #$AA
LDA (ZEROPAGE_A,X)
LDX #$AA
BBS 5,A,row_a
LDY ZEROPAGE_A
LDA ZEROPAGE_A
LDX ZEROPAGE_A
BBS 5,ZEROPAGE_A,row_a
TAY
LDA #$AA
TAX
SEB 5,A
LDY datablockabs
LDA datablockabs
LDX datablockabs
SEB 5,ZEROPAGE_A
; $Bx
row_b BCS row_b_target
LDA (ZEROPAGE_B),Y
row_b_target JMP (ZEROPAGE_B)
BBC 5,A,row_b
LDY ZEROPAGE_B,X
LDA ZEROPAGE_B,X
LDX ZEROPAGE_B,Y
BBC 5,ZEROPAGE_B,row_b
CLV
LDA datablockabs,Y
TSX
CLB 5,A
LDY datablockabs,X
LDA datablockabs,X
LDX datablockabs,Y
CLB 5,ZEROPAGE_B
; $Cx
row_c CPY #$CC
CMP (ZEROPAGE_C,X)
WIT
BBS 6,A,row_c
CPY ZEROPAGE_C
CMP ZEROPAGE_C
DEC ZEROPAGE_C
BBS 6,ZEROPAGE_C,row_c
INY
CMP #$CC
DEX
SEB 6,A
CPY datablockabs
CMP datablockabs
DEC datablockabs
SEB 6,ZEROPAGE_C
; $Dx
row_d BNE row_d_target
CMP (ZEROPAGE_D),Y
;
row_d_target BBC 6,A,row_d
;
CMP ZEROPAGE_D,X
DEC ZEROPAGE_D,X
BBC 6,ZEROPAGE_D,row_d
CLD
CMP datablockabs,Y
;
CLB 6,A
;
CMP datablockabs,X
DEC datablockabs,X
CLB 7,ZEROPAGE_D
; $Ex
row_e CPX #$EE
SBC (ZEROPAGE_E,X)
;
BBS 7,A,row_e
CPX ZEROPAGE_E
SBC ZEROPAGE_E
INC ZEROPAGE_E
BBS 7,ZEROPAGE_E,row_e
INX
SBC #$EE
NOP
SEB 7,A
CPX datablockabs
SBC datablockabs
INC datablockabs
SEB 7,ZEROPAGE_E
; $Fx
row_f BEQ row_f_target
SBC (ZEROPAGE_F),Y
;
row_f_target BBC 7,A,row_f
;
SBC ZEROPAGE_F,X
INC ZEROPAGE_F,X
BBC 7,ZEROPAGE_F,row_f
SED
SBC datablockabs,Y
;
CLB 7,A
;
SBC datablockabs,X
INC datablockabs,X
CLB 7,ZEROPAGE_7
end RTS
datablockabs ADR $1234
farcode RTI
|
agatti/hopper-plugins
| 5,200
|
test/6502/r6500opcodes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 65c02
org $1000
ZEROPAGE_0 equ $0
ZEROPAGE_1 equ $1
ZEROPAGE_2 equ $2
ZEROPAGE_3 equ $3
ZEROPAGE_4 equ $4
ZEROPAGE_5 equ $5
ZEROPAGE_6 equ $6
ZEROPAGE_7 equ $7
ZEROPAGE_8 equ $8
ZEROPAGE_9 equ $9
ZEROPAGE_A equ $A
ZEROPAGE_B equ $B
ZEROPAGE_C equ $C
ZEROPAGE_D equ $D
ZEROPAGE_E equ $E
ZEROPAGE_F equ $F
row_0 BRK
ORA (ZEROPAGE_0,X)
ORA ZEROPAGE_0
ASL ZEROPAGE_0
RMB0 ZEROPAGE_0
PHP
ORA $00
ASL
ORA datablockabs
ASL datablockabs
BBR0 ZEROPAGE_0,row_1
JMP row_1
row_1 BPL row_1_target
ORA (ZEROPAGE_1),Y
row_1_target ORA ZEROPAGE_1,X
ASL ZEROPAGE_1,X
RMB1 ZEROPAGE_1
CLC
ORA datablockabs,Y
ORA datablockabs,X
ASL datablockabs,X
BBR1 ZEROPAGE_1,row_2
JMP row_2
row_2 JSR farcode
AND (ZEROPAGE_2,X)
BIT ZEROPAGE_2
AND ZEROPAGE_2
ROL ZEROPAGE_2
RMB2 ZEROPAGE_2
PLP
AND #$22
ROL
BIT datablockabs
AND datablockabs
ROL datablockabs
BBR2 ZEROPAGE_2,row_3
JMP row_3
row_3 BMI row_3_target
AND (ZEROPAGE_3),Y
row_3_target AND ZEROPAGE_3,X
ROL ZEROPAGE_3,X
RMB3 ZEROPAGE_3
SEC
AND datablockabs,Y
AND datablockabs,X
ROL datablockabs,X
BBR3 ZEROPAGE_3,row_4
JMP row_4
row_4 RTI
EOR (ZEROPAGE_4,X)
EOR ZEROPAGE_4
LSR ZEROPAGE_4
RMB4 ZEROPAGE_4
PHA
EOR #$44
LSR
JMP farcode
EOR datablockabs
LSR datablockabs
BBR4 ZEROPAGE_4,row_5
JMP row_5
row_5 BVC row_5_target
EOR (ZEROPAGE_5),Y
row_5_target EOR ZEROPAGE_5,X
LSR ZEROPAGE_5,X
RMB5 ZEROPAGE_5
CLI
EOR datablockabs,Y
EOR datablockabs,X
LSR datablockabs,X
BBR5 ZEROPAGE_5,row_6
JMP row_6
row_6 RTS
ADC (ZEROPAGE_6,X)
ADC ZEROPAGE_6
ROR ZEROPAGE_6
RMB6 ZEROPAGE_6
PLA
ADC #$66
ROR
JMP farcode
ADC datablockabs
ROR datablockabs
BBR6 ZEROPAGE_6,row_7
JMP row_7
row_7 BVS row_7_target
ADC (ZEROPAGE_7),Y
row_7_target ADC ZEROPAGE_7,X
ROR ZEROPAGE_7,X
RMB7 ZEROPAGE_7
SEI
ADC datablockabs,Y
ADC datablockabs,X
ROR datablockabs,X
BBR7 ZEROPAGE_7,row_8
JMP row_8
row_8 STA (ZEROPAGE_8,X)
STY ZEROPAGE_8
STA ZEROPAGE_8
STX ZEROPAGE_8
SMB0 ZEROPAGE_8
DEY
TXA
STY datablockabs
STA datablockabs
STX datablockabs
BBS0 ZEROPAGE_8,row_9
JMP row_9
row_9 BCC row_9_target
STA (ZEROPAGE_9),Y
row_9_target STY ZEROPAGE_9,X
STA ZEROPAGE_9,X
STX ZEROPAGE_9,Y
SMB1 ZEROPAGE_9
TYA
STA datablockabs,Y
TXS
STA datablockabs,X
BBS1 ZEROPAGE_9,row_a
JMP row_a
row_a LDY #$AA
LDA (ZEROPAGE_A,X)
LDX #$AA
LDY ZEROPAGE_A
LDA ZEROPAGE_A
LDX ZEROPAGE_A
SMB2 ZEROPAGE_A
TAY
LDA #$AA
TAX
LDY datablockabs
LDA datablockabs
LDX datablockabs
BBS2 ZEROPAGE_A,row_b
JMP row_b
row_b BCS row_b_target
LDA (ZEROPAGE_B),Y
row_b_target LDY ZEROPAGE_B,X
LDA ZEROPAGE_B,X
LDX ZEROPAGE_B,Y
SMB3 ZEROPAGE_B
CLV
LDA datablockabs,Y
TSX
LDY datablockabs,X
LDA datablockabs,X
LDX datablockabs,Y
BBS3 ZEROPAGE_B,row_c
JMP row_c
row_c CPY #$CC
CMP (ZEROPAGE_C,X)
CPY ZEROPAGE_C
CMP ZEROPAGE_C
DEC ZEROPAGE_C
SMB4 ZEROPAGE_C
INY
CMP #$CC
DEX
CPY datablockabs
CMP datablockabs
DEC datablockabs
BBS4 ZEROPAGE_C,row_d
JMP row_d
row_d BNE row_d_target
CMP (ZEROPAGE_D),Y
row_d_target CMP ZEROPAGE_D,X
DEC ZEROPAGE_D,X
SMB5 ZEROPAGE_D
CLD
CMP datablockabs,Y
CMP datablockabs,X
DEC datablockabs,X
BBS5 ZEROPAGE_D,row_e
JMP row_e
row_e CPX #$EE
SBC (ZEROPAGE_E,X)
CPX ZEROPAGE_E
SBC ZEROPAGE_E
INC ZEROPAGE_E
SMB6 ZEROPAGE_E
INX
SBC #$EE
NOP
CPX datablockabs
SBC datablockabs
INC datablockabs
BBS6 ZEROPAGE_E,row_f
JMP row_f
row_f BEQ row_f_target
SBC (ZEROPAGE_F),Y
row_f_target SBC ZEROPAGE_F,X
INC ZEROPAGE_F,X
SMB7 ZEROPAGE_F
SED
SBC datablockabs,Y
SBC datablockabs,X
INC datablockabs,X
BBS7 ZEROPAGE_F,end
JMP end
end RTS
datablockabs ADR $1234
farcode RTI
|
agatti/hopper-plugins
| 5,636
|
test/6502/w65c02sopcodes.s
|
; Copyright (c) 2014-2021, Alessandro Gatti - frob.it
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
cpu 65c02
org $1000
ZEROPAGE_0 equ $0
ZEROPAGE_1 equ $1
ZEROPAGE_2 equ $2
ZEROPAGE_3 equ $3
ZEROPAGE_4 equ $4
ZEROPAGE_5 equ $5
ZEROPAGE_6 equ $6
ZEROPAGE_7 equ $7
ZEROPAGE_8 equ $8
ZEROPAGE_9 equ $9
ZEROPAGE_A equ $A
ZEROPAGE_B equ $B
ZEROPAGE_C equ $C
ZEROPAGE_D equ $D
ZEROPAGE_E equ $E
ZEROPAGE_F equ $F
row_0 BRK
ORA (ZEROPAGE_0,X)
TSB ZEROPAGE_0
ORA ZEROPAGE_0
ASL ZEROPAGE_0
RMB0 ZEROPAGE_0
PHP
ORA $00
ASL
TSB datablockabs
ORA datablockabs
ASL datablockabs
BBR0 ZEROPAGE_0,row_1
JMP row_1
row_1 BPL row_1_target
ORA (ZEROPAGE_1),Y
row_1_target ORA (ZEROPAGE_1)
TRB ZEROPAGE_1
ORA ZEROPAGE_1,X
ASL ZEROPAGE_1,X
RMB1 ZEROPAGE_1
CLC
ORA datablockabs,Y
INC
TRB datablockabs
ORA datablockabs,X
ASL datablockabs,X
BBR1 ZEROPAGE_1,row_2
JMP row_2
row_2 JSR farcode
AND (ZEROPAGE_2,X)
BIT ZEROPAGE_2
AND ZEROPAGE_2
ROL ZEROPAGE_2
RMB2 ZEROPAGE_2
PLP
AND #$22
ROL
BIT datablockabs
AND datablockabs
ROL datablockabs
BBR2 ZEROPAGE_2,row_3
JMP row_3
row_3 BMI row_3_target
AND (ZEROPAGE_3),Y
row_3_target AND (ZEROPAGE_3)
BIT ZEROPAGE_3,X
AND ZEROPAGE_3,X
ROL ZEROPAGE_3,X
RMB3 ZEROPAGE_3
SEC
AND datablockabs,Y
DEC
BIT datablockabs,X
AND datablockabs,X
ROL datablockabs,X
BBR3 ZEROPAGE_3,row_4
JMP row_4
row_4 RTI
EOR (ZEROPAGE_4,X)
EOR ZEROPAGE_4
LSR ZEROPAGE_4
RMB4 ZEROPAGE_4
PHA
EOR #$44
LSR
JMP farcode
EOR datablockabs
LSR datablockabs
BBR4 ZEROPAGE_4,row_5
JMP row_5
row_5 BVC row_5_target
EOR (ZEROPAGE_5),Y
row_5_target EOR ZEROPAGE_5,X
LSR ZEROPAGE_5,X
RMB5 ZEROPAGE_5
CLI
EOR datablockabs,Y
PHY
EOR datablockabs,X
LSR datablockabs,X
BBR5 ZEROPAGE_5,row_6
JMP row_6
row_6 RTS
ADC (ZEROPAGE_6,X)
STZ ZEROPAGE_6
ADC ZEROPAGE_6
ROR ZEROPAGE_6
RMB6 ZEROPAGE_6
PLA
ADC #$66
ROR
JMP farcode
ADC datablockabs
ROR datablockabs
BBR6 ZEROPAGE_6,row_7
JMP row_7
row_7 BVS row_7_target
ADC (ZEROPAGE_7),Y
row_7_target ADC (ZEROPAGE_7)
STZ ZEROPAGE_7,X
ADC ZEROPAGE_7,X
ROR ZEROPAGE_7,X
RMB7 ZEROPAGE_7
SEI
ADC datablockabs,Y
PLY
JMP (farcode,X)
ADC datablockabs,X
ROR datablockabs,X
BBR7 ZEROPAGE_7,row_8
JMP row_8
row_8 BRA row_8_target
STA (ZEROPAGE_8,X)
row_8_target STY ZEROPAGE_8
STA ZEROPAGE_8
STX ZEROPAGE_8
SMB0 ZEROPAGE_8
DEY
BIT #$88
TXA
STY datablockabs
STA datablockabs
STX datablockabs
BBS0 ZEROPAGE_8,row_9
JMP row_9
row_9 BCC row_9_target
STA (ZEROPAGE_9),Y
row_9_target STA (ZEROPAGE_9)
STY ZEROPAGE_9,X
STA ZEROPAGE_9,X
STX ZEROPAGE_9,Y
SMB1 ZEROPAGE_9
TYA
STA datablockabs,Y
TXS
STZ datablockabs
STA datablockabs,X
STZ datablockabs,X
BBS1 ZEROPAGE_9,row_a
JMP row_a
row_a LDY #$AA
LDA (ZEROPAGE_A,X)
LDX #$AA
LDY ZEROPAGE_A
LDA ZEROPAGE_A
LDX ZEROPAGE_A
SMB2 ZEROPAGE_A
TAY
LDA #$AA
TAX
LDY datablockabs
LDA datablockabs
LDX datablockabs
BBS2 ZEROPAGE_A,row_b
JMP row_b
row_b BCS row_b_target
LDA (ZEROPAGE_B),Y
row_b_target LDA (ZEROPAGE_B)
LDY ZEROPAGE_B,X
LDA ZEROPAGE_B,X
LDX ZEROPAGE_B,Y
SMB3 ZEROPAGE_B
CLV
LDA datablockabs,Y
TSX
LDY datablockabs,X
LDA datablockabs,X
LDX datablockabs,Y
BBS3 ZEROPAGE_B,row_c
JMP row_c
row_c CPY #$CC
CMP (ZEROPAGE_C,X)
CPY ZEROPAGE_C
CMP ZEROPAGE_C
DEC ZEROPAGE_C
SMB4 ZEROPAGE_C
INY
CMP #$CC
DEX
BYT $DB
CPY datablockabs
CMP datablockabs
DEC datablockabs
BBS4 ZEROPAGE_C,row_d
JMP row_d
row_d BNE row_d_target
CMP (ZEROPAGE_D),Y
row_d_target CMP (ZEROPAGE_D)
CMP ZEROPAGE_D,X
DEC ZEROPAGE_D,X
SMB5 ZEROPAGE_D
CLD
CMP datablockabs,Y
PHX
BYT $CB
CMP datablockabs,X
DEC datablockabs,X
BBS5 ZEROPAGE_D,row_e
JMP row_e
row_e CPX #$EE
SBC (ZEROPAGE_E,X)
CPX ZEROPAGE_E
SBC ZEROPAGE_E
INC ZEROPAGE_E
SMB6 ZEROPAGE_E
INX
SBC #$EE
NOP
CPX datablockabs
SBC datablockabs
INC datablockabs
BBS6 ZEROPAGE_E,row_f
JMP row_f
row_f BEQ row_f_target
SBC (ZEROPAGE_F),Y
row_f_target SBC (ZEROPAGE_F)
SBC ZEROPAGE_F,X
INC ZEROPAGE_F,X
SMB7 ZEROPAGE_F
SED
SBC datablockabs,Y
PLX
SBC datablockabs,X
INC datablockabs,X
BBS7 ZEROPAGE_F,end
JMP end
end RTS
datablockabs ADR $1234
farcode RTI
|
agavrel/Nailing-the-Coding-Interview
| 35,974
|
parsing/string_to_lowercase/benchmark.s
|
.file "benchmark.cpp"
.text
.align 2
.p2align 4,,15
.type _ZNKUlOT_DpOT0_E_clIRFNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSB_EJSC_EEEDaS0_S3_.isra.26, @function
_ZNKUlOT_DpOT0_E_clIRFNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSB_EJSC_EEEDaS0_S3_.isra.26:
.LFB4308:
.cfi_startproc
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
movq %rsi, %r13
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %r12
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rsp, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rbx, %rdi
movq %rax, %rbp
movq %r13, %rsi
call *%r12
movq (%rsp), %rdi
addq $16, %rbx
cmpq %rbx, %rdi
je .L2
call _ZdlPv@PLT
.L2:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movabsq $3022314549036572937, %rdx
subq %rbp, %rax
movq %rax, %rcx
imulq %rdx
sarq $63, %rcx
sarq $14, %rdx
movq %rdx, %rax
subq %rcx, %rax
movq 40(%rsp), %rsi
xorq %fs:40, %rsi
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4308:
.size _ZNKUlOT_DpOT0_E_clIRFNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSB_EJSC_EEEDaS0_S3_.isra.26, .-_ZNKUlOT_DpOT0_E_clIRFNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSB_EJSC_EEEDaS0_S3_.isra.26
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "basic_string::_M_create"
.text
.align 2
.p2align 4,,15
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.isra.38.constprop.51, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.isra.38.constprop.51:
.LFB4333:
.cfi_startproc
movq (%rdi), %rdi
testq %rdi, %rdi
js .L12
addq $1, %rdi
jmp _Znwm@PLT
.L12:
leaq .LC0(%rip), %rdi
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZSt20__throw_length_errorPKc@PLT
.cfi_endproc
.LFE4333:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.isra.38.constprop.51, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.isra.38.constprop.51
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "basic_string::_M_construct null not valid"
.text
.align 2
.p2align 4,,15
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag.isra.39, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag.isra.39:
.LFB4321:
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %rbp
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
testq %rsi, %rsi
jne .L14
testq %rdx, %rdx
jne .L30
.L14:
movq %rdx, %rbx
subq %rsi, %rbx
cmpq $15, %rbx
movq %rbx, 16(%rsp)
ja .L31
movq 0(%rbp), %rdx
cmpq $1, %rbx
movq %rdx, %rax
je .L32
testq %rbx, %rbx
jne .L16
.L18:
movq 16(%rsp), %rax
movq %rax, 8(%rbp)
movb $0, (%rdx,%rax)
movq 24(%rsp), %rax
xorq %fs:40, %rax
jne .L33
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.p2align 4,,10
.p2align 3
.L32:
.cfi_restore_state
movzbl (%rsi), %eax
movb %al, (%rdx)
movq 0(%rbp), %rdx
jmp .L18
.p2align 4,,10
.p2align 3
.L31:
leaq 16(%rsp), %rdi
movq %rsi, 8(%rsp)
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.isra.38.constprop.51
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 0(%rbp)
movq %rdx, 16(%rbp)
.L16:
movq %rbx, %rdx
movq %rax, %rdi
call memcpy@PLT
movq 0(%rbp), %rdx
jmp .L18
.L30:
leaq .LC1(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4321:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag.isra.39, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag.isra.39
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag.isra.41,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag.isra.39
.p2align 4,,15
.globl _Z16str_to_lowercaseRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _Z16str_to_lowercaseRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_Z16str_to_lowercaseRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3443:
.cfi_startproc
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $32, %ecx
movq %rdi, %rbx
movq %rsi, %r8
subq $272, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
rep stosq
movabsq $2314885530818453536, %rax
movq 8(%rsi), %rdi
movq %rax, 65(%rsp)
movq %rax, 73(%rsp)
movq %rax, 81(%rsp)
movl $8224, %eax
movw %ax, 89(%rsp)
movq (%rsi), %rax
addq %rax, %rdi
cmpq %rax, %rdi
je .L35
.p2align 4,,10
.p2align 3
.L36:
movsbq (%rax), %rcx
addq $1, %rax
movq %rcx, %rdx
orb (%rsp,%rcx), %dl
movb %dl, -1(%rax)
cmpq %rax, %rdi
jne .L36
.L35:
leaq 16(%rbx), %rax
movq %rbx, %rdi
movq %rax, (%rbx)
movq (%r8), %rsi
movq 8(%r8), %rdx
addq %rsi, %rdx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag.isra.41
movq 264(%rsp), %rsi
xorq %fs:40, %rsi
movq %rbx, %rax
jne .L40
addq $272, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3443:
.size _Z16str_to_lowercaseRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_Z16str_to_lowercaseRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4,,15
.globl _Z17str_to_lowercase2RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _Z17str_to_lowercase2RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_Z17str_to_lowercase2RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3444:
.cfi_startproc
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
movq %rsi, %r13
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %r12
subq $8, %rsp
.cfi_def_cfa_offset 48
movq (%rsi), %rbx
movq 8(%rsi), %rbp
addq %rbx, %rbp
cmpq %rbx, %rbp
je .L42
.p2align 4,,10
.p2align 3
.L43:
movsbl (%rbx), %edi
addq $1, %rbx
call toupper@PLT
movb %al, -1(%rbx)
cmpq %rbx, %rbp
jne .L43
.L42:
leaq 16(%r12), %rax
movq %r12, %rdi
movq %rax, (%r12)
movq 0(%r13), %rsi
movq 8(%r13), %rdx
addq %rsi, %rdx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag.isra.41
addq $8, %rsp
.cfi_def_cfa_offset 40
movq %r12, %rax
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3444:
.size _Z17str_to_lowercase2RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_Z17str_to_lowercase2RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4,,15
.globl _Z17str_to_lowercase3RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _Z17str_to_lowercase3RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_Z17str_to_lowercase3RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3445:
.cfi_startproc
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
movq %rsi, %r14
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
movq %rdi, %r13
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq (%rsi), %rbx
movq 8(%rsi), %r12
addq %rbx, %r12
cmpq %rbx, %r12
je .L47
.p2align 4,,10
.p2align 3
.L49:
movsbl (%rbx), %edi
movl %edi, %ebp
call isalpha@PLT
testl %eax, %eax
je .L48
orl $32, %ebp
movb %bpl, (%rbx)
.L48:
addq $1, %rbx
cmpq %r12, %rbx
jne .L49
.L47:
leaq 16(%r13), %rax
movq %r13, %rdi
movq %rax, 0(%r13)
movq (%r14), %rsi
movq 8(%r14), %rdx
addq %rsi, %rdx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag.isra.41
popq %rbx
.cfi_def_cfa_offset 40
movq %r13, %rax
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3445:
.size _Z17str_to_lowercase3RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_Z17str_to_lowercase3RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4,,15
.globl _Z17str_to_lowercase4RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _Z17str_to_lowercase4RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_Z17str_to_lowercase4RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3446:
.cfi_startproc
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
movq %rsi, %r14
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
movq %rdi, %r13
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq (%rsi), %rbp
movq 8(%rsi), %r12
addq %rbp, %r12
cmpq %rbp, %r12
je .L56
.p2align 4,,10
.p2align 3
.L58:
movsbl 0(%rbp), %edi
movl %edi, %ebx
call isalpha@PLT
movl %ebx, %edx
orl $32, %edx
testl %eax, %eax
cmovne %edx, %ebx
addq $1, %rbp
movb %bl, -1(%rbp)
cmpq %rbp, %r12
jne .L58
.L56:
leaq 16(%r13), %rax
movq %r13, %rdi
movq %rax, 0(%r13)
movq (%r14), %rsi
movq 8(%r14), %rdx
addq %rsi, %rdx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag.isra.41
popq %rbx
.cfi_def_cfa_offset 40
movq %r13, %rax
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3446:
.size _Z17str_to_lowercase4RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_Z17str_to_lowercase4RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED5Ev,comdat
.align 2
.p2align 4,,15
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev
.type _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev, @function
_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev:
.LFB3797:
.cfi_startproc
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq 8(%rdi), %rbp
movq (%rdi), %rbx
cmpq %rbx, %rbp
je .L64
movq %rdi, %r12
.p2align 4,,10
.p2align 3
.L66:
movq (%rbx), %rdi
leaq 16(%rbx), %rax
cmpq %rax, %rdi
je .L65
call _ZdlPv@PLT
.L65:
addq $32, %rbx
cmpq %rbx, %rbp
jne .L66
movq (%r12), %rbx
.L64:
testq %rbx, %rbx
je .L63
movq %rbx, %rdi
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
jmp _ZdlPv@PLT
.p2align 4,,10
.p2align 3
.L63:
.cfi_restore_state
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev, .-_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev
.set _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.align 2
.p2align 4,,15
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv:
.LFB4052:
.cfi_startproc
movq 4992(%rdi), %rax
cmpq $623, %rax
leaq 1(%rax), %rdx
ja .L89
.L72:
movq (%rdi,%rax,8), %rax
movq %rdx, 4992(%rdi)
movq %rax, %rcx
shrq $11, %rcx
movl %ecx, %edx
xorq %rax, %rdx
movq %rdx, %rax
salq $7, %rax
andl $2636928640, %eax
xorq %rax, %rdx
movq %rdx, %rax
salq $15, %rax
andl $4022730752, %eax
xorq %rdx, %rax
movq %rax, %rdx
shrq $18, %rdx
xorq %rdx, %rax
ret
.p2align 4,,10
.p2align 3
.L89:
leaq 1816(%rdi), %r8
movq %rdi, %rax
movq %rdi, %rdx
movl $2567483615, %r9d
.p2align 4,,10
.p2align 3
.L74:
movq (%rdx), %rcx
movq 8(%rdx), %rsi
andq $-2147483648, %rcx
andl $2147483647, %esi
orq %rsi, %rcx
movq %rcx, %rsi
shrq %rsi
xorq 3176(%rdx), %rsi
andl $1, %ecx
je .L73
xorq %r9, %rsi
.L73:
movq %rsi, (%rdx)
addq $8, %rdx
cmpq %rdx, %r8
jne .L74
leaq 3168(%rdi), %rsi
movl $2567483615, %r8d
.p2align 4,,10
.p2align 3
.L76:
movq 1816(%rax), %rdx
movq 1824(%rax), %rcx
andq $-2147483648, %rdx
andl $2147483647, %ecx
orq %rcx, %rdx
movq %rdx, %rcx
shrq %rcx
xorq (%rax), %rcx
andl $1, %edx
je .L75
xorq %r8, %rcx
.L75:
movq %rcx, 1816(%rax)
addq $8, %rax
cmpq %rax, %rsi
jne .L76
movq 4984(%rdi), %rax
movq (%rdi), %rdx
andq $-2147483648, %rax
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 3168(%rdi), %rdx
testb $1, %al
je .L77
movl $2567483615, %eax
xorq %rax, %rdx
.L77:
movq %rdx, 4984(%rdi)
xorl %eax, %eax
movl $1, %edx
jmp .L72
.cfi_endproc
.LFE4052:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.p2align 4,,15
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE:
.LFB3940:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdx, %rbp
movq %rsi, %rbx
subq $40, %rsp
.cfi_def_cfa_offset 96
movslq 4(%rdx), %r15
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movslq (%rdx), %rax
subq %rax, %r15
movl $4294967294, %eax
cmpq %rax, %r15
ja .L91
leaq 1(%r15), %r12
addq $1, %rax
xorl %edx, %edx
divq %r12
imulq %rax, %r12
movq %rax, %r13
.p2align 4,,10
.p2align 3
.L92:
movq %rbx, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
cmpq %rax, %r12
jbe .L92
xorl %edx, %edx
divq %r13
.L93:
addl 0(%rbp), %eax
movq 24(%rsp), %rcx
xorq %fs:40, %rcx
jne .L106
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.p2align 4,,10
.p2align 3
.L91:
.cfi_restore_state
movl $4294967295, %eax
cmpq %rax, %r15
jne .L107
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .L93
.p2align 4,,10
.p2align 3
.L107:
leaq 16(%rsp), %rax
movq %rdi, %r13
movabsq $-4294967296, %r12
movq %rax, 8(%rsp)
.L98:
movq 8(%rsp), %rdx
movq %rbx, %rsi
movq %r13, %rdi
movq %r12, 16(%rsp)
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movq %rbx, %rdi
movl %eax, %r14d
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
movq %r14, %rdx
salq $32, %rdx
addq %rdx, %rax
setc %dl
cmpq %rax, %r15
movzbl %dl, %edx
jb .L98
testq %rdx, %rdx
jne .L98
jmp .L93
.L106:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3940:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.section .rodata.str1.1
.LC2:
.string "default"
.text
.p2align 4,,15
.globl _Z22generate_random_stringB5cxx11j
.type _Z22generate_random_stringB5cxx11j, @function
_Z22generate_random_stringB5cxx11j:
.LFB3439:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3439
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
leaq 7+.LC2(%rip), %rdx
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
movq %rdi, %rbp
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %esi, %ebx
leaq -7(%rdx), %rsi
subq $10064, %rsp
.cfi_def_cfa_offset 10112
leaq 16(%rsp), %r12
leaq 5056(%rsp), %r13
movq %fs:40, %rax
movq %rax, 10056(%rsp)
xorl %eax, %eax
leaq 16(%r12), %rax
movq %r12, %rdi
movq %rax, 16(%rsp)
.LEHB0:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag.isra.39
.LEHE0:
movq %r12, %rsi
movq %r13, %rdi
.LEHB1:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE1:
movq %r13, %rdi
.LEHB2:
call _ZNSt13random_device9_M_getvalEv@PLT
.LEHE2:
movl %eax, %ecx
movl $1, %edx
leaq 48(%rsp), %r14
movq %rcx, 48(%rsp)
jmp .L110
.p2align 4,,10
.p2align 3
.L128:
movq -8(%r14,%rdx,8), %rcx
.L110:
movq %rcx, %rax
shrq $30, %rax
xorq %rcx, %rax
imulq $1812433253, %rax, %rax
addl %edx, %eax
movq %rax, (%r14,%rdx,8)
addq $1, %rdx
cmpq $624, %rdx
jne .L128
movq %r13, %rdi
movq $624, 5040(%rsp)
addq $16, %r12
call _ZNSt13random_device7_M_finiEv@PLT
movq 16(%rsp), %rdi
cmpq %r12, %rdi
je .L111
call _ZdlPv@PLT
.L111:
movabsq $523986010160, %rax
movl %ebx, %edx
movq %rax, 8(%rsp)
leaq 16(%rbp), %rax
cmpq $15, %rdx
movq %rdx, (%rsp)
movq %rax, 0(%rbp)
ja .L129
.L112:
testq %rdx, %rdx
je .L113
cmpq $1, %rdx
je .L130
xorl %esi, %esi
movq %rax, %rdi
call memset@PLT
movq (%rsp), %rdx
movq 0(%rbp), %rax
.L113:
movq %rdx, 8(%rbp)
movb $0, (%rax,%rdx)
movq 0(%rbp), %rbx
movq 8(%rbp), %r13
addq %rbx, %r13
cmpq %rbx, %r13
je .L108
leaq 8(%rsp), %r12
.p2align 4,,10
.p2align 3
.L116:
movq %r12, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
addq $1, %rbx
movb %al, -1(%rbx)
cmpq %rbx, %r13
jne .L116
.L108:
movq 10056(%rsp), %rsi
xorq %fs:40, %rsi
movq %rbp, %rax
jne .L131
addq $10064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L130:
.cfi_restore_state
movb $0, (%rax)
movq (%rsp), %rdx
movq 0(%rbp), %rax
jmp .L113
.L129:
movq %rsp, %rdi
.LEHB3:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.isra.38.constprop.51
.LEHE3:
movq (%rsp), %rdx
movq %rax, 0(%rbp)
movq %rdx, 16(%rbp)
jmp .L112
.L122:
movq %r13, %rdi
movq %rax, %rbx
call _ZNSt13random_device7_M_finiEv@PLT
.L118:
movq 16(%rsp), %rdi
addq $16, %r12
cmpq %r12, %rdi
je .L119
call _ZdlPv@PLT
.L119:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L121:
movq %rax, %rbx
jmp .L118
.L131:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3439:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3439:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3439-.LLSDACSB3439
.LLSDACSB3439:
.uleb128 .LEHB0-.LFB3439
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3439
.uleb128 .LEHE1-.LEHB1
.uleb128 .L121-.LFB3439
.uleb128 0
.uleb128 .LEHB2-.LFB3439
.uleb128 .LEHE2-.LEHB2
.uleb128 .L122-.LFB3439
.uleb128 0
.uleb128 .LEHB3-.LFB3439
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB3439
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3439:
.text
.size _Z22generate_random_stringB5cxx11j, .-_Z22generate_random_stringB5cxx11j
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.align 2
.p2align 4,,15
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.type _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_, @function
_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_:
.LFB4066:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
movq %rsi, %r15
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
movq %rsi, %r13
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r14
subq $24, %rsp
.cfi_def_cfa_offset 80
movq (%rdi), %rcx
movq 8(%rdi), %rax
subq %rcx, %rax
subq %rcx, %r13
sarq $5, %rax
testq %rax, %rax
je .L150
leaq (%rax,%rax), %rcx
movq $-32, %r12
cmpq %rcx, %rax
jbe .L161
.L134:
movq %r12, %rdi
movq %rdx, 8(%rsp)
movq %rsi, (%rsp)
call _Znwm@PLT
movq (%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rax), %rbx
movq %rax, %rbp
addq %rax, %r12
.L135:
addq %rbp, %r13
movq (%rdx), %rcx
leaq 16(%r13), %rax
movq %rax, 0(%r13)
leaq 16(%rdx), %rax
cmpq %rax, %rcx
je .L162
movq %rcx, 0(%r13)
movq 16(%rdx), %rcx
movq %rcx, 16(%r13)
.L137:
movq 8(%rdx), %rcx
movq %rax, (%rdx)
movq $0, 8(%rdx)
movb $0, 16(%rdx)
movq (%r14), %rdx
movq %rcx, 8(%r13)
cmpq %rsi, %rdx
je .L138
leaq 16(%rdx), %rax
movq %rsi, %rdi
addq $32, %rdx
subq %rdx, %rdi
movq %rbp, %rbx
movq %rdi, %rdx
andq $-32, %rdx
leaq 32(%rbp,%rdx), %rcx
jmp .L141
.p2align 4,,10
.p2align 3
.L139:
movq %rdx, (%rbx)
movq (%rax), %rdx
movq %rdx, 16(%rbx)
.L140:
movq -8(%rax), %rdx
movq %rdx, 8(%rbx)
leaq 32(%rbx), %rdx
movq $0, -8(%rax)
movb $0, (%rax)
movq %rax, -16(%rax)
addq $32, %rax
cmpq %rcx, %rdx
je .L163
movq %rdx, %rbx
.L141:
leaq 16(%rbx), %rdx
movq %rdx, (%rbx)
movq -16(%rax), %rdx
cmpq %rax, %rdx
jne .L139
movdqu (%rax), %xmm0
movups %xmm0, 16(%rbx)
jmp .L140
.p2align 4,,10
.p2align 3
.L163:
addq $64, %rbx
.L138:
movq 8(%r14), %rdx
cmpq %rsi, %rdx
je .L142
leaq 16(%rsi), %rax
addq $32, %rsi
subq %rsi, %rdx
andq $-32, %rdx
leaq 32(%rbx,%rdx), %rcx
jmp .L145
.p2align 4,,10
.p2align 3
.L143:
movq %rdx, (%rbx)
movq (%rax), %rdx
movq %rdx, 16(%rbx)
.L144:
movq -8(%rax), %rdx
addq $32, %rbx
movq $0, -8(%rax)
movb $0, (%rax)
movq %rax, -16(%rax)
addq $32, %rax
movq %rdx, -24(%rbx)
cmpq %rcx, %rbx
je .L164
.L145:
leaq 16(%rbx), %rdx
movq %rdx, (%rbx)
movq -16(%rax), %rdx
cmpq %rax, %rdx
jne .L143
movdqu (%rax), %xmm0
movups %xmm0, 16(%rbx)
jmp .L144
.p2align 4,,10
.p2align 3
.L164:
movq 8(%r14), %r15
.L142:
movq (%r14), %r13
cmpq %r15, %r13
je .L146
.p2align 4,,10
.p2align 3
.L148:
movq 0(%r13), %rdi
leaq 16(%r13), %rax
cmpq %rax, %rdi
je .L147
call _ZdlPv@PLT
.L147:
addq $32, %r13
cmpq %r15, %r13
jne .L148
movq (%r14), %r15
.L146:
testq %r15, %r15
je .L149
movq %r15, %rdi
call _ZdlPv@PLT
.L149:
movq %rbp, (%r14)
movq %rbx, 8(%r14)
movq %r12, 16(%r14)
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.p2align 4,,10
.p2align 3
.L150:
.cfi_restore_state
movl $1, %ecx
.L133:
salq $5, %rcx
movq %rcx, %r12
jmp .L134
.p2align 4,,10
.p2align 3
.L162:
movdqu 16(%rdx), %xmm0
movups %xmm0, 16(%r13)
jmp .L137
.p2align 4,,10
.p2align 3
.L161:
movabsq $576460752303423487, %rax
cmpq %rax, %rcx
ja .L134
testq %rcx, %rcx
jne .L133
movl $32, %ebx
xorl %r12d, %r12d
xorl %ebp, %ebp
jmp .L135
.cfi_endproc
.LFE4066:
.size _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_, .-_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEERS5_DpOT_,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEERS5_DpOT_,comdat
.align 2
.p2align 4,,15
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEERS5_DpOT_
.type _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEERS5_DpOT_, @function
_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEERS5_DpOT_:
.LFB3967:
.cfi_startproc
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
je .L166
leaq 16(%rax), %rdx
movq %rdx, (%rax)
movq (%rsi), %rcx
leaq 16(%rsi), %rdx
cmpq %rdx, %rcx
je .L173
movq %rcx, (%rax)
movq 16(%rsi), %rcx
movq %rcx, 16(%rax)
.L168:
movq 8(%rsi), %rcx
movq %rcx, 8(%rax)
movb $0, 16(%rsi)
movq 8(%rdi), %rax
movq %rdx, (%rsi)
movq $0, 8(%rsi)
addq $32, %rax
movq %rax, 8(%rdi)
subq $32, %rax
ret
.p2align 4,,10
.p2align 3
.L173:
movdqu 16(%rsi), %xmm0
movups %xmm0, 16(%rax)
jmp .L168
.p2align 4,,10
.p2align 3
.L166:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rdx
movq %rdi, %rbx
movq %rax, %rsi
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
movq 8(%rbx), %rax
popq %rbx
.cfi_def_cfa_offset 8
subq $32, %rax
ret
.cfi_endproc
.LFE3967:
.size _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEERS5_DpOT_, .-_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEERS5_DpOT_
.section .text.startup,"ax",@progbits
.p2align 4,,15
.globl main
.type main, @function
main:
.LFB3447:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3447
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
movl $3000000, %esi
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
leaq 48(%rsp), %rbx
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rbx, %rdi
movq $0, 32(%rsp)
leaq 16(%rsp), %rbp
.LEHB5:
call _Z22generate_random_stringB5cxx11j
.LEHE5:
leaq 16(%rsp), %rbp
movq %rbx, %rsi
movq %rbp, %rdi
.LEHB6:
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEERS5_DpOT_
.LEHE6:
movq 48(%rsp), %rdi
leaq 16(%rbx), %rax
cmpq %rax, %rdi
je .L175
call _ZdlPv@PLT
.L175:
movl $3000000, %esi
movq %rbx, %rdi
.LEHB7:
call _Z22generate_random_stringB5cxx11j
.LEHE7:
movq %rbx, %rsi
movq %rbp, %rdi
.LEHB8:
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEERS5_DpOT_
.LEHE8:
movq 48(%rsp), %rdi
leaq 16(%rbx), %rax
cmpq %rax, %rdi
je .L176
call _ZdlPv@PLT
.L176:
movl $3000000, %esi
movq %rbx, %rdi
.LEHB9:
call _Z22generate_random_stringB5cxx11j
.LEHE9:
movq %rbx, %rsi
movq %rbp, %rdi
.LEHB10:
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEERS5_DpOT_
.LEHE10:
movq 48(%rsp), %rdi
leaq 16(%rbx), %rax
cmpq %rax, %rdi
je .L177
call _ZdlPv@PLT
.L177:
movl $3000000, %esi
movq %rbx, %rdi
.LEHB11:
call _Z22generate_random_stringB5cxx11j
.LEHE11:
movq %rbx, %rsi
movq %rbp, %rdi
.LEHB12:
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEERS5_DpOT_
.LEHE12:
movq 48(%rsp), %rdi
addq $16, %rbx
cmpq %rbx, %rdi
je .L178
call _ZdlPv@PLT
.L178:
movq 16(%rsp), %rsi
leaq _Z16str_to_lowercaseRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(%rip), %rdi
.LEHB13:
call _ZNKUlOT_DpOT0_E_clIRFNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSB_EJSC_EEEDaS0_S3_.isra.26
leaq _ZSt4cout(%rip), %rdi
movq %rax, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rax
leaq _Z17str_to_lowercase2RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(%rip), %rdi
leaq 32(%rax), %rsi
call _ZNKUlOT_DpOT0_E_clIRFNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSB_EJSC_EEEDaS0_S3_.isra.26
leaq _ZSt4cout(%rip), %rdi
movq %rax, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rax
leaq _Z17str_to_lowercase3RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(%rip), %rdi
leaq 64(%rax), %rsi
call _ZNKUlOT_DpOT0_E_clIRFNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSB_EJSC_EEEDaS0_S3_.isra.26
leaq _ZSt4cout(%rip), %rdi
movq %rax, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rax
leaq _Z17str_to_lowercase4RNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(%rip), %rdi
leaq 96(%rax), %rsi
call _ZNKUlOT_DpOT0_E_clIRFNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSB_EJSC_EEEDaS0_S3_.isra.26
leaq _ZSt4cout(%rip), %rdi
movq %rax, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE13:
movq %rbp, %rdi
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev
xorl %eax, %eax
movq 88(%rsp), %rdx
xorq %fs:40, %rdx
jne .L201
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L201:
.cfi_restore_state
call __stack_chk_fail@PLT
.L193:
.L198:
movq 48(%rsp), %rdi
addq $16, %rbx
movq %rax, %r12
cmpq %rbx, %rdi
je .L187
call _ZdlPv@PLT
.L187:
movq %r12, %rax
.L181:
movq %rbp, %rdi
movq %rax, 8(%rsp)
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev
movq 8(%rsp), %rax
movq %rax, %rdi
.LEHB14:
call _Unwind_Resume@PLT
.LEHE14:
.L192:
jmp .L198
.L191:
jmp .L198
.L190:
jmp .L198
.L189:
jmp .L181
.cfi_endproc
.LFE3447:
.section .gcc_except_table
.LLSDA3447:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3447-.LLSDACSB3447
.LLSDACSB3447:
.uleb128 .LEHB5-.LFB3447
.uleb128 .LEHE5-.LEHB5
.uleb128 .L189-.LFB3447
.uleb128 0
.uleb128 .LEHB6-.LFB3447
.uleb128 .LEHE6-.LEHB6
.uleb128 .L190-.LFB3447
.uleb128 0
.uleb128 .LEHB7-.LFB3447
.uleb128 .LEHE7-.LEHB7
.uleb128 .L189-.LFB3447
.uleb128 0
.uleb128 .LEHB8-.LFB3447
.uleb128 .LEHE8-.LEHB8
.uleb128 .L191-.LFB3447
.uleb128 0
.uleb128 .LEHB9-.LFB3447
.uleb128 .LEHE9-.LEHB9
.uleb128 .L189-.LFB3447
.uleb128 0
.uleb128 .LEHB10-.LFB3447
.uleb128 .LEHE10-.LEHB10
.uleb128 .L192-.LFB3447
.uleb128 0
.uleb128 .LEHB11-.LFB3447
.uleb128 .LEHE11-.LEHB11
.uleb128 .L189-.LFB3447
.uleb128 0
.uleb128 .LEHB12-.LFB3447
.uleb128 .LEHE12-.LEHB12
.uleb128 .L193-.LFB3447
.uleb128 0
.uleb128 .LEHB13-.LFB3447
.uleb128 .LEHE13-.LEHB13
.uleb128 .L189-.LFB3447
.uleb128 0
.uleb128 .LEHB14-.LFB3447
.uleb128 .LEHE14-.LEHB14
.uleb128 0
.uleb128 0
.LLSDACSE3447:
.section .text.startup
.size main, .-main
.p2align 4,,15
.type _GLOBAL__sub_I__Z22generate_random_stringB5cxx11j, @function
_GLOBAL__sub_I__Z22generate_random_stringB5cxx11j:
.LFB4281:
.cfi_startproc
leaq _ZStL8__ioinit(%rip), %rdi
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZNSt8ios_base4InitC1Ev@PLT
movq _ZNSt8ios_base4InitD1Ev@GOTPCREL(%rip), %rdi
leaq __dso_handle(%rip), %rdx
leaq _ZStL8__ioinit(%rip), %rsi
addq $8, %rsp
.cfi_def_cfa_offset 8
jmp __cxa_atexit@PLT
.cfi_endproc
.LFE4281:
.size _GLOBAL__sub_I__Z22generate_random_stringB5cxx11j, .-_GLOBAL__sub_I__Z22generate_random_stringB5cxx11j
.section .init_array,"aw"
.align 8
.quad _GLOBAL__sub_I__Z22generate_random_stringB5cxx11j
.local _ZStL8__ioinit
.comm _ZStL8__ioinit,1,1
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.hidden __dso_handle
.ident "GCC: (Ubuntu 7.3.0-27ubuntu1~18.04) 7.3.0"
.section .note.GNU-stack,"",@progbits
|
agbrs/agb
| 2,952
|
agb/src/interrupt_handler.s
|
.arm
.global InterruptHandler
.section .iwram.interrupt_handler, "ax", %progbits
.align
InterruptHandler:
.set IO_MEMORY_MAPPED_REGISTERS, 0x04000000
.set OFFSET_INTERRUPT_ENABLED, 0x200
mov r1, #IO_MEMORY_MAPPED_REGISTERS
ldr r3, [r1, #OFFSET_INTERRUPT_ENABLED]!
and r0, r3, r3, lsr #16 @ interrupts that are enabled AND triggered
@ temporarily disable interrupts that were triggered here
bic r2, r3, r0
strh r2, [r1]
@ r0: interrupts that are enabled AND triggered
@ r1: #IO_MEMORY_MAPPED_REGISTERS + #OFFSET_INTERRUPT_ENABLED
@ r3: Original contents of enabled interrupts
@ acknowledge interrupts
strh r0, [r1, #2]
.set OFFSET_BIOS_INTERRUPT_ACKNOWLEDGE, -0x8
@ acknowledge bios interrupts
sub r1, r1, #OFFSET_INTERRUPT_ENABLED
ldrh r2, [r1, #OFFSET_BIOS_INTERRUPT_ACKNOWLEDGE]
orr r2, r2, r0
strh r2, [r1, #OFFSET_BIOS_INTERRUPT_ACKNOWLEDGE]
@ r0: interrupts that are enabled AND triggered
@ r1: #IO_MEMORY_MAPPED_REGISTERS
@ r3: Original contents of enabled interrupts
.set OFFSET_INTERRUPT_MASTER_ENABLE, 0x208
@ clear interrupt master enable
add r1, r1, #OFFSET_INTERRUPT_MASTER_ENABLE
mov r2, #0
swp r2, r2, [r1]
@ r0: interrupts that are enabled AND triggered
@ r2: old interrrupt master enable
@ r3: Original contents of enabled interrupts
@ push saved program status, old interrupt master enable, original enabled interrupts, and the link register
mrs r1, spsr
push {{r1-r3, lr}}
@ r0: interrupts that are enabled AND triggered
.set PSR_MODE_MASK, 0x1F
.set PSR_IRQ_DISABLE_MASK, 0x80
.set PSR_MODE_SYSETM, 0x1F
@ switch to system mode in the current program status register
mrs r1, cpsr
bic r1, r1, #(PSR_MODE_MASK | PSR_IRQ_DISABLE_MASK)
orr r1, r1, #PSR_MODE_SYSETM
msr cpsr, r1
@ SYSTEM MODE
push {{lr}}
@ r0: interrupts that are enabled AND triggered
@ call the rust interrupt handler with r0 set to the triggered interrupts
ldr r1, =__RUST_INTERRUPT_HANDLER
mov lr, pc
bx r1
pop {{lr}}
@ NO MEANING TO ANY REGISTERS
@ Clear the interrupt master enable
mov r0, #IO_MEMORY_MAPPED_REGISTERS
str r0, [r0, #OFFSET_INTERRUPT_MASTER_ENABLE]
.set PSR_MODE_INTERRUPT, 0x12
@ change back to interrupt mode
mrs r1, cpsr
bic r1, r1, #(PSR_MODE_MASK)
orr r1, r1, #(PSR_MODE_INTERRUPT | PSR_IRQ_DISABLE_MASK)
msr cpsr, r1
@ r0: #IO_MEMORY_MAPPED_REGISTERS
pop {{r1-r3, lr}}
msr spsr, r1
str r2, [r0, #OFFSET_INTERRUPT_MASTER_ENABLE]!
@ r0: #(IO_MEMORY_MAPPED_REGISTERS + OFFSET_INTERRUPT_MASTER_ENABLE)
strh r3, [r0, #(OFFSET_INTERRUPT_ENABLED - OFFSET_INTERRUPT_MASTER_ENABLE)]
bx lr @ return to bios
.pool
.section .iwram.program_counter
.global agb_rs__program_counter
.balign 4
agb_rs__program_counter:
.word 0
|
agbrs/agb
| 2,613
|
agb/src/entrypoint.s
|
.arm
.section .entrypoint.regular, "ax", %progbits
.align
.global __start
__start:
b .Initialise
@ Filled in by gbafix
.space 188
.Initialise:
@ Set interrupt handler
ldr r0, =InterruptHandler
ldr r1, =0x03007FFC
str r0, [r1]
@ copies ewram section in rom to ewram in ram
ldr r0, =__ewram_rom_start @ load memory address storing start of data for ewram in rom
ldr r1, =__ewram_data_start @ load memory address storing location of ewram in ram
ldr r2, =__ewram_rom_length_halfwords @ load number of 16 bit values to copy
swi 0x000B0000 @ call interrupt CpuSet.
@ r0: source
@ r1: destination
@ r2: length + size information
@
@ see: https://mgba-emu.github.io/gbatek/#swi-0bh-gbands7nds9dsi7dsi9---cpuset
ldr r0, =CommonInit
bx r0
.arm
.section .entrypoint.multiboot, "ax", %progbits
.align
b __mb_entry
@ Filled in by gbafix
.space 188
@ multiboot launch point
.global __mb_entry
__mb_entry:
b .Initialise_mb
.byte 0 @ boot mode, BIOS overwrites this value
.byte 0 @ slave ID number
.space 26 @ unused?
.Initialise_mb:
swi 0x00250000
@ Set interrupt handler
ldr r0, =InterruptHandler
ldr r1, =0x03007FFC
str r0, [r1]
ldr r0, =CommonInit
bx r0
.arm
.section .entrypoint.common, "ax", %progbits
.align
.global CommonInit
CommonInit:
@ set the waitstate control register to the normal value used in manufactured cartridges
ldr r0, =0x04000204 @ address for waitstate control register
ldr r1, =0x4317 @ WS0/ROM=3,1 clks; SRAM=8 clks; WS2/EEPROM: 8,8 clks; prefetch enabled
strh r1, [r0]
@ copies iwram section in rom to iwram in ram
ldr r0, =__iwram_rom_start
ldr r1, =__iwram_data_start
ldr r2, =__iwram_rom_length_halfwords
swi 0x000B0000
@ enable interrupts
ldr r0, =0x04000208
ldr r1, =1
str r1, [r0]
@ put zero in both r0 and r1
@ This corresponds to zero for argc and argv (which would technically be required for a c runtime)
ldr r0, =0
mov r1, r0
@ ensure the frame pointer is zero so that stack traces are guaranteed to terminate
mov r7, r0
@ load main and branch
ldr r2, =main
mov lr, pc
bx r2
@ loop if we end up here
1:
b 1b
.pool
|
agbrs/agb
| 1,240
|
agb/src/save/asm_routines.s
|
@
@ char WramReadByte(const char* offset);
@
@ A routine that reads a byte from a given memory offset.
@
agb_thumb_func agb_rs__WramReadByte
ldrb r0, [r0]
bx lr
agb_thumb_end agb_rs__WramReadByte
@
@ bool WramVerifyBuf(const char* buf1, const char* buf2, int count);
@
@ A routine that compares two memory offsets.
@
agb_thumb_func agb_rs__WramVerifyBuf
push {{r4-r5, lr}}
movs r5, r0 @ set up r5 to be r0, so we can use it immediately for the return result
movs r0, #0 @ set up r0 so the default return result is false
@ At this point, buf1 is actually in r5, so r0 can be used as a status return
1: ldrb r3, [r5,r2]
ldrb r4, [r1,r2]
cmp r3, r4
bne 0f
subs r2, #1
bpl 1b
@ Returns from the function successfully
movs r0, #1
0: @ Jumps to here return the function unsuccessfully, because r0 contains 0 at this point
pop {{r4-r5}}
pop {{r1}}
bx r1
agb_thumb_end agb_rs__WramVerifyBuf
@
@ void WramTransferBuf(const char* source, char* dest, int count);
@
@ A routine that copies one buffer into another.
@
agb_thumb_func agb_rs__WramTransferBuf
0: subs r2, #1
ldrb r3, [r0,r2]
strb r3, [r1,r2]
bne 0b
bx lr
agb_thumb_end agb_rs__WramTransferBuf
|
agbrs/agb
| 3,132
|
agb/src/agbabi/memset.s
|
@===============================================================================
@
@ ABI:
@ __aeabi_memclr, __aeabi_memclr4, __aeabi_memclr8,
@ __aeabi_memset, __aeabi_memset4, __aeabi_memset8
@ Standard:
@ memset
@ Support:
@ __agbabi_wordset4, __agbabi_lwordset4, __agbabi_memset1
@
@ Copyright (C) 2021-2023 agbabi contributors
@ For conditions of distribution and use, see copyright notice in LICENSE.md
@
@===============================================================================
.syntax unified
.arm
.align 2
.section .iwram.__aeabi_memclr, "ax", %progbits
.global __aeabi_memclr
.type __aeabi_memclr, %function
__aeabi_memclr:
mov r2, #0
b __aeabi_memset
.global __aeabi_memclr8
.type __aeabi_memclr8, %function
__aeabi_memclr8:
.global __aeabi_memclr4
.type __aeabi_memclr4, %function
__aeabi_memclr4:
mov r2, #0
b __agbabi_wordset4
.section .iwram.__aeabi_memset, "ax", %progbits
.global __agbabi_memset
.type __agbabi_memset, %function
__agbabi_memset:
.global __aeabi_memset
.type __aeabi_memset, %function
__aeabi_memset:
@ < 8 bytes probably won't be aligned: go byte-by-byte
cmp r1, #8
blt __agbabi_memset1
@ Copy head to align to next word
rsb r3, r0, #4
joaobapt_test r3
strbmi r2, [r0], #1
submi r1, r1, #1
strbcs r2, [r0], #1
strbcs r2, [r0], #1
subcs r1, r1, #2
.global __aeabi_memset8
.type __aeabi_memset8, %function
__aeabi_memset8:
.global __aeabi_memset4
.type __aeabi_memset4, %function
__aeabi_memset4:
lsl r2, r2, #24
orr r2, r2, r2, lsr #8
orr r2, r2, r2, lsr #16
.global __agbabi_wordset4
.type __agbabi_wordset4, %function
__agbabi_wordset4:
mov r3, r2
.global __agbabi_lwordset4
.type __agbabi_lwordset4, %function
__agbabi_lwordset4:
@ 16 words is roughly the threshold when lwordset is slower
cmp r1, #64
blt .Lset_2_words
@ 8 word set
push {{r4-r9}}
mov r4, r2
mov r5, r3
mov r6, r2
mov r7, r3
mov r8, r2
mov r9, r3
.Lset_8_words:
subs r1, r1, #32
stmiage r0!, {{r2-r9}}
bgt .Lset_8_words
pop {{r4-r9}}
bxeq lr
@ Fixup remaining
add r1, r1, #32
.Lset_2_words:
subs r1, r1, #8
stmiage r0!, {{r2-r3}}
bgt .Lset_2_words
bxeq lr
@ Test for remaining word
adds r1, r1, #4
strge r2, [r0], #4
bxeq lr
@ Set tail
joaobapt_test r1
strhcs r2, [r0], #2
strbmi r2, [r0], #1
bx lr
.section .iwram.__agbabi_memset1, "ax", %progbits
.global __agbabi_memset1
.type __agbabi_memset1, %function
__agbabi_memset1:
subs r1, r1, #1
strbge r2, [r0], #1
bgt __agbabi_memset1
bx lr
.section .iwram.memset, "ax", %progbits
.global memset
.type memset, %function
memset:
mov r3, r1
mov r1, r2
mov r2, r3
push {{r0, lr}}
bl __aeabi_memset
pop {{r0, lr}}
bx lr
|
agbrs/agb
| 3,054
|
agb/src/agbabi/memcpy.s
|
@===============================================================================
@
@ ABI:
@ __aeabi_memcpy, __aeabi_memcpy4, __aeabi_memcpy8
@ Standard:
@ memcpy
@ Support:
@ __agbabi_memcpy2, __agbabi_memcpy1
@
@ Copyright (C) 2021-2023 agbabi contributors
@ For conditions of distribution and use, see copyright notice in LICENSE.md
@
@===============================================================================
.syntax unified
.arm
.align 2
.section .iwram.__aeabi_memcpy, "ax", %progbits
.global __agbabi_memcpy
.type __agbabi_memcpy, %function
__agbabi_memcpy:
.global __aeabi_memcpy
.type __aeabi_memcpy, %function
__aeabi_memcpy:
@ >6-bytes is roughly the threshold when byte-by-byte copy is slower
cmp r2, #6
ble __agbabi_memcpy1
align_switch r0, r1, r3, __agbabi_memcpy1, .Lcopy_halves
@ Check if r0 (or r1) needs word aligning
rsbs r3, r0, #4
joaobapt_test r3
@ Copy byte head to align
ldrbmi r3, [r1], #1
strbmi r3, [r0], #1
submi r2, r2, #1
@ r0, r1 are now half aligned
@ Copy half head to align
ldrhcs r3, [r1], #2
strhcs r3, [r0], #2
subcs r2, r2, #2
@ r0, r1 are now word aligned
.global __aeabi_memcpy8
.type __aeabi_memcpy8, %function
__aeabi_memcpy8:
.global __aeabi_memcpy4
.type __aeabi_memcpy4, %function
__aeabi_memcpy4:
cmp r2, #32
blt .Lcopy_words
@ Word aligned, 32-byte copy
push {{r4-r10}}
.Lloop_32:
subs r2, r2, #32
ldmiage r1!, {{r3-r10}}
stmiage r0!, {{r3-r10}}
bgt .Lloop_32
pop {{r4-r10}}
bxeq lr
@ < 32 bytes remaining to be copied
add r2, r2, #32
.Lcopy_words:
cmp r2, #4
blt .Lcopy_halves
.Lloop_4:
subs r2, r2, #4
ldrge r3, [r1], #4
strge r3, [r0], #4
bgt .Lloop_4
bxeq lr
@ Copy byte & half tail
@ This test still works when r2 is negative
joaobapt_test r2
@ Copy half
ldrhcs r3, [r1], #2
strhcs r3, [r0], #2
@ Copy byte
ldrbmi r3, [r1]
strbmi r3, [r0]
bx lr
.Lcopy_halves:
@ Copy byte head to align
tst r0, #1
ldrbne r3, [r1], #1
strbne r3, [r0], #1
subne r2, r2, #1
@ r0, r1 are now half aligned
.global __agbabi_memcpy2
.type __agbabi_memcpy2, %function
__agbabi_memcpy2:
subs r2, r2, #2
ldrhge r3, [r1], #2
strhge r3, [r0], #2
bgt __agbabi_memcpy2
bxeq lr
@ Copy byte tail
adds r2, r2, #2
ldrbne r3, [r1]
strbne r3, [r0]
bx lr
.section .iwram.__agbabi_memcpy1, "ax", %progbits
.global __agbabi_memcpy1
.type __agbabi_memcpy1, %function
__agbabi_memcpy1:
subs r2, r2, #1
ldrbge r3, [r1], #1
strbge r3, [r0], #1
bgt __agbabi_memcpy1
bx lr
.section .iwram.memcpy, "ax", %progbits
.global memcpy
.type memcpy, %function
memcpy:
push {{r0, lr}}
bl __aeabi_memcpy
pop {{r0, lr}}
bx lr
|
agbrs/agb
| 7,808
|
agb/src/sound/mixer/mixer.s
|
.macro mono_add_fn_loop fn_name:req is_first:req is_loop:req
agb_arm_func \fn_name
@ Arguments
@ r0 - pointer to the sample data from the beginning
@ r1 - pointer to the target sample buffer &[i32; BUFFER_SIZE]
@ r2 - BUFFER_SIZE - the length of the array in r1. Must be a multiple of 4
@ r3 - (length - restart point) (how much to rewind by)
@ Stack position 1 - channel length
@ Stack position 2 - current channel position
@ Stack position 3 - the playback speed
@ Stack position 4 - the amount to multiply by
@
@ Returns the new channel position
push {{r4-r11}}
ldr r4, [sp, #(8*4)] @ load the channel length into r4
ldr r5, [sp, #(9*4)] @ load the current channel position into r5
ldr r6, [sp, #(10*4)] @ load the playback speed into r6
ldr r12, [sp, #(11*4)] @ load the amount to multiply by into r12
@ The core loop
1:
.ifc \is_first,false
ldm r1, {{r7-r10}}
.endif
.irp reg, r7,r8,r9,r10
cmp r4, r5, lsr #8 @ check if we're overflowing
.ifc \is_loop,true
suble r5, r5, r3 @ if we are, subtract the overflow amount
.else
ble 2f @ if we are, zero the rest of the buffer
.endif
mov r11, r5, lsr #8 @ calculate the next location to get a value from
ldrsb r11, [r0, r11] @ load a single value
.ifc \is_first,true @ multiply the sample value, but only add if not the first call
mul \reg, r11, r12
.else
mla \reg, r11, r12, \reg
.endif
add r5, r5, r6 @ calculate the next sample read location
.endr
stmia r1!, {{r7-r10}}
subs r2, r2, #4
bne 1b
.ifc \is_loop,false
b 3f
2:
.ifc \is_first,true @ zero the rest of the buffer as this sample has ended
ands r7, r2, #3
sub r2, r2, r7
beq 5f
mov r8, #0
4:
stmia r1!, {{r8}}
subs r7, r7, #1
bne 4b
5:
cmp r2, #0
beq 3f
.irp reg, r7,r8,r9,r10
mov \reg, #0
.endr
5:
stmia r1!, {{r7-r10}}
subs r2, r2, #4
bne 5b
.endif
3:
.endif
mov r0, r5 @ return the playback position
pop {{r4-r11}}
bx lr
agb_arm_end \fn_name
.endm
mono_add_fn_loop agb_rs__mixer_add_mono_loop_first true true
mono_add_fn_loop agb_rs__mixer_add_mono_loop false true
mono_add_fn_loop agb_rs__mixer_add_mono_first true false
mono_add_fn_loop agb_rs__mixer_add_mono false false
.macro stereo_add_fn fn_name:req is_first:req
agb_arm_func \fn_name
@ Arguments
@ r0 - pointer to the data to be copied (u8 array)
@ r1 - pointer to the sound buffer (i16 array which will alternate left and right channels, 32-bit aligned)
@ r2 - volume to play the sound at
@ r3 - the buffer size
@
@ The sound buffer must be SOUND_BUFFER_SIZE * 2 in size = 176 * 2
push {{r4-r11}}
ldr r5, =0x00000FFF
mov r8, r3
.macro add_stereo_sample sample_reg:req
ldrsh r6, [r0], #2 @ load the current sound sample to r6
@ This is slightly convoluted, but is mainly done for performance reasons. It is better
@ to hit ROM just once and then do 3 really simple instructions then do 2 ldrsbs however annoying
@ this is. Also, since all this code is in IWRAM and we never hit ROM otherwise, all accesses
@ are sequential and exactly the size of the bus to ROM (16 bits), so hopefully this will be super fast.
@
@ The next 3 instructions set up the current value in r6 to be in the expected format
@ 1 = 2s complement marks (so if negative, these are all 1s, if positive these are 0s)
@ L = the left sample
@ R = the right sample
@ 0 = all zeros
@ Split into bytes
@
@ At this point
@ r6 = | 1 | 1 | L | R | where the upper bytes are 1s if L is negative. No care about R
@ asr #8 | 1 | 1 | 1 | L | drop R off the right hand side
and r7, r5, r6, asr #8 @ r7 = | 0 | 0 | 1 | L | exactly what we want this to be. The mask puts the 1 as 00001111 ready for the shift later
lsl r6, r6, #24 @ r6 = | R | 0 | 0 | 0 | drop everything except the right sample
orr r6, r7, r6, asr #8 @ r6 = | 1 | R | 1 | L | now we have it perfectly set up
.ifc \is_first,true
mul \sample_reg, r6, r2
.else
mla \sample_reg, r6, r2, \sample_reg @ r4 += r6 * r2 (calculating both the left and right samples together)
.endif
.endm
1:
.ifc \is_first,true
.else
ldmia r1, {{r9-r12}} @ read the current values
.endif
add_stereo_sample r9
add_stereo_sample r10
add_stereo_sample r11
add_stereo_sample r12
.purgem add_stereo_sample
stmia r1!, {{r9-r12}} @ store the new value, and increment the pointer
subs r8, r8, #4 @ loop counter
bne 1b @ jump back if we're done with the loop
pop {{r4-r11}}
bx lr
agb_arm_end \fn_name
.endm
stereo_add_fn agb_rs__mixer_add_stereo false
stereo_add_fn agb_rs__mixer_add_stereo_first true
@ TODO(GI): Might bring this back later
@ stereo_add_fn agb_rs__mixer_add_stereo_first true
agb_arm_func agb_rs__mixer_collapse
@ Arguments:
@ r0 = target buffer (i8)
@ r1 = input buffer (i16) of fixnums with 4 bits of precision (read in sets of i16 in an i32)
@ r2 = loop counter
push {{r4-r11,lr}}
CONST_0 .req r7
CONST_128 .req r8
TEMP .req r10
SWAP_SIGN .req r11
ldr CONST_0, =0
ldr CONST_128, =128
ldr SWAP_SIGN, =0x80808080
mov r4, r2
@ The idea for this solution came from pimpmobile:
@ https://github.com/kusma/pimpmobile/blob/f2b2be49e806ca2a0d99cf91b3838d6d10f86b7d/src/pimp_mixer_clip_arm.S
@
@ The register should be 127 bigger then what you actually want, and we'll correct for that later. Hence the
@ add instructions in `load_sample`.
@
@ The idea behind this is in the bit patters of -128 and 127 which are 10000000 and 01111111 respectively, -x = !x + 1 => !x = -x-1
@ and we want to clamp the value between them.
@
@ The first instruction calculates `-((sample + 128) >> 8)`. If sample is between -128 and 127, then
@ 0 <= sample + 128 <= 255 which means that shifting that right by 8 is 0. Hence the zero flag will be set, so
@ the `andne` instruction won't execute.
@
@ If the sample is outside of a signed 8 bit value, then `sample >> 8` will either be -1 or 1 (we assume that samples)
@ don't go too high, but the idea still works, so you can generalise this further if you want. This value is stored in TEMP
@
@ -1 has binary expansion (as a 32-bit integer) of all 1s and 1 of all zeros and then a 1.
@ So (-1 logical >> 24) gives 11111111 and (1 logical >> 24) gives 00000000 so register is clamped between these two values.
.macro clamp_s8 reg:req
subs TEMP, CONST_0, \reg, asr #8
movne \reg, TEMP, lsr #24
.endm
.macro load_sample left_reg:req right_reg:req
mov \right_reg, \left_reg, lsl #16 @ push the sample 16 bits first
add \right_reg, CONST_128, \right_reg, asr #20 @ move right sample back to being the correct value
add \left_reg, CONST_128, \left_reg, asr #20 @ now we only have the left sample
clamp_s8 \left_reg @ clamp the audio to 8 bit values
clamp_s8 \right_reg
.endm
1:
.rept 4
ldmia r1!, {{r3,r5,r6,r9}}
load_sample r3, r12
load_sample r5, lr
orr r3, r3, r5, lsl #8
orr r12, r12, lr, lsl #8
load_sample r6, lr
orr r3, r3, r6, lsl #16
orr r12, r12, lr, lsl #16
load_sample r9, lr
orr r3, r3, r9, lsl #24
orr r12, r12, lr, lsl #24
eor r3, r3, SWAP_SIGN
eor r12, r12, SWAP_SIGN
str r3, [r0, r4] @ *(r0 + (r4 = SOUND_BUFFER_SIZE)) = r3
str r12, [r0], #4 @ *r0 = r12; r0 += 4
.endr
subs r2, r2, #16 @ r2 -= 16
bne 1b @ loop if not 0
pop {{r4-r11,lr}}
bx lr
agb_arm_end agb_rs__mixer_collapse
|
ageneau/ecl-android
| 2,486
|
nacl/libgc/rs6000_mach_dep.s
|
.set r0,0
.set r1,1
.set r2,2
.set r3,3
.set r4,4
.set r5,5
.set r6,6
.set r7,7
.set r8,8
.set r9,9
.set r10,10
.set r11,11
.set r12,12
.set r13,13
.set r14,14
.set r15,15
.set r16,16
.set r17,17
.set r18,18
.set r19,19
.set r20,20
.set r21,21
.set r22,22
.set r23,23
.set r24,24
.set r25,25
.set r26,26
.set r27,27
.set r28,28
.set r29,29
.set r30,30
.set r31,31
.extern .GC_push_one
# Mark from machine registers that are saved by C compiler
.globl .GC_push_regs
.csect .text[PR]
.align 2
.globl GC_push_regs
.globl .GC_push_regs
.csect GC_push_regs[DS]
GC_push_regs:
.long .GC_push_regs, TOC[tc0], 0
.csect .text[PR]
.GC_push_regs:
stu r1,-64(r1) # reserve stack frame
mflr r0 # save link register
st r0,0x48(r1)
oril r3,r2,0x0 # mark from r2
bl .GC_push_one
cror 15,15,15
oril r3,r13,0x0 # mark from r13-r31
bl .GC_push_one
cror 15,15,15
oril r3,r14,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r15,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r16,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r17,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r18,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r19,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r20,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r21,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r22,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r23,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r24,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r25,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r26,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r27,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r28,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r29,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r30,0x0
bl .GC_push_one
cror 15,15,15
oril r3,r31,0x0
bl .GC_push_one
cror 15,15,15
l r0,0x48(r1)
mtlr r0
ai r1,r1,64
br
.long 0
.byte 0,0,0,0,0,0,0,0
|
ageneau/ecl-android
| 2,525
|
nacl/libgc/powerpc_macosx_mach_dep.s
|
.text
.set linkageArea,24
.set params,4
.set alignment,4
.set spaceToSave,linkageArea+params+alignment
.set spaceToSave8,spaceToSave+8
; Mark from machine registers that are saved by C compiler
.globl _GC_push_regs
_GC_push_regs:
; PROLOG
mflr r0 ; get return address
stw r0,8(r1) ; save return address
stwu r1,-spaceToSave(r1) ; skip over caller save area
;
mr r3,r2 ; mark from r2. Well Im not really sure
; that this is necessary or even the right
; thing to do - at least it doesnt harm...
; According to Apples docs it points to
; the direct data area, whatever that is...
bl L_GC_push_one$stub
mr r3,r13 ; mark from r13-r31
bl L_GC_push_one$stub
mr r3,r14
bl L_GC_push_one$stub
mr r3,r15
bl L_GC_push_one$stub
mr r3,r16
bl L_GC_push_one$stub
mr r3,r17
bl L_GC_push_one$stub
mr r3,r18
bl L_GC_push_one$stub
mr r3,r19
bl L_GC_push_one$stub
mr r3,r20
bl L_GC_push_one$stub
mr r3,r21
bl L_GC_push_one$stub
mr r3,r22
bl L_GC_push_one$stub
mr r3,r23
bl L_GC_push_one$stub
mr r3,r24
bl L_GC_push_one$stub
mr r3,r25
bl L_GC_push_one$stub
mr r3,r26
bl L_GC_push_one$stub
mr r3,r27
bl L_GC_push_one$stub
mr r3,r28
bl L_GC_push_one$stub
mr r3,r29
bl L_GC_push_one$stub
mr r3,r30
bl L_GC_push_one$stub
mr r3,r31
bl L_GC_push_one$stub
; EPILOG
lwz r0,spaceToSave8(r1) ; get return address back
mtlr r0 ; reset link register
addic r1,r1,spaceToSave ; restore stack pointer
blr
.data
.picsymbol_stub
L_GC_push_one$stub:
.indirect_symbol _GC_push_one
mflr r0
bcl 20,31,L0$_GC_push_one
L0$_GC_push_one:
mflr r11
addis r11,r11,ha16(L_GC_push_one$lazy_ptr-L0$_GC_push_one)
mtlr r0
lwz r12,lo16(L_GC_push_one$lazy_ptr-L0$_GC_push_one)(r11)
mtctr r12
addi r11,r11,lo16(L_GC_push_one$lazy_ptr-L0$_GC_push_one)
bctr
.data
.lazy_symbol_pointer
L_GC_push_one$lazy_ptr:
.indirect_symbol _GC_push_one
.long dyld_stub_binding_helper
.non_lazy_symbol_pointer
L_GC_push_one$non_lazy_ptr:
.indirect_symbol _GC_push_one
.long 0
|
ageneau/ecl-android
| 2,081
|
nacl/libgc/alpha_mach_dep.S
|
.arch ev6
.text
.align 4
.globl GC_push_regs
.ent GC_push_regs 2
GC_push_regs:
ldgp $gp, 0($27)
lda $sp, -16($sp)
stq $26, 0($sp)
.mask 0x04000000, 0
.frame $sp, 16, $26, 0
/* $0 integer result */
/* $1-$8 temp regs - not preserved cross calls */
/* $9-$15 call saved regs */
/* $16-$21 argument regs - not preserved cross calls */
/* $22-$28 temp regs - not preserved cross calls */
/* $29 global pointer - not preserved cross calls */
/* $30 stack pointer */
# define call_push(x) \
mov x, $16; \
jsr $26, GC_push_one; \
ldgp $gp, 0($26)
call_push($9)
call_push($10)
call_push($11)
call_push($12)
call_push($13)
call_push($14)
call_push($15)
/* $f0-$f1 floating point results */
/* $f2-$f9 call saved regs */
/* $f10-$f30 temp regs - not preserved cross calls */
/* Use the most efficient transfer method for this hardware. */
/* Bit 1 detects the FIX extension, which includes ftoit. */
amask 2, $0
bne $0, $use_stack
#undef call_push
#define call_push(x) \
ftoit x, $16; \
jsr $26, GC_push_one; \
ldgp $gp, 0($26)
call_push($f2)
call_push($f3)
call_push($f4)
call_push($f5)
call_push($f6)
call_push($f7)
call_push($f8)
call_push($f9)
ldq $26, 0($sp)
lda $sp, 16($sp)
ret $31, ($26), 1
.align 4
$use_stack:
#undef call_push
#define call_push(x) \
stt x, 8($sp); \
ldq $16, 8($sp); \
jsr $26, GC_push_one; \
ldgp $gp, 0($26)
call_push($f2)
call_push($f3)
call_push($f4)
call_push($f5)
call_push($f6)
call_push($f7)
call_push($f8)
call_push($f9)
ldq $26, 0($sp)
lda $sp, 16($sp)
ret $31, ($26), 1
.end GC_push_regs
|
ageneau/ecl-android
| 1,526
|
nacl/libgc/powerpc_darwin_mach_dep.s
|
; GC_push_regs function. Under some optimization levels GCC will clobber
; some of the non-volatile registers before we get a chance to save them
; therefore, this cannot be inline asm.
.text
.align 2
.globl _GC_push_regs
_GC_push_regs:
; Prolog
mflr r0
stw r0,8(r1)
stwu r1,-80(r1)
; Push r13-r31
mr r3,r13
bl L_GC_push_one$stub
mr r3,r14
bl L_GC_push_one$stub
mr r3,r15
bl L_GC_push_one$stub
mr r3,r16
bl L_GC_push_one$stub
mr r3,r17
bl L_GC_push_one$stub
mr r3,r18
bl L_GC_push_one$stub
mr r3,r19
bl L_GC_push_one$stub
mr r3,r20
bl L_GC_push_one$stub
mr r3,r21
bl L_GC_push_one$stub
mr r3,r22
bl L_GC_push_one$stub
mr r3,r23
bl L_GC_push_one$stub
mr r3,r24
bl L_GC_push_one$stub
mr r3,r25
bl L_GC_push_one$stub
mr r3,r26
bl L_GC_push_one$stub
mr r3,r27
bl L_GC_push_one$stub
mr r3,r28
bl L_GC_push_one$stub
mr r3,r29
bl L_GC_push_one$stub
mr r3,r30
bl L_GC_push_one$stub
mr r3,r31
bl L_GC_push_one$stub
;
lwz r0,88(r1)
addi r1,r1,80
mtlr r0
; Return
blr
; PIC stuff, generated by GCC
.data
.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
.align 2
L_GC_push_one$stub:
.indirect_symbol _GC_push_one
mflr r0
bcl 20,31,L0$_GC_push_one
L0$_GC_push_one:
mflr r11
addis r11,r11,ha16(L_GC_push_one$lazy_ptr-L0$_GC_push_one)
mtlr r0
lwzu r12,lo16(L_GC_push_one$lazy_ptr-L0$_GC_push_one)(r11)
mtctr r12
bctr
.data
.lazy_symbol_pointer
L_GC_push_one$lazy_ptr:
.indirect_symbol _GC_push_one
.long dyld_stub_binding_helper
|
ageneau/ecl-android
| 1,736
|
nacl/libgc/sparc_mach_dep.S
|
! SPARCompiler 3.0 and later apparently no longer handles
! asm outside functions. So we need a separate .s file
! This is only set up for SunOS 5, not SunOS 4.
! Assumes this is called before the stack contents are
! examined.
.seg "text"
.globl GC_save_regs_in_stack
.globl GC_push_regs
GC_save_regs_in_stack:
GC_push_regs:
#if defined(__arch64__) || defined(__sparcv9)
save %sp,-128,%sp
flushw
ret
restore %sp,2047+128,%o0
#else /* 32 bit SPARC */
ta 0x3 ! ST_FLUSH_WINDOWS
mov %sp,%o0
retl
nop
#endif /* 32 bit SPARC */
.GC_save_regs_in_stack_end:
.size GC_save_regs_in_stack,.GC_save_regs_in_stack_end-GC_save_regs_in_stack
.globl GC_clear_stack_inner
GC_clear_stack_inner:
#if defined(__arch64__) || defined(__sparcv9)
mov %sp,%o2 ! Save sp
add %sp,2047-8,%o3 ! p = sp+bias-8
add %o1,-2047-192,%sp ! Move sp out of the way,
! so that traps still work.
! Includes some extra words
! so we can be sloppy below.
loop:
stx %g0,[%o3] ! *(long *)p = 0
cmp %o3,%o1
bgu,pt %xcc, loop ! if (p > limit) goto loop
add %o3,-8,%o3 ! p -= 8 (delay slot)
retl
mov %o2,%sp ! Restore sp., delay slot
#else /* 32 bit SPARC */
mov %sp,%o2 ! Save sp
add %sp,-8,%o3 ! p = sp-8
clr %g1 ! [g0,g1] = 0
add %o1,-0x60,%sp ! Move sp out of the way,
! so that traps still work.
! Includes some extra words
! so we can be sloppy below.
loop:
std %g0,[%o3] ! *(long long *)p = 0
cmp %o3,%o1
bgu loop ! if (p > limit) goto loop
add %o3,-8,%o3 ! p -= 8 (delay slot)
retl
mov %o2,%sp ! Restore sp., delay slot
#endif /* 32 bit SPARC */
.GC_clear_stack_inner_end:
.size GC_clear_stack_inner,.GC_clear_stack_inner_end-GC_clear_stack_inner
|
ageneau/ecl-android
| 1,267
|
nacl/libgc/mips_sgi_mach_dep.s
|
#include <sys/regdef.h>
#include <sys/asm.h>
/* This file must be preprocessed. But the SGI assembler always does */
/* that. Furthermore, a generic preprocessor won't do, since some of */
/* the SGI-supplied include files rely on behavior of the MIPS */
/* assembler. Hence we treat and name this file as though it required */
/* no preprocessing. */
# define call_push(x) move $4,x; jal GC_push_one
.option pic2
.text
/* Mark from machine registers that are saved by C compiler */
# define FRAMESZ 32
# define RAOFF FRAMESZ-SZREG
# define GPOFF FRAMESZ-(2*SZREG)
NESTED(GC_push_regs, FRAMESZ, ra)
.mask 0x80000000,-SZREG # inform debugger of saved ra loc
move t0,gp
SETUP_GPX(t8)
PTR_SUBU sp,FRAMESZ
# ifdef SETUP_GP64
SETUP_GP64(GPOFF, GC_push_regs)
# endif
SAVE_GP(GPOFF)
REG_S ra,RAOFF(sp)
# if (_MIPS_SIM == _MIPS_SIM_ABI32)
call_push($2)
call_push($3)
# endif
call_push($16)
call_push($17)
call_push($18)
call_push($19)
call_push($20)
call_push($21)
call_push($22)
call_push($23)
call_push($30)
REG_L ra,RAOFF(sp)
# ifdef RESTORE_GP64
RESTORE_GP64
# endif
PTR_ADDU sp,FRAMESZ
j ra
.end GC_push_regs
|
AgentD/hausboot
| 1,297
|
mbr/abi.S
|
/* SPDX-License-Identifier: ISC */
/*
* abi.S
*
* Copyright (C) 2023 David Oberhollenzer <goliath@infraroot.at>
*/
.code16
.global main
.global CallVbr
.section ".entry"
/*
Main entry point. The BIOS loads the MBR to 0000:7c00 and then jump here.
We relocate the MBR to 0000:0600 (the linker "thinks" we are there already,
so the addresses are fixed up if we use the symbols, but we need to be
carefull about relative addressing!)
We also setup a stack and call into the main() function, passing along the
original EDX register value, containing the boot device ID (for use
with INT 13) in the lower 8 bit.
*/
_start:
xor %ax, %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %ss
mov $0x0a00, %sp
pushl %edx
mov $0x0600, %di
mov $0x7c00, %si
mov $512, %cx
rep
movsb
ljmp $00,$_relocated
_relocated:
calll main
/*
void CallVbr(uint32_t edx, const MBREntry *ent);
Jumps into the volume boot record loaded to 0000:7c00, setting up the
binary interface as expected:
- DL containing the boot device number for INT 13
- DS:SI pointing to the partition table entry that was selected
Note: edx is popped twice intentionally. First time is to get rid of the
return address that is also on the stack.
*/
CallVbr:
pop %edx
pop %edx
pop %esi
ljmp $00,$0x7c00
|
AgentD/hausboot
| 1,528
|
kernel/abi.S
|
/* SPDX-License-Identifier: ISC */
/*
* abi.S
*
* Copyright (C) 2023 David Oberhollenzer <goliath@infraroot.at>
*/
.global _start
.extern multiboot_main
.extern inital_stack_ptr
/*
We use the linker script to set up the following order of sections:
- text
- data
- bss
Each with 4k alignment. We instruct the linker to export the following
pseudo symbols for use in the code to get the addresses of the segments.
*/
.extern __start_text
.extern __stop_text
.extern __start_data
.extern __stop_data
.extern __start_bss
.extern __stop_bss
/*
Multiboot header. Because we are using a flat binary instead of ELF, we
manually specify load address and section layout for the boot loader.
*/
.section .mbheader
.align 4
.long 0x1BADB002
.long 0x00010003
.long -(0x1BADB002 + 0x00010003)
.long .mbheader
.long __start_text
.long __stop_data
.long __stop_bss
.long _start
/*
Entry point that the boot loader jumps to.
*/
.section .text
_start:
movl %eax, %ecx
movl $gdt_desc, %eax
lgdt (%eax)
movl $0x10, %eax
movl %eax, %ds
movl %eax, %es
movl %eax, %fs
movl %eax, %gs
movl %eax, %ss
ljmp $0x08,$.flush
.flush:
movl $_init_stack_ptr, %esp
push %ecx
push %ebx
call multiboot_main
/*
A dummy GDT with identity mapping, replacing the one from the boot loader.
*/
gdt:
.quad 0x0000000000000000
.quad 0x00CF9A000000FFFF
.quad 0x00CF92000000FFFF
gdt_end:
gdt_desc:
.word gdt_end - gdt - 1
.long gdt
/*
Initial kernel stack
*/
.section .bss
_init_stack:
.space 1024
_init_stack_ptr:
|
AgentD/hausboot
| 1,840
|
lib/pm86/pmcall.S
|
/* SPDX-License-Identifier: ISC */
/*
* pmcall.S
*
* Copyright (C) 2023 David Oberhollenzer <goliath@infraroot.at>
*/
.code16
.section ".text"
.globl ProtectedModeCall
.type ProtectedModeCall, @function
ProtectedModeCall:
/* save away the 16 bit context */
popl %eax
movl %eax, (_scratch)
movl %ebp, (_scratch + 4)
movw %ss, %ax
movw %ax, (_scratch + 8)
movw %sp, (_scratch + 10)
movw %ds, (_scratch + 12)
movw %es, (_scratch + 14)
/* calculate abolute, 32 bit stack pointer */
movzx %sp, %ebp
shl $4, %eax
addl %eax, %ebp
movl %ebp, %esp
/* enter protected mode */
cli
cld
xor %eax, %eax
movw %ax, %ds
movl $gdt_desc, %eax
lgdt (%eax)
movl %cr0, %eax
or 0x01, %al
movl %eax, %cr0
ljmp $0x08,$_enterpm
.code32
_enterpm:
/* call into the desired 32 bit function */
mov $0x10, %eax
mov %eax, %ss
mov %eax, %ds
pop %eax
call *%eax
/* jump into a 16 bit segment */
cli
cld
ljmp $0x18,$_seg16
.code16
_seg16:
movw $0x20, %ax
movw %ax, %es
movw %ax, %ds
movw %ax, %ss
/* leave protected mode */
movl %cr0, %eax
and ~0x01, %al
movl %eax, %cr0
ljmp $0,$_leavepm
_leavepm:
/* restore old 16 bit environment */
movl (_scratch + 4), %ebp
movw (_scratch + 8), %ss
movw (_scratch + 10), %ax
movzx %ax, %esp
movw (_scratch + 12), %ds
movw (_scratch + 14), %es
/* repair stack and return */
movl (_scratch), %eax
pushl %eax
retl
gdt:
.quad 0x0000000000000000 /* 0x00: null segment */
.quad 0x00CF9A000000FFFF /* 0x08: 32 bit code segment */
.quad 0x00CF92000000FFFF /* 0x10: 32 bit data segment */
.quad 0x008F9A000000FFFF /* 0x18: 16 bit code segment */
.quad 0x008F92000000FFFF /* 0x18: 16 bit data segment */
gdt_end:
gdt_desc:
.word gdt_end - gdt - 1
.long gdt
_scratch:
.quad 0x0000000000000000
.quad 0x0000000000000000
.size ProtectedModeCall, .-ProtectedModeCall
|
Aghajari/AXrLottie
| 19,929
|
AXrLottie/src/main/cpp/src/vector/pixman/pixman-arm-neon-asm.S
|
/*
* Copyright © 2009 Nokia Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Author: Siarhei Siamashka (siarhei.siamashka@nokia.com)
*/
/*
* This file contains implementations of NEON optimized pixel processing
* functions. There is no full and detailed tutorial, but some functions
* (those which are exposing some new or interesting features) are
* extensively commented and can be used as examples.
*
* You may want to have a look at the comments for following functions:
* - pixman_composite_over_8888_0565_asm_neon
* - pixman_composite_over_n_8_0565_asm_neon
*/
/* Prevent the stack from becoming executable for no reason... */
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits
#endif
.text
.fpu neon
.arch armv7a
.object_arch armv4
.eabi_attribute 10, 0 /* suppress Tag_FP_arch */
.eabi_attribute 12, 0 /* suppress Tag_Advanced_SIMD_arch */
.arm
.altmacro
.p2align 2
//#include "pixman-arm-asm.h"
/* Supplementary macro for setting function attributes */
.macro pixman_asm_function fname
.func fname
.global fname
#ifdef __ELF__
.hidden fname
.type fname, %function
#endif
fname:
.endm
//#include "pixman-private.h"
/*
* The defines which are shared between C and assembly code
*/
/* bilinear interpolation precision (must be < 8) */
#define BILINEAR_INTERPOLATION_BITS 7
#define BILINEAR_INTERPOLATION_RANGE (1 << BILINEAR_INTERPOLATION_BITS)
#include "pixman-arm-neon-asm.h"
/* Global configuration options and preferences */
/*
* The code can optionally make use of unaligned memory accesses to improve
* performance of handling leading/trailing pixels for each scanline.
* Configuration variable RESPECT_STRICT_ALIGNMENT can be set to 0 for
* example in linux if unaligned memory accesses are not configured to
* generate.exceptions.
*/
.set RESPECT_STRICT_ALIGNMENT, 1
/*
* Set default prefetch type. There is a choice between the following options:
*
* PREFETCH_TYPE_NONE (may be useful for the ARM cores where PLD is set to work
* as NOP to workaround some HW bugs or for whatever other reason)
*
* PREFETCH_TYPE_SIMPLE (may be useful for simple single-issue ARM cores where
* advanced prefetch intruduces heavy overhead)
*
* PREFETCH_TYPE_ADVANCED (useful for superscalar cores such as ARM Cortex-A8
* which can run ARM and NEON instructions simultaneously so that extra ARM
* instructions do not add (many) extra cycles, but improve prefetch efficiency)
*
* Note: some types of function can't support advanced prefetch and fallback
* to simple one (those which handle 24bpp pixels)
*/
.set PREFETCH_TYPE_DEFAULT, PREFETCH_TYPE_ADVANCED
/* Prefetch distance in pixels for simple prefetch */
.set PREFETCH_DISTANCE_SIMPLE, 64
/*
* Implementation of pixman_composite_over_8888_0565_asm_neon
*
* This function takes a8r8g8b8 source buffer, r5g6b5 destination buffer and
* performs OVER compositing operation. Function fast_composite_over_8888_0565
* from pixman-fast-path.c does the same in C and can be used as a reference.
*
* First we need to have some NEON assembly code which can do the actual
* operation on the pixels and provide it to the template macro.
*
* Template macro quite conveniently takes care of emitting all the necessary
* code for memory reading and writing (including quite tricky cases of
* handling unaligned leading/trailing pixels), so we only need to deal with
* the data in NEON registers.
*
* NEON registers allocation in general is recommented to be the following:
* d0, d1, d2, d3 - contain loaded source pixel data
* d4, d5, d6, d7 - contain loaded destination pixels (if they are needed)
* d24, d25, d26, d27 - contain loading mask pixel data (if mask is used)
* d28, d29, d30, d31 - place for storing the result (destination pixels)
*
* As can be seen above, four 64-bit NEON registers are used for keeping
* intermediate pixel data and up to 8 pixels can be processed in one step
* for 32bpp formats (16 pixels for 16bpp, 32 pixels for 8bpp).
*
* This particular function uses the following registers allocation:
* d0, d1, d2, d3 - contain loaded source pixel data
* d4, d5 - contain loaded destination pixels (they are needed)
* d28, d29 - place for storing the result (destination pixels)
*/
/*
* Step one. We need to have some code to do some arithmetics on pixel data.
* This is implemented as a pair of macros: '*_head' and '*_tail'. When used
* back-to-back, they take pixel data from {d0, d1, d2, d3} and {d4, d5},
* perform all the needed calculations and write the result to {d28, d29}.
* The rationale for having two macros and not just one will be explained
* later. In practice, any single monolitic function which does the work can
* be split into two parts in any arbitrary way without affecting correctness.
*
* There is one special trick here too. Common template macro can optionally
* make our life a bit easier by doing R, G, B, A color components
* deinterleaving for 32bpp pixel formats (and this feature is used in
* 'pixman_composite_over_8888_0565_asm_neon' function). So it means that
* instead of having 8 packed pixels in {d0, d1, d2, d3} registers, we
* actually use d0 register for blue channel (a vector of eight 8-bit
* values), d1 register for green, d2 for red and d3 for alpha. This
* simple conversion can be also done with a few NEON instructions:
*
* Packed to planar conversion:
* vuzp.8 d0, d1
* vuzp.8 d2, d3
* vuzp.8 d1, d3
* vuzp.8 d0, d2
*
* Planar to packed conversion:
* vzip.8 d0, d2
* vzip.8 d1, d3
* vzip.8 d2, d3
* vzip.8 d0, d1
*
* But pixel can be loaded directly in planar format using VLD4.8 NEON
* instruction. It is 1 cycle slower than VLD1.32, so this is not always
* desirable, that's why deinterleaving is optional.
*
* But anyway, here is the code:
*/
/*
* OK, now we got almost everything that we need. Using the above two
* macros, the work can be done right. But now we want to optimize
* it a bit. ARM Cortex-A8 is an in-order core, and benefits really
* a lot from good code scheduling and software pipelining.
*
* Let's construct some code, which will run in the core main loop.
* Some pseudo-code of the main loop will look like this:
* head
* while (...) {
* tail
* head
* }
* tail
*
* It may look a bit weird, but this setup allows to hide instruction
* latencies better and also utilize dual-issue capability more
* efficiently (make pairs of load-store and ALU instructions).
*
* So what we need now is a '*_tail_head' macro, which will be used
* in the core main loop. A trivial straightforward implementation
* of this macro would look like this:
*
* pixman_composite_over_8888_0565_process_pixblock_tail
* vst1.16 {d28, d29}, [DST_W, :128]!
* vld1.16 {d4, d5}, [DST_R, :128]!
* vld4.32 {d0, d1, d2, d3}, [SRC]!
* pixman_composite_over_8888_0565_process_pixblock_head
* cache_preload 8, 8
*
* Now it also got some VLD/VST instructions. We simply can't move from
* processing one block of pixels to the other one with just arithmetics.
* The previously processed data needs to be written to memory and new
* data needs to be fetched. Fortunately, this main loop does not deal
* with partial leading/trailing pixels and can load/store a full block
* of pixels in a bulk. Additionally, destination buffer is already
* 16 bytes aligned here (which is good for performance).
*
* New things here are DST_R, DST_W, SRC and MASK identifiers. These
* are the aliases for ARM registers which are used as pointers for
* accessing data. We maintain separate pointers for reading and writing
* destination buffer (DST_R and DST_W).
*
* Another new thing is 'cache_preload' macro. It is used for prefetching
* data into CPU L2 cache and improve performance when dealing with large
* images which are far larger than cache size. It uses one argument
* (actually two, but they need to be the same here) - number of pixels
* in a block. Looking into 'pixman-arm-neon-asm.h' can provide some
* details about this macro. Moreover, if good performance is needed
* the code from this macro needs to be copied into '*_tail_head' macro
* and mixed with the rest of code for optimal instructions scheduling.
* We are actually doing it below.
*
* Now after all the explanations, here is the optimized code.
* Different instruction streams (originaling from '*_head', '*_tail'
* and 'cache_preload' macro) use different indentation levels for
* better readability. Actually taking the code from one of these
* indentation levels and ignoring a few VLD/VST instructions would
* result in exactly the code from '*_head', '*_tail' or 'cache_preload'
* macro!
*/
/*
* And now the final part. We are using 'generate_composite_function' macro
* to put all the stuff together. We are specifying the name of the function
* which we want to get, number of bits per pixel for the source, mask and
* destination (0 if unused, like mask in this case). Next come some bit
* flags:
* FLAG_DST_READWRITE - tells that the destination buffer is both read
* and written, for write-only buffer we would use
* FLAG_DST_WRITEONLY flag instead
* FLAG_DEINTERLEAVE_32BPP - tells that we prefer to work with planar data
* and separate color channels for 32bpp format.
* The next things are:
* - the number of pixels processed per iteration (8 in this case, because
* that's the maximum what can fit into four 64-bit NEON registers).
* - prefetch distance, measured in pixel blocks. In this case it is 5 times
* by 8 pixels. That would be 40 pixels, or up to 160 bytes. Optimal
* prefetch distance can be selected by running some benchmarks.
*
* After that we specify some macros, these are 'default_init',
* 'default_cleanup' here which are empty (but it is possible to have custom
* init/cleanup macros to be able to save/restore some extra NEON registers
* like d8-d15 or do anything else) followed by
* 'pixman_composite_over_8888_0565_process_pixblock_head',
* 'pixman_composite_over_8888_0565_process_pixblock_tail' and
* 'pixman_composite_over_8888_0565_process_pixblock_tail_head'
* which we got implemented above.
*
* The last part is the NEON registers allocation scheme.
*/
/******************************************************************************/
/******************************************************************************/
.macro pixman_composite_out_reverse_8888_8888_process_pixblock_head
vmvn.8 d24, d3 /* get inverted alpha */
/* do alpha blending */
vmull.u8 q8, d24, d4
vmull.u8 q9, d24, d5
vmull.u8 q10, d24, d6
vmull.u8 q11, d24, d7
.endm
.macro pixman_composite_out_reverse_8888_8888_process_pixblock_tail
vrshr.u16 q14, q8, #8
vrshr.u16 q15, q9, #8
vrshr.u16 q12, q10, #8
vrshr.u16 q13, q11, #8
vraddhn.u16 d28, q14, q8
vraddhn.u16 d29, q15, q9
vraddhn.u16 d30, q12, q10
vraddhn.u16 d31, q13, q11
.endm
/******************************************************************************/
.macro pixman_composite_over_8888_8888_process_pixblock_head
pixman_composite_out_reverse_8888_8888_process_pixblock_head
.endm
.macro pixman_composite_over_8888_8888_process_pixblock_tail
pixman_composite_out_reverse_8888_8888_process_pixblock_tail
vqadd.u8 q14, q0, q14
vqadd.u8 q15, q1, q15
.endm
.macro pixman_composite_over_8888_8888_process_pixblock_tail_head
vld4.8 {d4, d5, d6, d7}, [DST_R, :128]!
vrshr.u16 q14, q8, #8
PF add PF_X, PF_X, #8
PF tst PF_CTL, #0xF
vrshr.u16 q15, q9, #8
vrshr.u16 q12, q10, #8
vrshr.u16 q13, q11, #8
PF addne PF_X, PF_X, #8
PF subne PF_CTL, PF_CTL, #1
vraddhn.u16 d28, q14, q8
vraddhn.u16 d29, q15, q9
PF cmp PF_X, ORIG_W
vraddhn.u16 d30, q12, q10
vraddhn.u16 d31, q13, q11
vqadd.u8 q14, q0, q14
vqadd.u8 q15, q1, q15
fetch_src_pixblock
PF pld, [PF_SRC, PF_X, lsl #src_bpp_shift]
vmvn.8 d22, d3
PF pld, [PF_DST, PF_X, lsl #dst_bpp_shift]
vst4.8 {d28, d29, d30, d31}, [DST_W, :128]!
PF subge PF_X, PF_X, ORIG_W
vmull.u8 q8, d22, d4
PF subges PF_CTL, PF_CTL, #0x10
vmull.u8 q9, d22, d5
PF ldrgeb DUMMY, [PF_SRC, SRC_STRIDE, lsl #src_bpp_shift]!
vmull.u8 q10, d22, d6
PF ldrgeb DUMMY, [PF_DST, DST_STRIDE, lsl #dst_bpp_shift]!
vmull.u8 q11, d22, d7
.endm
generate_composite_function \
pixman_composite_over_8888_8888_asm_neon, 32, 0, 32, \
FLAG_DST_READWRITE | FLAG_DEINTERLEAVE_32BPP, \
8, /* number of pixels, processed in a single block */ \
5, /* prefetch distance */ \
default_init, \
default_cleanup, \
pixman_composite_over_8888_8888_process_pixblock_head, \
pixman_composite_over_8888_8888_process_pixblock_tail, \
pixman_composite_over_8888_8888_process_pixblock_tail_head
generate_composite_function_single_scanline \
pixman_composite_scanline_over_asm_neon, 32, 0, 32, \
FLAG_DST_READWRITE | FLAG_DEINTERLEAVE_32BPP, \
8, /* number of pixels, processed in a single block */ \
default_init, \
default_cleanup, \
pixman_composite_over_8888_8888_process_pixblock_head, \
pixman_composite_over_8888_8888_process_pixblock_tail, \
pixman_composite_over_8888_8888_process_pixblock_tail_head
/******************************************************************************/
.macro pixman_composite_over_n_8888_process_pixblock_head
/* deinterleaved source pixels in {d0, d1, d2, d3} */
/* inverted alpha in {d24} */
/* destination pixels in {d4, d5, d6, d7} */
vmull.u8 q8, d24, d4
vmull.u8 q9, d24, d5
vmull.u8 q10, d24, d6
vmull.u8 q11, d24, d7
.endm
.macro pixman_composite_over_n_8888_process_pixblock_tail
vrshr.u16 q14, q8, #8
vrshr.u16 q15, q9, #8
vrshr.u16 q2, q10, #8
vrshr.u16 q3, q11, #8
vraddhn.u16 d28, q14, q8
vraddhn.u16 d29, q15, q9
vraddhn.u16 d30, q2, q10
vraddhn.u16 d31, q3, q11
vqadd.u8 q14, q0, q14
vqadd.u8 q15, q1, q15
.endm
.macro pixman_composite_over_n_8888_process_pixblock_tail_head
vrshr.u16 q14, q8, #8
vrshr.u16 q15, q9, #8
vrshr.u16 q2, q10, #8
vrshr.u16 q3, q11, #8
vraddhn.u16 d28, q14, q8
vraddhn.u16 d29, q15, q9
vraddhn.u16 d30, q2, q10
vraddhn.u16 d31, q3, q11
vld4.8 {d4, d5, d6, d7}, [DST_R, :128]!
vqadd.u8 q14, q0, q14
PF add PF_X, PF_X, #8
PF tst PF_CTL, #0x0F
PF addne PF_X, PF_X, #8
PF subne PF_CTL, PF_CTL, #1
vqadd.u8 q15, q1, q15
PF cmp PF_X, ORIG_W
vmull.u8 q8, d24, d4
PF pld, [PF_DST, PF_X, lsl #dst_bpp_shift]
vmull.u8 q9, d24, d5
PF subge PF_X, PF_X, ORIG_W
vmull.u8 q10, d24, d6
PF subges PF_CTL, PF_CTL, #0x10
vmull.u8 q11, d24, d7
PF ldrgeb DUMMY, [PF_DST, DST_STRIDE, lsl #dst_bpp_shift]!
vst4.8 {d28, d29, d30, d31}, [DST_W, :128]!
.endm
.macro pixman_composite_over_n_8888_init
add DUMMY, sp, #ARGS_STACK_OFFSET
vld1.32 {d3[0]}, [DUMMY]
vdup.8 d0, d3[0]
vdup.8 d1, d3[1]
vdup.8 d2, d3[2]
vdup.8 d3, d3[3]
vmvn.8 d24, d3 /* get inverted alpha */
.endm
generate_composite_function \
pixman_composite_over_n_8888_asm_neon, 0, 0, 32, \
FLAG_DST_READWRITE | FLAG_DEINTERLEAVE_32BPP, \
8, /* number of pixels, processed in a single block */ \
5, /* prefetch distance */ \
pixman_composite_over_n_8888_init, \
default_cleanup, \
pixman_composite_over_8888_8888_process_pixblock_head, \
pixman_composite_over_8888_8888_process_pixblock_tail, \
pixman_composite_over_n_8888_process_pixblock_tail_head
/******************************************************************************/
.macro pixman_composite_src_n_8888_process_pixblock_head
.endm
.macro pixman_composite_src_n_8888_process_pixblock_tail
.endm
.macro pixman_composite_src_n_8888_process_pixblock_tail_head
vst1.32 {d0, d1, d2, d3}, [DST_W, :128]!
.endm
.macro pixman_composite_src_n_8888_init
add DUMMY, sp, #ARGS_STACK_OFFSET
vld1.32 {d0[0]}, [DUMMY]
vsli.u64 d0, d0, #32
vorr d1, d0, d0
vorr q1, q0, q0
.endm
.macro pixman_composite_src_n_8888_cleanup
.endm
generate_composite_function \
pixman_composite_src_n_8888_asm_neon, 0, 0, 32, \
FLAG_DST_WRITEONLY, \
8, /* number of pixels, processed in a single block */ \
0, /* prefetch distance */ \
pixman_composite_src_n_8888_init, \
pixman_composite_src_n_8888_cleanup, \
pixman_composite_src_n_8888_process_pixblock_head, \
pixman_composite_src_n_8888_process_pixblock_tail, \
pixman_composite_src_n_8888_process_pixblock_tail_head, \
0, /* dst_w_basereg */ \
0, /* dst_r_basereg */ \
0, /* src_basereg */ \
0 /* mask_basereg */
/******************************************************************************/
.macro pixman_composite_src_8888_8888_process_pixblock_head
.endm
.macro pixman_composite_src_8888_8888_process_pixblock_tail
.endm
.macro pixman_composite_src_8888_8888_process_pixblock_tail_head
vst1.32 {d0, d1, d2, d3}, [DST_W, :128]!
fetch_src_pixblock
cache_preload 8, 8
.endm
generate_composite_function \
pixman_composite_src_8888_8888_asm_neon, 32, 0, 32, \
FLAG_DST_WRITEONLY, \
8, /* number of pixels, processed in a single block */ \
10, /* prefetch distance */ \
default_init, \
default_cleanup, \
pixman_composite_src_8888_8888_process_pixblock_head, \
pixman_composite_src_8888_8888_process_pixblock_tail, \
pixman_composite_src_8888_8888_process_pixblock_tail_head, \
0, /* dst_w_basereg */ \
0, /* dst_r_basereg */ \
0, /* src_basereg */ \
0 /* mask_basereg */
/******************************************************************************/
|
aggresss/RFDemo
| 33,817
|
Code/start.S
|
/*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <rt_mmap.h>
#define SDRAM_CFG0_REG RALINK_SYSCTL_BASE + 0x0300
#define SDRAM_CFG1_REG RALINK_SYSCTL_BASE + 0x0304
#define SDRAM_CFG0_ALWAYS_ONE ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_START ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_DONE ( 1 << 30)
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
.set noreorder
.globl _start
.text
_start:
RVECENT(reset,0) /* U-boot entry point */
RVECENT(reset,1) /* software reboot */
#if defined(CONFIG_INCA_IP)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word 0x00000000 /* phase of the flash */
#elif defined(CONFIG_PURPLE)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
#else
RVECENT(romReserved,2)
#endif
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
/* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
#ifdef CONFIG_PURPLE
/* 0xbfc00400 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
reset:
#if defined (RT2883_FPGA_BOARD) || defined (RT2883_ASIC_BOARD) || \
defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD) || \
defined (RT3883_FPGA_BOARD) || defined (RT3883_ASIC_BOARD) || \
defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD)
# Initialize the register file
# should not be required with good software practices
or $1,$0, $0
or $2,$0, $0
or $3,$0, $0
or $4,$0, $0
or $5,$0, $0
or $6,$0, $0
or $7,$0, $0
or $8,$0, $0
or $9,$0, $0
or $10,$0, $0
or $11,$0, $0
or $12,$0, $0
or $13,$0, $0
or $14,$0, $0
or $15,$0, $0
or $16,$0, $0
or $17,$0, $0
or $18,$0, $0
or $19,$0, $0
or $20,$0, $0
or $21,$0, $0
or $22,$0, $0
or $23,$0, $0
or $24,$0, $0
or $25,$0, $0
or $26,$0, $0
or $27,$0, $0
or $28,$0, $0
or $29,$0, $0
or $30,$0, $0
or $31,$0, $0
# Initialize Misc. Cop0 state
# Read status register
mfc0 $10, $12
# Set up Status register:
# Disable Coprocessor Usable bits
# Turn off Reduce Power bit
# Turn off reverse endian
# Turn off BEV (use normal exception vectors)
# Clear TS, SR, NMI bits
# Clear Interrupt masks
# Clear User Mode
# Clear ERL
# Set EXL
# Clear Interrupt Enable
# modify by Bruce
#li $11, 0x0000ff02
li $11, 0x00000004
mtc0 $11, $12
# Disable watch exceptions
mtc0 $0, $18
# Clear Watch Status bits
li $11, 0x3
mtc0 $11, $19
# Clear WP bit to avoid watch exception upon user code entry
# Clear IV bit - Interrupts go to general exception vector
# Clear software interrupts
mtc0 $0, $13
# Set KSeg0 to cacheable
# Config.K0
mfc0 $10, $16
li $11, 0x7
not $11
and $10, $11
or $10, 0x3
mtc0 $10, $16
# Clear Count register
mtc0 $0, $9
# Set compare to -1 to delay 1st count=compare
# Also, clears timer interrupt
li $10, -1
mtc0 $10, $11
# Cache initialization routine
# Long and needed on HW
# Can be skipped if using magic simulation cache flush
# Determine how big the I$ is
/*
************************************************************************
* C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| MMU Size | IS | IL | IA | DS | DL | DA |Rsvd |W|C|E|F| Config1
* | | | | | | | | | |R|A|P|P|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 1 # .word 0x400a8001
# Isolate I$ Line Size
sll $11, $10, 10
srl $11, 29
# Skip ahead if No I$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true I$ line size in bytes
sll $12, $10, 7
srl $12, 29
li $14, 64
sllv $12, $14, $12 # I$ Sets per way
sll $13, $10, 13
srl $13, 29 # I$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x8, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
# Now go through and invalidate the D$
# Now that the I$ has been flushed, the rest of the code can be
# moved to kseg0 and run from the cache to go faster
10:
# Isolate D$ Line Size
sll $11, $10, 19
srl $11, 29
# Skip ahead if No D$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true D$ line size in bytes
sll $12, $10, 16
srl $12, 29
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
sll $13, $10, 22
srl $13, 29 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
mtc0 $0, $28, 2
mtc0 $0, $29, 2
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x9, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
#
# Now go through and initialize the L2$
10:
# Check L2 cache size
/*
************************************************************************
* C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| TU | TS | TL | TA | SU | SS | SL | SA | Config2
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 2
# Isolate L2$ Line Size
sll $11, $10, 24
srl $11, 28
# Skip ahead if No L2$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true L2$ line size in bytes
# Isolate L2$ Sets per Way
sll $12, $10, 20
srl $12, 28
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
# Isolate L2$ Associativity
sll $13, $10, 28
srl $13, 28 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear L23TagLo/L23TagHi registers
mtc0 $0, $28, 4
mtc0 $0, $29, 4
move $15, $12
# L2$ Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0xB, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
10:
# Determine if we have a TLB
mfc0 $11, $16
sll $11, 22
srl $11, 29
li $15, 0x1 # MT = 1 => TLB
bne $11, $15, 15f
nop
mfc0 $10, $16, 1 # .word 0x400a8001
sll $11, $10, 1
srl $11, 26 # Number of TLB entries (-1)
mtc0 $0, $2 # EntryLo0
mtc0 $0, $3 # EntryLo1
mtc0 $0, $5 # PageMask
mtc0 $0, $6 # Wired
li $12, 0x80000000
1:
mtc0 $11, $0 # Index register
mtc0 $12, $10 # EntryHi
ssnop #.word 0x00000040
ssnop #.word 0x00000040
TLBWI
add $12, (2<<13) # Add 8K to the address to avoid TLB conflict with previous entry
bne $11, $0, 1b
add $11, -1
15:
#endif
#if defined(RT3350_ASIC_BOARD)
// force SDRAM_MD_DRV and SDRAM_MA_DRV from 8mA --> 4mA
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
or t1, t1, (3 << 4)
sw t1, 0(t0)
nop
#endif
#if (TEXT_BASE == 0xBFC00000) || (TEXT_BASE == 0xBF000000) || (TEXT_BASE == 0xBC000000)
/* SDR and DDR initialization: delay 200us
*/
li t0, 0xFFFF
li t1, 0x1
1:
sub t0, t0, t1
bnez t0, 1b
nop
#if defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#if defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD)
/* Use default SYSCFG1 setting */
#else
/* DDR initialization: reg SYSCFG1[25:16]:
* ODT disabled, LVCMOS=1, half drive, turn ON RT3662 DDR IO ODT as 150 ohm when read DRAM
*/
li t1, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t1)
nop
and t2, ~(0x3FF<<16)
or t2, (0x361<<16)
sw t2, 0(t1)
nop
#endif
/* DDR initialization: reset pin to 0
*/
li t1, RALINK_SYSCTL_BASE + 0x34
sw zero, 0(t1)
nop
/* DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
*/
DDR_READY:
li t1, RALINK_MEMCTRL_BASE + 0x44 //DDR_CFG1
lw t0, 0(t1)
nop
and t2, t0, (1<<21)
beqz t2, DDR_READY
nop
/* DDR initialization:
*/
#if defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD)
/* fpga/asic: reg DDR_CFG2 -- set bit[30]=0 as DDR1 mode when DDR1
* fpga/asic: reg DDR_CFG2 -- set bit[30]=1 as DDR2 mode when DDR2
* fpga/asic: reg DDR_CFG2 -- set bit[6:4]=3'b011 when DDR1
* fpga/asic: reg DDR_CFG2 -- set bit[6:4]=3'b100 when DDR2
*/
li t1, RALINK_MEMCTRL_BASE + 0x48 //DDR_CFG2
lw t0, 0(t1)
nop
and t0, ~(1<<30)
#if ON_BOARD_DDR2
and t0, ~(7<<4)
or t0, (4<<4)
or t0, (1<<30)
#elif ON_BOARD_DDR1
and t0, ~(7<<4)
or t0, (3<<4)
#endif
sw t0, 0(t1)
nop
#endif /* defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD) */
/* RT3883 and RT6855 will share below setting, RT3352 no boot from NOR */
/*
* fpga: reg DDR_CFG3 -- disable DLL
* asic: reg DDR_CFG3 -- ODT enable (bit 6,2) = 2'b10 when 6855/3883 DDR2
* fpga/asic: reg DDR_CFG3 -- ODT enable (bit 6,2) = 2'b00 when 6855 DDR1
* fpga/asic: reg DDR_CFG3[10][5:3] = 4'b0000 when 6855 DDR1
*/
li t1, RALINK_MEMCTRL_BASE + 0x4c ////DDR_CFG3
lw t2, 0(t1)
#ifdef ON_BOARD_DDR2
#disable ODT; reference board ok, ev board fail
#and t2, ~(1<<6)
#enable ODT; both ok
or t2, (1<<6)
and t2, ~(1<<2)
#elif ON_BOARD_DDR1
and t2, ~(1<<10)
and t2, ~(7<<3)
#endif
#if defined(RT3883_FPGA_BOARD) || defined(RT6855_FPGA_BOARD)
or t2, 0x1
#endif
sw t2, 0(t1)
nop
#ifdef RALINK_DDR_OPTIMIZATION
/* DDR: set Burst Length=4 in 32 bits dram bus for better performance
* Burst Length=8 in non 32 bits dram bus
*/
li t0, RALINK_MEMCTRL_BASE + 0x48
lw t1, 0(t0)
nop
and t1, 0xffffff88
or t1, (CAS_VALUE<<CAS_OFFSET)
or t1, (BL_VALUE<<BL_OFFSET)
sw t1, 0(t0)
nop
li t0, RALINK_MEMCTRL_BASE + 0x4c
lw t1, 0(t0)
nop
and t1, 0xffffffc7
or t1, (AdditiveLatency_VALUE<<AdditiveLatency_OFFSET)
sw t1, 0(t0)
#endif
#if defined (RT3352_FPGA_BOARD) || defined (RT3883_FPGA_BOARD) || defined (RT6855_FPGA_BOARD)
/* DDR initialization: DDR_CFG0 bit 12:0 (refresh interval) to 0x64
* Note. this may have a bad affect on efficiency if the clock rate is 40MHz
*/
li t1, RALINK_MEMCTRL_BASE + 0x40
lw t2, 0(t1)
nop
and t2, ~(0xfff)
#if defined(ON_BOARD_DDR1) && defined(RT6855_FPGA_BOARD)
li t2, 0x21086141
#else
or t2, 0x64
#endif
sw t2, 0(t1)
nop
#endif
#if 0
/* data output (DQ) delay */
li t1, RALINK_MEMCTRL_BASE + 0x60
li t2, 0xffffffff
sw t2, 0(t1)
nop
li t1, RALINK_MEMCTRL_BASE + 0x64
li t2, 0xffffffff
sw t2, 0(t1)
nop
#endif
/* DDR initialization: config size and width on reg DDR_CFG1
*/
#if defined(RT6855_ASIC_BOARD)&&defined(ON_BOARD_DDR2)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x332A3525
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x332E3525
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x33323525
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x33363525
#else
DRAM Component not defined
#endif
#elif defined(RT6855_ASIC_BOARD)&&defined(ON_BOARD_DDR1)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x332A3525
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x332E3525
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x33323525
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x33363525
#else
DRAM Component not defined
#endif
#elif defined(RT6855_FPGA_BOARD)&&defined(ON_BOARD_DDR2)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x122A3121
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222e2323 //0x122E3121
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x12323121
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x12363121
#else
DRAM Component not defined
#endif
#elif defined(RT6855_FPGA_BOARD)&&defined(ON_BOARD_DDR1)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x122A3111
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222e2113 //0x122E3111
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x12323111
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x12363111
#else
DRAM Component not defined
#endif
#else /* RT3883 and RT3352 */
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x222A3323
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222E3323
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x22323323
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x22363323
#else
DRAM Component not defined
#endif
#endif /* end of setting DDR_CFG1 */
#ifdef ON_BOARD_DDR_WIDTH_16
or t6, (1<<17)
and t6, ~(1<<16)
#elif defined (ON_BOARD_DDR_WIDTH_8)
and t6, ~(1<<17)
or t6, (1<<16)
#else
DDR width not defined
#endif
/* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
and t6, ~(3<<12)
#ifdef ON_BOARD_32BIT_DRAM_BUS
or t6, (3<<12)
#elif defined (ON_BOARD_16BIT_DRAM_BUS)
or t6, (2<<12)
#else
DRAM bus not defined
#endif
li t5, RALINK_MEMCTRL_BASE + 0x44
sw t6, 0(t5)
nop
j SDRAM_INIT_DOWN
nop
#endif /* defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2) */
#ifdef ON_BOARD_SDR
SDR_INIT:
/* SDR initialization: SDRAM_CFG0
*/
li t5, SDRAM_CFG0_REG
lw t6, 0(t5)
nop
and t6, 0xF0000000
#ifdef FPGA_BOARD
#ifdef RT2880_FPGA_BOARD
#ifdef RT2880_MP
nop
or t6, 0x01825282
//or t6, 0x01815282
nop
#else /* RT2880_SHUTTLE */
or t6, 0x91825282
//or t6, 0x91815282
#endif
#elif defined(RT6855_FPGA_BOARD)
or t6, 0xD1825272
//or t6, 0xD1916292
#else //2883, 3052, 3352, 3883, 5350 fpga
nop
or t6, 0xD1825272
//or t6, 0x01815282
nop
#endif
#else //ASIC_BOARD
#if defined(RT6855_ASIC_BOARD)
or t6, 0xD1916292
#else
or t6, 0xD1825272
#endif
#endif
nop
sw t6, 0(t5)
nop
li t5, SDRAM_CFG1_REG
#ifdef ASIC_BOARD
/*
* Turn on SDRAM RBC (BIT 29 in SDRAM_CFG1, offset 0x4) in RT3052.
* RT2880 RBC bit is Reserved bit, and change the same value for RT2880 and RT3052
* Original 0x81xx0600 -> 0xa1xx0600
* by bobtseng, 2008.7.7.
*/
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t6, 0xa1010600
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t6, 0xa1110600
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0xa1120300
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0xa1220600
#elif defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6, 0xFEFFFFFF
or t6, (1<<24)
#elif defined ON_BOARD_16BIT_DRAM_BUS
and t6, 0xFEFFFFFF
#else
DRAM bus not defined
#endif
#else /* not ASIC_BOARD */
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t6, 0xa1010096
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t6, 0xa1110096
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0xa112004B
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0xa1220096
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6, 0xFEFFFFFF
or t6, (1<<24)
#elif defined (ON_BOARD_16BIT_DRAM_BUS)
and t6, 0xFEFFFFFF
#else
DRAM bus not defined
#endif
#endif
DO_SDRINIT:
nop
sw t6, 0(t5)
nop
WAIT_SDRAM_INIT_DOWN:
lw t6, 0(t5)
nop
and t6, t6, SDRAM_CFG1_SDRAM_INIT_DONE
beqz t6, WAIT_SDRAM_INIT_DOWN
nop
#endif // ON_BOARD_SDR //
SDRAM_INIT_DOWN:
#endif
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
#ifdef ON_BOARD_DDR2
#if (TEXT_BASE != 0xBFC00000) && (TEXT_BASE != 0xBF000000) && (TEXT_BASE != 0xBC000000)
/* DDR initialization: reg SYSCFG1[25:16]:
* ODT disabled, LVCMOS=1, half drive, turn ON RT3662 DDR IO ODT as 150 ohm when read DRAM
*/
li t1, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t1)
nop
and t2, ~(0x3FF<<16)
or t2, (0x361<<16)
sw t2, 0(t1)
nop
#endif
#endif
#endif
#ifdef RT3352_ASIC_BOARD
/* adjust the SW reg voltage level higher */
li t1, RALINK_SYSCTL_BASE + 0x88
li t2, 0xECC340
sw t2, 0(t1)
nop
/* set LDODIG 1.24V */
li t1, RALINK_SYSCTL_BASE + 0x8c
li t2, 0x9B82
sw t2, 0(t1)
nop
/*
* Enable spreading spectrum clock
* SSC_MODUMAG=7: +/-1.00% for center; -2.00% for down
*/
li t1, RALINK_SYSCTL_BASE + 0x54
li t2, 0x71
nop
sw t2, 0(t1)
#ifdef ON_BOARD_DDR2
#if 0
/* RT3352 EVB board with 32bits DDR shall enable this */
/* data output (DQ) delay */
li t1, RALINK_MEMCTRL_BASE + 0x60
li t2, 0xffffffff
sw t2, 0(t1)
nop
li t1, RALINK_MEMCTRL_BASE + 0x64
li t2, 0xffffffff
sw t2, 0(t1)
nop
#endif
#if 0
/* RT3352 EVB board with 16/32 bits DDR shall enable this */
/*
* DDR_PAD_DRV_1=00 (full drive)
* DDR_PAD_DS=0 (DDR2 differential RX application)
* DDR_PAD_LVCMO=0 (DDR default)
* DDR_PAD_DRV_0=00 (full drive)
*/
li t1, RALINK_SYSCTL_BASE + 0x14
and t2, ~(0x33F00000)
sw t2, 0(t1)
nop
#endif
#endif /* ON_BOARD_DDR2 */
#endif /* RT3352_ASIC_BOARD */
#if defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
/* get cpu frequency from SYSCFG0 bit 9:8, and adjust tRFC accordingly
*/
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
and t1, (0x3 << 8)
bne t1, (0x3 << 8), tRFC480
nop
/* DDR initialization: DDR_CFG0: adjust tRFC according to size and cpu clock
* for a better performance
* applied for both rom and ram version (SPI and NAND flash)
*/
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498E4F0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498E4F0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E4F0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x249924F0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249964F0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249924F0
#else
DRAM Component not defined
#endif
j tRFCinit
tRFC480:
bne t1, (0x2 << 8), tRFC250
nop
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498E4C0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498E4C0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E4C0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x249924C0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249964C0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249924C0
#else
DRAM Component not defined
#endif
j tRFCinit
tRFC250:
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498A3B0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498A3B0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498A3B0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x2499C3B0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249903B0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x2499A3B0
#else
DRAM Component not defined
#endif
#elif defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD)
#if defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E400
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x24992400
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x24996400
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249A2400
#else
DRAM Component not defined
#endif
#elif defined(RT6855_ASIC_BOARD)
#if defined(ON_BOARD_DDR1)
/* below 0x2419C640 is base on CLK = 200Mhz setting */
li t4, 0x2419C640
#endif /* defined(ON_BOARD_DDR1) */
#if defined(ON_BOARD_DDR2)
/* below 0x35AEA823 is base on CLK = 266Mhz setting */
li t4, 0x35AEA823
#endif /* defined(ON_BOARD_DDR2) */
#elif defined(RT6855_FPGA_BOARD)
#if defined(ON_BOARD_DDR1)
/* below 0x21086140 is base on CLK = 40Mhz setting */
li t4, 0x21086140
#endif /* defined(ON_BOARD_DDR1) */
#if defined(ON_BOARD_DDR2)
/* below 0x21090138 is base on CLK = 40Mhz setting */
li t4, 0x21090138
#endif /* defined(ON_BOARD_DDR2) */
/*
#elif defined(RT6855_FPGA_BOARD) || defined(RT6855_ASIC_BOARD)
#if defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E400
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x24992400
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x24996400
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249A2400
#else
DRAM Component not defined
#endif
*/
#endif // defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD) //
tRFCinit:
#if 0
li t3, RALINK_MEMCTRL_BASE + 0x40
sw t4, 0(t3)
nop
#endif
#if defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD)
#if defined(RALINK_DDR_POWERSAVE)
/* DDR: enable self auto refresh for power saving
* enable it by default for both RAM and ROM version (for CoC)
*/
li t0, RALINK_MEMCTRL_BASE + 0x1C
lw t1, 0(t0)
nop
and t1, 0xff000000
or t1, 0x01
sw t1, 0(t0)
nop
li t0, RALINK_MEMCTRL_BASE + 0x18
lw t1, 0(t0)
nop
or t1, 0x10
sw t1, 0(t0)
nop
#endif
#endif // defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) //
#else // SDR //
#if defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
#if defined(RALINK_SDR_POWERSAVE)
/* SDR:enable precharge power saving
*/
li t0, RALINK_MEMCTRL_BASE + 0x1C
lw t1, 0(t0)
nop
and t1, 0xff000000
or t1, 0x01
sw t1, 0(t0)
nop
li t0, RALINK_MEMCTRL_BASE + 0x04
lw t1, 0(t0)
nop
or t1, 0x10000000
sw t1, 0(t0)
nop
#endif // RALINK_MEMORY_POWER_SAVE //
#endif // defined(RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD)
#endif /* defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2) */
#if defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
#if defined (RALINK_CPU_AUTOFREQUENCY)
/* auto freq adjustment 3352,5350 support
*/
li t0, RALINK_SYSCTL_BASE + 0x44
li t1, 0x1f0112
sw t1, 0(t0)
nop
li t0, RALINK_SYSCTL_BASE + 0x3c
li t1, 0x3040101
sw t1, 0(t0)
nop
li t0, RALINK_SYSCTL_BASE + 0x40
li t1, 0x80035f41
sw t1, 0(t0)
nop
#endif
#endif // defined(RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) //
li t5, RALINK_SYSCTL_BASE + 0x0060
lw t6, 0(t5)
nop
or t6, 0x03
#if defined (RT2880_ASIC_BOARD) || defined (RT2880_FPGA_BOARD)
/* enable normal function i2c, spi, uartl, jtag, mdio, sdram */
and t6, ~(0x1<<0)
and t6, ~(0x1<<2)
and t6, ~(0x1<<3)
and t6, ~(0x1<<4)
and t6, ~(0x1<<5)
and t6, ~(0x1<<6)
#else
/* enable normal function i2c, spi, uartl, jtag, mdio, ge1 */
and t6, ~(0xf<<7)
and t6, ~(0x3<<5)
and t6, ~(0x3)
/* LNA_G_SHARE_MODE and LNA_A_SHARE_MODE at normal function, not GPIO mode */
and t6, ~(0xf<<16)
#endif
#if defined(RT3052_ASIC_BOARD) || defined(RT3352_ASIC_BOARD) || defined(RT6855_ASIC_BOARD)
#if defined(P5_MAC_TO_PHY_MODE)
//set mdio pin to normal mode
and t6, ~0x80
#else
//set mdio pin to gpio mode
or t6, 0x80
#endif
#if defined(ON_BOARD_16BIT_DRAM_BUS)
//set SDRAM pin to gpio mode
or t6, 0x100
#endif
#if defined(UARTF_AT_GPIO_FUNC)
//configure UARTF pin to gpio mode (GPIO7~GPIO14)
or t6, 0x1c
#endif
#endif
#ifdef MAC_TO_VITESSE_MODE
//set spi pin to normal mode
#if defined (RT2880_FGPA_BOARD) || defined (RT2880_ASIC_BOARD)
and t6, ~(1<<2)
#else
and t6, ~(1<<1)
#endif
#endif
#ifdef PCI_AT_GPIO_FUNC
or t6, 1<<7
#endif
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
//PCI share mode for NOR flash read/write
#if 0
//old PCI share mode: 3'b010
and t6, ~(7<<11)
or t6, 2<<11
#else
//new PCI share mode: 3'b011
and t6, ~(7<<11)
or t6, 3<<11
#endif
#endif
//set GPIOMODE
nop
sw t6, 0(t5)
nop
#ifdef PCI_AT_GPIO_FUNC
li t5, 0xa0300674
li t6, 0xffffffff
nop
sw t6,0(t5)
nop
li t5, 0xa0300670
li t6, 0xffffffff
nop
sw t6, 0(t5)
nop
#endif
//set all GPIO to output high
li t5, RALINK_PIO_BASE + 0x24
li t6, 0xffffbfff
nop
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x2C
li t6, 0xffffffff
nop
sw t6, 0(t5)
nop
#if defined(ON_BOARD_16BIT_DRAM_BUS)
//if sdram bus is 16bits,set gpio24~gpio39 to output high
li t5, RALINK_PIO_BASE + 0x4C
li t6, 0xffff
nop
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x54
li t6, 0xffff
nop
sw t6, 0(t5)
nop
#endif
#if defined(RT5350_ASIC_BOARD)
// set default LED polarity value for RT5350 REF board
// Active status:
// EPHY_LED0 H: Light
// EPHY_LED1 H: Light
// EPHY_LED2 H: Light
// EPHY_LED3 L: Light
// EPHY_LED4 H: Light
li t5, RALINK_ETH_SW_BASE + 0x168
li t6, 0x17
nop
sw t6, 0(t5)
nop
#endif
#if defined(RT2880_ASIC_BOARD)
//turn on power LED (GPIO 12)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<12
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<12
nop
sw t6, 0(t5)
nop
#elif defined(RT2883_ASIC_BOARD)
//turn on power LED (GPIO 8)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<8
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<8
nop
sw t6, 0(t5)
nop
#elif defined(RT3052_ASIC_BOARD)
//turn on power LED (GPIO 9)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<9
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<9
nop
sw t6, 0(t5)
nop
#elif defined(RT3352_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT5350_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT6855_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT3883_ASIC_BOARD)
//turn on power LED (GPIO ?)
#endif
/* config SYSCFG or SYSCFG1 register accordingly
*/
#if defined(RT2880_ASIC_BOARD) || defined(RT2880_FPGA_BOARD)
// Need to remap the vector memory to 0x0 if no memory there
li t0, RALINK_SYSCTL_BASE + 0x0010
li t1, 0x00C10084 //prefetch off
sw t1, 0(t0)
#endif
#if defined(RT2883_ASIC_BOARD) || defined(RT2883_FPGA_BOARD)
//set PCIe to RC mode
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
or t1, t1, (1 << 23)
sw t1, 0(t0)
nop
#endif
#if defined(RT3883_ASIC_BOARD) || defined(RT3883_FPGA_BOARD)
//FIXME: read from SYSCFG
li t0, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t0)
nop
and t2, ~(3 << 14) //GE2 to RGMII mode
and t2, ~(3 << 12) //GE1 to RGMII mode
or t2, (1 << 8) //PCIe to RC mode (for ethernet)
or t2, (1 << 7) //PCI to Host mode (for ethernet)
sw t2, 0(t0)
nop
#endif
#if defined(RT2880_FPGA_BOARD) || defined(RT2880_ASIC_BOARD)
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
/* Initialize caches...
*/
bal mips_cache_reset
nop
/* ... and enable them.
*/
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
#endif
/* Set up temporary stack.
*/
li a0, CFG_INIT_SP_OFFSET
//bal mips_cache_lock
nop
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
la sp, 0(t0)
/* Initialize GOT pointer.
*/
#if 0
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_ - 1f + 4
1:
move gp, ra
lw t1, 0(ra)
add gp, t1
#else
/* winfred: a easier way to get gp value so that mipsel-linux-as can
* assemble correctly without -mips_allow_branch_to_undefined flag
*/
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
lw gp, 0(ra)
#endif
la t9, board_init_f
j t9
nop
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
relocate_code:
move sp, a0 /* Set new stack pointer */
li t0, CFG_MONITOR_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
move t1, a2
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset */
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
/* On the purple board we copy the code earlier in a special way
* in order to solve flash problems
*/
#ifndef CONFIG_PURPLE
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
*/
/* Jump to where we've relocated ourselves.
*/
addi t0, a2, in_ram - _start
j t0
nop
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/* Now we want to update GOT.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
add t1, t6
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4 /* delay slot */
/* Clear BSS.
*/
lw t1, -12(t0) /* t1 <-- uboot_end_data */
lw t2, -8(t0) /* t2 <-- uboot_end */
add t1, t6 /* adjust pointers */
add t2, t6
sub t1, 4
1: addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
move a0, a1
la t9, board_init_r
j t9
move a1, a2 /* delay slot */
.end relocate_code
/* Exception handlers.
*/
romReserved:
b romReserved
romExcHandle:
b romExcHandle
|
aggresss/RFDemo
| 19,812
|
Code/Uboot/stage1/start.S
|
/*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <rt_mmap.h>
#define RT2880_LED_1 0x2
#define RT2880_LED_2 0x4
#define RT2880_LED_3 0x8
#define RT2880_LED_4 0x10
#define RT2880_LED_5 0x20
#define RT2880_LED_6 0x40
#define RT2880_LED_7 0x80
#define SDRAM_CFG0_REG RALINK_SYSCTL_BASE + 0x0300
#define SDRAM_CFG1_REG RALINK_SYSCTL_BASE + 0x0304
#define SDRAM_CFG0_ALWAYS_ONE ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_START ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_DONE ( 1 << 30)
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
#if 0 //DISCARD exception_vect
.section except_vect
except_vector:
RVECENT(reset,0) /* U-boot entry point */
RVECENT(reset,1) /* software reboot */
#if defined(CONFIG_INCA_IP)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word 0x00000000 /* phase of the flash */
#elif defined(CONFIG_PURPLE)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
#else
RVECENT(romReserved,2)
#endif
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
/* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
#ifdef CONFIG_PURPLE
/* 0xbfc00400 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
#endif //DISCARD exception sector
.set noreorder
.globl _start
.section .text
_start:
reset:
#if defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || defined (RT2883_ASIC_BOARD)
# Initialize the register file
# should not be required with good software practices
or $1,$0, $0
or $2,$0, $0
or $3,$0, $0
or $4,$0, $0
or $5,$0, $0
or $6,$0, $0
or $7,$0, $0
or $8,$0, $0
or $9,$0, $0
or $10,$0, $0
or $11,$0, $0
or $12,$0, $0
or $13,$0, $0
or $14,$0, $0
or $15,$0, $0
or $16,$0, $0
or $17,$0, $0
or $18,$0, $0
or $19,$0, $0
or $20,$0, $0
or $21,$0, $0
or $22,$0, $0
or $23,$0, $0
or $24,$0, $0
or $25,$0, $0
or $26,$0, $0
or $27,$0, $0
or $28,$0, $0
or $29,$0, $0
or $30,$0, $0
or $31,$0, $0
# Initialize Misc. Cop0 state
# Read status register
mfc0 $10, $12
# Set up Status register:
# Disable Coprocessor Usable bits
# Turn off Reduce Power bit
# Turn off reverse endian
# Turn off BEV (use normal exception vectors)
# Clear TS, SR, NMI bits
# Clear Interrupt masks
# Clear User Mode
# Clear ERL
# Set EXL
# Clear Interrupt Enable
# modify by Bruce
#li $11, 0x0000ff02
li $11, 0x00000004
mtc0 $11, $12
# Disable watch exceptions
mtc0 $0, $18
# Clear Watch Status bits
li $11, 0x3
mtc0 $11, $19
# Clear WP bit to avoid watch exception upon user code entry
# Clear IV bit - Interrupts go to general exception vector
# Clear software interrupts
mtc0 $0, $13
#if 0 // YT
# Set KSeg0 to cacheable
# Config.K0
mfc0 $10, $16
li $11, 0x7
not $11
and $10, $11
or $10, 0x3
mtc0 $10, $16
#endif //
# Clear Count register
mtc0 $0, $9
# Set compare to -1 to delay 1st count=compare
# Also, clears timer interrupt
li $10, -1
mtc0 $10, $11
#if 0 //disable cache
# Cache initialization routine
# Long and needed on HW
# Can be skipped if using magic simulation cache flush
# Determine how big the I$ is
/*
************************************************************************
* C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| MMU Size | IS | IL | IA | DS | DL | DA |Rsvd |W|C|E|F| Config1
* | | | | | | | | | |R|A|P|P|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 1 # .word 0x400a8001
# Isolate I$ Line Size
sll $11, $10, 10
srl $11, 29
# Skip ahead if No I$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true I$ line size in bytes
sll $12, $10, 7
srl $12, 29
li $14, 64
sllv $12, $14, $12 # I$ Sets per way
sll $13, $10, 13
srl $13, 29 # I$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x8, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
# Now go through and invalidate the D$
# Now that the I$ has been flushed, the rest of the code can be
# moved to kseg0 and run from the cache to go faster
10:
# Isolate D$ Line Size
sll $11, $10, 19
srl $11, 29
# Skip ahead if No D$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true D$ line size in bytes
sll $12, $10, 16
srl $12, 29
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
sll $13, $10, 22
srl $13, 29 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
mtc0 $0, $28, 2
mtc0 $0, $29, 2
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x9, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
#
# Now go through and initialize the L2$
10:
# Check L2 cache size
/*
************************************************************************
* C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| TU | TS | TL | TA | SU | SS | SL | SA | Config2
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 2
# Isolate L2$ Line Size
sll $11, $10, 24
srl $11, 28
# Skip ahead if No L2$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true L2$ line size in bytes
# Isolate L2$ Sets per Way
sll $12, $10, 20
srl $12, 28
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
# Isolate L2$ Associativity
sll $13, $10, 28
srl $13, 28 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear L23TagLo/L23TagHi registers
mtc0 $0, $28, 4
mtc0 $0, $29, 4
move $15, $12
# L2$ Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0xB, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
10:
# Determine if we have a TLB
mfc0 $11, $16
sll $11, 22
srl $11, 29
li $15, 0x1 # MT = 1 => TLB
bne $11, $15, 15f
nop
mfc0 $10, $16, 1 # .word 0x400a8001
sll $11, $10, 1
srl $11, 26 # Number of TLB entries (-1)
mtc0 $0, $2 # EntryLo0
mtc0 $0, $3 # EntryLo1
mtc0 $0, $5 # PageMask
mtc0 $0, $6 # Wired
li $12, 0x80000000
1:
mtc0 $11, $0 # Index register
mtc0 $12, $10 # EntryHi
ssnop #.word 0x00000040
ssnop #.word 0x00000040
TLBWI
add $12, (2<<13) # Add 8K to the address to avoid TLB conflict with previous entry
bne $11, $0, 1b
add $11, -1
#endif //disable cache
15:
#endif
/* delay cycle */
li t0,0xFFFF
li t1,0x1
1:
sub t0, t0, t1
bnez t0, 1b
/* end of delay cycle */
li t5,SDRAM_CFG0_REG
lw t6,0(t5)
nop
and t6,0xF0000000
#if defined (RT2880_FPGA_BOARD) || defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD)
#ifdef RT2880_FPGA_BOARD
#ifdef RT2880_MP
nop
or t6,0x01825282
//or t6,0x01815282
nop
#else /* RT2880_SHUTTLE */
or t6,0x91825282
//or t6,0x91815282
#endif
#else //2883, 3052 fpga
nop
or t6,0xD1825282
//or t6,0x01815282
nop
#endif
#else //RT2880_ASIC_BOARD, RT2883_ASIC_BOARD, RT3052_ASIC_BOARD
or t6,0xD1825272
#endif
nop
sw t6,0(t5)
nop
// justic whether SDRAM active
li t5,SDRAM_CFG1_REG
lw t6,0(t5)
nop
and t6, t6, SDRAM_CFG1_SDRAM_INIT_DONE
bnez t6, SDRAM_INIT_DONE
nop
nop
#if defined (RT2880_ASIC_BOARD) || defined (RT2883_ASIC_BOARD) || defined (RT3052_ASIC_BOARD)
#ifdef ON_BOARD_64M_DRAM_COMPONENT
//64Mbits sdram component
li t6,0xa1010600
#elif ON_BOARD_128M_DRAM_COMPONENT
//128Mbits sdram component
li t6,0xa1110600
#elif ON_BOARD_256M_DRAM_COMPONENT
//256Mbits sdram component
li t6,0xa1120600
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6,0xFEFFFFFF
or t6,(1<<24)
#elif ON_BOARD_16BIT_DRAM_BUS
and t6,0xFEFFFFFF
#else
DRAM bus not defined
#endif
#else
#ifdef ON_BOARD_64M_DRAM_COMPONENT
//64Mbits sdram component
li t6,0x81010096
#elif ON_BOARD_128M_DRAM_COMPONENT
//128Mbits sdram component
li t6,0x81110096
#elif ON_BOARD_256M_DRAM_COMPONENT
//256Mbits sdram component
li t6,0x81120096
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6,0xFEFFFFFF
or t6,(1<<24)
#elif ON_BOARD_16BIT_DRAM_BUS
and t6,0xFEFFFFFF
#else
DRAM bus not defined
#endif
#endif
nop
sw t6,0(t5)
nop
WAIT_SDRAM_INIT_DOWN:
lw t6,0(t5)
nop
and t6, t6, SDRAM_CFG1_SDRAM_INIT_DONE
beqz t6, WAIT_SDRAM_INIT_DOWN
nop
SDRAM_INIT_DONE:
li t5,RALINK_SYSCTL_BASE + 0x0060
li t6,0x3
#if defined(RT3052_ASIC_BOARD)
#if defined(P5_MAC_TO_PHY_MODE)
//set mdio pin to normal mode
and t6,~0x80
#else
//set mdio pin to gpio mode
or t6,0x80
#endif
//configure UARTF pin to gpio mode (GPIO7~GPIO14)
#if defined(UARTF_AT_GPIO_FUNC)
or t6,0x1c
#endif
#endif
#ifdef MAC_TO_VITESSE_MODE
and t6,~(1<<2)
#endif
#ifdef PCI_AT_GPIO_FUNC
or t6,1<<7
#endif
nop
sw t6,0(t5)
nop
#ifdef PCI_AT_GPIO_FUNC
li t5, 0xa0300674
li t6, 0xffffffff
nop
sw t6,0(t5)
nop
li t5, 0xa0300670
li t6, 0xffffffff
nop
sw t6,0(t5)
nop
#endif
//set all GPIO to output high
li t5, RALINK_PIO_BASE + 0x24
li t6, 0xffffbfff
nop
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x2C
li t6, 0xffffffff
nop
sw t6, 0(t5)
nop
#if defined(RT2880_ASIC_BOARD)
//turn on power LED (GPIO 12)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<12
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<12
nop
sw t6, 0(t5)
nop
#elif defined(RT3052_ASIC_BOARD)
//turn on power LED (GPIO 9)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<9
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<9
nop
sw t6, 0(t5)
nop
#endif
#if defined(RT2880_ASIC_BOARD) || defined(RT2880_FPGA_BOARD)
// Need to remap the vector memory to 0x0 if no memory there
li t0, RALINK_SYSCTL_BASE + 0x0010
li t1, 0x00C10084 //prefetch off
sw t1, 0(t0)
#endif
#if defined(RT3052_ASIC_BOARD) || defined(RT3052_FPGA_BOARD)|| defined(RT3050_FPGA_BOARD)|| defined(RT3050_ASIC_BOARD)
li t0,RALINK_SYSCTL_BASE + 0x10
lw t1,0(t0)
nop
and t1,t1,(1 << 18)
bne t1,zero,SYTEM_CLOCK_SET_384MHZ
nop
// Initialize Icache size to 16K
mfc0 t0, CP0_CONFIG
or t0,(1<<19)
mtc0 t0, CP0_CONFIG
nop
mfc0 t0, CP0_CONFIG,1
move t1 ,t0
and t0,~(0x7 << 22)
or t0,(1 <<22)
mtc0 t0, CP0_CONFIG,1
nop
mfc0 t0, CP0_CONFIG
and t0,~(1<<19)
mtc0 t0, CP0_CONFIG
nop
nop
SYTEM_CLOCK_SET_384MHZ:
#endif
#if defined(RT2880_FPGA_BOARD) || defined(RT2880_ASIC_BOARD)
/* CONFIG0 register */
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
#if 1
/* Initialize caches...
*/
bal mips_cache_reset
nop
/* ... and enable them.
#define CONF_CM_CACHABLE_NO_WA 0
#define CONF_CM_CACHABLE_WA 1
#define CONF_CM_UNCACHED 2
#define CONF_CM_CACHABLE_NONCOHERENT 3
#define CONF_CM_CACHABLE_CE 4
*/
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
#endif
#endif
/* Set up temporary stack.
*/
li a0, CFG_INIT_SP_OFFSET
//bal mips_cache_lock
nop
// li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
// la sp, 0(t0)
/* Initialize GOT pointer.
*/
#if 0
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_ - 1f + 4
1:
move gp, ra
lw t1, 0(ra)
add gp, t1
#else
/* winfred: a easier way to get gp value so that mipsel-linux-as can
* assemble correctly without -mips_allow_branch_to_undefined flag
*/
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
lw gp, 0(ra)
#endif
// relocate got entries
move t4, gp // <---- t4: current GP
la t3, _GLOBAL_OFFSET_TABLE_ // <---- t3: original GP
subu t1, t4, t3 // <---- t1: offset to relocate
beqz t1, toload_stage2 // <---- (t1 == 0) ?(no_relocate): (do_relocate)
nop
bal num_got
nop
.word num_got_entries
num_got:
lw t0, 0(ra) //number_got_entries
addi t4, 8 //skip first 2 enties
addiu t0, -2
blez t0, toload_stage2
nop
2: lw t2, 0(t4)
beqz t2, 3f
add t2, t1
sw t2, 0(t4)
3: addiu t0, -1
bgtz t0, 2b
addi t4, 4
toload_stage2:
.extern _fstack //this reference to stag2's stack.
la sp, TEXT_BASE - 8
.extern load_stage2
la t9, load_stage2
jal t9
nop
#if 0
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
relocate_code:
move sp, a0 /* Set new stack pointer */
li t0, CFG_MONITOR_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
move t1, a2
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset */
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
/* On the purple board we copy the code earlier in a special way
* in order to solve flash problems
*/
#ifndef CONFIG_PURPLE
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
*/
/* Jump to where we've relocated ourselves.
*/
addi t0, a2, in_ram - _start
j t0
nop
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/* Now we want to update GOT.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
add t1, t6
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4 /* delay slot */
/* Clear BSS.
*/
lw t1, -12(t0) /* t1 <-- uboot_end_data */
lw t2, -8(t0) /* t2 <-- uboot_end */
add t1, t6 /* adjust pointers */
add t2, t6
sub t1, 4
1: addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
move a0, a1
la t9, board_init_r
j t9
move a1, a2 /* delay slot */
.end relocate_code
/* Exception handlers.
*/
#endif //COFNIG_STAGE1
romReserved:
b romReserved
romExcHandle:
b romExcHandle
|
aggresss/RFDemo
| 5,948
|
Code/Uboot/board/rt2880/memsetup.S
|
/* FILE_DESC *****************************************************************
//
// Purpose:
// This file contains macros used for memory initialization.
//
// Sp. Notes:
//
// *****************************************************************************/
/*=====================*
* Include Files *
*=====================*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include "include/product.h"
#include "include/mem_map.h"
#include "include/mac.inc"
#include "include/chip_reg_map.h"
/*=====================*
* Defines *
*=====================*/
.set noreorder
// SDRAM Width
#ifdef USE_SDRAM
#ifdef SDRAM32
#define MAC_SDRAM_WIDTH (MAC_SDRAM_WIDTH_32)
#else
#ifdef SDRAM16
#define MAC_SDRAM_WIDTH (MAC_SDRAM_WIDTH_16)
#else
#error "SDRAM width not defined in makefile"
#endif
#endif
#endif
// SRAM Width
#if USE_SRAM
#if SRAM32
#define MAC_SRAM_WIDTH (MAC_WIDTH_32)
#else
#if SRAM16
#define MAC_SRAM_WIDTH (MAC_WIDTH_16)
#else
#error "SRAM width not defined in makefile"
#endif
#endif
#endif
// Configures the SRAM bank. Must be done
// before attempting SRAM reads or writes.
// Setup modedata with 2-clk cas latency, burst length = 4.
//
// Uses registers t0-t1.
//
#ifdef USE_SRAM
#define CONFIG_SRAM() \
\
li t0, MAC_SRAM_CONFIG_REG; \
li t1, ( (1 << MAC_ADDR2CS_SETUP_SHIFT) | \
(1 << MAC_WADDR_SETUP_SHIFT) | \
(1 << MAC_RADDR_SETUP_SHIFT) | \
(1 << MAC_WE_SHIFT) | \
(1 << MAC_OE_SHIFT) | \
(1 << MAC_WHOLD_SHIFT) | \
(1 << MAC_RHOLD_SHIFT) | \
(2 << MAC_BANKTYPE_SHIFT) | \
MAC_SRAM_WIDTH); \
sw t1, 0(t0);
#endif
// Configures the SDRAM bank. Must be done
// before attempting SDRAM reads or writes.
// Setup modedata with 2-clk cas latency, burst length = 4.
// Configure SDRAM2 bank identically.
//
// Uses registers t5-t7.
//
#ifdef USE_SDRAM
#define CONFIG_SDRAM() \
\
li t6, MAC_SDRAM_CONFIG_REG; \
li t7, MAC_SDRAM2_CONFIG_REG; \
j sdram_pgsize_board; \
nop ; \
\
sdram_pgsize_sim: \
li t5, (0 << MAC_PGSIZE_SHIFT); \
j sdram_pgsize_done; \
nop ; \
\
sdram_pgsize_board: \
li t5, (1 << MAC_PGSIZE_SHIFT); \
j sdram_pgsize_done; \
nop ; \
\
sdram_pgsize_done: \
or t5, ( (7 << MAC_REFR_SHIFT) | \
(0 << MAC_ACTIVE_SHIFT) | \
(0 << MAC_PRECHRG_SHIFT) | \
(1 << MAC_NUMROWADR_SHIFT) | \
(1 << MAC_PRECHGOPT_SHIFT) | \
(2 << MAC_PCABIT_SHIFT) | \
(MAC_BANKTYPE_SDRAM << MAC_BANKTYPE_SHIFT) | \
MAC_SDRAM_WIDTH); \
sw t5, 0(t6); \
sw t5, 0(t7); \
li t6, MAC_SDRAM_MODE_REG; \
li t7, MAC_SDRAM2_MODE_REG; \
li t5, ( (2 << MAC_MD_BURSTLEN_SHIFT) | \
(2 << MAC_MD_LATMODE_SHIFT)); \
sw t5, 0(t6); \
sw t5, 0(t7);
// Initializes SDRAM via the memory controller.
// Must be done before attempting to use SDRAM.
// Initializes SDRAM2 as well.
//
// Uses t4-t6.
//
#define INIT_SDRAM() \
\
/* Enable SDRAM Clock */ \
li t6, MAC_SDRAM_CNTL_REG; \
li t4, MAC_CTRL_SDRAMCLK; \
sw t4, 0(t6); \
\
/* Tell the MAC to initialize SDRAM */ \
add t5, t4, MAC_CTRL_SDRAMINI; \
sw t5, 0(t6); \
\
/* Wait for completion of initialization */ \
init_sdram_loop: \
lw t5, 0(t6); \
bne t5, t4, init_sdram_loop; \
nop; /* branch delay slot */ \
\
\
/* Enable SDRAM2 Clock */ \
li t6, MAC_SDRAM2_CNTL_REG; \
li t4, MAC_CTRL_SDRAMCLK; \
sw t4, 0(t6); \
\
/* Tell the MAC to initialize SDRAM2 */ \
add t5, t4, MAC_CTRL_SDRAMINI; \
sw t5, 0(t6); \
\
init_sdram2_loop: \
lw t5, 0(t6); \
bne t5, t4, init_sdram2_loop; \
nop; /* branch delay slot */ \
\
/* Initialize SDRAM Refresh Control register */ \
/* Setup refresh rate */ \
li t6, MAC_SDRAM_REFR_CNTL_REG; \
li t5, ((0x05F << MAC_REFRESH_RATE_SHIFT) | \
(1 << MAC_REFRESH_PRESCALE_SHIFT)); \
sw t5, 0(t6);
#endif
/*=====================*
* External Variables *
*=====================*/
/*=====================*
* External Functions *
*=====================*/
.globl memsetup
.ent memsetup
memsetup:
CONFIG_SDRAM()
INIT_SDRAM()
j ra
nop
.end memsetup
|
aggresss/RFDemo
| 6,127
|
Code/Uboot/board/rt2880/rt2880_init.S
|
/*=====================*
* Include Files *
*=====================*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include "include/sysc.h"
#include "include/product.h"
#include "include/mem_map.h"
#include "include/mac.inc"
#include "include/chip_reg_map.h"
#include "include/cpu.h"
/*=====================*
* Defines *
*=====================*/
.set noreorder
// Configures the SRAM bank. Must be done
// before attempting SRAM reads or writes.
// Setup modedata with 2-clk cas latency, burst length = 4.
//
// Uses registers t0-t1.
//
#ifdef USE_SRAM
#define CONFIG_SRAM() \
\
li t0, MAC_SRAM_CONFIG_REG; \
li t1, ( (1 << MAC_ADDR2CS_SETUP_SHIFT) | \
(1 << MAC_WADDR_SETUP_SHIFT) | \
(1 << MAC_RADDR_SETUP_SHIFT) | \
(1 << MAC_WE_SHIFT) | \
(1 << MAC_OE_SHIFT) | \
(1 << MAC_WHOLD_SHIFT) | \
(1 << MAC_RHOLD_SHIFT) | \
(2 << MAC_BANKTYPE_SHIFT) | \
MAC_SRAM_WIDTH); \
sw t1, 0(t0);
#endif
/*=====================*
* External Functions *
*=====================*/
.globl soc_init
.ent soc_init
soc_init:
//////////////////////////////////////////
// S T A R T P L L A N D / O R D L L
//////////////////////////////////////////
#ifdef CODE_IN_SDRAM
// If current code is in SDRAM, may have problems reading and executing
// the code if the DLL clock to the SDRAM is changed on the fly.
#else
#ifdef USE_DLL_INIT
// Must enable DLL before enabling PLL. PLL before DLL does not work.
// DLL_INVERT and DLL_PHASE are defined in product.h
li a0, SYSC_BASE
li a1, DLL_INVERT
li a2, DLL_PHASE
// Disable DLL
lw t1, 0x4c(a0) // DLL Cfg Reg : offset 0x4c
li t0, ~DLL_ENABLE
and t1, t1, t0
sw t1, 0x4c(a0)
// Setup Configuration
// cfg = ((uint32)a2 & DLL_PHASE_MASK) << DLL_PHASE_SHIFT;
// cfg |= a1 ? DLL_INVERT_SYSCLK : 0;
andi a2, a2, DLL_PHASE_MASK
sll a2, a2, DLL_PHASE_SHIFT
ori t0, a2, DLL_INVERT_SYSCLK
movn a2, t0, a1 // if (t) d=s
sw a2, 0x4c(a0)
// enable the DLL
lw t0, 0x4c(a0)
ori t0, t0, DLL_ENABLE
sw t0, 0x4c(a0)
// Wait until dll locked
1: lw t0, 0x50(a0) // DLL Stat Reg: offset 0x50
andi t0, t0, DLL_LOCKED
beqz t0, 1b
nop
#else
// Current graphite (rev 2) requires DLL_INVERT_SYSCLK bit to be
// cleared to access SDRAM
// For CODE_IN_SDRAM, bit is cleared by debugger startice.cmd file
li t0, DLL_CONFIG_REG
lw t1, 0(t0)
li t2, ~DLL_INVERT_SYSCLK
and t3, t1, t2
sw t3, 0(t0)
#endif
#endif
#ifdef USE_PLL_INIT
// PLL_DIV and PLL_MULT are defined in product.h
li a0, SYSC_BASE
li a1, (PLL_DIV - 1)
#ifdef USE_DLL_INIT
// Adjust for fact that system clock is divided by two when DLL enabled
li a2, ((PLL_MULT * 2) - 1) // branch delay slot
#else
li a2, (PLL_MULT - 1) // branch delay slot
#endif
//Put PLL control in its POR state. (bypass, ~enable, reset)
lw t0, 0x40(a0) // PLL Ctrl Reg: offset 0x40
ori t0, t0, PLL_BYPASS
sw t0, 0x40(a0)
li t0, PLL_BYPASS | PLL_RESET
sw t0, 0x40(a0)
// Setup configuration
andi a2, a2, PLL_FEEDBACK_NDIV_MASK
sll a2, a2, PLL_FEEDBACK_NDIV_SHIFT
andi a1,a1, PLL_REFCLK_MDIV_MASK
sll a1, a1, PLL_REFCLK_MDIV_SHIFT
or a1, a1, a2
sw a1, 0x44(a0) // PLL Cfg Reg: offset 0x44
// Enable the pll
// ** Must be done in two steps.
// ** Step 1: take pll out of reset state
// ** Step 2: enable pll
// Step 1:
lw t0, 0x40(a0)
li t1, ~PLL_RESET
and t0, t0, t1
sw t0, 0x40(a0)
// Step 2:
lw t0, 0x40(a0)
ori t0, t0, PLL_ENABLE
sw t0, 0x40(a0)
// Wait until pll locked before selecting pll as system clock
1: lw t0, 0x48(a0) // PLL Stat Reg: offset 0x48
andi t0, t0, PLL_LOCKED
beqz t0, 1b
nop
// Select pll clock for system clock
lw t0, 0x40(a0)
li t1, ~PLL_BYPASS
and t0, t0, t1
sw t0,0x40(a0)
#endif
// Configure ROM Bank, which at power-up is initialized in its
// slowest mode.
// Use the current (POR) MAC_WIDTH value, since hardware should always
// have the correct ROM MAC_WIDTH as the POR value.
li t0, MAC_ROM_CONFIG_REG
lw t2, 0(t0)
andi t2, (MAC_WIDTH_MASK << MAC_WIDTH_SHIFT)
#if 0 // DEBUG - ROM set for fastest access
li t1, ( (1 << MAC_BYTE_EN_SHIFT) | \
(1 << MAC_ADDR2CS_SETUP_SHIFT) | \
(1 << MAC_WADDR_SETUP_SHIFT) | \
(1 << MAC_RADDR_SETUP_SHIFT) | \
(1 << MAC_WE_SHIFT) | \
(1 << MAC_OE_SHIFT) | \
(1 << MAC_WHOLD_SHIFT) | \
(1 << MAC_RHOLD_SHIFT) | \
(2 << MAC_BANKTYPE_SHIFT) )
#else // DEBUG - ROM set for slowest access
li t1, ( (0x1 << MAC_BYTE_EN_SHIFT) | \
(0x3 << MAC_ADDR2CS_SETUP_SHIFT) | \
(0x3 << MAC_WADDR_SETUP_SHIFT) | \
(0x3 << MAC_RADDR_SETUP_SHIFT) | \
(0xF << MAC_WE_SHIFT) | \
(0xF << MAC_OE_SHIFT) | \
(0x3 << MAC_WHOLD_SHIFT) | \
(0x3 << MAC_RHOLD_SHIFT) | \
(0x2 << MAC_BANKTYPE_SHIFT) )
#endif
or t1, t2
sw t1, 0(t0)
#ifdef USE_SRAM
CONFIG_SRAM()
#endif
/////////////////////////////
// I N I T P A L M P A K
/////////////////////////////
#ifdef REMAPPED_VECTOR_MEM
// Need to remap the vector memory to 0x0 if no memory there
li t0, CPU_CONFIG_REG
lw t1, 0(t0)
ori t1, REMAP_VECTMEM
sw t1, 0(t0)
#endif
#ifdef REMAPPED_SDRAM
// -OR- remap the first 2MB of sdram to 0x0
// NOTE: If both REMAPPED_VECTOR_MEM and REMAPPED_SDRAM are defined,
// software can setup for both, but hardware will give vector_mem
// precedence and remap it to 0x0.
li t0, CPU_CONFIG_REG
lw t1, 0(t0)
ori t1, REMAP_SDRAM2VEC
sw t1, 0(t0)
kaiker
#endif
j ra
nop
.end soc_init
|
aggresss/RFDemo
| 6,388
|
Code/Uboot/cpu/ralink_soc/cache.S
|
/*
* Cache-handling routined for MIPS 4K CPUs
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
/* 16KB is the maximum size of instruction and data caches on
* MIPS 4K.
*/
#define MIPS_MAX_CACHE_SIZE 0x4000
/*
* cacheop macro to automate cache operations
* first some helpers...
*/
#define _mincache(size, maxsize) \
bltu size,maxsize,9f ; \
move size,maxsize ; \
9:
#define _align(minaddr, maxaddr, linesize) \
.set noat ; \
subu AT,linesize,1 ; \
not AT ; \
and minaddr,AT ; \
addu maxaddr,-1 ; \
and maxaddr,AT ; \
.set at
/* general operations */
#define doop1(op1) \
cache op1,0(a0)
#define doop2(op1, op2) \
cache op1,0(a0) ; \
nop ; \
cache op2,0(a0)
/* specials for cache initialisation */
#define doop1lw(op1) \
lw zero,0(a0)
#define doop1lw1(op1) \
cache op1,0(a0) ; \
lw zero,0(a0) ; \
cache op1,0(a0)
#define doop121(op1,op2) \
cache op1,0(a0) ; \
nop; \
cache op2,0(a0) ; \
nop; \
cache op1,0(a0)
#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
.set noreorder ; \
10: doop##tag##ops ; \
bne minaddr,maxaddr,10b ; \
add minaddr,linesize ; \
.set reorder
/* finally the cache operation macros */
#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
_mincache(n, cacheSize); \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
/*******************************************************************************
*
* mips_cache_reset - low level initialisation of the primary caches
*
* This routine initialises the primary caches to ensure that they
* have good parity. It must be called by the ROM before any cached locations
* are used to prevent the possibility of data with bad parity being written to
* memory.
* To initialise the instruction cache it is essential that a source of data
* with good parity is available. This routine
* will initialise an area of memory starting at location zero to be used as
* a source of parity.
*
* RETURNS: N/A
*
*/
.globl mips_cache_reset
.ent mips_cache_reset
mips_cache_reset:
li t2, CFG_ICACHE_SIZE
li t3, CFG_DCACHE_SIZE
li t4, CFG_CACHELINE_SIZE
move t5, t4
#if 1
li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero.
*/
li a0, KSEG1
addu a1, a0, v0
2: sw zero, 0(a0)
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
sw zero, 16(a0)
sw zero, 20(a0)
sw zero, 24(a0)
sw zero, 28(a0)
addu a0, 32
bltu a0, a1, 2b
nop
#endif
/* Set invalid tag.
*/
mtc0 zero, CP0_TAGLO
/*
* The caches are probably in an indeterminate state,
* so we force good parity into them by doing an
* invalidate, load/fill, invalidate for each line.
*/
/* Assume bottom of RAM will generate good parity for the cache.
*/
li a0, K0BASE
move a2, t2 # icacheSize
move a3, t4 # icacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
nop
/* To support Orion/R4600, we initialise the data cache in 3 passes.
*/
/* 1: initialise dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
nop
/* 2: fill dcache.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,1lw,(dummy))
nop
/*
3: clear dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
nop
j ra
nop
nop
.end mips_cache_reset
/*******************************************************************************
*
* dcache_status - get cache status
*
* RETURNS: 0 - cache disabled; 1 - cache enabled
*
*/
.globl dcache_status
.ent dcache_status
dcache_status:
mfc0 v0, CP0_CONFIG
andi v0, v0, 1
j ra
.end dcache_status
/*******************************************************************************
*
* dcache_disable - disable cache
*
* RETURNS: N/A
*
*/
.globl dcache_disable
.ent dcache_disable
dcache_disable:
mfc0 t0, CP0_CONFIG
li t1, -8
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
j ra
.end dcache_disable
/*******************************************************************************
*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
*
* RETURNS: N/A
*
*/
#if defined(CONFIG_PURPLE)
# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
#else
# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock
mips_cache_lock:
j KAIKER_0
nop
nop
KAIKER_0:
li a1, K0BASE - CACHE_LOCK_SIZE
addu a0, a1
li a2, CACHE_LOCK_SIZE
li a3, CFG_CACHELINE_SIZE
move a1, a2
j KAIKER_1
nop
nop
KAIKER_1:
j KAIKER_11
nop
nop
KAIKER_11:
icacheop(a0,a1,a2,a3,0x1D)
j KAIKER_2
nop
nop
KAIKER_2:
j ra
.end mips_cache_lock
|
aggresss/RFDemo
| 33,902
|
Code/Uboot/cpu/ralink_soc/start.S
|
/*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <rt_mmap.h>
#define SDRAM_CFG0_REG RALINK_SYSCTL_BASE + 0x0300
#define SDRAM_CFG1_REG RALINK_SYSCTL_BASE + 0x0304
#define SDRAM_CFG0_ALWAYS_ONE ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_START ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_DONE ( 1 << 30)
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
.set noreorder
.globl _start
.text
_start:
RVECENT(reset,0) /* U-boot entry point */
RVECENT(reset,1) /* software reboot */
#if defined(CONFIG_INCA_IP)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word 0x00000000 /* phase of the flash */
#elif defined(CONFIG_PURPLE)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
#else
RVECENT(romReserved,2)
#endif
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
/* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
#ifdef CONFIG_PURPLE
/* 0xbfc00400 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
reset:
#if defined (RT2883_FPGA_BOARD) || defined (RT2883_ASIC_BOARD) || \
defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD) || \
defined (RT3883_FPGA_BOARD) || defined (RT3883_ASIC_BOARD) || \
defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD)
# Initialize the register file
# should not be required with good software practices
or $1,$0, $0
or $2,$0, $0
or $3,$0, $0
or $4,$0, $0
or $5,$0, $0
or $6,$0, $0
or $7,$0, $0
or $8,$0, $0
or $9,$0, $0
or $10,$0, $0
or $11,$0, $0
or $12,$0, $0
or $13,$0, $0
or $14,$0, $0
or $15,$0, $0
or $16,$0, $0
or $17,$0, $0
or $18,$0, $0
or $19,$0, $0
or $20,$0, $0
or $21,$0, $0
or $22,$0, $0
or $23,$0, $0
or $24,$0, $0
or $25,$0, $0
or $26,$0, $0
or $27,$0, $0
or $28,$0, $0
or $29,$0, $0
or $30,$0, $0
or $31,$0, $0
# Initialize Misc. Cop0 state
# Read status register
mfc0 $10, $12
# Set up Status register:
# Disable Coprocessor Usable bits
# Turn off Reduce Power bit
# Turn off reverse endian
# Turn off BEV (use normal exception vectors)
# Clear TS, SR, NMI bits
# Clear Interrupt masks
# Clear User Mode
# Clear ERL
# Set EXL
# Clear Interrupt Enable
# modify by Bruce
#li $11, 0x0000ff02
li $11, 0x00000004
mtc0 $11, $12
# Disable watch exceptions
mtc0 $0, $18
# Clear Watch Status bits
li $11, 0x3
mtc0 $11, $19
# Clear WP bit to avoid watch exception upon user code entry
# Clear IV bit - Interrupts go to general exception vector
# Clear software interrupts
mtc0 $0, $13
# Set KSeg0 to cacheable
# Config.K0
mfc0 $10, $16
li $11, 0x7
not $11
and $10, $11
or $10, 0x3
mtc0 $10, $16
# Clear Count register
mtc0 $0, $9
# Set compare to -1 to delay 1st count=compare
# Also, clears timer interrupt
li $10, -1
mtc0 $10, $11
# Cache initialization routine
# Long and needed on HW
# Can be skipped if using magic simulation cache flush
# Determine how big the I$ is
/*
************************************************************************
* C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| MMU Size | IS | IL | IA | DS | DL | DA |Rsvd |W|C|E|F| Config1
* | | | | | | | | | |R|A|P|P|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 1 # .word 0x400a8001
# Isolate I$ Line Size
sll $11, $10, 10
srl $11, 29
# Skip ahead if No I$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true I$ line size in bytes
sll $12, $10, 7
srl $12, 29
li $14, 64
sllv $12, $14, $12 # I$ Sets per way
sll $13, $10, 13
srl $13, 29 # I$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x8, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
# Now go through and invalidate the D$
# Now that the I$ has been flushed, the rest of the code can be
# moved to kseg0 and run from the cache to go faster
10:
# Isolate D$ Line Size
sll $11, $10, 19
srl $11, 29
# Skip ahead if No D$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true D$ line size in bytes
sll $12, $10, 16
srl $12, 29
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
sll $13, $10, 22
srl $13, 29 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
mtc0 $0, $28, 2
mtc0 $0, $29, 2
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x9, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
#
# Now go through and initialize the L2$
10:
# Check L2 cache size
/*
************************************************************************
* C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| TU | TS | TL | TA | SU | SS | SL | SA | Config2
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 2
# Isolate L2$ Line Size
sll $11, $10, 24
srl $11, 28
# Skip ahead if No L2$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true L2$ line size in bytes
# Isolate L2$ Sets per Way
sll $12, $10, 20
srl $12, 28
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
# Isolate L2$ Associativity
sll $13, $10, 28
srl $13, 28 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear L23TagLo/L23TagHi registers
mtc0 $0, $28, 4
mtc0 $0, $29, 4
move $15, $12
# L2$ Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0xB, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
10:
# Determine if we have a TLB
mfc0 $11, $16
sll $11, 22
srl $11, 29
li $15, 0x1 # MT = 1 => TLB
bne $11, $15, 15f
nop
mfc0 $10, $16, 1 # .word 0x400a8001
sll $11, $10, 1
srl $11, 26 # Number of TLB entries (-1)
mtc0 $0, $2 # EntryLo0
mtc0 $0, $3 # EntryLo1
mtc0 $0, $5 # PageMask
mtc0 $0, $6 # Wired
li $12, 0x80000000
1:
mtc0 $11, $0 # Index register
mtc0 $12, $10 # EntryHi
ssnop #.word 0x00000040
ssnop #.word 0x00000040
TLBWI
add $12, (2<<13) # Add 8K to the address to avoid TLB conflict with previous entry
bne $11, $0, 1b
add $11, -1
15:
#endif
#if defined(RT3350_ASIC_BOARD)
// force SDRAM_MD_DRV and SDRAM_MA_DRV from 8mA --> 4mA
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
or t1, t1, (3 << 4)
sw t1, 0(t0)
nop
#endif
#if (TEXT_BASE == 0xBFC00000) || (TEXT_BASE == 0xBF000000) || (TEXT_BASE == 0xBC000000)
/* SDR and DDR initialization: delay 200us
*/
li t0, 0xFFFF
li t1, 0x1
1:
sub t0, t0, t1
bnez t0, 1b
nop
#if defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#if defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD)
/* Use default SYSCFG1 setting */
#else
/* DDR initialization: reg SYSCFG1[25:16]:
* ODT disabled, LVCMOS=1, half drive, turn ON RT3662 DDR IO ODT as 150 ohm when read DRAM
*/
li t1, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t1)
nop
and t2, ~(0x3FF<<16)
or t2, (0x361<<16)
sw t2, 0(t1)
nop
#endif
/* DDR initialization: reset pin to 0
*/
li t1, RALINK_SYSCTL_BASE + 0x34
sw zero, 0(t1)
nop
/* DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
*/
DDR_READY:
li t1, RALINK_MEMCTRL_BASE + 0x44 //DDR_CFG1
lw t0, 0(t1)
nop
and t2, t0, (1<<21)
beqz t2, DDR_READY
nop
/* DDR initialization:
*/
#if defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD)
/* fpga/asic: reg DDR_CFG2 -- set bit[30]=0 as DDR1 mode when DDR1
* fpga/asic: reg DDR_CFG2 -- set bit[30]=1 as DDR2 mode when DDR2
* fpga/asic: reg DDR_CFG2 -- set bit[6:4]=3'b011 when DDR1
* fpga/asic: reg DDR_CFG2 -- set bit[6:4]=3'b100 when DDR2
*/
li t1, RALINK_MEMCTRL_BASE + 0x48 //DDR_CFG2
lw t0, 0(t1)
nop
and t0, ~(1<<30)
#if ON_BOARD_DDR2
and t0, ~(7<<4)
or t0, (4<<4)
or t0, (1<<30)
#elif ON_BOARD_DDR1
and t0, ~(7<<4)
or t0, (3<<4)
#endif
sw t0, 0(t1)
nop
#endif /* defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD) */
/* RT3883 and RT6855 will share below setting, RT3352 no boot from NOR */
/*
* fpga: reg DDR_CFG3 -- disable DLL
* asic: reg DDR_CFG3 -- ODT enable (bit 6,2) = 2'b10 when 6855/3883 DDR2
* fpga/asic: reg DDR_CFG3 -- ODT enable (bit 6,2) = 2'b00 when 6855 DDR1
* fpga/asic: reg DDR_CFG3[10][5:3] = 4'b0000 when 6855 DDR1
*/
li t1, RALINK_MEMCTRL_BASE + 0x4c ////DDR_CFG3
lw t2, 0(t1)
#ifdef ON_BOARD_DDR2
#disable ODT; reference board ok, ev board fail
#and t2, ~(1<<6)
#enable ODT; both ok
or t2, (1<<6)
and t2, ~(1<<2)
#elif ON_BOARD_DDR1
and t2, ~(1<<10)
and t2, ~(7<<3)
#endif
#if defined(RT3883_FPGA_BOARD) || defined(RT6855_FPGA_BOARD)
or t2, 0x1
#endif
sw t2, 0(t1)
nop
#ifdef RALINK_DDR_OPTIMIZATION
/* DDR: set Burst Length=4 in 32 bits dram bus for better performance
* Burst Length=8 in non 32 bits dram bus
*/
li t0, RALINK_MEMCTRL_BASE + 0x48
lw t1, 0(t0)
nop
and t1, 0xffffff88
or t1, (CAS_VALUE<<CAS_OFFSET)
or t1, (BL_VALUE<<BL_OFFSET)
sw t1, 0(t0)
nop
li t0, RALINK_MEMCTRL_BASE + 0x4c
lw t1, 0(t0)
nop
and t1, 0xffffffc7
or t1, (AdditiveLatency_VALUE<<AdditiveLatency_OFFSET)
sw t1, 0(t0)
#endif
#if defined (RT3352_FPGA_BOARD) || defined (RT3883_FPGA_BOARD) || defined (RT6855_FPGA_BOARD)
/* DDR initialization: DDR_CFG0 bit 12:0 (refresh interval) to 0x64
* Note. this may have a bad affect on efficiency if the clock rate is 40MHz
*/
li t1, RALINK_MEMCTRL_BASE + 0x40
lw t2, 0(t1)
nop
and t2, ~(0xfff)
#if defined(ON_BOARD_DDR1) && defined(RT6855_FPGA_BOARD)
li t2, 0x21086141
#else
or t2, 0x64
#endif
sw t2, 0(t1)
nop
#endif
#if 0
/* data output (DQ) delay */
li t1, RALINK_MEMCTRL_BASE + 0x60
li t2, 0xffffffff
sw t2, 0(t1)
nop
li t1, RALINK_MEMCTRL_BASE + 0x64
li t2, 0xffffffff
sw t2, 0(t1)
nop
#endif
/* DDR initialization: config size and width on reg DDR_CFG1
*/
#if defined(RT6855_ASIC_BOARD)&&defined(ON_BOARD_DDR2)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x332A3525
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x332E3525
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x33323525
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x33363525
#else
DRAM Component not defined
#endif
#elif defined(RT6855_ASIC_BOARD)&&defined(ON_BOARD_DDR1)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x332A3525
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x332E3525
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x33323525
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x33363525
#else
DRAM Component not defined
#endif
#elif defined(RT6855_FPGA_BOARD)&&defined(ON_BOARD_DDR2)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x122A3121
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222e2323 //0x122E3121
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x12323121
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x12363121
#else
DRAM Component not defined
#endif
#elif defined(RT6855_FPGA_BOARD)&&defined(ON_BOARD_DDR1)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x122A3111
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222e2113 //0x122E3111
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x12323111
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x12363111
#else
DRAM Component not defined
#endif
#else /* RT3883 and RT3352 */
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x222A3323
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222E3323
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x22323323
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x22363323
#else
DRAM Component not defined
#endif
#endif /* end of setting DDR_CFG1 */
#ifdef ON_BOARD_DDR_WIDTH_16
or t6, (1<<17)
and t6, ~(1<<16)
#elif defined (ON_BOARD_DDR_WIDTH_8)
and t6, ~(1<<17)
or t6, (1<<16)
#else
DDR width not defined
#endif
/* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
and t6, ~(3<<12)
#ifdef ON_BOARD_32BIT_DRAM_BUS
or t6, (3<<12)
#elif defined (ON_BOARD_16BIT_DRAM_BUS)
or t6, (2<<12)
#else
DRAM bus not defined
#endif
li t5, RALINK_MEMCTRL_BASE + 0x44
sw t6, 0(t5)
nop
j SDRAM_INIT_DOWN
nop
#endif /* defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2) */
#ifdef ON_BOARD_SDR
SDR_INIT:
/* SDR initialization: SDRAM_CFG0
*/
li t5, SDRAM_CFG0_REG
lw t6, 0(t5)
nop
and t6, 0xF0000000
#ifdef FPGA_BOARD
#ifdef RT2880_FPGA_BOARD
#ifdef RT2880_MP
nop
or t6, 0x01825282
//or t6, 0x01815282
nop
#else /* RT2880_SHUTTLE */
or t6, 0x91825282
//or t6, 0x91815282
#endif
#elif defined(RT6855_FPGA_BOARD)
or t6, 0xD1825272
//or t6, 0xD1916292
#else //2883, 3052, 3352, 3883, 5350 fpga
nop
or t6, 0xD1825272
//or t6, 0x01815282
nop
#endif
#else //ASIC_BOARD
#if defined(RT6855_ASIC_BOARD)
or t6, 0xD1916292
#else
or t6, 0xD1825272
#endif
#endif
nop
sw t6, 0(t5)
nop
li t5, SDRAM_CFG1_REG
#ifdef ASIC_BOARD
/*
* Turn on SDRAM RBC (BIT 29 in SDRAM_CFG1, offset 0x4) in RT3052.
* RT2880 RBC bit is Reserved bit, and change the same value for RT2880 and RT3052
* Original 0x81xx0600 -> 0xa1xx0600
* by bobtseng, 2008.7.7.
*/
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t6, 0xa1010600
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t6, 0xa1110600
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0xa1120300
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0xa1220600
#elif defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6, 0xFEFFFFFF
or t6, (1<<24)
#elif defined ON_BOARD_16BIT_DRAM_BUS
and t6, 0xFEFFFFFF
#else
DRAM bus not defined
#endif
#else /* not ASIC_BOARD */
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t6, 0xa1010096
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t6, 0xa1110096
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0xa112004B
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0xa1220096
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6, 0xFEFFFFFF
or t6, (1<<24)
#elif defined (ON_BOARD_16BIT_DRAM_BUS)
and t6, 0xFEFFFFFF
#else
DRAM bus not defined
#endif
#endif
DO_SDRINIT:
nop
sw t6, 0(t5)
nop
WAIT_SDRAM_INIT_DOWN:
lw t6, 0(t5)
nop
and t6, t6, SDRAM_CFG1_SDRAM_INIT_DONE
beqz t6, WAIT_SDRAM_INIT_DOWN
nop
#endif // ON_BOARD_SDR //
SDRAM_INIT_DOWN:
#endif
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
#ifdef ON_BOARD_DDR2
#if (TEXT_BASE != 0xBFC00000) && (TEXT_BASE != 0xBF000000) && (TEXT_BASE != 0xBC000000)
/* DDR initialization: reg SYSCFG1[25:16]:
* ODT disabled, LVCMOS=1, half drive, turn ON RT3662 DDR IO ODT as 150 ohm when read DRAM
*/
li t1, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t1)
nop
and t2, ~(0x3FF<<16)
or t2, (0x361<<16)
sw t2, 0(t1)
nop
#endif
#endif
#endif
#ifdef RT3352_ASIC_BOARD
/* adjust the SW reg voltage level higher */
li t1, RALINK_SYSCTL_BASE + 0x88
li t2, 0xECC340
sw t2, 0(t1)
nop
/* set LDODIG 1.24V */
li t1, RALINK_SYSCTL_BASE + 0x8c
li t2, 0x9B82
sw t2, 0(t1)
nop
/*
* Enable spreading spectrum clock
* SSC_MODUMAG=7: +/-1.00% for center; -2.00% for down
*/
li t1, RALINK_SYSCTL_BASE + 0x54
li t2, 0x71
nop
sw t2, 0(t1)
#ifdef ON_BOARD_DDR2
#if 0
/* RT3352 EVB board with 32bits DDR shall enable this */
/* data output (DQ) delay */
li t1, RALINK_MEMCTRL_BASE + 0x60
li t2, 0xffffffff
sw t2, 0(t1)
nop
li t1, RALINK_MEMCTRL_BASE + 0x64
li t2, 0xffffffff
sw t2, 0(t1)
nop
#endif
#if 0
/* RT3352 EVB board with 16/32 bits DDR shall enable this */
/*
* DDR_PAD_DRV_1=00 (full drive)
* DDR_PAD_DS=0 (DDR2 differential RX application)
* DDR_PAD_LVCMO=0 (DDR default)
* DDR_PAD_DRV_0=00 (full drive)
*/
li t1, RALINK_SYSCTL_BASE + 0x14
and t2, ~(0x33F00000)
sw t2, 0(t1)
nop
#endif
#endif /* ON_BOARD_DDR2 */
#endif /* RT3352_ASIC_BOARD */
#if defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
/* get cpu frequency from SYSCFG0 bit 9:8, and adjust tRFC accordingly
*/
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
and t1, (0x3 << 8)
bne t1, (0x3 << 8), tRFC480
nop
/* DDR initialization: DDR_CFG0: adjust tRFC according to size and cpu clock
* for a better performance
* applied for both rom and ram version (SPI and NAND flash)
*/
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498E4F0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498E4F0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E4F0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x249924F0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249964F0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249924F0
#else
DRAM Component not defined
#endif
j tRFCinit
tRFC480:
bne t1, (0x2 << 8), tRFC250
nop
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498E4C0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498E4C0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E4C0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x249924C0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249964C0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249924C0
#else
DRAM Component not defined
#endif
j tRFCinit
tRFC250:
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498A3B0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498A3B0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498A3B0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x2499C3B0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249903B0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x2499A3B0
#else
DRAM Component not defined
#endif
#elif defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD)
#if defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E400
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x24992400
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x24996400
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249A2400
#else
DRAM Component not defined
#endif
#elif defined(RT6855_ASIC_BOARD)
#if defined(ON_BOARD_DDR1)
/* below 0x2419C640 is base on CLK = 200Mhz setting */
li t4, 0x2419C640
#endif /* defined(ON_BOARD_DDR1) */
#if defined(ON_BOARD_DDR2)
/* below 0x35AEA823 is base on CLK = 266Mhz setting */
li t4, 0x35AEA823
#endif /* defined(ON_BOARD_DDR2) */
#elif defined(RT6855_FPGA_BOARD)
#if defined(ON_BOARD_DDR1)
/* below 0x21086140 is base on CLK = 40Mhz setting */
li t4, 0x21086140
#endif /* defined(ON_BOARD_DDR1) */
#if defined(ON_BOARD_DDR2)
/* below 0x21090138 is base on CLK = 40Mhz setting */
li t4, 0x21090138
#endif /* defined(ON_BOARD_DDR2) */
/*
#elif defined(RT6855_FPGA_BOARD) || defined(RT6855_ASIC_BOARD)
#if defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E400
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x24992400
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x24996400
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249A2400
#else
DRAM Component not defined
#endif
*/
#endif // defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD) //
tRFCinit:
#if 0
li t3, RALINK_MEMCTRL_BASE + 0x40
sw t4, 0(t3)
nop
#endif
#if defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD)
#if defined(RALINK_DDR_POWERSAVE)
/* DDR: enable self auto refresh for power saving
* enable it by default for both RAM and ROM version (for CoC)
*/
li t0, RALINK_MEMCTRL_BASE + 0x1C
lw t1, 0(t0)
nop
and t1, 0xff000000
or t1, 0x01
sw t1, 0(t0)
nop
li t0, RALINK_MEMCTRL_BASE + 0x18
lw t1, 0(t0)
nop
or t1, 0x10
sw t1, 0(t0)
nop
#endif
#endif // defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) //
#else // SDR //
#if defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
#if defined(RALINK_SDR_POWERSAVE)
/* SDR:enable precharge power saving
*/
li t0, RALINK_MEMCTRL_BASE + 0x1C
lw t1, 0(t0)
nop
and t1, 0xff000000
or t1, 0x01
sw t1, 0(t0)
nop
li t0, RALINK_MEMCTRL_BASE + 0x04
lw t1, 0(t0)
nop
or t1, 0x10000000
sw t1, 0(t0)
nop
#endif // RALINK_MEMORY_POWER_SAVE //
#endif // defined(RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD)
#endif /* defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2) */
#if defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
#if defined (RALINK_CPU_AUTOFREQUENCY)
/* auto freq adjustment 3352,5350 support
*/
li t0, RALINK_SYSCTL_BASE + 0x44
li t1, 0x1f0112
sw t1, 0(t0)
nop
li t0, RALINK_SYSCTL_BASE + 0x3c
li t1, 0x3040101
sw t1, 0(t0)
nop
li t0, RALINK_SYSCTL_BASE + 0x40
li t1, 0x80035f41
sw t1, 0(t0)
nop
#endif
#endif // defined(RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) //
li t5, RALINK_SYSCTL_BASE + 0x0060
lw t6, 0(t5)
nop
or t6, 0x03
#if defined (RT2880_ASIC_BOARD) || defined (RT2880_FPGA_BOARD)
/* enable normal function i2c, spi, uartl, jtag, mdio, sdram */
and t6, ~(0x1<<0)
and t6, ~(0x1<<2)
and t6, ~(0x1<<3)
and t6, ~(0x1<<4)
and t6, ~(0x1<<5)
and t6, ~(0x1<<6)
#else
/* enable normal function i2c, spi, uartl, jtag, mdio, ge1 */
and t6, ~(0xf<<7)
and t6, ~(0x3<<5)
and t6, ~(0x3)
/* LNA_G_SHARE_MODE and LNA_A_SHARE_MODE at normal function, not GPIO mode */
and t6, ~(0xf<<16)
/* disable I2C mode and turned to gpio mode, modify by agg */
or t6, 0x01<<1
#endif
#if defined(RT3052_ASIC_BOARD) || defined(RT3352_ASIC_BOARD) || defined(RT6855_ASIC_BOARD)
#if defined(P5_MAC_TO_PHY_MODE)
//set mdio pin to normal mode
and t6, ~0x80
#else
//set mdio pin to gpio mode
or t6, 0x80
#endif
#if defined(ON_BOARD_16BIT_DRAM_BUS)
//set SDRAM pin to gpio mode
or t6, 0x100
#endif
#if defined(UARTF_AT_GPIO_FUNC)
//configure UARTF pin to gpio mode (GPIO7~GPIO14)
or t6, 0x1c
#endif
#endif
#ifdef MAC_TO_VITESSE_MODE
//set spi pin to normal mode
#if defined (RT2880_FGPA_BOARD) || defined (RT2880_ASIC_BOARD)
and t6, ~(1<<2)
#else
and t6, ~(1<<1)
#endif
#endif
#ifdef PCI_AT_GPIO_FUNC
or t6, 1<<7
#endif
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
//PCI share mode for NOR flash read/write
#if 0
//old PCI share mode: 3'b010
and t6, ~(7<<11)
or t6, 2<<11
#else
//new PCI share mode: 3'b011
and t6, ~(7<<11)
or t6, 3<<11
#endif
#endif
//set GPIOMODE
nop
sw t6, 0(t5)
nop
#ifdef PCI_AT_GPIO_FUNC
li t5, 0xa0300674
li t6, 0xffffffff
nop
sw t6,0(t5)
nop
li t5, 0xa0300670
li t6, 0xffffffff
nop
sw t6, 0(t5)
nop
#endif
//set all GPIO to output high
li t5, RALINK_PIO_BASE + 0x24
li t6, 0xffffbfff
nop
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x2C
li t6, 0xffffffff
nop
sw t6, 0(t5)
nop
#if defined(ON_BOARD_16BIT_DRAM_BUS)
//if sdram bus is 16bits,set gpio24~gpio39 to output high
li t5, RALINK_PIO_BASE + 0x4C
li t6, 0xffff
nop
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x54
li t6, 0xffff
nop
sw t6, 0(t5)
nop
#endif
#if defined(RT5350_ASIC_BOARD)
// set default LED polarity value for RT5350 REF board
// Active status:
// EPHY_LED0 H: Light
// EPHY_LED1 H: Light
// EPHY_LED2 H: Light
// EPHY_LED3 L: Light
// EPHY_LED4 H: Light
li t5, RALINK_ETH_SW_BASE + 0x168
li t6, 0x17
nop
sw t6, 0(t5)
nop
#endif
#if defined(RT2880_ASIC_BOARD)
//turn on power LED (GPIO 12)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<12
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<12
nop
sw t6, 0(t5)
nop
#elif defined(RT2883_ASIC_BOARD)
//turn on power LED (GPIO 8)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<8
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<8
nop
sw t6, 0(t5)
nop
#elif defined(RT3052_ASIC_BOARD)
//turn on power LED (GPIO 9)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<9
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<9
nop
sw t6, 0(t5)
nop
#elif defined(RT3352_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT5350_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT6855_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT3883_ASIC_BOARD)
//turn on power LED (GPIO ?)
#endif
/* config SYSCFG or SYSCFG1 register accordingly
*/
#if defined(RT2880_ASIC_BOARD) || defined(RT2880_FPGA_BOARD)
// Need to remap the vector memory to 0x0 if no memory there
li t0, RALINK_SYSCTL_BASE + 0x0010
li t1, 0x00C10084 //prefetch off
sw t1, 0(t0)
#endif
#if defined(RT2883_ASIC_BOARD) || defined(RT2883_FPGA_BOARD)
//set PCIe to RC mode
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
or t1, t1, (1 << 23)
sw t1, 0(t0)
nop
#endif
#if defined(RT3883_ASIC_BOARD) || defined(RT3883_FPGA_BOARD)
//FIXME: read from SYSCFG
li t0, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t0)
nop
and t2, ~(3 << 14) //GE2 to RGMII mode
and t2, ~(3 << 12) //GE1 to RGMII mode
or t2, (1 << 8) //PCIe to RC mode (for ethernet)
or t2, (1 << 7) //PCI to Host mode (for ethernet)
sw t2, 0(t0)
nop
#endif
#if defined(RT2880_FPGA_BOARD) || defined(RT2880_ASIC_BOARD)
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
/* Initialize caches...
*/
bal mips_cache_reset
nop
/* ... and enable them.
*/
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
#endif
/* Set up temporary stack.
*/
li a0, CFG_INIT_SP_OFFSET
//bal mips_cache_lock
nop
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
la sp, 0(t0)
/* Initialize GOT pointer.
*/
#if 0
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_ - 1f + 4
1:
move gp, ra
lw t1, 0(ra)
add gp, t1
#else
/* winfred: a easier way to get gp value so that mipsel-linux-as can
* assemble correctly without -mips_allow_branch_to_undefined flag
*/
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
lw gp, 0(ra)
#endif
la t9, board_init_f
j t9
nop
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
relocate_code:
move sp, a0 /* Set new stack pointer */
li t0, CFG_MONITOR_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
move t1, a2
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset */
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
/* On the purple board we copy the code earlier in a special way
* in order to solve flash problems
*/
#ifndef CONFIG_PURPLE
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
*/
/* Jump to where we've relocated ourselves.
*/
addi t0, a2, in_ram - _start
j t0
nop
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/* Now we want to update GOT.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
add t1, t6
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4 /* delay slot */
/* Clear BSS.
*/
lw t1, -12(t0) /* t1 <-- uboot_end_data */
lw t2, -8(t0) /* t2 <-- uboot_end */
add t1, t6 /* adjust pointers */
add t2, t6
sub t1, 4
1: addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
move a0, a1
la t9, board_init_r
j t9
move a1, a2 /* delay slot */
.end relocate_code
/* Exception handlers.
*/
romReserved:
b romReserved
romExcHandle:
b romExcHandle
|
aggresss/RFDemo
| 19,812
|
Code/Uboot_httpd/stage1/start.S
|
/*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <rt_mmap.h>
#define RT2880_LED_1 0x2
#define RT2880_LED_2 0x4
#define RT2880_LED_3 0x8
#define RT2880_LED_4 0x10
#define RT2880_LED_5 0x20
#define RT2880_LED_6 0x40
#define RT2880_LED_7 0x80
#define SDRAM_CFG0_REG RALINK_SYSCTL_BASE + 0x0300
#define SDRAM_CFG1_REG RALINK_SYSCTL_BASE + 0x0304
#define SDRAM_CFG0_ALWAYS_ONE ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_START ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_DONE ( 1 << 30)
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
#if 0 //DISCARD exception_vect
.section except_vect
except_vector:
RVECENT(reset,0) /* U-boot entry point */
RVECENT(reset,1) /* software reboot */
#if defined(CONFIG_INCA_IP)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word 0x00000000 /* phase of the flash */
#elif defined(CONFIG_PURPLE)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
#else
RVECENT(romReserved,2)
#endif
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
/* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
#ifdef CONFIG_PURPLE
/* 0xbfc00400 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
#endif //DISCARD exception sector
.set noreorder
.globl _start
.section .text
_start:
reset:
#if defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || defined (RT2883_ASIC_BOARD)
# Initialize the register file
# should not be required with good software practices
or $1,$0, $0
or $2,$0, $0
or $3,$0, $0
or $4,$0, $0
or $5,$0, $0
or $6,$0, $0
or $7,$0, $0
or $8,$0, $0
or $9,$0, $0
or $10,$0, $0
or $11,$0, $0
or $12,$0, $0
or $13,$0, $0
or $14,$0, $0
or $15,$0, $0
or $16,$0, $0
or $17,$0, $0
or $18,$0, $0
or $19,$0, $0
or $20,$0, $0
or $21,$0, $0
or $22,$0, $0
or $23,$0, $0
or $24,$0, $0
or $25,$0, $0
or $26,$0, $0
or $27,$0, $0
or $28,$0, $0
or $29,$0, $0
or $30,$0, $0
or $31,$0, $0
# Initialize Misc. Cop0 state
# Read status register
mfc0 $10, $12
# Set up Status register:
# Disable Coprocessor Usable bits
# Turn off Reduce Power bit
# Turn off reverse endian
# Turn off BEV (use normal exception vectors)
# Clear TS, SR, NMI bits
# Clear Interrupt masks
# Clear User Mode
# Clear ERL
# Set EXL
# Clear Interrupt Enable
# modify by Bruce
#li $11, 0x0000ff02
li $11, 0x00000004
mtc0 $11, $12
# Disable watch exceptions
mtc0 $0, $18
# Clear Watch Status bits
li $11, 0x3
mtc0 $11, $19
# Clear WP bit to avoid watch exception upon user code entry
# Clear IV bit - Interrupts go to general exception vector
# Clear software interrupts
mtc0 $0, $13
#if 0 // YT
# Set KSeg0 to cacheable
# Config.K0
mfc0 $10, $16
li $11, 0x7
not $11
and $10, $11
or $10, 0x3
mtc0 $10, $16
#endif //
# Clear Count register
mtc0 $0, $9
# Set compare to -1 to delay 1st count=compare
# Also, clears timer interrupt
li $10, -1
mtc0 $10, $11
#if 0 //disable cache
# Cache initialization routine
# Long and needed on HW
# Can be skipped if using magic simulation cache flush
# Determine how big the I$ is
/*
************************************************************************
* C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| MMU Size | IS | IL | IA | DS | DL | DA |Rsvd |W|C|E|F| Config1
* | | | | | | | | | |R|A|P|P|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 1 # .word 0x400a8001
# Isolate I$ Line Size
sll $11, $10, 10
srl $11, 29
# Skip ahead if No I$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true I$ line size in bytes
sll $12, $10, 7
srl $12, 29
li $14, 64
sllv $12, $14, $12 # I$ Sets per way
sll $13, $10, 13
srl $13, 29 # I$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x8, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
# Now go through and invalidate the D$
# Now that the I$ has been flushed, the rest of the code can be
# moved to kseg0 and run from the cache to go faster
10:
# Isolate D$ Line Size
sll $11, $10, 19
srl $11, 29
# Skip ahead if No D$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true D$ line size in bytes
sll $12, $10, 16
srl $12, 29
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
sll $13, $10, 22
srl $13, 29 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
mtc0 $0, $28, 2
mtc0 $0, $29, 2
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x9, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
#
# Now go through and initialize the L2$
10:
# Check L2 cache size
/*
************************************************************************
* C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| TU | TS | TL | TA | SU | SS | SL | SA | Config2
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 2
# Isolate L2$ Line Size
sll $11, $10, 24
srl $11, 28
# Skip ahead if No L2$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true L2$ line size in bytes
# Isolate L2$ Sets per Way
sll $12, $10, 20
srl $12, 28
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
# Isolate L2$ Associativity
sll $13, $10, 28
srl $13, 28 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear L23TagLo/L23TagHi registers
mtc0 $0, $28, 4
mtc0 $0, $29, 4
move $15, $12
# L2$ Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0xB, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
10:
# Determine if we have a TLB
mfc0 $11, $16
sll $11, 22
srl $11, 29
li $15, 0x1 # MT = 1 => TLB
bne $11, $15, 15f
nop
mfc0 $10, $16, 1 # .word 0x400a8001
sll $11, $10, 1
srl $11, 26 # Number of TLB entries (-1)
mtc0 $0, $2 # EntryLo0
mtc0 $0, $3 # EntryLo1
mtc0 $0, $5 # PageMask
mtc0 $0, $6 # Wired
li $12, 0x80000000
1:
mtc0 $11, $0 # Index register
mtc0 $12, $10 # EntryHi
ssnop #.word 0x00000040
ssnop #.word 0x00000040
TLBWI
add $12, (2<<13) # Add 8K to the address to avoid TLB conflict with previous entry
bne $11, $0, 1b
add $11, -1
#endif //disable cache
15:
#endif
/* delay cycle */
li t0,0xFFFF
li t1,0x1
1:
sub t0, t0, t1
bnez t0, 1b
/* end of delay cycle */
li t5,SDRAM_CFG0_REG
lw t6,0(t5)
nop
and t6,0xF0000000
#if defined (RT2880_FPGA_BOARD) || defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD)
#ifdef RT2880_FPGA_BOARD
#ifdef RT2880_MP
nop
or t6,0x01825282
//or t6,0x01815282
nop
#else /* RT2880_SHUTTLE */
or t6,0x91825282
//or t6,0x91815282
#endif
#else //2883, 3052 fpga
nop
or t6,0xD1825282
//or t6,0x01815282
nop
#endif
#else //RT2880_ASIC_BOARD, RT2883_ASIC_BOARD, RT3052_ASIC_BOARD
or t6,0xD1825272
#endif
nop
sw t6,0(t5)
nop
// justic whether SDRAM active
li t5,SDRAM_CFG1_REG
lw t6,0(t5)
nop
and t6, t6, SDRAM_CFG1_SDRAM_INIT_DONE
bnez t6, SDRAM_INIT_DONE
nop
nop
#if defined (RT2880_ASIC_BOARD) || defined (RT2883_ASIC_BOARD) || defined (RT3052_ASIC_BOARD)
#ifdef ON_BOARD_64M_DRAM_COMPONENT
//64Mbits sdram component
li t6,0xa1010600
#elif ON_BOARD_128M_DRAM_COMPONENT
//128Mbits sdram component
li t6,0xa1110600
#elif ON_BOARD_256M_DRAM_COMPONENT
//256Mbits sdram component
li t6,0xa1120600
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6,0xFEFFFFFF
or t6,(1<<24)
#elif ON_BOARD_16BIT_DRAM_BUS
and t6,0xFEFFFFFF
#else
DRAM bus not defined
#endif
#else
#ifdef ON_BOARD_64M_DRAM_COMPONENT
//64Mbits sdram component
li t6,0x81010096
#elif ON_BOARD_128M_DRAM_COMPONENT
//128Mbits sdram component
li t6,0x81110096
#elif ON_BOARD_256M_DRAM_COMPONENT
//256Mbits sdram component
li t6,0x81120096
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6,0xFEFFFFFF
or t6,(1<<24)
#elif ON_BOARD_16BIT_DRAM_BUS
and t6,0xFEFFFFFF
#else
DRAM bus not defined
#endif
#endif
nop
sw t6,0(t5)
nop
WAIT_SDRAM_INIT_DOWN:
lw t6,0(t5)
nop
and t6, t6, SDRAM_CFG1_SDRAM_INIT_DONE
beqz t6, WAIT_SDRAM_INIT_DOWN
nop
SDRAM_INIT_DONE:
li t5,RALINK_SYSCTL_BASE + 0x0060
li t6,0x3
#if defined(RT3052_ASIC_BOARD)
#if defined(P5_MAC_TO_PHY_MODE)
//set mdio pin to normal mode
and t6,~0x80
#else
//set mdio pin to gpio mode
or t6,0x80
#endif
//configure UARTF pin to gpio mode (GPIO7~GPIO14)
#if defined(UARTF_AT_GPIO_FUNC)
or t6,0x1c
#endif
#endif
#ifdef MAC_TO_VITESSE_MODE
and t6,~(1<<2)
#endif
#ifdef PCI_AT_GPIO_FUNC
or t6,1<<7
#endif
nop
sw t6,0(t5)
nop
#ifdef PCI_AT_GPIO_FUNC
li t5, 0xa0300674
li t6, 0xffffffff
nop
sw t6,0(t5)
nop
li t5, 0xa0300670
li t6, 0xffffffff
nop
sw t6,0(t5)
nop
#endif
//set all GPIO to output high
li t5, RALINK_PIO_BASE + 0x24
li t6, 0xffffbfff
nop
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x2C
li t6, 0xffffffff
nop
sw t6, 0(t5)
nop
#if defined(RT2880_ASIC_BOARD)
//turn on power LED (GPIO 12)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<12
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<12
nop
sw t6, 0(t5)
nop
#elif defined(RT3052_ASIC_BOARD)
//turn on power LED (GPIO 9)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<9
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<9
nop
sw t6, 0(t5)
nop
#endif
#if defined(RT2880_ASIC_BOARD) || defined(RT2880_FPGA_BOARD)
// Need to remap the vector memory to 0x0 if no memory there
li t0, RALINK_SYSCTL_BASE + 0x0010
li t1, 0x00C10084 //prefetch off
sw t1, 0(t0)
#endif
#if defined(RT3052_ASIC_BOARD) || defined(RT3052_FPGA_BOARD)|| defined(RT3050_FPGA_BOARD)|| defined(RT3050_ASIC_BOARD)
li t0,RALINK_SYSCTL_BASE + 0x10
lw t1,0(t0)
nop
and t1,t1,(1 << 18)
bne t1,zero,SYTEM_CLOCK_SET_384MHZ
nop
// Initialize Icache size to 16K
mfc0 t0, CP0_CONFIG
or t0,(1<<19)
mtc0 t0, CP0_CONFIG
nop
mfc0 t0, CP0_CONFIG,1
move t1 ,t0
and t0,~(0x7 << 22)
or t0,(1 <<22)
mtc0 t0, CP0_CONFIG,1
nop
mfc0 t0, CP0_CONFIG
and t0,~(1<<19)
mtc0 t0, CP0_CONFIG
nop
nop
SYTEM_CLOCK_SET_384MHZ:
#endif
#if defined(RT2880_FPGA_BOARD) || defined(RT2880_ASIC_BOARD)
/* CONFIG0 register */
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
#if 1
/* Initialize caches...
*/
bal mips_cache_reset
nop
/* ... and enable them.
#define CONF_CM_CACHABLE_NO_WA 0
#define CONF_CM_CACHABLE_WA 1
#define CONF_CM_UNCACHED 2
#define CONF_CM_CACHABLE_NONCOHERENT 3
#define CONF_CM_CACHABLE_CE 4
*/
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
#endif
#endif
/* Set up temporary stack.
*/
li a0, CFG_INIT_SP_OFFSET
//bal mips_cache_lock
nop
// li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
// la sp, 0(t0)
/* Initialize GOT pointer.
*/
#if 0
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_ - 1f + 4
1:
move gp, ra
lw t1, 0(ra)
add gp, t1
#else
/* winfred: a easier way to get gp value so that mipsel-linux-as can
* assemble correctly without -mips_allow_branch_to_undefined flag
*/
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
lw gp, 0(ra)
#endif
// relocate got entries
move t4, gp // <---- t4: current GP
la t3, _GLOBAL_OFFSET_TABLE_ // <---- t3: original GP
subu t1, t4, t3 // <---- t1: offset to relocate
beqz t1, toload_stage2 // <---- (t1 == 0) ?(no_relocate): (do_relocate)
nop
bal num_got
nop
.word num_got_entries
num_got:
lw t0, 0(ra) //number_got_entries
addi t4, 8 //skip first 2 enties
addiu t0, -2
blez t0, toload_stage2
nop
2: lw t2, 0(t4)
beqz t2, 3f
add t2, t1
sw t2, 0(t4)
3: addiu t0, -1
bgtz t0, 2b
addi t4, 4
toload_stage2:
.extern _fstack //this reference to stag2's stack.
la sp, TEXT_BASE - 8
.extern load_stage2
la t9, load_stage2
jal t9
nop
#if 0
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
relocate_code:
move sp, a0 /* Set new stack pointer */
li t0, CFG_MONITOR_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
move t1, a2
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset */
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
/* On the purple board we copy the code earlier in a special way
* in order to solve flash problems
*/
#ifndef CONFIG_PURPLE
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
*/
/* Jump to where we've relocated ourselves.
*/
addi t0, a2, in_ram - _start
j t0
nop
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/* Now we want to update GOT.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
add t1, t6
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4 /* delay slot */
/* Clear BSS.
*/
lw t1, -12(t0) /* t1 <-- uboot_end_data */
lw t2, -8(t0) /* t2 <-- uboot_end */
add t1, t6 /* adjust pointers */
add t2, t6
sub t1, 4
1: addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
move a0, a1
la t9, board_init_r
j t9
move a1, a2 /* delay slot */
.end relocate_code
/* Exception handlers.
*/
#endif //COFNIG_STAGE1
romReserved:
b romReserved
romExcHandle:
b romExcHandle
|
aggresss/RFDemo
| 5,948
|
Code/Uboot_httpd/board/rt2880/memsetup.S
|
/* FILE_DESC *****************************************************************
//
// Purpose:
// This file contains macros used for memory initialization.
//
// Sp. Notes:
//
// *****************************************************************************/
/*=====================*
* Include Files *
*=====================*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include "include/product.h"
#include "include/mem_map.h"
#include "include/mac.inc"
#include "include/chip_reg_map.h"
/*=====================*
* Defines *
*=====================*/
.set noreorder
// SDRAM Width
#ifdef USE_SDRAM
#ifdef SDRAM32
#define MAC_SDRAM_WIDTH (MAC_SDRAM_WIDTH_32)
#else
#ifdef SDRAM16
#define MAC_SDRAM_WIDTH (MAC_SDRAM_WIDTH_16)
#else
#error "SDRAM width not defined in makefile"
#endif
#endif
#endif
// SRAM Width
#if USE_SRAM
#if SRAM32
#define MAC_SRAM_WIDTH (MAC_WIDTH_32)
#else
#if SRAM16
#define MAC_SRAM_WIDTH (MAC_WIDTH_16)
#else
#error "SRAM width not defined in makefile"
#endif
#endif
#endif
// Configures the SRAM bank. Must be done
// before attempting SRAM reads or writes.
// Setup modedata with 2-clk cas latency, burst length = 4.
//
// Uses registers t0-t1.
//
#ifdef USE_SRAM
#define CONFIG_SRAM() \
\
li t0, MAC_SRAM_CONFIG_REG; \
li t1, ( (1 << MAC_ADDR2CS_SETUP_SHIFT) | \
(1 << MAC_WADDR_SETUP_SHIFT) | \
(1 << MAC_RADDR_SETUP_SHIFT) | \
(1 << MAC_WE_SHIFT) | \
(1 << MAC_OE_SHIFT) | \
(1 << MAC_WHOLD_SHIFT) | \
(1 << MAC_RHOLD_SHIFT) | \
(2 << MAC_BANKTYPE_SHIFT) | \
MAC_SRAM_WIDTH); \
sw t1, 0(t0);
#endif
// Configures the SDRAM bank. Must be done
// before attempting SDRAM reads or writes.
// Setup modedata with 2-clk cas latency, burst length = 4.
// Configure SDRAM2 bank identically.
//
// Uses registers t5-t7.
//
#ifdef USE_SDRAM
#define CONFIG_SDRAM() \
\
li t6, MAC_SDRAM_CONFIG_REG; \
li t7, MAC_SDRAM2_CONFIG_REG; \
j sdram_pgsize_board; \
nop ; \
\
sdram_pgsize_sim: \
li t5, (0 << MAC_PGSIZE_SHIFT); \
j sdram_pgsize_done; \
nop ; \
\
sdram_pgsize_board: \
li t5, (1 << MAC_PGSIZE_SHIFT); \
j sdram_pgsize_done; \
nop ; \
\
sdram_pgsize_done: \
or t5, ( (7 << MAC_REFR_SHIFT) | \
(0 << MAC_ACTIVE_SHIFT) | \
(0 << MAC_PRECHRG_SHIFT) | \
(1 << MAC_NUMROWADR_SHIFT) | \
(1 << MAC_PRECHGOPT_SHIFT) | \
(2 << MAC_PCABIT_SHIFT) | \
(MAC_BANKTYPE_SDRAM << MAC_BANKTYPE_SHIFT) | \
MAC_SDRAM_WIDTH); \
sw t5, 0(t6); \
sw t5, 0(t7); \
li t6, MAC_SDRAM_MODE_REG; \
li t7, MAC_SDRAM2_MODE_REG; \
li t5, ( (2 << MAC_MD_BURSTLEN_SHIFT) | \
(2 << MAC_MD_LATMODE_SHIFT)); \
sw t5, 0(t6); \
sw t5, 0(t7);
// Initializes SDRAM via the memory controller.
// Must be done before attempting to use SDRAM.
// Initializes SDRAM2 as well.
//
// Uses t4-t6.
//
#define INIT_SDRAM() \
\
/* Enable SDRAM Clock */ \
li t6, MAC_SDRAM_CNTL_REG; \
li t4, MAC_CTRL_SDRAMCLK; \
sw t4, 0(t6); \
\
/* Tell the MAC to initialize SDRAM */ \
add t5, t4, MAC_CTRL_SDRAMINI; \
sw t5, 0(t6); \
\
/* Wait for completion of initialization */ \
init_sdram_loop: \
lw t5, 0(t6); \
bne t5, t4, init_sdram_loop; \
nop; /* branch delay slot */ \
\
\
/* Enable SDRAM2 Clock */ \
li t6, MAC_SDRAM2_CNTL_REG; \
li t4, MAC_CTRL_SDRAMCLK; \
sw t4, 0(t6); \
\
/* Tell the MAC to initialize SDRAM2 */ \
add t5, t4, MAC_CTRL_SDRAMINI; \
sw t5, 0(t6); \
\
init_sdram2_loop: \
lw t5, 0(t6); \
bne t5, t4, init_sdram2_loop; \
nop; /* branch delay slot */ \
\
/* Initialize SDRAM Refresh Control register */ \
/* Setup refresh rate */ \
li t6, MAC_SDRAM_REFR_CNTL_REG; \
li t5, ((0x05F << MAC_REFRESH_RATE_SHIFT) | \
(1 << MAC_REFRESH_PRESCALE_SHIFT)); \
sw t5, 0(t6);
#endif
/*=====================*
* External Variables *
*=====================*/
/*=====================*
* External Functions *
*=====================*/
.globl memsetup
.ent memsetup
memsetup:
CONFIG_SDRAM()
INIT_SDRAM()
j ra
nop
.end memsetup
|
aggresss/RFDemo
| 6,127
|
Code/Uboot_httpd/board/rt2880/rt2880_init.S
|
/*=====================*
* Include Files *
*=====================*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include "include/sysc.h"
#include "include/product.h"
#include "include/mem_map.h"
#include "include/mac.inc"
#include "include/chip_reg_map.h"
#include "include/cpu.h"
/*=====================*
* Defines *
*=====================*/
.set noreorder
// Configures the SRAM bank. Must be done
// before attempting SRAM reads or writes.
// Setup modedata with 2-clk cas latency, burst length = 4.
//
// Uses registers t0-t1.
//
#ifdef USE_SRAM
#define CONFIG_SRAM() \
\
li t0, MAC_SRAM_CONFIG_REG; \
li t1, ( (1 << MAC_ADDR2CS_SETUP_SHIFT) | \
(1 << MAC_WADDR_SETUP_SHIFT) | \
(1 << MAC_RADDR_SETUP_SHIFT) | \
(1 << MAC_WE_SHIFT) | \
(1 << MAC_OE_SHIFT) | \
(1 << MAC_WHOLD_SHIFT) | \
(1 << MAC_RHOLD_SHIFT) | \
(2 << MAC_BANKTYPE_SHIFT) | \
MAC_SRAM_WIDTH); \
sw t1, 0(t0);
#endif
/*=====================*
* External Functions *
*=====================*/
.globl soc_init
.ent soc_init
soc_init:
//////////////////////////////////////////
// S T A R T P L L A N D / O R D L L
//////////////////////////////////////////
#ifdef CODE_IN_SDRAM
// If current code is in SDRAM, may have problems reading and executing
// the code if the DLL clock to the SDRAM is changed on the fly.
#else
#ifdef USE_DLL_INIT
// Must enable DLL before enabling PLL. PLL before DLL does not work.
// DLL_INVERT and DLL_PHASE are defined in product.h
li a0, SYSC_BASE
li a1, DLL_INVERT
li a2, DLL_PHASE
// Disable DLL
lw t1, 0x4c(a0) // DLL Cfg Reg : offset 0x4c
li t0, ~DLL_ENABLE
and t1, t1, t0
sw t1, 0x4c(a0)
// Setup Configuration
// cfg = ((uint32)a2 & DLL_PHASE_MASK) << DLL_PHASE_SHIFT;
// cfg |= a1 ? DLL_INVERT_SYSCLK : 0;
andi a2, a2, DLL_PHASE_MASK
sll a2, a2, DLL_PHASE_SHIFT
ori t0, a2, DLL_INVERT_SYSCLK
movn a2, t0, a1 // if (t) d=s
sw a2, 0x4c(a0)
// enable the DLL
lw t0, 0x4c(a0)
ori t0, t0, DLL_ENABLE
sw t0, 0x4c(a0)
// Wait until dll locked
1: lw t0, 0x50(a0) // DLL Stat Reg: offset 0x50
andi t0, t0, DLL_LOCKED
beqz t0, 1b
nop
#else
// Current graphite (rev 2) requires DLL_INVERT_SYSCLK bit to be
// cleared to access SDRAM
// For CODE_IN_SDRAM, bit is cleared by debugger startice.cmd file
li t0, DLL_CONFIG_REG
lw t1, 0(t0)
li t2, ~DLL_INVERT_SYSCLK
and t3, t1, t2
sw t3, 0(t0)
#endif
#endif
#ifdef USE_PLL_INIT
// PLL_DIV and PLL_MULT are defined in product.h
li a0, SYSC_BASE
li a1, (PLL_DIV - 1)
#ifdef USE_DLL_INIT
// Adjust for fact that system clock is divided by two when DLL enabled
li a2, ((PLL_MULT * 2) - 1) // branch delay slot
#else
li a2, (PLL_MULT - 1) // branch delay slot
#endif
//Put PLL control in its POR state. (bypass, ~enable, reset)
lw t0, 0x40(a0) // PLL Ctrl Reg: offset 0x40
ori t0, t0, PLL_BYPASS
sw t0, 0x40(a0)
li t0, PLL_BYPASS | PLL_RESET
sw t0, 0x40(a0)
// Setup configuration
andi a2, a2, PLL_FEEDBACK_NDIV_MASK
sll a2, a2, PLL_FEEDBACK_NDIV_SHIFT
andi a1,a1, PLL_REFCLK_MDIV_MASK
sll a1, a1, PLL_REFCLK_MDIV_SHIFT
or a1, a1, a2
sw a1, 0x44(a0) // PLL Cfg Reg: offset 0x44
// Enable the pll
// ** Must be done in two steps.
// ** Step 1: take pll out of reset state
// ** Step 2: enable pll
// Step 1:
lw t0, 0x40(a0)
li t1, ~PLL_RESET
and t0, t0, t1
sw t0, 0x40(a0)
// Step 2:
lw t0, 0x40(a0)
ori t0, t0, PLL_ENABLE
sw t0, 0x40(a0)
// Wait until pll locked before selecting pll as system clock
1: lw t0, 0x48(a0) // PLL Stat Reg: offset 0x48
andi t0, t0, PLL_LOCKED
beqz t0, 1b
nop
// Select pll clock for system clock
lw t0, 0x40(a0)
li t1, ~PLL_BYPASS
and t0, t0, t1
sw t0,0x40(a0)
#endif
// Configure ROM Bank, which at power-up is initialized in its
// slowest mode.
// Use the current (POR) MAC_WIDTH value, since hardware should always
// have the correct ROM MAC_WIDTH as the POR value.
li t0, MAC_ROM_CONFIG_REG
lw t2, 0(t0)
andi t2, (MAC_WIDTH_MASK << MAC_WIDTH_SHIFT)
#if 0 // DEBUG - ROM set for fastest access
li t1, ( (1 << MAC_BYTE_EN_SHIFT) | \
(1 << MAC_ADDR2CS_SETUP_SHIFT) | \
(1 << MAC_WADDR_SETUP_SHIFT) | \
(1 << MAC_RADDR_SETUP_SHIFT) | \
(1 << MAC_WE_SHIFT) | \
(1 << MAC_OE_SHIFT) | \
(1 << MAC_WHOLD_SHIFT) | \
(1 << MAC_RHOLD_SHIFT) | \
(2 << MAC_BANKTYPE_SHIFT) )
#else // DEBUG - ROM set for slowest access
li t1, ( (0x1 << MAC_BYTE_EN_SHIFT) | \
(0x3 << MAC_ADDR2CS_SETUP_SHIFT) | \
(0x3 << MAC_WADDR_SETUP_SHIFT) | \
(0x3 << MAC_RADDR_SETUP_SHIFT) | \
(0xF << MAC_WE_SHIFT) | \
(0xF << MAC_OE_SHIFT) | \
(0x3 << MAC_WHOLD_SHIFT) | \
(0x3 << MAC_RHOLD_SHIFT) | \
(0x2 << MAC_BANKTYPE_SHIFT) )
#endif
or t1, t2
sw t1, 0(t0)
#ifdef USE_SRAM
CONFIG_SRAM()
#endif
/////////////////////////////
// I N I T P A L M P A K
/////////////////////////////
#ifdef REMAPPED_VECTOR_MEM
// Need to remap the vector memory to 0x0 if no memory there
li t0, CPU_CONFIG_REG
lw t1, 0(t0)
ori t1, REMAP_VECTMEM
sw t1, 0(t0)
#endif
#ifdef REMAPPED_SDRAM
// -OR- remap the first 2MB of sdram to 0x0
// NOTE: If both REMAPPED_VECTOR_MEM and REMAPPED_SDRAM are defined,
// software can setup for both, but hardware will give vector_mem
// precedence and remap it to 0x0.
li t0, CPU_CONFIG_REG
lw t1, 0(t0)
ori t1, REMAP_SDRAM2VEC
sw t1, 0(t0)
kaiker
#endif
j ra
nop
.end soc_init
|
aggresss/RFDemo
| 6,388
|
Code/Uboot_httpd/cpu/ralink_soc/cache.S
|
/*
* Cache-handling routined for MIPS 4K CPUs
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
/* 16KB is the maximum size of instruction and data caches on
* MIPS 4K.
*/
#define MIPS_MAX_CACHE_SIZE 0x4000
/*
* cacheop macro to automate cache operations
* first some helpers...
*/
#define _mincache(size, maxsize) \
bltu size,maxsize,9f ; \
move size,maxsize ; \
9:
#define _align(minaddr, maxaddr, linesize) \
.set noat ; \
subu AT,linesize,1 ; \
not AT ; \
and minaddr,AT ; \
addu maxaddr,-1 ; \
and maxaddr,AT ; \
.set at
/* general operations */
#define doop1(op1) \
cache op1,0(a0)
#define doop2(op1, op2) \
cache op1,0(a0) ; \
nop ; \
cache op2,0(a0)
/* specials for cache initialisation */
#define doop1lw(op1) \
lw zero,0(a0)
#define doop1lw1(op1) \
cache op1,0(a0) ; \
lw zero,0(a0) ; \
cache op1,0(a0)
#define doop121(op1,op2) \
cache op1,0(a0) ; \
nop; \
cache op2,0(a0) ; \
nop; \
cache op1,0(a0)
#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
.set noreorder ; \
10: doop##tag##ops ; \
bne minaddr,maxaddr,10b ; \
add minaddr,linesize ; \
.set reorder
/* finally the cache operation macros */
#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
_mincache(n, cacheSize); \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
/*******************************************************************************
*
* mips_cache_reset - low level initialisation of the primary caches
*
* This routine initialises the primary caches to ensure that they
* have good parity. It must be called by the ROM before any cached locations
* are used to prevent the possibility of data with bad parity being written to
* memory.
* To initialise the instruction cache it is essential that a source of data
* with good parity is available. This routine
* will initialise an area of memory starting at location zero to be used as
* a source of parity.
*
* RETURNS: N/A
*
*/
.globl mips_cache_reset
.ent mips_cache_reset
mips_cache_reset:
li t2, CFG_ICACHE_SIZE
li t3, CFG_DCACHE_SIZE
li t4, CFG_CACHELINE_SIZE
move t5, t4
#if 1
li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero.
*/
li a0, KSEG1
addu a1, a0, v0
2: sw zero, 0(a0)
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
sw zero, 16(a0)
sw zero, 20(a0)
sw zero, 24(a0)
sw zero, 28(a0)
addu a0, 32
bltu a0, a1, 2b
nop
#endif
/* Set invalid tag.
*/
mtc0 zero, CP0_TAGLO
/*
* The caches are probably in an indeterminate state,
* so we force good parity into them by doing an
* invalidate, load/fill, invalidate for each line.
*/
/* Assume bottom of RAM will generate good parity for the cache.
*/
li a0, K0BASE
move a2, t2 # icacheSize
move a3, t4 # icacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
nop
/* To support Orion/R4600, we initialise the data cache in 3 passes.
*/
/* 1: initialise dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
nop
/* 2: fill dcache.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,1lw,(dummy))
nop
/*
3: clear dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
nop
j ra
nop
nop
.end mips_cache_reset
/*******************************************************************************
*
* dcache_status - get cache status
*
* RETURNS: 0 - cache disabled; 1 - cache enabled
*
*/
.globl dcache_status
.ent dcache_status
dcache_status:
mfc0 v0, CP0_CONFIG
andi v0, v0, 1
j ra
.end dcache_status
/*******************************************************************************
*
* dcache_disable - disable cache
*
* RETURNS: N/A
*
*/
.globl dcache_disable
.ent dcache_disable
dcache_disable:
mfc0 t0, CP0_CONFIG
li t1, -8
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
j ra
.end dcache_disable
/*******************************************************************************
*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
*
* RETURNS: N/A
*
*/
#if defined(CONFIG_PURPLE)
# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
#else
# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock
mips_cache_lock:
j KAIKER_0
nop
nop
KAIKER_0:
li a1, K0BASE - CACHE_LOCK_SIZE
addu a0, a1
li a2, CACHE_LOCK_SIZE
li a3, CFG_CACHELINE_SIZE
move a1, a2
j KAIKER_1
nop
nop
KAIKER_1:
j KAIKER_11
nop
nop
KAIKER_11:
icacheop(a0,a1,a2,a3,0x1D)
j KAIKER_2
nop
nop
KAIKER_2:
j ra
.end mips_cache_lock
|
aggresss/RFDemo
| 33,902
|
Code/Uboot_httpd/cpu/ralink_soc/start.S
|
/*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <rt_mmap.h>
#define SDRAM_CFG0_REG RALINK_SYSCTL_BASE + 0x0300
#define SDRAM_CFG1_REG RALINK_SYSCTL_BASE + 0x0304
#define SDRAM_CFG0_ALWAYS_ONE ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_START ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_DONE ( 1 << 30)
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
.set noreorder
.globl _start
.text
_start:
RVECENT(reset,0) /* U-boot entry point */
RVECENT(reset,1) /* software reboot */
#if defined(CONFIG_INCA_IP)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word 0x00000000 /* phase of the flash */
#elif defined(CONFIG_PURPLE)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
#else
RVECENT(romReserved,2)
#endif
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
/* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
#ifdef CONFIG_PURPLE
/* 0xbfc00400 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
reset:
#if defined (RT2883_FPGA_BOARD) || defined (RT2883_ASIC_BOARD) || \
defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD) || \
defined (RT3883_FPGA_BOARD) || defined (RT3883_ASIC_BOARD) || \
defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD)
# Initialize the register file
# should not be required with good software practices
or $1,$0, $0
or $2,$0, $0
or $3,$0, $0
or $4,$0, $0
or $5,$0, $0
or $6,$0, $0
or $7,$0, $0
or $8,$0, $0
or $9,$0, $0
or $10,$0, $0
or $11,$0, $0
or $12,$0, $0
or $13,$0, $0
or $14,$0, $0
or $15,$0, $0
or $16,$0, $0
or $17,$0, $0
or $18,$0, $0
or $19,$0, $0
or $20,$0, $0
or $21,$0, $0
or $22,$0, $0
or $23,$0, $0
or $24,$0, $0
or $25,$0, $0
or $26,$0, $0
or $27,$0, $0
or $28,$0, $0
or $29,$0, $0
or $30,$0, $0
or $31,$0, $0
# Initialize Misc. Cop0 state
# Read status register
mfc0 $10, $12
# Set up Status register:
# Disable Coprocessor Usable bits
# Turn off Reduce Power bit
# Turn off reverse endian
# Turn off BEV (use normal exception vectors)
# Clear TS, SR, NMI bits
# Clear Interrupt masks
# Clear User Mode
# Clear ERL
# Set EXL
# Clear Interrupt Enable
# modify by Bruce
#li $11, 0x0000ff02
li $11, 0x00000004
mtc0 $11, $12
# Disable watch exceptions
mtc0 $0, $18
# Clear Watch Status bits
li $11, 0x3
mtc0 $11, $19
# Clear WP bit to avoid watch exception upon user code entry
# Clear IV bit - Interrupts go to general exception vector
# Clear software interrupts
mtc0 $0, $13
# Set KSeg0 to cacheable
# Config.K0
mfc0 $10, $16
li $11, 0x7
not $11
and $10, $11
or $10, 0x3
mtc0 $10, $16
# Clear Count register
mtc0 $0, $9
# Set compare to -1 to delay 1st count=compare
# Also, clears timer interrupt
li $10, -1
mtc0 $10, $11
# Cache initialization routine
# Long and needed on HW
# Can be skipped if using magic simulation cache flush
# Determine how big the I$ is
/*
************************************************************************
* C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| MMU Size | IS | IL | IA | DS | DL | DA |Rsvd |W|C|E|F| Config1
* | | | | | | | | | |R|A|P|P|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 1 # .word 0x400a8001
# Isolate I$ Line Size
sll $11, $10, 10
srl $11, 29
# Skip ahead if No I$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true I$ line size in bytes
sll $12, $10, 7
srl $12, 29
li $14, 64
sllv $12, $14, $12 # I$ Sets per way
sll $13, $10, 13
srl $13, 29 # I$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x8, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
# Now go through and invalidate the D$
# Now that the I$ has been flushed, the rest of the code can be
# moved to kseg0 and run from the cache to go faster
10:
# Isolate D$ Line Size
sll $11, $10, 19
srl $11, 29
# Skip ahead if No D$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true D$ line size in bytes
sll $12, $10, 16
srl $12, 29
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
sll $13, $10, 22
srl $13, 29 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
mtc0 $0, $28, 2
mtc0 $0, $29, 2
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x9, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
#
# Now go through and initialize the L2$
10:
# Check L2 cache size
/*
************************************************************************
* C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| TU | TS | TL | TA | SU | SS | SL | SA | Config2
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 2
# Isolate L2$ Line Size
sll $11, $10, 24
srl $11, 28
# Skip ahead if No L2$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true L2$ line size in bytes
# Isolate L2$ Sets per Way
sll $12, $10, 20
srl $12, 28
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
# Isolate L2$ Associativity
sll $13, $10, 28
srl $13, 28 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear L23TagLo/L23TagHi registers
mtc0 $0, $28, 4
mtc0 $0, $29, 4
move $15, $12
# L2$ Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0xB, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
10:
# Determine if we have a TLB
mfc0 $11, $16
sll $11, 22
srl $11, 29
li $15, 0x1 # MT = 1 => TLB
bne $11, $15, 15f
nop
mfc0 $10, $16, 1 # .word 0x400a8001
sll $11, $10, 1
srl $11, 26 # Number of TLB entries (-1)
mtc0 $0, $2 # EntryLo0
mtc0 $0, $3 # EntryLo1
mtc0 $0, $5 # PageMask
mtc0 $0, $6 # Wired
li $12, 0x80000000
1:
mtc0 $11, $0 # Index register
mtc0 $12, $10 # EntryHi
ssnop #.word 0x00000040
ssnop #.word 0x00000040
TLBWI
add $12, (2<<13) # Add 8K to the address to avoid TLB conflict with previous entry
bne $11, $0, 1b
add $11, -1
15:
#endif
#if defined(RT3350_ASIC_BOARD)
// force SDRAM_MD_DRV and SDRAM_MA_DRV from 8mA --> 4mA
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
or t1, t1, (3 << 4)
sw t1, 0(t0)
nop
#endif
#if (TEXT_BASE == 0xBFC00000) || (TEXT_BASE == 0xBF000000) || (TEXT_BASE == 0xBC000000)
/* SDR and DDR initialization: delay 200us
*/
li t0, 0xFFFF
li t1, 0x1
1:
sub t0, t0, t1
bnez t0, 1b
nop
#if defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#if defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD)
/* Use default SYSCFG1 setting */
#else
/* DDR initialization: reg SYSCFG1[25:16]:
* ODT disabled, LVCMOS=1, half drive, turn ON RT3662 DDR IO ODT as 150 ohm when read DRAM
*/
li t1, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t1)
nop
and t2, ~(0x3FF<<16)
or t2, (0x361<<16)
sw t2, 0(t1)
nop
#endif
/* DDR initialization: reset pin to 0
*/
li t1, RALINK_SYSCTL_BASE + 0x34
sw zero, 0(t1)
nop
/* DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
*/
DDR_READY:
li t1, RALINK_MEMCTRL_BASE + 0x44 //DDR_CFG1
lw t0, 0(t1)
nop
and t2, t0, (1<<21)
beqz t2, DDR_READY
nop
/* DDR initialization:
*/
#if defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD)
/* fpga/asic: reg DDR_CFG2 -- set bit[30]=0 as DDR1 mode when DDR1
* fpga/asic: reg DDR_CFG2 -- set bit[30]=1 as DDR2 mode when DDR2
* fpga/asic: reg DDR_CFG2 -- set bit[6:4]=3'b011 when DDR1
* fpga/asic: reg DDR_CFG2 -- set bit[6:4]=3'b100 when DDR2
*/
li t1, RALINK_MEMCTRL_BASE + 0x48 //DDR_CFG2
lw t0, 0(t1)
nop
and t0, ~(1<<30)
#if ON_BOARD_DDR2
and t0, ~(7<<4)
or t0, (4<<4)
or t0, (1<<30)
#elif ON_BOARD_DDR1
and t0, ~(7<<4)
or t0, (3<<4)
#endif
sw t0, 0(t1)
nop
#endif /* defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD) */
/* RT3883 and RT6855 will share below setting, RT3352 no boot from NOR */
/*
* fpga: reg DDR_CFG3 -- disable DLL
* asic: reg DDR_CFG3 -- ODT enable (bit 6,2) = 2'b10 when 6855/3883 DDR2
* fpga/asic: reg DDR_CFG3 -- ODT enable (bit 6,2) = 2'b00 when 6855 DDR1
* fpga/asic: reg DDR_CFG3[10][5:3] = 4'b0000 when 6855 DDR1
*/
li t1, RALINK_MEMCTRL_BASE + 0x4c ////DDR_CFG3
lw t2, 0(t1)
#ifdef ON_BOARD_DDR2
#disable ODT; reference board ok, ev board fail
#and t2, ~(1<<6)
#enable ODT; both ok
or t2, (1<<6)
and t2, ~(1<<2)
#elif ON_BOARD_DDR1
and t2, ~(1<<10)
and t2, ~(7<<3)
#endif
#if defined(RT3883_FPGA_BOARD) || defined(RT6855_FPGA_BOARD)
or t2, 0x1
#endif
sw t2, 0(t1)
nop
#ifdef RALINK_DDR_OPTIMIZATION
/* DDR: set Burst Length=4 in 32 bits dram bus for better performance
* Burst Length=8 in non 32 bits dram bus
*/
li t0, RALINK_MEMCTRL_BASE + 0x48
lw t1, 0(t0)
nop
and t1, 0xffffff88
or t1, (CAS_VALUE<<CAS_OFFSET)
or t1, (BL_VALUE<<BL_OFFSET)
sw t1, 0(t0)
nop
li t0, RALINK_MEMCTRL_BASE + 0x4c
lw t1, 0(t0)
nop
and t1, 0xffffffc7
or t1, (AdditiveLatency_VALUE<<AdditiveLatency_OFFSET)
sw t1, 0(t0)
#endif
#if defined (RT3352_FPGA_BOARD) || defined (RT3883_FPGA_BOARD) || defined (RT6855_FPGA_BOARD)
/* DDR initialization: DDR_CFG0 bit 12:0 (refresh interval) to 0x64
* Note. this may have a bad affect on efficiency if the clock rate is 40MHz
*/
li t1, RALINK_MEMCTRL_BASE + 0x40
lw t2, 0(t1)
nop
and t2, ~(0xfff)
#if defined(ON_BOARD_DDR1) && defined(RT6855_FPGA_BOARD)
li t2, 0x21086141
#else
or t2, 0x64
#endif
sw t2, 0(t1)
nop
#endif
#if 0
/* data output (DQ) delay */
li t1, RALINK_MEMCTRL_BASE + 0x60
li t2, 0xffffffff
sw t2, 0(t1)
nop
li t1, RALINK_MEMCTRL_BASE + 0x64
li t2, 0xffffffff
sw t2, 0(t1)
nop
#endif
/* DDR initialization: config size and width on reg DDR_CFG1
*/
#if defined(RT6855_ASIC_BOARD)&&defined(ON_BOARD_DDR2)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x332A3525
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x332E3525
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x33323525
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x33363525
#else
DRAM Component not defined
#endif
#elif defined(RT6855_ASIC_BOARD)&&defined(ON_BOARD_DDR1)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x332A3525
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x332E3525
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x33323525
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x33363525
#else
DRAM Component not defined
#endif
#elif defined(RT6855_FPGA_BOARD)&&defined(ON_BOARD_DDR2)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x122A3121
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222e2323 //0x122E3121
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x12323121
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x12363121
#else
DRAM Component not defined
#endif
#elif defined(RT6855_FPGA_BOARD)&&defined(ON_BOARD_DDR1)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x122A3111
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222e2113 //0x122E3111
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x12323111
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x12363111
#else
DRAM Component not defined
#endif
#else /* RT3883 and RT3352 */
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x222A3323
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222E3323
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x22323323
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x22363323
#else
DRAM Component not defined
#endif
#endif /* end of setting DDR_CFG1 */
#ifdef ON_BOARD_DDR_WIDTH_16
or t6, (1<<17)
and t6, ~(1<<16)
#elif defined (ON_BOARD_DDR_WIDTH_8)
and t6, ~(1<<17)
or t6, (1<<16)
#else
DDR width not defined
#endif
/* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
and t6, ~(3<<12)
#ifdef ON_BOARD_32BIT_DRAM_BUS
or t6, (3<<12)
#elif defined (ON_BOARD_16BIT_DRAM_BUS)
or t6, (2<<12)
#else
DRAM bus not defined
#endif
li t5, RALINK_MEMCTRL_BASE + 0x44
sw t6, 0(t5)
nop
j SDRAM_INIT_DOWN
nop
#endif /* defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2) */
#ifdef ON_BOARD_SDR
SDR_INIT:
/* SDR initialization: SDRAM_CFG0
*/
li t5, SDRAM_CFG0_REG
lw t6, 0(t5)
nop
and t6, 0xF0000000
#ifdef FPGA_BOARD
#ifdef RT2880_FPGA_BOARD
#ifdef RT2880_MP
nop
or t6, 0x01825282
//or t6, 0x01815282
nop
#else /* RT2880_SHUTTLE */
or t6, 0x91825282
//or t6, 0x91815282
#endif
#elif defined(RT6855_FPGA_BOARD)
or t6, 0xD1825272
//or t6, 0xD1916292
#else //2883, 3052, 3352, 3883, 5350 fpga
nop
or t6, 0xD1825272
//or t6, 0x01815282
nop
#endif
#else //ASIC_BOARD
#if defined(RT6855_ASIC_BOARD)
or t6, 0xD1916292
#else
or t6, 0xD1825272
#endif
#endif
nop
sw t6, 0(t5)
nop
li t5, SDRAM_CFG1_REG
#ifdef ASIC_BOARD
/*
* Turn on SDRAM RBC (BIT 29 in SDRAM_CFG1, offset 0x4) in RT3052.
* RT2880 RBC bit is Reserved bit, and change the same value for RT2880 and RT3052
* Original 0x81xx0600 -> 0xa1xx0600
* by bobtseng, 2008.7.7.
*/
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t6, 0xa1010600
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t6, 0xa1110600
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0xa1120300
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0xa1220600
#elif defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6, 0xFEFFFFFF
or t6, (1<<24)
#elif defined ON_BOARD_16BIT_DRAM_BUS
and t6, 0xFEFFFFFF
#else
DRAM bus not defined
#endif
#else /* not ASIC_BOARD */
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t6, 0xa1010096
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t6, 0xa1110096
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0xa112004B
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0xa1220096
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6, 0xFEFFFFFF
or t6, (1<<24)
#elif defined (ON_BOARD_16BIT_DRAM_BUS)
and t6, 0xFEFFFFFF
#else
DRAM bus not defined
#endif
#endif
DO_SDRINIT:
nop
sw t6, 0(t5)
nop
WAIT_SDRAM_INIT_DOWN:
lw t6, 0(t5)
nop
and t6, t6, SDRAM_CFG1_SDRAM_INIT_DONE
beqz t6, WAIT_SDRAM_INIT_DOWN
nop
#endif // ON_BOARD_SDR //
SDRAM_INIT_DOWN:
#endif
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
#ifdef ON_BOARD_DDR2
#if (TEXT_BASE != 0xBFC00000) && (TEXT_BASE != 0xBF000000) && (TEXT_BASE != 0xBC000000)
/* DDR initialization: reg SYSCFG1[25:16]:
* ODT disabled, LVCMOS=1, half drive, turn ON RT3662 DDR IO ODT as 150 ohm when read DRAM
*/
li t1, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t1)
nop
and t2, ~(0x3FF<<16)
or t2, (0x361<<16)
sw t2, 0(t1)
nop
#endif
#endif
#endif
#ifdef RT3352_ASIC_BOARD
/* adjust the SW reg voltage level higher */
li t1, RALINK_SYSCTL_BASE + 0x88
li t2, 0xECC340
sw t2, 0(t1)
nop
/* set LDODIG 1.24V */
li t1, RALINK_SYSCTL_BASE + 0x8c
li t2, 0x9B82
sw t2, 0(t1)
nop
/*
* Enable spreading spectrum clock
* SSC_MODUMAG=7: +/-1.00% for center; -2.00% for down
*/
li t1, RALINK_SYSCTL_BASE + 0x54
li t2, 0x71
nop
sw t2, 0(t1)
#ifdef ON_BOARD_DDR2
#if 0
/* RT3352 EVB board with 32bits DDR shall enable this */
/* data output (DQ) delay */
li t1, RALINK_MEMCTRL_BASE + 0x60
li t2, 0xffffffff
sw t2, 0(t1)
nop
li t1, RALINK_MEMCTRL_BASE + 0x64
li t2, 0xffffffff
sw t2, 0(t1)
nop
#endif
#if 0
/* RT3352 EVB board with 16/32 bits DDR shall enable this */
/*
* DDR_PAD_DRV_1=00 (full drive)
* DDR_PAD_DS=0 (DDR2 differential RX application)
* DDR_PAD_LVCMO=0 (DDR default)
* DDR_PAD_DRV_0=00 (full drive)
*/
li t1, RALINK_SYSCTL_BASE + 0x14
and t2, ~(0x33F00000)
sw t2, 0(t1)
nop
#endif
#endif /* ON_BOARD_DDR2 */
#endif /* RT3352_ASIC_BOARD */
#if defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
/* get cpu frequency from SYSCFG0 bit 9:8, and adjust tRFC accordingly
*/
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
and t1, (0x3 << 8)
bne t1, (0x3 << 8), tRFC480
nop
/* DDR initialization: DDR_CFG0: adjust tRFC according to size and cpu clock
* for a better performance
* applied for both rom and ram version (SPI and NAND flash)
*/
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498E4F0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498E4F0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E4F0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x249924F0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249964F0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249924F0
#else
DRAM Component not defined
#endif
j tRFCinit
tRFC480:
bne t1, (0x2 << 8), tRFC250
nop
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498E4C0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498E4C0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E4C0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x249924C0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249964C0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249924C0
#else
DRAM Component not defined
#endif
j tRFCinit
tRFC250:
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498A3B0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498A3B0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498A3B0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x2499C3B0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249903B0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x2499A3B0
#else
DRAM Component not defined
#endif
#elif defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD)
#if defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E400
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x24992400
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x24996400
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249A2400
#else
DRAM Component not defined
#endif
#elif defined(RT6855_ASIC_BOARD)
#if defined(ON_BOARD_DDR1)
/* below 0x2419C640 is base on CLK = 200Mhz setting */
li t4, 0x2419C640
#endif /* defined(ON_BOARD_DDR1) */
#if defined(ON_BOARD_DDR2)
/* below 0x35AEA823 is base on CLK = 266Mhz setting */
li t4, 0x35AEA823
#endif /* defined(ON_BOARD_DDR2) */
#elif defined(RT6855_FPGA_BOARD)
#if defined(ON_BOARD_DDR1)
/* below 0x21086140 is base on CLK = 40Mhz setting */
li t4, 0x21086140
#endif /* defined(ON_BOARD_DDR1) */
#if defined(ON_BOARD_DDR2)
/* below 0x21090138 is base on CLK = 40Mhz setting */
li t4, 0x21090138
#endif /* defined(ON_BOARD_DDR2) */
/*
#elif defined(RT6855_FPGA_BOARD) || defined(RT6855_ASIC_BOARD)
#if defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E400
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x24992400
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x24996400
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249A2400
#else
DRAM Component not defined
#endif
*/
#endif // defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD) //
tRFCinit:
#if 0
li t3, RALINK_MEMCTRL_BASE + 0x40
sw t4, 0(t3)
nop
#endif
#if defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD)
#if defined(RALINK_DDR_POWERSAVE)
/* DDR: enable self auto refresh for power saving
* enable it by default for both RAM and ROM version (for CoC)
*/
li t0, RALINK_MEMCTRL_BASE + 0x1C
lw t1, 0(t0)
nop
and t1, 0xff000000
or t1, 0x01
sw t1, 0(t0)
nop
li t0, RALINK_MEMCTRL_BASE + 0x18
lw t1, 0(t0)
nop
or t1, 0x10
sw t1, 0(t0)
nop
#endif
#endif // defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) //
#else // SDR //
#if defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
#if defined(RALINK_SDR_POWERSAVE)
/* SDR:enable precharge power saving
*/
li t0, RALINK_MEMCTRL_BASE + 0x1C
lw t1, 0(t0)
nop
and t1, 0xff000000
or t1, 0x01
sw t1, 0(t0)
nop
li t0, RALINK_MEMCTRL_BASE + 0x04
lw t1, 0(t0)
nop
or t1, 0x10000000
sw t1, 0(t0)
nop
#endif // RALINK_MEMORY_POWER_SAVE //
#endif // defined(RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD)
#endif /* defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2) */
#if defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
#if defined (RALINK_CPU_AUTOFREQUENCY)
/* auto freq adjustment 3352,5350 support
*/
li t0, RALINK_SYSCTL_BASE + 0x44
li t1, 0x1f0112
sw t1, 0(t0)
nop
li t0, RALINK_SYSCTL_BASE + 0x3c
li t1, 0x3040101
sw t1, 0(t0)
nop
li t0, RALINK_SYSCTL_BASE + 0x40
li t1, 0x80035f41
sw t1, 0(t0)
nop
#endif
#endif // defined(RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) //
li t5, RALINK_SYSCTL_BASE + 0x0060
lw t6, 0(t5)
nop
or t6, 0x03
#if defined (RT2880_ASIC_BOARD) || defined (RT2880_FPGA_BOARD)
/* enable normal function i2c, spi, uartl, jtag, mdio, sdram */
and t6, ~(0x1<<0)
and t6, ~(0x1<<2)
and t6, ~(0x1<<3)
and t6, ~(0x1<<4)
and t6, ~(0x1<<5)
and t6, ~(0x1<<6)
#else
/* enable normal function i2c, spi, uartl, jtag, mdio, ge1 */
and t6, ~(0xf<<7)
and t6, ~(0x3<<5)
and t6, ~(0x3)
/* LNA_G_SHARE_MODE and LNA_A_SHARE_MODE at normal function, not GPIO mode */
and t6, ~(0xf<<16)
/* disable I2C mode and turned to gpio mode, modify by agg */
or t6, 0x01<<1
#endif
#if defined(RT3052_ASIC_BOARD) || defined(RT3352_ASIC_BOARD) || defined(RT6855_ASIC_BOARD)
#if defined(P5_MAC_TO_PHY_MODE)
//set mdio pin to normal mode
and t6, ~0x80
#else
//set mdio pin to gpio mode
or t6, 0x80
#endif
#if defined(ON_BOARD_16BIT_DRAM_BUS)
//set SDRAM pin to gpio mode
or t6, 0x100
#endif
#if defined(UARTF_AT_GPIO_FUNC)
//configure UARTF pin to gpio mode (GPIO7~GPIO14)
or t6, 0x1c
#endif
#endif
#ifdef MAC_TO_VITESSE_MODE
//set spi pin to normal mode
#if defined (RT2880_FGPA_BOARD) || defined (RT2880_ASIC_BOARD)
and t6, ~(1<<2)
#else
and t6, ~(1<<1)
#endif
#endif
#ifdef PCI_AT_GPIO_FUNC
or t6, 1<<7
#endif
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
//PCI share mode for NOR flash read/write
#if 0
//old PCI share mode: 3'b010
and t6, ~(7<<11)
or t6, 2<<11
#else
//new PCI share mode: 3'b011
and t6, ~(7<<11)
or t6, 3<<11
#endif
#endif
//set GPIOMODE
nop
sw t6, 0(t5)
nop
#ifdef PCI_AT_GPIO_FUNC
li t5, 0xa0300674
li t6, 0xffffffff
nop
sw t6,0(t5)
nop
li t5, 0xa0300670
li t6, 0xffffffff
nop
sw t6, 0(t5)
nop
#endif
//set all GPIO to output high
li t5, RALINK_PIO_BASE + 0x24
li t6, 0xffffbfff
nop
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x2C
li t6, 0xffffffff
nop
sw t6, 0(t5)
nop
#if defined(ON_BOARD_16BIT_DRAM_BUS)
//if sdram bus is 16bits,set gpio24~gpio39 to output high
li t5, RALINK_PIO_BASE + 0x4C
li t6, 0xffff
nop
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x54
li t6, 0xffff
nop
sw t6, 0(t5)
nop
#endif
#if defined(RT5350_ASIC_BOARD)
// set default LED polarity value for RT5350 REF board
// Active status:
// EPHY_LED0 H: Light
// EPHY_LED1 H: Light
// EPHY_LED2 H: Light
// EPHY_LED3 L: Light
// EPHY_LED4 H: Light
li t5, RALINK_ETH_SW_BASE + 0x168
li t6, 0x17
nop
sw t6, 0(t5)
nop
#endif
#if defined(RT2880_ASIC_BOARD)
//turn on power LED (GPIO 12)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<12
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<12
nop
sw t6, 0(t5)
nop
#elif defined(RT2883_ASIC_BOARD)
//turn on power LED (GPIO 8)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<8
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<8
nop
sw t6, 0(t5)
nop
#elif defined(RT3052_ASIC_BOARD)
//turn on power LED (GPIO 9)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<9
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<9
nop
sw t6, 0(t5)
nop
#elif defined(RT3352_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT5350_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT6855_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT3883_ASIC_BOARD)
//turn on power LED (GPIO ?)
#endif
/* config SYSCFG or SYSCFG1 register accordingly
*/
#if defined(RT2880_ASIC_BOARD) || defined(RT2880_FPGA_BOARD)
// Need to remap the vector memory to 0x0 if no memory there
li t0, RALINK_SYSCTL_BASE + 0x0010
li t1, 0x00C10084 //prefetch off
sw t1, 0(t0)
#endif
#if defined(RT2883_ASIC_BOARD) || defined(RT2883_FPGA_BOARD)
//set PCIe to RC mode
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
or t1, t1, (1 << 23)
sw t1, 0(t0)
nop
#endif
#if defined(RT3883_ASIC_BOARD) || defined(RT3883_FPGA_BOARD)
//FIXME: read from SYSCFG
li t0, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t0)
nop
and t2, ~(3 << 14) //GE2 to RGMII mode
and t2, ~(3 << 12) //GE1 to RGMII mode
or t2, (1 << 8) //PCIe to RC mode (for ethernet)
or t2, (1 << 7) //PCI to Host mode (for ethernet)
sw t2, 0(t0)
nop
#endif
#if defined(RT2880_FPGA_BOARD) || defined(RT2880_ASIC_BOARD)
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
/* Initialize caches...
*/
bal mips_cache_reset
nop
/* ... and enable them.
*/
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
#endif
/* Set up temporary stack.
*/
li a0, CFG_INIT_SP_OFFSET
//bal mips_cache_lock
nop
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
la sp, 0(t0)
/* Initialize GOT pointer.
*/
#if 0
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_ - 1f + 4
1:
move gp, ra
lw t1, 0(ra)
add gp, t1
#else
/* winfred: a easier way to get gp value so that mipsel-linux-as can
* assemble correctly without -mips_allow_branch_to_undefined flag
*/
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
lw gp, 0(ra)
#endif
la t9, board_init_f
j t9
nop
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
relocate_code:
move sp, a0 /* Set new stack pointer */
li t0, CFG_MONITOR_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
move t1, a2
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset */
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
/* On the purple board we copy the code earlier in a special way
* in order to solve flash problems
*/
#ifndef CONFIG_PURPLE
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
*/
/* Jump to where we've relocated ourselves.
*/
addi t0, a2, in_ram - _start
j t0
nop
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/* Now we want to update GOT.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
add t1, t6
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4 /* delay slot */
/* Clear BSS.
*/
lw t1, -12(t0) /* t1 <-- uboot_end_data */
lw t2, -8(t0) /* t2 <-- uboot_end */
add t1, t6 /* adjust pointers */
add t2, t6
sub t1, 4
1: addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
move a0, a1
la t9, board_init_r
j t9
move a1, a2 /* delay slot */
.end relocate_code
/* Exception handlers.
*/
romReserved:
b romReserved
romExcHandle:
b romExcHandle
|
agiledragon/gomonkey
| 1,855
|
write_darwin_amd64.s
|
/*
* Copyright 2022 ByteDance Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "textflag.h"
#define NOP8 BYTE $0x90; BYTE $0x90; BYTE $0x90; BYTE $0x90; BYTE $0x90; BYTE $0x90; BYTE $0x90; BYTE $0x90;
#define NOP64 NOP8; NOP8; NOP8; NOP8; NOP8; NOP8; NOP8; NOP8;
#define NOP512 NOP64; NOP64; NOP64; NOP64; NOP64; NOP64; NOP64; NOP64;
#define NOP4096 NOP512; NOP512; NOP512; NOP512; NOP512; NOP512; NOP512; NOP512;
#define protRW $(0x1|0x2|0x10)
#define mProtect $(0x2000000+74)
TEXT ·write(SB),NOSPLIT,$24
JMP START
NOP4096
START:
MOVQ mProtect, AX
MOVQ page+24(FP), DI
MOVQ pageSize+32(FP), SI
MOVQ protRW, DX
SYSCALL
CMPQ AX, $0
JZ PROTECT_OK
CALL mach_task_self(SB)
MOVQ AX, DI
MOVQ target+0(FP), SI
MOVQ len+16(FP), DX
MOVQ $0, CX
MOVQ protRW, R8
CALL mach_vm_protect(SB)
CMPQ AX, $0
JNZ RETURN
PROTECT_OK:
MOVQ target+0(FP), DI
MOVQ data+8(FP), SI
MOVQ len+16(FP), CX
MOVQ DI, to-24(SP)
MOVQ SI, from-16(SP)
MOVQ CX, n-8(SP)
CALL runtime·memmove(SB)
MOVQ mProtect, AX
MOVQ page+24(FP), DI
MOVQ pageSize+32(FP), SI
MOVQ oriProt+40(FP), DX
SYSCALL
JMP RETURN
NOP4096
RETURN:
MOVQ AX, ret+48(FP)
RET
|
agiledragon/gomonkey
| 1,818
|
write_darwin_arm64.s
|
/*
* Copyright 2022 ByteDance Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "textflag.h"
#define NOP64 WORD $0x1f2003d5; WORD $0x1f2003d5;
#define NOP512 NOP64; NOP64; NOP64; NOP64; NOP64; NOP64; NOP64; NOP64;
#define NOP4096 NOP512; NOP512; NOP512; NOP512; NOP512; NOP512; NOP512; NOP512;
#define NOP16384 NOP4096; NOP4096; NOP4096; NOP4096; NOP4096; NOP4096; NOP4096; NOP4096;
#define protRW $(0x1|0x2|0x10)
#define mProtect $(0x2000000+74)
TEXT ·write(SB),NOSPLIT,$24
B START
NOP16384
START:
MOVD mProtect, R16
MOVD page+24(FP), R0
MOVD pageSize+32(FP), R1
MOVD protRW, R2
SVC $0x80
CMP $0, R0
BEQ PROTECT_OK
CALL mach_task_self(SB)
MOVD target+0(FP), R1
MOVD len+16(FP), R2
MOVD $0, R3
MOVD protRW, R4
CALL mach_vm_protect(SB)
CMP $0, R0
BNE RETURN
PROTECT_OK:
MOVD target+0(FP), R0
MOVD data+8(FP), R1
MOVD len+16(FP), R2
MOVD R0, to-24(SP)
MOVD R1, from-16(SP)
MOVD R2, n-8(SP)
CALL runtime·memmove(SB)
MOVD mProtect, R16
MOVD page+24(FP), R0
MOVD pageSize+32(FP), R1
MOVD oriProt+40(FP), R2
SVC $0x80
B RETURN
NOP16384
RETURN:
MOVD R0, ret+48(FP)
RET
|
AgonPlatform/agondev
| 3,835
|
release/examples/ez80asm/src/moscalls.s
|
.assume adl=1
.global _removefile
.global _getfilesize
.global _fast_strcasecmp
.global _fast_strncasecmp
.section .text
; Removes filename from SD card
; Input: filename string
; Output: A: File error, or 0 if OK
_removefile:
push ix
ld ix,0
add ix, sp
ld hl, (ix+6) ; Address of path (zero terminated)
ld a, 05h ; MOS_DEL API
rst.lil 08h ; Delete a file or folder from the SD card
ld sp,ix
pop ix
; TEST
call __test
; TEST
ret
.global __test
__test:
scf
;virtual
; jr nc, $ + 2
; load .jr_nc: 1 from $$
;end virtual
; db .jr_nc
db 0x30 ; first opcode for <JR NC, xx>
.global __test2
__test2:
db 0
db 0
db 0
db 0
; Gets filesize from an open file
; requires MOS mos_getfil call
; Input: MOS filehandle
; Output: HL - 24bit filesize
_getfilesize:
PUSH IX
LD IX, 0h
ADD IX, SP
; get pointer to FIL structure in MOS memory
LD A, (IX+6)
LD C, A
LD A, 19h ; MOS_GETFIL API call
RST.LIL 08h
LD DE, 11 ; offset to lower 3bytes in FSIZE_t, part of the FFOBJD struct that HL points to
ADD HL, DE
LD HL, (HL) ; load actual FSIZE_t value (lower 3 bytes)
LD SP, IX
POP IX
RET
; Fast lowercase compare between two strings
; Stops at first difference of the two strings, or at either string terminator (0)
; returns first character difference in A
_fast_strcasecmp:
push ix
ld ix,0
add ix,sp
dec sp
ld hl, (ix+6) ; s1
ld de, (ix+9) ; s2
a.loop:
ld c,(hl) ; *s1
inc hl ; s1++
; *s1 tolower
ld a, c
sub a, 'A'
cp a, 1+'Z'-'A'
jr nc, a.conts2
add a, 'a'
ld c, a
a.conts2: ; c now contains tolower(*s1)
ex de, hl
ld b,(hl) ; *s2
inc hl ; s2++
ex de, hl
; *s2 tolower
ld a, b
sub a, 'A'
cp a, 1+'Z'-'A'
jr nc, a.conts1
add a, 'a'
ld b, a
a.conts1: ; d now contains tolower(*s2)
ld a, b
cp a, 0 ; stop at 0 of string s2
jr z, a.done
cp a, c ; loop back, or stop at difference (might be 0 of string s1)
jr z, a.loop
a.done:
sub a, c ; *s1 == *s2? -> result in A (0 == equal)
ld sp,ix
pop ix
ret
; Fast lowercase compare between two strings, max uint8_t n characters
; Stops at first difference of the two strings, or at either string terminator (0)
; returns first character difference in A
_fast_strncasecmp:
push ix
ld ix,0
add ix,sp
dec sp
ld hl, (ix+12) ; n
add hl, de
or a,a
sbc hl,de
jr z, .ret0 ; n == 0? return 0
ld hl, (ix+6) ; s1
ld de, (ix+9) ; s2
.loop:
ld c,(hl) ; *s1
inc hl ; s1++
; *s1 tolower
ld a, c
sub a, 'A'
cp a, 1+'Z'-'A'
jr nc, .conts2
add a, 'a'
ld c, a
.conts2: ; c now contains tolower(*s1)
ex de, hl
ld b,(hl) ; *s2
inc hl ; s2++
ex de, hl
; *s2 tolower
ld a, b
sub a, 'A'
cp a, 1+'Z'-'A'
jr nc, .conts1
add a, 'a'
ld b, a
.conts1: ; d now contains tolower(*s2)
ld a, b
cp a, 0 ; stop at 0 of string s2
jr z, .done
cp a, c ; loop back, or stop at difference (might be 0 of string s1)
jr z, .checkn0
.done:
sub a, c ; *s1 == *s2? -> result in A (0 == equal)
ld sp,ix
pop ix
ret
.ret0:
ld a,0
ld sp, ix
pop ix
ret
.checkn0:
push hl
ld hl, (ix+12)
dec hl
ld (ix+12), hl
add hl, de
or a,a
sbc hl,de
pop hl
jr z, .ret0 ; n == 0? return 0
jr .loop
|
AgonPlatform/agon-ez80asm
| 2,629
|
tests/Macro/tests/nested_macro_test.s
|
; Nested Macros test for Jeroen
; Richard Turnnidge 2024
; ---------------------------------------------
;
; MACROS
;
; ---------------------------------------------
macro MOSCALL afunc
ld a, afunc
rst.lil $08
endmacro
macro TAB_TO_XY x, y
ld a, 31
rst.lil $10
ld a, x
rst.lil $10
ld a, y
rst.lil $10
endmacro
macro SETCOLOUR colour
ld a, 17
rst.lil $10
ld a, colour
rst.lil $10
endmacro
macro PRINTCAPTION_AT_XY caption, colour, x, y
SETCOLOUR colour
TAB_TO_XY x, y
ld hl, caption
call printString
endmacro
macro CLEARSCREEN
ld a, 12
rst.lil $10 ; CLS
endmacro
macro HIDE_CURSOR
ld a, 23
rst.lil $10
ld a, 1
rst.lil $10
ld a,0
rst.lil $10 ;VDU 23,1,0
endmacro
; ---------------------------------------------
;
; INITIALISE
;
; ---------------------------------------------
.assume adl=1 ; big memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
; ---------------------------------------------
;
; INITIAL SETUP CODE HERE
;
; ---------------------------------------------
start_here:
; store everything as good practice
push af ; pop back when we return from code later
push bc
push de
push ix
push iy
CLEARSCREEN
HIDE_CURSOR ; hide the cursor
PRINTCAPTION_AT_XY caption1, 1, 10,10
PRINTCAPTION_AT_XY caption2, 2, 15,20
PRINTCAPTION_AT_XY caption3, 3, 0,30
PRINTCAPTION_AT_XY caption4, 4, 18,5
; ---------------------------------------------
;
; MAIN LOOP
;
; ---------------------------------------------
MAIN_LOOP:
MOSCALL $08 ; get IX pointer to sysvars
ld a, (ix + 05h) ; ix+5h is 'last key pressed'
cp 27 ; is it ESC key?
jp z, exit_here ; if so exit cleanly
jp MAIN_LOOP
; ---------------------------------------------
;
; EXIT CODE CLEANLY
;
; ---------------------------------------------
exit_here:
; reset all values before returning to MOS
pop iy
pop ix
pop de
pop bc
pop af
ld hl,0
ret ; return to MOS here
; ---------------------------------------------
;
; OTHER ROUTINES
;
; ---------------------------------------------
printString: ; print zero terminated string
ld a,(hl)
or a
ret z
RST.LIL 10h
inc hl
jr printString
; ---------------------------------------------
;
; TEXT AND DATA
;
; ---------------------------------------------
caption1: .asciz "Hello World"
caption2: .asciz "ez80asm rocks"
caption3: .asciz "we love feature creep"
caption4: .asciz "Agon is cool"
LINEFEED: .asciz "\r\n",0
|
AgonPlatform/agon-ez80asm
| 1,509
|
tests/Parser/tests/operands_with_spaces.s
|
; testing the getOperator code
; spacing after operators
ld a,1+1
ld a,1+1;
ld a,1+1 ;
ld a,1+1 ;
ld a,1+1 ;
; spacing just before operators
ld a, 1+1
ld a, 1+1;
ld a, 1+1 ;
ld a, 1+1 ;
ld a, 1+1 ;
ld a, 1+1
ld a, 1+1;
ld a, 1+1 ;
ld a, 1+1 ;
ld a, 1+1 ;
ld a, 1+1
ld a, 1+1;
ld a, 1+1 ;
ld a, 1+1 ;
ld a, 1+1 ;
ld a, 1+1
ld a, 1+1;
ld a, 1+1 ;
ld a, 1+1 ;
ld a, 1+1 ;
; spacing within operator
ld a,1 +1
ld a,1 +1;
ld a,1 +1 ;
ld a,1 +1 ;
ld a,1 +1 ;
ld a,1 +1
ld a,1 +1;
ld a,1 +1 ;
ld a,1 +1 ;
ld a,1 +1 ;
ld a,1 +1
ld a,1 +1;
ld a,1 +1 ;
ld a,1 +1 ;
ld a,1 +1 ;
ld a,1 +1
ld a,1 +1;
ld a,1 +1 ;
ld a,1 +1 ;
ld a,1 +1 ;
ld a,1 +1
ld a,1 +1;
ld a,1 +1 ;
ld a,1 +1 ;
ld a,1 +1 ;
; spacing within operator, 2nd term
ld a,1+ 1
ld a,1+ 1;
ld a,1+ 1 ;
ld a,1+ 1 ;
ld a,1+ 1 ;
ld a,1+ 1
ld a,1+ 1;
ld a,1+ 1 ;
ld a,1+ 1 ;
ld a,1+ 1 ;
ld a,1+ 1
ld a,1+ 1;
ld a,1+ 1 ;
ld a,1+ 1 ;
ld a,1+ 1 ;
ld a,1+ 1
ld a,1+ 1;
ld a,1+ 1 ;
ld a,1+ 1 ;
ld a,1+ 1 ;
ld a,1+ 1
ld a,1+ 1;
ld a,1+ 1 ;
ld a,1+ 1 ;
ld a,1+ 1 ;
; combined spacing within operator
ld a,1 + 1
ld a,1 + 1;
ld a,1 + 1 ;
ld a,1 + 1 ;
ld a,1 + 1 ;
ld a,1 + 1
ld a,1 + 1;
ld a,1 + 1 ;
ld a,1 + 1 ;
ld a,1 + 1 ;
ld a,1 + 1
ld a,1 + 1;
ld a,1 + 1 ;
ld a,1 + 1 ;
ld a,1 + 1 ;
ld a,1 + 1
ld a,1 + 1;
ld a,1 + 1 ;
ld a,1 + 1 ;
ld a,1 + 1 ;
|
AgonPlatform/agon-ez80asm
| 2,129
|
tests/Parser/tests/compound.s
|
; line with label, opcode, tokens
; objective: check parser handling of spacing and parsing of basic tokens
;
; regular spaces, without comments
label1:ld a ,b
;label2:ld.lil a,(5)
label3: ld a,b
label4: ld a, b
label5: ld a, b
label6: ld a, b
; with tabs
label7: ld a , b
; with comments
label8: ld a,b;comment
label9: ld a,b ;comment
labela: ld a,b ; comment
; empty line
; simple opcodes spaced between labels
labelb:
ld a,b
ld b,c
labelc:
ld a,b
ld b,c
; register indirect with spaces
ld a,(bc)
ld a,(de)
ld a,(hl)
ld a, (hl)
ld a ,(hl)
ld a , (hl)
ld a, ( bc)
ld a, ( de)
ld a, ( hl)
ld a, (bc )
ld a, (de )
ld a, (hl )
ld a, ( bc )
ld a, ( de )
ld a, ( hl )
ld a,(ix+1)
ld a,(ix-1)
ld a,( ix+1)
ld a,( ix+1 )
ld a,(ix+1 )
ld a,(ix-1 )
ld a,(ix+ 1)
ld a,(ix- 1)
ld a,(ix +1)
ld a,(ix -1)
ld a,(ix + 1)
ld a,( ix + 1)
ld a,(iy+1) ; iy has separate parsing code
ld a,( iy+1)
ld a,( iy+1 )
ld a,(iy+1 )
ld a,(iy+ 1)
ld a,(iy +1)
ld a,(iy + 1)
ld a,( iy + 1)
; register indirect with tabs
ld a,(hl)
ld a, (hl)
ld a ,(hl)
ld a , (hl)
ld a, ( bc)
ld a, ( de)
ld a, ( hl)
ld a, (bc )
ld a, (de )
ld a, (hl )
ld a, ( bc )
ld a, ( de )
ld a, ( hl )
ld a,(ix+1)
ld a,(ix-1)
ld a,( ix+1)
ld a,( ix+1 )
ld a,(ix+1 )
ld a,(ix-1 )
ld a,(ix+ 1)
ld a,(ix- 1)
ld a,(ix +1)
ld a,(ix -1)
ld a,(ix + 1)
ld a,( ix + 1)
ld a,(iy+1) ; iy has separate parsing code
ld a,( iy+1)
ld a,( iy+1 )
ld a,(iy+1 )
ld a,(iy+ 1)
ld a,(iy +1)
ld a,(iy + 1)
ld a,( iy + 1)
; simple number parsing with spaces and tabs
ld a, ffh
ld a, ffh
ld a, ffh ; with comment
ld a, ffh
ld a, ffh
ld a, ffh ; with comment
; simple indirect number parsing with spaces and tabs
ld (50000h),a
ld (50000h), a
ld (50000h), a
ld (50000h) ,a
ld (50000h) ,a
ld ( 50000h),a
ld ( 50000h),a
ld ( 50000h ),a
ld ( 50000h ),a
|
AgonPlatform/agon-ez80asm
| 17,079
|
tests/Numbers/tests/compound_binarytest.s
|
; line with label, opcode, tokens
; objective: correct parsing of different number systems
;
; Basic 1-byte number tests
.org $40000
; Hexadecimal
ld a, 0xa
ld a, 0xA
ld a, 0XA
ld a, 0x0A
ld a, 0X0A
ld a, 0x00A ; test overflow test in operand parsing
ld a, 0X00A
ld a, #A
ld a, #0A
ld a, #00A
ld a, $A
ld a, $0A
ld a, $00A
ld a, Ah
ld a, AH
ld a, 0Ah
ld a, 0AH
ld a, 00Ah
ld a, 00AH
ld a, 0bh ; weird case, needs priority before binary
ld a, 0bH
ld a, 0b0h ; idem
ld a, 0b0H
ld a, 0b1h ; idem
ld a, 0b1H
; all numbers for safety
ld a, 0h
ld a, 1h
ld a, 2h
ld a, 3h
ld a, 4h
ld a, 5h
ld a, 6h
ld a, 7h
ld a, 8h
ld a, 9h
ld a, ah
ld a, bh
ld a, ch
ld a, dh
ld a, eh
ld a, fh
ld a, 00h
ld a, 01h
ld a, 02h
ld a, 03h
ld a, 04h
ld a, 05h
ld a, 06h
ld a, 07h
ld a, 08h
ld a, 09h
ld a, 0ah
ld a, 0bh
ld a, 0ch
ld a, 0dh
ld a, 0eh
ld a, 0fh
ld a, 10h
ld a, 11h
ld a, 12h
ld a, 13h
ld a, 14h
ld a, 15h
ld a, 16h
ld a, 17h
ld a, 18h
ld a, 19h
ld a, 1ah
ld a, 1bh
ld a, 1ch
ld a, 1dh
ld a, 1eh
ld a, 1fh
ld a, 20h
ld a, 21h
ld a, 22h
ld a, 23h
ld a, 24h
ld a, 25h
ld a, 26h
ld a, 27h
ld a, 28h
ld a, 29h
ld a, 2ah
ld a, 2bh
ld a, 2ch
ld a, 2dh
ld a, 2eh
ld a, 2fh
ld a, 30h
ld a, 31h
ld a, 32h
ld a, 33h
ld a, 34h
ld a, 35h
ld a, 36h
ld a, 37h
ld a, 38h
ld a, 39h
ld a, 3ah
ld a, 3bh
ld a, 3ch
ld a, 3dh
ld a, 3eh
ld a, 3fh
ld a, 40h
ld a, 41h
ld a, 42h
ld a, 43h
ld a, 44h
ld a, 45h
ld a, 46h
ld a, 47h
ld a, 48h
ld a, 49h
ld a, 4ah
ld a, 4bh
ld a, 4ch
ld a, 4dh
ld a, 4eh
ld a, 4fh
ld a, 50h
ld a, 51h
ld a, 52h
ld a, 53h
ld a, 54h
ld a, 55h
ld a, 56h
ld a, 57h
ld a, 58h
ld a, 59h
ld a, 5ah
ld a, 5bh
ld a, 5ch
ld a, 5dh
ld a, 5eh
ld a, 5fh
ld a, 60h
ld a, 61h
ld a, 62h
ld a, 63h
ld a, 64h
ld a, 65h
ld a, 66h
ld a, 67h
ld a, 68h
ld a, 69h
ld a, 6ah
ld a, 6bh
ld a, 6ch
ld a, 6dh
ld a, 6eh
ld a, 6fh
ld a, 70h
ld a, 71h
ld a, 72h
ld a, 73h
ld a, 74h
ld a, 75h
ld a, 76h
ld a, 77h
ld a, 78h
ld a, 79h
ld a, 7ah
ld a, 7bh
ld a, 7ch
ld a, 7dh
ld a, 7eh
ld a, 7fh
ld a, 80h
ld a, 81h
ld a, 82h
ld a, 83h
ld a, 84h
ld a, 85h
ld a, 86h
ld a, 87h
ld a, 88h
ld a, 89h
ld a, 8ah
ld a, 8bh
ld a, 8ch
ld a, 8dh
ld a, 8eh
ld a, 8fh
ld a, 90h
ld a, 91h
ld a, 92h
ld a, 93h
ld a, 94h
ld a, 95h
ld a, 96h
ld a, 97h
ld a, 98h
ld a, 99h
ld a, 9ah
ld a, 9bh
ld a, 9ch
ld a, 9dh
ld a, 9eh
ld a, 9fh
ld a, a0h
ld a, a1h
ld a, a2h
ld a, a3h
ld a, a4h
ld a, a5h
ld a, a6h
ld a, a7h
ld a, a8h
ld a, a9h
ld a, aah
ld a, abh
ld a, ach
ld a, adh
ld a, aeh
ld a, afh
ld a, b0h
ld a, b1h
ld a, b2h
ld a, b3h
ld a, b4h
ld a, b5h
ld a, b6h
ld a, b7h
ld a, b8h
ld a, b9h
ld a, bah
ld a, bbh
ld a, bch
ld a, bdh
ld a, beh
ld a, bfh
ld a, c0h
ld a, c1h
ld a, c2h
ld a, c3h
ld a, c4h
ld a, c5h
ld a, c6h
ld a, c7h
ld a, c8h
ld a, c9h
ld a, cah
ld a, cbh
ld a, cch
ld a, cdh
ld a, ceh
ld a, cfh
ld a, d0h
ld a, d1h
ld a, d2h
ld a, d3h
ld a, d4h
ld a, d5h
ld a, d6h
ld a, d7h
ld a, d8h
ld a, d9h
ld a, dah
ld a, dbh
ld a, dch
ld a, ddh
ld a, deh
ld a, dfh
ld a, e0h
ld a, e1h
ld a, e2h
ld a, e3h
ld a, e4h
ld a, e5h
ld a, e6h
ld a, e7h
ld a, e8h
ld a, e9h
ld a, eah
ld a, ebh
ld a, ech
ld a, edh
ld a, eeh
ld a, efh
ld a, f0h
ld a, f1h
ld a, f2h
ld a, f3h
ld a, f4h
ld a, f5h
ld a, f6h
ld a, f7h
ld a, f8h
ld a, f9h
ld a, fah
ld a, fbh
ld a, fch
ld a, fdh
ld a, feh
ld a, ffh
ld a, $0
ld a, $1
ld a, $2
ld a, $3
ld a, $4
ld a, $5
ld a, $6
ld a, $7
ld a, $8
ld a, $9
ld a, $a
ld a, $b
ld a, $c
ld a, $d
ld a, $e
ld a, $f
ld a, $00
ld a, $01
ld a, $02
ld a, $03
ld a, $04
ld a, $05
ld a, $06
ld a, $07
ld a, $08
ld a, $09
ld a, $0a
ld a, $0b
ld a, $0c
ld a, $0d
ld a, $0e
ld a, $0f
ld a, $10
ld a, $11
ld a, $12
ld a, $13
ld a, $14
ld a, $15
ld a, $16
ld a, $17
ld a, $18
ld a, $19
ld a, $1a
ld a, $1b
ld a, $1c
ld a, $1d
ld a, $1e
ld a, $1f
ld a, $20
ld a, $21
ld a, $22
ld a, $23
ld a, $24
ld a, $25
ld a, $26
ld a, $27
ld a, $28
ld a, $29
ld a, $2a
ld a, $2b
ld a, $2c
ld a, $2d
ld a, $2e
ld a, $2f
ld a, $30
ld a, $31
ld a, $32
ld a, $33
ld a, $34
ld a, $35
ld a, $36
ld a, $37
ld a, $38
ld a, $39
ld a, $3a
ld a, $3b
ld a, $3c
ld a, $3d
ld a, $3e
ld a, $3f
ld a, $40
ld a, $41
ld a, $42
ld a, $43
ld a, $44
ld a, $45
ld a, $46
ld a, $47
ld a, $48
ld a, $49
ld a, $4a
ld a, $4b
ld a, $4c
ld a, $4d
ld a, $4e
ld a, $4f
ld a, $50
ld a, $51
ld a, $52
ld a, $53
ld a, $54
ld a, $55
ld a, $56
ld a, $57
ld a, $58
ld a, $59
ld a, $5a
ld a, $5b
ld a, $5c
ld a, $5d
ld a, $5e
ld a, $5f
ld a, $60
ld a, $61
ld a, $62
ld a, $63
ld a, $64
ld a, $65
ld a, $66
ld a, $67
ld a, $68
ld a, $69
ld a, $6a
ld a, $6b
ld a, $6c
ld a, $6d
ld a, $6e
ld a, $6f
ld a, $70
ld a, $71
ld a, $72
ld a, $73
ld a, $74
ld a, $75
ld a, $76
ld a, $77
ld a, $78
ld a, $79
ld a, $7a
ld a, $7b
ld a, $7c
ld a, $7d
ld a, $7e
ld a, $7f
ld a, $80
ld a, $81
ld a, $82
ld a, $83
ld a, $84
ld a, $85
ld a, $86
ld a, $87
ld a, $88
ld a, $89
ld a, $8a
ld a, $8b
ld a, $8c
ld a, $8d
ld a, $8e
ld a, $8f
ld a, $90
ld a, $91
ld a, $92
ld a, $93
ld a, $94
ld a, $95
ld a, $96
ld a, $97
ld a, $98
ld a, $99
ld a, $9a
ld a, $9b
ld a, $9c
ld a, $9d
ld a, $9e
ld a, $9f
ld a, $a0
ld a, $a1
ld a, $a2
ld a, $a3
ld a, $a4
ld a, $a5
ld a, $a6
ld a, $a7
ld a, $a8
ld a, $a9
ld a, $aa
ld a, $ab
ld a, $ac
ld a, $ad
ld a, $ae
ld a, $af
ld a, $b0
ld a, $b1
ld a, $b2
ld a, $b3
ld a, $b4
ld a, $b5
ld a, $b6
ld a, $b7
ld a, $b8
ld a, $b9
ld a, $ba
ld a, $bb
ld a, $bc
ld a, $bd
ld a, $be
ld a, $bf
ld a, $c0
ld a, $c1
ld a, $c2
ld a, $c3
ld a, $c4
ld a, $c5
ld a, $c6
ld a, $c7
ld a, $c8
ld a, $c9
ld a, $ca
ld a, $cb
ld a, $cc
ld a, $cd
ld a, $ce
ld a, $cf
ld a, $d0
ld a, $d1
ld a, $d2
ld a, $d3
ld a, $d4
ld a, $d5
ld a, $d6
ld a, $d7
ld a, $d8
ld a, $d9
ld a, $da
ld a, $db
ld a, $dc
ld a, $dd
ld a, $de
ld a, $df
ld a, $e0
ld a, $e1
ld a, $e2
ld a, $e3
ld a, $e4
ld a, $e5
ld a, $e6
ld a, $e7
ld a, $e8
ld a, $e9
ld a, $ea
ld a, $eb
ld a, $ec
ld a, $ed
ld a, $ee
ld a, $ef
ld a, $f0
ld a, $f1
ld a, $f2
ld a, $f3
ld a, $f4
ld a, $f5
ld a, $f6
ld a, $f7
ld a, $f8
ld a, $f9
ld a, $fa
ld a, $fb
ld a, $fc
ld a, $fd
ld a, $fe
ld a, $ff
ld a, #0
ld a, #1
ld a, #2
ld a, #3
ld a, #4
ld a, #5
ld a, #6
ld a, #7
ld a, #8
ld a, #9
ld a, #a
ld a, #b
ld a, #c
ld a, #d
ld a, #e
ld a, #f
ld a, #00
ld a, #01
ld a, #02
ld a, #03
ld a, #04
ld a, #05
ld a, #06
ld a, #07
ld a, #08
ld a, #09
ld a, #0a
ld a, #0b
ld a, #0c
ld a, #0d
ld a, #0e
ld a, #0f
ld a, #10
ld a, #11
ld a, #12
ld a, #13
ld a, #14
ld a, #15
ld a, #16
ld a, #17
ld a, #18
ld a, #19
ld a, #1a
ld a, #1b
ld a, #1c
ld a, #1d
ld a, #1e
ld a, #1f
ld a, #20
ld a, #21
ld a, #22
ld a, #23
ld a, #24
ld a, #25
ld a, #26
ld a, #27
ld a, #28
ld a, #29
ld a, #2a
ld a, #2b
ld a, #2c
ld a, #2d
ld a, #2e
ld a, #2f
ld a, #30
ld a, #31
ld a, #32
ld a, #33
ld a, #34
ld a, #35
ld a, #36
ld a, #37
ld a, #38
ld a, #39
ld a, #3a
ld a, #3b
ld a, #3c
ld a, #3d
ld a, #3e
ld a, #3f
ld a, #40
ld a, #41
ld a, #42
ld a, #43
ld a, #44
ld a, #45
ld a, #46
ld a, #47
ld a, #48
ld a, #49
ld a, #4a
ld a, #4b
ld a, #4c
ld a, #4d
ld a, #4e
ld a, #4f
ld a, #50
ld a, #51
ld a, #52
ld a, #53
ld a, #54
ld a, #55
ld a, #56
ld a, #57
ld a, #58
ld a, #59
ld a, #5a
ld a, #5b
ld a, #5c
ld a, #5d
ld a, #5e
ld a, #5f
ld a, #60
ld a, #61
ld a, #62
ld a, #63
ld a, #64
ld a, #65
ld a, #66
ld a, #67
ld a, #68
ld a, #69
ld a, #6a
ld a, #6b
ld a, #6c
ld a, #6d
ld a, #6e
ld a, #6f
ld a, #70
ld a, #71
ld a, #72
ld a, #73
ld a, #74
ld a, #75
ld a, #76
ld a, #77
ld a, #78
ld a, #79
ld a, #7a
ld a, #7b
ld a, #7c
ld a, #7d
ld a, #7e
ld a, #7f
ld a, #80
ld a, #81
ld a, #82
ld a, #83
ld a, #84
ld a, #85
ld a, #86
ld a, #87
ld a, #88
ld a, #89
ld a, #8a
ld a, #8b
ld a, #8c
ld a, #8d
ld a, #8e
ld a, #8f
ld a, #90
ld a, #91
ld a, #92
ld a, #93
ld a, #94
ld a, #95
ld a, #96
ld a, #97
ld a, #98
ld a, #99
ld a, #9a
ld a, #9b
ld a, #9c
ld a, #9d
ld a, #9e
ld a, #9f
ld a, #a0
ld a, #a1
ld a, #a2
ld a, #a3
ld a, #a4
ld a, #a5
ld a, #a6
ld a, #a7
ld a, #a8
ld a, #a9
ld a, #aa
ld a, #ab
ld a, #ac
ld a, #ad
ld a, #ae
ld a, #af
ld a, #b0
ld a, #b1
ld a, #b2
ld a, #b3
ld a, #b4
ld a, #b5
ld a, #b6
ld a, #b7
ld a, #b8
ld a, #b9
ld a, #ba
ld a, #bb
ld a, #bc
ld a, #bd
ld a, #be
ld a, #bf
ld a, #c0
ld a, #c1
ld a, #c2
ld a, #c3
ld a, #c4
ld a, #c5
ld a, #c6
ld a, #c7
ld a, #c8
ld a, #c9
ld a, #ca
ld a, #cb
ld a, #cc
ld a, #cd
ld a, #ce
ld a, #cf
ld a, #d0
ld a, #d1
ld a, #d2
ld a, #d3
ld a, #d4
ld a, #d5
ld a, #d6
ld a, #d7
ld a, #d8
ld a, #d9
ld a, #da
ld a, #db
ld a, #dc
ld a, #dd
ld a, #de
ld a, #df
ld a, #e0
ld a, #e1
ld a, #e2
ld a, #e3
ld a, #e4
ld a, #e5
ld a, #e6
ld a, #e7
ld a, #e8
ld a, #e9
ld a, #ea
ld a, #eb
ld a, #ec
ld a, #ed
ld a, #ee
ld a, #ef
ld a, #f0
ld a, #f1
ld a, #f2
ld a, #f3
ld a, #f4
ld a, #f5
ld a, #f6
ld a, #f7
ld a, #f8
ld a, #f9
ld a, #fa
ld a, #fb
ld a, #fc
ld a, #fd
ld a, #fe
ld a, #ff
ld a, 0x0
ld a, 0x1
ld a, 0x2
ld a, 0x3
ld a, 0x4
ld a, 0x5
ld a, 0x6
ld a, 0x7
ld a, 0x8
ld a, 0x9
ld a, 0xa
ld a, 0xb
ld a, 0xc
ld a, 0xd
ld a, 0xe
ld a, 0xf
ld a, 0x00
ld a, 0x01
ld a, 0x02
ld a, 0x03
ld a, 0x04
ld a, 0x05
ld a, 0x06
ld a, 0x07
ld a, 0x08
ld a, 0x09
ld a, 0x0a
ld a, 0x0b
ld a, 0x0c
ld a, 0x0d
ld a, 0x0e
ld a, 0x0f
ld a, 0x10
ld a, 0x11
ld a, 0x12
ld a, 0x13
ld a, 0x14
ld a, 0x15
ld a, 0x16
ld a, 0x17
ld a, 0x18
ld a, 0x19
ld a, 0x1a
ld a, 0x1b
ld a, 0x1c
ld a, 0x1d
ld a, 0x1e
ld a, 0x1f
ld a, 0x20
ld a, 0x21
ld a, 0x22
ld a, 0x23
ld a, 0x24
ld a, 0x25
ld a, 0x26
ld a, 0x27
ld a, 0x28
ld a, 0x29
ld a, 0x2a
ld a, 0x2b
ld a, 0x2c
ld a, 0x2d
ld a, 0x2e
ld a, 0x2f
ld a, 0x30
ld a, 0x31
ld a, 0x32
ld a, 0x33
ld a, 0x34
ld a, 0x35
ld a, 0x36
ld a, 0x37
ld a, 0x38
ld a, 0x39
ld a, 0x3a
ld a, 0x3b
ld a, 0x3c
ld a, 0x3d
ld a, 0x3e
ld a, 0x3f
ld a, 0x40
ld a, 0x41
ld a, 0x42
ld a, 0x43
ld a, 0x44
ld a, 0x45
ld a, 0x46
ld a, 0x47
ld a, 0x48
ld a, 0x49
ld a, 0x4a
ld a, 0x4b
ld a, 0x4c
ld a, 0x4d
ld a, 0x4e
ld a, 0x4f
ld a, 0x50
ld a, 0x51
ld a, 0x52
ld a, 0x53
ld a, 0x54
ld a, 0x55
ld a, 0x56
ld a, 0x57
ld a, 0x58
ld a, 0x59
ld a, 0x5a
ld a, 0x5b
ld a, 0x5c
ld a, 0x5d
ld a, 0x5e
ld a, 0x5f
ld a, 0x60
ld a, 0x61
ld a, 0x62
ld a, 0x63
ld a, 0x64
ld a, 0x65
ld a, 0x66
ld a, 0x67
ld a, 0x68
ld a, 0x69
ld a, 0x6a
ld a, 0x6b
ld a, 0x6c
ld a, 0x6d
ld a, 0x6e
ld a, 0x6f
ld a, 0x70
ld a, 0x71
ld a, 0x72
ld a, 0x73
ld a, 0x74
ld a, 0x75
ld a, 0x76
ld a, 0x77
ld a, 0x78
ld a, 0x79
ld a, 0x7a
ld a, 0x7b
ld a, 0x7c
ld a, 0x7d
ld a, 0x7e
ld a, 0x7f
ld a, 0x80
ld a, 0x81
ld a, 0x82
ld a, 0x83
ld a, 0x84
ld a, 0x85
ld a, 0x86
ld a, 0x87
ld a, 0x88
ld a, 0x89
ld a, 0x8a
ld a, 0x8b
ld a, 0x8c
ld a, 0x8d
ld a, 0x8e
ld a, 0x8f
ld a, 0x90
ld a, 0x91
ld a, 0x92
ld a, 0x93
ld a, 0x94
ld a, 0x95
ld a, 0x96
ld a, 0x97
ld a, 0x98
ld a, 0x99
ld a, 0x9a
ld a, 0x9b
ld a, 0x9c
ld a, 0x9d
ld a, 0x9e
ld a, 0x9f
ld a, 0xa0
ld a, 0xa1
ld a, 0xa2
ld a, 0xa3
ld a, 0xa4
ld a, 0xa5
ld a, 0xa6
ld a, 0xa7
ld a, 0xa8
ld a, 0xa9
ld a, 0xaa
ld a, 0xab
ld a, 0xac
ld a, 0xad
ld a, 0xae
ld a, 0xaf
ld a, 0xb0
ld a, 0xb1
ld a, 0xb2
ld a, 0xb3
ld a, 0xb4
ld a, 0xb5
ld a, 0xb6
ld a, 0xb7
ld a, 0xb8
ld a, 0xb9
ld a, 0xba
ld a, 0xbb
ld a, 0xbc
ld a, 0xbd
ld a, 0xbe
ld a, 0xbf
ld a, 0xc0
ld a, 0xc1
ld a, 0xc2
ld a, 0xc3
ld a, 0xc4
ld a, 0xc5
ld a, 0xc6
ld a, 0xc7
ld a, 0xc8
ld a, 0xc9
ld a, 0xca
ld a, 0xcb
ld a, 0xcc
ld a, 0xcd
ld a, 0xce
ld a, 0xcf
ld a, 0xd0
ld a, 0xd1
ld a, 0xd2
ld a, 0xd3
ld a, 0xd4
ld a, 0xd5
ld a, 0xd6
ld a, 0xd7
ld a, 0xd8
ld a, 0xd9
ld a, 0xda
ld a, 0xdb
ld a, 0xdc
ld a, 0xdd
ld a, 0xde
ld a, 0xdf
ld a, 0xe0
ld a, 0xe1
ld a, 0xe2
ld a, 0xe3
ld a, 0xe4
ld a, 0xe5
ld a, 0xe6
ld a, 0xe7
ld a, 0xe8
ld a, 0xe9
ld a, 0xea
ld a, 0xeb
ld a, 0xec
ld a, 0xed
ld a, 0xee
ld a, 0xef
ld a, 0xf0
ld a, 0xf1
ld a, 0xf2
ld a, 0xf3
ld a, 0xf4
ld a, 0xf5
ld a, 0xf6
ld a, 0xf7
ld a, 0xf8
ld a, 0xf9
ld a, 0xfa
ld a, 0xfb
ld a, 0xfc
ld a, 0xfd
ld a, 0xfe
ld a, 0xff
; Binary
ld a, 0b0
ld a, 0B0
ld a, 0b1
ld a, 0B1
ld a, 0b01
ld a, 0B01
ld a, 0b10
ld a, 0B10
ld a, 0b11111111
ld a, 0B11111111
ld a, 0b00000000
ld a, 0B00000000
ld a, 0b000000001 ; test overflow test in operand parsing
ld a, 0B000000001
ld a, %0
ld a, %1
ld a, %01
ld a, %10
ld a, %11111111
ld a, %00000000
ld a, %000000001 ; test overflow test in operand parsing
ld a, 0b
ld a, 0B
ld a, 1b
ld a, 1B
ld a, 01b
ld a, 01B
ld a, 10b
ld a, 10B
ld a, 11111111b
ld a, 11111111B
ld a, 00000000b
ld a, 00000000B
ld a, 000000001b ; test overflow test in operand parsing
ld a, 000000001B
; Decimal
ld a, 00
ld a, 01
ld a, 02
ld a, 03
ld a, 04
ld a, 05
ld a, 06
ld a, 07
ld a, 08
ld a, 09
ld a, 0
ld a, 1
ld a, 2
ld a, 3
ld a, 4
ld a, 5
ld a, 6
ld a, 7
ld a, 8
ld a, 9
ld a, 128
ld a, 255
|
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