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stringlengths 5
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AgonPlatform/agon-ez80asm
| 2,783
|
tests/Numbers/tests/all_char_literals.s
|
; Escaped characters
LD A, '\a'
LD A, '\b'
LD A, '\e'
LD A, '\f'
LD A, '\n'
LD A, '\r'
LD A, '\t'
LD A, '\v'
LD A, '\\'
LD A, '\''
LD A, '\"'
LD A, '\?'
; Normal characters
LD A, ' '
LD A, '!'
LD A, '"'
LD A, '#'
LD A, '$'
LD A, '%'
LD A, '&'
LD A, '\''
LD A, '('
LD A, ')'
LD A, '*'
LD A, '+'
LD A, ','
LD A, '-'
LD A, '.'
LD A, '/'
LD A, '0'
LD A, '1'
LD A, '2'
LD A, '3'
LD A, '4'
LD A, '5'
LD A, '6'
LD A, '7'
LD A, '8'
LD A, '9'
LD A, ':'
LD A, ';'
LD A, '<'
LD A, '='
LD A, '>'
LD A, '?'
LD A, '@'
LD A, 'A'
LD A, 'B'
LD A, 'C'
LD A, 'D'
LD A, 'E'
LD A, 'F'
LD A, 'G'
LD A, 'H'
LD A, 'I'
LD A, 'J'
LD A, 'K'
LD A, 'L'
LD A, 'M'
LD A, 'N'
LD A, 'O'
LD A, 'P'
LD A, 'Q'
LD A, 'R'
LD A, 'S'
LD A, 'T'
LD A, 'U'
LD A, 'V'
LD A, 'W'
LD A, 'X'
LD A, 'Y'
LD A, 'Z'
LD A, '['
LD A, '\'
LD A, ']'
LD A, '^'
LD A, '_'
LD A, '`'
LD A, 'a'
LD A, 'b'
LD A, 'c'
LD A, 'd'
LD A, 'e'
LD A, 'f'
LD A, 'g'
LD A, 'h'
LD A, 'i'
LD A, 'j'
LD A, 'k'
LD A, 'l'
LD A, 'm'
LD A, 'n'
LD A, 'o'
LD A, 'p'
LD A, 'q'
LD A, 'r'
LD A, 's'
LD A, 't'
LD A, 'u'
LD A, 'v'
LD A, 'w'
LD A, 'x'
LD A, 'y'
LD A, 'z'
LD A, '{'
LD A, '|'
LD A, '}'
LD A, '~'
; Escaped characters
DB '\a'
DB '\b'
DB '\e'
DB '\f'
DB '\n'
DB '\r'
DB '\t'
DB '\v'
DB '\\'
DB '\''
DB '\"'
DB '\?'
; Normal characters
DB ' '
DB '!'
DB '"'
DB '#'
DB '$'
DB '%'
DB '&'
DB '\''
DB '('
DB ')'
DB '*'
DB '+'
DB ','
DB '-'
DB '.'
DB '/'
DB '0'
DB '1'
DB '2'
DB '3'
DB '4'
DB '5'
DB '6'
DB '7'
DB '8'
DB '9'
DB ':'
DB ';'
DB '<'
DB '='
DB '>'
DB '?'
DB '@'
DB 'A'
DB 'B'
DB 'C'
DB 'D'
DB 'E'
DB 'F'
DB 'G'
DB 'H'
DB 'I'
DB 'J'
DB 'K'
DB 'L'
DB 'M'
DB 'N'
DB 'O'
DB 'P'
DB 'Q'
DB 'R'
DB 'S'
DB 'T'
DB 'U'
DB 'V'
DB 'W'
DB 'X'
DB 'Y'
DB 'Z'
DB '['
DB '\'
DB ']'
DB '^'
DB '_'
DB '`'
DB 'a'
DB 'b'
DB 'c'
DB 'd'
DB 'e'
DB 'f'
DB 'g'
DB 'h'
DB 'i'
DB 'j'
DB 'k'
DB 'l'
DB 'm'
DB 'n'
DB 'o'
DB 'p'
DB 'q'
DB 'r'
DB 's'
DB 't'
DB 'u'
DB 'v'
DB 'w'
DB 'x'
DB 'y'
DB 'z'
DB '{'
DB '|'
DB '}'
DB '~'
|
AgonPlatform/agon-ez80asm
| 1,173
|
tests/Value_operators/tests/bracket_compound.s
|
; All values should result in zero
; Testing basic bracket functionality including spacing tolerances in the parser
ld a, [0]
ld a, [ 0]
ld a, [0 ]
ld a, [ 0 ]
ld a, [ 0 ];tab
ld a, [1-1]
ld a, [ 1-1 ]
ld a, [ 1 -1]
ld a, [ 1 -1 ]
ld a, [ 1 - 1]
ld a, [ 1 - 1 ]
ld a, 5-[5]
ld a, 5- [5]
ld a, 5 -[5]
ld a, 5 - [5]
ld a, 5 - [ 5]
ld a, 5 - [5 ]
ld a, 5 - [ 5 ]
ld a, -5+[5]
ld a, -5+ [5]
ld a, -5 +[5]
ld a, -5 + [5]
ld a, -5 + [ 5]
ld a, -5 + [5 ]
ld a, -5 + [ 5 ]
ld a, 42-[2*12]-18
ld a, 42- [2*12]-18
ld a, 42 -[2*12]-18
ld a, 42 - [2*12]-18
ld a, 42 - [ 2*12]-18
ld a, 42 - [2*12 ]-18
ld a, 42 - [ 2*12 ]-18
ld a, 42 - [ 2 * 12 ]-18
ld a, 42-[2*12] -18
ld a, 42-[2*12]- 18
ld a, 42-[2*12] - 18
; Testing order of operations using brackets
ld a, [1-1]*64
ld a, 64*[1-1]
ld a, 64*[1-0]-64
ld a, 64*[2/2]-[64/1]
; Testing nested brackets
ld a, 20-[[[10*2]]]
ld a, 20-[40-[10*2]]
ld a, 20-[60-[10*2]-20]
ld a, 20-[60-[10*2]-20] + 5*[20-[2*10]]
ld a, [20-[60-[10*2]-20] + 5*[20-[2*10]]]
|
AgonPlatform/agon-ez80asm
| 6,351
|
tests/Z_PRG_AgonBits_Lessons/tests/ink.s
|
; Example of MOSlet
.assume adl=1
.org $0B0000 ; NOTE different assemble address for MOSlets
jp start ; We jump over the header
.align 64
.db "MOS"
.db 00h
.db 01h
app_name: .db "ink.bin", 0 ; The executable name, only used in arg1
max_args: EQU 16 ; Maximum number of arguments allowed in argv
arg_pointer: .blkb max_args * 3, 0 ; max 16 x 3 bytes each
num_args: .db 0 ; the number of arguments entered
; ---------------------------------------------
;
; INITIAL SETUP CODE HERE
;
; ---------------------------------------------
start:
push af ; Push all registers to the stack
push bc
push de
push ix
push iy
ld IX, arg_pointer ; The argv array pointer address
push IX
call PARSE_PARAMS ; Parse the parameters
ld a,c ; C contains the number of params entered
ld (num_args),a ; store number of arguments entered
pop IX ; IX: argv
cp 2
jr c, error ; if less than 2 args, then exit
ld de, (ix+3) ; address of first arg, is a 0 terminated string for the file
call STRING2INT ; turn string into a integer we can use
; hl = result, de = pointer to ASCII number
; no error checking, so watch out!
; lower byte L will contain the integer we want to use
ld a, 17
rst.lil $10 ; change ink colour to...
ld a, l
rst.lil $10 ; the value we got back in L
now_exit:
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return MOS
error:
ld hl, errorString ; location of string
call printString
jp now_exit
printString: ; print zero terminated string
ld a,(hl)
or a
ret z
RST.LIL 10h
inc hl
jr printString
errorString:
.db "ERROR - no value entered\n\r",0
; ---------------------------------------------
;
; PARAM PARSING ROUTINE WRITTEN BY OTHERS
;
; ---------------------------------------------
; Parse the parameter string into a C style array
; Parameters
; - HL: Address of parameter string
; - IX: Address for array pointer storage
; Returns:
; - C: Number of parameters parsed
PARSE_PARAMS:
ld BC, app_name
ld (IX+0), BC ; ARGV[0] = the executable name
inc IX
inc IX
inc IX
call skip_spaces ; Skip HL past any leading spaces
ld BC, 1 ; C: ARGC = 1 - also clears out top 16 bits of BCU
ld B, max_args - 1 ; B: Maximum number of arg_pointer
parse_step_2:
push BC ; Stack ARGC
push HL ; Stack start address of token
call get_token ; Get the next token
ld A, C ; A: Length of the token in characters
pop DE ; Start address of token (was in HL)
pop BC ; ARGC
or A ; Check for A=0 (no token found) OR at end of string
ret Z
ld (IX+0), DE ; Store the pointer to the token
push HL ; DE=HL
pop DE
call skip_spaces ; And skip HL past any spaces onto the next character
Xor A
ld (DE), A ; Zero-terminate the token
inc IX
inc IX
inc IX ; Advance to next pointer position
inc C ; Increment ARGC
ld A, C ; Check for C >= A
cp B
jr C, parse_step_2 ; And loop
RET
; ---------------------------------------------
; Skip spaces in the parameter string
; Parameters:
; - HL: Address of parameter string
; Returns:
; - HL: Address of next none-space character
; F: Z if at end of string, otherwise NZ if there are more tokens to be parsed
skip_spaces:
ld A, (HL) ; Get the character from the parameter string
cp ' ' ; Exit if not space
ret NZ
inc HL ; Advance to next character
jr skip_spaces ; Increment length
; ---------------------------------------------
; Get the next token
; Parameters:
; - HL: Address of parameter string
; Returns:
; - HL: Address of first character after token
; - C: Length of token (in characters)
get_token:
ld C, 0 ; Initialise length
token_loop:
ld A, (HL) ; Get the character from the parameter string
or A ; Exit if 0 (end of parameter string in MOS)
ret Z
cp 13 ; Exit if CR (end of parameter string in BBC BASIC)
ret Z
cp ' ' ; Exit if space (end of token)
ret Z
inc HL ; Advance to next character
inc C ; Increment length
jr token_loop
; ---------------------------------------------
;
; STRING TO INTEGER ROUTINE WRITTEN BY OTHERS
;
; ---------------------------------------------
; Takes pointer to a string of ascii representing an integer and converts to 3 byte integer
; hl = result
; de = pointer to ASCII number
STRING2INT:
Ld hl,0
s2i_loop:
ld a,(de)
Sub 48
Jr c,s2i_done
Cp 10
Jr nc,s2i_done
Push hl
Pop bc
Add hl,hl ; x2
Add hl,hl ; x4
Add hl,bc ; x5
Add hl,hl ; x10
Ld bc,0
Ld c,a
Add hl,bc ; Add digit
Inc de ; go to next number
Jr s2i_loop
s2i_done:
ret
; ---------------------------------------------
|
AgonPlatform/agon-ez80asm
| 2,658
|
tests/Z_PRG_AgonBits_Lessons/tests/udg.s
|
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
; Setup UDG character
ld hl, udgData ; address of string to use
ld bc, endUgdData - udgData ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
; prepare the screen
SET_MODE 8 ; mode 8 is 640x480 pixels, 64 colours
SET_COLOUR bright_red ; colours are define at end of this code
TAB_TO 5,10
ld a, alien
rst.lil $10 ; print our UDG
SET_COLOUR blue
SET_BG_COLOUR white
TAB_TO 10,15
; Sending a VDU byte stream
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
; reset the colours
SET_COLOUR bright_white
SET_BG_COLOUR black
; ------------------
; This is where we exit the program
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; UGD data
alien: equ 128
udgData:
.db 23, alien ; define UDG character number
.db 10000010b ; binary data 0
.db 01111100b ; binary data 1
.db 10101010b ; binary data 2
.db 10000010b ; binary data 3
.db 11000110b ; binary data 4
.db 00111000b ; binary data 5
.db 01000100b ; binary data 6
.db 10000010b ; binary data 7
endUgdData:
; ------------------
; This is the text data we send to VDP
VDUdata:
.db "Hello Agon UDGs" ; print this text
.db 13,10 ; CR, LF
endVDUdata:
; ------------------
; colour data
bright_red: equ 9
green: equ 2
blue: equ 4
white: equ 7
black: equ 0
bright_white: equ 15
|
AgonPlatform/agon-ez80asm
| 2,526
|
tests/Z_PRG_AgonBits_Lessons/tests/joystick.s
|
; AGON CONSOLE8
; Joystick Lesson
; Richard Turnnidge 2024
.assume adl=1 ; big memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
; ---------------------------------------------
;
; INITIAL SETUP CODE HERE
;
; ---------------------------------------------
include "myMacros.inc"
include "debug.asm"
start_here:
; store everything as good practice
push af
push bc
push de
push ix
push iy
showTitle:
ld hl, title_str ; data to send
ld bc, end_title - title_str ; lenght of data
rst.lil $18
; ---------------------------------------------
;
; MAIN LOOP
;
; ---------------------------------------------
MAIN_LOOP:
get_key_input:
MOSCALL $08 ; get IX pointer to sysvars
ld a, (ix + 05h) ; ix+5h is 'last key pressed'
cp 27 ; is it ESC key?
jp z, exit_here ; if so exit cleanly
check_joystick:
; needed to clear flags, else it didn't seem to work
ld a,0 ; set A to 0
or a ; clear flags
in a, (portC) ; grab current io value of port C
ld b, 13 ; BC is XY of print position
ld c, 5
call printBin ; display value of port C in BINARY
ld a,0 ; set A to 0
or a ; clear flags
in a, (portD) ; grab current io value of port D
ld b, 13 ; BC is XY of print position
ld c, 7
call printBin
in a, (portD) ; grab current io value of port D
bit 5, a
call nz, sayUp
in a, (portD) ; grab current io value of port D
bit 5, a
call z, sayDown
jp MAIN_LOOP
portC: EQU $9E
portD: EQU $A2
sayDown:
TAB_TO 1,9
ld hl, downTxt
ld bc,0
ld a,0
rst.lil $18
ret
sayUp:
TAB_TO 1,9
ld hl, upTxt
ld bc,0
ld a,0
rst.lil $18
ret
downTxt:
.db "Button DOWN",0
upTxt:
.db "Button UP ",0
; ---------------------------------------------
;
; EXIT CODE CLEANLY
;
; ---------------------------------------------
exit_here:
CLS
; reset all values before returning to MOS
pop iy
pop ix
pop de
pop bc
pop af
ld hl,0
ret ; return to MOS here
; ---------------------------------------------
;
; DATA & STRINGS
;
; ---------------------------------------------
title_str:
.db 12 ; CLS
.db 31,1,1 ; TAB to 0,0
.db "Joystick Lesson z80 assembler" ; text to show
.db 31,8,3 ; TAB to 0,0
.db "Bits:76543210" ; text to show
.db 31,13,4 ; TAB to 0,0
.db "--------" ; text to show
.db 31,1,5 ; TAB to 0,0
.db "eZ80 Port C:" ; text to show
.db 31,1,7 ; TAB to 0,0
.db "eZ80 Port D:" ; text to show
end_title:
|
AgonPlatform/agon-ez80asm
| 1,563
|
tests/Z_PRG_AgonBits_Lessons/tests/usemacros.s
|
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
CLS
SET_COLOUR red
SET_BG_COLOUR green
TAB_TO 15,10
; Sending a VDU byte stream
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
; reset the colours
SET_COLOUR bright_white
SET_BG_COLOUR black
; ------------------
; This is where we exit the program
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; This is the data we send to VDP
VDUdata:
.db "Hello Agon macros\r\n" ; print this text
endVDUdata:
; ------------------
; colour data
red: equ 1
green: equ 2
blue: equ 4
white: equ 7
black: equ 0
bright_white: equ 15
|
AgonPlatform/agon-ez80asm
| 7,611
|
tests/Z_PRG_AgonBits_Lessons/tests/scroll.s
|
; extra MACRO files need to go here
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
; prepare the screen
SET_MODE 8 ; mode 8 is 640x480 pixels, 64 colours
; Sending a VDU byte stream
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ld a, $08 ; code to send to MOS
rst.lil $08 ; get IX pointer to System Variables
; ------------------
LOOP_HERE: ; loop here until we hit ESC key
MOSCALL $1E ; load IX with keymap address
ld a, (ix + $0E)
bit 0, a ; index $0E, bit 0 is for ESC key in matrix
jp nz, EXIT_HERE ; if pressed, ESC key to exit
MOSCALL $1E ; load IX with keymap address
ld a, (ix + $03)
bit 1, a ; index $06 bit 0 is for 'left' key in matrix
call nz, scroll_left ; if pressed, setFrame1
MOSCALL $1E ; load IX with keymap address
ld a, (ix + $0F)
bit 1, a ; index $06 bit 0 is for 'left' key in matrix
call nz, scroll_right ; if pressed, setFrame1
MOSCALL $1E ; load IX with keymap address
ld a, (ix + $07)
bit 1, a ; index $06 bit 0 is for 'left' key in matrix
call nz, scroll_up ; if pressed, setFrame1
MOSCALL $1E ; load IX with keymap address
ld a, (ix + $05)
bit 1, a ; index $06 bit 0 is for 'left' key in matrix
call nz, scroll_down ; if pressed, setFrame1
jp LOOP_HERE
; ------------------
scroll_left:
ld a, 1
ld (scrollDirection), a
call doScroll
ret
scroll_right:
ld a, 0
ld (scrollDirection), a
call doScroll
ret
scroll_up:
ld a, 3
ld (scrollDirection), a
call doScroll
ret
scroll_down:
ld a, 2
ld (scrollDirection), a
call doScroll
ret
; ------------------
doScroll:
ld hl, scrollData ; address of string to use
ld bc, endScrollData - scrollData ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ld a, 00010000b
call multiPurposeDelay
ret
; Scroll the screen
; VDU 23, 7, extent, direction, speed
scrollData:
.db 23, 7, 2 ; extent: 0 = text viewport, 1 = whole screen
; 2 = graphics viewport
scrollDirection: .db 0 ; direction: 0 right, 1 left, 2 down, 3 up
.db 1 ; speed = number of pixels
endScrollData:
; ------------------
; This is where we exit the program
EXIT_HERE:
CLS
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; This is the data we send to VDP
VDUdata:
.db 23, 0, 192, 0 ; set to non-scaled graphics
.db 17, 128 +7 ; background text black
.db 12 ; cls
.db 24 ; set graphics viewport:-
.dw 40, 150, 270, 40 ; 24, left; bottom; right; top;
.db 17, 128 ; background text grey
.db 12 ; cls
; FOR A SINGLE PIXEL PLOT
.db 18, 0, bright_red ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 200,80 ; X; Y;
; FOR A LINE
.db 18, 0, bright_magenta ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 300, 60 ; X; Y;
.db 25, 13 ; PLOT: mode (13 is a line),
.dw 250,130 ; X; Y;
; FOR A RECTANGLE
.db 18, 0, green ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 10,120 ; X; Y;
.db 25, 101 ; PLOT: mode (101 is a filled rectangle),
.dw 100,180 ; X; Y;
; FOR A CIRCLE
.db 18, 0, bright_yellow ; set graphics colour: mode (0), colour
.db 25, 68 ; PLOT: mode (69 is a MOVE TO but don't plot point),
.dw 180,140 ; X; Y;
.db 25, 149 ; PLOT: mode (149 is an outlined circle),
.dw 200,160 ; X; Y;
; FOR A FILLED TRIANGLE
.db 18, 0, blue ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 10,10 ; X; Y;
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 50, 100 ; X; Y;
.db 25, 85 ; PLOT: mode (85 is a filled triangle),
.dw 200,20 ; X; Y;
endVDUdata:
; ------------------
; colour data
bright_red: equ 9
green: equ 2
bright_yellow: equ 11
bright_magenta: equ 13
blue: equ 4
white: equ 7
black: equ 0
bright_white: equ 15
; ------------------
multiPurposeDelay:
push bc
ld b, a
MOSCALL $08 ; get IX pointer to sysvars
waitLoop:
ld a, (ix + 0) ; ix+0h is lowest byte of clock timer
; we check if bit set is same as last time we checked.
; bit 0 - don't use
; bit 1 - changes 64 times per second
; bit 2 - changes 32 times per second
; bit 3 - changes 16 times per second
; bit 4 - changes 8 times per second
; bit 5 - changes 4 times per second
; bit 6 - changes 2 times per second
; bit 7 - changes 1 times per second
and b
ld c,a
ld a, (oldTimeStamp)
cp c ; is A same as last value?
jr z, waitLoop ; loop here if it is
ld a, c
ld (oldTimeStamp), a ; set new value
pop bc
ret
oldTimeStamp: .db 00h
|
AgonPlatform/agon-ez80asm
| 3,913
|
tests/Z_PRG_AgonBits_Lessons/tests/slowdown.s
|
; extra MACRO files need to go here
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
; extra code files need to go here, or later
include "debug.asm"
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; display message
ld d, 0 ; Set D, our counter
LOOP_HERE: ; loop here until we hit ESC or SPACE key
MOSCALL $1E ; load IX with keymap address
ld a, (ix + $0E)
bit 0, a ; index $0E, bit 0 is for ESC key in matrix
jp nz, EXIT_HERE ; if pressed, ESC key to exit
ld a, 00100000b ; put a bit value into A. Only set ONE bit
call multiPurposeDelay ; call the delay routine
ld a, d ; store the counter in A
ld b, 0 ; x position in B
ld c, 6 ; y position in C
call printHexA ; print A to screen in HEX
inc d
jr LOOP_HERE ; go round the loop
; ------------------
; This is the data we send to VDP
VDUdata:
.db 22,8 ; set screen to MODE 8, this will also clear screen
.db 31, 0, 0 ; TAB to 10,20
.db "Clock based delay" ; print this text
.db 31, 0, 2 ; TAB to 10,20
.db "Press ESC to exit\r\n" ; print this text
endVDUdata:
; ------------------
; This is where we exit the program
EXIT_HERE:
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; delay routine
; routine waits a fixed time, then returns
; arrive with A = the delay byte. One bit to be set only.
; eg. ld A, 00000100b
multiPurposeDelay:
push bc
ld b, a
MOSCALL $08 ; get IX pointer to sysvars
waitLoop:
ld a, (ix + 0) ; ix+0h is lowest byte of clock timer
; we check if bit set is same as last time we checked.
; bit 0 - don't use
; bit 1 - changes 64 times per second
; bit 2 - changes 32 times per second
; bit 3 - changes 16 times per second
; bit 4 - changes 8 times per second
; bit 5 - changes 4 times per second
; bit 6 - changes 2 times per second
; bit 7 - changes 1 times per second
and b
ld c,a
ld a, (oldTimeStamp)
cp c ; is A same as last value?
jr z, waitLoop ; loop here if it is
ld a, c
ld (oldTimeStamp), a ; set new value
pop bc
ret
oldTimeStamp: .db 00h
ld a, 00100000b ; put a bit value into A. Only set ONE bit
call multiPurposeDelay ; call the delay routine
|
AgonPlatform/agon-ez80asm
| 2,256
|
tests/Z_PRG_AgonBits_Lessons/tests/showkey.s
|
; extra MACRO files need to go here
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
; extra code files need to go here, or later
include "debug.asm"
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
CLS
ld a, 23 ; HIDE CURSOR
rst.lil $10
ld a, 1
rst.lil $10
ld a,0 ; VDU 23,1,0 = hide the text cursor
rst.lil $10 ; VDU 23,1,1 = show the text cursor
; From 'LESSON 03'
ld a, $08 ; code to send to MOS...
rst.lil $08 ; get IX pointer to System Variables
WAIT_HERE: ; loop here until we hit ESC key
ld a, (ix + $05) ; get ASCII code of LAST key pressed
cp 27 ; check if 27 (ascii code for ESC)
jp z, EXIT_HERE ; if pressed, jump to EXIT_HERE
ld b,10 ; set the X position
ld c,5 ; set the Y position
call printHexA ; display HEX value of A, at TAB B, C
jr WAIT_HERE
; ------------------
; This is where we exit the program
EXIT_HERE:
ld a, 23 ; SHOW CURSOR
rst.lil $10
ld a, 1
rst.lil $10
ld a,1 ; VDU 23,1,0 = hide the text cursor
rst.lil $10 ; VDU 23,1,1 = show the text cursor
CLS
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
|
AgonPlatform/agon-ez80asm
| 1,960
|
tests/Z_PRG_AgonBits_Lessons/tests/getinfo.s
|
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; display message
LOOP_HERE: ; loop here until we hit ESC or SPACE key
ld a, $08
rst.lil $08 ; get IX pointer to sysvars
ld a, (ix + $05)
cp 32 ; 32 is ascii code for SPACE
jp z, EXIT_HERE ; if pressed, SPACE key to exit
ld a, $1E
rst.lil $08 ; get IX pointer to keyvals matrix of pressed keys
ld a, (ix + $0E)
bit 0, a ; index $0E, bit 0 is for ESC key in matrix
jp nz, EXIT_HERE ; if pressed, ESC key to exit
jr LOOP_HERE
; ------------------
; This is where we exit the program
EXIT_HERE:
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; This is the data we send to VDP
VDUdata:
.db 22,4 ; set screen to MODE 8, this will also clear screen
.db 31, 10, 10 ; TAB to 10,20
.db "Press ESC to exit\r\n" ; print this text
endVDUdata:
|
AgonPlatform/agon-ez80asm
| 3,285
|
tests/Z_PRG_AgonBits_Lessons/tests/random.s
|
; extra MACRO files need to go here
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
; extra code files need to go here, or later
include "debug.asm"
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; display message
LOOP_HERE: ; loop here until we hit ESC or SPACE key
MOSCALL $1E ; load IX with keymap address
ld a, (ix + $0E)
bit 0, a ; index $0E, bit 0 is for ESC key in matrix
jp nz, EXIT_HERE ; if pressed, ESC key to exit
ld a, (ix + $0C)
bit 2, a ; index $0C bit 2 is for SPACE key in matrix
call nz, DO_RANDOM ; if pressed, SPACE key to exit
jr LOOP_HERE
; ------------------
DO_RANDOM:
ld a, (ix + $0C)
bit 2, a ; index $0C bit 2 is for SPACE key in matrix
jp nz, DO_RANDOM ; if pressed, SPACE key to exit
call PRINT_RANDOM1
call PRINT_RANDOM2
ret
PRINT_RANDOM1:
MOSCALL $08 ; load IX with sysvars address
ld a, (ix + $0) ; get first byte of clock counter
ld b, 0
ld c, 4
call printHexA ; display it
ret
PRINT_RANDOM2:
; LD A, 0 is created here with two bytes, $3E $00
.db $3E ; start of LD A, number
randSeed:
.db $00 ; 2nd part of LD A, number
push bc
ld c,a
add a,a
add a,c
add a,a
add a,a
add a,c
add a,83
ld (randSeed),a
pop bc
ld b, 0
ld c, 6
call printHexA
ret
; ------------------
; This is the data we send to VDP
VDUdata:
.db 22,8 ; set screen to MODE 8, this will also clear screen
.db 31, 4, 4 ; TAB to 10,20
.db "Clock based randomness" ; print this text
.db 31, 4, 6 ; TAB to 10,20
.db "Random from a seed value" ; print this text
.db 31, 0, 0 ; TAB to 10,20
.db "Press SPACE for new number\r\n" ; print this text
.db "or ESC to exit\r\n" ; print this text
endVDUdata:
; ------------------
; This is where we exit the program
EXIT_HERE:
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
|
AgonPlatform/agon-ez80asm
| 4,971
|
tests/Z_PRG_AgonBits_Lessons/tests/savedata.s
|
; extra MACRO files need to go here
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
; try loading the file
ld hl, filename ; file name
ld de, lastKey ; were to load data
ld bc, 1 ; num bytes to read
MOSCALL $01 ; try to open and read byte from file
ld hl, startText ; print initial text
call printString
ld a, (lastKey)
rst.lil $10 ; print last key saved to file
ld hl, newline ; print initial text
call printString
wait_for_keyup: ; wait for key up state so we only do it once
MOSCALL $08 ; get IX pointer to sysvars
ld a, (ix + 18h) ; get key state
cp 0 ; are keys up, none currently pressed?
jr nz, wait_for_keyup ; loop if there is a key still pressed
LOOP_HERE: ; loop here until we press a key
MOSCALL $08 ; get IX pointer to sysvars
ld a, (ix + 18h) ; get key state, 0 or 1
cp 0 ; are keys up, none currently pressed?
jr z, LOOP_HERE ; nothing is currently pressed
; a key was pressed, so fetch it
MOSCALL $08 ; get IX pointer to sysvars
ld a, (ix + 05h) ; ix+5h is 'last key pressed'
ld (lastKey),a ; store the key value ready to save
; we need to delete the old file first
ld hl, filename ; file name
MOSCALL $05 ; delete call
ld a, 00010000b ; wait a moment for SD to catch up
call multiPurposeDelay
; save new file
ld hl, filename ; file name
ld de, lastKey ; data to save
ld bc, 1 ; num bytes to save
MOSCALL $02 ; save the new file, then EXIT
; ------------------
; This is where we exit the program
EXIT_HERE:
ld hl, exitText
call printString
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------------------------
; DATA AND FUNCTIONS
; ------------------------------------
filename: .db "savedata.ini",0 ; prefs file storing high score
lastKey: .db 32
; ------------------
; This is the text we send to VDP
startText:
.db "Last time you pressed: ",0 ; print this text
newline:
.db "\r\nPress another key...\r\n",0
exitText:
.db "Thanks, Goodbye\r\n",0 ; print this text
; ------------------
printString: ; print zero terminated string
ld a,(hl)
or a
ret z
RST.LIL 10h
inc hl
jr printString
; ------------------
multiPurposeDelay: ; routine to wait for a given time
push bc
ld b, a
MOSCALL $08 ; get IX pointer to sysvars
waitLoop:
ld a, (ix + 0) ; ix+0h is lowest byte of clock timer
; we check if bit set is same as last time we checked.
; bit 0 - don't use
; bit 1 - changes 64 times per second
; bit 2 - changes 32 times per second
; bit 3 - changes 16 times per second
; bit 4 - changes 8 times per second
; bit 5 - changes 4 times per second
; bit 6 - changes 2 times per second
; bit 7 - changes 1 times per second
and b
ld c,a
ld a, (oldTimeStamp)
cp c ; is A same as last value?
jr z, waitLoop ; loop here if it is
ld a, c
ld (oldTimeStamp), a ; set new value
pop bc
ret
oldTimeStamp: .db 00h
|
AgonPlatform/agon-ez80asm
| 5,691
|
tests/Z_PRG_AgonBits_Lessons/tests/getpixel.s
|
; extra MACRO files need to go here
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
; extra code files need to go here, or later
include "debug.asm"
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
; prepare the screen
SET_MODE 8 ; mode 8 is 640x480 pixels, 64 colours
; Sending a VDU byte stream to create some graphics
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
MOSCALL $08 ; set IX pointer to the sysvars
; define which pixel to check ; NOTE pixel positions are WORDS
; so we need to define two bytes
call resetReplyFlag ; make sure Flag is reset
call doPixelQuery ; send the query to find pixel colour
call waitForFlagUpdate ; wait for p flag to be updated
; NOTE (ix + 0A),(ix + 0B),(ix + 0C) contain R,B,G colour values
ld a, (ix + $16) ; (ix + $16) contains the palette index of the colour
ld b, 0 ; set B to X pos
ld c, 0 ; set C to Y pos
call printHexA ; print out what is in A at X, Y
WAIT_HERE: ; loop here until we hit ESC key
ld a, (ix + $05) ; get ASCII code of key pressed
cp 27 ; check if 27 (ascii code for ESC)
jp z, EXIT_HERE ; if pressed, jump to exit
jr WAIT_HERE
; ------------------
; This is where we exit the program
EXIT_HERE:
CLS
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; This is the query we send to VDP
doPixelQuery: ; routine sends request to VDP for pixel colour
ld hl, vduQuery
ld bc, endvduQuery - vduQuery
rst.lil $18
ret
vduQuery:
.db 23,0,$84 ; get pixel of colour at X, Y
vduX: .dw 200 ; X is a word
vduY: .dw 80 ; Y s a word
endvduQuery:
; ---------------------------------------------
resetReplyFlag:
ld a, (ix + $04) ; get flag for point
res 2,a ; reset the P flag
ld (ix + $04), a ; store flag status
ret
waitForFlagUpdate:
ld a, (ix + $04) ; plflags variable
bit 2,a ; bit2 is result from a point query
jr z, waitForFlagUpdate ; if not updated, then wait here
ret
; ---------------------------------------------
VDUdata:
.db 23, 0, 192, 0 ; set to non-scaled graphics
; FOR A SINGLE PIXEL PLOT
.db 18, 0, bright_red ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 200,80 ; X; Y;
; FOR A LINE
.db 18, 0, bright_magenta ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 300, 60 ; X; Y;
.db 25, 13 ; PLOT: mode (13 is a line),
.dw 250,130 ; X; Y;
; FOR A RECTANGLE
.db 18, 0, green ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 10,120 ; X; Y;
.db 25, 101 ; PLOT: mode (101 is a filled rectangle),
.dw 100,180 ; X; Y;
; FOR A CIRCLE
.db 18, 0, bright_yellow ; set graphics colour: mode (0), colour
.db 25, 68 ; PLOT: mode (69 is a MOVE TO but don't plot point),
.dw 180,140 ; X; Y;
.db 25, 149 ; PLOT: mode (149 is an outlined circle),
.dw 200,160 ; X; Y;
; FOR A FILLED TRIANGLE
.db 18, 0, blue ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 10,10 ; X; Y;
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 50, 100 ; X; Y;
.db 25, 85 ; PLOT: mode (85 is a filled triangle),
.dw 200,20 ; X; Y;
endVDUdata:
; ------------------
; colour definitions - palette index colours
bright_red: equ 9
green: equ 2
bright_yellow: equ 11
bright_magenta: equ 13
blue: equ 4
white: equ 7
black: equ 0
bright_white: equ 15
|
AgonPlatform/agon-ez80asm
| 2,717
|
tests/Z_PRG_AgonBits_Lessons/tests/textinput.s
|
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
include "myMacros.inc"
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
CLS ; just CLS
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; display message
ld hl, textBuffer ; HL needs to point to where text will be stored
ld bc, 10 ; BC is maximum nunber of chars
ld e, 1 ; 1 to clear buffer, 0 not to clear
MOSCALL $09 ; call $09 mos_editline
cp 27 ; A gives return code: 27 ESC, 13 CR
jr z, hitEscape
hitEnter:
ld hl, answer ; HL is location of answer to print
jr printAnswer
hitEscape:
ld hl, escaped ; lHL is ocation of 'escaped' text to print
jr printAnswer
printAnswer:
SET_BG_COLOUR 0 ; reset background colour to black
TAB_TO 0, 14 ; go to TAB position
ld bc,0
ld a,0
rst.lil $18 ; print out text stored at HL, terminated in 0
TAB_TO 0, 16 ; go to TAB position
; ------------------
; This is where we exit the program
EXIT_HERE:
ld a, 17
rst.lil $10
ld a, 128
rst.lil $10 ; BG to black
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; This is the data we send to VDP
VDUdata:
.db 31, 0, 10 ; TAB to 10,20
.db "Please enter your name:" ; print this text
.db 31, 0, 12 ; TAB to 10,20
.db 17, 128+4 ; background colour
.blkb 10,32 ; a line of 10 spaces
.db 31, 0, 12 ; TAB to 10,20
endVDUdata:
answer: .db "You typed: "
textBuffer: .blkb 10,0
lineOfSpaces: .blkb 10,32
escaped: .db "You escaped...",0
|
AgonPlatform/agon-ez80asm
| 1,768
|
tests/Z_PRG_AgonBits_Lessons/tests/text.s
|
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
; Sending VDU commands byte by byte
ld a, 22
rst.lil $10 ; set screen mode...
ld a, 8
rst.lil $10 ; to mode 8, 320x240 64 colours
; Sending a VDU byte stream
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
; ------------------
; This is where we exit the program
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; This is the data we send to VDP
VDUdata:
.db 17, 0 ; set text colour, 0 = black, 1 = red, etc
.db 17, 11 + 128 ; set text background, +128 for background
.db 31, 10, 10 ; TAB to 10,20
.db "Hello Agon coders\r\n" ; print this text
.db 17, 15 ; reset text colour, 15 = bright white
.db 17, 0 + 128 ; reset text background, +128 for background
endVDUdata:
|
AgonPlatform/agon-ez80asm
| 3,963
|
tests/Z_PRG_AgonBits_Lessons/tests/plot.s
|
; extra MACRO files need to go here
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
; prepare the screen
SET_MODE 8 ; mode 8 is 640x480 pixels, 64 colours
; Sending a VDU byte stream
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ld a, $08 ; code to send to MOS
rst.lil $08 ; get IX pointer to System Variables
WAIT_HERE: ; loop here until we hit ESC key
ld a, (ix + $05) ; get ASCII code of key pressed
cp 27 ; check if 27 (ascii code for ESC)
jp z, EXIT_HERE ; if pressed, jump to exit
jr WAIT_HERE
; ------------------
; This is where we exit the program
EXIT_HERE:
CLS
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; This is the data we send to VDP
VDUdata:
.db 23, 0, 192, 0 ; set to non-scaled graphics
; FOR A SINGLE PIXEL PLOT
.db 18, 0, bright_red ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 200,80 ; X; Y;
; FOR A LINE
.db 18, 0, bright_magenta ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 300, 60 ; X; Y;
.db 25, 13 ; PLOT: mode (13 is a line),
.dw 250,130 ; X; Y;
; FOR A RECTANGLE
.db 18, 0, green ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 10,120 ; X; Y;
.db 25, 101 ; PLOT: mode (101 is a filled rectangle),
.dw 100,180 ; X; Y;
; FOR A CIRCLE
.db 18, 0, bright_yellow ; set graphics colour: mode (0), colour
.db 25, 68 ; PLOT: mode (69 is a MOVE TO but don't plot point),
.dw 180,140 ; X; Y;
.db 25, 149 ; PLOT: mode (149 is an outlined circle),
.dw 200,160 ; X; Y;
; FOR A FILLED TRIANGLE
.db 18, 0, blue ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 10,10 ; X; Y;
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 50, 100 ; X; Y;
.db 25, 85 ; PLOT: mode (85 is a filled triangle),
.dw 200,20 ; X; Y;
endVDUdata:
; ------------------
; colour data
bright_red: equ 9
green: equ 2
bright_yellow: equ 11
bright_magenta: equ 13
blue: equ 4
white: equ 7
black: equ 0
bright_white: equ 15
|
AgonPlatform/agon-ez80asm
| 3,142
|
tests/Z_PRG_AgonBits_Lessons/tests/bitmap.s
|
; extra MACRO files need to go here
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
; prepare the screen
SET_MODE 8 ; mode 8 is 640x480 pixels, 64 colours
; Sending a VDU byte stream
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ld a, $08 ; code to send to MOS
rst.lil $08 ; get IX pointer to System Variables
WAIT_HERE: ; loop here until we hit ESC key
ld a, (ix + $05) ; get ASCII code of key pressed
cp 27 ; check if 27 (ascii code for ESC)
jp z, EXIT_HERE ; if pressed, jump to exit
jr WAIT_HERE
; ------------------
; This is where we exit the program
EXIT_HERE:
CLS
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; This is the data we send to VDP
crystal: EQU 0 ; used for bitmap ID number
star: EQU 1 ; used for bitmap ID number
VDUdata:
.db 23, 0, 192, 0 ; set to non-scaled graphics
; LOAD THE BITMAP FROM A FILE
; file must be 24bit colour plus 8 bit alpha, byte order: RGBA
; 16x16 pixels RGBA should be 1,024 bytes in size
.db 23, 27, 0, crystal ; select bitmap 0 - crystal
.db 23, 27, 1 ; load bitmap data...
.dw 16, 16 ; of size 16x16, from file:
incbin "crystal.data"
.db 23, 27, 0, star ; select bitmap 1 - star
.db 23, 27, 1 ; load bitmap data...
.dw 16, 16 ; of size 16x16, from file:
incbin "star.data"
; PRINT THE BITMAP ON THE SCREEN VDP v1.04 onwards
.db 23, 27, 0, crystal ; select bitmap 0 - crystal
.db 23, 27, 3 ; draw selected bitmap at...
.dw 80, 50 ; X, Y on the screen
; PLOT THE BITMAP ON THE SCREEN VDP v2.1.0 onwards
.db 23, 27, 0, star ; select bitmap 0 - crystal
.db 25, $ED ; plot absolute selected bitmap at...
.dw 150, 120 ; X, Y on the screen
endVDUdata:
; ------------------
|
AgonPlatform/agon-ez80asm
| 4,102
|
tests/Z_PRG_AgonBits_Lessons/tests/viewport.s
|
; extra MACRO files need to go here
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
; prepare the screen
SET_MODE 8 ; mode 8 is 640x480 pixels, 64 colours
; Sending a VDU byte stream
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ld a, $08 ; code to send to MOS
rst.lil $08 ; get IX pointer to System Variables
WAIT_HERE: ; loop here until we hit ESC key
ld a, (ix + $05) ; get ASCII code of key pressed
cp 27 ; check if 27 (ascii code for ESC)
jp z, EXIT_HERE ; if pressed, jump to exit
jr WAIT_HERE
; ------------------
; This is where we exit the program
EXIT_HERE:
CLS
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; This is the data we send to VDP
VDUdata:
.db 23, 0, 192, 0 ; set to non-scaled graphics
.db 24 ; set graphics viewport:-
.dw 40, 150, 270, 40 ; 24, left; bottom; right; top;
; FOR A SINGLE PIXEL PLOT
.db 18, 0, bright_red ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 200,80 ; X; Y;
; FOR A LINE
.db 18, 0, bright_magenta ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 300, 60 ; X; Y;
.db 25, 13 ; PLOT: mode (13 is a line),
.dw 250,130 ; X; Y;
; FOR A RECTANGLE
.db 18, 0, green ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 10,120 ; X; Y;
.db 25, 101 ; PLOT: mode (101 is a filled rectangle),
.dw 100,180 ; X; Y;
; FOR A CIRCLE
.db 18, 0, bright_yellow ; set graphics colour: mode (0), colour
.db 25, 68 ; PLOT: mode (69 is a MOVE TO but don't plot point),
.dw 180,140 ; X; Y;
.db 25, 149 ; PLOT: mode (149 is an outlined circle),
.dw 200,160 ; X; Y;
; FOR A FILLED TRIANGLE
.db 18, 0, blue ; set graphics colour: mode (0), colour
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 10,10 ; X; Y;
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 50, 100 ; X; Y;
.db 25, 85 ; PLOT: mode (85 is a filled triangle),
.dw 200,20 ; X; Y;
endVDUdata:
; ------------------
; colour data
bright_red: equ 9
green: equ 2
bright_yellow: equ 11
bright_magenta: equ 13
blue: equ 4
white: equ 7
black: equ 0
bright_white: equ 15
|
AgonPlatform/agon-ez80asm
| 6,010
|
tests/Z_PRG_AgonBits_Lessons/tests/mouse.s
|
; extra MACRO files need to go here
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
; prepare the screen
SET_MODE 8 ; mode 8 is 320x240 pixels, 64 colours
; enable mouse command
ld a, 23
rst.lil $10
ld a, 0
rst.lil $10
ld a, 89h
rst.lil $10
ld a, 0 ; 0=enable, 1=disable
rst.lil $10
; set mouse icon style
ld a, 23
rst.lil $10
ld a, 0
rst.lil $10
ld a, 89h
rst.lil $10
ld a, 3 ; setCursor
rst.lil $10
ld a, 5 ; fab-gl style number, or my own defined ones
rst.lil $10
ld a, 0 ; 0 as 16 bit number
rst.lil $10
; Sending an initialising VDU byte stream
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
; ------------------
MOUSE_IS_UP_LOOP: ; loop here until we hit ESC key
MOSCALL $1E ; load IX with keymap address
ld a, (ix + $0E)
bit 0, a ; index $0E, bit 0 is for ESC key in matrix
jp nz, EXIT_HERE ; if pressed, ESC key to exit
MOSCALL $08 ; get IX pointer to sysvars
ld a, (ix + $2D) ; + $2D is mouse buttons status
and 00000001b ; bit 0 is left mouse button
cp 1 ; check if pressed
jp z, DO_MOUSE_DOWN ; if so, then jump to mouse down routines
jp MOUSE_IS_UP_LOOP
; ---------------
DO_MOUSE_DOWN:
; set start position
ld a, (ix + $29) ; mouse x position
ld (mouse_start_x), a
ld a, (ix + $2A) ; mouse x position
ld (mouse_start_x + 1), a
ld a, (ix + $2B) ; mouse y position
ld (mouse_start_y), a
ld a, (ix + $2C) ; mouse y position
ld (mouse_start_y + 1), a
call plotStart
jp MOUSE_STILLDOWN_LOOP
; ------------------
plotStart:
ld hl, plot ; address of string to use
ld bc, endPlot - plot ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ret
plot:
.db 25, 69 ; PLOT point at...
mouse_start_x: .dw 0 ; x
mouse_start_y: .dw 0 ; y
endPlot:
; ------------------
MOUSE_STILLDOWN_LOOP:
MOSCALL $1E ; load IX with keymap address
ld a, (ix + $0E)
bit 0, a ; index $0E, bit 0 is for ESC key in matrix
jp nz, EXIT_HERE ; if pressed, ESC key to exit
MOSCALL $08 ; get IX pointer to sysvars
ld a, (ix + $2D) ; +$2D is mouse buttons status
and 00000001b
cp 0
jp z, MOUSE_IS_UP_LOOP
ld a, (ix + $29) ; mouse x position
ld (mouse_pos_x), a
ld a, (ix + $2A) ; mouse x position
ld (mouse_pos_x + 1), a
ld a, (ix + $2B) ; mouse y position
ld (mouse_pos_y), a
ld a, (ix + $2C) ; mouse y position
ld (mouse_pos_y + 1), a
call drawLine
jp MOUSE_STILLDOWN_LOOP
; ------------------
drawLine:
ld hl, line ; address of string to use
ld bc, endLine - line ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ret
line:
.db 25, 5 ; PLOT line from last position to...
mouse_pos_x: .dw 0 ; x
mouse_pos_y: .dw 0 ; y
endLine:
; ------------------
; This is where we exit the program
EXIT_HERE:
CLS
; disable mouse command
ld a, 23
rst.lil $10
ld a, 0
rst.lil $10
ld a, 89h
rst.lil $10
ld a, 1 ; 0=enable, 1=disable
rst.lil $10
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; This is the data we send to VDP
VDUdata:
.db 23, 0, 192, 0 ; set to non-scaled graphics
endVDUdata:
; ------------------
; Cursor styles
; 0 CursorPointerAmigaLike
; 11x11 Amiga like colored mouse pointer
; 1 CursorPointerSimpleReduced
; 10x15 mouse pointer
; 2 CursorPointerSimple
; 11x19 mouse pointer
; 3 CursorPointerShadowed
; 11x19 shadowed mouse pointer
; 4 CursorPointer
; 12x17 mouse pointer
; 5 CursorPen
; 16x16 pen
; 6 CursorCross1
; 9x9 cross
; 7 CursorCross2
; 11x11 cross
; 8 CursorPoint
; 5x5 point
; 9 CursorLeftArrow
; 11x11 left arrow
; 10 CursorRightArrow
; 11x11 right arrow
; 11 CursorDownArrow
; 11x11 down arrow
; 12 CursorUpArrow
; 11x11 up arrow
; 13 CursorMove
; 19x19 move
; 14 CursorResize1
; 12x12 resize orientation 1
; 15 CursorResize2
; 12x12 resize orientation 2
; 16 CursorResize3
; 11x17 resize orientation 3
; 17 CursorResize4
; 17x11 resize orientation 4
; 18 CursorTextInput
; 7x15 text input
|
AgonPlatform/agon-ez80asm
| 6,050
|
tests/Z_PRG_AgonBits_Lessons/tests/sprite.s
|
; extra MACRO files need to go here
include "myMacros.inc"
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
; prepare the screen
SET_MODE 8 ; mode 8 is 320x240 pixels, 64 colours
; Sending a VDU byte stream
ld hl, VDUdata ; address of string to use
ld bc, endVDUdata - VDUdata ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ld a, $08 ; code to send to MOS
rst.lil $08 ; get IX pointer to System Variables
WAIT_HERE: ; loop here until we hit ESC key
MOSCALL $1E ; load IX with keymap address
ld a, (ix + $0E)
bit 0, a ; index $0E, bit 0 is for ESC key in matrix
jp nz, EXIT_HERE ; if pressed, ESC key to exit
ld a, (ix + $06)
bit 0, a ; index $06 bit 0 is for '1' key in matrix
call nz, setFrame0 ; if pressed, setFrame1
ld a, (ix + $06)
bit 1, a ; index $06 bit 1 is for '2' key in matrix
call nz, setFrame1 ; if pressed, setFrame2
ld a, (ix + $0A)
bit 4, a ; index $0A bit 4 is for 'h' key in matrix
call nz, hideSprite ; if pressed, setFrame2
ld a, (ix + $0A)
bit 1, a ; index $0A bit 1 is for 's' key in matrix
call nz, showSprite ; if pressed, setFrame2
jp WAIT_HERE
; ------------------
setFrame0:
ld hl, set0 ; address of string to use
ld bc, endset0 - set0 ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ret
set0:
.db 23, 27, 4, 0 ; select sprite 0
.db 23, 27, 10, 0 ; select frame 0
endset0:
; ------------------
setFrame1:
ld hl, set1 ; address of string to use
ld bc, endset1 - set1 ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ret
set1:
.db 23, 27, 4, 0 ; select sprite 0
.db 23, 27, 10, 1 ; select frame 1
endset1:
; ------------------
hideSprite:
ld hl, hide ; address of string to use
ld bc, endhide - hide ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ret
hide:
.db 23, 27, 4, 0 ; select sprite 0
.db 23, 27, 12 ; hide current sprite
endhide:
; ------------------
showSprite:
ld hl, show ; address of string to use
ld bc, endshow - show ; length of string
rst.lil $18 ; Call the MOS API to send data to VDP
ret
show:
.db 23, 27, 4, 0 ; select sprite 0
.db 23, 27, 11 ; show current sprite
endshow:
; ------------------
; This is where we exit the program
EXIT_HERE:
CLS
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
; This is the data we send to VDP
crystal: EQU 0 ; used for bitmap ID number
star: EQU 1 ; used for bitmap ID number
our_sprite: EQU 0 ; sprite ID - always start at 0 upwards
VDUdata:
.db 23, 0, 192, 0 ; set to non-scaled graphics
; LOAD THE BITMAP FROM A FILE
; file must be 24bit colour plus 8 bit alpha, byte order: RGBA
; 16x16 pixels RGBA should be 1,024 bytes in size
.db 23, 27, 0, crystal ; select bitmap 0 - crystal
.db 23, 27, 1 ; load bitmap data...
.dw 16, 16 ; of size 16x16, from file:
incbin "crystal.data"
.db 23, 27, 0, star ; select bitmap 1 - star
.db 23, 27, 1 ; load bitmap data...
.dw 16, 16 ; of size 16x16, from file:
incbin "star.data"
; SETUP THE SPRITE
.db 23, 27, 4, our_sprite ; select sprite 0
.db 23, 27, 5 ; clear frames
.db 23, 27, 6, crystal ; add bitmap frame crystal to sprite
.db 23, 27, 6, star ; add bitmap frame star to sprite
.db 23, 27, 7, 1 ; activate 1 sprite(s)
.db 23, 27, 11 ; show current sprite
; MOVE A SPRITE
.db 23, 27, 4, our_sprite ; select sprite 0
.db 23, 27, 13 ; move currrent sprite to...
.dw 150, 100 ; x,y (as words)
.db 23, 27, 15 ; update sprites in GPU
; PLOT A RECTANGLE
.db 18, 0, 45 ; set graphics colour: mode (0), colour 45 = purple
.db 25, 69 ; PLOT: mode (69 is a point in current colour),
.dw 80,80 ; X; Y;
.db 25, 101 ; PLOT: mode (101 is a filled rectangle),
.dw 190,130 ; X; Y;
endVDUdata:
; ------------------
|
AgonPlatform/agon-ez80asm
| 990
|
tests/Z_PRG_AgonBits_Lessons/tests/hello.s
|
.assume adl=1 ; ez80 ADL memory mode
.org $40000 ; load code here
jp start_here ; jump to start of code
.align 64 ; MOS header
.db "MOS",0,1
start_here:
push af ; store all the registers
push bc
push de
push ix
push iy
; ------------------
; This is our actual code
ld hl, string ; address of string to use
ld bc,0 ; length of string, or 0 if a delimiter is used
ld a,0 ; A is the delimiter
rst.lil $18 ; Call the MOS API to send data to VDP
; ------------------
; This is where we exit the program
pop iy ; Pop all registers back from the stack
pop ix
pop de
pop bc
pop af
ld hl,0 ; Load the MOS API return code (0) for no errors.
ret ; Return to MOS
; ------------------
string:
.db "Hello Agon World\r\n",0
|
AgonPlatform/agon-ez80asm
| 3,940
|
tests/Opcodes/tests/opcodes_m-z.s
|
.assume adl=1
mlt bc
mlt de
mlt hl
mlt sp
neg
nop
or a, (hl)
or a, ixh
or a, ixl
or a, iyh
or a, iyl
or a, (ix+5)
or a, (iy+5)
or a, 5
or a, a
or a, b
or a, c
or a, d
or a, e
or a, h
or a, l
otd2r
otdm
otdmr
otdr
otdrx
oti2r
otim
otimr
otir
otirx
out (bc), a
out (bc), b
out (bc), c
out (bc), d
out (bc), e
out (bc), h
out (bc), l
out (c), a
out (c), b
out (c), c
out (c), d
out (c), e
out (c), h
out (c), l
out (5), a
out0 (5), a
out0 (5), b
out0 (5), c
out0 (5), d
out0 (5), e
out0 (5), h
out0 (5), l
outd
outd2
outi
outi2
pea ix+5
pea iy+5
pop af
pop ix
pop iy
pop bc
pop de
pop hl
push af
push ix
push iy
push bc
push de
push hl
res 0, (hl)
res 1, (hl)
res 2, (hl)
res 3, (hl)
res 4, (hl)
res 5, (hl)
res 6, (hl)
res 7, (hl)
res 0, (ix+5)
res 1, (ix+5)
res 2, (ix+5)
res 3, (ix+5)
res 4, (ix+5)
res 5, (ix+5)
res 6, (ix+5)
res 7, (ix+5)
res 0, (iy+5)
res 1, (iy+5)
res 2, (iy+5)
res 3, (iy+5)
res 4, (iy+5)
res 5, (iy+5)
res 6, (iy+5)
res 7, (iy+5)
res 0, a
res 1, a
res 2, a
res 3, a
res 4, a
res 5, a
res 6, a
res 7, a
res 0, b
res 1, b
res 2, b
res 3, b
res 4, b
res 5, b
res 6, b
res 7, b
res 0, c
res 1, c
res 2, c
res 3, c
res 4, c
res 5, c
res 6, c
res 7, c
res 0, d
res 1, d
res 2, d
res 3, d
res 4, d
res 5, d
res 6, d
res 7, d
res 0, e
res 1, e
res 2, e
res 3, e
res 4, e
res 5, e
res 6, e
res 7, e
res 0, h
res 1, h
res 2, h
res 3, h
res 4, h
res 5, h
res 6, h
res 7, h
res 0, l
res 1, l
res 2, l
res 3, l
res 4, l
res 5, l
res 6, l
res 7, l
ret
ret nz
ret z
ret nc
ret c
ret po
ret pe
ret p
ret m
reti
retn
rl (hl)
rl (ix+5)
rl (iy+5)
rl a
rl b
rl c
rl d
rl e
rl h
rl l
rla
rlc (hl)
rlc (ix+5)
rlc (iy+5)
rlc a
rlc b
rlc c
rlc d
rlc e
rlc h
rlc l
rlca
rld
rr (hl)
rr (ix+5)
rr (iy+5)
rr a
rr b
rr c
rr d
rr e
rr h
rr l
rra
rrc (hl)
rrc (ix+5)
rrc (iy+5)
rrc a
rrc b
rrc c
rrc d
rrc e
rrc h
rrc l
rrca
rrd
rsmix
rst 0
rst 08h
rst 10h
rst 18h
rst 20h
rst 28h
rst 30h
rst 38h
sbc a, (hl)
sbc a, ixh
sbc a, ixl
sbc a, iyh
sbc a, iyl
sbc a, (ix+5)
sbc a, (iy+5)
sbc a, 5
sbc a, a
sbc a, b
sbc a, c
sbc a, d
sbc a, e
sbc a, h
sbc a, l
sbc hl, bc
sbc hl, de
sbc hl, hl
sbc hl, sp
scf
set 0, (hl)
set 1, (hl)
set 2, (hl)
set 3, (hl)
set 4, (hl)
set 5, (hl)
set 6, (hl)
set 7, (hl)
set 0, (ix+5)
set 1, (ix+5)
set 2, (ix+5)
set 3, (ix+5)
set 4, (ix+5)
set 5, (ix+5)
set 6, (ix+5)
set 7, (ix+5)
set 0, (iy+5)
set 1, (iy+5)
set 2, (iy+5)
set 3, (iy+5)
set 4, (iy+5)
set 5, (iy+5)
set 6, (iy+5)
set 7, (iy+5)
set 0, a
set 0, b
set 0, c
set 0, d
set 0, e
set 0, h
set 0, l
set 1, a
set 1, b
set 1, c
set 1, d
set 1, e
set 1, h
set 1, l
set 2, a
set 2, b
set 2, c
set 2, d
set 2, e
set 2, h
set 2, l
set 3, a
set 3, b
set 3, c
set 3, d
set 3, e
set 3, h
set 3, l
set 4, a
set 4, b
set 4, c
set 4, d
set 4, e
set 4, h
set 4, l
set 5, a
set 5, b
set 5, c
set 5, d
set 5, e
set 5, h
set 5, l
set 6, a
set 6, b
set 6, c
set 6, d
set 6, e
set 6, h
set 6, l
set 7, a
set 7, b
set 7, c
set 7, d
set 7, e
set 7, h
set 7, l
sla (hl)
sla (ix+5)
sla (iy+5)
sla a
sla b
sla c
sla d
sla e
sla h
sla l
slp
sra (hl)
sra (ix+5)
sra (iy+5)
sra a
sra b
sra c
sra d
sra e
sra h
sra l
srl (hl)
srl (ix+5)
srl (iy+5)
srl a
srl b
srl c
srl d
srl e
srl h
srl l
stmix
sub a, (hl)
sub a, ixh
sub a, ixl
sub a, iyh
sub a, iyl
sub a, (ix+5)
sub a, (iy+5)
sub a, 5
sub a, a
sub a, b
sub a, c
sub a, d
sub a, e
sub a, h
sub a, l
tst a, (hl)
tst a, 5
tst a, a
tst a, b
tst a, c
tst a, d
tst a, e
tst a, h
tst a, l
tstio 5
xor a, (hl)
xor a, ixh
xor a, ixl
xor a, iyh
xor a, iyl
xor a, (ix+5)
xor a, (iy+5)
xor a, 5
xor a, a
xor a, b
xor a, c
xor a, d
xor a, e
xor a, h
xor a, l
|
AgonPlatform/agon-ez80asm
| 11,675
|
tests/Opcodes/tests/z80_undocumented.s
|
; Testing only the undocumented Z80 instructions.
.cpu Z80
inc ixh ; DD 24
inc ixl ; DD 2C
inc iyh ; FD 24
inc iyl ; FD 2C
sll b ; DDCB 30
sll c ; DDCB 31
sll d ; DDCB 32
sll e ; DDCB 33
sll h ; DDCB 34
sll l ; DDCB 35
sll a ; DDCB 37
in (c) ; ED 70
out (c),0 ; ED 71
ld ixh,b ; DD 60
ld ixh,c ; DD 61
ld ixh,d ; DD 62
ld ixh,e ; DD 63
ld ixh,ixh ; DD 64
ld ixh,ixl ; DD 65
ld ixh,a ; DD 67
ld ixl,b ; FD 60
ld ixl,c ; FD 61
ld ixl,d ; FD 62
ld ixl,e ; FD 63
ld ixl,ixh ; FD 64
ld ixl,ixl ; FD 65
ld ixl,a ; FD 67
ld b,ixh ; 44
ld b,ixl ; 45
ld c,ixh ; 4C
ld c,ixl ; 4D
ld d,ixh ; 54
ld d,ixl ; 55
ld e,ixh ; 5C
ld e,ixl ; 5D
ld ixh,0 ; 26
ld ixl,0 ; 2E
ld a,ixh ; 7C
ld a,ixl ; 7D
inc ixh ; 24
inc ixl ; 2C
dec ixh ; 25
dec ixl ; 2D
add a,ixh ; 84
add a,ixl ; 85
adc a,ixh ; 8C
adc a,ixl ; 8D
sub ixh ; 94
sub ixl ; 95
sbc a,ixh ; 9C
sbc a,ixl ; 9D
and ixh ; A4
and ixl ; A5
xor ixh ; AC
xor ixl ; AD
or ixh ; B4
or ixl ; B5
cp ixh ; BC
cp ixl ; BD
inc iyh;24
dec iyh;25
ld iyh,0;26
inc iyl;2C
dec iyl;2D
ld iyl,0;2E
ld b,iyh;44
ld b,iyl;45
ld c,iyh;4C
ld c,iyl;4D
ld d,iyh;54
ld d,iyl;55
ld e,iyh;5C
ld e,iyl;5D
ld iyh,b;60
ld iyh,c;61
ld iyh,d;62
ld iyh,e;63
ld iyh,iyh;64
ld iyh,iyl;65
ld iyh,a;67
ld iyl,b;68
ld iyl,c;69
ld iyl,d;6A
ld iyl,e;6B
ld iyl,iyh;6C
ld iyl,iyl;6D
ld iyl,a;6F
add a,iyh;84
add a,iyl;85
adc a,iyh;8C
adc a,iyl;8D
ld a,iyh;7C
ld a,iyl;7D
sub iyh;94
sub iyl;95
sbc a,iyh;9C
sbc a,iyl;9D
and iyh;A4
and iyl;A5
xor iyh;AC
xor iyl;AD
or iyh;B4
or iyl;B5
cp iyh;BC
cp iyl;BD
; DDCB
rlc (ix+0),b ; DDCB 00
rlc (ix+0),c ; DDCB 01
rlc (ix+0),d ; DDCB 02
rlc (ix+0),e ; DDCB 03
rlc (ix+0),h ; DDCB 04
rlc (ix+0),l ; DDCB 05
rlc (ix+0),a ; DDCB 07
rrc (ix+0),b ; DDCB 08
rrc (ix+0),c ; DDCB 09
rrc (ix+0),d ; DDCB 0A
rrc (ix+0),e ; DDCB 0B
rrc (ix+0),h ; DDCB 0C
rrc (ix+0),l ; DDCB 0D
rrc (ix+0),a ; DDCB 0F
rl (ix+0),b ; DDCB 10
rl (ix+0),c ; DDCB 11
rl (ix+0),d ; DDCB 12
rl (ix+0),e ; DDCB 13
rl (ix+0),h ; DDCB 14
rl (ix+0),l ; DDCB 15
rl (ix+0),a ; DDCB 17
rr (ix+0),b ; DDCB 18
rr (ix+0),c ; DDCB 19
rr (ix+0),d ; DDCB 1A
rr (ix+0),e ; DDCB 1B
rr (ix+0),h ; DDCB 1C
rr (ix+0),l ; DDCB 1D
rr (ix+0),a ; DDCB 1F
sla (ix+0),b ; DDCB 20
sla (ix+0),c ; DDCB 21
sla (ix+0),d ; DDCB 22
sla (ix+0),e ; DDCB 23
sla (ix+0),h ; DDCB 24
sla (ix+0),l ; DDCB 25
sla (ix+0),a ; DDCB 27
sra (ix+0),b ; DDCB 28
sra (ix+0),c ; DDCB 29
sra (ix+0),d ; DDCB 2A
sra (ix+0),e ; DDCB 2B
sra (ix+0),h ; DDCB 2C
sra (ix+0),l ; DDCB 2D
sra (ix+0),a ; DDCB 2F
sll (ix+0),b ; DDCB 30
sll (ix+0),c ; DDCB 31
sll (ix+0),d ; DDCB 32
sll (ix+0),e ; DDCB 33
sll (ix+0),h ; DDCB 34
sll (ix+0),l ; DDCB 35
sll (ix+0) ; DDCB 36
sll (ix+0),a ; DDCB 37
srl (ix+0),b ; DDCB 38
srl (ix+0),c ; DDCB 39
srl (ix+0),d ; DDCB 3A
srl (ix+0),e ; DDCB 3B
srl (ix+0),h ; DDCB 3C
srl (ix+0),l ; DDCB 3D
srl (ix+0),a ; DDCB 3F
res 0,(ix+0),b ; DDCB 80
res 0,(ix+0),c ; DDCB 81
res 0,(ix+0),d ; DDCB 82
res 0,(ix+0),e ; DDCB 83
res 0,(ix+0),h ; DDCB 84
res 0,(ix+0),l ; DDCB 85
res 0,(ix+0),a ; DDCB 87
res 1,(ix+0),b ; DDCB 88
res 1,(ix+0),c ; DDCB 89
res 1,(ix+0),d ; DDCB 8A
res 1,(ix+0),e ; DDCB 8B
res 1,(ix+0),h ; DDCB 8C
res 1,(ix+0),l ; DDCB 8D
res 1,(ix+0),a ; DDCB 8F
res 2,(ix+0),b ; DDCB 90
res 2,(ix+0),c ; DDCB 91
res 2,(ix+0),d ; DDCB 92
res 2,(ix+0),e ; DDCB 93
res 2,(ix+0),h ; DDCB 94
res 2,(ix+0),l ; DDCB 95
res 2,(ix+0),a ; DDCB 97
res 3,(ix+0),b ; DDCB 98
res 3,(ix+0),c ; DDCB 99
res 3,(ix+0),d ; DDCB 9A
res 3,(ix+0),e ; DDCB 9B
res 3,(ix+0),h ; DDCB 9C
res 3,(ix+0),l ; DDCB 9D
res 3,(ix+0),a ; DDCB 9F
res 4,(ix+0),b ; DDCB A0
res 4,(ix+0),c ; DDCB A1
res 4,(ix+0),d ; DDCB A2
res 4,(ix+0),e ; DDCB A3
res 4,(ix+0),h ; DDCB A4
res 4,(ix+0),l ; DDCB A5
res 4,(ix+0),a ; DDCB A7
res 5,(ix+0),b ; DDCB A8
res 5,(ix+0),c ; DDCB A9
res 5,(ix+0),d ; DDCB AA
res 5,(ix+0),e ; DDCB AB
res 5,(ix+0),h ; DDCB AC
res 5,(ix+0),l ; DDCB AD
res 5,(ix+0),a ; DDCB AF
res 6,(ix+0),b ; DDCB B0
res 6,(ix+0),c ; DDCB B1
res 6,(ix+0),d ; DDCB B2
res 6,(ix+0),e ; DDCB B3
res 6,(ix+0),h ; DDCB B4
res 6,(ix+0),l ; DDCB B5
res 6,(ix+0),a ; DDCB B7
res 7,(ix+0),b ; DDCB B8
res 7,(ix+0),c ; DDCB B9
res 7,(ix+0),d ; DDCB BA
res 7,(ix+0),e ; DDCB BB
res 7,(ix+0),h ; DDCB BC
res 7,(ix+0),l ; DDCB BD
res 7,(ix+0),a ; DDCB B7
set 0,(ix+0),b ; DDCB C0
set 0,(ix+0),c ; DDCB C1
set 0,(ix+0),d ; DDCB C2
set 0,(ix+0),e ; DDCB C3
set 0,(ix+0),h ; DDCB C4
set 0,(ix+0),l ; DDCB C5
set 0,(ix+0),a ; DDCB C7
set 1,(ix+0),b ; DDCB C8
set 1,(ix+0),c ; DDCB C9
set 1,(ix+0),d ; DDCB CA
set 1,(ix+0),e ; DDCB CB
set 1,(ix+0),h ; DDCB CC
set 1,(ix+0),l ; DDCB CD
set 1,(ix+0),a ; DDCB CF
set 2,(ix+0),b ; DDCB D0
set 2,(ix+0),c ; DDCB D1
set 2,(ix+0),d ; DDCB D2
set 2,(ix+0),e ; DDCB D3
set 2,(ix+0),h ; DDCB D4
set 2,(ix+0),l ; DDCB D5
set 2,(ix+0),a ; DDCB D7
set 3,(ix+0),b ; DDCB D8
set 3,(ix+0),c ; DDCB D9
set 3,(ix+0),d ; DDCB DA
set 3,(ix+0),e ; DDCB DB
set 3,(ix+0),h ; DDCB DC
set 3,(ix+0),l ; DDCB DD
set 3,(ix+0),a ; DDCB DF
set 4,(ix+0),b ; DDCB E0
set 4,(ix+0),c ; DDCB E1
set 4,(ix+0),d ; DDCB E2
set 4,(ix+0),e ; DDCB E3
set 4,(ix+0),h ; DDCB E4
set 4,(ix+0),l ; DDCB E5
set 4,(ix+0),a ; DDCB E7
set 5,(ix+0),b ; DDCB E8
set 5,(ix+0),c ; DDCB E9
set 5,(ix+0),d ; DDCB EA
set 5,(ix+0),e ; DDCB EB
set 5,(ix+0),h ; DDCB EC
set 5,(ix+0),l ; DDCB ED
set 5,(ix+0),a ; DDCB EF
set 6,(ix+0),b ; DDCB F0
set 6,(ix+0),c ; DDCB F1
set 6,(ix+0),d ; DDCB F2
set 6,(ix+0),e ; DDCB F3
set 6,(ix+0),h ; DDCB F4
set 6,(ix+0),l ; DDCB F5
set 6,(ix+0),a ; DDCB F7
set 7,(ix+0),b ; DDCB F8
set 7,(ix+0),c ; DDCB F9
set 7,(ix+0),d ; DDCB FA
set 7,(ix+0),e ; DDCB FB
set 7,(ix+0),h ; DDCB FC
set 7,(ix+0),l ; DDCB FD
set 7,(ix+0),a ; DDCB FF
; FDCB
rlc (iy+0),b ; FDCB 00
rlc (iy+0),c ; FDCB 01
rlc (iy+0),d ; FDCB 02
rlc (iy+0),e ; FDCB 03
rlc (iy+0),h ; FDCB 04
rlc (iy+0),l ; FDCB 05
rlc (iy+0),a ; FDCB 07
rrc (iy+0),b ; FDCB 08
rrc (iy+0),c ; FDCB 09
rrc (iy+0),d ; FDCB 0A
rrc (iy+0),e ; FDCB 0B
rrc (iy+0),h ; FDCB 0C
rrc (iy+0),l ; FDCB 0D
rrc (iy+0),a ; FDCB 0F
rl (iy+0),b ; FDCB 10
rl (iy+0),c ; FDCB 11
rl (iy+0),d ; FDCB 12
rl (iy+0),e ; FDCB 13
rl (iy+0),h ; FDCB 14
rl (iy+0),l ; FDCB 15
rl (iy+0),a ; FDCB 17
rr (iy+0),b ; FDCB 18
rr (iy+0),c ; FDCB 19
rr (iy+0),d ; FDCB 1A
rr (iy+0),e ; FDCB 1B
rr (iy+0),h ; FDCB 1C
rr (iy+0),l ; FDCB 1D
rr (iy+0),a ; FDCB 1F
sla (iy+0),b ; FDCB 20
sla (iy+0),c ; FDCB 21
sla (iy+0),d ; FDCB 22
sla (iy+0),e ; FDCB 23
sla (iy+0),h ; FDCB 24
sla (iy+0),l ; FDCB 25
sla (iy+0),a ; FDCB 27
sra (iy+0),b ; FDCB 28
sra (iy+0),c ; FDCB 29
sra (iy+0),d ; FDCB 2A
sra (iy+0),e ; FDCB 2B
sra (iy+0),h ; FDCB 2C
sra (iy+0),l ; FDCB 2D
sra (iy+0),a ; FDCB 2F
sll (iy+0),b ; FDCB 30
sll (iy+0),c ; FDCB 31
sll (iy+0),d ; FDCB 32
sll (iy+0),e ; FDCB 33
sll (iy+0),h ; FDCB 34
sll (iy+0),l ; FDCB 35
sll (iy+0) ; FDCB 36
sll (iy+0),a ; FDCB 37
srl (iy+0),b ; FDCB 38
srl (iy+0),c ; FDCB 39
srl (iy+0),d ; FDCB 3A
srl (iy+0),e ; FDCB 3B
srl (iy+0),h ; FDCB 3C
srl (iy+0),l ; FDCB 3D
srl (iy+0),a ; FDCB 3F
res 0,(iy+0),b ; FDCB 80
res 0,(iy+0),c ; FDCB 81
res 0,(iy+0),d ; FDCB 82
res 0,(iy+0),e ; FDCB 83
res 0,(iy+0),h ; FDCB 84
res 0,(iy+0),l ; FDCB 85
res 0,(iy+0),a ; FDCB 87
res 1,(iy+0),b ; FDCB 88
res 1,(iy+0),c ; FDCB 89
res 1,(iy+0),d ; FDCB 8A
res 1,(iy+0),e ; FDCB 8B
res 1,(iy+0),h ; FDCB 8C
res 1,(iy+0),l ; FDCB 8D
res 1,(iy+0),a ; FDCB 8F
res 2,(iy+0),b ; FDCB 90
res 2,(iy+0),c ; FDCB 91
res 2,(iy+0),d ; FDCB 92
res 2,(iy+0),e ; FDCB 93
res 2,(iy+0),h ; FDCB 94
res 2,(iy+0),l ; FDCB 95
res 2,(iy+0),a ; FDCB 97
res 3,(iy+0),b ; FDCB 98
res 3,(iy+0),c ; FDCB 99
res 3,(iy+0),d ; FDCB 9A
res 3,(iy+0),e ; FDCB 9B
res 3,(iy+0),h ; FDCB 9C
res 3,(iy+0),l ; FDCB 9D
res 3,(iy+0),a ; FDCB 9F
res 4,(iy+0),b ; FDCB A0
res 4,(iy+0),c ; FDCB A1
res 4,(iy+0),d ; FDCB A2
res 4,(iy+0),e ; FDCB A3
res 4,(iy+0),h ; FDCB A4
res 4,(iy+0),l ; FDCB A5
res 4,(iy+0),a ; FDCB A7
res 5,(iy+0),b ; FDCB A8
res 5,(iy+0),c ; FDCB A9
res 5,(iy+0),d ; FDCB AA
res 5,(iy+0),e ; FDCB AB
res 5,(iy+0),h ; FDCB AC
res 5,(iy+0),l ; FDCB AD
res 5,(iy+0),a ; FDCB AF
res 6,(iy+0),b ; FDCB B0
res 6,(iy+0),c ; FDCB B1
res 6,(iy+0),d ; FDCB B2
res 6,(iy+0),e ; FDCB B3
res 6,(iy+0),h ; FDCB B4
res 6,(iy+0),l ; FDCB B5
res 6,(iy+0),a ; FDCB B7
res 7,(iy+0),b ; FDCB B8
res 7,(iy+0),c ; FDCB B9
res 7,(iy+0),d ; FDCB BA
res 7,(iy+0),e ; FDCB BB
res 7,(iy+0),h ; FDCB BC
res 7,(iy+0),l ; FDCB BD
res 7,(iy+0),a ; FDCB B7
set 0,(iy+0),b ; FDCB C0
set 0,(iy+0),c ; FDCB C1
set 0,(iy+0),d ; FDCB C2
set 0,(iy+0),e ; FDCB C3
set 0,(iy+0),h ; FDCB C4
set 0,(iy+0),l ; FDCB C5
set 0,(iy+0),a ; FDCB C7
set 1,(iy+0),b ; FDCB C8
set 1,(iy+0),c ; FDCB C9
set 1,(iy+0),d ; FDCB CA
set 1,(iy+0),e ; FDCB CB
set 1,(iy+0),h ; FDCB CC
set 1,(iy+0),l ; FDCB CD
set 1,(iy+0),a ; FDCB CF
set 2,(iy+0),b ; FDCB D0
set 2,(iy+0),c ; FDCB D1
set 2,(iy+0),d ; FDCB D2
set 2,(iy+0),e ; FDCB D3
set 2,(iy+0),h ; FDCB D4
set 2,(iy+0),l ; FDCB D5
set 2,(iy+0),a ; FDCB D7
set 3,(iy+0),b ; FDCB D8
set 3,(iy+0),c ; FDCB D9
set 3,(iy+0),d ; FDCB DA
set 3,(iy+0),e ; FDCB DB
set 3,(iy+0),h ; FDCB DC
set 3,(iy+0),l ; FDCB DD
set 3,(iy+0),a ; FDCB DF
set 4,(iy+0),b ; FDCB E0
set 4,(iy+0),c ; FDCB E1
set 4,(iy+0),d ; FDCB E2
set 4,(iy+0),e ; FDCB E3
set 4,(iy+0),h ; FDCB E4
set 4,(iy+0),l ; FDCB E5
set 4,(iy+0),a ; FDCB E7
set 5,(iy+0),b ; FDCB E8
set 5,(iy+0),c ; FDCB E9
set 5,(iy+0),d ; FDCB EA
set 5,(iy+0),e ; FDCB EB
set 5,(iy+0),h ; FDCB EC
set 5,(iy+0),l ; FDCB ED
set 5,(iy+0),a ; FDCB EF
set 6,(iy+0),b ; FDCB F0
set 6,(iy+0),c ; FDCB F1
set 6,(iy+0),d ; FDCB F2
set 6,(iy+0),e ; FDCB F3
set 6,(iy+0),h ; FDCB F4
set 6,(iy+0),l ; FDCB F5
set 6,(iy+0),a ; FDCB F7
set 7,(iy+0),b ; FDCB F8
set 7,(iy+0),c ; FDCB F9
set 7,(iy+0),d ; FDCB FA
set 7,(iy+0),e ; FDCB FB
set 7,(iy+0),h ; FDCB FC
set 7,(iy+0),l ; FDCB FD
set 7,(iy+0),a ; FDCB FF
|
AgonPlatform/agon-ez80asm
| 2,426
|
tests/Opcodes/tests/opcodes_l.s
|
.assume adl=1
ld a, i
ld a, (ix+5)
ld a, (iy+5)
ld a, mb
ld a, (aabbcch)
ld a, r
ld a, (bc)
ld a, (de)
ld a, (hl)
ld hl, i
ld (hl), ix
ld (hl), iy
ld (hl), 5
ld (hl), a
ld (hl), b
ld (hl), c
ld (hl), d
ld (hl), e
ld (hl), h
ld (hl), l
ld (hl), bc
ld (hl), de
ld (hl), hl
ld i, hl
ld i, a
ld ixh, ixh
ld ixh, ixl
ld ixl, ixh
ld ixl, ixl
ld iyh, iyh
ld iyh, iyl
ld iyl, iyh
ld iyl, iyl
ld ixh, 5
ld ixl, 5
ld iyh, 5
ld iyl, 5
ld ixh, a
ld ixh, b
ld ixh, c
ld ixh, d
ld ixh, e
ld ixl, a
ld ixl, b
ld ixl, c
ld ixl, d
ld ixl, e
ld iyh, a
ld iyh, b
ld iyh, c
ld iyh, d
ld iyh, e
ld iyl, a
ld iyl, b
ld iyl, c
ld iyl, d
ld iyl, e
ld ix, (hl)
ld iy, (hl)
ld ix, (ix+5)
ld iy, (ix+5)
ld ix, (iy+5)
ld iy, (iy+5)
ld ix, aabbcch
ld iy, aabbcch
ld ix, (aabbcch)
ld iy, (aabbcch)
ld (ix+5), ix
ld (ix+5), iy
ld (iy+5), ix
ld (iy+5), iy
ld (ix+5), 10
ld (iy+5), 10
ld (ix+5), a
ld (ix+5), b
ld (ix+5), c
ld (ix+5), d
ld (ix+5), e
ld (ix+5), h
ld (ix+5), l
ld (iy+5), a
ld (iy+5), b
ld (iy+5), c
ld (iy+5), d
ld (iy+5), e
ld (iy+5), h
ld (iy+5), l
ld (ix+5), bc
ld (ix+5), de
ld (ix+5), hl
ld (iy+5), bc
ld (iy+5), de
ld (iy+5), hl
ld mb, a
ld (aabbcch), a
ld (aabbcch), ix
ld (aabbcch), iy
ld (aabbcch), bc
ld (aabbcch), de
ld (aabbcch), hl
ld (aabbcch), sp
ld r, a
ld a, (hl)
ld b, (hl)
ld c, (hl)
ld d, (hl)
ld e, (hl)
ld h, (hl)
ld l, (hl)
ld a, ixh
ld a, ixl
ld a, iyh
ld a, iyl
ld b, ixh
ld b, ixl
ld b, iyh
ld b, iyl
ld c, ixh
ld c, ixl
ld c, iyh
ld c, iyl
ld d, ixh
ld d, ixl
ld d, iyh
ld d, iyl
ld e, ixh
ld e, ixl
ld e, iyh
ld e, iyl
ld a, (ix+5)
ld b, (ix+5)
ld c, (ix+5)
ld d, (ix+5)
ld e, (ix+5)
ld h, (ix+5)
ld l, (ix+5)
ld a, (iy+5)
ld b, (iy+5)
ld c, (iy+5)
ld d, (iy+5)
ld e, (iy+5)
ld h, (iy+5)
ld l, (iy+5)
ld a, 5
ld b, 5
ld c, 5
ld d, 5
ld e, 5
ld h, 5
ld l, 5
ld a, a
ld bc, (hl)
ld de, (hl)
ld hl, (hl)
ld bc, (ix+5)
ld de, (ix+5)
ld hl, (ix+5)
ld bc, (iy+5)
ld de, (iy+5)
ld hl, (iy+5)
ld bc, aabbcch
ld de, aabbcch
ld hl, aabbcch
ld bc, (aabbcch)
ld de, (aabbcch)
ld hl, (aabbcch)
ld (bc), a
ld (de), a
ld (hl), a
ld sp, hl
ld sp, ix
ld sp, iy
ld sp, aabbcch
ld sp, (aabbcch)
ldd
lddr
ldi
ldir
lea ix, ix+5
lea iy, ix+5
lea ix, iy+5
lea iy, iy+5
lea bc, ix+5
lea de, ix+5
lea hl, ix+5
lea bc, iy+5
lea de, iy+5
lea hl, iy+5
|
AgonPlatform/agon-ez80asm
| 1,407
|
tests/Addressing/tests/test_relocate_addressing.s
|
; Testing relocation addresses using the .relocate directive
.org $40000
start:
jp $50000
.align $100 ; to facilitate manual byte counting in preparation of this test
.relocate $50000
ld a,0 ; 50000 / 50001
ld a,0 ; 50002 / 50003
rellabel: ; 50004
ld a,0 ; 50004 / 50005
@local: ; 50006
dw24 $ ; 50006 / 50007 / 50008 - content should be 50006 - the relocated current address
jp rellabel ; 50009 / 5000A / 5000B / 5000C - should jump to 50004
jp @local ; 5000D / 5000E / 5000F / 50010 - should jump to 50006
jp start ; 50011 / 50012 / 50013 / 50014 - should jump to 40000
jp outside ; 50015 / 50016 / 50017 / 50018 - should jump to 40124
val: EQU 0 ; EQU should be zero
dw24 val ; 50019 / 5001A / 5001B value should be 0
ina: equ $ ; 5001C - nastigram - should be relocated address 5001C
jp ina ; 5001C / 5001D / 5001E / 5001F - should jump to 5001C
jp $ ; 50020 / 50021 / 50022 / 50023 - should jump to 50020
.endrelocate
outside: ; real address 40124, would have been 50024 if endrelocate wasn't given
jp outside ; 40124 / 40125 / 40126 / 40127
oad: equ $
dw24 oad ; 40128 / 40129 / 4012A value should be 40128
jp $ ; 4012B / 4012C / 4012D / 4012E - should jump to 4012B
|
AgonPlatform/agon-ez80asm
| 2,108
|
tests/Defines/tests/compound.s
|
; Test directive variants
db 1
.db 1
DB 1
.DB 1
defb 1
.defb 1
ascii 1
.ascii 1
byte 1
.byte 1
dw 1
.dw 1
DW 1
.DW 1
defw 1
.defw 1
DEFW 1
.DEFW 1
dl 1
.dl 1
DL 1
.DL 1
dw24 1
.dw24 1
DW24 1
.DW24 1
dw32 1
.dw32 1
DW32 1
.DW32 1
asciz "test"
ASCIZ "test"
blkb 1
.blkb 1
BLKB 1
.BLKB 1
; blkw 1
; .blkw 1
; BLKW 1
; .BLKW 1
; blkp 1
; .blkp 1
; BLKP 1
; .BLKP 1
; blkl 1
; .blkl 1
; BLKL 1
; .BLKL 1
; we'll use the directive without ., or the reference ZDS assembler barks at us
; byte tests
db 5
db 1,2,3
db 10;comment
byte 5
byte 1,2,3
byte 10;comment
ascii 5
ascii 1,2,3
ascii 10;comment
defb 5
defb 1,2,3
defb 10;comment
label:
jp label2
; 16-bit word tests
dw 5
dw 1,2,3
dw 10;comment
dw ffffh
;dw label
; 24-bit word tests
dl 5
dl 1,2,3
dl 10;comment
dl ffffh
dl label
dw24 5
dw24 1,2,3
dw24 10;comment
dw24 ffffh
dw24 label
; define space
; ds 10
; ds 10;uninitialized. Will be different between assemblers
; ds 10,0xFF
; define blocks
; blkb 16, 0xFF
; blkb 10h, 0xFF
; blkb 16;uninitialized. Will be different between assemblers
; blkw 16, 0xAAFF
; blkw 10h, 0xAAFF
; blkw 16;uninitialized. Will be different between assemblers
; blkp 16, 0xAABBFF
; blkp 10h, 0xAABBFF
; blkp 10h, label
; blkp 16;uninitialized. Will be different between assemblers
; blkl 16, 0xAABBCCFF
; blkl 10h, 0xAABBCCFF
; blkl 16;uninitialized. Will be different between assemblers
label2:
jp label
|
AgoraIO-Community/Solo
| 2,632
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_resampler_private_AR2_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
VARDEF len, r4
VARDEF S_0, r5
VARDEF S_1, r6
VARDEF in0, _r7
VARDEF out32, r8
VARDEF A_Q140, sb
VARDEF A_Q141, sl
.set sp_S, 0
.globl SYM(SKP_Silk_resampler_private_AR2)
SYM(SKP_Silk_resampler_private_AR2):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #4
.set sp_len, 44
str r0, [sp, #sp_S]
ldr S_0, [r0], #4
ldr S_1, [r0], #-4
ldr len, [sp, #sp_len]
ldrsh A_Q140, [r3], #2
ldrsh A_Q141, [r3]
cmp len, #0
beq LR(1, f)
L(0)
ldrsh in0, [r2], #2
add out32, S_0, in0, lsl #8
str out32, [r1], #4
subs len, len, #1
mov out32, out32, lsl #2
smlawb S_0, out32, A_Q140, S_1
smulwb S_1, out32, A_Q141
bgt LR(0, b)
str S_0, [r0], #4
str S_1, [r0]
L(1)
add sp, sp, #4
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 10,005
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_decode_core_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#include "SKP_Silk_AsmPreproc.h"
#define MAX_LPC_ORDER 16
#define MAX_LPC_ORDER_INT32_OFFSET 64
#if EMBEDDED_ARM >= 5
VARDEF ptr_vec_Q10, r0
VARDEF ptr_pres_Q10, r1
VARDEF ptr_sLPC_Q14, r2
VARDEF ptr_A_Q12_tmp, r3
VARDEF ptr_LPC_Q14, r4
VARDEF val1_LPC_Q14, r5
VARDEF val_pres_Q10, r5
VARDEF val2_LPC_Q14, r6
VARDEF val_vec_Q10, r6
VARDEF val3_LPC_Q14, r8
VARDEF val4_LPC_Q14, sb
VARDEF val1_Atmp, sl
VARDEF val_LPC_Q14, sl
VARDEF val2_Atmp, ip
VARDEF val_subfr_length, _r7
VARDEF val_LPC_order, lr
VARDEF val_LPC_pred_Q10, lr
.globl SYM(SKP_Silk_decode_short_term_prediction)
SYM(SKP_Silk_decode_short_term_prediction):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
.set ptr_LPC_order, 40
.set ptr_subfr_length, 44
ldr val_LPC_order, [sp, #ptr_LPC_order]
ldr val_subfr_length, [sp, #ptr_subfr_length]
ands val1_Atmp, ptr_A_Q12_tmp, #3
add ptr_sLPC_Q14, ptr_sLPC_Q14, #MAX_LPC_ORDER_INT32_OFFSET
bne LR(2, f)
cmp val_LPC_order, #16
bne LR(1, f)
/*LPC_order == 16*/
L(0)
mov ptr_LPC_Q14, ptr_sLPC_Q14
ldmia ptr_A_Q12_tmp!, {val1_Atmp, val2_Atmp}
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
smulwb val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp
smlawt val_LPC_pred_Q10, val1_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
ldr val1_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
smlawt val_LPC_pred_Q10, val3_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
ldr val2_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
smlawt val_LPC_pred_Q10, val1_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
ldr val1_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
smlawt val_LPC_pred_Q10, val3_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
ldr val2_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
smlawt val_LPC_pred_Q10, val1_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
ldr val1_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
smlawt val_LPC_pred_Q10, val3_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
ldr val2_Atmp, [ptr_A_Q12_tmp], #-28
smlawb val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
smlawt val_LPC_pred_Q10, val1_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldr val_pres_Q10, [ptr_pres_Q10], #4
smlawb val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
smlawt val_LPC_pred_Q10, val3_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
subs val_subfr_length, val_subfr_length, #1
add val_vec_Q10, val_LPC_pred_Q10, val_pres_Q10
mov val_LPC_Q14, val_vec_Q10, lsl #4
str val_vec_Q10, [ptr_vec_Q10], #4
str val_LPC_Q14, [ptr_sLPC_Q14], #4
bgt LR(0, b)
ldmia sp!, {r4-r10, fp, ip, pc}
/*LPC_order == 10*/
L(1)
mov ptr_LPC_Q14, ptr_sLPC_Q14
ldr val2_Atmp, [ptr_A_Q12_tmp], #4
ldr val1_Atmp, [ptr_A_Q12_tmp], #4
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
smulwb val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp
smlawt val_LPC_pred_Q10, val3_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
ldr val2_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
smlawt val_LPC_pred_Q10, val1_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
ldr val1_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
smlawt val_LPC_pred_Q10, val3_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
ldr val2_Atmp, [ptr_A_Q12_tmp], #-16
smlawb val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
smlawt val_LPC_pred_Q10, val1_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldr val_pres_Q10, [ptr_pres_Q10], #4
smlawb val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
smlawt val_LPC_pred_Q10, val3_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
subs val_subfr_length, val_subfr_length, #1
add val_vec_Q10, val_LPC_pred_Q10, val_pres_Q10
mov val_LPC_Q14, val_vec_Q10, lsl #4
str val_vec_Q10, [ptr_vec_Q10], #4
str val_LPC_Q14, [ptr_sLPC_Q14], #4
bgt LR(1, b)
ldmia sp!, {r4-r10, fp, ip, pc}
L(2)
cmp val_LPC_order, #16
bne LR(4, f)
/*LPC_order == 16*/
L(3)
mov ptr_LPC_Q14, ptr_sLPC_Q14
ldrh val1_Atmp, [ptr_A_Q12_tmp], #2
ldr val2_Atmp, [ptr_A_Q12_tmp], #4
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
smulwb val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp
ldr val1_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val1_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
smlawt val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldr val2_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val3_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
smlawt val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldr val1_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val1_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
smlawt val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldr val2_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val3_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
smlawt val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldr val1_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val1_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
smlawt val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldr val2_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val3_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
smlawt val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldrh val1_Atmp, [ptr_A_Q12_tmp], #-30
smlawb val_LPC_pred_Q10, val1_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldr val_pres_Q10, [ptr_pres_Q10], #4
smlawt val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
smlawb val_LPC_pred_Q10, val3_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
subs val_subfr_length, val_subfr_length, #1
add val_vec_Q10, val_LPC_pred_Q10, val_pres_Q10
mov val_LPC_Q14, val_vec_Q10, lsl #4
str val_vec_Q10, [ptr_vec_Q10], #4
str val_LPC_Q14, [ptr_sLPC_Q14], #4
bgt LR(3, b)
ldmia sp!, {r4-r10, fp, ip, pc}
/*LPC_order == 10*/
L(4)
mov ptr_LPC_Q14, ptr_sLPC_Q14
ldrh val2_Atmp, [ptr_A_Q12_tmp], #2
ldr val1_Atmp, [ptr_A_Q12_tmp], #4
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
smulwb val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp
ldr val2_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val3_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
smlawt val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldr val1_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val1_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val1_LPC_Q14, val2_LPC_Q14}
smlawt val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldr val2_Atmp, [ptr_A_Q12_tmp], #4
smlawb val_LPC_pred_Q10, val3_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldmdb ptr_LPC_Q14!, {val3_LPC_Q14, val4_LPC_Q14}
smlawt val_LPC_pred_Q10, val2_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
ldr val1_Atmp, [ptr_A_Q12_tmp], #-18
smlawb val_LPC_pred_Q10, val1_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
ldr val_pres_Q10, [ptr_pres_Q10], #4
smlawt val_LPC_pred_Q10, val4_LPC_Q14, val2_Atmp, val_LPC_pred_Q10
smlawb val_LPC_pred_Q10, val3_LPC_Q14, val1_Atmp, val_LPC_pred_Q10
subs val_subfr_length, val_subfr_length, #1
add val_vec_Q10, val_LPC_pred_Q10, val_pres_Q10
mov val_LPC_Q14, val_vec_Q10, lsl #4
str val_vec_Q10, [ptr_vec_Q10], #4
str val_LPC_Q14, [ptr_sLPC_Q14], #4
bgt LR(4, b)
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
|
AgoraIO-Community/Solo
| 6,467
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_resampler_private_down_FIR_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
VARDEF out, r1
VARDEF ind, r2
VARDEF coef0, r3
VARDEF coef1, r4
VARDEF coef2, r5
#ifdef IPHONE
VARDEF val0, r6
VARDEF val1, r8
VARDEF val2, sb
VARDEF val3, _r7
#else
VARDEF val0, r6
VARDEF val1, _r7
VARDEF val2, r8
VARDEF val3, sb
#endif
VARDEF tmpptr, sl
VARDEF tmp0, ip
VARDEF tmp1, lr
.set sp_buf, 0
.set sp_maxi, 4
.globl SYM(SKP_Silk_resampler_private_down_FIR_INTERPOL0)
SYM(SKP_Silk_resampler_private_down_FIR_INTERPOL0):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #8
.set sp_inc, 48
cmp r3, #0
str r1, [sp, #sp_buf]
str r3, [sp, #sp_maxi]
ble LR(1, f)
ldrh r3, [r2], #2
ldrh r6, [r2], #2
ldrh r4, [r2], #2
ldrh _r7, [r2], #2
ldrh r5, [r2], #2
ldrh r8, [r2]
mov tmpptr, r1
add coef0, r3, r6, lsl #16
add coef1, r4, _r7, lsl #16
add coef2, r5, r8, lsl #16
ldmia tmpptr, {val0, val1}
add tmpptr, tmpptr, #40
ldr tmp0, [sp, #sp_inc]
ldmia tmpptr, {val2, val3}
mov ind, #0
L(0)
sub tmpptr, tmpptr, #32
add ind, ind, tmp0
add tmp0, val0, val3
add tmp1, val1, val2
ldmia tmpptr, {val0, val1}
add tmpptr, tmpptr, #24
ldmia tmpptr, {val2, val3}
smulwb out, tmp0, coef0
smlawt out, tmp1, coef0, out
sub tmpptr, tmpptr, #16
add tmp0, val0, val3
add tmp1, val1, val2
ldmia tmpptr, {val0, val1, val2, val3}
smlawb out, tmp0, coef1, out
smlawt out, tmp1, coef1, out
ldr tmpptr, [sp, #sp_buf]
add tmp0, val0, val3
add tmp1, val1, val2
smlawb out, tmp0, coef2, out
smlawt out, tmp1, coef2, out
mov tmp0, ind, asr #16
mov out, out, asr #5
add tmpptr, tmpptr, tmp0, lsl #2
add out, out, #1
cmp out, #0x10000
mov out, out, asr #1
ldr tmp1, [sp, #sp_maxi]
#ifdef _WINRT
ble LR(2, f)
mov out, #0x8000
L(2)
#else
movgt out, #0x8000
#endif
subge out, out, #1
cmn out, #0x8000
ldr tmp0, [sp, #sp_inc]
#ifdef _WINRT
bge LR(2, f)
mov out, #0x8000
L(2)
#else
movlt out, #0x8000
#endif
cmp ind, tmp1
#ifdef _WINRT
bge LR(2, f)
ldmia tmpptr, {val0, val1}
strh out, [r0], #2
add tmpptr, tmpptr, #40
ldmia tmpptr, {val2, val3}
b LR(0, b)
L(2)
strh out, [r0], #2
add tmpptr, tmpptr, #40
#else
ldmltia tmpptr, {val0, val1}
strh out, [r0], #2
add tmpptr, tmpptr, #40
ldmltia tmpptr, {val2, val3}
blt LR(0, b)
#endif
L(1)
add sp, sp, #8
ldmia sp!, {r4-r10, fp, ip, pc}
#ifdef IPHONE
VARDEF coefptr, _r7
VARDEF bufptr, sl
#else
VARDEF coefptr, sb
VARDEF bufptr, sl
#endif
.set sp_buf, 0
.set sp_coef, 4
.set sp_maxi, 8
.globl SYM(SKP_Silk_resampler_private_down_FIR_INTERPOL1)
SYM(SKP_Silk_resampler_private_down_FIR_INTERPOL1):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #12
.set sp_inc, 52
.set sp_fir_fracs, 56
cmp r3, #0
str r1, [sp, #sp_buf]
str r2, [sp, #sp_coef]
str r3, [sp, #sp_maxi]
blt LR(1, f)
mov tmp1, #0xFF00
mov ind, #0
add tmp1, tmp1, #0xFF
ldr coefptr, [sp, #sp_coef]
ldr bufptr, [sp, #sp_buf]
L(0)
ldr out, [sp, #sp_fir_fracs]
mov tmp0, ind, asr #16
add bufptr, bufptr, tmp0, lsl #2
and tmp1, ind, tmp1
smulwb tmp1, tmp1, out
ldmia bufptr!, {val0, val1, val2}
add coefptr, coefptr, tmp1, lsl #3
add coefptr, coefptr, tmp1, lsl #2
ldmia coefptr, {coef0, coef1, coef2}
sub tmp1, out, tmp1
ldr tmp0, [sp, #sp_inc]
ldr coefptr, [sp, #sp_coef]
smulwb out, val0, coef0
smlawt out, val1, coef0, out
smlawb out, val2, coef1, out
ldmia bufptr!, {val0, val1, val2}
sub tmp1, tmp1, #1
add ind, ind, tmp0
add coefptr, coefptr, tmp1, lsl #3
add coefptr, coefptr, tmp1, lsl #2
smlawt out, val0, coef1, out
smlawb out, val1, coef2, out
smlawt out, val2, coef2, out
ldmia coefptr, {coef0, coef1, coef2}
ldmia bufptr!, {val0, val1, val2}
ldr tmp0, [sp, #sp_maxi]
mov tmp1, #0xFF00
add tmp1, tmp1, #0xFF
smlawt out, val0, coef2, out
smlawb out, val1, coef2, out
smlawt out, val2, coef1, out
ldmia bufptr!, {val0, val1, val2}
ldr coefptr, [sp, #sp_coef]
ldr bufptr, [sp, #sp_buf]
smlawb out, val0, coef1, out
smlawt out, val1, coef0, out
smlawb out, val2, coef0, out
mov out, out, asr #5
add out, out, #1
cmp out, #0x10000
mov out, out, asr #1
#ifdef _WINRT
ble LR(2, f)
mov out, #0x8000
L(2)
#else
movgt out, #0x8000
#endif
subge out, out, #1
cmn out, #0x8000
#ifdef _WINRT
bge LR(2, f)
mov out, #0x8000
L(2)
#else
movlt out, #0x8000
#endif
cmp ind, tmp0
strh out, [r0], #2
blt LR(0, b)
L(1)
add sp, sp, #12
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 7,104
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_warped_autocorrelation_FIX_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#define QC 10
#define QS 14
#include "SKP_Silk_AsmPreproc.h"
#if ( EMBEDDED_ARM >= 6 )
VARDEF tmp1_QS, r4
VARDEF length, r5
VARDEF state_QS_ptr, r6
VARDEF val_i, _r7
VARDEF tmp3, r8
VARDEF tmp4, sb
VARDEF corr_QC_ptr, sl
VARDEF state_QS1, ip
VARDEF state_QS2, lr
VARDEF ret0, r0
VARDEF ret1, r1
VARDEF state_QS0, r2
VARDEF warping_Q16, r3
.set sp_state_QS, 0
.set sp_corr_QS, 68
.set sp_corr_ptr, 204
.set sp_scale_ptr, 208
.set sp_input_ptr, 212
.globl SYM(SKP_Silk_warped_autocorrelation_FIX)
SYM(SKP_Silk_warped_autocorrelation_FIX):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #216
.set ptr_length, 256
.set ptr_order, 260
.set ptr_tmp1_QS, 264
.set ptr_state_QS, 268
.set ptr_corr_QC, 272
str r0, [sp, #sp_corr_ptr]
str r1, [sp, #sp_scale_ptr]
add state_QS_ptr, sp, #sp_state_QS
add corr_QC_ptr, sp, #sp_corr_QS
mov r4, #0
mov r5, #0
mov _r7, #17
L(2)
subs _r7, _r7, #1
str r4, [state_QS_ptr], #4
stmia corr_QC_ptr!, {r4, r5}
bgt LR(2, b)
ldr length, [sp, #ptr_length]
/*OUTTER_LOOP*/
L(1)
ldrsh tmp1_QS, [r2], #2
add state_QS_ptr, sp, #sp_state_QS
add corr_QC_ptr, sp, #sp_corr_QS
ldr val_i, [sp, #ptr_order]
str r2, [sp, #sp_input_ptr]
mov tmp1_QS, tmp1_QS, lsl #14
sub val_i, val_i, #2
ldr state_QS1, [state_QS_ptr], #4
ldr state_QS2, [state_QS_ptr], #4
str tmp1_QS, [state_QS_ptr, #-8]
sub ret0, state_QS2, tmp1_QS
mov state_QS0, tmp1_QS
smull tmp3, tmp4, tmp1_QS, state_QS0
smlawb tmp1_QS, ret0, warping_Q16, state_QS1
ldmia corr_QC_ptr, {ret0, ret1}
mov tmp3, tmp3, lsr #18
orr tmp3, tmp3, tmp4, lsl #14
adds ret0, ret0, tmp3
adc ret1, ret1, tmp4, asr #18
stmia corr_QC_ptr!, {ret0, ret1}
ldr state_QS1, [state_QS_ptr], #4
str tmp1_QS, [state_QS_ptr, #-8]
sub ret0, state_QS1, tmp1_QS
smull tmp3, tmp4, tmp1_QS, state_QS0
smlawb tmp1_QS, ret0, warping_Q16, state_QS2
ldmia corr_QC_ptr, {ret0, ret1}
mov tmp3, tmp3, lsr #18
orr tmp3, tmp3, tmp4, lsl #14
adds ret0, ret0, tmp3
adc ret1, ret1, tmp4, asr #18
stmia corr_QC_ptr!, {ret0, ret1}
/*INNER_LOOP*/
L(0)
ldr state_QS2, [state_QS_ptr], #4
str tmp1_QS, [state_QS_ptr, #-8]
smull tmp3, tmp4, tmp1_QS, state_QS0
ldmia corr_QC_ptr, {ret0, ret1}
sub tmp1_QS, state_QS2, tmp1_QS
smlawb tmp1_QS, tmp1_QS, warping_Q16, state_QS1
mov tmp3, tmp3, lsr #18
orr tmp3, tmp3, tmp4, lsl #14
ldr state_QS1, [state_QS_ptr], #4
str tmp1_QS, [state_QS_ptr, #-8]
adds ret0, ret0, tmp3
adc ret1, ret1, tmp4, asr #18
stmia corr_QC_ptr!, {ret0, ret1}
smull tmp3, tmp4, tmp1_QS, state_QS0
ldmia corr_QC_ptr, {ret0, ret1}
sub tmp1_QS, state_QS1, tmp1_QS
smlawb tmp1_QS, tmp1_QS, warping_Q16, state_QS2
mov tmp3, tmp3, lsr #18
orr tmp3, tmp3, tmp4, lsl #14
adds ret0, ret0, tmp3
adc ret1, ret1, tmp4, asr #18
subs val_i, val_i, #2
stmia corr_QC_ptr!, {ret0, ret1}
bgt LR(0, b)
str tmp1_QS, [state_QS_ptr, #-4]
smull tmp3, tmp4, tmp1_QS, state_QS0
ldmia corr_QC_ptr, {ret0, ret1}
ldr r2, [sp, #sp_input_ptr]
mov tmp3, tmp3, lsr #18
orr tmp3, tmp3, tmp4, lsl #14
adds ret0, ret0, tmp3
adc ret1, ret1, tmp4, asr #18
subs length, length, #1
stmia corr_QC_ptr!, {ret0, ret1}
bgt LR(1, b)
ldr r4, [sp, #sp_corr_ptr]
ldr state_QS_ptr, [sp, #sp_scale_ptr]
add corr_QC_ptr, sp, #sp_corr_QS
ldr val_i, [sp, #ptr_order]
ldmia corr_QC_ptr!, {state_QS1, state_QS2}
cmp state_QS2, #0
clz tmp3, state_QS1
clz tmp4, state_QS2
#ifdef _WINRT
bne LR(6, f)
add tmp4, tmp3, #32
L(6)
#else
addeq tmp4, tmp3, #32
#endif
sub tmp4, tmp4, #35
cmn tmp4, #22
#ifdef _WINRT
bge LR(6, f)
mov tmp4, #-22
L(6)
cmp tmp4, #20
ble LR(6, f)
mov tmp4, #20
L(6)
#else
movlt tmp4, #-22
cmp tmp4, #20
movgt tmp4, #20
#endif
add tmp3, tmp4, #10
rsb tmp3, tmp3, #0
str tmp3, [state_QS_ptr]
cmp tmp4, #0
bge LR(3, f)
rsb tmp4, tmp4, #0
rsb tmp3, tmp4, #32
mov state_QS2, state_QS2, lsl tmp3
mov state_QS1, state_QS1, lsr tmp4
orr state_QS1, state_QS1, state_QS2
ldmia corr_QC_ptr!, {r0, r1, r2, r3}
str state_QS1, [r4], #4
L(4)
subs val_i, val_i, #2
mov r0, r0, lsr tmp4
#ifdef _WINRT
mov state_QS1, r1, lsl tmp3
orr state_QS1, r0, state_QS1
#else
orr state_QS1, r0, r1, lsl tmp3
#endif
mov r2, r2, lsr tmp4
#ifdef _WINRT
mov state_QS2, r3, lsl tmp3
orr state_QS2, r2, state_QS2
#else
orr state_QS2, r2, r3, lsl tmp3
#endif
#ifdef _WINRT
ble LR(6, f)
ldmia corr_QC_ptr!, {r0, r1, r2, r3}
stmia r4!, {state_QS1, state_QS2}
b LR(4, b)
L(6)
stmia r4!, {state_QS1, state_QS2}
#else
ldmgtia corr_QC_ptr!, {r0, r1, r2, r3}
stmia r4!, {state_QS1, state_QS2}
bgt LR(4, b)
#endif
add sp, sp, #216
ldmia sp!, {r4-r10, fp, ip, pc}
L(3)
mov state_QS1, state_QS1, lsl tmp4
ldr r1, [corr_QC_ptr], #8
ldr r3, [corr_QC_ptr], #8
str state_QS1, [r4], #4
L(5)
subs val_i, val_i, #2
mov r0, r1, lsl tmp4
mov r2, r3, lsl tmp4
#ifdef _WINRT
ble LR(6, f)
ldr r1, [corr_QC_ptr], #8
ldr r3, [corr_QC_ptr], #8
stmia r4!, {r0, r2}
b LR(5, b)
L(6)
stmia r4!, {r0, r2}
#else
ldrgt r1, [corr_QC_ptr], #8
ldrgt r3, [corr_QC_ptr], #8
stmia r4!, {r0, r2}
bgt LR(5, b)
#endif
add sp, sp, #216
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 2,964
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_A2NLSF_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=6
VARDEF y32, r3
VARDEF pn1, r4
VARDEF pn2, r5
VARDEF lo, r6
VARDEF hi, r8
.globl SYM(SKP_Silk_A2NLSF_eval_poly)
SYM(SKP_Silk_A2NLSF_eval_poly):
stmdb sp!, {r4-r8, fp, ip, lr}
add fp, sp, #28
add r0, r0, r2, lsl #2
ldr y32, [r0], #-4
tst r2, #1
beq LR(1, f)
ldr pn1, [r0], #-4
sub r2, r2, #1
mov r1, r1, lsl #4
L(0)
smull lo, hi, y32, r1
subs r2, r2, #1
add y32, pn1, hi, lsl #16
ldr pn1, [r0], #-4
add y32, y32, lo, lsr #16
bgt LR(0, b)
smull lo, hi, y32, r1
add y32, pn1, hi, lsl #16
add r0, y32, lo, lsr #16
ldmia sp!, {r4-r8, fp, ip, pc}
L(1)/*EVEN:*/
add r0, r0, #4
ldmdb r0!, {pn1, pn2}
sub r2, r2, #2
mov r1, r1, lsl #4
L(0)
smull lo, hi, y32, r1
subs r2, r2, #2
add y32, pn2, hi, lsl #16
add y32, y32, lo, lsr #16
smull lo, hi, y32, r1
add y32, pn1, hi, lsl #16
ldmdb r0!, {pn1, pn2}
add y32, y32, lo, lsr #16
bgt LR(0, b)
smull lo, hi, y32, r1
add y32, pn2, hi, lsl #16
add y32, y32, lo, lsr #16
smull lo, hi, y32, r1
add y32, pn1, hi, lsl #16
add r0, y32, lo, lsr #16
ldmia sp!, {r4-r8, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 3,468
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_resampler_up2_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
#define SKP_Silk_resampler_up2_lq_0 0x1FA6
#define SKP_Silk_resampler_up2_lq_1 0x8FAF
VARDEF xy0, r4
VARDEF xy1, r5
VARDEF up2_coefs, _r7
VARDEF S_0, r6
VARDEF S_1, r8
VARDEF in, sb
VARDEF out0, sl
VARDEF out1, r0
.set sp_S, 0
.globl SYM(SKP_Silk_resampler_up2)
SYM(SKP_Silk_resampler_up2):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #4
mov up2_coefs, #0x1F000000
ldrsh in, [r2], #2
add up2_coefs, up2_coefs, #0xA60000
str r0, [sp, #sp_S]
add up2_coefs, up2_coefs, #0x8F00
ldmia r0, {S_0, S_1}
add up2_coefs, up2_coefs, #0xAF
mov ip, #512
cmp r3, #0
beq LR(1, f)
L(0)
mov in, in, lsl #10
sub xy0, in, S_0
sub xy1, in, S_1
smulwt xy0, xy0, up2_coefs
smlawb xy1, xy1, up2_coefs, xy1
add out0, S_0, xy0
add out1, S_1, xy1
add S_0, in, xy0
add S_1, in, xy1
qadd out0, out0, ip
qadd out1, out1, ip
#if EMBEDDED_ARM<6
cmp out0, #0x2000000
movge out0, #0x2000000
subge out0, out0, #1
cmn out0, #0x2000000
movlt out0, #0x2000000
cmp out1, #0x2000000
movge out1, #0x2000000
subge out1 ,out1, #1
cmn out1, #0x2000000
movlt out1, #0x2000000
mov out0, out0, asr #10
mov out1, out1, asr #10
#else
ssat out0, #16, out0, asr #10
ssat out1, #16, out1, asr #10
#endif
subs r3, r3, #1
#ifdef _WINRT
ble LR(2, f)
ldrsh in, [r2], #2
strh out0, [r1], #2
strh out1, [r1], #2
b LR(0, b)
L(2)
strh out0, [r1], #2
strh out1, [r1], #2
#else
ldrgtsh in, [r2], #2
strh out0, [r1], #2
strh out1, [r1], #2
bgt LR(0, b)
#endif
ldr r0, [sp, #sp_S]
stmia r0, {S_0, S_1}
L(1)
add sp, sp, #4
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 4,326
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_prefilter_FIX_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#include "SKP_Silk_AsmPreproc.h"
#if ( EMBEDDED_ARM >= 6 )
VARDEF ptr_state, r0
VARDEF ptr_res, r1
VARDEF val_tmp2, r1
VARDEF val_state0, r1
VARDEF ptr_coef, r2
VARDEF ptr_input, r3
VARDEF val_tmp, r3
VARDEF val_lambda, r4
VARDEF val_state1, r5
VARDEF val_state2, r6
VARDEF val_tmp1, _r7
VARDEF val_coef, r8
VARDEF val_input, sb
VARDEF val_acc, sl
VARDEF val_order, ip
VARDEF val_length, lr
.set sp_state_ptr, 0
.set sp_res_ptr, 4
.set sp_coef_Q13_ptr, 8
.set sp_input_ptr, 12
.globl SYM(SKP_Silk_warped_LPC_analysis_filter_FIX)
SYM(SKP_Silk_warped_LPC_analysis_filter_FIX):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #16
.set ptr_lambda_Q16, 56
.set ptr_length, 60
.set ptr_order, 64
str r0, [sp, #sp_state_ptr]
str r1, [sp, #sp_res_ptr]
str r2, [sp, #sp_coef_Q13_ptr]
str r3, [sp, #sp_input_ptr]
ldr val_lambda, [sp, #ptr_lambda_Q16]
ldr val_length, [sp, #ptr_length]
/*OUTTER_LOOP*/
L(1)
ldmia ptr_state, {val_state0, val_state1, val_state2}
ldrsh val_input, [ptr_input], #2
ldrh val_coef, [ptr_coef], #2
ldr val_order, [sp, #ptr_order]
smlawb val_tmp2, val_state1, val_lambda, val_state0
str ptr_input, [sp, #sp_input_ptr]
mov val_tmp1, val_input, lsl #14
sub val_tmp, val_state2, val_tmp2
str val_tmp1, [ptr_state], #4
str val_tmp2, [ptr_state], #4
smlawb val_tmp1, val_tmp, val_lambda, val_state1
smulwb val_acc, val_tmp2, val_coef
sub val_order, val_order, #2
/*INNER_LOOP*/
L(0)
ldrh val_coef, [ptr_coef], #2
ldr val_state1, [ptr_state, #4]
str val_tmp1, [ptr_state], #4
smlawb val_acc, val_tmp1, val_coef, val_acc
sub val_tmp, val_state1, val_tmp1
smlawb val_tmp2, val_tmp, val_lambda, val_state2
ldrh val_coef, [ptr_coef], #2
ldr val_state2, [ptr_state, #4]
str val_tmp2, [ptr_state], #4
subs val_order, val_order, #2
smlawb val_acc, val_tmp2, val_coef, val_acc
sub val_tmp, val_state2, val_tmp2
smlawb val_tmp1, val_tmp, val_lambda, val_state1
bgt LR(0, b)
str val_tmp1, [ptr_state]
ldrh val_coef, [ptr_coef], #2
ldr ptr_res, [sp, #sp_res_ptr]
ldr ptr_input, [sp, #sp_input_ptr]
ldr ptr_coef, [sp, #sp_coef_Q13_ptr]
ldr ptr_state, [sp, #sp_state_ptr]
smlawb val_acc, val_tmp1, val_coef, val_acc
mov val_acc, val_acc, asr #10
add val_acc, val_acc, #1
mov val_acc, val_acc, asr #1
sub val_input, val_input, val_acc
ssat val_input, #16, val_input
strh val_input, [ptr_res], #2
subs val_length, val_length, #1
str ptr_res, [sp, #sp_res_ptr]
bgt LR(1, b)
add sp, sp, #16
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
|
AgoraIO-Community/Solo
| 5,057
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_NLSF_VQ_sum_error_FIX_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if __arm__
#include "SKP_Silk_AsmPreproc.h"
#if ( EMBEDDED_ARM >= 6 )
VARDEF val_N, r4
VARDEF val_K, r5
VARDEF val_order, r6
VARDEF val_in_Q15, _r7
VARDEF val_cb_Q15, r8
VARDEF val_wtmp_Q6, sb
VARDEF val_sum_error, sl
VARDEF val_diff, ip
VARDEF val_tmp, lr
VARDEF val_in_Q15_tmp, ip
VARDEF val_wtmp_Q6_tmp, lr
VARDEF ptr_wtmp, _r7
VARDEF val0_wtmp, sb
VARDEF val1_wtmp, r5
VARDEF val2_wtmp, r8
VARDEF ptr_err_Q20, r0
VARDEF ptr_in_Q15, r1
VARDEF ptr_w_Q6, r2
VARDEF ptr_pCB_Q15, r3
.set sp_wtmp, 0
.set sp_err_Q20, 32
.set sp_in_Q15, 36
.set sp_w_Q6, 40
.set sp_pCB_Q15, 44
.globl SYM(SKP_Silk_NLSF_VQ_sum_error_FIX)
SYM(SKP_Silk_NLSF_VQ_sum_error_FIX):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #48
.set ptr_N, 88
.set ptr_K, 92
.set ptr_LPC_order, 96
str r0, [sp, #sp_err_Q20]
str r1, [sp, #sp_in_Q15]
str r2, [sp, #sp_w_Q6]
str r3, [sp, #sp_pCB_Q15]
ldr val_N, [sp, #ptr_N]
ldr val_order, [sp, #ptr_LPC_order]
ldr val1_wtmp, [r2], #4
ldr val2_wtmp, [r2], #4
sub val_order, val_order, #2
add ptr_wtmp, sp, #sp_wtmp
L(3)
pkhbt val0_wtmp, val1_wtmp, val2_wtmp, lsl #16
subs val_order, val_order, #2
ldr val1_wtmp, [r2], #4
ldr val2_wtmp, [r2], #4
str val0_wtmp, [ptr_wtmp], #4
bgt LR(3, b)
pkhbt val0_wtmp, val1_wtmp, val2_wtmp, lsl #16
str val0_wtmp, [ptr_wtmp], #4
ands val_tmp, ptr_pCB_Q15, #3
bgt LR(4, f)
/*OUTTER_LOOP*/
L(2)
ldr ptr_pCB_Q15, [sp, #sp_pCB_Q15]
ldr val_K, [sp, #ptr_K]
/*MIDDLE_LOOP*/
L(1)
ldr ptr_in_Q15, [sp, #sp_in_Q15]
add ptr_w_Q6, sp, #sp_wtmp
ldr val_order, [sp, #ptr_LPC_order]
mov val_sum_error, #0
/*INNER_LOOP*/
L(0)
ldmia ptr_in_Q15!, {val_in_Q15, val_in_Q15_tmp}
ldr val_wtmp_Q6, [ptr_w_Q6], #4
ldr val_cb_Q15, [ptr_pCB_Q15], #4
subs val_order, val_order, #2
pkhbt val_in_Q15, val_in_Q15, val_in_Q15_tmp, lsl #16
ssub16 val_diff, val_in_Q15, val_cb_Q15
smulbb val_tmp, val_diff, val_diff
smultt val_diff, val_diff, val_diff
smlawb val_sum_error, val_tmp, val_wtmp_Q6, val_sum_error
smlawt val_sum_error, val_diff, val_wtmp_Q6, val_sum_error
bgt LR(0, b)
subs val_K, val_K, #1
str val_sum_error, [ptr_err_Q20], #4
bgt LR(1, b)
subs val_N, val_N, #1
str ptr_in_Q15, [sp, #sp_in_Q15]
bgt LR(2, b)
add sp, sp, #48
ldmia sp!, {r4-r10, fp, ip, pc}
L(4)
ldr ptr_pCB_Q15, [sp, #sp_pCB_Q15]
ldr val_K, [sp, #ptr_K]
/*MIDDLE_LOOP*/
L(1)
ldr ptr_in_Q15, [sp, #sp_in_Q15]
add ptr_w_Q6, sp, #sp_wtmp
ldr val_order, [sp, #ptr_LPC_order]
mov val_sum_error, #0
/*INNER_LOOP*/
L(0)
ldmia ptr_in_Q15!, {val_in_Q15, val_in_Q15_tmp}
ldr val_wtmp_Q6, [ptr_w_Q6], #4
ldrh val_cb_Q15, [ptr_pCB_Q15], #2
ldrh val_tmp, [ptr_pCB_Q15], #2
subs val_order, val_order, #2
pkhbt val_in_Q15, val_in_Q15, val_in_Q15_tmp, lsl #16
pkhbt val_cb_Q15, val_cb_Q15, val_tmp, lsl #16
ssub16 val_diff, val_in_Q15, val_cb_Q15
smulbb val_tmp, val_diff, val_diff
smultt val_diff, val_diff, val_diff
smlawb val_sum_error, val_tmp, val_wtmp_Q6, val_sum_error
smlawt val_sum_error, val_diff, val_wtmp_Q6, val_sum_error
bgt LR(0, b)
subs val_K, val_K, #1
str val_sum_error, [ptr_err_Q20], #4
bgt LR(1, b)
subs val_N, val_N, #1
str ptr_in_Q15, [sp, #sp_in_Q15]
bgt LR(4, b)
add sp, sp, #48
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 3,883
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_lin2log_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
VARDEF val_lz, r1
VARDEF val_shift, r2
VARDEF val_frac, r3
VARDEF val_ret1, r1
VARDEF val_128minfrac, r2
VARDEF val_mul_ret, r0
VARDEF val_add_ret, r3
VARDEF const1, r1
.globl SYM(SKP_Silk_lin2log)
SYM(SKP_Silk_lin2log):
stmdb sp!, {r4-r5, fp, ip, lr}
add fp, sp, #16
clz val_lz, r0 /*lz*/
cmp val_lz, #24
sub val_shift, val_lz, #24
#ifdef _WINRT
bge LR(0, f)
rsb val_shift, val_lz, #24
mov val_frac, r0, asr val_shift
b LR(1, f)
L(0)
mov val_frac, r0, lsl val_shift
L(1)
#else
rsblt val_shift, val_lz, #24
movlt val_frac, r0, asr val_shift
movge val_frac, r0, lsl val_shift
#endif
and val_frac, val_frac, #0x7F /*frac_Q7*/
rsb val_ret1, val_lz, #31 /*31-lz*/
rsb val_128minfrac, val_frac, #128 /*128-frac_Q7*/
mov val_ret1, val_ret1, lsl #7
mul val_mul_ret, val_frac, val_128minfrac /*SKP_MUL(frac_Q7, 128 - frac_Q7)*/
add val_add_ret, val_ret1, val_frac
mov const1, #179
smlawb r0, val_mul_ret, const1, val_add_ret
ldmia sp!, {r4-r5, fp, ip, pc}
#elif EMBEDDED_ARM>=4
VARDEF val_lz, r0
VARDEF val_in, r4
VARDEF val_shift, r1
VARDEF val_frac, r2
VARDEF val_ret1, r1
VARDEF val_128minfrac, r3
VARDEF val_mul_ret, r3
VARDEF tmp0, r4
VARDEF const1, r2
VARDEF val_ret, r0
.globl SYM(SKP_Silk_lin2log)
SYM(SKP_Silk_lin2log):
stmdb sp!, {r4-r5, fp, ip, lr}
add fp, sp, #16
mov val_in, r0
bl SYM(SKP_Silk_CLZ32)
cmp val_lz, #24
sub val_shift, val_lz, #24
rsblt val_shift, val_lz, #24
movlt val_frac, val_in, asr val_shift
movge val_frac, val_in, lsl val_shift
and val_frac, val_frac, #0x7F /*frac_Q7*/
rsb val_ret1, val_lz, #31 /*31-lz*/
rsb val_128minfrac, val_frac, #128 /*128-frac_Q7*/
mov val_ret1, val_ret1, lsl #7
mul val_mul_ret, val_frac, val_128minfrac /*SKP_MUL(frac_Q7, 128 - frac_Q7)*/
add val_ret, val_ret1, val_frac
mov tmp0, #0
mov const1, #0xB30000
smlal tmp0, val_ret, val_mul_ret, const1
ldmia sp!, {r4-r5, fp, ip, pc}
#endif
END
#endif
|
AgoraIO-Community/Solo
| 3,256
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_clz_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if (EMBEDDED_ARM>0) && (EMBEDDED_ARM<5)
.globl SYM(SKP_Silk_CLZ16)
.globl SYM(SKP_Silk_CLZ32)
SYM(SKP_Silk_CLZ16):
str lr, [sp, #-4]!
mov r2, r0
mov r0, #0
ands r1, r2, #0xF000
movne r1, r2, asr #12
bne 0f
add r0, r0, #4
ands r1, r2, #0xF00
movne r1, r2, asr #8
bne 0f
add r0, r0, #4
ands r1, r2, #0xF0
movne r1, r2, asr #4
bne 0f
add r0, r0, #4
mov r1, r2
0:
ands r2, r1, #0x8
bne 1f
add r0, r0, #1
ands r2, r1, #0x4
bne 1f
add r0, r0, #1
ands r2, r1, #0x2
bne 1f
add r0, r0, #1
ands r2, r1, #0x1
bne 1f
add r0, r0, #1
1:
ldr pc, [sp], #4
SYM(SKP_Silk_CLZ32):
str lr, [sp, #-4]!
mov r2, r0
mov r0, #0
ands r1, r2, #0xF0000000
movne r1, r2, asr #28
bne 0f
add r0, r0, #4
ands r1, r2, #0xF000000
movne r1, r2, asr #24
bne 0f
add r0, r0, #4
ands r1, r2, #0xF00000
movne r1, r2, asr #20
bne 0f
add r0, r0, #4
ands r1, r2, #0xF0000
movne r1, r2, asr #16
bne 0f
add r0, r0, #4
ands r1, r2, #0xF000
movne r1, r2, asr #12
bne 0f
add r0, r0, #4
ands r1, r2, #0xF00
movne r1, r2, asr #8
bne 0f
add r0, r0, #4
ands r1, r2, #0xF0
movne r1, r2, asr #4
bne 0f
add r0, r0, #4
mov r1, r2
0:
ands r2, r1, #0x8
bne 1f
add r0, r0, #1
ands r2, r1, #0x4
bne 1f
add r0, r0, #1
ands r2, r1, #0x2
bne 1f
add r0, r0, #1
ands r2, r1, #0x1
bne 1f
add r0, r0, #1
1:
ldr pc, [sp], #4
#endif
#endif
|
AgoraIO-Community/Solo
| 47,507
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_MA_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=7
VARDEF val_order, r5
VARDEF val_len, r4
VARDEF tmp_len, r5
.set sp_ptr_in, 0
.set sp_ptr_B, 4
.set sp_ptr_S, 8
.set sp_ptr_out, 12
.globl SYM(SKP_Silk_MA_Prediction)
SYM(SKP_Silk_MA_Prediction):
stmdb sp!, {r4-r10, fp, ip, lr}
vpush {q0-q7}
vpush {q8-q11}
add fp, sp, #228
sub sp, sp, #16
.set arg_len, 248
.set arg_order, 252
/*LOAD INPUT ARGS*/
ldr val_order, [sp, #arg_order] /*order*/
ldr val_len, [sp, #arg_len] /*len*/
ands _r7, r1, #3 /*CHECK: if ( B is 4 byte aligned ) Prerequest for ARMv6 SIMD*/
bne LR(2, f)
ands r6, val_order, #1 /*CHECK: if ( order % 2 == 0 ) Prerequest for ARMv6 SIMD*/
bne LR(2, f)
cmp val_order, #8 /*CHECK: if ( order == 8 ) ARMv7 SIMD*/
beq LR(5, f)/*SYM(SKP_Silk_MA_Prediction_ARMv7_order8)*/
cmp val_order, #12 /*CHECK: if ( order == 12 ) ARMv7 SIMD*/
beq LR(6, f)/*SYM(SKP_Silk_MA_Prediction_ARMv7_order12)*/
cmp val_order, #16 /*CHECK: if ( order == 16 ) ARMv7 SIMD*/
beq LR(7, f)/*SYM(SKP_Silk_MA_Prediction_ARMv7_order16)*/
cmp val_order, #6 /*CHECK: if ( order >= 6 ) Prerequest for ARMv6 SIMD*/
blt LR(2, f)
VARDEF ptr1_in, sb
VARDEF ptr1_out, sl
VARDEF ptr1_S, ip
VARDEF ptr1_B, lr
VARDEF val1_in, r0
VARDEF val1_B, r6
VARDEF val1_S0, r1
VARDEF val1_S1, r2
VARDEF val1_S2, r3
VARDEF val1_SO1, _r7
VARDEF val1_SO2, r8
VARDEF val1_out, r1
VARDEF val1_tmp, r3
// ARMv6 SIMD
// order % 2 == 0
str r0, [sp, #sp_ptr_in]
str r1, [sp, #sp_ptr_B]
str r2, [sp, #sp_ptr_S]
str r3, [sp, #sp_ptr_out]
mov ptr1_in, r0 /*in*/
mov ptr1_out, r3 /*out*/
L(0)
ldr ptr1_S, [sp, #sp_ptr_S] /*S*/
ldr ptr1_B, [sp, #sp_ptr_B] /*B*/
ldrsh val1_in, [ptr1_in], #2 /*in[k]*/
ldr val1_S0, [ptr1_S], #4 /*S[0]*/
ldr val_order, [sp, #arg_order] /*order*/
ldr val1_S1, [ptr1_S], #4 /*S[1]*/
rsb val1_tmp, val1_S0, val1_in, lsl #12 /*SKP_LSHIFT(in16, 12) - S[0]*/
ldr val1_B, [ptr1_B], #4 /*B[0], B[1]*/
mov val1_tmp, val1_tmp, asr #11
sub val_order, val_order, #4 /*order - 2 - 2*/
add val1_out, r3, #1 /*SKP_RSHIFT_ROUND*/
ldr val1_S2, [ptr1_S], #4 /*S[2]*/
ssat val1_out, #16, val1_out, asr #1 /*SKP_SAT16( out32 )*/
strh val1_out, [ptr1_out], #2 /*save it to out[k]*/
L(1)
smlabb val1_SO1, val1_in, val1_B, val1_S1 /*SKP_SMLABB(S[d + 1], in16, B32)*/
smlabt val1_SO2, val1_in, val1_B, val1_S2 /*SKP_SMLABT(S[d + 2], in16, B32)*/
ldr val1_S1, [ptr1_S], #4 /*S[d+1]*/
ldr val1_S2, [ptr1_S], #-16 /*S[d+2]*/
ldr val1_B, [ptr1_B], #4 /*B[d], B[d+1]*/
subs val_order, val_order, #2
str val1_SO1, [ptr1_S], #4
str val1_SO2, [ptr1_S], #16
bgt LR(1, b)
smlabb val1_SO1, val1_in, val1_B, val1_S1 /*SKP_SMLABB(S[d + 1], in16, B32)*/
smlabt val1_SO2, val1_in, val1_B, val1_S2 /*SKP_SMLABT(S[d + 2], in16, B32)*/
ldr val1_S1, [ptr1_S], #-12 /*S[d+1]*/
ldr val1_B, [ptr1_B] /*B[d], B[d+1]*/
str val1_SO1, [ptr1_S], #4
str val1_SO2, [ptr1_S], #4
smlabb val1_SO1, val1_in, val1_B, val1_S1 /*SKP_SMLABB(S[d + 1], in16, B32)*/
smulbt val1_SO2, val1_in, val1_B /*SKP_SMLABT(S[d + 2], in16, B32)*/
subs val_len, val_len, #1
str val1_SO1, [ptr1_S], #4
str val1_SO2, [ptr1_S]
bgt LR(0, b)
add sp, sp, #16
vpop {q8-q11}
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
VARDEF ptr2_in, r6
VARDEF ptr2_out, sb
VARDEF val2_S0, lr
VARDEF ptr2_B, _r7
VARDEF ptr2_S, r8
VARDEF val2_in, r0
VARDEF val2_B, r2
VARDEF val2_B1, r1
VARDEF val2_S1, r3
VARDEF val2_out, r1
VARDEF val2_S2, r2
// order % 2 != 0
L(2)
add r2, r2, #4
str r0, [sp, #sp_ptr_in]
str r1, [sp, #sp_ptr_B]
str r2, [sp, #sp_ptr_S]
str r3, [sp, #sp_ptr_out]
mov ptr2_in, r0 /*in_ptr*/
mov ptr2_out, r3 /*out_ptr*/
ldr val2_S0, [r2, #-4] /*S0*/
L(0)
ldrsh val2_in, [ptr2_in], #2 /*in[k]*/
ldr val_order, [sp, #arg_order] /*order*/
ldr ptr2_B, [sp, #sp_ptr_B]
ldr ptr2_S, [sp, #sp_ptr_S] /*S_ptr*/
rsb val2_out, val2_S0, val2_in, lsl #12
ldrsh val2_in, [ptr2_B], #2
mov val2_out, val2_out, asr #11
ldr val2_S1, [ptr2_S]
add val2_out, val2_out, #1
smlabb val2_S0, val2_in, val2_in, val2_S1
ssat val2_out, #16, val2_out, asr #1
sub val_order, val_order, #3
ldr val2_S1, [ptr2_S, #4]
strh val2_out, [ptr2_out], #2
ldrsh val2_B1, [ptr2_B], #2
L(1)
smlabb val2_S2, val2_in, val2_B1, val2_S1
ldr val2_S1, [ptr2_S, #8]
ldrsh val2_B1, [ptr2_B], #2
str val2_S2, [ptr2_S], #4
subs val_order, val_order, #1
bgt LR(1, b)
smlabb val2_S2, val2_in, val2_B1, val2_S1
ldrsh val2_B1, [ptr2_B], #2
str val2_S2, [ptr2_S], #4
smulbb val2_S2, val2_in, val2_B1
subs val_len, val_len, #1
str val2_S2, [ptr2_S]
bgt LR(0, b)
ldr val2_S2, [sp, #sp_ptr_S]
str val2_S0, [r2, #-4]
add sp, sp, #16
vpop {q8-q11}
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
/*SYM(SKP_Silk_MA_Prediction_ARMv7_order8):*/
L(5)
VARDEF ptr3_in, sb
VARDEF ptr3_out, sl
VARDEF val3_rS0, r6
VARDEF const3_2048, r3
VARDEF val3_in0, r0
VARDEF val3_in1, r1
VARDEF val3_out32, r8
VARDEFD val3_B0_lo, d0
VARDEFD val3_b0_hi, d1
VARDEFQ val3_S0, q2
VARDEFD val3_S0_lo, d4
VARDEFD val3_S0_hi, d5
VARDEFQ val3_S1, q3
VARDEFD val3_S1_lo, d6
VARDEFD val3_S1_hi, d7
VARDEFQ val3_S2_zero, q4
VARDEFQ val3_S_0, q5
VARDEFQ const3, q7
VARDEFQ val3_in, q1
VARDEFD val3_in_lo, d2
VARDEFD val3_in_hi, d3
VARDEFQ val3_out, q6
VARDEFD val3_out_lo, d12
VARDEFD val3_out_hi, d13
str r0, [sp, #sp_ptr_in]
str r1, [sp, #sp_ptr_B]
str r2, [sp, #sp_ptr_S]
str r3, [sp, #sp_ptr_out]
cmp val_len, #4
mov ptr3_in, r0
mov ptr3_out, r3
ldr val3_rS0, [r2]
vld1.16 {val3_B0_lo, val3_b0_hi}, [r1] /*read all B*/
vld1.32 {val3_S0_lo, val3_S0_hi, val3_S1_lo, val3_S1_hi}, [r2] /*read all S*/
vmov.i32 val3_S2_zero, #0 /*clear q4*/
mov const3_2048, #2048 /*r3 = 1 << 11, will be used for rounding.*/
and tmp_len, val_len, #3 /*r5 = r4 % 4 ==> numbers in second loop*/
blt LR(3, f)
vdup.32 const3, const3_2048 /*d12 = [2048] [2048]*/
sub val_len, val_len, #4
L(2) // Input/Ouput are processed SI4D
ldrsh val3_in0, [ptr3_in], #2 /*in[k]*/
ldrsh val3_in1, [ptr3_in], #2
vext.32 val3_S_0, val3_S_0, val3_S0, #1 /*shift S[2k] in */
vdup.16 val3_in, val3_in0 /*mov r0 to q1(d2, d3)*/
vext.32 val3_S0, val3_S0, val3_S1, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val3_S1, val3_S1, val3_S2_zero, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vmlal.s16 val3_S0, val3_B0_lo, val3_in_lo /*calculate S[0-3]*/
vmlal.s16 val3_S1, val3_b0_hi, val3_in_hi /*calculate S[4-7]*/
vmov val3_out_lo, val3_in0, val3_in1 /*in[2k], in[2k]+1*/
vext.32 val3_S_0, val3_S_0, val3_S0, #1 /*shift S[2k] in */
vdup.16 val3_in, val3_in1 /*mov r0 to q1(d2, d3)*/
vext.32 val3_S0, val3_S0, val3_S1, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val3_S1, val3_S1, val3_S2_zero, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vmlal.s16 val3_S0, val3_B0_lo, val3_in_lo /*calculate S[0-3]*/
vmlal.s16 val3_S1, val3_b0_hi, val3_in_hi /*calculate S[4-7]*/
ldrsh val3_in0, [ptr3_in], #2 /*in[k]*/
ldrsh val3_in1, [ptr3_in], #2
vext.32 val3_S_0, val3_S_0, val3_S0, #1 /*shift S[2k] in */
vdup.16 val3_in, val3_in0 /*mov r0 to q1(d2, d3)*/
vext.32 val3_S0, val3_S0, val3_S1, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val3_S1, val3_S1, val3_S2_zero, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vmlal.s16 val3_S0, val3_B0_lo, val3_in_lo /*calculate S[0-3]*/
vmlal.s16 val3_S1, val3_b0_hi, val3_in_hi /*calculate S[4-7]*/
vmov val3_out_hi, val3_in0, val3_in1 /*in[2k], in[2k]+1*/
vext.32 val3_S_0, val3_S_0, val3_S0, #1 /*shift S[2k] in */
vdup.16 val3_in, val3_in1 /*mov r0 to q1(d2, d3)*/
vext.32 val3_S0, val3_S0, val3_S1, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val3_S1, val3_S1, val3_S2_zero, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vmlal.s16 val3_S0, val3_B0_lo, val3_in_lo /*calculate S[0-3]*/
vmlal.s16 val3_S1, val3_b0_hi, val3_in_hi /*calculate S[4-7]*/
vshl.s32 val3_out, val3_out, #12 /*SKP_LSHIFT(in16, 12)*/
vsub.s32 val3_out, val3_out, val3_S_0 /*SKP_LSHIFT(in16, 12) - S[0]*/
vqadd.s32 val3_out, val3_out, const3 /*qadd out32, out32, LR(0, x)2048*/
vqshrn.s32 d10, val3_out, #12
subs val_len, val_len, #4
vst1.16 d10, [ptr3_out]!
bge LR(2, b)
cmp tmp_len, #0
beq LR(4, f)
vst1.32 val3_S0_lo, [sp]
ldr val3_rS0, [sp] /*r6 = new [S0]*/
L(3) // Input/Ouput are processed 1 by 1
L(0)
ldrsh val3_in0, [ptr3_in], #2 /*in[k]*/
vext.32 val3_S0, val3_S0, val3_S1, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val3_S1, val3_S1, val3_S2_zero, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vdup.16 val3_in, val3_in0 /*mov r0 to q1(d2, d3)*/
rsb val3_out32, val3_rS0, r0, lsl #12 /*out32 = SKP_LSHIFT(in16, 12) - S[0];*/
vmlal.s16 val3_S0, val3_B0_lo, val3_in_lo /*calculate S[0-3]*/
vmlal.s16 val3_S1, val3_b0_hi, val3_in_hi /*calculate S[4-7]*/
vst1.32 val3_S0_lo, [sp]
qadd val3_out32, val3_out32, const3_2048
ssat val3_out32, #16, val3_out32, asr #12 /*out = round and sat*/
subs tmp_len, tmp_len, #1
strh val3_out32, [ptr3_out], #2
ldr val3_rS0, [sp] /*r6 = new [S0]*/
bgt LR(0, b)
L(4)
vst1.32 {val3_S0_lo, val3_S0_hi, val3_S1_lo, val3_S1_hi}, [r2]
add sp, sp, #16
vpop {q8-q11}
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
/*SYM(SKP_Silk_MA_Prediction_ARMv7_order16):*/
L(7)
VARDEF ptr4_in, sb
VARDEF ptr4_out, sl
VARDEF val4_rS0, r6
VARDEF const4_2048, r3
VARDEF val4_in0, r0
VARDEF val4_in1, r1
VARDEF val4_out32, r8
VARDEFD val4_B0_lo, d0
VARDEFD val4_B0_hi, d1
VARDEFD val4_B1_lo, d2
VARDEFD val4_B1_hi, d3
VARDEFQ val4_S1, q2
VARDEFD val4_S1_lo, d4
VARDEFD val4_S1_hi, d5
VARDEFQ val4_S2, q3
VARDEFD val4_S2_lo, d6
VARDEFD val4_S2_hi, d7
VARDEFQ val4_S3, q4
VARDEFD val4_S3_lo, d8
VARDEFD val4_S3_hi, d9
VARDEFQ val4_S4, q5
VARDEFD val4_S4_lo, d10
VARDEFD val4_S4_hi, d11
VARDEFQ val4_S5, q6
VARDEFQ val4_S0, q8
VARDEFD val4_S0_lo, d16
VARDEFQ val4_in, q9
VARDEFD val4_in_lo, d18
VARDEFD val4_in_hi, d19
VARDEFQ val4_out, q10
VARDEFD val4_out_lo, d20
VARDEFD val4_out_hi, d21
VARDEFQ val4_const, q7
str r0, [sp, #sp_ptr_in]
str r1, [sp, #sp_ptr_B]
str r2, [sp, #sp_ptr_S]
str r3, [sp, #sp_ptr_out]
cmp val_len, #4
mov ptr4_in, r0 /*in*/
mov ptr4_out, r3 /*out*/
ldr val4_rS0, [r2] /*r6 = S[0]*/
vld1.16 {val4_B0_lo, val4_B0_hi, val4_B1_lo, val4_B1_hi}, [r1] /*read all 16 Bs*/
vld1.32 {val4_S1_lo, val4_S1_hi, val4_S2_lo, val4_S2_hi}, [r2]! /*read first 16 Ss*/
vld1.32 {val4_S3_lo, val4_S3_hi, val4_S4_lo, val4_S4_hi}, [r2] /*read last 16 Ss*/
vmov.i32 val4_S5, #0 /*clear q6*/
mov const4_2048, #2048 /*r3 = 1 << 11, will be used for rounding.*/
and tmp_len, val_len, #3 /*r5 = r4 % 4 ==> numbers in second loop*/
blt LR(3, f)
vdup.32 val4_const, const4_2048 /*d12 = [2048] [2048]*/
sub val_len, val_len, #4
L(2) // Input/Ouput are processed SI4D
ldrsh val4_in0, [ptr4_in], #2 /*in[k]*/
ldrsh val4_in1, [ptr4_in], #2
vext.32 val4_S0, val4_S0, val4_S1, #1 /*shift S[2k] in */
vdup.16 val4_in, val4_in0 /*mov r0 to q9(d2, d3)*/
vext.32 val4_S1, val4_S1, val4_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val4_S2, val4_S2, val4_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val4_S3, val4_S3, val4_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vext.32 val4_S4, val4_S4, val4_S5, #1 /*shift q5 by 32bit and put 32-lsb of q6 to 32-msb q5*/
vmlal.s16 val4_S1, val4_B0_lo, val4_in_lo /*calculate S[0-3]*/
vmlal.s16 val4_S2, val4_B0_hi, val4_in_lo /*calculate S[4-7]*/
vmlal.s16 val4_S3, val4_B1_lo, val4_in_lo /*calculate S[8-11]*/
vmlal.s16 val4_S4, val4_B1_hi, val4_in_lo /*calculate S[12-15]*/
vmov val4_out_lo, val4_in0, val4_in1 /*in[2k], in[2k]+1 ==> q10*/
vext.32 val4_S0, val4_S0, val4_S1, #1 /*shift S[2k] in */
vdup.16 val4_in, val4_in1 /*mov r0 to q1(d2, d3)*/
vext.32 val4_S1, val4_S1, val4_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val4_S2, val4_S2, val4_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val4_S3, val4_S3, val4_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vext.32 val4_S4, val4_S4, val4_S5, #1 /*shift q5 by 32bit and put 32-lsb of q6 to 32-msb q5*/
vmlal.s16 val4_S1, val4_B0_lo, val4_in_lo /*calculate S[0-3]*/
vmlal.s16 val4_S2, val4_B0_hi, val4_in_lo /*calculate S[4-7]*/
vmlal.s16 val4_S3, val4_B1_lo, val4_in_lo /*calculate S[8-11]*/
vmlal.s16 val4_S4, val4_B1_hi, val4_in_lo /*calculate S[12-15]*/
ldrsh val4_in0, [ptr4_in], #2 /*in[k]*/
ldrsh val4_in1, [ptr4_in], #2
vext.32 val4_S0, val4_S0, val4_S1, #1 /*shift S[2k] in */
vdup.16 val4_in, val4_in0 /*mov r0 to q9(d2, d3)*/
vext.32 val4_S1, val4_S1, val4_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val4_S2, val4_S2, val4_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val4_S3, val4_S3, val4_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vext.32 val4_S4, val4_S4, val4_S5, #1 /*shift q5 by 32bit and put 32-lsb of q6 to 32-msb q5*/
vmlal.s16 val4_S1, val4_B0_lo, val4_in_lo /*calculate S[0-3]*/
vmlal.s16 val4_S2, val4_B0_hi, val4_in_lo /*calculate S[4-7]*/
vmlal.s16 val4_S3, val4_B1_lo, val4_in_lo /*calculate S[8-11]*/
vmlal.s16 val4_S4, val4_B1_hi, val4_in_lo /*calculate S[12-15]*/
vmov val4_out_hi, val4_in0, val4_in1 /*in[2k], in[2k]+1 ==> q10*/
vext.32 val4_S0, val4_S0, val4_S1, #1 /*shift S[2k] in */
vdup.16 val4_in, val4_in1 /*mov r0 to q1(d2, d3)*/
vext.32 val4_S1, val4_S1, val4_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val4_S2, val4_S2, val4_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val4_S3, val4_S3, val4_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vext.32 val4_S4, val4_S4, val4_S5, #1 /*shift q5 by 32bit and put 32-lsb of q6 to 32-msb q5*/
vmlal.s16 val4_S1, val4_B0_lo, val4_in_lo /*calculate S[0-3]*/
vmlal.s16 val4_S2, val4_B0_hi, val4_in_lo /*calculate S[4-7]*/
vmlal.s16 val4_S3, val4_B1_lo, val4_in_lo /*calculate S[8-11]*/
vmlal.s16 val4_S4, val4_B1_hi, val4_in_lo /*calculate S[12-15]*/
vshl.s32 val4_out, val4_out, #12 /*SKP_LSHIFT(in16, 12)*/
vsub.s32 val4_out, val4_out, val4_S0 /*SKP_LSHIFT(in16, 12) - S[0]*/
vqadd.s32 val4_out, val4_out, val4_const /*qadd out32, out32, LR(0, x)2048*/
vqshrn.s32 val4_S0_lo, val4_out, #12
subs val_len, val_len, #4
vst1.16 val4_S0_lo, [ptr4_out]!
bge LR(2, b)
cmp tmp_len, #0
beq LR(4, f)
vst1.32 val4_S1_lo, [sp]
ldr val4_rS0, [sp] /*r6 = new [S0]*/
L(3) // Input/Ouput are processed 1 by 1
L(0)
ldrsh val4_in0, [ptr4_in], #2 /*in[k]*/
vext.32 val4_S1, val4_S1, val4_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val4_S2, val4_S2, val4_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val4_S3, val4_S3, val4_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vext.32 val4_S4, val4_S4, val4_S5, #1 /*shift q5 by 32bit and put 32-lsb of q6 to 32-msb q5*/
vdup.16 val4_S0, val4_in0 /*mov r0 to q1(d2, d3)*/
rsb val4_out32, val4_rS0, val4_in0, lsl #12 /*out32 = SKP_LSHIFT(in16, 12) - S[0];*/
vmlal.s16 val4_S1, val4_B0_lo, val4_S0_lo /*calculate S[0-3]*/
vmlal.s16 val4_S2, val4_B0_hi, val4_S0_lo /*calculate S[4-7]*/
vmlal.s16 val4_S3, val4_B1_lo, val4_S0_lo /*calculate S[8-11]*/
vmlal.s16 val4_S4, val4_B1_hi, val4_S0_lo /*calculate S[12-15]*/
vst1.32 val4_S1_lo, [sp]
qadd val4_out32, val4_out32, const4_2048
ssat val4_out32, #16, val4_out32, asr #12 /*out = round and sat*/
subs tmp_len, tmp_len, #1
strh val4_out32, [ptr4_out], #2
ldr val4_rS0, [sp] /*r6 = new [S0]*/
bgt LR(0, b)
L(4)
sub r2, r2, #32
vst1.32 {val4_S1_lo, val4_S1_hi, val4_S2_lo, val4_S2_hi}, [r2]!
vst1.32 {val4_S3_lo, val4_S3_hi, val4_S4_lo, val4_S4_hi}, [r2]
add sp, sp, #16
vpop {q8-q11}
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
/*SYM(SKP_Silk_MA_Prediction_ARMv7_order12):*/
L(6)
VARDEF ptr5_in, sb
VARDEF ptr5_out, sl
VARDEF val5_rS0, r6
VARDEF val5_in0, r0
VARDEF val5_in1, r1
VARDEF const5_2048, r3
VARDEF val5_out32, r8
VARDEFD val5_B1_lo, d0
VARDEFD val5_B1_hi, d1
VARDEFD val5_B2_lo, d2
VARDEFQ val5_S1, q2
VARDEFD val5_S1_lo, d4
VARDEFD val5_S1_hi, d5
VARDEFQ val5_S2, q3
VARDEFD val5_S2_lo, d6
VARDEFD val5_S2_hi, d7
VARDEFQ val5_S3, q4
VARDEFD val5_S3_lo, d8
VARDEFD val5_S3_hi, d9
VARDEFQ val5_S4, q5
VARDEFQ val5_S0, q8
VARDEFD val5_S0_lo, d16
VARDEFQ val5_const, q7
VARDEFQ val5_in, q9
VARDEFD val5_in_lo, d18
VARDEFQ val5_out, q10
VARDEFD val5_out_lo, d20
VARDEFD val5_out_hi, d21
str r0, [sp, #sp_ptr_in] /*in*/
str r1, [sp, #sp_ptr_B] /*B*/
str r2, [sp, #sp_ptr_S] /*S*/
str r3, [sp, #sp_ptr_out] /*out*/
cmp val_len, #4
mov ptr5_in, r0 /*in*/
mov ptr5_out, r3 /*out*/
ldr val5_rS0, [r2] /*r6 = S[0]*/
vld1.16 {val5_B1_lo, val5_B1_hi, val5_B2_lo}, [r1] /*read all 16 Bs*/
vld1.32 {val5_S1_lo, val5_S1_hi, val5_S2_lo, val5_S2_hi}, [r2]! /*read first 16 Ss*/
vld1.32 {val5_S3_lo, val5_S3_hi}, [r2] /*read last 16 Ss*/
vmov.i32 val5_S4, #0 /*clear q5*/
mov const5_2048, #2048 /*r3 = 1 << 11, will be used for rounding.*/
and tmp_len, val_len, #3 /*r5 = r4 % 4 ==> numbers in second loop*/
blt LR(3, f)
vdup.32 val5_const, const5_2048 /*d12 = [2048] [2048]*/
sub val_len, val_len, #4
L(2) // Input/Ouput are processed SI4D
ldrsh val5_in0, [ptr5_in], #2 /*in[k]*/
ldrsh val5_in1, [ptr5_in], #2
vext.32 val5_S0, val5_S0, val5_S1, #1 /*shift S[2k] in */
vdup.16 val5_in, val5_in0 /*mov r0 to q9(d2, d3)*/
vext.32 val5_S1, val5_S1, val5_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val5_S2, val5_S2, val5_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val5_S3, val5_S3, val5_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vmlal.s16 val5_S1, val5_B1_lo, val5_in_lo /*calculate S[0-3]*/
vmlal.s16 val5_S2, val5_B1_hi, val5_in_lo /*calculate S[4-7]*/
vmlal.s16 val5_S3, val5_B2_lo, val5_in_lo /*calculate S[8-11]*/
vmov val5_out_lo, val5_in0, val5_in1 /*in[2k], in[2k]+1 ==> q10*/
vext.32 val5_S0, val5_S0, val5_S1, #1 /*shift S[2k] in */
vdup.16 val5_in, val5_in1 /*mov r0 to q1(d2, d3)*/
vext.32 val5_S1, val5_S1, val5_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val5_S2, val5_S2, val5_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val5_S3, val5_S3, val5_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vmlal.s16 val5_S1, val5_B1_lo, val5_in_lo /*calculate S[0-3]*/
vmlal.s16 val5_S2, val5_B1_hi, val5_in_lo /*calculate S[4-7]*/
vmlal.s16 val5_S3, val5_B2_lo, val5_in_lo /*calculate S[8-11]*/
ldrsh val5_in0, [ptr5_in], #2 /*in[k]*/
ldrsh val5_in1, [ptr5_in], #2
vext.32 val5_S0, val5_S0, val5_S1, #1 /*shift S[2k] in */
vdup.16 val5_in, val5_in0 /*mov r0 to q9(d2, d3)*/
vext.32 val5_S1, val5_S1, val5_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val5_S2, val5_S2, val5_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val5_S3, val5_S3, val5_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vmlal.s16 val5_S1, val5_B1_lo, val5_in_lo /*calculate S[0-3]*/
vmlal.s16 val5_S2, val5_B1_hi, val5_in_lo /*calculate S[4-7]*/
vmlal.s16 val5_S3, val5_B2_lo, val5_in_lo /*calculate S[8-11]*/
vmov val5_out_hi, val5_in0, val5_in1 /*in[2k], in[2k]+1 ==> q10*/
vext.32 val5_S0, val5_S0, val5_S1, #1 /*shift S[2k] in */
vdup.16 val5_in, val5_in1 /*mov r0 to q1(d2, d3)*/
vext.32 val5_S1, val5_S1, val5_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val5_S2, val5_S2, val5_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val5_S3, val5_S3, val5_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vmlal.s16 val5_S1, val5_B1_lo, val5_in_lo /*calculate S[0-3]*/
vmlal.s16 val5_S2, val5_B1_hi, val5_in_lo /*calculate S[4-7]*/
vmlal.s16 val5_S3, val5_B2_lo, val5_in_lo /*calculate S[8-11]*/
vshl.s32 val5_out, val5_out, #12 /*SKP_LSHIFT(in16, 12)*/
vsub.s32 val5_out, val5_out, val5_S0 /*SKP_LSHIFT(in16, 12) - S[0]*/
vqadd.s32 val5_out, val5_out, val5_const /*qadd out32, out32, LR(0, x)2048*/
vqshrn.s32 val5_S0_lo, val5_out, #12
subs val_len, val_len, #4
vst1.16 val5_S0_lo, [ptr5_out]!
bge LR(2, b)
cmp tmp_len, #0
beq LR(4, f)
vst1.32 val5_S1_lo, [sp]
ldr val5_rS0, [sp] /*r6 = new [S0]*/
L(3) // Input/Ouput are processed 1 by 1
L(0)
ldrsh val5_in0, [ptr5_in], #2 /*in[k]*/
vext.32 val5_S1, val5_S1, val5_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val5_S2, val5_S2, val5_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val5_S3, val5_S3, val5_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vdup.16 val5_S0, val5_in0 /*mov r0 to q8(d16, d17)*/
rsb val5_out32, val5_rS0, val5_in0, lsl #12 /*out32 = SKP_LSHIFT(in16, 12) - S[0];*/
vmlal.s16 val5_S1, val5_B1_lo, val5_S0_lo /*calculate S[0-3]*/
vmlal.s16 val5_S2, val5_B1_hi, val5_S0_lo /*calculate S[4-7]*/
vmlal.s16 val5_S3, val5_B2_lo, val5_S0_lo /*calculate S[8-11]*/
vst1.32 val5_S1_lo, [sp]
qadd val5_out32, val5_out32, const5_2048
ssat val5_out32, #16, val5_out32, asr #12 /*out = round and sat*/
subs tmp_len, tmp_len, #1
strh val5_out32, [ptr5_out], #2
ldr val5_rS0, [sp] /*r6 = new [S0]*/
bgt LR(0, b)
L(4)
sub r2, r2, #32
vst1.32 {val5_S1_lo, val5_S1_hi, val5_S2_lo, val5_S2_hi}, [r2]!
vst1.32 {val5_S3_lo, val5_S3_hi}, [r2]
add sp, sp, #16
vpop {q8-q11}
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
.set sp13_ptr_in, 0
.set sp13_ptr_B, 4
.set sp13_ptr_S, 8
.set sp13_ptr_out, 12
.globl SYM(SKP_Silk_MA_Prediction_Q13)
SYM(SKP_Silk_MA_Prediction_Q13):
stmdb sp!, {r4-r10, fp, ip, lr}
vpush {q0-q7}
vpush {q8-q11}
add fp, sp, #228
sub sp, sp, #16
.set arg13_len, 248
.set arg13_order, 252
/*LOAD INPUT ARGS*/
VARDEF val6_order, r5
VARDEF val6_len, r4
VARDEF ptr6_in, sb
VARDEF ptr6_out, sl
VARDEF ptr6_S, ip
VARDEF ptr6_B, lr
VARDEF val6_in, r0
VARDEF val6_S0, r1
VARDEF val6_out, r1
VARDEF val6_S1, r2
VARDEF val6_S2, r3
VARDEF val6_B, r6
VARDEF val6_SO1, _r7
VARDEF val6_SO2, r8
ldr val6_order, [sp, #arg13_order] /*order*/
ldr val6_len, [sp, #arg13_len] /*len*/
ands _r7, r1, #3 /*CHECK: if ( B is 4 byte aligned ) Prerequest for ARMv6 SIMD*/
bne LR(2, f)
ands r6, val6_order, #1 /*CHECK: if ( order % 2 == 0 ) Prerequest for ARMv6 SIMD*/
bne LR(2, f)
cmp val6_order, #12 /*CHECK: if ( order == 12 ) ARMv7 SIMD*/
beq LR(8, f)/*SYM(SKP_Silk_MA_Prediction_Q13_ARMv7_order12)*/
cmp val6_order, #6 /*CHECK: if ( order >= 6 ) Prerequest for ARMv6 SIMD*/
blt LR(2, f)
// ARMv6 SIMD
// order % 2 == 0
str r0, [sp, #sp13_ptr_in]
str r1, [sp, #sp13_ptr_B]
str r2, [sp, #sp13_ptr_S]
str r3, [sp, #sp13_ptr_out]
mov ptr6_in, r0 /*in*/
mov ptr6_out, r3 /*out*/
L(0)
ldr ptr6_S, [sp, #sp13_ptr_S] /*S*/
ldr ptr6_B, [sp, #sp13_ptr_B] /*B*/
ldrsh val6_in, [ptr6_in], #2 /*in[k]*/
ldr val6_S0, [ptr6_S], #4 /*S[0]*/
ldr val6_order, [sp, #arg13_order] /*order*/
ldr val6_S1, [ptr6_S], #4 /*S[1]*/
rsb r3, val6_S0, val6_in, lsl #13 /*SKP_LSHIFT(in16, 12) - S[0]*/
ldr val6_B, [ptr6_B], #4 /*B[0], B[1]*/
mov r3, r3, asr #12
sub val6_order, val6_order, #4 /*order - 2 - 2*/
add val6_out, r3, #1 /*SKP_RSHIFT_ROUND*/
ldr val6_S2, [ptr6_S], #4 /*S[2]*/
ssat val6_out, #16, val6_out, asr #1 /*SKP_SAT16( out32 )*/
strh val6_out, [ptr6_out], #2 /*save it to out[k]*/
L(1)
smlabb val6_SO1, val6_in, val6_B, val6_S1 /*SKP_SMLABB(S[d + 1], in16, B32)*/
smlabt val6_SO2, val6_in, val6_B, val6_S2 /*SKP_SMLABT(S[d + 2], in16, B32)*/
ldr val6_S1, [ptr6_S], #4 /*S[d+1]*/
ldr val6_S2, [ptr6_S], #-16 /*S[d+2]*/
ldr val6_B, [ptr6_B], #4 /*B[d], B[d+1]*/
subs val6_order, val6_order, #2
str val6_SO1, [ptr6_S], #4
str val6_SO2, [ptr6_S], #16
bgt LR(1, b)
smlabb val6_SO1, val6_in, val6_B, val6_S1 /*SKP_SMLABB(S[d + 1], in16, B32)*/
smlabt val6_SO2, val6_in, val6_B, val6_S2 /*SKP_SMLABT(S[d + 2], in16, B32)*/
ldr val6_S1, [ptr6_S], #-12 /*S[d+1]*/
ldr val6_B, [ptr6_B] /*B[d], B[d+1]*/
str val6_SO1, [ptr6_S], #4
str val6_SO2, [ptr6_S], #4
smlabb val6_SO1, val6_in, val6_B, val6_S1 /*SKP_SMLABB(S[d + 1], in16, B32)*/
smulbt val6_SO2, val6_in, val6_B /*SKP_SMLABT(S[d + 2], in16, B32)*/
subs val6_len, val6_len, #1
str val6_SO1, [ptr6_S], #4
str val6_SO2, [ptr6_S]
bgt LR(0, b)
add sp, sp, #16
vpop {q8-q11}
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
VARDEF ptr7_in, r6
VARDEF ptr7_out, sb
VARDEF val7_B0, r2
VARDEF ptr7_B, _r7
VARDEF ptr7_S, r8
VARDEF val7_S0, lr
VARDEF val7_in, r0
VARDEF val7_out, r1
VARDEF val7_B, r1
VARDEF val7_S1, r3
VARDEF val7_Sout, r2
// order % 2 != 0
L(2)
add r2, r2, #4
str r0, [sp, #sp13_ptr_in]
str r1, [sp, #sp13_ptr_B]
str r2, [sp, #sp13_ptr_S]
str r3, [sp, #sp13_ptr_out]
mov ptr7_in, r0 /*in_ptr*/
mov ptr7_out, r3 /*out_ptr*/
ldr val7_S0, [r2, #-4] /*S0*/
L(0)
ldrsh val7_in, [ptr7_in], #2 /*in[k]*/
ldr val6_order, [sp, #arg13_order] /*order*/
ldr ptr7_B, [sp, #sp13_ptr_B]
ldr ptr7_S, [sp, #sp13_ptr_S] /*S_ptr*/
rsb val7_out, val7_S0, val7_in, lsl #13
ldrsh val7_B0, [ptr7_B], #2
mov val7_out, val7_out, asr #12
ldr val7_S1, [ptr7_S]
add val7_out, val7_out, #1
smlabb val7_S0, val7_in, val7_B0, val7_S1
ssat val7_out, #16, val7_out, asr #1
sub val6_order, val6_order, #3
ldr val7_S1, [ptr7_S, #4]
strh val7_out, [ptr7_out], #2
ldrsh val7_B, [ptr7_B], #2
L(1)
smlabb val7_Sout, val7_in, val7_B, val7_S1
ldr val7_S1, [ptr7_S, #8]
ldrsh val7_B, [ptr7_B], #2
str val7_Sout, [ptr7_S], #4
subs val6_order, val6_order, #1
bgt LR(1, b)
smlabb val7_Sout, val7_in, val7_B, val7_S1
ldrsh val7_B, [ptr7_B], #2
str val7_Sout, [ptr7_S], #4
smulbb val7_Sout, val7_in, val7_B
subs val6_len, val6_len, #1
str val7_Sout, [ptr7_S]
bgt LR(0, b)
ldr r2, [sp, #sp13_ptr_S]
str val7_S0, [r2, #-4]
add sp, sp, #16
vpop {q8-q11}
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
/*SYM(SKP_Silk_MA_Prediction_Q13_ARMv7_order12):*/
L(8)
VARDEF ptr8_in, sb
VARDEF ptr8_out, sl
VARDEF val8_rS0, r6
VARDEF const8_4096, r3
VARDEF val8_in0, r0
VARDEF val8_in1, r1
VARDEF val8_len, r5
VARDEF val8_out32, r8
VARDEFD val8_B0_lo, d0
VARDEFD val8_B0_hi, d1
VARDEFD val8_B1_lo, d2
VARDEFQ val8_S1, q2
VARDEFD val8_S1_lo, d4
VARDEFD val8_S1_hi, d5
VARDEFQ val8_S2, q3
VARDEFD val8_S2_lo, d6
VARDEFD val8_S2_hi, d7
VARDEFQ val8_S3, q4
VARDEFD val8_S3_lo, d8
VARDEFD val8_S3_hi, d9
VARDEFQ val8_S4, q5
VARDEFQ const8, q7
VARDEFQ val8_S0, q8
VARDEFD val8_S0_lo, d16
VARDEFQ val8_in, q9
VARDEFD val8_in_lo, d18
VARDEFQ val8_out, q10
VARDEFD val8_out_lo, d20
VARDEFD val8_out_hi, d21
str r0, [sp, #sp13_ptr_in] /*in*/
str r1, [sp, #sp13_ptr_B] /*B*/
str r2, [sp, #sp13_ptr_S] /*S*/
str r3, [sp, #sp13_ptr_out] /*out*/
cmp val6_len, #4
mov ptr8_in, r0 /*in*/
mov ptr8_out, r3 /*out*/
ldr val8_rS0, [r2] /*r6 = S[0]*/
vld1.16 {val8_B0_lo, val8_B0_hi, val8_B1_lo}, [r1] /*read all 16 Bs*/
vld1.32 {val8_S1_lo, val8_S1_hi, val8_S2_lo, val8_S2_hi}, [r2]! /*read first 16 Ss*/
vld1.32 {val8_S3_lo, val8_S3_hi}, [r2] /*read last 16 Ss*/
vmov.i32 val8_S4, #0 /*clear q5*/
mov const8_4096, #4096 /*r3 = 1 << 12, will be used for rounding.*/
and val8_len, val6_len, #3 /*r5 = r4 % 4 ==> numbers in second loop*/
blt LR(3, f)
vdup.32 const8, const8_4096 /*d12 = [2048] [2048]*/
sub val6_len, val6_len, #4
L(2) // Input/Ouput are processed SI4D
ldrsh val8_in0, [ptr8_in], #2 /*in[k]*/
ldrsh val8_in1, [ptr8_in], #2
vext.32 val8_S0, val8_S0, val8_S1, #1 /*shift S[2k] in */
vdup.16 val8_in, val8_in0 /*mov r0 to q9(d2, d3)*/
vext.32 val8_S1, val8_S1, val8_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val8_S2, val8_S2, val8_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val8_S3, val8_S3, val8_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vmlal.s16 val8_S1, val8_B0_lo, val8_in_lo /*calculate S[0-3]*/
vmlal.s16 val8_S2, val8_B0_hi, val8_in_lo /*calculate S[4-7]*/
vmlal.s16 val8_S3, val8_B1_lo, val8_in_lo /*calculate S[8-11]*/
vmov val8_out_lo, val8_in0, val8_in1 /*in[2k], in[2k]+1 ==> q10*/
vext.32 val8_S0, val8_S0, val8_S1, #1 /*shift S[2k] in */
vdup.16 val8_in, val8_in1 /*mov r0 to q1(d2, d3)*/
vext.32 val8_S1, val8_S1, val8_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val8_S2, val8_S2, val8_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val8_S3, val8_S3, val8_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vmlal.s16 val8_S1, val8_B0_lo, val8_in_lo /*calculate S[0-3]*/
vmlal.s16 val8_S2, val8_B0_hi, val8_in_lo /*calculate S[4-7]*/
vmlal.s16 val8_S3, val8_B1_lo, val8_in_lo /*calculate S[8-11]*/
ldrsh val8_in0, [ptr8_in], #2 /*in[k]*/
ldrsh val8_in1, [ptr8_in], #2
vext.32 val8_S0, val8_S0, val8_S1, #1 /*shift S[2k] in */
vdup.16 val8_in, val8_in0 /*mov r0 to q9(d2, d3)*/
vext.32 val8_S1, val8_S1, val8_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val8_S2, val8_S2, val8_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val8_S3, val8_S3, val8_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vmlal.s16 val8_S1, val8_B0_lo, val8_in_lo /*calculate S[0-3]*/
vmlal.s16 val8_S2, val8_B0_hi, val8_in_lo /*calculate S[4-7]*/
vmlal.s16 val8_S3, val8_B1_lo, val8_in_lo /*calculate S[8-11]*/
vmov val8_out_hi, val8_in0, val8_in1 /*in[2k], in[2k]+1 ==> q10*/
vext.32 val8_S0, val8_S0, val8_S1, #1 /*shift S[2k] in */
vdup.16 val8_in, val8_in1 /*mov r0 to q1(d2, d3)*/
vext.32 val8_S1, val8_S1, val8_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val8_S2, val8_S2, val8_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val8_S3, val8_S3, val8_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vmlal.s16 val8_S1, val8_B0_lo, val8_in_lo /*calculate S[0-3]*/
vmlal.s16 val8_S2, val8_B0_hi, val8_in_lo /*calculate S[4-7]*/
vmlal.s16 val8_S3, val8_B1_lo, val8_in_lo /*calculate S[8-11]*/
vshl.s32 val8_out, val8_out, #13 /*SKP_LSHIFT(in16, 12)*/
vsub.s32 val8_out, val8_out, val8_S0 /*SKP_LSHIFT(in16, 12) - S[0]*/
vqadd.s32 val8_out, val8_out, const8 /*qadd out32, out32, LR(0, x)2048*/
vqshrn.s32 val8_S0_lo, val8_out, #13
subs val6_len, val6_len, #4
vst1.16 val8_S0_lo, [ptr8_out]!
bge LR(2, b)
cmp val8_len, #0
beq LR(4, f)
vst1.32 val8_S1_lo, [sp]
ldr val8_rS0, [sp] /*r6 = new [S0]*/
L(3) // Input/Ouput are processed 1 by 1
L(0)
ldrsh val8_in0, [ptr8_in], #2 /*in[k]*/
vext.32 val8_S1, val8_S1, val8_S2, #1 /*shift q2 by 32bit and put 32-lsb of q3 to 32-msb q2*/
vext.32 val8_S2, val8_S2, val8_S3, #1 /*shift q3 by 32bit and put 32-lsb of q4 to 32-msb q3*/
vext.32 val8_S3, val8_S3, val8_S4, #1 /*shift q4 by 32bit and put 32-lsb of q5 to 32-msb q4*/
vdup.16 val8_S0, val8_in0 /*mov r0 to q8(d16, d17)*/
rsb val8_out32, val8_rS0, val8_in0, lsl #13 /*out32 = SKP_LSHIFT(in16, 12) - S[0];*/
vmlal.s16 val8_S1, val8_B0_lo, val8_S0_lo /*calculate S[0-3]*/
vmlal.s16 val8_S2, val8_B0_hi, val8_S0_lo /*calculate S[4-7]*/
vmlal.s16 val8_S3, val8_B1_lo, val8_S0_lo /*calculate S[8-11]*/
vst1.32 val8_S1_lo, [sp]
qadd val8_out32, val8_out32, const8_4096
ssat val8_out32, #16, val8_out32, asr #13 /*out = round and sat*/
subs val8_len, val8_len, #1
strh val8_out32, [ptr8_out], #2
ldr val8_rS0, [sp] /*r6 = new [S0]*/
bgt LR(0, b)
L(4)
sub r2, r2, #32
vst1.32 {val8_S1_lo, val8_S1_hi, val8_S2_lo, val8_S2_hi}, [r2]!
vst1.32 {val8_S3_lo, val8_S3_hi}, [r2]
add sp, sp, #16
vpop {q8-q11}
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
#elif EMBEDDED_ARM>=5
/*
* void SKP_Silk_MA_Prediction(
* const SKP_int16 *in, I: input signal
* const SKP_int16 *B, I: MA coefficients, Q13 [order+1]
* SKP_int32 *S, I/O: state vector [order]
* SKP_int16 *out, O: output signal
* const SKP_int32 len, I: signal length
* const SKP_int32 order I: filter order
* )
*
*
*/
VARDEF ma_in, sb
VARDEF ma_out, sl
VARDEF ma_s, ip
VARDEF ma_b, lr
VARDEF ma_len, r4
VARDEF ma_in_val, r0
VARDEF ma_s0_val, r1
VARDEF ma_s1_val, r2
VARDEF ma_order, r5
VARDEF ma_b_val, r6
VARDEF ma_tmp0, r3
VARDEF ma_out_val, r1
VARDEF ma_const0, r3
VARDEF ma_s2_val, r3
#ifdef IPHONE
VARDEF ma_new_s1, r8
VARDEF ma_new_s2, _r7
#else
VARDEF ma_new_s1, _r7
VARDEF ma_new_s2, r8
#endif
.set SAVE_IN, 0
.set SAVE_B, 4
.set SAVE_S, 8
.set SAVE_OUT, 12
.globl SYM(SKP_Silk_MA_Prediction)
SYM(SKP_Silk_MA_Prediction):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #16
.set arg_len, 56
.set arg_order, 60
/*LOAD INPUT ARGS*/
ldr ma_order, [sp, #arg_order]
ldr ma_len, [sp, #arg_len]
ands _r7, r1, #3
bne LR(9, f)/*MA_Prediction_ORDER_2BYTE*/
ands r6, ma_order, #1
bne LR(9, f)/*MA_Prediction_ORDER_2BYTE*/
cmp ma_order, #6
blt LR(9, f)/*MA_Prediction_ORDER_2BYTE*/
// order % 2 == 0
str r0, [sp, #SAVE_IN]
str r1, [sp, #SAVE_B]
str r2, [sp, #SAVE_S]
str r3, [sp, #SAVE_OUT]
mov ma_in, r0
mov ma_out, r3
L(0)
ldr ma_s, [sp, #SAVE_S]
ldr ma_b, [sp, #SAVE_B]
ldrsh ma_in_val, [ma_in], #2
ldr ma_s0_val, [ma_s], #4
ldr ma_order, [sp, #arg_order]
ldr ma_s1_val, [ma_s], #4
rsb ma_tmp0, ma_s0_val, ma_in_val, lsl #12
ldr ma_b_val, [ma_b], #4
qadd ma_out_val, ma_tmp0, ma_tmp0
sub ma_order, ma_order, #4
mov ma_const0, #32768
qadd ma_out_val, ma_out_val, ma_out_val
qadd ma_out_val, ma_out_val, ma_out_val
qadd ma_out_val, ma_out_val, ma_out_val
qadd ma_out_val, ma_out_val, ma_const0
ldr ma_s2_val, [ma_s], #4
mov ma_out_val, ma_out_val, asr #16
strh ma_out_val, [ma_out], #2
sub r1, ma_s, #12
L(1)
smlabb ma_new_s1, ma_in_val, ma_b_val, ma_s1_val
smlabt ma_new_s2, ma_in_val, ma_b_val, ma_s2_val
ldmia ma_s!, {ma_s1_val, ma_s2_val}
ldr ma_b_val, [ma_b], #4
subs ma_order, ma_order, #2
stmia r1!, {ma_new_s1, ma_new_s2}
bgt LR(1, b)
smlabb ma_new_s1, ma_in_val, ma_b_val, ma_s1_val
smlabt ma_new_s2, ma_in_val, ma_b_val, ma_s2_val
ldr ma_s1_val, [ma_s], #-12
ldr ma_b_val, [ma_b]
str ma_new_s1, [ma_s], #4
str ma_new_s2, [ma_s], #4
smlabb ma_new_s1, ma_in_val, ma_b_val, ma_s1_val
smulbt ma_new_s2, ma_in_val, ma_b_val
subs ma_len, ma_len, #1
str ma_new_s1, [ma_s], #4
str ma_new_s2, [ma_s]
bgt LR(0, b)
add sp, sp, #16
ldmia sp!, {r4-r10, fp, ip, pc}
VARDEF ma1_in, r6
VARDEF ma1_out, sb
VARDEF ma1_s0_val, lr
VARDEF ma1_b, _r7
VARDEF ma1_s, r8
VARDEF ma1_b_val, r2
VARDEF ma1_s1_val, r3
VARDEF ma1_b0_val, r1
VARDEF ma1_s2_val, r2
// order % 2 != 0
/*MA_Prediction_ORDER_2BYTE: */
L(9)
add r2, r2, #4
str r0, [sp, #SAVE_IN]
str r1, [sp, #SAVE_B]
str r2, [sp, #SAVE_S]
str r3, [sp, #SAVE_OUT]
mov ma1_in, r0
mov ma1_out, r3
ldr ma1_s0_val, [r2, #-4]
L(0)
ldrsh ma_in_val, [ma1_in], #2
ldr ma_order, [sp, #arg_order]
ldr ma1_b, [sp, #SAVE_B]
ldr ma1_s, [sp, #SAVE_S]
rsb ma_out_val, ma1_s0_val, ma_in_val, lsl #12
ldrsh ma1_b_val, [ma1_b], #2
qadd ma_out_val, ma_out_val, ma_out_val
ldr ma1_s1_val, [ma1_s]
qadd ma_out_val, ma_out_val, ma_out_val
smlabb ma1_s0_val, ma_in_val, ma1_b_val, ma1_s1_val
mov ma1_s1_val, #32768
qadd ma_out_val, ma_out_val, ma_out_val
qadd ma_out_val, ma_out_val, ma_out_val
qadd ma_out_val, ma_out_val, ma1_s1_val
mov ma_out_val, ma_out_val, asr #16
sub ma_order, ma_order, #3
ldr ma1_s1_val, [ma1_s, #4]
strh ma_out_val, [ma1_out], #2
ldrsh ma1_b0_val, [ma1_b], #2
L(1)
smlabb ma1_s2_val, ma_in_val, ma1_b0_val, ma1_s1_val
ldr ma1_s1_val, [ma1_s, #8]
ldrsh ma1_b0_val, [ma1_b], #2
str ma1_s2_val, [ma1_s], #4
subs ma_order, ma_order, #1
bgt LR(1, b)
smlabb ma1_s2_val, ma_in_val, ma1_b0_val, ma1_s1_val
ldrsh ma1_b0_val, [ma1_b], #2
str ma1_s2_val, [ma1_s], #4
smulbb ma1_s2_val, ma_in_val, ma1_b0_val
subs ma_len, ma_len, #1
str ma1_s2_val, [ma1_s]
bgt LR(0, b)
ldr r2, [sp, #SAVE_S]
str ma1_s0_val, [r2, #-4]
add sp, sp, #16
ldmia sp!, {r4-r10, fp, ip, pc}
/*
* void SKP_Silk_MA_Prediction_Q13(
* const SKP_int16 *in, I: input signal
* const SKP_int16 *B, I: MA coefficients, Q13 [order+1]
* SKP_int32 *S, I/O: state vector [order]
* SKP_int16 *out, O: output signal
* const SKP_int32 len, I: signal length
* const SKP_int32 order I: filter order
* )
*
*
*/
VARDEF maq13_s, ip
VARDEF maq13_b, lr
VARDEF maq13_in, sb
VARDEF maq13_out, sl
VARDEF maq13_in_val, r0
VARDEF maq13_out_val, r1
VARDEF maq13_order, r5
VARDEF maq13_len, r4
VARDEF maq13_s1, r1
VARDEF maq13_s2, r2
VARDEF maq13_s3, r3
VARDEF maq13_b1, r6
VARDEF maq13_s1_new, _r7
VARDEF maq13_s2_new, r8
.set SAVE_IN, 0
.set SAVE_B, 4
.set SAVE_S, 8
.set SAVE_OUT, 12
.globl SYM(SKP_Silk_MA_Prediction_Q13)
SYM(SKP_Silk_MA_Prediction_Q13):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #16
.set arg_len, 56
.set arg_order, 60
/*LOAD INPUT ARGS*/
ldr maq13_order, [sp, #arg_order]
ldr maq13_len, [sp, #arg_len]
ands _r7, r1, #3
bne LR(2, f)/*MA_Prediction_Q13_ORDER_2BYTE*/
ands r6, r5, #1
bne LR(2, f)/*MA_Prediction_Q13_ORDER_2BYTE*/
cmp r5, #6
blt LR(2, f)/*MA_Prediction_Q13_ORDER_2BYTE*/
// order % 2 == 0
str r0, [sp, #SAVE_IN]
str r1, [sp, #SAVE_B]
str r2, [sp, #SAVE_S]
str r3, [sp, #SAVE_OUT]
mov maq13_in, r0
mov maq13_out, r3
L(0)
ldr maq13_s, [sp, #SAVE_S]
ldr maq13_b, [sp, #SAVE_B]
ldrsh maq13_in_val, [maq13_in], #2
ldr maq13_s1, [maq13_s], #4
ldr maq13_order, [sp, #arg_order]
ldr maq13_s2, [maq13_s], #4
rsb maq13_s3, maq13_s1, maq13_in_val, lsl #13
ldr maq13_b1, [maq13_b], #4
qadd maq13_out_val, maq13_s3, maq13_s3
sub maq13_order, maq13_order, #4
mov r3, #32768
qadd maq13_out_val, maq13_out_val, maq13_out_val
qadd maq13_out_val, maq13_out_val, maq13_out_val
qadd maq13_out_val, maq13_out_val, r3
ldr maq13_s3, [maq13_s], #4
mov maq13_out_val, maq13_out_val, asr #16
strh maq13_out_val, [maq13_out], #2
L(1)
smlabb maq13_s1_new, maq13_in_val, maq13_b1, maq13_s2
smlabt maq13_s2_new, maq13_in_val, maq13_b1, maq13_s3
ldr maq13_s2, [maq13_s], #4
ldr maq13_s3, [maq13_s], #-16
ldr maq13_b1, [maq13_b], #4
subs maq13_order, maq13_order, #2
str maq13_s1_new, [maq13_s], #4
str maq13_s2_new, [maq13_s], #16
bgt LR(1, b)
smlabb maq13_s1_new, maq13_in_val, maq13_b1, maq13_s2
smlabt maq13_s2_new, maq13_in_val, maq13_b1, maq13_s3
ldr maq13_s2, [maq13_s], #-12
ldr maq13_b1, [maq13_b]
str maq13_s1_new, [maq13_s], #4
str maq13_s2_new, [maq13_s], #4
smlabb maq13_s1_new, maq13_in_val, maq13_b1, maq13_s2
smulbt maq13_s2_new, maq13_in_val, maq13_b1
subs maq13_len, maq13_len, #1
str maq13_s1_new, [maq13_s], #4
str maq13_s2_new, [maq13_s]
bgt LR(0, b)
add sp, sp, #16
ldmia sp!, {r4-r10, fp, ip, pc}
VARDEF ma1q13_s, r8
VARDEF ma1q13_b, _r7
VARDEF ma1q13_in, r6
VARDEF ma1q13_out, sb
VARDEF ma1q13_s1, r3
VARDEF ma1q13_s0, r2
VARDEF ma1q13_b1, r1
VARDEF ma1q13_b_tmp, r2
// order % 2 != 0
/*MA_Prediction_Q13_ORDER_2BYTE: */
L(2)
add r2, r2, #4
str r0, [sp, #SAVE_IN]
str r1, [sp, #SAVE_B]
str r2, [sp, #SAVE_S]
str r3, [sp, #SAVE_OUT]
mov ma1q13_in, r0
mov ma1q13_out, r3
ldr lr, [r2, #-4]
L(0)
ldrsh maq13_in_val, [ma1q13_in], #2
ldr maq13_order, [sp, #arg_order]
ldr ma1q13_b, [sp, #SAVE_B]
ldr ma1q13_s, [sp, #SAVE_S]
rsb maq13_out_val, lr, maq13_in_val, lsl #13
ldrsh ma1q13_b_tmp, [ma1q13_b], #2
qadd maq13_out_val, maq13_out_val, maq13_out_val
ldr ma1q13_s1, [ma1q13_s]
qadd maq13_out_val, maq13_out_val, maq13_out_val
smlabb lr, maq13_in_val, ma1q13_b_tmp, ma1q13_s1
mov r3, #32768
qadd maq13_out_val, maq13_out_val, maq13_out_val
qadd maq13_out_val, maq13_out_val, r3
mov maq13_out_val, maq13_out_val, asr #16
sub maq13_order, maq13_order, #3
ldr ma1q13_s1, [ma1q13_s, #4]
strh maq13_out_val, [sb], #2
ldrsh ma1q13_b1, [ma1q13_b], #2
L(1)
smlabb ma1q13_s0, maq13_in_val, ma1q13_b1, ma1q13_s1
ldr ma1q13_s1, [ma1q13_s, #8]
ldrsh ma1q13_b1, [ma1q13_b], #2
str ma1q13_s0, [ma1q13_s], #4
subs maq13_order, maq13_order, #1
bgt LR(1, b)
smlabb ma1q13_s0, maq13_in_val, ma1q13_b1, ma1q13_s1
ldrsh ma1q13_b1, [ma1q13_b], #2
str ma1q13_s0, [ma1q13_s], #4
smulbb ma1q13_s0, maq13_in_val, ma1q13_b1
subs maq13_len, maq13_len, #1
str ma1q13_s0, [ma1q13_s]
bgt LR(0, b)
ldr r2, [sp, #SAVE_S]
str lr, [r2, #-4]
add sp, sp, #16
ldmia sp!, {r4-r10, fp, ip, pc}
#endif
#if EMBEDDED_ARM>=5
#define SKP_Silk_MAX_ORDER_LPC 16
.set sp_B, 0
.set sp_pin, 32
.set sp_pB, 36
.set sp_pS, 40
.set sp_pout, 44
.globl SYM(SKP_Silk_LPC_analysis_filter)
SYM(SKP_Silk_LPC_analysis_filter):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #48
.set arg_len, 88
.set arg_Order, 92
VARDEF len, r4
VARDEF order, r5
VARDEF S_val, r6
VARDEF B_val, _r7
VARDEF S_tmp1, r8
VARDEF S_tmp2, sb
VARDEF out32, sl
// Registers not used in main inner loop
VARDEF in, r6
VARDEF in_Q12, _r7
VARDEF B_tmp, r6
VARDEF pB_tmp, _r7
str r0, [sp, #sp_pin]
str r1, [sp, #sp_pB]
str r2, [sp, #sp_pS]
str r3, [sp, #sp_pout]
ldr len, [sp, #arg_len]
ldr order, [sp, #arg_Order]
/*B_ALIGNMENT:*/
tst r1, #0x3
beq LR(3, f)/*S_ALIGNMENT*/
ldrh B_tmp, [r1], #2
add pB_tmp, sp, #sp_B
sub order, order, #1
L(0)
subs order, order, #1
strh B_tmp, [pB_tmp]
ldrh B_tmp, [r1], #2
bgt LR(0, b)
ldr order, [sp, #arg_Order]
strh B_tmp, [pB_tmp]
add r1, sp, #sp_B //R1 aligned pointer to B.
/*S_ALIGNMENT:*/
L(3)
tst r2, #0x3
bne LR(4, f)/*MAIN_FORLOOP1*/
/*MAIN_FORLOOP0: */
L(0)
mov out32, #0
ldr order, [sp, #arg_Order]
/*MAIN_INNER_FORLOOP0:*/
ldr S_val, [r2], #2
ldr B_val, [r1], #4
sub order, order, #4
mov S_tmp2, S_val, lsr #16
strh S_val, [r2], #2
SKP_SMLAD out32, B_val, S_val, out32
ldr S_val, [r2]
L(1)
ldr B_val, [r1], #4
add S_tmp2, S_tmp2, S_val, lsl #16
ldr S_tmp1, [r2, #4]
subs order, order, #2
str S_tmp2, [r2], #4
SKP_SMLAD out32, B_val, S_val, out32
mov S_tmp2, S_val, lsr #16
mov S_val, S_tmp1
bgt LR(1, b)
ldr B_val, [r1]
add S_tmp2, S_tmp2, S_val, lsl #16
SKP_SMLAD out32, B_val, S_val, out32
str S_tmp2, [r2]
ldrsh in, [r0], #2
ldr r2, [sp, #sp_pS]
ldr r1, [sp, #sp_pB]
mov in_Q12, in, lsl #12
qsub out32, in_Q12, out32
mov out32, out32, asr #11
strh in, [r2]
add out32, out32, #1
#if EMBEDDED_ARM >=6
ssat out32, #16, out32, asr #1
#else
mov out32, out32, asr #1
cmp out32, #0x8000
mvnge out32, #0x8000
subge out32, out32, #1
cmn out32, #0x8000
movlt out32, #0x8000
#endif
subs len, len, #1
strh out32, [r3], #2
bgt LR(0, b)
add sp, sp, #48
ldmia sp!, {r4-r10, fp, ip, pc}
/*MAIN_FORLOOP1: //pS&3!=0*/
L(4)
L(0)
mov out32, #0
ldr order, [sp, #arg_Order]
/*MAIN_INNER_FORLOOP1:*/
ldrh S_val, [r2], #2
ldr S_tmp1, [r2]
ldr S_tmp2, [r2, #4]
ldr B_val, [r1], #4
sub order, order, #4
add S_val, S_val, S_tmp1, lsl #16
mov S_tmp1, S_tmp1, lsr #16
str S_val, [r2], #4
SKP_SMLAD out32, B_val, S_val, out32
L(1)
ldr B_val, [r1], #4
add S_val, S_tmp1, S_tmp2, lsl #16
mov S_tmp1, S_tmp2, lsr #16
subs order, order, #2
#ifdef _WINRT
ble LR(2, f)
ldr S_tmp2, [r2, #4]
L(2)
#else
ldrgt S_tmp2, [r2, #4]
#endif
str S_val, [r2], #4
SKP_SMLAD out32, B_val, S_val, out32
bgt LR(1, b)
ldrsh S_tmp2, [r2]
ldr B_val, [r1]
add S_val, S_tmp1, S_tmp2, lsl #16
SKP_SMLAD out32, B_val, S_val, out32
strh S_val, [r2]
ldrsh in, [r0], #2
ldr r2, [sp, #sp_pS]
ldr r1, [sp, #sp_pB]
mov in_Q12, in, lsl #12
qsub out32, in_Q12, out32
mov out32, out32, asr #11
strh in, [r2]
add out32, out32, #1
#if EMBEDDED_ARM >=6
ssat out32, #16, out32, asr #1
#else
mov out32, out32, asr #1
cmp out32, #0x8000
mvnge out32, #0x8000
subge out32, out32, #1
cmn out32, #0x8000
movlt out32, #0x8000
#endif
subs len, len, #1
strh out32, [r3], #2
bgt LR(0, b)
add sp, sp, #48
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 8,030
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_array_maxabs_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
VARDEF ptr_vec, r0
VARDEF val_vec, r2
VARDEF val_return, r0
VARDEF len, r1
VARDEF val1_max, r3
VARDEF val2_max, r4
VARDEF val_lvl, r5
VARDEF val_ind, r6
VARDEF const_int16_MAX, r5
.globl SYM(SKP_Silk_int16_array_maxabs)
SYM(SKP_Silk_int16_array_maxabs):
stmdb sp!, {r4-r6, fp, ip, lr}
add fp, sp, #20
cmp r1, #6
mvn r5, #0 /*r5 = -1(max)*/
blt LR(7, f)
ands r2, r0, #3
bne LR(3, f)
ands r2, r1, #0x1
bne LR(1, f)
ldr val_vec, [ptr_vec], #4
sub len, len, #2
L(0)
smulbb val1_max, val_vec, val_vec
smultt val2_max, val_vec, val_vec
ldr val_vec, [ptr_vec], #4
cmp val1_max, r5
movge val_lvl, val1_max
#ifdef _WINRT
subge val_ind, ptr_vec, #4 /*address*/
subge val_ind, val_ind, #4 /*address*/
#else
subge val_ind, ptr_vec, #8 /*address*/
#endif
cmp val2_max, val_lvl
movge val_lvl, val2_max
subge val_ind, ptr_vec, #6
subs len, len, #2
bgt LR(0, b)
smulbb val1_max, val_vec, val_vec
smultt val2_max, val_vec, val_vec
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #4 /*address*/
cmp val2_max, val_lvl
movge val_lvl, val2_max
subge val_ind, ptr_vec, #2
b LR(9, f)
/*Odd number of iterations*/
L(1)
ldr val_vec, [ptr_vec], #4
sub len, len, #3
L(2)
smulbb val1_max, val_vec, val_vec
smultt val2_max, val_vec, val_vec
ldr val_vec, [ptr_vec], #4
cmp val1_max, val_lvl
movge val_lvl, val1_max
#ifdef _WINRT
subge val_ind, ptr_vec, #4 /*address*/
subge val_ind, val_ind, #4 /*address*/
#else
subge val_ind, ptr_vec, #8 /*address*/
#endif
cmp val2_max, val_lvl
movge val_lvl, val2_max
subge val_ind, ptr_vec, #6
subs len, len, #2
bgt LR(2, b)
smulbb val1_max, val_vec, val_vec
smultt val2_max, val_vec, val_vec
ldrsh val_vec, [ptr_vec], #2
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #6 /*address*/
smulbb val1_max, val_vec, val_vec
cmp val2_max, val_lvl
movge val_lvl, val2_max
subge val_ind, ptr_vec, #4
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #2 /*address*/
b LR(9, f)
/*Oddly aligned*/
L(3)
ands r2, r1, #0x1
bne LR(5, f)
ldrsh val_vec, [ptr_vec], #2
smulbb val1_max, val_vec, val_vec
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #2
ldr val_vec, [ptr_vec], #4
sub len, len, #4
L(4)
smulbb val1_max, val_vec, val_vec
smultt val2_max, val_vec, val_vec
ldr val_vec, [ptr_vec], #4
cmp val1_max, val_lvl
movge val_lvl, val1_max
#ifdef _WINRT
subge val_ind, ptr_vec, #4 /*address*/
subge val_ind, val_ind, #4 /*address*/
#else
subge val_ind, ptr_vec, #8 /*address*/
#endif
cmp val2_max, val_lvl
movge val_lvl, val2_max
subge val_ind, ptr_vec, #6
subs len, len, #2
bgt LR(4, b)
smulbb val1_max, val_vec, val_vec
smultt val2_max, val_vec, val_vec
ldrsh val_vec, [ptr_vec], #2
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #6 /*address*/
smulbb val1_max, val_vec, val_vec
cmp val2_max, val_lvl
movge val_lvl, val2_max
subge val_ind, ptr_vec, #4
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #2 /*address*/
b LR(9, f)
/*Odd number of iterations+Oddly aligned*/
L(5)
ldrsh val_vec, [ptr_vec], #2
smulbb val1_max, val_vec, val_vec
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #2
ldr val_vec, [ptr_vec], #4
sub len, len, #3
L(6)
smulbb val1_max, val_vec, val_vec
smultt val2_max, val_vec, val_vec
ldr val_vec, [ptr_vec], #4
cmp val1_max, val_lvl
movge val_lvl, val1_max
#ifdef _WINRT
subge val_ind, ptr_vec, #4 /*address*/
subge val_ind, val_ind, #4 /*address*/
#else
subge val_ind, ptr_vec, #8 /*address*/
#endif
cmp val2_max, val_lvl
movge val_lvl, val2_max
subge val_ind, ptr_vec, #6
subs len, len, #2
bgt LR(6, b)
smulbb val1_max, val_vec, val_vec
smultt val2_max, val_vec, val_vec
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #4 /*address*/
cmp val2_max, val_lvl
movge val_lvl, val2_max
subge val_ind, ptr_vec, #2
b LR(9, f)
/*Less than 6 iterations*/
L(7)
ldrsh val_vec, [ptr_vec], #2
sub len, len, #1
L(8)
smulbb val1_max, val_vec, val_vec
ldrsh val_vec, [ptr_vec], #2
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #4
subs len, len, #1
bgt LR(8, b)
smulbb val1_max, val_vec, val_vec
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #2
L(9)
ldrsh val_return, [val_ind]
mvn const_int16_MAX, #0x80000000
mov const_int16_MAX, const_int16_MAX, asr #16
cmp val_return, #0
rsblt val_return, val_return, #0
cmp val_return, const_int16_MAX
movge val_return, const_int16_MAX
ldmia sp!, {r4-r6, fp, ip, pc}
#elif EMBEDDED_ARM>=4
VARDEF ptr_vec, r0
VARDEF val1_vec, r2
VARDEF val2_vec, r7
VARDEF len, r1
VARDEF val1_max, r3
VARDEF val2_max, r8
VARDEF val_lvl, r5
VARDEF val_ind, r6
VARDEF val_return, r0
VARDEF const_int16_MAX, r5
.globl SYM(SKP_Silk_int16_array_maxabs)
SYM(SKP_Silk_int16_array_maxabs):
stmdb sp!, {r4-r8, fp, ip, lr}
add fp, sp, #28
mvn val_lvl, #0 /*r5 = -1(max)*/
ldrsh val1_vec, [ptr_vec], #2
ldrsh val2_vec, [ptr_vec], #2
sub len, len, #2
L(0)
mul val1_max, val1_vec, val1_vec
mul val2_max, val2_vec, val2_vec
ldrsh val1_vec, [ptr_vec], #2
ldrsh val2_vec, [ptr_vec], #2
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #8
cmp val2_max, val_lvl
movge val_lvl, val2_max
subge val_ind, ptr_vec, #6
subs len, len, #2
bgt LR(0, b)
mul val1_max, val1_vec, val1_vec
mul val2_max, val2_vec, val2_vec
cmp val1_max, val_lvl
movge val_lvl, val1_max
subge val_ind, ptr_vec, #4
cmn len, #1 /*r1?=-1*/
beq LR(1, f)
cmp val2_max, val_lvl
movge val_lvl, val2_max
subge val_ind, ptr_vec, #2
L(1)
ldrsh val_return, [val_ind]
mvn const_int16_MAX, #0x80000000
mov const_int16_MAX, const_int16_MAX, asr #16
cmp val_return, #0
rsblt val_return, val_return, #0
cmp val_return, const_int16_MAX
movge val_return, const_int16_MAX
ldmia sp!, {r4-r8, fp, ip, pc}
#endif
END
#endif
|
AgoraIO-Community/Solo
| 5,346
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_schur64_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=6
VARDEF ptr_rc, r4
VARDEF ptr_C0, r3
VARDEF val_C0, _r7
VARDEF ptr_C1, _r7
VARDEF val_a32, r0
VARDEF val_b32, r1
VARDEF val_a32_tmp, r2
VARDEF val_b32_tmp, r3
VARDEF a_headrm, r0
VARDEF b_headrm, r1
VARDEF a32_nrm, r5
VARDEF b32_nrm, sl
VARDEF headrm_tmp, r8
VARDEF result, r1
VARDEF tmp0, r2
VARDEF lshift, r3
VARDEF rc_tmp_Q31, r0
VARDEF tmp1, r1
VARDEF val_rc, r2
VARDEF ptr_C2, r8
VARDEF ptr_C3, sb
VARDEF val_C2, r1
VARDEF val_C3, r2
VARDEF out_C2, r5
VARDEF out_C3, sl
VARDEF order1, r6
VARDEF order2, r3
EXTERN SYM(SKP_DIV32_arm)
.set sp_ptr_C, 0
.globl SYM(SKP_Silk_schur64)
SYM(SKP_Silk_schur64):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #136
mov ptr_rc, r0 /*rc_Q16*/
mov order1, r2 /*order*/
mov ptr_C0, sp
ldr val_C0, [r1], #4
L(0)
subs r2, r2, #1
str val_C0, [ptr_C0], #4
str val_C0, [ptr_C0], #4
ldr val_C0, [r1], #4
bgt LR(0, b)
str val_C0, [ptr_C0], #4
str val_C0, [ptr_C0], #4
add ptr_C1, sp, #8
L(1)
ldr val_a32, [ptr_C1], #8
ldr val_b32, [sp, #4]
rsb val_a32, val_a32, #0 /*-C[k + 1][0]*/
mov val_a32_tmp, val_a32 /*a32*/
mov val_b32_tmp, val_b32 /*b32*/
cmp val_a32, #0
rsblt val_a32, val_a32_tmp, #0 /*a_headrm*/
clz a_headrm, val_a32
cmp val_b32, #0
rsblt val_b32, val_b32_tmp, #0 /*b_headrm*/
clz b_headrm, val_b32
sub a_headrm, a_headrm, #1
sub b_headrm, b_headrm, #1
mov a32_nrm, val_a32_tmp, lsl a_headrm /*a32_nrm*/
mov b32_nrm, val_b32_tmp, lsl b_headrm /*b32_nrm*/
sub headrm_tmp, a_headrm, b_headrm /*a_headrm - b_headrm*/
mvn r0, #0x80000000 /*r0 = 0x7FFF FFFF*/
mov r1, b32_nrm, asr #16 /*SKP_RSHIFT(b32_nrm, 16)*/
mov r0, r0, asr #2
// registers need to preserve: ptr_rc (r4)
// a32_nrm (r5)
// order1 (r6)
// ptr_C1 (r7)
// headrm_tmp (r8)
// b32_nrm (sl)
bl SYM(SKP_DIV32_arm)
smulwb result, a32_nrm, r0 /*result = SKP_SMULWB(a32_nrm, b32_inv);*/
smmul tmp0, b32_nrm, result /*SKP_SMMUL(b32_nrm, result)*/
sub a32_nrm, a32_nrm, tmp0, lsl #3 /*a32_nrm -= SKP_LSHIFT_ovflw( SKP_SMMUL(b32_nrm, result), 3 );*/
smlawb result, a32_nrm, r0, result /*result = SKP_SMLAWB(result, a32_nrm, b32_inv);*/
subs lshift, headrm_tmp, #2 /*lshift= 29 + a_headrm - b_headrm - Qres;*/
rsble lshift, lshift, #0
#ifdef _WINRT
bgt LR(3, f)
mov rc_tmp_Q31, result, lsl lshift
b LR(4, f)
L(3)
mov rc_tmp_Q31, result, asr lshift
L(4)
#else
movle rc_tmp_Q31, result, lsl lshift
movgt rc_tmp_Q31, result, asr lshift
#endif
mov tmp1, rc_tmp_Q31, asr #14 /*SKP_RSHIFT_ROUND( rc_tmp_Q31, 15 )*/
add val_rc, tmp1, #1
mov val_rc, val_rc, asr #1
str val_rc, [ptr_rc], #4
mov order2, order1 /*order-k*/
sub ptr_C2, ptr_C1, #8 /*r8 = &C[k+1][0]*/
add ptr_C3, sp, #4 /*sb = &C[0][1]*/
L(2)
ldr val_C2, [ptr_C2]
ldr val_C3, [ptr_C3]
subs order2, order2, #1
mov out_C2, val_C2, lsl #1
mov out_C3, val_C3, lsl #1
smmul out_C2, out_C2, rc_tmp_Q31
smmul out_C3, out_C3, rc_tmp_Q31
add out_C2, out_C2, val_C3
add out_C3, out_C3, val_C2
str out_C2, [ptr_C3], #8
str out_C3, [ptr_C2], #8
bgt LR(2, b)
subs order1, order1, #1
bgt LR(1, b)
ldr r0, [sp, #4] /*r0 = C[0][1]*/
add sp, sp, #136
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 9,351
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_resampler_rom_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
EXPORT SYM(SKP_Silk_resampler_frac_FIR_144_alt)
/*DATA*/
ALIGN 4
SKP_TABLE SKP_Silk_resampler_frac_FIR_144_alt, 2
DCW -647, 1884, 30078, 2207, -851, 73, \
-625, 1736, 30044, 2409, -901, 81, \
-603, 1591, 30005, 2614, -952, 89, \
-581, 1448, 29963, 2820, -1003, 97, \
-559, 1308, 29917, 3028, -1054, 105, \
-537, 1169, 29867, 3238, -1105, 113, \
-515, 1032, 29813, 3450, -1156, 121, \
-494, 898, 29755, 3664, -1207, 129, \
-473, 766, 29693, 3880, -1258, 137, \
-452, 636, 29627, 4098, -1309, 145
DCW -431, 508, 29558, 4317, -1359, 152, \
-410, 383, 29484, 4538, -1410, 160, \
-390, 260, 29407, 4761, -1460, 168, \
-369, 139, 29327, 4986, -1511, 175, \
-349, 20, 29242, 5212, -1561, 183, \
-330, -97, 29154, 5439, -1611, 190, \
-310, -211, 29062, 5668, -1660, 197, \
-291, -324, 28967, 5899, -1709, 204, \
-271, -434, 28868, 6131, -1758, 212, \
-253, -542, 28765, 6364, -1807, 219
DCW -234, -647, 28659, 6599, -1856, 226, \
-215, -751, 28550, 6835, -1904, 232, \
-197, -852, 28436, 7072, -1951, 239, \
-179, -951, 28320, 7311, -1998, 246, \
-162, -1048, 28200, 7550, -2045, 252, \
-144, -1143, 28077, 7791, -2091, 259, \
-127, -1235, 27950, 8032, -2137, 265, \
-110, -1326, 27820, 8275, -2182, 271, \
-94, -1414, 27687, 8519, -2227, 277, \
-77, -1500, 27550, 8763, -2271, 283
DCW -61, -1584, 27410, 9009, -2315, 289, \
-45, -1665, 27268, 9255, -2358, 294, \
-30, -1745, 27122, 9502, -2400, 300, \
-15, -1822, 26972, 9750, -2442, 305, \
0, -1897, 26820, 9998, -2482, 310, \
15, -1970, 26665, 10247, -2523, 315, \
29, -2041, 26507, 10497, -2562, 320, \
44, -2110, 26346, 10747, -2601, 324, \
57, -2177, 26182, 10997, -2639, 328, \
71, -2242, 26015, 11248, -2676, 333
DCW 84, -2305, 25845, 11500, -2712, 337, \
97, -2365, 25673, 11751, -2747, 341, \
110, -2424, 25498, 12003, -2782, 344, \
122, -2480, 25320, 12255, -2815, 348, \
134, -2534, 25140, 12508, -2848, 351, \
146, -2587, 24956, 12760, -2880, 354, \
157, -2637, 24771, 13012, -2910, 357, \
168, -2685, 24583, 13265, -2940, 359, \
179, -2732, 24392, 13517, -2968, 362, \
190, -2776, 24199, 13770, -2996, 364
DCW 200, -2819, 24003, 14022, -3022, 366, \
210, -2859, 23805, 14274, -3048, 368, \
220, -2898, 23605, 14526, -3072, 369, \
229, -2934, 23403, 14777, -3095, 370, \
238, -2969, 23198, 15028, -3117, 371, \
247, -3002, 22992, 15279, -3138, 372, \
255, -3033, 22783, 15529, -3157, 373, \
263, -3062, 22572, 15779, -3175, 373, \
271, -3089, 22359, 16028, -3192, 373, \
279, -3114, 22144, 16277, -3208, 373
DCW 286, -3138, 21927, 16525, -3222, 372, \
293, -3160, 21709, 16772, -3235, 372, \
300, -3180, 21488, 17018, -3247, 371, \
306, -3198, 21266, 17264, -3257, 369, \
312, -3215, 21042, 17509, -3266, 368, \
318, -3229, 20816, 17753, -3273, 366, \
323, -3242, 20589, 17996, -3279, 364, \
328, -3254, 20360, 18238, -3283, 362, \
333, -3263, 20130, 18478, -3286, 359, \
338, -3272, 19898, 18718, -3288, 356
DCW 342, -3278, 19665, 18957, -3288, 353, \
346, -3283, 19430, 19194, -3286, 350, \
350, -3286, 19194, 19430, -3283, 346, \
353, -3288, 18957, 19665, -3278, 342, \
356, -3288, 18718, 19898, -3272, 338, \
359, -3286, 18478, 20130, -3263, 333, \
362, -3283, 18238, 20360, -3254, 328, \
364, -3279, 17996, 20589, -3242, 323, \
366, -3273, 17753, 20816, -3229, 318, \
368, -3266, 17509, 21042, -3215, 312
DCW 369, -3257, 17264, 21266, -3198, 306, \
371, -3247, 17018, 21488, -3180, 300, \
372, -3235, 16772, 21709, -3160, 293, \
372, -3222, 16525, 21927, -3138, 286, \
373, -3208, 16277, 22144, -3114, 279, \
373, -3192, 16028, 22359, -3089, 271, \
373, -3175, 15779, 22572, -3062, 263, \
373, -3157, 15529, 22783, -3033, 255, \
372, -3138, 15279, 22992, -3002, 247, \
371, -3117, 15028, 23198, -2969, 238
DCW 370, -3095, 14777, 23403, -2934, 229, \
369, -3072, 14526, 23605, -2898, 220, \
368, -3048, 14274, 23805, -2859, 210, \
366, -3022, 14022, 24003, -2819, 200, \
364, -2996, 13770, 24199, -2776, 190, \
362, -2968, 13517, 24392, -2732, 179, \
359, -2940, 13265, 24583, -2685, 168, \
357, -2910, 13012, 24771, -2637, 157, \
354, -2880, 12760, 24956, -2587, 146, \
351, -2848, 12508, 25140, -2534, 134
DCW 348, -2815, 12255, 25320, -2480, 122, \
344, -2782, 12003, 25498, -2424, 110, \
341, -2747, 11751, 25673, -2365, 97, \
337, -2712, 11500, 25845, -2305, 84, \
333, -2676, 11248, 26015, -2242, 71, \
328, -2639, 10997, 26182, -2177, 57, \
324, -2601, 10747, 26346, -2110, 44, \
320, -2562, 10497, 26507, -2041, 29, \
315, -2523, 10247, 26665, -1970, 15, \
310, -2482, 9998, 26820, -1897, 0
DCW 305, -2442, 9750, 26972, -1822, -15, \
300, -2400, 9502, 27122, -1745, -30, \
294, -2358, 9255, 27268, -1665, -45, \
289, -2315, 9009, 27410, -1584, -61, \
283, -2271, 8763, 27550, -1500, -77, \
277, -2227, 8519, 27687, -1414, -94, \
271, -2182, 8275, 27820, -1326, -110, \
265, -2137, 8032, 27950, -1235, -127, \
259, -2091, 7791, 28077, -1143, -144, \
252, -2045, 7550, 28200, -1048, -162
DCW 246, -1998, 7311, 28320, -951, -179, \
239, -1951, 7072, 28436, -852, -197, \
232, -1904, 6835, 28550, -751, -215, \
226, -1856, 6599, 28659, -647, -234, \
219, -1807, 6364, 28765, -542, -253, \
212, -1758, 6131, 28868, -434, -271, \
204, -1709, 5899, 28967, -324, -291, \
197, -1660, 5668, 29062, -211, -310, \
190, -1611, 5439, 29154, -97, -330, \
183, -1561, 5212, 29242, 20, -349
DCW 175, -1511, 4986, 29327, 139, -369, \
168, -1460, 4761, 29407, 260, -390, \
160, -1410, 4538, 29484, 383, -410, \
152, -1359, 4317, 29558, 508, -431, \
145, -1309, 4098, 29627, 636, -452, \
137, -1258, 3880, 29693, 766, -473, \
129, -1207, 3664, 29755, 898, -494, \
121, -1156, 3450, 29813, 1032, -515, \
113, -1105, 3238, 29867, 1169, -537, \
105, -1054, 3028, 29917, 1308, -559
DCW 97, -1003, 2820, 29963, 1448, -581, \
89, -952, 2614, 30005, 1591, -603, \
81, -901, 2409, 30044, 1736, -625, \
73, -851, 2207, 30078, 1884, -647
END
#endif
#endif
|
AgoraIO-Community/Solo
| 3,613
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_resampler_private_ARMA4_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
VARDEF len, r0
VARDEF S_0, r3
VARDEF S_1, r4
VARDEF S_2, r5
VARDEF S_3, r6
VARDEF in, _r7
VARDEF out1, r8
VARDEF coef01, sb
VARDEF coef23, sl
VARDEF coef45, ip
VARDEF coef6, r8
VARDEF coef_tmp, _r7
VARDEF out2, lr
.set sp_S, 0
.set sp_coef, 4
.globl SYM(SKP_Silk_resampler_private_ARMA4)
SYM(SKP_Silk_resampler_private_ARMA4):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #8
.set sp_len, 48
ldr lr, [sp, #sp_len]
ldrh coef01, [r3], #2
ldrh S_1, [r3], #2
ldrh coef23, [r3], #2
ldrh S_2, [r3], #2
ldrh coef45, [r3], #2
ldrh S_3, [r3], #2
ldrh coef6, [r3], #2
cmp lr, #0
str r0, [sp, #sp_S]
beq LR(1, f) // if len==0
str coef6, [sp, #sp_coef]
ldrsh in, [r2], #2
add coef01, coef01, S_1, lsl #16
add coef23, coef23, S_2, lsl #16
add coef45, coef45, S_3, lsl #16
ldmia r0, {S_0, S_1, S_2, S_3}
mov len, lr
L(0)
mov in, in, lsl #8
add out1, in, S_0, lsl #2
add out2, out1, S_2, lsl #2
smlawb S_0, in, coef01, S_1
smlawb S_0, out1, coef23, S_0
smlawt S_2, out1, coef01, S_3
smlawb S_2, out2, coef45, S_2
smulwt S_1, out1, coef23
smulwt S_3, out2, coef45
add S_1, S_1, in, asr #2
ldr coef_tmp, [sp, #sp_coef]
add S_3, S_3, out1, asr #2
mov out1, #128
smlawb out1, out2, coef_tmp, out1
#if EMBEDDED_ARM<6
cmp out1, #0x800000
movge out1, #0x800000
subge out1, out1, #1
cmn out1, #0x800000
movlt out1, #0x800000
mov out1, out1, asr #8
#else
ssat out1, #16, out1, asr #8
#endif
subs len, len, #1
strh out1, [r1], #2
#ifdef _WINRT
ble LR(1, f)
ldrsh in, [r2], #2
b LR(0, b)
L(1)
#else
ldrgtsh in, [r2], #2
bgt LR(0, b)
#endif
ldr r0, [sp, #sp_S]
stmia r0, {S_0, S_1, S_2, S_3}
L(1)
add sp, sp, #8
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 3,431
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_sum_sqr_shift_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
VARDEF x0, r4
VARDEF nrg_tmp, r5
VARDEF shift, r6
VARDEF nrg, _r7
VARDEF idx, r8
.globl SYM(SKP_Silk_sum_sqr_shift)
SYM(SKP_Silk_sum_sqr_shift):
stmdb sp!, {r4-r8, fp, ip, lr}
add fp, sp, #28
mov idx, r3
ands nrg_tmp, r2, #2
mov nrg, #0
#ifdef _WINRT
beq LR(6, f)
ldrh x0, [r2], #2
smulbb nrg, x0, x0
sub idx, idx, #1
L(6)
#else
ldrneh x0, [r2], #2
smulbbne nrg, x0, x0
subne idx, idx, #1
#endif
ldr r4, [r2], #4
mov shift, #0
sub idx, idx, #1
L(0)
subs idx, idx, #2
SKP_SMLAD nrg, x0, x0, nrg
#ifdef _WINRT
ldrgt x0, [r2]
addgt r2, r2, #4
#else
ldrgt x0, [r2], #4
#endif
cmp nrg, #0
blt LR(1, f)
cmp idx, #0
bgt LR(0, b)
beq LR(4, f)
b LR(5, f)
L(1)
mov nrg, nrg, lsr #2
mov shift, #2
cmp idx, #0
beq LR(4, f)
blt LR(5, f)
L(3)
subs idx, idx, #2
SKP_SMUAD nrg_tmp, x0, x0
#ifdef _WINRT
ldrgt x0, [r2]
addgt r2, r2, #4
mov nrg_tmp, nrg_tmp, lsr shift
adds nrg, nrg, nrg_tmp
#else
ldrgt x0, [r2], #4
add nrg, nrg, nrg_tmp, lsr shift
cmp nrg, #0
#endif
movlt nrg, nrg, lsr #2
addlt shift, shift, #2
cmp idx, #0
bgt LR(3, b)
blt LR(5, f)
L(4)
ldrh x0, [r2]
smulbb nrg_tmp, x0, x0
#ifdef _WINRT
mov nrg_tmp, nrg_tmp, lsr shift
add nrg, nrg, nrg_tmp
#else
add nrg, nrg, nrg_tmp, lsr shift
#endif
L(5)
ands nrg_tmp, nrg, #0xC0000000
movne nrg, nrg, lsr #2
addne shift, shift, #2
str shift, [r1]
str nrg, [r0]
ldmia sp!, {r4-r8, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 3,588
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_allpass_int_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM >= 5
VARDEF A, r2
VARDEF len, r4
VARDEF S00, r5
VARDEF ink1, r6
VARDEF ink2, r8
VARDEF Y2, sb
VARDEF outk1, sl
VARDEF outk2, ip
.globl SYM(SKP_Silk_allpass_int)
SYM(SKP_Silk_allpass_int):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
.set len_offset, 40
ldr len, [sp, #len_offset]
ldr S00, [r1]
movs A, A, lsl #17
sub len, len, #1
ldmia r0!, {ink1,ink2}
bge LR(1, f)/*AgeZero*/
L(0)
sub Y2, ink1, S00
smlawt outk1, Y2, A, ink1
add S00, Y2, outk1
subs len, len, #2
sub Y2, ink2, S00
smlawt outk2, Y2, A, ink2
#ifdef _WINRT
ble LR(3, f)
ldmia r0!, {ink1,ink2}
L(3)
#else
ldmgtia r0!, {ink1,ink2}
#endif
add S00, Y2, outk2
stmia r3!, {outk1, outk2}
bgt LR(0, b)
#ifdef _WINRT
bne LR(2, f)
ldr ink1, [r0], #4
sub Y2, ink1, S00
smlawt outk1, Y2, A, ink1
add S00, Y2, outk1
str outk1, [r3]
L(2)
#else
ldreq ink1, [r0], #4
subeq Y2, ink1, S00
smlawteq outk1, Y2, A, ink1
addeq S00, Y2, outk1
streq outk1, [r3]
#endif
str S00, [r1]
ldmia sp!, {r4-r10, fp, ip, pc}
L(1)/*AgeZero:*/
sub Y2, ink1, S00
smlawt outk1, Y2, A, S00
add S00, Y2, outk1
subs len, len, #2
sub Y2, ink2, S00
smlawt outk2, Y2, A, S00
#ifdef _WINRT
ble LR(3, f)
ldmia r0!, {ink1,ink2}
L(3)
#else
ldmgtia r0!, {ink1,ink2}
#endif
add S00, Y2, outk2
stmia r3!, {outk1, outk2}
bgt LR(1, b)
#ifdef _WINRT
bne LR(2, f)
ldr ink1, [r0], #4
sub Y2, ink1, S00
smlawt outk1, Y2, A, S00
add S00, Y2, outk1
str outk1, [r3]
L(2)
#else
ldreq ink1, [r0], #4
subeq Y2, ink1, S00
smlawteq outk1, Y2, A, S00
addeq S00, Y2, outk1
streq outk1, [r3]
#endif
str S00, [r1]
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 4,293
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_resampler_private_up2_HQ_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
VARDEF S_ptr, r0
VARDEF xy0, r4
VARDEF xy1, r5
VARDEF up2_coefs, r6
#ifdef IPHONE
VARDEF S_0, r8
VARDEF S_1, _r7
VARDEF S_2, r8
VARDEF S_3, _r7
VARDEF S_4, r8
VARDEF S_5, _r7
#else
VARDEF S_0, _r7
VARDEF S_1, r8
VARDEF S_2, _r7
VARDEF S_3, r8
VARDEF S_4, _r7
VARDEF S_5, r8
#endif
VARDEF in, sb
VARDEF out1, sl
VARDEF out2, ip
VARDEF out, lr
.globl SYM(SKP_Silk_resampler_private_up2_HQ)
SYM(SKP_Silk_resampler_private_up2_HQ):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
L(0)
ldrsh in, [r2], #2
ldmia S_ptr, {S_0, S_1}
ldr up2_coefs, SYM(resampler_up2_hq_0)
mov in, in, lsl #10
sub xy0, in, S_0
smulwb xy0, xy0, up2_coefs
add out1, S_0, xy0
sub xy1, out1, S_1
smlawt xy1, xy1, up2_coefs, xy1
add out2, S_1, xy1
add S_0, in, xy0
add S_1, out1, xy1
stmia S_ptr, {S_0, S_1}
add S_ptr, S_ptr, #16 // &S[4]
ldmia S_ptr, {S_4, S_5}
ldr xy1, SYM(resampler_up2_hq_notch_2)
ldr xy0, SYM(resampler_up2_hq_notch_1)
ldr up2_coefs, SYM(resampler_up2_hq_1)
sub S_ptr, S_ptr, #8 // &S[2]
mov out, #256
smlawb out2, S_5, xy1, out2
smlawt out2, S_4, xy0, out2
smlawb out1, S_4, xy0, out2
smlawt out, out1, xy1, out
sub S_5, out2, S_5
#if EMBEDDED_ARM<6
cmp out, #0x1000000
movge out, #0x1000000
subge out, out, #1
cmn out, #0x1000000
movlt out, #0x1000000
mov out, out, asr #9
#else
ssat out, #16, out, asr #9
#endif
str S_5, [S_ptr, #12] // S[5]
strh out, [r1], #2
ldmia S_ptr, {S_2, S_3}
sub xy0, in, S_2
smulwb xy0, xy0, up2_coefs
add out1, S_2, xy0
sub xy1, out1, S_3
smlawt xy1, xy1, up2_coefs, xy1
add out2, S_3, xy1
add S_2, in, xy0
add S_3, out1, xy1
stmia S_ptr!, {S_2, S_3}
ldmia S_ptr, {S_4, S_5}
ldr xy1, SYM(resampler_up2_hq_notch_2)
ldr xy0, SYM(resampler_up2_hq_notch_1)
mov out, #256
smlawb out2, S_4, xy1, out2
smlawt out2, S_5, xy0, out2
smlawb out1, S_5, xy0, out2
smlawt out, out1, xy1, out
sub S_4, out2, S_4
#if EMBEDDED_ARM<6
cmp out, #0x1000000
movge out, #0x1000000
subge out, out, #1
cmn out, #0x1000000
movlt out, #0x1000000
mov out, out, asr #9
#else
ssat out, #16, out, asr #9
#endif
subs r3, r3, #1
str S_4, [S_ptr], #-16 // &S[0]
strh out, [r1], #2
bgt LR(0, b)
ldmia sp!, {r4-r10, fp, ip, pc}
L(SYM(resampler_up2_hq_0))
DCD 0x83BF10B8
L(SYM(resampler_up2_hq_1))
DCD 0xD2FF3FA7
L(SYM(resampler_up2_hq_notch_1))
DCD 0xF1EC1EB8
L(SYM(resampler_up2_hq_notch_2))
DCD 0x6F5C3333
END
#endif
#endif
|
AgoraIO-Community/Solo
| 3,460
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_resampler_down2_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
#define SKP_Silk_resampler_down2_0 0x2690
#define SKP_Silk_resampler_down2_1 0x9B81
VARDEF xy0, r4
VARDEF xy1, r5
VARDEF down2_coefs, _r7
VARDEF S_0, r6
VARDEF S_1, r8
VARDEF in0, sb
VARDEF in1, sl
VARDEF out32, r0
.set sp_S, 0
.globl SYM(SKP_Silk_resampler_down2)
SYM(SKP_Silk_resampler_down2):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #4
ldrsh in0, [r2], #2 // Avoid un-aligned access
ldrsh in1, [r2], #2
str r0, [sp, #sp_S]
ldmia r0, {S_0, S_1}
mov down2_coefs, #0x26000000
add down2_coefs, down2_coefs, #0x900000
add down2_coefs, down2_coefs, #0x9B00
add down2_coefs, down2_coefs, #0x81
mov r3, r3, asr #1
mov ip, #1024
L(0)
add out32, S_0, S_1
rsb xy0, S_0, in0, lsl #10
rsb xy1, S_1, in1, lsl #10
smlawb xy0, xy0, down2_coefs, xy0
smulwt xy1, xy1, down2_coefs
add out32, out32, xy0
add S_0, xy0, in0, lsl #10
add out32, out32, xy1
add S_1, xy1, in1, lsl #10
#if EMBEDDED_ARM>=6
qadd out32, out32, ip
subs r3, r3, #1
ssat out32, #16, out32, asr #11
#ifdef _WINRT
ble LR(1, f)
ldrsh in0, [r2], #2
ldrsh in1, [r2], #2
L(1)
#else
ldrgtsh in0, [r2], #2
ldrgtsh in1, [r2], #2
#endif
#else
qadd out32, out32, ip
cmp out32, #0x4000000
movge out32, #0x4000000
subge out32, out32, #1
cmn out32, #0x4000000
movlt out32, #0x4000000
subs r3, r3, #1
mov out32, out32, asr #11
ldrgtsh in0, [r2], #2
ldrgtsh in1, [r2], #2
#endif
strh out32, [r1], #2
bgt LR(0, b)
ldr r0, [sp, #sp_S]
stmia r0, {S_0, S_1}
add sp, sp, #4
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
|
AgoraIO-Community/Solo
| 15,326
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_inner_prod_aligned_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if ( EMBEDDED_ARM >= 7 )
VARDEF len32, r3
VARDEF len32tmp, lr
VARDEF ptr1, r2
VARDEF ptr2, r1
VARDEF tmp1, r4
VARDEF tmp2, r5
VARDEFD val_0, d0
VARDEFD val_1, d1
VARDEFD val_2, d2
VARDEFD val_3, d3
VARDEFQ sum_tmp1, q2
VARDEFQ sum_tmp2, q3
VARDEFD sum_tmp1_lo, d4
VARDEFD sum_tmp1_hi, d5
.globl SYM(SKP_Silk_inner_prod_aligned)
SYM(SKP_Silk_inner_prod_aligned):
stmdb sp!, {r4-r10, fp, ip, lr}
vpush {q0-q7}
add fp, sp, #164
mov len32, r2 // put length into r3
mov ptr1, r0 // put in1 to r2
mov r0, #0 // put result to r0
// USE SL8D, SI4D
L(2)
cmp len32, #24
and len32tmp, len32, #0x7
blt LR(3, f)
vmov.i32 sum_tmp1, #0
vld1.16 {val_0, val_1}, [ptr2]!
vld1.16 {val_2, val_3}, [ptr1]!
vmov.i32 sum_tmp2, #0 // Set Q2, Q3 to 0
sub len32, len32, #16
L(0)
subs len32, len32, #8
vmlal.s16 sum_tmp1, val_0, val_2
vmlal.s16 sum_tmp2, val_1, val_3
vld1.16 {val_0, val_1}, [ptr2]!
vld1.16 {val_2, val_3}, [ptr1]!
bge LR(0, b)
vmlal.s16 sum_tmp1, val_0, val_2
vmlal.s16 sum_tmp2, val_1, val_3
vadd.s32 sum_tmp1, sum_tmp1, sum_tmp2
vadd.s32 val_0, sum_tmp1_lo, sum_tmp1_hi
vmov tmp1, tmp2, val_0
cmp len32tmp, #0 // Check if length%4 == 0
add r0, r0, tmp1
add r0, r0, tmp2
bgt LR(1, f) // Jump to process the reminder
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
VARDEFQ sum_tmp3, q1
VARDEFD sum_tmp3_lo, d2
VARDEFD sum_tmp3_hi, d3
// USE SL4D, SI4D
L(3)
cmp len32, #12
and len32tmp, len32, #0x3
movlt len32tmp, len32 // if length is not enough for SIMD.
blt LR(1, f)
vld1.16 val_0, [ptr2]!
vld1.16 val_1, [ptr1]!
vmov.i32 sum_tmp3, #0
sub len32, len32, #8
L(0)
subs len32, len32, #4
vmlal.s16 sum_tmp3, val_0, val_1
vld1.16 val_0, [ptr2]!
vld1.16 val_1, [ptr1]!
bge LR(0, b)
vmlal.s16 sum_tmp3, val_0, val_1
vadd.s32 val_0, sum_tmp3_lo, sum_tmp3_hi
vmov tmp1, tmp2, val_0
cmp len32tmp, #0 // Check if length%4 == 0
add r0, r0, tmp1
add r0, r0, tmp2
bgt LR(1, f) // Jump to process the reminder
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
VARDEF tmp0, r3
L(1)
subs len32tmp, len32tmp, #1
ldrsh tmp0, [ptr2], #2
ldrsh tmp1, [ptr1], #2
beq LR(2, f)
L(0)
smlabb r0, tmp0, tmp1, r0
ldrsh tmp0, [ptr2], #2
ldrsh tmp1, [ptr1], #2
subs len32tmp, len32tmp, #1
bgt LR(0, b)
L(2)
smlabb r0, tmp0, tmp1, r0
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
VARDEF len64, r4
VARDEF len64tmp, lr
VARDEF ptr00, r2
VARDEF ptr01, r3
VARDEFD val0, d0
VARDEFD val1, d1
VARDEFD val2, d2
VARDEFD val3, d3
VARDEFQ mul0, q2
VARDEFD mul0_lo, d4
VARDEFD mul0_hi, d5
VARDEFQ mul1, q3
VARDEFD mul1_lo, d6
VARDEFD mul1_hi, d7
VARDEFQ accu0, q4
VARDEFD accu0_lo, d8
VARDEFD accu0_hi, d9
VARDEFQ accu1, q5
VARDEFD accu1_lo, d10
VARDEFD accu1_hi, d11
.globl SYM(SKP_Silk_inner_prod16_aligned_64)
SYM(SKP_Silk_inner_prod16_aligned_64):
stmdb sp!, {r4-r10, fp, ip, lr}
vpush {q0-q7}
add fp, sp, #164
mov len64, r2
mov ptr00, r0
mov ptr01, r1
mov r0, #0 /*Output*/
mov r1, #0
// USE SL8D, SI4D
L(2)
cmp len64, #24
and len64tmp, len64, #0x7
blt LR(3, f)
vld1.16 {val0, val1}, [ptr00]!
vld1.16 {val2, val3}, [ptr01]!
vmov accu0_lo, r0, r1
vmov accu0_hi, r0, r1
vmov accu1, accu0
sub len64, len64, #16
L(0)
vmull.s16 mul0, val0, val2
vmull.s16 mul1, val1, val3
vld1.16 {val0, val1}, [ptr00]!
subs len64, len64, #8
//vqadd.s32 mul0, mul0, mul1
vld1.16 {val2, val3}, [ptr01]!
vaddw.s32 accu0, accu0, mul0_lo
vaddw.s32 accu1, accu1, mul0_hi
vaddw.s32 accu0, accu0, mul1_lo
vaddw.s32 accu1, accu1, mul1_hi
bge LR(0, b)
vmull.s16 mul0, val0, val2
vmull.s16 mul1, val1, val3
//vqadd.s32 mul0, mul0, mul1
vaddw.s32 accu0, accu0, mul0_lo
vaddw.s32 accu1, accu1, mul0_hi
vaddw.s32 accu0, accu0, mul1_lo
vaddw.s32 accu1, accu1, mul1_hi
vqadd.s64 accu0, accu0, accu1
vqadd.s64 accu0_lo, accu0_lo, accu0_hi
vmov r0, r1, accu0_lo
cmp len64tmp, #0 // Check if length%4 == 0
bgt LR(1, f) // Jump to process the reminder
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
VARDEFQ mul2, q1
VARDEFD mul2_lo, d2
VARDEFD mul2_hi, d3
VARDEFQ accu2, q2
VARDEFD accu2_lo, d4
VARDEFD accu2_hi, d5
VARDEFQ accu3, q3
// USE SL4D, SI4D
L(3)
cmp len64, #12
and len64tmp, len64, #0x3
movlt len64tmp, len64 // if length is not enough for SIMD.
blt LR(1, f)
vld1.16 val0, [ptr00]!
vld1.16 val1, [ptr01]!
vmov accu2_lo, r0, r1
vmov accu2_hi, r0, r1
vmov accu3, accu2
sub len64, len64, #8
L(0)
vmull.s16 mul2, val0, val1
vld1.16 val0, [ptr00]!
subs len64, len64, #4
vaddw.s32 accu2, accu2, mul2_lo
vld1.16 val1, [ptr01]!
vaddw.s32 accu3, accu3, mul2_hi
bge LR(0, b)
vmull.s16 mul2, val0, val1
vaddw.s32 accu2, accu2, mul2_lo
vaddw.s32 accu3, accu3, mul2_hi
vqadd.s64 accu2, accu2, accu3
vqadd.s64 accu2_lo, accu2_lo, accu2_hi
vmov r0, r1, accu2_lo
cmp len64tmp, #0
bgt LR(1, f)
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
VARDEF val4, r4
VARDEF val5, r5
L(1)
subs len64tmp, len64tmp, #1
ldrsh val4, [ptr00], #2
ldrsh val5, [ptr01], #2
beq LR(2, f)
L(0)
smlalbb r0, r1, val4, val5
ldrsh val4, [ptr00], #2
ldrsh val5, [ptr01], #2
subs len64tmp, len64tmp, #1
bgt LR(0, b)
L(2)
smlalbb r0, r1, val4, val5
vpop {q0-q7}
ldmia sp!, {r4-r10, fp, ip, pc}
#elif EMBEDDED_ARM >=5
/*
* SKP_Silk_inner_prod_aligned(val1_16bit[], val2_16bit[], len)
*
* Known issue:
* 1. val1_16bit and val2_16bit needs to be 16bit aligned.
* 2. result is in 32bit, no saturation, wrap around instead.
*/
VARDEF sum, r0
VARDEF val_p1, r1
VARDEF val_p2, r2
VARDEF len, r3
VARDEF val1, r4
VARDEF val2, r5
VARDEF val3, r6
#ifdef IPHONE
VARDEF val4, r8
VARDEF tmp, sb
VARDEF val5, sl
VARDEF val6, _r7
VARDEF val7, lr
VARDEF val8, ip
#else
VARDEF val4, _r7
VARDEF tmp, r8
VARDEF val5, sb
VARDEF val6, sl
VARDEF val7, lr
VARDEF val8, ip
#endif
.globl SYM(SKP_Silk_inner_prod_aligned)
SYM(SKP_Silk_inner_prod_aligned):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
cmp r2, #14
blt LR(9, f)/*LenLessThan14*/
ands tmp, r2, #1 /*check if len is a even number*/
mov len, r2
mov val_p2, r0
mov sum, #0
beq LR(0, f)/*LenEven*/
ldrsh val3, [val_p1], #2
ldrsh val4, [val_p2], #2
sub len, len, #1
smulbb sum, val3, val4
/*LenEven:*/
L(0)
ands val1, val_p1, #2 /*Check if val_p1 is LR(4, B) aligned.*/
bgt LR(1, f)/*R1Odd*/
ands val2, val_p2, #2 /*Check if val_p2 is LR(4, B) aligned*/
bgt LR(2, f)/*R2Odd*/
/*R1R2Even:*/
ands tmp, len, #3
beq LR(4, f)/*Len4*/
sub len, len, #2
ldr val1, [val_p1], #4
ldr val2, [val_p2], #4
SKP_SMLAD sum, val1, val2, sum
L(4)/*Len4:*/
ands tmp, len, #7
beq LR(8, f)/*Len8*/
ldmia val_p1!, {val1, val3}
ldmia val_p2!, {val2, val4}
sub len, len, #4
SKP_SMLAD sum, val1, val2, sum
SKP_SMLAD sum, val3, val4, sum
L(8)/*Len8:*/
ldmia val_p1!, {val1, val3, val5, val7}
ldmia val_p2!, {val2, val4, val6, val8}
L(0)
subs len, len, #8
SKP_SMLAD sum, val1, val2, sum
SKP_SMLAD sum, val3, val4, sum
SKP_SMLAD sum, val5, val6, sum
SKP_SMLAD sum, val7, val8, sum
ldmgtia val_p1!, {val1, val3, val5, val7}
ldmgtia val_p2!, {val2, val4, val6, val8}
bgt LR(0, b)
ldmia sp!, {r4-r10, fp, ip, pc}
L(2)/*R2Odd:*/
ands tmp, len, #3
beq LR(6, f)/*Len4R2Odd*/
ldr val1, [val_p1], #4
ldrsh val3, [val_p2], #2
ldrsh val4, [val_p2], #2 /*make val_p2 even*/
sub len, len, #2
smlabb sum, val1, val3, sum
smlatb sum, val1, val4, sum
L(6)/*Len4R2Odd:*/
sub len, len, #4
ldrsh tmp, [val_p2], #2 /*make val_p2 even*/
ldmia val_p1!, {val1, val3}
ldmia val_p2!, {val2, val4}
mov tmp, tmp, lsl #16
L(0)
subs len, len, #4
smlabt sum, val1, tmp, sum
smlatb sum, val1, val2, sum
smlabt sum, val3, val2, sum
smlatb sum, val3, val4, sum
mov tmp, val4
ldmia val_p1!, {val1, val3}
ldmia val_p2!, {val2, val4}
bgt LR(0, b)
smlabt sum, val1, tmp, sum
smlatb sum, val1, val2, sum
smlabt sum, val3, val2, sum
smlatb sum, val3, val4, sum
ldmia sp!, {r4-r10, fp, ip, pc}
L(1)/*R1Odd:*/
ands val2, val_p2, #2 /*Check if val_p2 is LR(4, B) aligned*/
bgt LR(3, f)/*R1R2Odd*/
ands tmp, len, #3
beq LR(5, f)/*Len4R1Odd*/
ldrsh val1, [val_p1], #2
ldrsh val2, [val_p1], #2
ldr val3, [val_p2], #4 /*make val_p2 even*/
sub len, len, #2
smlabb sum, val1, val3, sum
smlabt sum, val2, val3, sum
L(5)/*Len4R1Odd:*/
sub len, len, #4
ldrsh tmp, [val_p1], #2 /*make val_p2 even*/
ldmia val_p1!, {val1, val3}
ldmia val_p2!, {val2, val4}
mov tmp, tmp, lsl #16
L(0)
subs len, len, #4
smlatb sum, tmp, val2, sum
smlabt sum, val1, val2, sum
smlatb sum, val1, val4, sum
smlabt sum, val3, val4, sum
mov tmp, val3
ldmia val_p1!, {val1, val3}
ldmia val_p2!, {val2, val4}
bgt LR(0, b)
smlatb sum, tmp, val2, sum
smlabt sum, val1, val2, sum
smlatb sum, val1, val4, sum
smlabt sum, val3, val4, sum
ldmia sp!, {r4-r10, fp, ip, pc}
L(3)/*R1R2Odd:*/
sub len, len, #4
ldrsh val3, [val_p1], #2
ldrsh val4, [val_p2], #2
ldr val1, [val_p1], #4
ldr val2, [val_p2], #4
smlabb sum, val3, val4, sum
L(0)
subs len, len, #2
SKP_SMLAD sum, val1, val2, sum
ldr val1, [val_p1], #4
ldr val2, [val_p2], #4
bgt LR(0, b)
ldrsh val3, [val_p1], #2
ldrsh val4, [val_p2], #2
SKP_SMLAD sum, val1, val2, sum
smlabb sum, val3, val4, sum
ldmia sp!, {r4-r10, fp, ip, pc}
L(9)/*LenLessThan14:*/
mov len, r2
mov val_p2, r0
mov sum, #0
L(0)
ldrsh val1, [val_p1], #2
ldrsh val2, [val_p2], #2
subs len, len, #1
smlabb sum, val1, val2, sum
bgt LR(0, b)
ldmia sp!, {r4-r10, fp, ip, pc}
/*
* SKP_Silk_inner_prod16_aligned_64(val1_16bit[], val2_16bit[], len)
*
* Known issue:
* 1. val1_16bit and val2_16bit needs to be 16bit aligned.
* 2. result is in 64bit.
*/
// only redefine those registers.
VARDEF sumLo, r0
VARDEF sumHi, r1
#ifdef IPHONE
VARDEF val_p3, sl
VARDEF val_5, sb
VARDEF val_6, _r7
VARDEF val_7, lr
VARDEF val_8, ip
#else
VARDEF val_p3, sb
VARDEF val_5, r8
VARDEF val_6, sl
VARDEF val_7, lr
VARDEF val_8, ip
#endif
.globl SYM(SKP_Silk_inner_prod16_aligned_64)
SYM(SKP_Silk_inner_prod16_aligned_64):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
cmp r2, #14
blt LR(9, f)/*LenLessThan14_64*/
ands tmp, r2, #1 /*check if len is a even number*/
mov len, r2
mov val_p2, r0
mov val_p3, r1
mov sumLo, #0
mov sumHi, #0
beq LR(0, f)/*LenEven64*/
ldrsh val3, [val_p3], #2
ldrsh val4, [val_p2], #2
sub len, len, #1
smlalbb sumLo, sumHi, val3, val4
L(0)/*LenEven64:*/
ands val1, val_p3, #2 /*Check if val_p3 is LR(4, B) aligned.*/
bgt LR(1, f)/*R1Odd64*/
ands val2, val_p2, #2 /*Check if val_p2 is LR(4, B) aligned*/
bgt LR(2, f)/*R2Odd64*/
/*R1R2Even64:*/
ands tmp, len, #3
beq LR(4, f)/*Len464*/
sub len, len, #2
ldr val1, [val_p3], #4
ldr val2, [val_p2], #4
SKP_SMLALD sumLo, sumHi, val1, val2
L(4)/*Len464:*/
ands tmp, len, #7
beq LR(8, f)/*Len864*/
sub len, len, #4
ldmia val_p3!, {val1, val3}
ldmia val_p2!, {val2, val4}
SKP_SMLALD sumLo, sumHi, val1, val2
SKP_SMLALD sumLo, sumHi, val3, val4
L(8)/*Len864:*/
ldmia val_p3!, {val1, val3, val_5, val_7}
ldmia val_p2!, {val2, val4, val_6, val_8}
L(0)
subs len, len, #8
SKP_SMLALD sumLo, sumHi, val1, val2
SKP_SMLALD sumLo, sumHi, val3, val4
SKP_SMLALD sumLo, sumHi, val_5, val_6
SKP_SMLALD sumLo, sumHi, val_7, val_8
ldmgtia val_p3!, {val1, val3, val_5, val_7}
ldmgtia val_p2!, {val2, val4, val_6, val_8}
bgt LR(0, b)
ldmia sp!, {r4-r10, fp, ip, pc}
L(2)/*R2Odd64:*/
sub len, len, #2
sub val_p2, val_p2, #2 /*make val_p2 even*/
ldr val1, [val_p3], #4
ldr val3, [val_p2], #4
ldr val2, [val_p2], #4
L(0)
subs len, len, #2
smlalbt sumLo, sumHi, val1, val3
smlaltb sumLo, sumHi, val1, val2
mov val3, val2
ldr val1, [val_p3], #4
ldr val2, [val_p2], #4
bgt LR(0, b)
smlalbt sumLo, sumHi, val1, val3
smlaltb sumLo, sumHi, val1, val2
ldmia sp!, {r4-r10, fp, ip, pc}
L(1)/*R1Odd64:*/
ands val2, r2, #2 /*Check if val_p2 is LR(4, B) aligned*/
bgt LR(3, f)/*R1R2Odd64*/
sub len, len, #2
sub val_p3, val_p3, #2 /*make val_p3 even*/
ldr val3, [val_p3], #4
ldr val1, [val_p3], #4
ldr val2, [val_p2], #4
L(0)
subs len, len, #2
smlaltb sumLo, sumHi, val3, val2
smlalbt sumLo, sumHi, val1, val2
mov val3, val1
ldr val1, [val_p3], #4
ldr val2, [val_p2], #4
bgt LR(0, b)
smlaltb sumLo, sumHi, val3, val2
smlalbt sumLo, sumHi, val1, val2
ldmia sp!, {r4-r10, fp, ip, pc}
L(3)/*R1R2Odd64:*/
sub len, len, #4
ldrsh val3, [val_p3], #2
ldrsh val4, [val_p2], #2
ldr val1, [val_p3], #4
ldr val2, [val_p2], #4
smlalbb sumLo, sumHi, val3, val4
L(0)
subs len, len, #2
SKP_SMLALD sumLo, sumHi, val1, val2
ldr val1, [val_p3], #4
ldr val2, [val_p2], #4
bgt LR(0, b)
ldrsh val3, [val_p3], #2
ldrsh val4, [val_p2], #2
SKP_SMLALD sumLo, sumHi, val1, val2
smlalbb sumLo, sumHi, val3, val4
ldmia sp!, {r4-r10, fp, ip, pc}
L(9)/*LenLessThan14_64:*/
mov len, r2
mov val_p2, r0
mov val_p3, r1
mov sumLo, #0
mov sumHi, #0
L(0)
ldrsh val1, [val_p3], #2
ldrsh val2, [val_p2], #2
subs len, len, #1
smlalbb sumLo, sumHi, val1, val2
bgt LR(0, b)
ldmia sp!, {r4-r10, fp, ip, pc}
#endif
END
#endif
|
AgoraIO-Community/Solo
| 3,564
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_resampler_private_IIR_FIR_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
VARDEF ind, r4
VARDEF tab1, r5
VARDEF tab2, r6
VARDEF tab3, _r7
VARDEF val1, r8
VARDEF val2, sb
VARDEF val3, r2
VARDEF val4, r3
VARDEF tmp1, sl
VARDEF tmp2, r2
VARDEF tmp3, r3
VARDEF tmp4, ip
VARDEF out, sl
.set sp_max_i, 0
.set sp_inc, 4
EXTERN SYM(SKP_Silk_resampler_frac_FIR_144_alt)
.globl SYM(SKP_Silk_resampler_private_IIR_FIR_INTERPOL)
SYM(SKP_Silk_resampler_private_IIR_FIR_INTERPOL):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #8
str r2, [sp, #sp_max_i]
str r3, [sp, #sp_inc]
cmp r2, #0
mov tmp3, #0xFF00
mov ind, #0
ble LR(1, f)
add tmp3, tmp3, #0xFF
L(0)
ldr tmp1, TABLE(L0, =SKP_Silk_resampler_frac_FIR_144_alt)
and tmp3, ind, tmp3
mov tmp2, #144
mov tmp4, ind, asr #16
smulwb tmp2, tmp3, tmp2
add tmp1, tmp1, tmp2, lsl #3
add tmp1, tmp1, tmp2, lsl #2
add tmp4, r1, tmp4, lsl #1
ldmia tmp1, {tab1, tab2, tab3}
ldrsh val1, [tmp4], #2
ldrsh val2, [tmp4], #2
ldrsh val3, [tmp4], #2
ldrsh val4, [tmp4], #2
smulbb out, val1, tab1
smlabt out, val2, tab1, out
ldrsh val1, [tmp4], #2
ldrsh val2, [tmp4]
smlabb out, val3, tab2, out
smlabt out, val4, tab2, out
ldr r2, [sp, #sp_max_i]
ldr r3, [sp, #sp_inc]
smlabb out, val1, tab3, out
smlabt out, val2, tab3, out
add ind, ind, r3
adds out, out, #1<<14
mov tmp3, #0xFF00
#ifdef _WINRT
bvc LR(2, f)
mvn out, #0x80000000
b LR(3, f)
L(2)
qadd out, out, out
L(3)
#else
mvnvs out, #0x80000000
qaddvc out, out, out
#endif
add tmp3, tmp3, #0xFF
mov out, out, asr #16
cmp ind, r2
strh out, [r0], #2
blt LR(0, b)
L(1)
add sp, sp, #8
ldmia sp!, {r4-r10, fp, ip, pc}
L(L0)
DCD SYM(SKP_Silk_resampler_frac_FIR_144_alt)
END
#endif
#endif
|
AgoraIO-Community/Solo
| 2,966
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_sigm_Q15_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=4
VARDEF ptr_slope, r6
VARDEF ptr_LUT, _r7
VARDEF in_Q5, r1
VARDEF ind, r2
VARDEF val_slope, r5
VARDEF val_PUT, r4
VARDEF in_Q5_tmp, r3
.globl SYM(SKP_Silk_sigm_Q15)
SYM(SKP_Silk_sigm_Q15):
stmdb sp!, {r4-r7, fp, ip, lr}
add fp, sp, #24
cmp r0, #0
ldr ptr_slope, TABLE(L0, =SKP_Silk_sigm_tab)
mov in_Q5, r0
rsblt in_Q5, r0, #0
mov r0, #32768
addlt ptr_slope, ptr_slope, #24
movlt r0, #1
add ptr_LUT, ptr_slope, #12 /*sigm_LUT_pos_Q15*/
cmp in_Q5, #192 /*6*32*/
sub r0, r0, #1
bge LR(1, f)
mov ind, in_Q5, asr #5 /*ind*/
mov ind, ind, lsl #1
and in_Q5_tmp, in_Q5, #0x1F
ldrsh val_slope, [ptr_slope, ind] /*sigm_LUT_slope_Q10*/
ldrsh val_PUT, [ptr_LUT, ind] /*sigm_LUT_pos/neg_Q15*/
mla r0, val_slope, in_Q5_tmp, val_PUT
L(1)
ldmia sp!, {r4-r7, fp, ip, pc}
L(L0)
DCD SYM(SKP_Silk_sigm_tab)
SKP_TABLE SKP_Silk_sigm_tab, 2
DCW 237, 153, 73, 30, 12, 7, \
16384, 23955, 28861, 31213, 32178, 32548, \
-237, -153, -73, -30, -12, -7, \
16384, 8812, 3906, 1554, 589, 219
END
#endif
#endif
|
AgoraIO-Community/Solo
| 5,894
|
JC1_SDK_SRC_ARM/src/libSATECodec/SKP_Silk_ana_filt_bank_1_arm.S
|
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM>=5
/*
* void SKP_Silk_ana_filt_bank_1(
* const SKP_int16 *in, I: Input signal [N]
* SKP_int32 *S, I/O: State vector [2]
* SKP_int16 *outL, O: Low band [N/2]
* SKP_int16 *outH, O: High band [N/2]
* SKP_int32 *scratch, I: Scratch memory [3*N/2]
* const SKP_int32 N I: Number of input samples
* )
*/
VARDEF ptr_in_lo, r0
VARDEF ptr_in_hi, r3
VARDEF val_in_lo, sb
VARDEF val_in_hi, sl
VARDEF ptr_scratch, r4
VARDEF ptr_scratch_N, r1
VARDEF ptr_scratch_halfN, r2
VARDEF idx_k, ip
VARDEF val_N, r8
VARDEF val_halfN, r8
VARDEF val_scratch1, r5
VARDEF val_scratch2, r6
VARDEF ptr_out_lo, r5
VARDEF ptr_out_hi, r6
VARDEF ptr_s, _r7
VARDEF val_const1, r2
VARDEF val_const2, ip // 0x03FF F800
VARDEF val_const3, sl // 0x0000 7FFF
VARDEF val_const4, lr // 0xFFFF 8000
VARDEF idx_k2, r8
VARDEF ptr_scratch_halfN_2, r3
VARDEF val_scratch3, r0
VARDEF val_scratch4, r1
VARDEF out_tmpla, sb
VARDEF out_tmplb, r2
VARDEF out_tmpha, r0
VARDEF out_tmphb, _r7
.set halfN, 0
.set sp_ptr_out_lo, 4
.set sp_ptr_out_hi, 8
EXTERN SYM(SKP_Silk_allpass_int)
.globl SYM(SKP_Silk_ana_filt_bank_1)
SYM(SKP_Silk_ana_filt_bank_1):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
sub sp, sp, #12
.set arg_scratch, 52
.set arg_N, 56
ldr ptr_scratch, [sp, #arg_scratch]
ldr val_N, [sp, #arg_N]
str r2, [sp, #sp_ptr_out_lo]
str r3, [sp, #sp_ptr_out_hi]
mov ptr_s, r1
mov val_halfN, val_N, asr #1
sub idx_k, val_halfN, #1
add ptr_in_hi, ptr_in_lo, #2
str val_halfN, [sp, #halfN]
ldrsh val_in_lo, [ptr_in_lo], #4
ldrsh val_in_hi, [ptr_in_hi], #4
add ptr_scratch_N, ptr_scratch, val_halfN, lsl #3
add ptr_scratch_halfN, ptr_scratch, val_halfN, lsl #2
L(0)
mov val_scratch1, val_in_lo, lsl #10
mov val_scratch2, val_in_hi, lsl #10
ldrsh val_in_lo, [ptr_in_lo], #4
ldrsh val_in_hi, [ptr_in_hi], #4
subs idx_k, idx_k, #1
str val_scratch1, [ptr_scratch_N], #4
str val_scratch2, [ptr_scratch_halfN], #4
bgt LR(0, b)
mov val_scratch1, val_in_lo, lsl #10
mov val_scratch2, val_in_hi, lsl #10
str val_scratch1, [ptr_scratch_N], #4
str val_scratch2, [ptr_scratch_halfN], #4
mov val_const1, #0x1500
add r0, ptr_scratch, val_halfN, lsl #2
add r1, ptr_s, #4
add val_const1, val_const1, #0x12
mov r3, ptr_scratch
bl SYM(SKP_Silk_allpass_int)
mov val_const1, #0x5000
add r0, ptr_scratch, val_halfN, lsl #3
mov r1, ptr_s
add val_const1, val_const1, #0x8F
add r3, ptr_scratch, val_halfN, lsl #2
bl SYM(SKP_Silk_allpass_int)
mvn val_const2, #0x80000000
add ptr_scratch_halfN_2, ptr_scratch, val_halfN, lsl #2
mov val_const3, val_const2, asr #16
rsb val_const4, val_const3, #0
mov idx_k2, val_halfN
mov val_const2, val_const3, lsl #11
ldr ptr_out_lo, [sp, #sp_ptr_out_lo]
ldr ptr_out_hi, [sp, #sp_ptr_out_hi]
L(1)
ldr val_scratch3, [ptr_scratch], #4
ldr val_scratch4, [ptr_scratch_halfN_2], #4
add out_tmpla, val_scratch3, val_scratch4
sub out_tmpha, val_scratch3, val_scratch4
add out_tmplb, out_tmpla, #1024
add out_tmphb, out_tmpha, #1024
mov out_tmplb, out_tmplb, asr #11
mov out_tmphb, out_tmphb, asr #11
strh out_tmplb, [ptr_out_lo], #2
strh out_tmphb, [ptr_out_hi], #2
#ifdef _WINRT
cmp out_tmpla, val_const2
ble LR(2, f)
strh val_const3, [ptr_out_lo, #-2]
L(2)
cmn out_tmpla, val_const2
bge LR(2, f)
strh val_const4, [ptr_out_lo, #-2]
L(2)
cmp out_tmpha, val_const2
ble LR(2, f)
strh val_const3, [ptr_out_hi, #-2]
L(2)
cmn out_tmpha, val_const2
bge LR(2, f)
strh val_const4, [ptr_out_hi, #-2]
L(2)
#else
cmp out_tmpla, val_const2
strgth val_const3, [ptr_out_lo, #-2]
cmn out_tmpla, val_const2
strlth val_const4, [ptr_out_lo, #-2]
cmp out_tmpha, val_const2
strgth val_const3, [ptr_out_hi, #-2]
cmn out_tmpha, val_const2
strlth val_const4, [ptr_out_hi, #-2]
#endif
subs idx_k2, idx_k2, #1
bgt LR(1, b)
add sp, sp, #12
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
|
AGProjects/python-sipsimple
| 1,487
|
deps/pjsip/pjlib/src/pj/compat/longjmp_i386.S
|
/* longjmp for i386.
Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public License as
published by the Free Software Foundation; either version 2 of the
License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with the GNU C Library; see the file COPYING.LIB. If not,
write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#define _ASM
#define _SETJMP_H
#define PJ_LINUX_KERNEL 1
#include <pj/compat/setjmp.h>
.global __longjmp
.type __longjmp,%function
.align 4
__longjmp:
movl 4(%esp), %ecx /* User's jmp_buf in %ecx. */
movl 8(%esp), %eax /* Second argument is return value. */
/* Save the return address now. */
movl (JB_PC*4)(%ecx), %edx
/* Restore registers. */
movl (JB_BX*4)(%ecx), %ebx
movl (JB_SI*4)(%ecx), %esi
movl (JB_DI*4)(%ecx), %edi
movl (JB_BP*4)(%ecx), %ebp
movl (JB_SP*4)(%ecx), %esp
/* Jump to saved PC. */
jmp *%edx
.size __longjmp,.-__longjmp
|
AGProjects/python-sipsimple
| 2,073
|
deps/pjsip/pjlib/src/pj/compat/setjmp_i386.S
|
/* setjmp for i386, ELF version.
Copyright (C) 1995, 1996, 1997, 2000, 2001 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
#define _ASM
#define _SETJMP_H
#define PJ_LINUX_KERNEL 1
#include <pj/compat/setjmp.h>
.global __sigsetjmp
.type __sigsetjmp,%function
.align 4
__sigsetjmp:
movl 4 (%esp), %eax
/* Save registers. */
movl %ebx, (0 *4)(%eax)
movl %esi, (1 *4)(%eax)
movl %edi, (2 *4)(%eax)
/* Save SP as it will be after we return. */
leal 4(%esp), %ecx
movl %ecx, (4 *4)(%eax)
/* Save PC we are returning to now. */
movl 0(%esp), %ecx
movl %ecx, (5 *4)(%eax)
/* Save caller's frame pointer. */
movl %ebp, (3 *4)(%eax)
/* Make a tail call to __sigjmp_save; it takes the same args. */
#ifdef __PIC__
/* We cannot use the PLT, because it requires that %ebx be set, but
we can't save and restore our caller's value. Instead, we do an
indirect jump through the GOT, using for the temporary register
%ecx, which is call-clobbered. */
call .Lhere
.Lhere:
popl %ecx
addl $_GLOBAL_OFFSET_TABLE_+[.- .Lhere ], %ecx
movl __sigjmp_save @GOT (%ecx), %ecx
jmp *%ecx
#else
jmp __sigjmp_save
#endif
.size __sigsetjmp,.-__sigsetjmp
|
agranlund/wolf
| 2,241
|
z80/main.s
|
; Wolfenstein 3D for Gameboy Color
; (c) 2017, Anders Granlund
; www.happydaze.se
;
; This program is free software; you can redistribute it and/or
; modify it under the terms of the GNU General Public License
; as published by the Free Software Foundation; either version 2
; of the License, or (at your option) any later version.
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
.include "defines.i"
.BANK 0 SLOT SLOT_ROM
;
; Main entry point
;
.ORG $150
.SECTION "Main" SEMIFREE
MAIN:
; compatability check
ld a, (g_console_type)
or a
jp z, display_compatability_error
; setup
call gfx_init
call snd_init
; clear palette, map & chr
call gfx_pal_clear
call gfx_map_clear
call gfx_chr_clear
; no password
xor a
ld (pwd_start), a
; no cheats
xor a
ld (cheat_godmode), a
ld (cheat_guns), a
ld a, 1
ld (start_floor), a
; hold start to skip directly into game
;call sys_update_joypad
;ld a, (g_joypad_status)
;bit 3, a
;jr nz, +
;jr +
; intro
call intro
; main menu
- call title
; game
+ call game
jr -
display_compatability_error:
ld a, :gbc_only_tile_data
ld ($2000), a
ld hl, $8000
ld de, gbc_only_tile_data
ld c, 127
call gfx_chr_copy ; copy chr
ld hl, $9800
ld de, gbc_only_map_data
call gfx_map_copy_20x18 ; copy map
ld a, %11100100 ; copy palette
ldh (R_BGP), a
ld a, %10010001 ; enable bg
ldh (R_LCDC), a
- halt
jr -
.ENDS
; Data for compatability warning
.BANK 3 SLOT SLOT_ROM_BANKED
.SECTION "gbc_only_data" SEMIFREE
.INCLUDE "gfx/gbc_only.s"
.ENDS
|
agranlund/wolf
| 27,685
|
z80/screens.s
|
; Wolfenstein 3D for Gameboy Color
; (c) 2017, Anders Granlund
; www.happydaze.se
;
; This program is free software; you can redistribute it and/or
; modify it under the terms of the GNU General Public License
; as published by the Free Software Foundation; either version 2
; of the License, or (at your option) any later version.
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
.INCLUDE "defines.i"
.RAMSECTION "password_vars" BANK 0 SLOT SLOT_RAM
vpw_buf DS 6
vpw_len DS 1
vpw_xpos DS 1
vpw_ypos DS 1
.ENDS
.BANK 0 SLOT SLOT_ROM
.ORG $200
.SECTION "Code_Screens" SEMIFREE
;
; Common screen init
; hl = palette
;
msg_screen_init:
push de
push hl
ld ($2000), a
; init all palettes
pop hl
ld bc, 8
push hl
call gfx_pal_copy_bg
pop hl
ld bc, 8
call gfx_pal_copy_obj
; init screen and interrupts
di
xor a
ldh (R_IF), a
ldh (R_IE), a
ld a, %10010001
ldh (R_LCDC), a
; copy map data
pop de
ld hl, $9800
call gfx_map_copy_20x18
; copy chr data
ld a, :msg_chr
ld ($2000), a
ld hl, $8000
ld de, msg_chr
ld c, 103
call gfx_chr_copy
ret
;
; Fade in
; hl = source pal
; de = dest pal
;
msg_screen_fade:
xor a
- push af
push hl
push de
ld bc, 4
call gfx_pal_fade_bg
ld bc, 1
call sys_delay
call snd_update
pop de
pop hl
pop af
add 4
cp 129
jr c, -
ret
;
; Game over
;
gameover:
call snd_stop_music
call snd_stop_fx
ld a, :msg_map_gameover
ld de, msg_map_gameover
ld hl, PAL_RED
call msg_screen_init
; fade in
ld hl, PAL_RED
ld de, msg_pal
call msg_screen_fade
; wait for any key or timeout
ld de, 60 * 20
- push de
ld bc, 1
call sys_delay
call sys_update_joypad
pop de
ld a, (g_joypad_trigger)
and %00001111
jr nz, +
dec de
ld a, d
or e
jr nz, -
; fade out
+ ld hl, msg_pal
ld de, PAL_BLACK
call msg_screen_fade
ret
;
; Victory
;
victory:
call snd_stop_music
call snd_stop_fx
ld a, :msg_map_victory
ld de, msg_map_victory
ld hl, PAL_WHITE
call msg_screen_init
; fade in
ld hl, PAL_WHITE
ld de, msg_pal
call msg_screen_fade
; wait for any key or timeout
ld de, 60 * 20
- push de
ld bc, 1
call sys_delay
call sys_update_joypad
pop de
ld a, (g_joypad_trigger)
and %00001111
jr nz, +
dec de
ld a, d
or e
jr nz, -
; fade out
+ ld hl, msg_pal
ld de, PAL_BLACK
call msg_screen_fade
ret
;
; Elevator
;
elevator:
call snd_stop_music
call snd_stop_fx
ld a, :msg_map_elevator
ld de, msg_map_elevator
ld hl, PAL_BLACK
call msg_screen_init
; print floor number
ld a, (floor)
inc a
ld b, a
ld hl, $9830
- ldh a, (R_STAT)
and $02
jr nz, -
ld (hl), b
; print password
call elevator_print_password
; fade in
ld hl, PAL_BLACK
ld de, msg_pal
call msg_screen_fade
; kills
call elevator_delay
ld a, (stat_kill_ratio)
call elevator_print_kill_ratio
; treasures
call elevator_delay
ld a, (stat_bonus_ratio)
call elevator_print_bonus_ratio
; secrets
call elevator_delay
ld a, (stat_secret_ratio)
call elevator_print_secret_ratio
; GET PSYCHED!
call elevator_delay
call elevator_print_psyched
; wait for any key or timeout
ld de, 60 * 20
- push de
ld bc, 1
call sys_delay
call sys_update_joypad
call snd_update
pop de
ld a, (g_joypad_trigger)
and %00001111
jr nz, +
dec de
ld a, d
or e
;jr nz, -
jr -
; fade out
+ ld hl, msg_pal
ld de, PAL_BLACK
call msg_screen_fade
ret
;
; Elevator - delay
;
elevator_delay:
ld c, 60
- push bc
ld bc, 1
call sys_delay
call snd_update
pop bc
dec c
jr nz, -
ret
;
; Elevator - print psyched
;
elevator_print_psyched:
ld a, 1
call snd_play_fx
ld hl, $99E4
ld de, elevator_psyched_string
ld c, 12
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, (de)
ldi (hl), a
inc de
dec c
jr nz, -
ret
elevator_psyched_string:
.db 17, 15, 30, 0, 26, 29, 35, 13, 18, 15, 14, 40
;
; Elevator - print password
;
elevator_print_password:
ld hl, vpw_buf
ld a, (lives)
ldi (hl), a ; vpw_buf + 0 = lives
ld b, a
ld a, (floordone_next)
ldi (hl), a ; vpw_buf + 1 = floor
add b
ld b, a
ld a, (health)
ldi (hl), a ; vpw_buf + 2 = health
add b
ld b, a
ld a, (guns)
ldi (hl), a ; vpw_buf + 3 = guns
add b
ld b, a
ld a, (ammo)
ldi (hl), a ; vpw_buf + 4 = ammo
add b
ld (hl), a ; vpw_buf + 5 = checksum
ld hl, tempbuf
ld b, 0
ld a, (vpw_buf + 5) ; c1
sra a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 1) ; f1
and %00000010
or b
ld b, a
ld a, (vpw_buf + 0) ; l0
sla a
sla a
and %00000100
or b
ld b, a
ld a, (vpw_buf + 2) ; h5
sra a
sra a
and %00001000
or b
ld b, a
ld a, (vpw_buf + 1) ; f4
and %00010000
or b
ldi (hl), a ; tempbuf+0
ld b, 0
ld a, (vpw_buf + 4) ; a4
sra a
sra a
sra a
sra a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 0) ; l4
sra a
sra a
sra a
and %00000010
or b
ld b, a
ld a, (vpw_buf + 1) ; f3
sra a
and %00000100
or b
ld b, a
ld a, (vpw_buf + 1) ; f2
sla a
and %00001000
or b
ld b, a
ld a, (vpw_buf + 4) ; a0
sla a
sla a
sla a
sla a
and %00010000
or b
ldi (hl), a ; tempbuf+1
ld b, 0
ld a, (vpw_buf + 3) ; g2
sra a
sra a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 2) ; h1
and %00000010
or b
ld b, a
ld a, (vpw_buf + 3) ; g0
sla a
sla a
and %00000100
or b
ld b, a
ld a, (vpw_buf + 2) ; h6
sra a
sra a
sra a
and %00001000
or b
ld b, a
ld a, (vpw_buf + 4) ; a6
sra a
sra a
and %00010000
or b
ldi (hl), a ; tempbuf+2
ld b, 0
ld a, (vpw_buf + 2) ; h4
sra a
sra a
sra a
sra a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 0) ; l2
sra a
and %00000010
or b
ld b, a
ld a, (vpw_buf + 2) ; h2
and %00000100
or b
ld b, a
ld a, (vpw_buf + 3) ; g1
sla a
sla a
and %00001000
or b
ld b, a
ld a, (vpw_buf + 4) ; a2
sla a
sla a
and %00010000
or b
ldi (hl), a ; tempbuf+3
ld b, 0
ld a, (vpw_buf + 0) ; l3
sra a
sra a
sra a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 2) ; h0
sla a
and %00000010
or b
ld b, a
ld a, (vpw_buf + 5) ; c0
sla a
sla a
and %00000100
or b
ld b, a
ld a, (vpw_buf + 4) ; a3
and %00001000
or b
ld b, a
ld a, (vpw_buf + 1) ; f0
sla a
sla a
sla a
sla a
and %00010000
or b
ldi (hl), a ; tempbuf+4
ld b, 0
ld a, (vpw_buf + 5) ; c2
sra a
sra a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 4) ; a5
sra a
sra a
sra a
sra a
and %00000010
or b
ld b, a
ld a, (vpw_buf + 2) ; h3
sra a
and %00000100
or b
ld b, a
ld a, (vpw_buf + 0) ; l1
sla a
sla a
and %00001000
or b
ld b, a
ld a, (vpw_buf + 4) ; a1
sla a
sla a
sla a
and %00010000
or b
ld (hl), a ; tempbuf+5
; convert to chr
ld b, 6
ld de, tempbuf
- ld a, (de)
push de
ld e, a
ld d, 0
ld hl, password_val_to_chr
add hl, de
pop de
ld a, (hl)
ld (de), a
inc de
dec b
jr nz, -
; print to screen
ld de, tempbuf
ld hl, $98CB
ld b, 6
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, (de)
ldi (hl), a
inc de
dec b
jr nz, -
ret
;
; Elevator - print score
; de = score
;
elevator_print_score:
ld a, 1
push de
call snd_play_fx
pop de
ld bc, 10000
call sys_div_16x16 ; de = health/10000, bc = remainder
ld a, e
ld (tempbuf), a
ld d, b
ld e, c
ld bc, 1000
call sys_div_16x16 ; de = health/1000, bc = remainder
ld a, e
ld (tempbuf+1), a
ld d, b
ld e, c
ld bc, 100
call sys_div_16x16 ; de = health/100, bc = remainder
ld a, e
ld (tempbuf+2), a
ld d, b
ld e, c
ld bc, 10
call sys_div_16x16 ; de = health/10, bc = remainder
ld a, e
ld (tempbuf+3), a
ld a, c
ld (tempbuf+4), a
xor a
ld (tempbuf+5), a
ld (tempbuf+6), a
ld a, $1D
ld (tempbuf+8), a
ld a, $0D
ld (tempbuf+9), a
ld a, $19
ld (tempbuf+10), a
ld a, $1C
ld (tempbuf+11), a
ld a, $0F
ld (tempbuf+12), a
ld hl, $99E4
ld de, tempbuf+8
ld c, 5
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, (de)
ldi (hl), a
inc de
dec c
jr nz, -
ld hl, $99EA
ld de, tempbuf+1
ld b, 0
ld c, 6
-- ld a, (de)
ld b, $FF
add 1 ; tile = 1 + digit
++ push hl
push de
push af
- ldh a, (R_STAT)
and $02
jr nz, -
pop af
ld (hl), a
pop de
pop hl
inc de
inc hl
dec c
jr nz, --
ret
;
; Elevator - print ratio
; a = ratio
; hl = map addr
;
elevator_print_kill_ratio:
ld hl, $994F
jr elevator_print_ratio
elevator_print_bonus_ratio:
ld hl, $996F
jr elevator_print_ratio
elevator_print_secret_ratio:
ld hl, $998F
jr elevator_print_ratio
elevator_print_ratio:
push hl
push af
ld a, 1
call snd_play_fx
pop af
ld e, a
ld d, 0
ld bc, 100
call sys_div_16x16 ; de = health/100, bc = remainder
ld a, e
ld (tempbuf), a
ld d, b
ld e, c
ld bc, 10
call sys_div_16x16 ; de = health/10, bc = remainder
ld hl, tempbuf+1
ld a, e
ldi (hl), a
ld a, c
ldd (hl), a
dec hl
ld d, h
ld e, l
pop hl
ld b, 0
ld c, 3
-- ld a, (de)
or b
jr nz, +
ld a, c
cp 1
jr z, +
xor a ; blank tile = 0
jr ++
+ ld a, (de)
ld b, $FF
add 1 ; tile = 1 + digit
++ push hl
push de
push af
- ldh a, (R_STAT)
and $02
jr nz, -
pop af
ld (hl), a
pop de
pop hl
inc de
inc hl
dec c
jr nz, --
ret
;
; Cheat menu
;
cheatmenu:
ld a, :msg_map_cheat
ld de, msg_map_cheat
ld hl, PAL_RED
call msg_screen_init
call snd_update
xor a
ld (tempbuf+0), a ; menu position
ld b, $2C
call cheatmenu_draw_cursor
call cheatmenu_redraw
; fade in
ld hl, PAL_RED
ld de, msg_pal
call msg_screen_fade
; wait for any key or timeout
- ld bc, 1
call sys_delay
call snd_update
call sys_update_joypad
; up
ld a, (g_joypad_trigger)
bit 6, a
jr z, +
ld a, (tempbuf+0)
cp 0
jr z, +
ld b, 0
call cheatmenu_draw_cursor
dec a
ld (tempbuf+0), a
ld b, $2C
call cheatmenu_draw_cursor
; down
+ ld a, (g_joypad_trigger)
bit 7, a
jr z, +
ld a, (tempbuf+0)
cp 3
jr z, +
ld b, 0
call cheatmenu_draw_cursor
inc a
ld (tempbuf+0), a
ld b, $2C
call cheatmenu_draw_cursor
; start game
+ ld a, (g_joypad_trigger)
bit 3, a
jr nz, cheatmenu_startgame
bit 0, a
jr z, +
ld a, (tempbuf+0)
cp 3
jr nz, +
jr cheatmenu_startgame
; options
+ ld a, (tempbuf+0)
cp 0
call z, cheatmenu_handle_floor
ld a, (tempbuf+0)
cp 1
call z, cheatmenu_handle_godmode
ld a, (tempbuf+0)
cp 2
call z, cheatmenu_handle_guns
; refresh
call cheatmenu_redraw
jr -
; fadeout
cheatmenu_startgame:
call snd_stop_music
ld a, $1
call snd_play_fx
ld c, 1
- push bc
call snd_update
ld bc, 1
call sys_delay
pop bc
dec c
jr nz, -
ld a, 1
call snd_play_fx
+ ld hl, msg_pal
ld de, PAL_BLACK
call msg_screen_fade
ret
ret
cheatmenu_handle_floor:
ld a, (g_joypad_trigger)
and %00010001
jr z, ++
ld a, (start_floor)
inc a
cp 10
jr c, +
xor a
+ ld (start_floor), a
++ ld a, (g_joypad_trigger)
and %00100010
ret z
ld a, (start_floor)
dec a
cp 255
jr nz, +
ld a, 9
+ ld (start_floor), a
ret
cheatmenu_handle_godmode:
ld a, (g_joypad_trigger)
and %00110011
ret z
ld a, (cheat_godmode)
inc a
and 1
ld (cheat_godmode), a
ret
cheatmenu_handle_guns:
ld a, (g_joypad_trigger)
and %00110011
ret z
ld a, (cheat_guns)
inc a
and 1
ld (cheat_guns), a
ret
cheatmenu_redraw:
; floor
ld a, (start_floor)
inc a
ld b, a
ld hl, $98D0
- ldh a, (R_STAT)
and $02
jr nz, -
ld (hl), b
; godmode
ld hl, $9910
ld de, cheatmenu_string_no
ld a, (cheat_godmode)
or a
jr z, +
ld de, cheatmenu_string_yes
+ call cheatmenu_draw_string
; guns
ld hl, $9950
ld de, cheatmenu_string_no
ld a, (cheat_guns)
or a
jr z, +
ld de, cheatmenu_string_yes
+ call cheatmenu_draw_string
ret
cheatmenu_draw_string:
ld c, 3
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, (de)
ldi (hl), a
inc de
dec c
jr nz, -
ret
cheatmenu_draw_cursor:
push af
ld a, (tempbuf+0)
sla a
ld hl, cheatmenu_ypos
ld e, a
ld d, 0
add hl, de
ldi a, (hl)
ld h, (hl)
ld l, a
- ldh a, (R_STAT)
and $02
jr nz, -
ld (hl), b
pop af
ret
cheatmenu_string_yes:
.db 35, 15, 29
cheatmenu_string_no:
.db 24, 25, 0
cheatmenu_ypos:
.dw $98C1, $9901, $9941, $99A1
;
; Password screen
;
.EQU PASSWORD_CURSOR $27
password:
; load screen
ld a, :msg_map_password
ld de, msg_map_password
ld hl, PAL_RED
call msg_screen_init
call snd_update
; fade in
ld hl, PAL_RED
ld de, msg_pal
call msg_screen_fade
; init vars
xor a
ld hl, vpw_buf
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ld (vpw_len), a
ld (vpw_ypos), a
ld (vpw_xpos), a
; draw cursor
ld a, PASSWORD_CURSOR
call password_draw_cursor
; update sound & joypad
- ld bc, 1
call sys_delay
call snd_update
call sys_update_joypad
; update cursor
ld a, (g_joypad_trigger)
bit 6, a
call nz, password_up
bit 7, a
call nz, password_down
bit 4, a
call nz, password_right
bit 5, a
call nz, password_left
bit 0, a
call nz, password_a
bit 1, a
call nz, password_b
ld a, (vpw_len)
cp 6
jr z, password_try
jr -
password_try:
; lives (tempbuf+0)
ld b, 0
ld a, (vpw_buf + 0) ; l0
srl a
srl a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 5) ; l1
srl a
srl a
and %00000010
or b
ld b, a
ld a, (vpw_buf + 3) ; l2
sla a
and %00000100
or b
ld b, a
ld a, (vpw_buf + 4) ; l3
sla a
sla a
sla a
and %00001000
or b
ld b, a
ld a, (vpw_buf + 1) ; l4
sla a
sla a
sla a
and %00010000
or b
ld (tempbuf + 0), a
; floor (tempbuf+1)
ld b, 0
ld a, (vpw_buf + 4) ; f0
sra a
sra a
sra a
sra a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 0) ; f1
and %00000010
or b
ld b, a
ld a, (vpw_buf + 1) ; f2
sra a
and %00000100
or b
ld b, a
ld a, (vpw_buf + 1) ; f3
sla a
and %00001000
or b
ld b, a
ld a, (vpw_buf + 0) ; f4
and %00010000
or b
ld (tempbuf + 1), a
; health (tempbuf+2)
ld b, 0
ld a, (vpw_buf + 4) ; h0
sra a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 2) ; h1
and %00000010
or b
ld b, a
ld a, (vpw_buf + 3) ; h2
and %00000100
or b
ld b, a
ld a, (vpw_buf + 5) ; h3
sla a
and %00001000
or b
ld b, a
ld a, (vpw_buf + 3) ; h4
sla a
sla a
sla a
sla a
and %00010000
or b
ld b, a
ld a, (vpw_buf + 0) ; h5
sla a
sla a
and %00100000
or b
ld b, a
ld a, (vpw_buf + 2) ; h6
sla a
sla a
sla a
and %01000000
or b
ld (tempbuf + 2), a
; guns (tempbuf + 3)
ld b, 0
ld a, (vpw_buf + 2) ; g0
sra a
sra a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 3) ; g1
sra a
sra a
and %00000010
or b
ld b, a
ld a, (vpw_buf + 2) ; g2
sla a
sla a
and %00000100
or b
ld (tempbuf + 3), a
; ammo (tempbuf + 4)
ld b, 0
ld a, (vpw_buf + 1) ; a0
sra a
sra a
sra a
sra a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 5) ; a1
sra a
sra a
sra a
and %00000010
or b
ld b, a
ld a, (vpw_buf + 3) ; a2
sra a
sra a
and %00000100
or b
ld b, a
ld a, (vpw_buf + 4) ; a3
and %00001000
or b
ld b, a
ld a, (vpw_buf + 1) ; a4
sla a
sla a
sla a
sla a
and %00010000
or b
ld b, a
ld a, (vpw_buf + 5) ; a5
sla a
sla a
sla a
sla a
and %00100000
or b
ld b, a
ld a, (vpw_buf + 2) ; a6
sla a
sla a
and %01000000
or b
ld (tempbuf + 4), a
; checksum (tempbuf + 5)
ld b, 0
ld a, (vpw_buf + 4) ; c0
sra a
sra a
and %00000001
or b
ld b, a
ld a, (vpw_buf + 0) ; c1
sla a
and %00000010
or b
ld b, a
ld a, (vpw_buf + 5) ; c2
sla a
sla a
and %00000100
or b
ld (tempbuf + 5), a
; stop music
call snd_stop_music
call snd_update
; verify password
xor a
ld (pwd_start), a
ld hl, tempbuf
call password_verify
ld b, $A
cp 0
jr z, +
; valid password
ld a, 1
ld (pwd_start), a
ld b, $15
+ ld a, b
call snd_play_fx
ld c, 40
- push bc
call snd_update
ld bc, 1
call sys_delay
pop bc
dec c
jr nz, -
+ ld hl, msg_pal
ld de, PAL_BLACK
call msg_screen_fade
ret
password_verify:
push hl
xor a
add (hl) ; lives
inc hl
add (hl) ; floor
inc hl
add (hl) ; health
inc hl
add (hl) ; guns
inc hl
add (hl) ; ammo
inc hl
and %00000111
ld b, a ; b = calculated checksum
ld a, (hl) ; a = stored checksum
pop hl
cp b
jr z, +
xor a
ret
+ ldi a, (hl) ; lives
cp 10
jr c, +
xor a
ret
+ ldi a, (hl) ; floor
cp 10
jr c, +
xor a
ret
+ ldi a, (hl) ; health
cp 0
jr z, +
cp 101
jr c, ++
+ xor a
ret
++ ldi a, (hl) ; guns
ldi a, (hl) ; ammo
cp 100
jr c, +
xor a
ret
+ ld a, 1
ret
password_draw:
; translate
ld hl, tempbuf
ld a, $25
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ld hl, tempbuf
ld de, vpw_buf
ld a, (vpw_len)
cp 0
jr z, +
ld b, a
- push hl
push bc
ld a, (de)
inc de
ld hl, password_val_to_chr
ld c, a
ld b, 0
add hl, bc
ld a, (hl)
pop bc
pop hl
ldi (hl), a
dec b
jr nz, -
; print
+ ld hl, $98E7
ld de, tempbuf
ld b, 6
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, (de)
ldi (hl), a
inc de
dec b
jr nz, -
ret
password_val_to_chr:
.DB $0C, $0D, $0E, $10, $11, $12, $13, $14
.DB $15, $16, $17, $18, $1A, $1B, $1C, $1D
.DB $1E, $20, $21, $22, $23, $24, $01, $02
.DB $03, $04, $05, $06, $07, $08, $09, $0A
password_draw_cursor:
push af
ld hl, $9942
ld a, (vpw_ypos)
sla a
sla a
sla a
sla a
sla a
sla a
ld e, a
ld a, (vpw_xpos)
sla a
add e
ld e, a
ld d, 0
add hl, de
pop af
ld b, a
- ldh a, (R_STAT)
and $02
jr nz, -
ld (hl), b
ret
password_up:
push af
ld a, 0
call password_draw_cursor
ld a, (vpw_ypos)
dec a
and 3
ld (vpw_ypos), a
ld a, PASSWORD_CURSOR
call password_draw_cursor
pop af
ret
password_down:
push af
ld a, 0
call password_draw_cursor
ld a, (vpw_ypos)
inc a
and 3
ld (vpw_ypos), a
ld a, PASSWORD_CURSOR
call password_draw_cursor
pop af
ret
password_left:
push af
ld a, 0
call password_draw_cursor
ld a, (vpw_xpos)
dec a
and 7
ld (vpw_xpos), a
ld a, PASSWORD_CURSOR
call password_draw_cursor
pop af
ret
password_right:
push af
ld a, 0
call password_draw_cursor
ld a, (vpw_xpos)
inc a
and 7
ld (vpw_xpos), a
ld a, PASSWORD_CURSOR
call password_draw_cursor
pop af
ret
password_b:
push af
ld a, (vpw_len)
cp 0
jr z, +
dec a
ld (vpw_len), a
call password_draw
+ pop af
ret
password_a:
push af
ld hl, vpw_buf
ld a, (vpw_len)
cp 6
jr nc, +
ld e, a
ld d, 0
add hl, de
ld a, (vpw_ypos)
sla a
sla a
sla a
ld b, a
ld a, (vpw_xpos)
add b
ld (hl), a
ld a, (vpw_len)
inc a
ld (vpw_len), a
call password_draw
+ pop af
ret
;
; Palette data
;
msg_pal:
.db 20, 0, 0
.db 10, 0, 0
.db 30, 10, 10
.db 25, 25, 25
.db 0, 0, 5
.db 10, 5, 0
.db 25, 15, 0
.db 20, 20, 20
.db 0, 0, 5
.db 10, 5, 0
.db 25, 15, 0
.db 15, 15, 15
.db 0, 0, 5
.db 10, 5, 0
.db 20, 20, 20
.db 15, 15, 15
.ENDS
;
; Map data
;
.BANK 1 SLOT SLOT_ROM_BANKED
.SECTION "msg_screen_data" SEMIFREE
; gameover
msg_map_gameover:
.INCBIN "gfx/msg_defeat_map.bin"
; victory
msg_map_victory:
.INCBIN "gfx/msg_victory_map.bin"
; elevator
msg_map_elevator:
.INCBIN "gfx/msg_floordone_map.bin"
; cheat menu
msg_map_cheat:
.INCBIN "gfx/msg_cheat_map.bin"
; password
msg_map_password:
.INCBIN "gfx/msg_password_map.bin"
; chr data
msg_chr:
.INCBIN "gfx/msg_chr.bin"
.ENDS
|
agranlund/wolf
| 12,876
|
z80/gbt_player.s
|
;###############################################################################
;# #
;# #
;# GBT PLAYER 3_0_5 #
;# #
;# Contact: antonio_nd@outlook_com #
;###############################################################################
; Copyright (c) 2009-2016, Antonio Niño Díaz (AntonioND)
; All rights reserved_
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer_
;
; * Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution_
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED_ IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE_
;###############################################################################
.INCLUDE "defines.i"
;###############################################################################
;SECTION "GBT_VAR_1",WRAM0
.RAMSECTION "GBT_VAR_1" BANK 0 SLOT SLOT_RAM_GBTP
;-------------------------------------------------------------------------------
gbt_playing DS 1
; pointer to the pattern pointer array
gbt_pattern_array_ptr DS 2 ; LSB first
gbt_pattern_array_bank DS 1
; playing speed
gbt_speed DS 1
; Up to 12 bytes per step are copied here to be handled in functions in bank 1
gbt_temp_play_data DS 12
gbt_loop_enabled DS 1
gbt_ticks_elapsed DS 1
gbt_current_step DS 1
gbt_current_pattern DS 1
gbt_current_step_data_ptr DS 2 ; pointer to next step data - LSB first
gbt_current_step_data_bank DS 1 ; bank of current pattern data
gbt_channels_enabled: DS 1
gbt_pan DS 4*1 ; Ch 1-4
gbt_vol DS 4*1 ; Ch 1-4
gbt_instr DS 4*1 ; Ch 1-4
gbt_freq DS 3*2 ; Ch 1-3
gbt_channel3_loaded_instrument DS 1 ; current loaded instrument ($FF if none)
; Arpeggio -> Ch 1-3
gbt_arpeggio_freq_index DS 3*3 ; {base index, base index+x, base index+y} * 3
gbt_arpeggio_enabled DS 3*1 ; if 0, disabled
gbt_arpeggio_tick DS 3*1
; Cut note
gbt_cut_note_tick DS 4*1 ; If tick == gbt_cut_note_tick, stop note_
; Last step of last pattern this is set to 1
gbt_have_to_stop_next_step DS 1
gbt_update_pattern_pointers DS 1 ; set to 1 by jump effects
.ENDS
;###############################################################################
.BANK 0 SLOT SLOT_ROM
.ORG $200
.SECTION "GBT_BANK0" SEMIFREE
;-------------------------------------------------------------------------------
gbt_get_pattern_ptr: ; a = pattern number
; loads a pointer to pattern a into gbt_current_step_data_ptr and
; gbt_current_step_data_bank
ld e,a
ld d,0
ld a,[gbt_pattern_array_bank]
ld [$2000],a ; MBC1, MBC3, MBC5 - Set bank
ld hl,gbt_pattern_array_ptr
ld a,[hl+]
ld h,[hl]
ld l,a
; hl = pointer to list of pointers
; de = pattern number
add hl,de
add hl,de
add hl,de
; hl = pointer to pattern bank
ld a,[hl+]
ld [gbt_current_step_data_bank+0],a
; hl = pointer to pattern data
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,l
ld [gbt_current_step_data_ptr],a
ld a,h
ld [gbt_current_step_data_ptr+1],a
ret
;-------------------------------------------------------------------------------
gbt_play: ; de = data, bc = bank, a = speed
ld hl,gbt_pattern_array_ptr
ld [hl],e
inc hl
ld [hl],d
ld [gbt_speed],a
ld a,c
ld [gbt_pattern_array_bank+0],a
ld a,0
call gbt_get_pattern_ptr
xor a
ld [gbt_current_step],a
ld [gbt_current_pattern],a
ld [gbt_ticks_elapsed],a
ld [gbt_loop_enabled],a
ld [gbt_have_to_stop_next_step],a
ld [gbt_update_pattern_pointers],a
ld a,$FF
ld [gbt_channel3_loaded_instrument],a
ld a,$0F
ld [gbt_channels_enabled],a
ld hl,gbt_pan
ld a,$11 ; L and R
ld [hl+],a
add a
ld [hl+],a
add a
ld [hl+],a
add a
ld [hl],a
ld hl,gbt_vol
ld a,$F0 ; 100%
ld [hl+],a
ld [hl+],a
ld a,$20 ; 100%
ld [hl+],a
ld a,$F0 ; 100%
ld [hl+],a
ld a,0
ld hl,gbt_instr
ld [hl+],a
ld [hl+],a
ld [hl+],a
ld [hl+],a
ld hl,gbt_freq
ld [hl+],a
ld [hl+],a
ld [hl+],a
ld [hl+],a
ld [hl+],a
ld [hl+],a
ld [gbt_arpeggio_enabled+0],a
ld [gbt_arpeggio_enabled+1],a
ld [gbt_arpeggio_enabled+2],a
ld a,$FF
ld [gbt_cut_note_tick+0],a
ld [gbt_cut_note_tick+1],a
ld [gbt_cut_note_tick+2],a
ld [gbt_cut_note_tick+3],a
ld a,$80
ld [NR52],a
ld a,$00
ld [NR51],a
ld a,$00 ; 0%
ld [NR50],a
xor a
ld [NR10],a
ld [NR11],a
ld [NR12],a
ld [NR13],a
ld [NR14],a
ld [NR21],a
ld [NR22],a
ld [NR23],a
ld [NR24],a
ld [NR30],a
ld [NR31],a
ld [NR32],a
ld [NR33],a
ld [NR34],a
ld [NR41],a
ld [NR42],a
ld [NR43],a
ld [NR44],a
ld a,$77 ; 100%
ld [NR50],a
ld a,$01
ld [gbt_playing],a
ret
;-------------------------------------------------------------------------------
gbt_pause: ; a = pause/unpause
ld [gbt_playing],a
or a
ret z
xor a
ld [NR50],a
ret
;-------------------------------------------------------------------------------
gbt_loop: ; a = loop/don't loop
ld [gbt_loop_enabled],a
ret
;-------------------------------------------------------------------------------
gbt_stop:
xor a
ld [gbt_playing],a
ld [NR50],a
ld [NR51],a
ld [NR52],a
ret
;-------------------------------------------------------------------------------
gbt_enable_channels: ; a = channel flags (channel flag = (1<<(channel_num-1)))
ld [gbt_channels_enabled],a
ret
;-------------------------------------------------------------------------------
;GLOBAL gbt_update_bank1
gbt_update:
ld a,[gbt_playing]
or a
ret z ; If not playing, return
; Handle tick counter
ld hl,gbt_ticks_elapsed
ld a,[gbt_speed] ; a = total ticks
ld b,[hl] ; b = ticks elapsed
inc b
ld [hl],b
cp b
jr z,_dontexit
; Tick != Speed, update effects and exit
ld a,$01
ld [$2000],a ; MBC1, MBC3, MBC5 - Set bank 1
; Call update function in bank 1 (in gbt_player_bank1_s)
call gbt_update_effects_bank1
ret
_dontexit:
ld [hl],$00 ; reset tick counter
; Clear tick-based effects
; ------------------------
xor a
ld hl,gbt_arpeggio_enabled ; Disable arpeggio
ld [hl+],a
ld [hl+],a
ld [hl],a
dec a ; a = $FF
ld hl,gbt_cut_note_tick ; Disable cut note
ld [hl+],a
ld [hl+],a
ld [hl+],a
ld [hl],a
; Update effects
; --------------
ld a,$01
ld [$2000],a ; MBC1, MBC3, MBC5 - Set bank 1
; Call update function in bank 1 (in gbt_player_bank1_s)
call gbt_update_effects_bank1
; Check if last step
; ------------------
ld a,[gbt_have_to_stop_next_step]
or a
jr z,_dont_stop
call gbt_stop
ld a,0
ld [gbt_have_to_stop_next_step],a
ret
_dont_stop:
; Get this step data
; ------------------
; Change to bank with song data
ld a,[gbt_current_step_data_bank]
ld [$2000],a ; MBC1, MBC3, MBC5 - Set bank
; Get step data
ld a,[gbt_current_step_data_ptr]
ld l,a
ld a,[gbt_current_step_data_ptr+1]
ld h,a ; hl = pointer to data
ld de,gbt_temp_play_data
ld b,4
_copy_loop: ; copy as bytes as needed for this step
ld a,[hl+]
ld [de],a
inc de
bit 7,a
jr nz,_more_bytes
bit 6,a
jr z,_no_more_bytes_this_channel
jr _one_more_byte
_more_bytes:
ld a,[hl+]
ld [de],a
inc de
bit 7,a
jr z,_no_more_bytes_this_channel
_one_more_byte:
ld a,[hl+]
ld [de],a
inc de
_no_more_bytes_this_channel:
dec b
jr nz,_copy_loop
ld a,l
ld [gbt_current_step_data_ptr],a
ld a,h
ld [gbt_current_step_data_ptr+1],a ; save pointer to data
; Increment step/pattern
; ----------------------
; Increment step
ld a,[gbt_current_step]
inc a
ld [gbt_current_step],a
cp 64
jr nz,_dont_increment_pattern
; Increment pattern
ld a,0
ld [gbt_current_step],a ; Step 0
ld a,[gbt_current_pattern]
inc a
ld [gbt_current_pattern],a
call gbt_get_pattern_ptr
ld a,[gbt_current_step_data_ptr]
ld b,a
ld a,[gbt_current_step_data_ptr+1]
or b
jr nz,_not_ended ; if pointer is 0, song has ended
ld a,[gbt_loop_enabled]
and a
jr z,_loop_disabled
; If loop is enabled, jump to pattern 0
ld a,0
ld [gbt_current_pattern],a
call gbt_get_pattern_ptr
jr _end_handling_steps_pattern
_loop_disabled:
; If loop is disabled, stop song
; Stop it next step, if not this step won't be played
ld a,1
ld [gbt_have_to_stop_next_step],a
_not_ended:
_dont_increment_pattern:
_end_handling_steps_pattern:
ld a,$01
ld [$2000],a ; MBC1, MBC3, MBC5 - Set bank 1
; Call update function in bank 1 (in gbt_player_bank1_s)
call gbt_update_bank1
; Check if any effect has changed the pattern or step
ld a,[gbt_update_pattern_pointers]
and a
ret z
; if any effect has changed the pattern or step, update
xor a
ld [gbt_update_pattern_pointers],a ; clear update flag
ld [gbt_have_to_stop_next_step],a ; clear stop flag
ld a,[gbt_current_pattern]
call gbt_get_pattern_ptr ; set ptr to start of the pattern
; Search the step
; Change to bank with song data
ld a,[gbt_pattern_array_bank+0]
ld [$2000],a ; MBC1, MBC3, MBC5
ld a,[gbt_current_step_data_ptr]
ld l,a
ld a,[gbt_current_step_data_ptr+1]
ld h,a ; hl = pointer to data
ld a,[gbt_current_step]
and a
ret z ; if changing to step 0, exit
add a
add a
ld b,a ; b = iterations = step * 4 (number of channels)
_next_channel:
ld a,[hl+]
bit 7,a
jr nz,_next_channel_more_bytes
bit 6,a
jr z,_next_channel_no_more_bytes_this_channel
jr _next_channel_one_more_byte
_next_channel_more_bytes:
ld a,[hl+]
bit 7,a
jr z,_next_channel_no_more_bytes_this_channel
_next_channel_one_more_byte:
ld a,[hl+]
_next_channel_no_more_bytes_this_channel:
dec b
jr nz,_next_channel
ld a,l
ld [gbt_current_step_data_ptr],a
ld a,h
ld [gbt_current_step_data_ptr+1],a ; save pointer to data
ret
.ENDS
;###############################################################################
|
agranlund/wolf
| 9,811
|
z80/gfx.s
|
; Wolfenstein 3D for Gameboy Color
; (c) 2017, Anders Granlund
; www.happydaze.se
;
; This program is free software; you can redistribute it and/or
; modify it under the terms of the GNU General Public License
; as published by the Free Software Foundation; either version 2
; of the License, or (at your option) any later version.
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
;
; gfx_init :
; gfx_oam_update :
; gfx_chr_copy : HL=dest, DE=source, C=num tiles
; gfx_map_copy_20x18 : HL=dest, DE=source
; gfx_map_clear :
; gfx_pal_copy_bg : HL=source, B=dst index, C=count
; gfx_pal_copy_obj : HL=source, B=dst index, C=count
; gfx_pal_clear :
; gfx_pal_fade_bg ; HL=source, DE=dst, B=dst index, C=count, A=val (1.7 fixed point)
; gfx_pal_fade_obj ; HL=source, DE=dst, B=dst index, C=count, A=val (1.7 fixed point)
;
.INCLUDE "defines.i"
;
; constants
;
.EQU gfx_oam_copy $FF80
;
; Variables
;
.RAMSECTION "lib_gfx_vars" BANK 0 SLOT SLOT_RAM
temp_pal_dh DB
temp_pal_dl DB
temp_pal_data DS 3*4*8
.ENDS
.STRUCT oam_entry
ypos DB
xpos DB
tile DB
flag DB
.ENDST
.RAMSECTION "lib_gfx_oam", BANK 0 SLOT SLOT_RAM_OAM
oam DS 4*40
.ENDS
;
; Code
;
.BANK 0 SLOT SLOT_ROM
.SECTION "lib_gfx" SEMIFREE
;
; oam dma
;
_gfx_oam_copy_start:
ld a, oam / $100
ldh (R_DMA), a
ld a, $28
- dec a
jr nz, -
ret
_gfx_oam_copy_end:
;
; init gfx lib
;
gfx_init:
; clear oam
ld hl, oam
ld b, 4*40
xor a
- ldi (hl), a
dec b
jr nz, -
; copy oam routine to hram
ld hl, _gfx_oam_copy_start
ld bc, _gfx_oam_copy_end - _gfx_oam_copy_start
ld de, gfx_oam_copy
- ldi a, (hl)
ld (de), a
inc de
dec bc
ld a, b
or c
jr nz, -
ret
;
; update sprite oam
;
gfx_oam_update:
jp gfx_oam_copy
;
; copy tiles to vram (dmg compatible)
; HL = destination
; DE = source
; C = number of tiles
; destroys: A, BC, DE, HL
;
gfx_chr_copy:
-- ld b, 16
- ldh a, (R_STAT) ; wait vram
and $02
jr nz, -
ld a, (de) ; copy byte
inc de
ldi (hl), a
dec b ; loop tile
jr nz, -
dec c ; loop count
jr nz, --
ret
;
; clear chr at 9800 & 9C00
; destroys: A, BC, DE, HL
;
gfx_chr_clear:
ld hl, sp+0 ; bank0
ld sp, $9800
ld de, $0000
ld bc, 768
xor a
ldh (R_VBK), a
-- di
- ldh a, (R_STAT)
and $02
jr nz, -
push de
push de
push de
push de
ei
dec c
jr nz, --
dec b
jr nz, --
ld sp, $9800
ld de, $0000
ld bc, 768
ld a, 1
ldh (R_VBK), a
-- di
- ldh a, (R_STAT)
and $02
jr nz, -
push de
push de
push de
push de
ei
dec c
jr nz, --
dec b
jr nz, --
xor a ; done
ldh (R_VBK), a
ld sp, hl
ret
;
; copy 20x18 map+attr to vram (dmg compatible)
; HL = destination
; DE = source
; destroys: A, BC, DE, HL
;
gfx_map_copy_20x18:
; tile numbers
push hl
ld b, 18
-- ld c, 20
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, (de)
ldi (hl), a
inc de
dec c
jr nz, -
push bc
ld bc, 12
add hl, bc
pop bc
dec b
jr nz, --
; attributes
pop hl
ld a, (g_console_type)
or a
ret z
ld a, 1
ldh (R_VBK), a
ld b, 18
-- ld c, 20
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, (de)
ldi (hl), a
inc de
dec c
jr nz, -
push bc
ld bc, 12
add hl, bc
pop bc
dec b
jr nz, --
xor a
ldh (R_VBK), a
ret
;
; clear maps at 9800 & 9C00
; destroys: A, BC, DE, HL
;
gfx_map_clear:
ld hl, sp+0
ld sp, $9800+2048
ld de, $0000
ld bc, 2048/8
-- di
- ldh a, (R_STAT) ; wait vram
and $02
jr nz, -
push de ; clear 8 bytes
push de
push de
push de
ei
dec c ; loop
jr nz, --
dec b
jr nz, --
ld sp, hl
ret
;
; copy bg palette to vram
; HL = source
; B = dst index
; C = count
; destroys: A, BC, DE, HL
;
gfx_pal_copy_bg:
ld a, b
sla a
sla a
sla a
or %10000000
--- ldh (R_BCPS), a
push af
ld b, 4
-- ldi a, (hl)
ld e, a
ldi a, (hl)
ld d, a
rrc a
rrc a
rrc a
and %11100000
or e
ld e, a
srl d
srl d
srl d
ldi a, (hl)
sla a
sla a
or d
ld d, a
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, e
ldh (R_BCPD), a
ld a, d
ldh (R_BCPD), a
dec b
jr nz, --
pop af
add 8
dec c
jr nz, ---
ret
;
; copy obj palette to vram
; HL = source
; B = dst index
; C = count
; destroys: A, B, C, DE, HL
;
gfx_pal_copy_obj:
ld a, b
sla a
sla a
sla a
or %10000000
--- ldh (R_OCPS), a
push af
ld b, 4
-- ldi a, (hl)
ld e, a
ldi a, (hl)
ld d, a
rrc a
rrc a
rrc a
and %11100000
or e
ld e, a
srl d
srl d
srl d
ldi a, (hl)
sla a
sla a
or d
ld d, a
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, e
ldh (R_OCPD), a
ld a, d
ldh (R_OCPD), a
dec b
jr nz, --
pop af
add 8
dec c
jr nz, ---
ret
;
; clear bg + obj palette
; destroys: A, B, C, DE, HL
;
gfx_pal_clear:
; bg pal
ld c, 8
ld a, %10000000
-- ldh (R_BCPS), a
push af
ld b, 4
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, %11111111
ldh (R_BCPD), a
ldh (R_BCPD), a
dec b
jr nz, -
pop af
add 8
dec c
jr nz, --
; obj pal
ld c, 8
ld a, %10000000
-- ldh (R_OCPS), a
push af
ld b, 4
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, %11111111
ldh (R_OCPD), a
ldh (R_OCPD), a
dec b
jr nz, -
pop af
add 8
dec c
jr nz, --
ret
;
; fade palette
; HL=src, DE=dst, B=dst index, C=count, A=val (0:s, 128:d)
; destroys: A, B, C, DE, HL
;
gfx_pal_fade_bg:
cp 0
jp z, gfx_pal_copy_bg
cp 128
jr nz, +
ld l, e
ld h, d
jp gfx_pal_copy_bg
+ call _gfx_pal_fade
jp gfx_pal_copy_bg
gfx_pal_fade_obj:
cp 0
jp z, gfx_pal_copy_obj
cp 128
jr nz, +
ld l, e
ld h, d
jp gfx_pal_copy_obj
+ call _gfx_pal_fade
jp gfx_pal_copy_obj
_gfx_pal_fade:
push bc
push af
sla c
sla c
ld a, c
sla c
add c
ld c, a ; c = number of bytes (count * 12)
push hl
ld hl, temp_pal_data
ld a, l
ld (temp_pal_dl), a
ld a, h
ld (temp_pal_dh), a
pop hl
pop af
ld b, a ; b = val
- push bc
ld a, (de)
inc de
ld c, (hl)
cp c
jr c, ++
; fade up
sub c
ld c, a
sla c ; c = abs(dst - src) << 1
push de
push hl
call sys_mul_8x8 ; d = color
ld a, d
pop hl
add (hl)
cp 32
jr c, +
ld a, 31
+ ld b, a ; b = src + (((dst - src) * (val<<1)) >> 8)
jr +++
; fade down
++ ld c, a
ld a, (hl)
sub c
ld c, a ; c = abs(dst-src)
sla c
push de
push hl
call sys_mul_8x8 ; d = color
pop hl
ld a, (hl)
sub d
cp 32
jr c, +
ld a, 0
+ ld b, a ; b = src - (((dst - src) * (val<<1)) >> 8)
; save to temp
+++ inc hl
push hl
ld a, (temp_pal_dl)
ld l, a
ld a, (temp_pal_dh)
ld h, a
ld a, b
ld (hl), a
inc hl
ld a, l
ld (temp_pal_dl), a
ld a, h
ld (temp_pal_dh), a
; loop
pop hl
pop de
pop bc
dec c
jr nz, -
; return hl = temp_palette
pop bc
ld hl, temp_pal_data
ret
.ENDS
;
; Data
;
.BANK 0 SLOT 0
.SECTION "lib_gfx_data" SEMIFREE
PAL_WHITE:
.REPT 4*8
.db 31, 31, 31
.db 31, 31, 31
.db 31, 31, 31
.ENDR
PAL_BLACK:
.REPT 4*8
.db 0, 0, 0
.db 0, 0, 0
.db 0, 0, 0
.ENDR
PAL_RED:
.REPT 4*8
.db 31, 0, 0
.db 31, 0, 0
.db 31, 0, 0
.ENDR
.ENDS
|
agranlund/wolf
| 27,687
|
z80/gbt_player_bank1.s
|
;###############################################################################
;# #
;# #
;# GBT PLAYER 3_0_5 #
;# #
;# Contact: antonio_nd@outlook_com #
;###############################################################################
; Copyright (c) 2009-2016, Antonio Nio Daz (AntonioND)
; All rights reserved_
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer_
;
; * Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution_
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED_ IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE_
;###############################################################################
.INCLUDE "defines.i"
;###############################################################################
.BANK 1 SLOT SLOT_ROM_BANKED
.ORG $0
.SECTION "GBT_BANK1" SEMIFREE
;-------------------------------------------------------------------------------
gbt_wave: ; 8 sounds
.DB $A5,$D7,$C9,$E1,$BC,$9A,$76,$31,$0C,$BA,$DE,$60,$1B,$CA,$03,$93 ; random
.DB $F0,$E1,$D2,$C3,$B4,$A5,$96,$87,$78,$69,$5A,$4B,$3C,$2D,$1E,$0F
.DB $FD,$EC,$DB,$CA,$B9,$A8,$97,$86,$79,$68,$57,$46,$35,$24,$13,$02 ; up-downs
.DB $DE,$FE,$DC,$BA,$9A,$A9,$87,$77,$88,$87,$65,$56,$54,$32,$10,$12
.DB $AB,$CD,$EF,$ED,$CB,$A0,$12,$3E,$DC,$BA,$BC,$DE,$FE,$DC,$32,$10 ; tri_ broken
.DB $FF,$EE,$DD,$CC,$BB,$AA,$99,$88,$77,$66,$55,$44,$33,$22,$11,$00 ; triangular
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$00,$00,$00,$00,$00,$00,$00,$00 ; square
.DB $79,$BC,$DE,$EF,$FF,$EE,$DC,$B9,$75,$43,$21,$10,$00,$11,$23,$45 ; sine
gbt_noise: ; 16 sounds
; 7 bit
.DB $5F,$5B,$4B,$2F,$3B,$58,$1F,$0F
; 15 bit
.DB $90,$80,$70,$50,$00
.DB $67,$63,$53
gbt_frequencies:
.DW 44, 156, 262, 363, 457, 547, 631, 710, 786, 854, 923, 986
.DW 1046, 1102, 1155, 1205, 1253, 1297, 1339, 1379, 1417, 1452, 1486, 1517
.DW 1546, 1575, 1602, 1627, 1650, 1673, 1694, 1714, 1732, 1750, 1767, 1783
.DW 1798, 1812, 1825, 1837, 1849, 1860, 1871, 1881, 1890, 1899, 1907, 1915
.DW 1923, 1930, 1936, 1943, 1949, 1954, 1959, 1964, 1969, 1974, 1978, 1982
.DW 1985, 1988, 1992, 1995, 1998, 2001, 2004, 2006, 2009, 2011, 2013, 2015
;-------------------------------------------------------------------------------
_gbt_get_freq_from_index: ; a = index, bc = returned freq
ld hl,gbt_frequencies
ld c,a
ld b,$00
add hl,bc
add hl,bc
ld c,[hl]
inc hl
ld b,[hl]
ret
;-------------------------------------------------------------------------------
; ---------------------------------- Channel 1 ---------------------------------
;-------------------------------------------------------------------------------
gbt_channel_1_handle: ; de = info
ld a,[gbt_channels_enabled]
and $01
jr nz,_channel1_enabled
; Channel is disabled_ Increment pointer as needed
ld a,[de]
inc de
bit 7,a
jr nz,_more_bytes1
bit 6,a
jr z,_no_more_bytes_this_channel1
jr _one_more_byte1
_more_bytes1:
ld a,[de]
inc de
bit 7,a
jr z,_no_more_bytes_this_channel1
_one_more_byte1:
inc de
_no_more_bytes_this_channel1:
ret
_channel1_enabled:
; Channel 1 is enabled
ld a,[de]
inc de
bit 7,a
jr nz,_has_frequency1
; Not frequency
bit 6,a
jr nz,_instr_effects1
; Set volume or NOP
bit 5,a
jr nz,_just_set_volume1
; NOP
ret
_just_set_volume1:
; Set volume
and $0F
swap a
ld [gbt_vol+0],a
jr _refresh_channel1_regs
_instr_effects1:
; Set instrument and effect
ld b,a ; save byte
and $30
add a
add a
ld [gbt_instr+0],a ; Instrument
ld a,b ; restore byte
and $0F ; a = effect
call gbt_channel_1_set_effect
jr _refresh_channel1_regs
_has_frequency1:
; Has frequency
and $7F
ld [gbt_arpeggio_freq_index+0*3],a
; This destroys hl and a_ Returns freq in bc
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+0*2+0],a
ld a,b
ld [gbt_freq+0*2+1],a ; Get frequency
ld a,[de]
inc de
bit 7,a
jr nz,_freq_instr_and_effect1
; Freq + Instr + Volume
ld b,a ; save byte
and $30
add a
add a
ld [gbt_instr+0],a ; Instrument
ld a,b ; restore byte
and $0F ; a = volume
swap a
ld [gbt_vol+0],a
jr _refresh_channel1_regs
_freq_instr_and_effect1:
; Freq + Instr + Effect
ld b,a ; save byte
and $30
add a
add a
ld [gbt_instr+0],a ; Instrument
ld a,b ; restore byte
and $0F ; a = effect
call gbt_channel_1_set_effect
;jr _refresh_channel1_regs
_refresh_channel1_regs:
; fall through!!!!!
; -----------------
channel1_refresh_registers:
xor a
ld [NR10],a
ld a,[gbt_instr+0]
ld [NR11],a
ld a,[gbt_vol+0]
ld [NR12],a
ld a,[gbt_freq+0*2+0]
ld [NR13],a
ld a,[gbt_freq+0*2+1]
or $80 ; start
ld [NR14],a
ret
; ------------------
channel1_update_effects: ; returns 1 in a if it needed to update sound registers
; Cut note
; --------
ld a,[gbt_cut_note_tick+0]
ld hl,gbt_ticks_elapsed
cp [hl]
jp nz,_dont_cut1
dec a ; a = $FF
ld [gbt_cut_note_tick+0],a ; disable cut note
xor a ; vol = 0
ld [NR12],a
ld a,$80 ; start
ld [NR14],a
_dont_cut1:
; Arpeggio
; --------
ld a,[gbt_arpeggio_enabled+0]
and a
ret z ; a is 0, return 0
; If enabled arpeggio, handle it
ld a,[gbt_arpeggio_tick+0]
and a
jr nz,_not_tick_01
; Tick 0 - Set original frequency
ld a,[gbt_arpeggio_freq_index+0*3+0]
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+0*2+0],a
ld a,b
ld [gbt_freq+0*2+1],a ; Set frequency
ld a,1
ld [gbt_arpeggio_tick+0],a
ret ; ret 1
_not_tick_01:
cp 1
jr nz,_not_tick_11
; Tick 1
ld a,[gbt_arpeggio_freq_index+0*3+1]
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+0*2+0],a
ld a,b
ld [gbt_freq+0*2+1],a ; Set frequency
ld a,2
ld [gbt_arpeggio_tick+0],a
dec a
ret ; ret 1
_not_tick_11:
; Tick 2
ld a,[gbt_arpeggio_freq_index+0*3+2]
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+0*2+0],a
ld a,b
ld [gbt_freq+0*2+1],a ; Set frequency
xor a
ld [gbt_arpeggio_tick+0],a
inc a ; ret 1
ret
; -----------------
; returns a = 1 if needed to update registers, 0 if not
gbt_channel_1_set_effect: ; a = effect, de = pointer to data_
ld hl,_gbt_ch1_jump_table
ld c,a
ld b,0
add hl,bc
add hl,bc
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[de] ; load args
inc de
jp hl
_gbt_ch1_jump_table:
.DW _gbt_ch1_pan
.DW _gbt_ch1_arpeggio
.DW _gbt_ch1_cut_note
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_jump_pattern
.DW gbt_ch1234_jump_position
.DW gbt_ch1234_speed
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
_gbt_ch1_pan:
and $11
ld [gbt_pan+0],a
ld a,1
ret ; ret 1
_gbt_ch1_arpeggio:
ld b,a ; b = params
ld hl,gbt_arpeggio_freq_index+0*3
ld c,[hl] ; c = base index
inc hl
ld a,b
swap a
and $0F
add c
ld [hl+],a ; save first increment
ld a,b
and $0F
add c
ld [hl],a ; save second increment
ld a,1
ld [gbt_arpeggio_enabled+0],a
ld [gbt_arpeggio_tick+0],a
ret ; ret 1
_gbt_ch1_cut_note:
ld [gbt_cut_note_tick+0],a
xor a ; ret 0
ret
;-------------------------------------------------------------------------------
; ---------------------------------- Channel 2 ---------------------------------
;-------------------------------------------------------------------------------
gbt_channel_2_handle: ; de = info
ld a,[gbt_channels_enabled]
and $02
jr nz,_channel2_enabled
; Channel is disabled_ Increment pointer as needed
ld a,[de]
inc de
bit 7,a
jr nz,_more_bytes2
bit 6,a
jr z,_no_more_bytes_this_channel2
jr _one_more_byte2
_more_bytes2:
ld a,[de]
inc de
bit 7,a
jr z,_no_more_bytes_this_channel2
_one_more_byte2:
inc de
_no_more_bytes_this_channel2:
ret
_channel2_enabled:
; Channel 2 is enabled
ld a,[de]
inc de
bit 7,a
jr nz,_has_frequency2
; Not frequency
bit 6,a
jr nz,_instr_effects2
; Set volume or NOP
bit 5,a
jr nz,_just_set_volume2
; NOP
ret
_just_set_volume2:
; Set volume
and $0F
swap a
ld [gbt_vol+1],a
jr _refresh_channel2_regs
_instr_effects2:
; Set instrument and effect
ld b,a ; save byte
and $30
add a
add a
ld [gbt_instr+1],a ; Instrument
ld a,b ; restore byte
and $0F ; a = effect
call gbt_channel_2_set_effect
jr _refresh_channel2_regs
_has_frequency2:
; Has frequency
and $7F
ld [gbt_arpeggio_freq_index+1*3],a
; This destroys hl and a_ Returns freq in bc
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+1*2+0],a
ld a,b
ld [gbt_freq+1*2+1],a ; Get frequency
ld a,[de]
inc de
bit 7,a
jr nz,_freq_instr_and_effect2
; Freq + Instr + Volume
ld b,a ; save byte
and $30
add a
add a
ld [gbt_instr+1],a ; Instrument
ld a,b ; restore byte
and $0F ; a = volume
swap a
ld [gbt_vol+1],a
jr _refresh_channel2_regs
_freq_instr_and_effect2:
; Freq + Instr + Effect
ld b,a ; save byte
and $30
add a
add a
ld [gbt_instr+1],a ; Instrument
ld a,b ; restore byte
and $0F ; a = effect
call gbt_channel_2_set_effect
;jr _refresh_channel2_regs
_refresh_channel2_regs:
; fall through!!!!!
; -----------------
channel2_refresh_registers:
ld a,[gbt_instr+1]
ld [NR21],a
ld a,[gbt_vol+1]
ld [NR22],a
ld a,[gbt_freq+1*2+0]
ld [NR23],a
ld a,[gbt_freq+1*2+1]
or $80 ; start
ld [NR24],a
ret
; ------------------
channel2_update_effects: ; returns 1 in a if it needed to update sound registers
; Cut note
; --------
ld a,[gbt_cut_note_tick+1]
ld hl,gbt_ticks_elapsed
cp [hl]
jp nz,_dont_cut2
dec a ; a = $FF
ld [gbt_cut_note_tick+1],a ; disable cut note
xor a ; vol = 0
ld [NR22],a
ld a,$80 ; start
ld [NR24],a
_dont_cut2:
; Arpeggio
; --------
ld a,[gbt_arpeggio_enabled+1]
and a
ret z ; a is 0, return 0
; If enabled arpeggio, handle it
ld a,[gbt_arpeggio_tick+1]
and a
jr nz,_not_tick_02
; Tick 0 - Set original frequency
ld a,[gbt_arpeggio_freq_index+1*3+0]
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+1*2+0],a
ld a,b
ld [gbt_freq+1*2+1],a ; Set frequency
ld a,1
ld [gbt_arpeggio_tick+1],a
ret ; ret 1
_not_tick_02:
cp 1
jr nz,_not_tick_12
; Tick 1
ld a,[gbt_arpeggio_freq_index+1*3+1]
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+1*2+0],a
ld a,b
ld [gbt_freq+1*2+1],a ; Set frequency
ld a,2
ld [gbt_arpeggio_tick+1],a
dec a
ret ; ret 1
_not_tick_12:
; Tick 2
ld a,[gbt_arpeggio_freq_index+1*3+2]
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+1*2+0],a
ld a,b
ld [gbt_freq+1*2+1],a ; Set frequency
xor a
ld [gbt_arpeggio_tick+1],a
inc a ; ret 1
ret
; -----------------
; returns a = 1 if needed to update registers, 0 if not
gbt_channel_2_set_effect: ; a = effect, de = pointer to data
ld hl,_gbt_ch2_jump_table
ld c,a
ld b,0
add hl,bc
add hl,bc
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[de] ; load args
inc de
jp hl
_gbt_ch2_jump_table:
.DW _gbt_ch2_pan
.DW _gbt_ch2_arpeggio
.DW _gbt_ch2_cut_note
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_jump_pattern
.DW gbt_ch1234_jump_position
.DW gbt_ch1234_speed
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
_gbt_ch2_pan:
and $22
ld [gbt_pan+1],a
ld a,1
ret ; ret 1
_gbt_ch2_arpeggio:
ld b,a ; b = params
ld hl,gbt_arpeggio_freq_index+1*3
ld c,[hl] ; c = base index
inc hl
ld a,b
swap a
and $0F
add c
ld [hl+],a ; save first increment
ld a,b
and $0F
add c
ld [hl],a ; save second increment
ld a,1
ld [gbt_arpeggio_enabled+1],a
ld [gbt_arpeggio_tick+1],a
ret ; ret 1
_gbt_ch2_cut_note:
ld [gbt_cut_note_tick+1],a
xor a ; ret 0
ret
;-------------------------------------------------------------------------------
; ---------------------------------- Channel 3 ---------------------------------
;-------------------------------------------------------------------------------
gbt_channel_3_handle: ; de = info
ld a,[gbt_channels_enabled]
and $04
jr nz,_channel3_enabled
; Channel is disabled_ Increment pointer as needed
ld a,[de]
inc de
bit 7,a
jr nz,_more_bytes3
bit 6,a
jr z,_no_more_bytes_this_channel3
jr _one_more_byte3
_more_bytes3:
ld a,[de]
inc de
bit 7,a
jr z,_no_more_bytes_this_channel3
_one_more_byte3:
inc de
_no_more_bytes_this_channel3:
ret
_channel3_enabled:
; Channel 3 is enabled
ld a,[de]
inc de
bit 7,a
jr nz,_has_frequency3
; Not frequency
bit 6,a
jr nz,_effects3
; Set volume or NOP
bit 5,a
jr nz,_just_set_volume3
; NOP
ret
_just_set_volume3:
; Set volume
and $0F
swap a
ld [gbt_vol+2],a
jr _refresh_channel3_regs
_effects3:
; Set effect
and $0F ; a = effect
call gbt_channel_3_set_effect
and a
ret z ; if 0, don't refresh registers
jr _refresh_channel3_regs
_has_frequency3:
; Has frequency
and $7F
ld [gbt_arpeggio_freq_index+2*3],a
; This destroys hl and a_ Returns freq in bc
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+2*2+0],a
ld a,b
ld [gbt_freq+2*2+1],a ; Get frequency
ld a,[de]
inc de
bit 7,a
jr nz,_freq_instr_and_effect3
; Freq + Instr + Volume
ld b,a ; save byte
and $0F
ld [gbt_instr+2],a ; Instrument
ld a,b ; restore byte
and $30 ; a = volume
add a
ld [gbt_vol+2],a
jr _refresh_channel3_regs
_freq_instr_and_effect3:
; Freq + Instr + Effect
ld b,a ; save byte
and $0F
ld [gbt_instr+2],a ; Instrument
ld a,b ; restore byte
and $70
swap a ; a = effect (only 0-7 allowed here)
call gbt_channel_3_set_effect
;jr _refresh_channel3_regs
_refresh_channel3_regs:
; fall through!!!!!
; -----------------
channel3_refresh_registers:
xor a
ld [NR30],a ; disable
ld a,[gbt_channel3_loaded_instrument]
ld b,a
ld a,[gbt_instr+2]
cp b
call nz,gbt_channel3_load_instrument ; a = instrument
ld a,$80
ld [NR30],a ; enable
xor a
ld [NR31],a
ld a,[gbt_vol+2]
ld [NR32],a
ld a,[gbt_freq+2*2+0]
ld [NR33],a
ld a,[gbt_freq+2*2+1]
or $80 ; start
ld [NR34],a
ret
; ------------------
gbt_channel3_load_instrument:
ld [gbt_channel3_loaded_instrument],a
swap a ; a = a * 16
ld c,a
ld b,0
ld hl,gbt_wave
add hl,bc
ld c,$30
ld b,16
_loop3:
ld a,[hl+]
ld [$FF00+c],a
inc c
dec b
jr nz,_loop3
ret
; ------------------
channel3_update_effects: ; returns 1 in a if it needed to update sound registers
; Cut note
; --------
ld a,[gbt_cut_note_tick+2]
ld hl,gbt_ticks_elapsed
cp [hl]
jp nz,_dont_cut3
dec a ; a = $FF
ld [gbt_cut_note_tick+2],a ; disable cut note
ld a,$80
ld [NR30],a ; enable
xor a ; vol = 0
ld [NR32],a
ld a,$80 ; start
ld [NR34],a
_dont_cut3:
; Arpeggio
; --------
ld a,[gbt_arpeggio_enabled+2]
and a
ret z ; a is 0, return 0
; If enabled arpeggio, handle it
ld a,[gbt_arpeggio_tick+2]
and a
jr nz,_not_tick_03
; Tick 0 - Set original frequency
ld a,[gbt_arpeggio_freq_index+2*3+0]
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+2*2+0],a
ld a,b
ld [gbt_freq+2*2+1],a ; Set frequency
ld a,1
ld [gbt_arpeggio_tick+2],a
ret ; ret 1
_not_tick_03:
cp 1
jr nz,_not_tick_13
; Tick 1
ld a,[gbt_arpeggio_freq_index+2*3+1]
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+2*2+0],a
ld a,b
ld [gbt_freq+2*2+1],a ; Set frequency
ld a,2
ld [gbt_arpeggio_tick+2],a
dec a
ret ; ret 1
_not_tick_13:
; Tick 2
ld a,[gbt_arpeggio_freq_index+2*3+2]
call _gbt_get_freq_from_index
ld a,c
ld [gbt_freq+2*2+0],a
ld a,b
ld [gbt_freq+2*2+1],a ; Set frequency
xor a
ld [gbt_arpeggio_tick+2],a
inc a
ret ; ret 1
; -----------------
; returns a = 1 if needed to update registers, 0 if not
gbt_channel_3_set_effect: ; a = effect, de = pointer to data
ld hl,_gbt_ch3_jump_table
ld c,a
ld b,0
add hl,bc
add hl,bc
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[de] ; load args
inc de
jp hl
_gbt_ch3_jump_table:
.DW _gbt_ch3_pan
.DW _gbt_ch3_arpeggio
.DW _gbt_ch3_cut_note
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_jump_pattern
.DW gbt_ch1234_jump_position
.DW gbt_ch1234_speed
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
_gbt_ch3_pan:
and $44
ld [gbt_pan+2],a
ld a,1
ret ; ret 1
_gbt_ch3_arpeggio:
ld b,a ; b = params
ld hl,gbt_arpeggio_freq_index+2*3
ld c,[hl] ; c = base index
inc hl
ld a,b
swap a
and $0F
add c
ld [hl+],a ; save first increment
ld a,b
and $0F
add c
ld [hl],a ; save second increment
ld a,1
ld [gbt_arpeggio_enabled+2],a
ld [gbt_arpeggio_tick+2],a
ret ; ret 1
_gbt_ch3_cut_note:
ld [gbt_cut_note_tick+2],a
xor a ; ret 0
ret
;-------------------------------------------------------------------------------
; ---------------------------------- Channel 4 ---------------------------------
;-------------------------------------------------------------------------------
gbt_channel_4_handle: ; de = info
ld a,[gbt_channels_enabled]
and $08
jr nz,_channel4_enabled
; Channel is disabled_ Increment pointer as needed
ld a,[de]
inc de
bit 7,a
jr nz,_more_bytes4
bit 6,a
jr z,_no_more_bytes_this_channel4
jr _one_more_byte4
_more_bytes4:
ld a,[de]
inc de
bit 7,a
jr z,_no_more_bytes_this_channel4
_one_more_byte4:
inc de
_no_more_bytes_this_channel4:
ret
_channel4_enabled:
; Channel 4 is enabled
ld a,[de]
inc de
bit 7,a
jr nz,_has_instrument4
; Not instrument
bit 6,a
jr nz,_effects4
; Set volume or NOP
bit 5,a
jr nz,_just_set_volume4
; NOP
ret
_just_set_volume4:
; Set volume
and $0F
swap a
ld [gbt_vol+3],a
jr _refresh_channel4_regs
_effects4:
; Set effect
and $0F ; a = effect
call gbt_channel_4_set_effect
and a
ret z ; if 0, don't refresh registers
jr _refresh_channel4_regs
_has_instrument4:
; Has instrument
and $1F
ld hl,gbt_noise
ld c,a
ld b,0
add hl,bc
ld a,[hl] ; a = instrument data
ld [gbt_instr+3],a
ld a,[de]
inc de
bit 7,a
jr nz,_instr_and_effect4
; Instr + Volume
and $0F ; a = volume
swap a
ld [gbt_vol+3],a
jr _refresh_channel4_regs
_instr_and_effect4:
; Instr + Effect
and $0F ; a = effect
call gbt_channel_4_set_effect
;jr _refresh_channel4_regs
_refresh_channel4_regs:
; fall through!!!!!
; -----------------
channel4_refresh_registers:
xor a
ld [NR41],a
ld a,[gbt_vol+3]
ld [NR42],a
ld a,[gbt_instr+3]
ld [NR43],a
ld a,$80 ; start
ld [NR44],a
ret
; ------------------
channel4_update_effects: ; returns 1 in a if it needed to update sound registers
; Cut note
; --------
ld a,[gbt_cut_note_tick+3]
ld hl,gbt_ticks_elapsed
cp [hl]
jp nz,_dont_cut4
dec a ; a = $FF
ld [gbt_cut_note_tick+3],a ; disable cut note
xor a ; vol = 0
ld [NR42],a
ld a,$80 ; start
ld [NR44],a
_dont_cut4:
xor a
ret ; a is 0, return 0
; -----------------
; returns a = 1 if needed to update registers, 0 if not
gbt_channel_4_set_effect: ; a = effect, de = pointer to data
ld hl,_gbt_ch4_jump_table
ld c,a
ld b,0
add hl,bc
add hl,bc
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[de] ; load args
inc de
jp hl
_gbt_ch4_jump_table:
.DW _gbt_ch4_pan
.DW gbt_ch1234_nop ; gbt_ch4_arpeggio
.DW _gbt_ch4_cut_note
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_jump_pattern
.DW gbt_ch1234_jump_position
.DW gbt_ch1234_speed
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
.DW gbt_ch1234_nop
_gbt_ch4_pan:
and $44
ld [gbt_pan+3],a
ld a,1
ret ; ret 1
_gbt_ch4_cut_note:
ld [gbt_cut_note_tick+3],a
xor a ; ret 0
ret
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
; Common effects go here:
gbt_ch1234_nop:
xor a ;ret 0
ret
gbt_ch1234_jump_pattern:
ld [gbt_current_pattern],a
xor a
ld [gbt_current_step],a
ld [gbt_have_to_stop_next_step],a ; clear stop flag
ld a,1
ld [gbt_update_pattern_pointers],a
xor a ;ret 0
ret
gbt_ch1234_jump_position:
ld [gbt_current_step],a
ld hl,gbt_current_pattern
inc [hl]
ld a,1
ld [gbt_update_pattern_pointers],a
xor a ;ret 0
ret
gbt_ch1234_speed:
ld [gbt_speed],a
xor a
ld [gbt_ticks_elapsed],a
ret ;ret 0
;-------------------------------------------------------------------------------
gbt_update_bank1:
ld de,gbt_temp_play_data
; each function will return in de the pointer to next byte
call gbt_channel_1_handle
call gbt_channel_2_handle
call gbt_channel_3_handle
call gbt_channel_4_handle
; end of channel handling
ld hl,gbt_pan
ld a,[hl+]
or [hl]
inc hl
or [hl]
inc hl
or [hl]
ld [NR51],a ; handle panning___
ret
;-------------------------------------------------------------------------------
gbt_update_effects_bank1:
call channel1_update_effects
and a
call nz,channel1_refresh_registers
call channel2_update_effects
and a
call nz,channel2_refresh_registers
call channel3_update_effects
and a
call nz,channel3_refresh_registers
call channel4_update_effects
and a
call nz,channel4_refresh_registers
ret
.ENDS
;###############################################################################
|
agranlund/wolf
| 7,588
|
z80/intro.s
|
; Wolfenstein 3D for Gameboy Color
; (c) 2017, Anders Granlund
; www.happydaze.se
;
; This program is free software; you can redistribute it and/or
; modify it under the terms of the GNU General Public License
; as published by the Free Software Foundation; either version 2
; of the License, or (at your option) any later version.
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
.INCLUDE "defines.i"
.RAMSECTION "intro_vars" BANK 0 SLOT SLOT_RAM
mm_ypos DS 1
.ENDS
.BANK 0 SLOT SLOT_ROM
.ORG $200
.SECTION "Code_Intro" SEMIFREE
;
; Legal screen
;
intro:
; copy legal screen chr & map
ld a, :legal_tile_data
ld ($2000), a
ld hl, $8000
ld de, legal_tile_data
ld c, 127
call gfx_chr_copy
ld hl, $9800
ld de, legal_map_data
call gfx_map_copy_20x18
; enable bg
ld a, %10010001
ldh (R_LCDC), a
; fade in
xor a
- push af
ld hl, PAL_WHITE
ld de, legal_pal_data
ld bc, 1
call gfx_pal_fade_bg
pop af
inc a
cp 129
jr nz, -
; pause a while
ld bc, 60 * 4
call sys_delay
; fade out
xor a
- push af
ld hl, legal_pal_data
ld de, PAL_BLACK
ld bc, 1
call gfx_pal_fade_bg
pop af
inc a
cp 129
jr nz, -
ret
;
; Title screen
;
title:
xor a
ld (cheat_godmode), a
ld (cheat_guns), a
ld a, 1
ld (start_floor), a
xor a
ld (mm_ypos), a
ld (pwd_start), a
; stop music and sound
call snd_stop_music
call snd_stop_fx
; clear all palettes to black
ld hl, PAL_BLACK
ld bc, 8
call gfx_pal_copy_bg
ld hl, PAL_BLACK
ld bc, 8
call gfx_pal_copy_obj
; init screen and interrupts
di
xor a
ldh (R_IF), a
ldh (R_IE), a
ld a, %10010001
ldh (R_LCDC), a
; copy title screen chr & map
ld a, :title_tile_data
ld ($2000), a
ld hl, $8000
ld de, title_tile_data
ld c, 127
call gfx_chr_copy
ld hl, $9800
ld de, title_map_data
call gfx_map_copy_20x18
; copy font
ld a, :msg_chr
ld ($2000), a
ld hl, $8500
ld de, msg_chr
ld c, 48
call gfx_chr_copy
; prepare menu
call sys_wait_vbl
ld a, 1
ldh (R_VBK), a
ld hl, $99C4
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ld hl, $99E4
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ldi (hl), a
ld a, %00100001
ld hl, $99CE
ld (hl), a
ld hl, $99EE
ld (hl), a
xor a
ldh (R_VBK), a
; start music
ld a, 0
call snd_play_music
; fade in
xor a
- push af
ld bc, 1
call sys_delay
call snd_update
ld a, :title_pal_data
ld ($2000), a
pop af
ld hl, PAL_BLACK
ld de, title_pal_data
ld bc, 2
push af
call gfx_pal_fade_bg
pop af
inc a
cp 129
jr c, -
call title_print_menu
ld a, $7C
call title_print_cursor
- call sys_wait_vbl
; play music, check start button
+ call snd_update
call sys_update_joypad
ld a, (g_joypad_trigger)
and %11000000
jr z, +
xor a
call title_print_cursor
ld a, (mm_ypos)
inc a
and 1
ld (mm_ypos), a
ld a, $7C
call title_print_cursor
+ ld a, (g_joypad_trigger)
and %00000001
jr z, -
ld a, (mm_ypos)
and %00000001
jp nz, title_to_password_screen
; go to cheat menu
ld a, (g_joypad_status)
and %00000100
jp nz, title_to_cheat_menu
; play sound effect
call snd_stop_music
ld a, $1
call snd_play_fx
ld c, 1
- push bc
call snd_update
ld bc, 1
call sys_delay
pop bc
dec c
jr nz, -
; fade out
xor a
- push af
ld bc, 1
call sys_delay
call snd_update
ld a, :title_pal_data
ld ($2000), a
pop af
ld hl, title_pal_data
ld de, PAL_BLACK
ld bc, 2
push af
call gfx_pal_fade_bg
pop af
add 4
cp 129
jr c, -
ld bc, 20
call sys_delay
ret
title_print_menu:
ld hl, $99C6
ld de, title_menu1
ld b, 8
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, (de)
ldi (hl), a
inc de
dec b
jr nz, -
ld hl, $99E6
ld de, title_menu2
ld b, 8
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, (de)
ldi (hl), a
inc de
dec b
jr nz, -
ret
title_print_cursor:
ld b, a
ld hl, $99C5
ld a, (mm_ypos)
sla a
sla a
sla a
sla a
sla a
ld e, a
ld d, 0
add hl, de
ld de, 9
- ldh a, (R_STAT)
and $02
jr nz, -
ld (hl), b
add hl, de
;ld (hl), b
ret
title_to_cheat_menu:
xor a
- push af
ld bc, 1
call sys_delay
call snd_update
ld a, :title_pal_data
ld ($2000), a
pop af
ld hl, title_pal_data
ld de, PAL_RED
ld bc, 2
push af
call gfx_pal_fade_bg
pop af
add 4
cp 129
jr c, -
ld bc, 20
jp cheatmenu
title_to_password_screen:
xor a
- push af
ld bc, 1
call sys_delay
call snd_update
ld a, :title_pal_data
ld ($2000), a
pop af
ld hl, title_pal_data
ld de, PAL_RED
ld bc, 2
push af
call gfx_pal_fade_bg
pop af
add 4
cp 129
jr c, -
ld bc, 20
call password
ld a, (pwd_start)
or a
jp z, title
ret
title_menu1:
.DB $68, $5F, $71, $00, $61, $5B, $67, $5F
title_menu2:
.DB $5D, $69, $68, $6E, $63, $68, $6F, $5F
.ENDS
.BANK 3 SLOT SLOT_ROM_BANKED
.SECTION "intro_data" SEMIFREE
; Data for legal screen
.INCLUDE "gfx/legal.s"
legal_pal_data:
.db 20, 0, 0
.db 13, 0, 0
.db 7, 0, 0
.db 25, 25, 25
; Data for title screen
.INCLUDE "gfx/title.s"
title_pal_data:
.db 31, 31, 31
.db 25, 15, 15
.db 20, 0, 0
.db 0, 0, 0
.db 20, 0, 0
.db 20, 0, 0
.db 20, 0, 0
.db 31, 31, 31
.ENDS
|
agranlund/wolf
| 5,050
|
z80/sound.s
|
; Wolfenstein 3D for Gameboy Color
; (c) 2017, Anders Granlund
; www.happydaze.se
;
; This program is free software; you can redistribute it and/or
; modify it under the terms of the GNU General Public License
; as published by the Free Software Foundation; either version 2
; of the License, or (at your option) any later version.
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
;
; snd_init :
; snd_update :
; snd_play_music : A=song
; snd_stop_music :
; snd_pause_music : A=status (1 = paused, 0 = resume)
; snd_play_fx : A=effect
; snd_stop_fx :
;
.INCLUDE "defines.i"
.IF ENABLE_SOUND == 1
;
; Sound FX data
;
.BANK 2 SLOT SLOT_ROM_BANKED
.ORG $0000
.SECTION "!SOUND_DATA" FREE
SoundFX_Bank:
.INCBIN "sound/fxbank.bin"
.ENDS
;
; Music data
;
.BANK 3 SLOT SLOT_ROM_BANKED
.ORG $0000
.SECTION "!MUSIC_MENU" SEMIFREE
.INCLUDE "music/mus_menu.s"
.ENDS
.BANK 4 SLOT SLOT_ROM_BANKED
.ORG $0000
.SECTION "!MUSIC_MAP1" SEMIFREE
.INCLUDE "music/mus_map1.s"
.ENDS
.BANK 4 SLOT SLOT_ROM_BANKED
.ORG $0000
.SECTION "!MUSIC_MAP2" SEMIFREE
.INCLUDE "music/mus_map2.s"
.ENDS
.BANK 5 SLOT SLOT_ROM_BANKED
.ORG $0000
.SECTION "!MUSIC_MAP3" SEMIFREE
.INCLUDE "music/mus_map3.s"
.ENDS
.BANK 6 SLOT SLOT_ROM_BANKED
.ORG $0000
.SECTION "!MUSIC_MAP4" SEMIFREE
.INCLUDE "music/mus_map4.s"
.ENDS
.BANK 5 SLOT SLOT_ROM_BANKED
.ORG $0000
.SECTION "!MUSIC_MAP0" SEMIFREE
.INCLUDE "music/mus_map0.s"
.ENDS
;
; Song list
;
.MACRO SONG
.DW :\1, \1
.ENDM
.BANK 0 SLOT 0
.SECTION "!SONG_LIST", FREE
song_list:
SONG mus_menu_data ; 0 - Menu
SONG mus_map1_data ; 1 - Map1_1
SONG mus_map2_data ; 2 - Map1_2
SONG mus_map3_data ; 3 - Map1_3
SONG mus_map4_data ; 4 - Map1_4
;SONG mus_map9_data ; 5 - Map1_9
SONG mus_map0_data ; 5 - Map1_0
.ENDS
.ENDIF
;
; variables
;
.RAMSECTION "sound_vars" BANK 0 SLOT SLOT_RAM
snd_fxplaying DB
.ENDS
;
; FXHammer variables
;
.RAMSECTION "GBT_VAR_1" BANK 0 SLOT SLOT_RAM_FXHAMMER
FXCurrentPri DB ; current prio ($00 = lowest)
FXSoundCount DB ; countdown
FXSoundP DB ; current step
FXSoundH DB ; current sound + $44
.ENDS
.EQU SoundFX_Trig $4000
.EQU SoundFX_Stop $4003
.EQU SoundFX_Update $4006
;
; Sound code
;
.BANK 0 SLOT SLOT_ROM
.ORG $200
.SECTION "sound_code" FREE
;
; init sound engine
;
snd_init:
xor a
ld (snd_fxplaying), a
.IF ENABLE_SOUND == 1
call gbt_enable_channels
call snd_stop_music
.ENDIF
ret
;
; update sound engine, call at 60hz
;
snd_update:
.IF ENABLE_SOUND == 1
; update music
call gbt_update
; update soundFX
ld a, :SoundFX_Bank
ld ($2000), a
call SoundFX_Update
; enable music on all channels after soundfx has finished
ld a, (snd_fxplaying)
or a
ret z
ld a, (FXSoundCount)
or a
ret nz
xor a
ld (snd_fxplaying), a
ld a, %00001111
call gbt_enable_channels
.ENDIF
ret
;
; play music, A = song number
;
snd_play_music:
.IF ENABLE_SOUND == 1
push af
call snd_stop_music
ld a, %00001111
call gbt_enable_channels
xor a
call snd_pause_music
pop af
ld b, 0
ld c, a
sla c
sla c
ld hl, song_list
add hl, bc
ldi a, (hl)
ld c, a
ldi a, (hl)
ld b, a ; bc = bank
ldi a, (hl)
ld e, a
ldi a, (hl)
ld d, a ; de = addr
ld a, 2 ; a = default speed
call gbt_play
ld a, 1 ; loop enable
call gbt_loop
.ENDIF
ret
;
; pause music, A = state (1 = pause, 0 = resume)
;
snd_pause_music:
push af
.IF ENABLE_SOUND == 1
call gbt_pause
.ENDIF
pop af
cp 0
jr z, +
xor a
ld [NR50], a
ret
+ ld a, $77
ld [NR50], a
ret
;
; stop music
;
snd_stop_music:
.IF ENABLE_SOUND == 1
call gbt_stop
ld a,$80
ld [NR52],a
ld a,$00
ld [NR51],a
ld a,$00
ld [NR50],a
xor a
ld [NR10],a
ld [NR11],a
ld [NR12],a
ld [NR13],a
ld [NR14],a
ld [NR21],a
ld [NR22],a
ld [NR23],a
ld [NR24],a
ld [NR30],a
ld [NR31],a
ld [NR32],a
ld [NR33],a
ld [NR34],a
ld [NR41],a
ld [NR42],a
ld [NR43],a
ld [NR44],a
ld a,$77
ld [NR50],a
.ENDIF
ret
;
; play effect, A = effect number
;
snd_play_fx:
.IF ENABLE_SOUND == 1
ld b, a
ld a, :SoundFX_Bank
ld ($2000), a
ld a, %00000101 ; disable music on channels 2+4
call gbt_enable_channels
ld a,%01010101
ld (NR51), a
ld a, b
call SoundFX_Trig
ld a, 1
ld (snd_fxplaying), a
.ENDIF
ret
;
; stop effect
;
snd_stop_fx:
.IF ENABLE_SOUND == 1
ld a, :SoundFX_Bank
ld ($2000), a
call SoundFX_Stop
ld a, %00001111 ; enable music on all channels
call gbt_enable_channels
xor a
ld (snd_fxplaying), a
.ENDIF
ret
.ENDS
|
agranlund/wolf
| 44,080
|
z80/game.s
|
; Wolfenstein 3D for Gameboy Color
; (c) 2017, Anders Granlund
; www.happydaze.se
;
; This program is free software; you can redistribute it and/or
; modify it under the terms of the GNU General Public License
; as published by the Free Software Foundation; either version 2
; of the License, or (at your option) any later version.
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
.INCLUDE "defines.i"
;
; constants
;
.DEFINE WOLF_FRAMEBUFFER $A000
.DEFINE WOLF_BGMAPBUFFER $B000
.DEFINE WOLF_CMDBUFFER_WR $B400
.DEFINE WOLF_CMDBUFFER_RD $B800
.DEFINE WOLF_Y_OFFSET 1
.DEFINE WOLF_MAP_OFFSET (WOLF_Y_OFFSET * 32)
.DEFINE WOLF_NUMTILES_X 20
.DEFINE WOLF_NUMTILES_Y 12
.DEFINE WOLF_LAST_Y_LINE (((WOLF_Y_OFFSET + WOLF_NUMTILES_Y) * 8) - 1)
.DEFINE WOLF_NUMTILES (WOLF_NUMTILES_X * WOLF_NUMTILES_Y)
.DEFINE WOLF_VRAM $8800
.DEFINE WOLF_DMA_COUNT1 112
.DEFINE WOLF_DMA_COUNT2 128
.DEFINE WOLF_TRIGGER_REG $4000
.DEFINE HUD_DIRTY_LIVES %10000000
.DEFINE HUD_DIRTY_FLOOR %01000000
.DEFINE HUD_DIRTY_HEALTH %00100000
.DEFINE HUD_DIRTY_KEYS %00010000
.DEFINE HUD_DIRTY_WEAPON %00001000
.DEFINE HUD_DIRTY_AMMO %00000100
.DEFINE HUD_DIRTY_HANDS %00000010
;
; variables
;
.RAMSECTION "vars" BANK 0 SLOT SLOT_RAM
backbuffer DB
wolf_lcdc DB
hud_map_addr DS 1
tempbuf DS 16
keys DS 1
health DS 1
lives DS 1
floor DS 1
ammo DS 1
guns DS 1
weapon DS 1
weapon_frame DS 1
hud_dirty DS 1
fade_cnt DS 1
fade_type DS 1 ; 1=dmg, 2=in_black, 3=in_red
death_trigger DS 1
gameover_trigger DS 1
victory_trigger DS 1
floordone_trigger DS 1
floordone_next DS 1
stat_kill_ratio DS 1
stat_secret_ratio DS 1
stat_bonus_ratio DS 1
stat_score DS 2
cheat_godmode DS 1
cheat_guns DS 1
start_floor DS 1
pwd_start DS 1
paused DS 1
dbg_music DS 1
.ENDS
.BANK 0 SLOT SLOT_ROM
;
; LCD Interrupt
;
.org $48
jp irq_lcd
.ORG $150
.SECTION "Game" SEMIFREE
irq_lcd:
di
push af
ldh a, (R_LY)
cp WOLF_LAST_Y_LINE
jr nz, +
; lcdc interrupt at start of lower hud
ld a, (wolf_lcdc)
or %00011010
ldh (R_LCDC), a ; select chr data from $8000, enable sprites
+ pop af
ei
reti
;
; Main loop
;
game_setup_tiles:
; clear all palettes to black
ld hl, PAL_BLACK
ld bc, 8
call gfx_pal_copy_bg
ld hl, PAL_BLACK
ld bc, 8
call gfx_pal_copy_obj
; load general sprite chr
ld a, 1
ldh (R_VBK), a
ld a, :HUD_OBJ_CHR
ld ($2000), a
ld hl, $8000 + (112 * 16)
ld de, HUD_OBJ_CHR
ld c, 16
call gfx_chr_copy
xor a
ldh (R_VBK), a
; load upper hud chr
ld hl, $9700
ld de, HUD_BG_CHR + (16 * 112)
ld c, 16
call gfx_chr_copy
; load lower hud chr to$8000
ld hl, $8000
ld de, HUD_BG_CHR
ld c, 128
call gfx_chr_copy
; load upper+lower hud map
ld hl, $9800
ld de, HUD_BG_MAP
call gfx_map_copy_20x18
ld hl, $9C00
ld de, HUD_BG_MAP
call gfx_map_copy_20x18
; setup maps for double buffering the wolf graphics
; $9800 references tiles from vram bank 0, $8800
; $9C00 references tiles from vram bank 1, $8800
call wolf_init_map
ret
game_setup_interrupts:
xor a
ldh (R_IF), a
ld a, WOLF_LAST_Y_LINE ; interrupt at last line of wolf gfx
ldh (R_LYC), a
ld a, %00001000 ; hblank interrupt
ldh (R_STAT), a
ld a, %00000010 ; lcd interrupt
ldh (R_IE), a
call sys_wait_vbl
ei
ret
game_start_music:
ld a, (floor)
ld e, a
ld d, 0
ld hl, game_music_table
add hl, de
ld a, (hl)
call snd_play_music
ret
game_music_table:
.db 5, 1, 2, 3, 4, 1, 2, 3, 4, 5
game:
game_main:
; init variables
ld a, (pwd_start)
cp 0
jr z, +
; continue
ld a, (tempbuf+0)
call hud_set_lives
ld a, (tempbuf+1)
call hud_set_floor
ld a, (tempbuf+2)
call hud_set_health
ld a, (tempbuf+3)
call hud_set_guns
ld a, (tempbuf+4)
call hud_set_ammo
jr ++
; new game
+ ld a, 3
call hud_set_lives
ld a, (start_floor)
call hud_set_floor
ld a, 100
call hud_set_health
ld a, 1
call hud_set_guns
ld a, 8
call hud_set_ammo
++ ld a, 1
ld (backbuffer), a
ld a, 0
call hud_set_keys
ld a, 1
call hud_set_weapon
ld a, 2
ld (weapon_frame), a
ld a, $FF
ld (hud_dirty), a
xor a
ld (stat_kill_ratio), a
ld (stat_bonus_ratio), a
ld (stat_secret_ratio), a
ld (stat_score), a
ld (stat_score+1), a
ld a, $1
ld (dbg_music), a
xor a
ld (paused), a
xor a
ld (death_trigger), a
ld (gameover_trigger), a
ld (victory_trigger), a
ld (floordone_trigger), a
ld (floordone_next), a
ld a, 0
ld (fade_cnt), a
ld a, 2
ld (fade_type), a
; clear sram
ld a, $0A
ld ($0000), a
ld bc, $2000
ld hl, $A000
xor a
- ldi (hl), a
dec c
jr nz, -
dec b
jr nz, -
ld ($0000), a
call game_setup_tiles
; setup display parameters
LD a, %10000011
ldh (R_LCDC), a ; screen on
; window map $9800-$9BFF
; window off
; bg chr data $8800-97FF
; bg map data $9800-9BFF
; obj size 8x8
; obj off
; bg on
ld (wolf_lcdc), a
; cpu speed
call sys_cpu_2mhz
; init wolf chip
call wolf_init
; start game
ld a, $0A ; enable sram
ld ($0000), a
ld hl, WOLF_CMDBUFFER_WR
ld a, (cheat_godmode)
sla a
sla a
ld b, a
ld a, (cheat_guns)
sla a
ld c, a
ld a, 1
or b ; cheat_guns
or c ; cheat_godmode
ldi (hl), a
ld a, (lives)
ldi (hl), a
ld a, (floor)
ldi (hl), a
ld a, (health)
ldi (hl), a
ld a, (guns)
ldi (hl), a
ld a, (ammo)
ldi (hl), a
ld a, (backbuffer)
ldi (hl), a
ld a, 0
ldi (hl), a
ld hl, WOLF_CMDBUFFER_RD ; clear rd buffer
xor a
ldi (hl), a
ld (hl), a
ld ($0000), a
call wolf_trigger ; trigger wolf
ld bc, 2
call sys_delay ; wait for result
call wolf_get_result ; handle reponse from wolf
ld a, $FF ; update hud
ld (hud_dirty), a
call hud_update
call game_setup_interrupts
call game_start_music
_main_loop:
; gameover
ld a, (gameover_trigger)
cp 0
jr z, +
xor a
ld (fade_cnt), a
ld (gameover_trigger), a
call snd_stop_music
call hud_fade_gameover
jp gameover
; death
+ ld a, (death_trigger)
cp 0
jr z, +
xor a
ld (fade_cnt), a
ld (death_trigger), a
call snd_stop_music
call hud_fade_death
; victory
+ ld a, (victory_trigger)
cp 0
jr z, +
xor a
ld (fade_cnt), a
ld (victory_trigger), a
call snd_stop_music
call hud_fade_victory
jp victory
; floor complete
+ ld a, (floordone_trigger)
cp 0
jr z, +
xor a
ld (fade_cnt), a
ld (floordone_trigger), a
call snd_stop_music
call hud_fade_floordone
call elevator
call game_setup_tiles
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call game_setup_interrupts
ld a, 2
ld (fade_type), a
+
;--------------------------------------
; frame 0
;--------------------------------------
; update joypad
call sys_update_joypad
; --- debug ---
jr +++
ld a, (g_joypad_trigger)
bit 2, a
jr z, ++
ld a, (dbg_music)
inc a
cp 6
jr c, +
xor a
+ ld (dbg_music), a
call snd_play_music
++ ld a, (g_joypad_trigger)
bit 0, a
jr z, +
ld a, $1
call snd_play_fx
+ ld a, (g_joypad_trigger)
bit 1, a
jr z, +++
ld a, $10
call snd_play_fx
+++
; pause
ld a, (g_joypad_trigger)
bit 3, a
call nz, pause
; send command buffer
ld a, $0A ; enable sram
ld ($0000), a
ld hl, WOLF_CMDBUFFER_WR
ld a, 0 ; WOLF_CMDBUFFER + 0 : init game
ldi (hl), a
ld a, (backbuffer) ; WOLF_CMDBUFFER + 1 : backbuffer index
ldi (hl), a
ld a, (g_joypad_status) ; WOLF_CMDBUFFER + 2 : joypad status
ldi (hl), a
; prepare read buffer
ld hl, WOLF_CMDBUFFER_RD
xor a
ldi (hl), a
ld (hl), a
; disable sram
ld ($0000), a
; wake the wolf
call wolf_trigger
; update sound
call snd_update
; update fade
call hud_update_fade1
; update hud
call hud_update
call sys_wait_vbl
;--------------------------------------
; vblank1
;--------------------------------------
di
; restore wolf tile numbering
ld a, (wolf_lcdc)
ldh (R_LCDC), a
; set backbuffer vram bank
ld de, backbuffer
ld a, (de)
ld b, a
ldh (R_VBK), a
; enable sram
ld a, $0A
ld ($0000), a
; dma bg tiles 0-111 = ~965us
ld hl, WOLF_FRAMEBUFFER
ld a, h
ldh (R_HDMA1), a
ld a, l
and %11111000
ldh (R_HDMA2), a
ld hl, WOLF_VRAM - $8000
ld a, h
and %00011111
ldh (R_HDMA3), a
ld a, l
ldh (R_HDMA4), a
ld a, WOLF_DMA_COUNT1-1
ldh (R_HDMA5), a
; disable sram
xor a
ld ($0000), a
; dma oam attributes = ~200us
call gfx_oam_update
;--------------------------------------
; frame1
;--------------------------------------
; vram bank 1 (map attributes)
ld a, 1
ldh (R_VBK), a
; enable sram
ld a, $0A
ld ($0000), a
; dma map attributes: ~24 scanlines (32*12 = 384 bytes)
ld hl, WOLF_BGMAPBUFFER
ld a, h
ldh (R_HDMA1), a
ld a, l
and %11111000
ldh (R_HDMA2), a
ld hl, $9800 + WOLF_MAP_OFFSET
ld a, (de)
or a
jr z, +
ld hl, $9C00 + WOLF_MAP_OFFSET
+ ld a, h
and %00011111
ldh (R_HDMA3), a
ld a, l
ldh (R_HDMA4), a
ld a, $97 ; bit7=1, bit0:6 = 23 ((32*12) / 16) - 1
ldh (R_HDMA5), a
; wait for dma completion
- ldh a, (R_HDMA5)
and %10000000
jr z, -
; disable sram
xor a
ld ($0000), a
; restore vram bank
xor a
ldh (R_VBK), a
ei
; update sound
call snd_update
; update fade
call hud_update_fade2
; read wolf result
call wolf_get_result
call sys_wait_vbl
;--------------------------------------
; vblank2
;--------------------------------------
di
; restore wolf tile numbering
ld a, (wolf_lcdc)
ldh (R_LCDC), a
; set backbuffer vram bank
ld de, backbuffer
ld a, (de)
ld b, a
ldh (R_VBK), a
; enable sram
ld a, $0A
ld ($0000), a
; dma bg tiles 112-239 = ~1087us
ld hl, WOLF_FRAMEBUFFER + (WOLF_DMA_COUNT1 * 16)
ld a, h
ldh (R_HDMA1), a
ld a, l
and %11111000
ldh (R_HDMA2), a
ld hl, WOLF_VRAM - $8000 + (WOLF_DMA_COUNT1 * 16)
ld a, h
and %00011111
ldh (R_HDMA3), a
ld a, l
ldh (R_HDMA4), a
ld a, WOLF_DMA_COUNT2-1
ldh (R_HDMA5), a
; disable sram
xor a
ld ($0000), a
; restore vram bank
xor a
ldh (R_VBK), a
; swap front and back buffers
ld a, b
inc a
and %00000001
ld (de),a
ld hl, wolf_lcdc
ld a, (hl)
and %11110111
sla b
sla b
sla b
or b
ldh (R_LCDC), a
ld (hl), a
ei
jp _main_loop
; pause
pause:
xor a
ld [NR51], a
ld hl, HUD_PAUSE_PAL
ld bc, 6
call gfx_pal_copy_bg
ld hl, HUD_PAUSE_PAL
ld bc, 4
call gfx_pal_copy_obj
ld a, 1
ld (paused), a
xor a
ld (tempbuf+0), a
ld a, 1
ld (tempbuf+1), a
- call sys_update_joypad
ld a, (g_joypad_trigger)
bit 3, a
jr z, +
xor a
ld (paused), a
ld (tempbuf+0), a
ld (tempbuf+1), a
+ ld a, (tempbuf+0)
inc a
cp 60
jr c, +
ld hl, tempbuf+1
inc (hl)
xor a
+ ld (tempbuf+0), a
ld de, 4
ld a, (tempbuf+1)
and 1
cp 0
jr z, +
ld a, 64
+ ld hl, oam + (30 * 4) + 0
.REPT 6
ld (hl), a
add hl, de
.ENDR
ld hl, oam + (30 * 4) + 1
ld a, 64
.REPT 6
ld (hl), a
add hl, de
add 8
.ENDR
ld hl, oam + (30 * 4) + 2
ld a, 115
.REPT 6
ld (hl), a
inc a
add hl, de
.ENDR
ld hl, oam + (30 * 4) + 3
ld a, %00001111
.REPT 6
ld (hl), a
add hl, de
.ENDR
call sys_wait_vbl
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call gfx_oam_update
ld a, (paused)
or a
jp nz, -
; restore palette
ld hl, HUD_BG_PAL
ld bc, 8
call gfx_pal_copy_bg
ld hl, HUD_OBJ_PAL
ld bc, 8
call gfx_pal_copy_obj
ret
; set weapon. A = weapon index
hud_set_weapon:
and 3
ld (weapon), a
ld a, (hud_dirty)
or HUD_DIRTY_WEAPON | HUD_DIRTY_AMMO | HUD_DIRTY_HANDS
ld (hud_dirty), a
ret
; set weapon frame. A = frame index
hud_set_weapon_frame:
ld (weapon_frame), a
ld a, (hud_dirty)
or HUD_DIRTY_HANDS
ld (hud_dirty), a
ret
; set keys. A = key bitfield
hud_set_keys:
and $3
ld (keys), a
ld a, (hud_dirty)
or HUD_DIRTY_KEYS
ld (hud_dirty), a
ret
; a = weapon index, de = ammo count
hud_set_ammo:
cp 99
jr c, +
ld a, 99
+ ld (ammo), a
ld a, (hud_dirty)
or HUD_DIRTY_AMMO
ld (hud_dirty), a
ret
; a = gun mask (1=gun, 2=machinegun, 4=minigun)
hud_set_guns:
ld (guns), a
ret
; a = health
hud_set_health:
cp 100
jr c, +
ld a, 100
+ ld (health), a
ld a, (hud_dirty)
or HUD_DIRTY_HEALTH
ld (hud_dirty), a
ret
; a = lives
hud_set_lives:
cp 9
jr c, +
ld a, 9
+ ld (lives), a
ld a, (hud_dirty)
or HUD_DIRTY_LIVES
ld (hud_dirty), a
ret
; a = floor
hud_set_floor:
cp 9
jr c, +
ld a, 9
+ ld (floor), a
ld a, (hud_dirty)
or HUD_DIRTY_FLOOR
ld (hud_dirty), a
call game_start_music
ret
hud_update:
ld a, (hud_dirty)
cp 0
ret z
and HUD_DIRTY_LIVES
call nz, hud_update_lives
ld a, (hud_dirty)
and HUD_DIRTY_FLOOR
call nz, hud_update_floor
ld a, (hud_dirty)
and HUD_DIRTY_HEALTH
call nz, hud_update_health
ld a, (hud_dirty)
and HUD_DIRTY_KEYS
call nz, hud_update_keys
ld a, (hud_dirty)
and HUD_DIRTY_WEAPON
call nz, hud_update_weapon
ld a, (hud_dirty)
and HUD_DIRTY_AMMO
call nz, hud_update_ammo
ld a, (hud_dirty)
and HUD_DIRTY_HANDS
call nz, hud_update_hands
xor a
ld (hud_dirty), a
ret
hud_update_hands:
ld a, (weapon)
sla a
sla a
sla a
ld e, a
ld a, (weapon_frame)
sla a
add e
ld e, a
ld d, 0
ld hl, WPN_FRAME_TABLE
add hl, de
ldi a, (hl)
ld h, (hl)
ld l, a ; hl = weapon tiles
ldi a, (hl)
ld c, a ; c = num oam entries
; hide unused sprites
ld a, 32
sub c
ld b, a
xor a
ld de, oam + (31 * 4)
- ld (de), a
dec de
dec de
dec de
dec de
dec b
jr nz, -
; assign used sprites
ld de, oam
- ldi a, (hl) ; ypos
ld (de), a
inc de
ldi a, (hl) ; xpos
ld (de), a
inc de
ldi a, (hl) ; tile
ld (de), a
inc de
ldi a, (hl) ; attr
ld (de), a
inc de
dec c
jr nz, -
ret
hud_update_lives:
ld a, (hud_dirty)
and HUD_DIRTY_LIVES
ret z
ld hl, $9800 + 2
ld de, $9C00 - $9800
ld a, (lives)
add 115
ld b, a
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, b
ld (hl), a
add hl, de
ld (hl), a
ret
hud_update_floor:
ld hl, $9800 + 18
ld de, $9C00 - $9800
ld a, (floor)
add 115
ld b, a
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, b
ld (hl), a
add hl, de
ld (hl), a
ret
hud_update_health:
ld a, (health)
ld e, a
ld d, 0
ld bc, 100
call sys_div_16x16 ; de = health/100, bc = remainder
ld a, e
ld (tempbuf), a
ld d, b
ld e, c
ld bc, 10
call sys_div_16x16 ; de = health/10, bc = remainder
ld hl, tempbuf+1
ld a, e
ldi (hl), a
ld a, c
ldd (hl), a
dec hl
ld d, h
ld e, l
ld hl, $9C00 + 5 + (15 * 32)
ld b, 0
ld c, 3
-- ld a, (de)
or b
jr nz, +
ld a, 14 ; bank tile = 14+15
jr ++
+ ld a, (de)
ld b, $FF
sla a
add 32 ; tile = 32 + (digit * 2)
++ push hl
push de
push af
- ldh a, (R_STAT)
and $02
jr nz, -
pop af
ld (hl), a
ld de, 32
add hl, de
inc a
ld (hl), a
pop de
pop hl
inc de
inc hl
dec c
jr nz, --
ret
hud_update_weapon:
; reset animation
xor a
ld (weapon_frame), a
; temporarily disable sprites
ld a, (wolf_lcdc)
and %11111101
ldh (R_LCDC), a
; copy weapons graphics to vram
+ ld a, (weapon)
sla a
sla a
ld c, a
ld b, 0
ld hl, WPN_CHR_TABLE
add hl, bc
ldi a, (hl) ; src addr_l
ldh (R_HDMA2), a
ldi a, (hl) ; src_addr_h
ldh (R_HDMA1), a
ldi a, (hl) ; bank
ld ($2000), a
ld c, (hl) ; c = tile count
ld a, 1
ldh (R_VBK), a ; vram bank 1
ld hl, $8000
ld a, h
and %00011111
ldh (R_HDMA3), a ; dst addr_h
ld a, l
ldh (R_HDMA4), a ; dst_addr_l
ld a, %10000000
dec c
or c
ldh (R_HDMA5), a ; start dma
- ldh a, (R_HDMA5) ; wait for dma completion
and %10000000
jr z, -
xor a
ldh (R_VBK), a ; vram bank 0
ret
hud_update_ammo:
ld a, (weapon)
or a
jr nz, +
ld de, 0
jr ++
+ ld hl, ammo
ld e, (hl)
ld d, 0
++ ld bc, 10
call sys_div_16x16 ; de = ammo/10, bc = ammo%10
ld hl, tempbuf
ld a, e
ldi (hl), a
ld a, c
ldd (hl), a
ld de, $9C00 + 13 + (16 * 32)
ld b, 0
ld c, 2
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, (hl)
or b
jr nz, +
ld a, 9
jr ++
+ ld a, (hl)
ld b, $FF
add 16
++ ld (de), a
inc de
inc hl
dec c
jr nz, -
ret
hud_update_keys:
; hide keys
xor a
ld (oam + (36*4)), a
ld (oam + (37*4)), a
ld (oam + (38*4)), a
ld (oam + (39*4)), a
; gold key
ld a, (keys)
ld b, a
bit 0, b
jr z, +
ld hl, oam + (36*4)
ld a, 136
ldi (hl), a
ld a, 88
ldi (hl), a
ld a, 112+1
ldi (hl), a
ld a, %00001101
ldi (hl), a
ld a, 144
ldi (hl), a
ld a, 88
ldi (hl), a
ld a, 112+2
ldi (hl), a
ld a, %00001101
ldi (hl), a
; silver key
+ bit 1, b
ret z
ld hl, oam + (38*4)
ld a, 136
ldi (hl), a
ld a, 96
ldi (hl), a
ld a, 112+1
ldi (hl), a
ld a, %00001100
ldi (hl), a
ld a, 144
ldi (hl), a
ld a, 96
ldi (hl), a
ld a, 112+2
ldi (hl), a
ld a, %00001100
ldi (hl), a
ret
hud_update_fade1:
ld a, (fade_type)
cp 2
jr z, hud_update_fadein_black1
cp 3
jr z, hud_update_fadein_red1
ret
hud_update_fade2:
ld a, (fade_type)
cp 1
jr z, hud_update_fade_dmg
cp 2
jr z, hud_update_fadein_black2
cp 3
jr z, hud_update_fadein_red2
ret
hud_update_fadein_black1:
ld a, (fade_cnt)
- push af
ld hl, PAL_BLACK
ld de, HUD_OBJ_PAL
ld bc, 8
call gfx_pal_fade_obj
pop af
ret
hud_update_fadein_black2:
ld a, (fade_cnt)
- push af
ld hl, PAL_BLACK
ld de, HUD_BG_PAL
ld bc, 8
call gfx_pal_fade_bg
pop af
add 8
cp 129
jr c, +
xor a
ld (fade_type), a
+ ld (fade_cnt), a
ret
hud_update_fadein_red1:
ld a, (fade_cnt)
- push af
ld hl, PAL_RED
ld de, HUD_OBJ_PAL
ld bc, 8
call gfx_pal_fade_obj
pop af
ret
hud_update_fadein_red2:
ld a, (fade_cnt)
- push af
ld hl, PAL_RED
ld de, HUD_BG_PAL
ld bc, 8
call gfx_pal_fade_bg
pop af
add 8
cp 129
jr c, +
xor a
ld (fade_type), a
+ ld (fade_cnt), a
ret
hud_update_fade_dmg:
ld a, (fade_cnt)
inc a
cp 8
jr nz, +
xor a
ld (fade_type), a
+ ld (fade_cnt), a
ld c, a
ld b, 0
ld hl, damagefadetable
add hl, bc
ld a, (hl)
push af
ld hl, HUD_BG_PAL
ld de, PAL_RED
ld b, 0
ld c, 6
call gfx_pal_fade_bg
pop af
ld hl, HUD_OBJ_PAL
ld de, PAL_RED
ld b, 0
ld c, 4
call gfx_pal_fade_obj
ret
damagefadetable:
.db 0, 16, 32, 64, 96, 64, 32, 16
hud_fade_death:
ld a, (fade_cnt)
- push af
call sys_wait_vbl
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call snd_update
pop af
ld hl, HUD_BG_PAL
ld de, PAL_RED
ld bc, 8
push af
call gfx_pal_fade_bg
pop af
push af
call sys_wait_vbl
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call snd_update
pop af
ld hl, HUD_OBJ_PAL
ld de, PAL_RED
ld bc, 8
push af
call gfx_pal_fade_obj
pop af
add 4
cp 129
jr c, -
ld bc, 40
call sys_delay
xor a
ld (fade_cnt), a
ld a, 3
ld (fade_type), a
ret
hud_fade_floordone:
ld a, (fade_cnt)
- push af
call sys_wait_vbl
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call snd_update
pop af
ld hl, HUD_BG_PAL
ld de, PAL_BLACK
ld bc, 8
push af
call gfx_pal_fade_bg
pop af
push af
call sys_wait_vbl
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call snd_update
pop af
ld hl, HUD_OBJ_PAL
ld de, PAL_BLACK
ld bc, 8
push af
call gfx_pal_fade_obj
pop af
add 4
cp 129
jr c, -
ld bc, 40
call sys_delay
xor a
ld (fade_cnt), a
ld (fade_type), a
; temp
ld a, 2
ld (fade_type), a
ret
hud_fade_gameover:
ld a, (fade_cnt)
- push af
call sys_wait_vbl
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call snd_update
pop af
ld hl, HUD_BG_PAL
ld de, PAL_RED
ld bc, 8
push af
call gfx_pal_fade_bg
pop af
push af
call sys_wait_vbl
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call snd_update
pop af
ld hl, HUD_OBJ_PAL
ld de, PAL_RED
ld bc, 8
push af
call gfx_pal_fade_obj
pop af
add 4
cp 129
jr c, -
ld bc, 40
call sys_delay
xor a
ld (fade_type), a
ld (fade_cnt), a
ret
; to black
+ ld a, 0
- push af
call sys_wait_vbl
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call snd_update
pop af
ld hl, PAL_RED
ld de, PAL_BLACK
ld bc, 8
push af
call gfx_pal_fade_bg
pop af
push af
call sys_wait_vbl
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call snd_update
pop af
ld hl, PAL_RED
ld de, PAL_BLACK
ld bc, 8
push af
call gfx_pal_fade_obj
pop af
add 16
cp 129
jr c, -
ld bc, 40
call sys_delay
xor a
ld (fade_type), a
ld (fade_cnt), a
ret
hud_fade_victory:
ld a, (fade_cnt)
- push af
call sys_wait_vbl
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call snd_update
pop af
ld hl, HUD_BG_PAL
ld de, PAL_WHITE
ld bc, 8
push af
call gfx_pal_fade_bg
pop af
push af
call sys_wait_vbl
ld a, (wolf_lcdc)
ldh (R_LCDC), a
call snd_update
pop af
ld hl, HUD_OBJ_PAL
ld de, PAL_WHITE
ld bc, 8
push af
call gfx_pal_fade_obj
pop af
add 4
cp 129
jr c, -
ld bc, 40
call sys_delay
xor a
ld (fade_type), a
ld (fade_cnt), a
ret
wolf_init:
; set RAM banking mode so EA0 and EA1 are stable
ld a, 1
ld ($6000), a
xor a
ld ($4000), a
ret
wolf_trigger:
; wake up KE04 from sleep mode by setting EA0 to high
ld a, 2
ld ($4000), a
xor a
ld ($4000), a
ret
wolf_init_map:
; setup maps for double buffering the wolf graphics
; $9800 references tiles from vram bank 0, $8800
; $9C00 references tiles from vram bank 1, $8800
ld a, %00000000
ld hl, $9800 + WOLF_MAP_OFFSET
call +
ld a, %00001000
ld hl, $9C00 + WOLF_MAP_OFFSET
call +
ret
+ ld d, -128
ld e, a
xor a
ldh (R_VBK), a
ld b, WOLF_NUMTILES_Y
-- ld c, WOLF_NUMTILES_X
- ldh a, (R_STAT)
and $02
jr nz, -
ld a, d
ld (hl), a
ld a, 1
ldh (R_VBK), a
ld a, (hl)
or e
ldi (hl), a
xor a
ldh (R_VBK), a
inc d
dec c
jr nz, -
push bc
ld bc, 32 - WOLF_NUMTILES_X
add hl, bc
pop bc
dec b
jr nz, --
ret
wolf_get_result:
; enable sram
ld a, $0A
ld ($0000), a
; process commands from wolf
ld hl, WOLF_CMDBUFFER_RD
- ldi a, (hl)
cp 0
jr z, ++
sla a
ld e, a
ld d, 0 ; de = cmd
ldi a, (hl)
ld b, a ; b = arg
push hl
ld hl, +
push hl
ld hl, wolfcmd_jumptable
add hl, de
ldi a, (hl)
ld h, (hl)
ld l, a
ld a, b
jp hl
+ pop hl
jr -
; disable sram
++ xor a
ld ($0000), a
ret
wolfcmd_jumptable:
.dw wolfcmd_nop ; 0
.dw snd_play_music ; 1 (a = song)
.dw snd_play_fx ; 2 (a = effect)
.dw snd_stop_music ; 3
.dw wolfcmd_nop ; 4
.dw wolfcmd_nop ; 5
.dw hud_set_weapon ; 6 (a = weapon)
.dw hud_set_weapon_frame ; 7 (a = frame)
.dw hud_set_ammo ; 8 (a = ammo)
.dw hud_set_health ; 9 (a = health)
.dw hud_set_lives ; 10 (a = lives)
.dw hud_set_floor ; 11 (a = floor)
.dw hud_set_keys ; 12 (a = key bitfield)
.dw hud_set_guns ; 13 (a = gun bitfield)
.dw wolfcmd_damage ; 14
.dw wolfcmd_death ; 15
.dw wolfcmd_gameover ; 16
.dw wolfcmd_victory ; 17
.dw wolfcmd_floordone ; 18 (a = next floor)
.dw wolfcmd_killratio ; 19 (a = kill %)
.dw wolfcmd_bonusratio ; 20 (a = bonus %)
.dw wolfcmd_secretratio ; 21 (a = secret %)
.dw wolfcmd_scorehi ; 22 (a = score HI)
.dw wolfcmd_scorelo ; 23 (a = score LO)
wolfcmd_damage:
ld a, 1
ld (fade_type), a
xor a
ld (fade_cnt), a
ret
wolfcmd_death:
ld a, 1
ld (death_trigger), a
ret
wolfcmd_gameover:
xor a
ld (death_trigger), a
ld a, 1
ld (gameover_trigger), a
ret
wolfcmd_victory:
ld a, 1
ld (victory_trigger), a
ret
wolfcmd_floordone:
ld (floordone_next), a
ld a, 1
ld (floordone_trigger), a
ret
wolfcmd_killratio:
ld (stat_kill_ratio), a
ret
wolfcmd_bonusratio:
ld (stat_bonus_ratio), a
ret
wolfcmd_secretratio:
ld (stat_secret_ratio), a
ret
wolfcmd_scorehi:
ld (stat_score), a
ret
wolfcmd_scorelo:
ld (stat_score+1), a
ret
wolfcmd_nop:
ret
.ENDS
;
; data in bank 1
;
.BANK 1 SLOT SLOT_ROM_BANKED
.SECTION "game_data_bank1" SEMIFREE
HUD_OBJ_CHR:
.INCBIN "gfx/obj_chr.bin"
HUD_BG_CHR:
.INCBIN "gfx/bg_chr.bin"
HUD_BG_MAP:
.INCBIN "gfx/bg_map.bin"
.ENDS
.BANK 1 SLOT SLOT_ROM_BANKED
.SECTION "game_data_wpn0" ALIGN 16 SEMIFREE
HUD_KNIFE_CHR:
.INCBIN "gfx/chr_knife.bin"
.ENDS
.BANK 1 SLOT SLOT_ROM_BANKED
.SECTION "game_data_wpn1" ALIGN 16 SEMIFREE
HUD_GUN_CHR:
.INCBIN "gfx/chr_gun.bin"
.ENDS
.BANK 1 SLOT SLOT_ROM_BANKED
.SECTION "game_data_wpn2" ALIGN 16 SEMIFREE
HUD_GUN2_CHR:
.INCBIN "gfx/chr_gun2.bin"
.ENDS
.BANK 1 SLOT SLOT_ROM_BANKED
.SECTION "game_data_wpn3" ALIGN 16 SEMIFREE
HUD_GUN3_CHR:
.INCBIN "gfx/chr_gun3.bin"
.ENDS
;
; data in bank 0
;
.BANK 0 SLOT SLOT_ROM
.SECTION "game_data_bank0" SEMIFREE
; WPNTILE tile, pal, xtile, ytile, xpos
.DEFINE WPN_YPOS WOLF_LAST_Y_LINE
.DEFINE WPN_XPOS_KNIFE 88
.DEFINE WPN_XPOS_GUN 72
.DEFINE WPN_XPOS_GUN2 72
.DEFINE WPN_XPOS_GUN3 64
WPN_CHR_TABLE:
.DW HUD_KNIFE_CHR
.DB :HUD_KNIFE_CHR
.DB 46
.DW HUD_GUN_CHR
.DB :HUD_GUN_CHR
.DB 68
.DW HUD_GUN2_CHR
.DB :HUD_GUN2_CHR
.DB 57
.DW HUD_GUN3_CHR
.DB :HUD_GUN3_CHR
.DB 86
WPN_FRAME_TABLE:
.DW WPN_KNIFE_TILES_0 ; knife
.DW WPN_KNIFE_TILES_1
.DW WPN_KNIFE_TILES_2
.DW WPN_KNIFE_TILES_3
.DW WPN_GUN_TILES_0 ; gun
.DW WPN_GUN_TILES_1
.DW WPN_GUN_TILES_2
.DW WPN_GUN_TILES_3
.DW WPN_GUN2_TILES_0 ; machinegun
.DW WPN_GUN2_TILES_1
.DW WPN_GUN2_TILES_2
.DW WPN_GUN2_TILES_3
.DW WPN_GUN3_TILES_0 ; minigun
.DW WPN_GUN3_TILES_1
.DW WPN_GUN3_TILES_2
.DW WPN_GUN3_TILES_3
.MACRO WPNTILE
.DB WPN_YPOS + 9 - (\4 * 8)
.DB \5 + (\3 * 8)
.DB \1
.DB \2 | %00001000
.ENDM
WPN_KNIFE_TILES_0: ; knife sprites
.DB 3
WPNTILE 15, 0, 1, 0, WPN_XPOS_KNIFE
WPNTILE 16, 0, 2, 0, WPN_XPOS_KNIFE
WPNTILE 17, 0, 1, 1, WPN_XPOS_KNIFE
WPN_KNIFE_TILES_1:
.DB 5
WPNTILE 18, 2, 1, 0, WPN_XPOS_KNIFE
WPNTILE 19, 2, 2, 0, WPN_XPOS_KNIFE
WPNTILE 20, 0, 1, 0, WPN_XPOS_KNIFE
WPNTILE 21, 0, 2, 0, WPN_XPOS_KNIFE
WPNTILE 22, 0, 1, 1, WPN_XPOS_KNIFE
WPN_KNIFE_TILES_2:
.DB 11
WPNTILE 23, 3, 1, 0, WPN_XPOS_KNIFE
WPNTILE 24, 3, 2, 0, WPN_XPOS_KNIFE
WPNTILE 25, 2, 0, 0, WPN_XPOS_KNIFE
WPNTILE 26, 2, 1, 0, WPN_XPOS_KNIFE
WPNTILE 27, 2, 2, 0, WPN_XPOS_KNIFE
WPNTILE 28, 2, 1, 1, WPN_XPOS_KNIFE
WPNTILE 29, 0, 0, 0, WPN_XPOS_KNIFE
WPNTILE 30, 0, 0, 1, WPN_XPOS_KNIFE
WPNTILE 31, 0, 1, 1, WPN_XPOS_KNIFE
WPNTILE 32, 0, 2, 1, WPN_XPOS_KNIFE
WPNTILE 33, 0, 0, 2, WPN_XPOS_KNIFE
WPN_KNIFE_TILES_3:
.DB 12
WPNTILE 34, 3, 1, 0, WPN_XPOS_KNIFE-3
WPNTILE 35, 3, 2, 0, WPN_XPOS_KNIFE-3
WPNTILE 36, 3, 3, 0, WPN_XPOS_KNIFE-3
WPNTILE 37, 3, 1, 1, WPN_XPOS_KNIFE-3
WPNTILE 38, 3, 2, 1, WPN_XPOS_KNIFE-3
WPNTILE 39, 2, 0, 0, WPN_XPOS_KNIFE-3
WPNTILE 40, 2, 0, 1, WPN_XPOS_KNIFE-3
WPNTILE 41, 2, 1, 1, WPN_XPOS_KNIFE-3
WPNTILE 42, 0, 0, 1, WPN_XPOS_KNIFE-3
WPNTILE 43, 0, 1, 1, WPN_XPOS_KNIFE-3
WPNTILE 44, 0, 0, 2, WPN_XPOS_KNIFE-3
WPNTILE 45, 0, 1, 2, WPN_XPOS_KNIFE-3
WPN_GUN_TILES_0: ; gun sprites
.DB 8
WPNTILE 15, 2, 1, 0, WPN_XPOS_GUN
WPNTILE 16, 2, 2, 0, WPN_XPOS_GUN
WPNTILE 17, 0, 1, 0, WPN_XPOS_GUN
WPNTILE 18, 0, 2, 0, WPN_XPOS_GUN
WPNTILE 19, 0, 1, 1, WPN_XPOS_GUN
WPNTILE 20, 0, 2, 1, WPN_XPOS_GUN
WPNTILE 21, 0, 1, 2, WPN_XPOS_GUN
WPNTILE 22, 0, 2, 2, WPN_XPOS_GUN
WPN_GUN_TILES_1:
.DB 12
WPNTILE 23, 3, 0, 0, WPN_XPOS_GUN-1
WPNTILE 24, 3, 1, 0, WPN_XPOS_GUN-1
WPNTILE 25, 3, 2, 0, WPN_XPOS_GUN-1
WPNTILE 26, 3, 3, 0, WPN_XPOS_GUN-1
WPNTILE 27, 2, 1, 0, WPN_XPOS_GUN-1
WPNTILE 28, 2, 2, 0, WPN_XPOS_GUN-1
WPNTILE 29, 2, 1, 1, WPN_XPOS_GUN-1
WPNTILE 30, 2, 2, 1, WPN_XPOS_GUN-1
WPNTILE 31, 0, 1, 1, WPN_XPOS_GUN-1
WPNTILE 32, 0, 2, 1, WPN_XPOS_GUN-1
WPNTILE 33, 0, 1, 2, WPN_XPOS_GUN-1
WPNTILE 34, 0, 2, 2, WPN_XPOS_GUN-1
WPN_GUN_TILES_2:
.DB 17
WPNTILE 35, 3, 1, 0, WPN_XPOS_GUN-2
WPNTILE 36, 3, 2, 0, WPN_XPOS_GUN-2
WPNTILE 37, 3, 3, 0, WPN_XPOS_GUN-2
WPNTILE 38, 2, 1, 0, WPN_XPOS_GUN-2
WPNTILE 39, 2, 2, 0, WPN_XPOS_GUN-2
WPNTILE 40, 2, 3, 0, WPN_XPOS_GUN-2
WPNTILE 41, 2, 1, 1, WPN_XPOS_GUN-2
WPNTILE 42, 2, 2, 1, WPN_XPOS_GUN-2
WPNTILE 43, 2, 3, 1, WPN_XPOS_GUN-2
WPNTILE 44, 0, 1, 1, WPN_XPOS_GUN-2
WPNTILE 45, 0, 2, 1, WPN_XPOS_GUN-2
WPNTILE 46, 0, 1, 2, WPN_XPOS_GUN-2
WPNTILE 47, 0, 2, 2, WPN_XPOS_GUN-2
WPNTILE 48, 1, 1, 2, WPN_XPOS_GUN-2
WPNTILE 49, 1, 2, 2, WPN_XPOS_GUN-2
WPNTILE 50, 1, 1, 3, WPN_XPOS_GUN-2
WPNTILE 51, 1, 2, 3, WPN_XPOS_GUN-2
WPN_GUN_TILES_3:
.DB 16
WPNTILE 52, 3, 1, 0, WPN_XPOS_GUN-3
WPNTILE 53, 3, 2, 0, WPN_XPOS_GUN-3
WPNTILE 54, 3, 3, 0, WPN_XPOS_GUN-3
WPNTILE 55, 2, 1, 0, WPN_XPOS_GUN-3
WPNTILE 56, 2, 2, 0, WPN_XPOS_GUN-3
WPNTILE 57, 2, 3, 0, WPN_XPOS_GUN-3
WPNTILE 58, 2, 1, 1, WPN_XPOS_GUN-3
WPNTILE 59, 2, 2, 1, WPN_XPOS_GUN-3
WPNTILE 60, 2, 3, 1, WPN_XPOS_GUN-3
WPNTILE 61, 2, 1, 2, WPN_XPOS_GUN-3
WPNTILE 62, 2, 3, 2, WPN_XPOS_GUN-3
WPNTILE 63, 0, 1, 1, WPN_XPOS_GUN-3
WPNTILE 64, 0, 2, 1, WPN_XPOS_GUN-3
WPNTILE 65, 0, 1, 2, WPN_XPOS_GUN-3
WPNTILE 66, 0, 2, 2, WPN_XPOS_GUN-3
WPNTILE 67, 0, 2, 3, WPN_XPOS_GUN-3
WPN_GUN2_TILES_0: ; machinegun sprites
.DB 4
WPNTILE 15, 0, 1, 0, WPN_XPOS_GUN2
WPNTILE 16, 0, 2, 0, WPN_XPOS_GUN2
WPNTILE 17, 0, 1, 1, WPN_XPOS_GUN2
WPNTILE 18, 0, 2, 1, WPN_XPOS_GUN2
WPN_GUN2_TILES_1:
.DB 9
WPNTILE 19, 3, 0, 0, WPN_XPOS_GUN2-1
WPNTILE 20, 3, 1, 0, WPN_XPOS_GUN2-1
WPNTILE 21, 2, 1, 0, WPN_XPOS_GUN2-1
WPNTILE 22, 0, 1, 0, WPN_XPOS_GUN2-1
WPNTILE 23, 0, 2, 0, WPN_XPOS_GUN2-1
WPNTILE 24, 0, 3, 0, WPN_XPOS_GUN2-1
WPNTILE 25, 0, 1, 1, WPN_XPOS_GUN2-1
WPNTILE 26, 0, 2, 1, WPN_XPOS_GUN2-1
WPNTILE 27, 0, 2, 2, WPN_XPOS_GUN2-1
WPN_GUN2_TILES_2:
.DB 20
WPNTILE 28, 3, 0, 0, WPN_XPOS_GUN2-2
WPNTILE 29, 3, 1, 0, WPN_XPOS_GUN2-2
WPNTILE 30, 2, 1, 0, WPN_XPOS_GUN2-2
WPNTILE 31, 0, 1, 0, WPN_XPOS_GUN2-2
WPNTILE 32, 0, 2, 0, WPN_XPOS_GUN2-2
WPNTILE 33, 0, 3, 0, WPN_XPOS_GUN2-2
WPNTILE 34, 0, 1, 1, WPN_XPOS_GUN2-2
WPNTILE 35, 0, 2, 1, WPN_XPOS_GUN2-2
WPNTILE 36, 0, 2, 2, WPN_XPOS_GUN2-2
WPNTILE 37, 1, 0, 1, WPN_XPOS_GUN2-2
WPNTILE 38, 1, 1, 1, WPN_XPOS_GUN2-2
WPNTILE 39, 1, 2, 1, WPN_XPOS_GUN2-2
WPNTILE 40, 1, 3, 1, WPN_XPOS_GUN2-2
WPNTILE 41, 1, 4, 1, WPN_XPOS_GUN2-2
WPNTILE 42, 1, 0, 2, WPN_XPOS_GUN2-2
WPNTILE 43, 1, 1, 2, WPN_XPOS_GUN2-2
WPNTILE 44, 1, 2, 2, WPN_XPOS_GUN2-2
WPNTILE 45, 1, 3, 2, WPN_XPOS_GUN2-2
WPNTILE 46, 1, 4, 2, WPN_XPOS_GUN2-2
WPNTILE 47, 1, 2, 3, WPN_XPOS_GUN2-2
WPN_GUN2_TILES_3:
.DB 9
WPNTILE 48, 3, 0, 0, WPN_XPOS_GUN2-3
WPNTILE 49, 3, 1, 0, WPN_XPOS_GUN2-3
WPNTILE 50, 2, 1, 0, WPN_XPOS_GUN2-3
WPNTILE 51, 0, 1, 0, WPN_XPOS_GUN2-3
WPNTILE 52, 0, 2, 0, WPN_XPOS_GUN2-3
WPNTILE 53, 0, 3, 0, WPN_XPOS_GUN2-3
WPNTILE 54, 0, 1, 1, WPN_XPOS_GUN2-3
WPNTILE 55, 0, 2, 1, WPN_XPOS_GUN2-3
WPNTILE 56, 0, 2, 2, WPN_XPOS_GUN2-3
WPN_GUN3_TILES_0: ; minigun sprites
.DB 6
WPNTILE 15, 0, 1, 0, WPN_XPOS_GUN3
WPNTILE 16, 0, 2, 0, WPN_XPOS_GUN3
WPNTILE 17, 0, 3, 0, WPN_XPOS_GUN3
WPNTILE 18, 0, 4, 0, WPN_XPOS_GUN3
WPNTILE 19, 0, 2, 1, WPN_XPOS_GUN3
WPNTILE 20, 0, 3, 1, WPN_XPOS_GUN3
WPN_GUN3_TILES_1: ; minigun sprites
.DB 12
WPNTILE 21, 0, 1, 0, WPN_XPOS_GUN3-1
WPNTILE 22, 0, 2, 0, WPN_XPOS_GUN3-1
WPNTILE 23, 0, 3, 0, WPN_XPOS_GUN3-1
WPNTILE 24, 0, 4, 0, WPN_XPOS_GUN3-1
WPNTILE 25, 0, 5, 0, WPN_XPOS_GUN3-1
WPNTILE 26, 0, 1, 1, WPN_XPOS_GUN3-1
WPNTILE 27, 0, 2, 1, WPN_XPOS_GUN3-1
WPNTILE 28, 0, 3, 1, WPN_XPOS_GUN3-1
WPNTILE 29, 0, 4, 1, WPN_XPOS_GUN3-1
WPNTILE 30, 0, 2, 2, WPN_XPOS_GUN3-1
WPNTILE 31, 0, 3, 2, WPN_XPOS_GUN3-1
WPNTILE 32, 0, 4, 2, WPN_XPOS_GUN3-1
WPN_GUN3_TILES_2: ; minigun sprites
.DB 28
WPNTILE 33, 0, 1, 0, WPN_XPOS_GUN3-2
WPNTILE 34, 0, 2, 0, WPN_XPOS_GUN3-2
WPNTILE 35, 0, 3, 0, WPN_XPOS_GUN3-2
WPNTILE 36, 0, 4, 0, WPN_XPOS_GUN3-2
WPNTILE 37, 0, 5, 0, WPN_XPOS_GUN3-2
WPNTILE 39, 0, 2, 1, WPN_XPOS_GUN3-2
WPNTILE 40, 0, 3, 1, WPN_XPOS_GUN3-2
WPNTILE 41, 0, 4, 1, WPN_XPOS_GUN3-2
WPNTILE 42, 0, 2, 2, WPN_XPOS_GUN3-2
WPNTILE 43, 0, 3, 2, WPN_XPOS_GUN3-2
WPNTILE 38, 0, 4, 2, WPN_XPOS_GUN3-2
WPNTILE 44, 1, 0, 1, WPN_XPOS_GUN3-2
WPNTILE 45, 1, 1, 1, WPN_XPOS_GUN3-2
WPNTILE 46, 1, 2, 1, WPN_XPOS_GUN3-2
WPNTILE 47, 1, 4, 1, WPN_XPOS_GUN3-2
WPNTILE 48, 1, 5, 1, WPN_XPOS_GUN3-2
WPNTILE 49, 1, 6, 1, WPN_XPOS_GUN3-2
WPNTILE 50, 1, 0, 2, WPN_XPOS_GUN3-2
WPNTILE 51, 1, 1, 2, WPN_XPOS_GUN3-2
WPNTILE 52, 1, 2, 2, WPN_XPOS_GUN3-2
WPNTILE 53, 1, 3, 2, WPN_XPOS_GUN3-2
WPNTILE 54, 1, 4, 2, WPN_XPOS_GUN3-2
WPNTILE 55, 1, 5, 2, WPN_XPOS_GUN3-2
WPNTILE 56, 1, 1, 3, WPN_XPOS_GUN3-2
WPNTILE 57, 1, 2, 3, WPN_XPOS_GUN3-2
WPNTILE 58, 1, 3, 3, WPN_XPOS_GUN3-2
WPNTILE 59, 1, 4, 3, WPN_XPOS_GUN3-2
WPNTILE 60, 1, 3, 4, WPN_XPOS_GUN3-2
WPN_GUN3_TILES_3: ; minigun sprites
.DB 25
WPNTILE 61, 0, 1, 0, WPN_XPOS_GUN3-3
WPNTILE 62, 0, 2, 0, WPN_XPOS_GUN3-3
WPNTILE 63, 0, 3, 0, WPN_XPOS_GUN3-3
WPNTILE 64, 0, 4, 0, WPN_XPOS_GUN3-3
WPNTILE 65, 0, 5, 0, WPN_XPOS_GUN3-3
WPNTILE 66, 0, 2, 1, WPN_XPOS_GUN3-3
WPNTILE 67, 0, 3, 1, WPN_XPOS_GUN3-3
WPNTILE 68, 0, 4, 1, WPN_XPOS_GUN3-3
WPNTILE 69, 0, 2, 2, WPN_XPOS_GUN3-3
WPNTILE 70, 0, 3, 2, WPN_XPOS_GUN3-3
WPNTILE 71, 0, 4, 2, WPN_XPOS_GUN3-3
WPNTILE 72, 1, 0, 1, WPN_XPOS_GUN3-3
WPNTILE 73, 1, 1, 1, WPN_XPOS_GUN3-3
WPNTILE 74, 1, 2, 1, WPN_XPOS_GUN3-3
WPNTILE 75, 1, 4, 1, WPN_XPOS_GUN3-3
WPNTILE 76, 1, 5, 1, WPN_XPOS_GUN3-3
WPNTILE 77, 1, 1, 2, WPN_XPOS_GUN3-3
WPNTILE 78, 1, 2, 2, WPN_XPOS_GUN3-3
WPNTILE 79, 1, 3, 2, WPN_XPOS_GUN3-3
WPNTILE 80, 1, 4, 2, WPN_XPOS_GUN3-3
WPNTILE 81, 1, 5, 2, WPN_XPOS_GUN3-3
WPNTILE 82, 1, 2, 3, WPN_XPOS_GUN3-3
WPNTILE 83, 1, 3, 3, WPN_XPOS_GUN3-3
WPNTILE 84, 1, 4, 3, WPN_XPOS_GUN3-3
WPNTILE 85, 1, 3, 4, WPN_XPOS_GUN3-3
; Paused palette
HUD_PAUSE_PAL:
.REPT 8
.db 15, 15, 15
.db 10, 10, 10
.db 5, 5, 5
.db 0, 0, 0
.ENDR
; Background palettes
HUD_BG_PAL:
.db 31, 31, 31 ; 0 gray
.db 20, 20, 20
.db 10, 10, 10
.db 0, 0, 0
.db 31, 0, 0 ; 1 red
.db 20, 20, 20
.db 10, 10, 10
.db 0, 0, 0
.db 0, 31, 0 ; 2 green
.db 20, 20, 20
.db 10, 10, 10
.db 0, 0, 0
.db 0, 0, 31 ; 3 blue
.db 20, 20, 20
.db 10, 10, 10
.db 0, 0, 0
.db 31, 19, 13 ; 4 skin
.db 20, 20, 20
.db 10, 10, 10
.db 0, 0, 0
.db 25, 22, 2 ; 5 gold
.db 20, 20, 20
.db 10, 10, 10
.db 0, 0, 0
.db 31, 31, 31 ; 6 HUD BG
.db 20, 25, 31
.db 5, 10, 31
.db 0, 0, 0
.db 30, 25, 22 ; HUD Face
.db 31, 21, 11
.db 10, 10, 10
.db 22, 8, 0
; Sprite palettes
HUD_OBJ_PAL:
.db 31, 0, 31 ; 0 gun
.db 31, 31, 31
.db 15, 15, 15
.db 0, 0, 0
.db 31, 0, 31 ; 1 fire
.db 31, 31, 0
.db 31, 0, 0
.db 10, 0, 0
.db 31, 0, 31 ; 2 hand
.db 30, 21, 17
.db 31, 19, 8
.db 17, 9, 0
.db 31, 0, 31 ; 3 sleeve
.db 22, 31, 11
.db 21, 28, 0
.db 3, 8, 1
.db 31, 0, 31 ; 4 key1
.db 31, 31, 31
.db 19, 30, 28
.db 0, 0, 0
.db 31, 0, 31 ; 5 key2
.db 31, 31, 31
.db 31, 24, 2
.db 0, 0, 0
.db 31, 0, 31 ; 6 blood
.db 31, 0, 0
.db 22, 0, 0
.db 10, 0, 0
.db 31, 0, 31 ; 7 pause
.db 31, 31, 0
.db 31, 0, 0
.db 0, 0, 0
.ENDS
|
agranlund/wolf
| 10,674
|
z80/sys.s
|
; Wolfenstein 3D for Gameboy Color
; (c) 2017, Anders Granlund
; www.happydaze.se
;
; This program is free software; you can redistribute it and/or
; modify it under the terms of the GNU General Public License
; as published by the Free Software Foundation; either version 2
; of the License, or (at your option) any later version.
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
;
; sys_update_joypad
; sys_cpu_1mhz
; sys_cpu_2mhz
; sys_wait_vbl
; mul_8x8 : DE = B * C
;
.INCLUDE "defines.i"
;
; Variables
;
.RAMSECTION "SysVars" BANK 0 SLOT SLOT_RAM
g_console_type: DB ; 0 = dmg, 1 = gbc, 2 = gba
g_joypad_status: DB ; down.up.right.left.start.select.b.a
g_joypad_trigger: DB ; down.up.right.left.start.select.b.a
temp_div16: DS 2
temp_div16count: DB
.ENDS
;
; Header
;
.BANK 0 SLOT SLOT_ROM
.ORG $100
.SYM "Start"
NOP
JP $150
.SYM "Header"
.DB $CE $ED $66 $66 $CC $0D $00 $0B $03 $73 $00 $83 $00 $0C $00 $0D
.DB $00 $08 $11 $1F $88 $89 $00 $0E $DC $CC $6E $E6 $DD $DD $D9 $99
.DB $BB $BB $67 $63 $6E $0E $EC $CC $DD $DC $99 $9F $BB $B9 $33 $3E
;
; Entry point
;
.ORG $150
.SYM "Entry"
;------------------------------------------
; identify console type (DMG / GBC / GBA)
;------------------------------------------
ld c, 0
sub $11 ; A = 0x11 on GBC/GBA
jr nz, +
inc c
rrc b ; bit 0 of B is 1 on GBA
jr nc, +
inc c
+ ld hl, g_console_type
ld (hl), c
reset:
;------------------------------------------
; init DMG
;------------------------------------------
di ; disable interrupts
ld sp, $FFFE ; set stack pointer
ld a, 1
ld ($2000), a ; ROM bank 1
ld a, %10010000 ; disable window + bg + obj
ldh (R_LCDC), a
xor a
ldh (R_IF), a ; clear irq request flags
ldh (R_IE), a ; disable all interrupt types
ldh (R_SCY), a ; scroll-Y
ldh (R_SCX), a ; scroll-X
ldh (R_NR52), a ; sound circuit disable
ldh (R_BGP), a ; clear bg palette
ldh (R_OBP0), a ; clear obj0 palette
ldh (R_OBP1), a ; clear obj1 palette
ld a, 7
ldh (R_WX),a ; window X position
ld a, 144
ldh (R_WY), a ; window Y position
ld a, (g_console_type)
or a
jp z, MAIN
;------------------------------------------
; init CGB
;------------------------------------------
- ldh a, (R_LY) ; wait vbl
cp $90
jr nz, -
ld b, 8 ; clear cgb bg palette
ld a, %10000000
- ldh (R_BCPS), a
ld c, a
ld a, %11111111
ldh (R_BCPD), a
ldh (R_BCPD), a
ldh (R_BCPD), a
ldh (R_BCPD), a
ldh (R_BCPD), a
ldh (R_BCPD), a
ldh (R_BCPD), a
ldh (R_BCPD), a
ld a, c
add 8
dec b
jr nz, -
ld b, 8 ; clear cgb obj palette
ld a, %10000000
- ldh (R_OCPS), a
ld c, a
ld a, %11111111
ldh (R_OCPD), a
ldh (R_OCPD), a
ldh (R_OCPD), a
ldh (R_OCPD), a
ldh (R_OCPD), a
ldh (R_OCPD), a
ldh (R_OCPD), a
ldh (R_OCPD), a
ld a, c
add 8
dec b
jr nz, -
xor a
ldh (R_VBK), a ; vram bank 0
jp MAIN
.SECTION "sys_code" SEMIFREE
;
; update joypad
;
sys_update_joypad:
ld a, $20
ldh (R_P1), a
ldh a, (R_P1)
ldh a, (R_P1)
cpl
and %00001111
swap a
ld b, a
ld a, $10
ldh (R_P1), a
ldh a, (R_P1)
ldh a, (R_P1)
ldh a, (R_P1)
ldh a, (R_P1)
ldh a, (R_P1)
ldh a, (R_P1)
cpl
and %00001111
or b
ld d, a
ld bc, g_joypad_trigger
ld hl, g_joypad_status
ld a, (hl)
xor d
and d
ld (bc), a
ld (hl), d
ld a, $30
ldh (R_P1), a
ret
;
; cpu speed
;
sys_cpu_1mhz:
ld a, (KEY1)
rlca
ret nc
jr +
sys_cpu_2mhz:
ld a, (KEY1)
rlca
ret c
+ di
ld hl, IE
ld a, (hl)
push af
xor a
ld (hl), a
ld (IF), a
ld a, $30
ld (P1), a
ld a, 1
ld (KEY1), a
stop
nop
pop af
ld (hl), a
ei
ret
;
; wait for vblank
;
sys_wait_vbl:
ldh a, (R_LY)
cp $90
jr nz, sys_wait_vbl
ret
;
; delay BC frames
;
sys_delay:
-- ldh a, (R_LY)
cp $90
jr nz, --
- ldh a, (R_LY)
cp $0
jr nz, -
dec bc
ld a, b
or c
jr nz, --
ret
;
; divide 16/16 -> 16
; DE = DE / BC
; BC remainder
;
sys_div_16x16:
ld hl, temp_div16
ld (hl), c
inc hl
ld (hl), b
inc hl
ld (hl), 17
ld bc, 0
- ld hl, temp_div16count
ld a, e
rla
ld e, a
ld a, d
rla
ld d, a
dec (hl)
ret z
ld a, c
rla
ld c, a
ld a, b
rla
ld b, a
dec hl
dec hl
ld a, c
sub (hl)
ld c, a
inc hl
ld a, b
sbc (hl)
ld b, a
jr nc,+
dec hl
ld a, c
add (hl)
ld c, a
inc hl
ld a, b
adc (hl)
ld b, a
+ ccf
jr -
;
; multiply 8x8->16
; DE = B * C
;
sys_mul_8x8:
ld l, c
ld h, 2
ld d, (hl) ; d = 32 * log_2(c)
ld l, b
ld a, (hl) ; a = 32 * log_2(b)
add d
ld l, a
ld a, 0
adc 0
ld h, a ; hl = d + a
add hl, hl
set 2, h ; hl = hl + $0400
ld e, (hl)
inc hl
ld d, (hl) ; de = 2^([hl]/32)
ret
.ENDS
.ORG $200
_log_table:
.db 0 , 0 , 32 , 50 , 64 , 74 , 82 , 89 , 96 , 101 , 106 , 110 , 114 , 118 , 121
.db 125 , 128 , 130 , 133 , 135 , 138 , 140 , 142 , 144 , 146 , 148 , 150 , 152
.db 153 , 155 , 157 , 158 , 160 , 161 , 162 , 164 , 165 , 166 , 167 , 169 , 170
.db 171 , 172 , 173 , 174 , 175 , 176 , 177 , 178 , 179 , 180 , 181 , 182 , 183
.db 184 , 185 , 185 , 186 , 187 , 188 , 189 , 189 , 190 , 191 , 192 , 192 , 193
.db 194 , 194 , 195 , 196 , 196 , 197 , 198 , 198 , 199 , 199 , 200 , 201 , 201
.db 202 , 202 , 203 , 204 , 204 , 205 , 205 , 206 , 206 , 207 , 207 , 208 , 208
.db 209 , 209 , 210 , 210 , 211 , 211 , 212 , 212 , 213 , 213 , 213 , 214 , 214
.db 215 , 215 , 216 , 216 , 217 , 217 , 217 , 218 , 218 , 219 , 219 , 219 , 220
.db 220 , 221 , 221 , 221 , 222 , 222 , 222 , 223 , 223 , 224 , 224 , 224 , 225
.db 225 , 225 , 226 , 226 , 226 , 227 , 227 , 227 , 228 , 228 , 228 , 229 , 229
.db 229 , 230 , 230 , 230 , 231 , 231 , 231 , 231 , 232 , 232 , 232 , 233 , 233
.db 233 , 234 , 234 , 234 , 234 , 235 , 235 , 235 , 236 , 236 , 236 , 236 , 237
.db 237 , 237 , 237 , 238 , 238 , 238 , 238 , 239 , 239 , 239 , 239 , 240 , 240
.db 240 , 241 , 241 , 241 , 241 , 241 , 242 , 242 , 242 , 242 , 243 , 243 , 243
.db 243 , 244 , 244 , 244 , 244 , 245 , 245 , 245 , 245 , 245 , 246 , 246 , 246
.db 246 , 247 , 247 , 247 , 247 , 247 , 248 , 248 , 248 , 248 , 249 , 249 , 249
.db 249 , 249 , 250 , 250 , 250 , 250 , 250 , 251 , 251 , 251 , 251 , 251 , 252
.db 252 , 252 , 252 , 252 , 253 , 253 , 253 , 253 , 253 , 253 , 254 , 254 , 254
.db 254 , 254 , 255 , 255 , 255 , 255 , 255
.ORG $400
_anti_log_table:
.dw 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 2
.dw 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2
.dw 2 , 2 , 2 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 4 , 4
.dw 4 , 4 , 4 , 4 , 4 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 6
.dw 6 , 6 , 6 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 8 , 9
.dw 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 , 12 , 12 , 12
.dw 13 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17
.dw 18 , 18 , 19 , 19 , 19 , 20 , 20 , 21 , 21 , 22 , 22 , 23 , 23 , 24 , 24 , 25
.dw 25 , 26 , 26 , 27 , 27 , 28 , 29 , 29 , 30 , 31 , 31 , 32 , 33 , 33 , 34 , 35
.dw 36 , 36 , 37 , 38 , 39 , 40 , 41 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49
.dw 50 , 52 , 53 , 54 , 55 , 56 , 57 , 59 , 60 , 61 , 63 , 64 , 65 , 67 , 68 , 70
.dw 71 , 73 , 74 , 76 , 78 , 79 , 81 , 83 , 85 , 87 , 89 , 91 , 92 , 95 , 97 , 99
.dw 101 , 103 , 105 , 108 , 110 , 112 , 115 , 117 , 120 , 123 , 125 , 128 , 131
.dw 134 , 137 , 140 , 143 , 146 , 149 , 152 , 156 , 159 , 162 , 166 , 170 , 173
.dw 177 , 181 , 185 , 189 , 193 , 197 , 202 , 206 , 211 , 215 , 220 , 225 , 230
.dw 235 , 240 , 245 , 251 , 256 , 262 , 267 , 273 , 279 , 285 , 292 , 298 , 304
.dw 311 , 318 , 325 , 332 , 339 , 347 , 354 , 362 , 370 , 378 , 386 , 395 , 403
.dw 412 , 421 , 431 , 440 , 450 , 459 , 470 , 480 , 490 , 501 , 512 , 523 , 535
.dw 546 , 558 , 571 , 583 , 596 , 609 , 622 , 636 , 650 , 664 , 679 , 693 , 709
.dw 724 , 740 , 756 , 773 , 790 , 807 , 825 , 843 , 861 , 880 , 899 , 919 , 939
.dw 960 , 981 , 1002 , 1024 , 1046 , 1069 , 1093 , 1117 , 1141 , 1166 , 1192
.dw 1218 , 1244 , 1272 , 1300 , 1328 , 1357 , 1387 , 1417 , 1448 , 1480 , 1512
.dw 1545 , 1579 , 1614 , 1649 , 1685 , 1722 , 1760 , 1798 , 1838 , 1878 , 1919
.dw 1961 , 2004 , 2048 , 2093 , 2139 , 2186 , 2233 , 2282 , 2332 , 2383 , 2435
.dw 2489 , 2543 , 2599 , 2656 , 2714 , 2774 , 2834 , 2896 , 2960 , 3025 , 3091
.dw 3158 , 3228 , 3298 , 3371 , 3444 , 3520 , 3597 , 3676 , 3756 , 3838 , 3922
.dw 4008 , 4096 , 4186 , 4277 , 4371 , 4467 , 4565 , 4664 , 4767 , 4871 , 4978
.dw 5087 , 5198 , 5312 , 5428 , 5547 , 5668 , 5793 , 5919 , 6049 , 6182 , 6317
.dw 6455 , 6597 , 6741 , 6889 , 7039 , 7194 , 7351 , 7512 , 7677 , 7845 , 8016
.dw 8192 , 8371 , 8555 , 8742 , 8933 , 9129 , 9329 , 9533 , 9742 , 9955 , 10173
.dw 10396 , 10624 , 10856 , 11094 , 11337 , 11585 , 11839 , 12098 , 12363 , 12634
.dw 12910 , 13193 , 13482 , 13777 , 14079 , 14387 , 14702 , 15024 , 15353 , 15689
.dw 16033 , 16384 , 16743 , 17109 , 17484 , 17867 , 18258 , 18658 , 19066 , 19484
.dw 19911 , 20347 , 20792 , 21247 , 21713 , 22188 , 22674 , 23170 , 23678 , 24196
.dw 24726 , 25268 , 25821 , 26386 , 26964 , 27554 , 28158 , 28774 , 29404 , 30048
.dw 30706 , 31379 , 32066 , 32768 , 33485 , 34219 , 34968 , 35734 , 36516 , 37316
.dw 38133 , 38968 , 39821 , 40693 , 41584 , 42495 , 43425 , 44376 , 45348 , 46341
.dw 47356 , 48393 , 49452 , 50535 , 51642 , 52772 , 53928 , 55109 , 56316 , 57549
.dw 58809 , 60097 , 61413 , 62757
|
agranlund/wolf
| 10,810
|
z80/gfx/legal.s
|
; ///////////////////////
; // //
; // File Attributes //
; // //
; ///////////////////////
; Filename: legal.bmp
; Pixel Width: 160px
; Pixel Height: 144px
; /////////////////
; // //
; // Constants //
; // //
; /////////////////
.EQU legal_tile_map_size $0168
.EQU legal_tile_map_width $14
.EQU legal_tile_map_height $12
.EQU legal_tile_data_size $07E0
.EQU legal_tile_count $0168
; ////////////////
; // //
; // Map Data //
; // //
; ////////////////
legal_map_data:
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$01,$02,$03,$04,$05,$06,$00,$00,$07,$08
.DB $09,$0A,$00,$0B,$0C,$0D,$00,$00,$00,$00,$0E,$0F,$10,$11,$12,$13
.DB $14,$15,$16,$17,$18,$19,$1A,$1B,$1C,$1D,$00,$00,$00,$00,$1E,$1F
.DB $20,$21,$22,$23,$24,$25,$26,$27,$28,$29,$2A,$2B,$2C,$2D,$00,$00
.DB $00,$00,$00,$00,$00,$00,$2E,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$2F,$30,$31,$32,$33,$34
.DB $35,$30,$36,$37,$38,$39,$3A,$3B,$3C,$3D,$00,$00,$00,$3A,$3E,$3F
.DB $40,$41,$42,$43,$44,$3A,$3E,$45,$46,$47,$48,$49,$4A,$4B,$4C,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$4D,$4E,$4F,$50
.DB $51,$52,$53,$54,$55,$56,$57,$58,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$59,$5A,$5B,$5C,$5D,$5E,$5F,$60,$5B,$61
.DB $62,$63,$64,$65,$66,$67,$58,$00,$00,$00,$00,$00,$68,$69,$6A,$6B
.DB $6C,$62,$6D,$6E,$6F,$70,$71,$5B,$00,$00,$00,$00,$00,$00,$72,$73
.DB $74,$75,$76,$6C,$62,$6A,$77,$78,$79,$78,$7A,$7B,$7C,$7D,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00
.REPT 20*18
.DB $00
.ENDR
; /////////////////
; // //
; // Tile Data //
; // //
; /////////////////
legal_tile_data:
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$08,$30,$78,$3C
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$10,$61,$6B,$F1
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$40,$80,$C0,$E0
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$06,$03,$07,$07
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$80,$01,$45,$83
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$E0,$C0,$E0,$F0
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$03,$01
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$C0,$00,$A0,$C0
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$03,$07,$03
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$80,$00,$80,$C0
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$07,$00,$07,$07,$07,$0F
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$F0,$00,$E0,$F8,$E8,$D0
.DB $00,$00,$00,$00,$00,$00,$00,$00,$04,$08,$0C,$1E,$3D,$1E,$3C,$1F
.DB $39,$7E,$39,$7E,$19,$3E,$18,$3E,$18,$3E,$18,$3E,$18,$3E,$18,$3E
.DB $F5,$FB,$F1,$FF,$F2,$7D,$71,$7C,$70,$7C,$F4,$78,$F5,$78,$E4,$79
.DB $D0,$E0,$C0,$F1,$C7,$F3,$C9,$F7,$E0,$DF,$B3,$DC,$DA,$BC,$1A,$FC
.DB $0F,$07,$43,$87,$D7,$E3,$EB,$F3,$E7,$FB,$77,$FB,$73,$7F,$3B,$77
.DB $14,$CF,$0E,$DD,$2C,$DF,$1C,$FF,$2E,$DD,$0C,$DF,$0D,$DE,$0D,$DE
.DB $E8,$D0,$00,$F0,$A0,$4E,$0D,$DE,$0E,$FF,$86,$7F,$6D,$56,$C0,$7F
.DB $00,$00,$00,$00,$33,$19,$73,$3F,$B3,$7F,$71,$BF,$72,$BD,$70,$3D
.DB $00,$00,$00,$00,$01,$C3,$C0,$E7,$D8,$E7,$D5,$EE,$C7,$FF,$CF,$F7
.DB $03,$03,$F7,$03,$E3,$FF,$57,$EB,$0B,$F3,$33,$03,$93,$E3,$F3,$FB
.DB $20,$C0,$B0,$C0,$81,$F8,$CB,$B1,$A4,$C3,$A0,$C7,$A5,$CE,$A4,$CF
.DB $02,$01,$01,$00,$03,$E1,$D7,$E3,$E3,$F7,$6F,$F3,$EB,$53,$57,$A3
.DB $20,$C0,$00,$C0,$04,$8E,$0C,$DF,$0C,$DF,$1C,$CF,$1C,$CF,$1C,$CF
.DB $00,$00,$40,$00,$C0,$70,$F0,$F8,$F4,$F8,$70,$FC,$B0,$7C,$30,$7C
.DB $00,$0F,$08,$07,$01,$00,$00,$01,$00,$01,$01,$00,$00,$00,$00,$00
.DB $20,$D0,$41,$A0,$D1,$E1,$F1,$FB,$F5,$FB,$33,$FF,$72,$3F,$1A,$37
.DB $1C,$0F,$2C,$CF,$CC,$FF,$CC,$FF,$4C,$BF,$BC,$4F,$CC,$0F,$4C,$8F
.DB $18,$3E,$1C,$3E,$3F,$1E,$1F,$1F,$1F,$0F,$06,$0F,$00,$07,$03,$00
.DB $E4,$79,$F6,$79,$F8,$7F,$7E,$FF,$BE,$7F,$9F,$7E,$20,$9F,$0D,$02
.DB $98,$5E,$5D,$9E,$1E,$9F,$4F,$9F,$1F,$CF,$0F,$87,$80,$07,$03,$00
.DB $6B,$37,$23,$3F,$37,$2B,$CB,$33,$81,$F3,$52,$A1,$20,$C1,$80,$00
.DB $0D,$DE,$0D,$DE,$8D,$DE,$AD,$DE,$4D,$BE,$8D,$5E,$4D,$9E,$0C,$1F
.DB $40,$FE,$70,$EC,$E0,$78,$F8,$7F,$3E,$7F,$5C,$3F,$20,$1F,$0D,$02
.DB $70,$3D,$70,$3D,$79,$3C,$FB,$3C,$3A,$B4,$A0,$1C,$00,$18,$00,$00
.DB $C1,$F7,$C4,$F3,$C0,$F0,$C9,$F6,$EF,$DF,$07,$FF,$00,$6F,$07,$00
.DB $F7,$FB,$3B,$F7,$C7,$3B,$51,$2B,$EB,$D1,$40,$B1,$21,$C0,$80,$00
.DB $AC,$CF,$AF,$CE,$A6,$CF,$DF,$E7,$EB,$D7,$A5,$D3,$02,$E1,$40,$00
.DB $27,$C3,$47,$83,$87,$03,$8B,$F3,$C9,$F3,$E2,$D1,$00,$F1,$E0,$00
.DB $1C,$CF,$1C,$CF,$BE,$CF,$9E,$EF,$AE,$4D,$00,$CF,$00,$86,$00,$00
.DB $30,$7C,$30,$7C,$30,$7C,$F2,$3C,$B8,$34,$04,$38,$08,$10,$00,$00
.DB $00,$00,$00,$00,$0D,$0E,$0F,$1F,$07,$1F,$10,$0F,$02,$01,$00,$00
.DB $0C,$33,$12,$29,$40,$39,$80,$F1,$D0,$A0,$A0,$40,$40,$80,$00,$00
.DB $0C,$8F,$1C,$8F,$4C,$9F,$9E,$FD,$7A,$FD,$AC,$72,$40,$3C,$10,$00
.DB $05,$1A,$10,$0E,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$75,$75,$25,$25,$27,$27,$25,$25,$25,$25,$00,$00
.DB $00,$00,$00,$00,$77,$77,$24,$24,$27,$27,$21,$21,$77,$77,$00,$00
.DB $00,$00,$00,$00,$07,$07,$04,$04,$05,$05,$05,$05,$07,$07,$00,$00
.DB $00,$00,$00,$00,$75,$75,$57,$57,$75,$75,$55,$55,$55,$55,$00,$00
.DB $00,$00,$00,$00,$70,$70,$40,$40,$60,$60,$40,$40,$70,$70,$00,$00
.DB $00,$00,$00,$00,$77,$77,$55,$55,$77,$77,$45,$45,$45,$45,$00,$00
.DB $00,$00,$00,$00,$50,$50,$50,$50,$60,$60,$50,$50,$50,$50,$00,$00
.DB $00,$00,$00,$00,$05,$05,$07,$07,$07,$07,$05,$05,$05,$05,$00,$00
.DB $00,$00,$00,$00,$77,$77,$52,$52,$52,$52,$52,$52,$72,$72,$00,$00
.DB $00,$00,$00,$00,$04,$04,$04,$04,$04,$04,$04,$04,$07,$07,$00,$00
.DB $00,$00,$00,$00,$77,$77,$24,$24,$24,$24,$24,$24,$77,$77,$00,$00
.DB $00,$00,$00,$00,$75,$75,$47,$47,$65,$65,$45,$45,$75,$75,$00,$00
.DB $00,$00,$00,$00,$77,$77,$44,$44,$76,$76,$14,$14,$77,$77,$00,$00
.DB $00,$00,$00,$00,$60,$60,$50,$50,$50,$50,$50,$50,$60,$60,$00,$00
.DB $00,$00,$00,$00,$77,$77,$55,$55,$57,$57,$56,$56,$75,$75,$00,$00
.DB $00,$00,$00,$00,$67,$67,$55,$55,$55,$55,$55,$55,$67,$67,$00,$00
.DB $00,$00,$00,$00,$77,$77,$54,$54,$77,$77,$61,$61,$57,$57,$00,$00
.DB $00,$00,$00,$00,$76,$76,$45,$45,$65,$65,$45,$45,$76,$76,$00,$00
.DB $00,$00,$00,$00,$06,$06,$05,$05,$06,$06,$05,$05,$06,$06,$00,$00
.DB $00,$00,$00,$00,$50,$50,$50,$50,$20,$20,$20,$20,$20,$20,$00,$00
.DB $00,$00,$00,$00,$57,$57,$72,$72,$52,$52,$52,$52,$57,$57,$00,$00
.DB $00,$00,$00,$00,$57,$57,$72,$72,$52,$52,$52,$52,$52,$52,$00,$00
.DB $00,$00,$00,$00,$07,$07,$05,$05,$05,$05,$05,$05,$27,$27,$40,$40
.DB $00,$00,$00,$00,$70,$70,$50,$50,$70,$70,$60,$60,$50,$50,$00,$00
.DB $00,$00,$00,$00,$76,$76,$25,$25,$25,$25,$25,$25,$76,$76,$00,$00
.DB $00,$00,$00,$00,$07,$07,$04,$04,$07,$07,$01,$01,$07,$07,$00,$00
.DB $00,$00,$00,$00,$77,$77,$54,$54,$56,$56,$54,$54,$74,$74,$00,$00
.DB $00,$00,$00,$00,$75,$75,$25,$25,$25,$25,$27,$27,$25,$25,$00,$00
.DB $00,$00,$00,$00,$77,$77,$55,$55,$77,$77,$56,$56,$55,$55,$00,$00
.DB $00,$00,$00,$00,$72,$72,$42,$42,$62,$62,$40,$40,$72,$72,$00,$00
.DB $00,$00,$78,$78,$84,$84,$B4,$B4,$A4,$A4,$B4,$B4,$84,$84,$78,$78
.DB $00,$00,$00,$00,$EE,$EE,$2A,$2A,$EA,$EA,$8A,$8A,$EE,$EE,$00,$00
.DB $00,$00,$00,$00,$C8,$C8,$48,$48,$4E,$4E,$4A,$4A,$EE,$EE,$00,$00
.DB $00,$00,$00,$00,$0A,$0A,$0A,$0A,$0A,$0A,$0E,$0E,$0A,$0A,$00,$00
.DB $00,$00,$00,$00,$AA,$AA,$AA,$AA,$AA,$AA,$EE,$EE,$AA,$AA,$00,$00
.DB $00,$00,$00,$00,$0A,$0A,$0A,$0A,$0E,$0E,$0A,$0A,$4A,$4A,$00,$00
.DB $00,$00,$00,$00,$EE,$EE,$AA,$AA,$EE,$EE,$A8,$A8,$A8,$A8,$00,$00
.DB $00,$00,$00,$00,$EA,$EA,$AA,$AA,$EA,$EA,$84,$84,$84,$84,$00,$00
.DB $00,$00,$00,$00,$CE,$CE,$AA,$AA,$AE,$AE,$AA,$AA,$CA,$CA,$00,$00
.DB $00,$00,$00,$00,$EE,$EE,$28,$28,$4C,$4C,$88,$88,$EE,$EE,$00,$00
.DB $00,$00,$00,$00,$0E,$0E,$08,$08,$0E,$0E,$02,$02,$4E,$4E,$00,$00
.DB $00,$00,$00,$00,$E0,$E0,$80,$80,$C0,$C0,$80,$80,$E0,$E0,$00,$00
.DB $00,$00,$00,$00,$AE,$AE,$AA,$AA,$AA,$AA,$EA,$EA,$AE,$AE,$00,$00
.DB $00,$00,$00,$00,$8E,$8E,$88,$88,$8C,$8C,$88,$88,$E8,$E8,$00,$00
.DB $00,$00,$00,$00,$EA,$EA,$8E,$8E,$CA,$CA,$8A,$8A,$EA,$EA,$00,$00
.DB $00,$00,$00,$00,$EE,$EE,$84,$84,$E4,$E4,$24,$24,$E4,$E4,$00,$00
.DB $00,$00,$00,$00,$EE,$EE,$84,$84,$C4,$C4,$84,$84,$EE,$EE,$00,$00
.DB $00,$00,$00,$00,$A0,$A0,$E0,$E0,$A0,$A0,$A0,$A0,$A0,$A0,$00,$00
.DB $00,$00,$00,$00,$EE,$EE,$8A,$8A,$8A,$8A,$8A,$8A,$EE,$EE,$00,$00
.DB $00,$00,$00,$00,$AE,$AE,$E4,$E4,$A4,$A4,$A4,$A4,$A4,$A4,$00,$00
.DB $00,$00,$03,$03,$E4,$E4,$45,$45,$45,$45,$45,$45,$44,$44,$03,$03
.DB $00,$00,$C0,$C0,$20,$20,$A0,$A0,$20,$20,$A0,$A0,$20,$20,$C0,$C0
.DB $00,$00,$00,$00,$EC,$EC,$4A,$4A,$4A,$4A,$4A,$4A,$EC,$EC,$00,$00
.DB $00,$00,$00,$00,$0E,$0E,$08,$08,$0E,$0E,$02,$02,$0E,$0E,$00,$00
.DB $00,$00,$00,$00,$EE,$EE,$A8,$A8,$AC,$AC,$A8,$A8,$E8,$E8,$00,$00
.DB $00,$00,$00,$00,$EA,$EA,$4A,$4A,$4A,$4A,$4E,$4E,$4A,$4A,$00,$00
.DB $00,$00,$00,$00,$EE,$EE,$AA,$AA,$EE,$EE,$AC,$AC,$AA,$AA,$00,$00
.DB $00,$00,$00,$00,$EA,$EA,$8A,$8A,$C4,$C4,$8A,$8A,$8A,$8A,$00,$00
.DB $00,$00,$00,$00,$0A,$0A,$0A,$0A,$EE,$EE,$0A,$0A,$0A,$0A,$00,$00
.DB $00,$00,$00,$00,$EA,$EA,$AE,$AE,$EA,$EA,$AA,$AA,$AA,$AA,$00,$00
.DB $00,$00,$00,$00,$AE,$AE,$E8,$E8,$AC,$AC,$A8,$A8,$AE,$AE,$00,$00
.DB $00,$00,$03,$03,$E4,$E4,$A5,$A5,$E5,$E5,$C5,$C5,$A4,$A4,$03,$03
.DB $00,$00,$00,$00,$E8,$E8,$A8,$A8,$E8,$E8,$A8,$A8,$AE,$AE,$00,$00
.DB $00,$00,$00,$00,$EA,$EA,$8A,$8A,$CC,$CC,$8A,$8A,$EA,$EA,$00,$00
.DB $00,$00,$00,$00,$EE,$EE,$84,$84,$E4,$E4,$24,$24,$EE,$EE,$00,$00
.DB $00,$00,$00,$00,$0E,$0E,$08,$08,$0C,$0C,$08,$08,$0E,$0E,$00,$00
.DB $00,$00,$00,$00,$EC,$EC,$8A,$8A,$CC,$CC,$8A,$8A,$EC,$EC,$00,$00
.DB $00,$00,$00,$00,$0E,$0E,$08,$08,$08,$08,$0A,$0A,$0E,$0E,$00,$00
.DB $00,$00,$00,$00,$CE,$CE,$A4,$A4,$C4,$C4,$A4,$A4,$C4,$C4,$00,$00
.DB $00,$00,$00,$00,$0E,$0E,$0A,$0A,$0E,$0E,$08,$08,$08,$08,$00,$00
.DB $00,$00,$00,$00,$8E,$8E,$8A,$8A,$8E,$8E,$8A,$8A,$EA,$EA,$00,$00
.DB $00,$00,$00,$00,$AE,$AE,$A8,$A8,$4C,$4C,$48,$48,$4E,$4E,$00,$00
.DB $00,$00,$00,$00,$EE,$EE,$4A,$4A,$4A,$4A,$4A,$4A,$4E,$4E,$00,$00
.DB $00,$00,$00,$00,$AE,$AE,$E4,$E4,$A4,$A4,$A4,$A4,$AE,$AE,$00,$00
.DB $00,$00,$00,$00,$E0,$E0,$A0,$A0,$A0,$A0,$A0,$A0,$E0,$E0,$00,$00
.DB $00,$00,$00,$00,$AE,$AE,$EA,$EA,$AA,$AA,$AA,$AA,$AE,$AE,$00,$00
.DB $00,$00,$00,$00,$0C,$0C,$0A,$0A,$0A,$0A,$0A,$0A,$0C,$0C,$00,$00
.DB $00,$00,$00,$00,$EE,$EE,$4A,$4A,$4E,$4E,$4A,$4A,$EA,$EA,$00,$00
.DB $00,$00,$00,$00,$E0,$E0,$20,$20,$40,$40,$80,$80,$E0,$E0,$00,$00
|
agranlund/wolf
| 5,308
|
z80/gfx/title.s
|
; ///////////////////////
; // //
; // File Attributes //
; // //
; ///////////////////////
; Filename: title.bmp
; Pixel Width: 160px
; Pixel Height: 144px
; /////////////////
; // //
; // Constants //
; // //
; /////////////////
.EQU title_tile_map_size $0168
.EQU title_tile_map_width $14
.EQU title_tile_map_height $12
.EQU title_tile_data_size $02D0
.EQU title_tile_count $0168
; ////////////////
; // //
; // Map Data //
; // //
; ////////////////
title_map_data:
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$01,$02,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$03,$04,$05,$06,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$07,$08,$09,$0A,$0B,$0C,$0D,$0E,$0F,$10,$11,$12
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$13,$14,$15,$16,$17,$18,$19
.DB $1A,$14,$1B,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $1C,$0C,$0D,$1D,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$1E,$0C,$0D,$1D,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$1E,$0C,$0D,$1D,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$1E,$1F,$20,$21
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $22,$23,$24,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$25,$26
.DB $27,$28,$29,$2A,$2B,$2C,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00
.REPT 20*18
.DB $00
.ENDR
; /////////////////
; // //
; // Tile Data //
; // //
; /////////////////
title_tile_data:
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.DB $C7,$38,$00,$FF,$00,$FF,$C7,$38,$00,$38,$00,$38,$00,$38,$00,$38
.DB $F0,$0F,$00,$FF,$00,$FF,$E9,$06,$09,$06,$09,$06,$09,$06,$09,$06
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.DB $FF,$00,$00,$FF,$00,$FF,$F4,$03,$00,$07,$10,$0F,$40,$3F,$80,$7F
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.DB $00,$FF,$00,$FF,$00,$FF,$4A,$84,$B0,$04,$06,$00,$82,$3D,$48,$84
.DB $00,$FF,$00,$FF,$00,$FF,$10,$21,$42,$A5,$52,$21,$94,$29,$42,$21
.DB $01,$F0,$00,$E6,$00,$E7,$02,$E1,$08,$F0,$20,$DC,$20,$CC,$10,$E1
.DB $00,$FF,$10,$EF,$50,$8F,$02,$84,$54,$89,$52,$8C,$54,$89,$04,$C0
.DB $00,$FF,$00,$FF,$00,$FF,$44,$20,$92,$20,$14,$23,$14,$23,$A2,$01
.DB $00,$FF,$00,$DF,$00,$9F,$08,$07,$00,$9F,$00,$9F,$00,$9F,$40,$8F
|
agranlund/wolf
| 10,648
|
z80/gfx/gbc_only.s
|
; Filename: gbc_only.bmp
; Pixel Width: 160px
; Pixel Height: 144px
.EQU gbc_only_tile_map_size $0168
.EQU gbc_only_tile_map_width $14
.EQU gbc_only_tile_map_height $12
.EQU gbc_only_tile_data_size $07F0
.EQU gbc_only_tile_count $0168
; ////////////////
; // //
; // Map Data //
; // //
; ////////////////
gbc_only_map_data:
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$01,$02,$03,$04,$05,$06,$07,$08,$01,$02,$03,$04
.DB $05,$06,$07,$08,$01,$02,$03,$04,$09,$0A,$0B,$0C,$0D,$0E,$0F,$10
.DB $11,$12,$13,$14,$0D,$0E,$0F,$10,$09,$0A,$0B,$0C,$15,$16,$17,$18
.DB $19,$1A,$1B,$1C,$1D,$1E,$1F,$20,$19,$1A,$1B,$1C,$15,$16,$17,$18
.DB $21,$22,$23,$24,$25,$26,$27,$28,$29,$2A,$2B,$2C,$25,$26,$27,$28
.DB $21,$22,$23,$24,$2D,$2E,$2F,$30,$31,$32,$33,$34,$35,$36,$37,$38
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.DB $49,$4A,$4B,$4C,$4D,$4E,$4F,$50,$49,$4A,$4B,$4C,$45,$46,$47,$48
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.DB $51,$52,$53,$54,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
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.DB $60,$61,$62,$63,$64,$65,$5E,$66,$67,$68,$69,$00,$00,$6A,$6B,$6C
.DB $6D,$6E,$6F,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$7C,$7D,$00,$00,$00,$00,$00
.DB $00,$7E,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00
; /////////////////
; // //
; // Tile Data //
; // //
; /////////////////
gbc_only_tile_data:
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.DB $FF,$FF,$00,$00,$02,$00,$B7,$00,$BF,$40,$FC,$03,$DD,$22,$00,$FF
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.DB $FF,$FF,$FF,$FF,$FF,$FF,$00,$FF,$00,$00,$55,$AA,$3D,$C2,$B3,$4C
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.DB $FF,$FF,$E0,$E0,$E1,$E0,$E6,$E0,$E7,$E0,$EF,$E0,$FD,$E2,$F0,$EF
.DB $FF,$FF,$FF,$FF,$FF,$FF,$C3,$FC,$00,$00,$FF,$00,$0B,$F4,$D6,$29
.DB $FF,$FF,$FF,$FF,$FF,$FF,$16,$0E,$F6,$0E,$A6,$5E,$F6,$0E,$A6,$5E
.DB $FF,$FF,$FF,$FF,$FF,$FF,$00,$00,$40,$00,$B5,$0A,$E0,$1F,$4A,$B5
.DB $F8,$FC,$FE,$FC,$FF,$FC,$5E,$3D,$BC,$7F,$3F,$FF,$7F,$FF,$FF,$7F
.DB $4A,$B5,$1E,$E1,$50,$AF,$3F,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.DB $AC,$53,$5A,$A5,$7F,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
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.DB $EF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$80,$E0,$9F,$C0,$96,$C9,$AD,$D2
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.DB $F8,$FC,$FE,$FC,$FF,$FC,$5E,$3D,$BC,$7F,$3F,$FF,$7F,$FF,$00,$00
.DB $83,$7C,$13,$EC,$42,$BD,$68,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$00,$00
.DB $96,$6E,$E6,$1E,$A7,$5E,$06,$FF,$FF,$FF,$FF,$FF,$FE,$FF,$00,$00
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.DB $FF,$FF,$90,$90,$FA,$FF,$A0,$A0,$EA,$FF,$88,$88,$EE,$FF,$10,$10
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.DB $01,$00,$FD,$02,$1B,$E4,$16,$E9,$83,$7C,$9E,$61,$56,$A9,$01,$FE
.DB $FE,$01,$01,$00,$FE,$00,$BA,$44,$AE,$51,$BA,$45,$75,$8A,$58,$A7
.DB $00,$FF,$FF,$00,$00,$00,$FF,$00,$51,$AE,$BA,$45,$0D,$F2,$90,$6F
.DB $03,$FF,$FB,$07,$0F,$07,$F7,$0F,$57,$AF,$E7,$1F,$57,$AF,$57,$AF
.DB $BA,$85,$A4,$9B,$BF,$80,$BB,$84,$F4,$8B,$CB,$B4,$F8,$87,$8F,$FC
.DB $11,$EE,$A4,$5B,$43,$BC,$50,$AF,$AA,$55,$E8,$17,$14,$EB,$49,$B6
.DB $7C,$7D,$7D,$7D,$7C,$7C,$7C,$7E,$7E,$7F,$7F,$7F,$7F,$7F,$3F,$3F
.DB $47,$47,$E7,$F7,$57,$57,$4F,$C7,$1F,$0F,$BF,$FF,$FF,$FF,$FF,$FF
.DB $D5,$FF,$80,$80,$EA,$FF,$CF,$FF,$E0,$E3,$F7,$FF,$FF,$FF,$FF,$FF
.DB $5E,$FE,$06,$06,$AE,$FE,$3E,$FE,$82,$B2,$FE,$FE,$FE,$FE,$FC,$FC
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$F0,$0F,$00,$00,$B5,$4A
.DB $82,$CD,$99,$C6,$80,$FF,$FF,$FF,$FF,$FF,$3F,$FF,$7F,$00,$C1,$00
.DB $A4,$5B,$51,$AE,$0B,$F4,$F8,$FF,$FF,$FF,$FF,$FF,$7F,$FF,$78,$F8
.DB $6B,$94,$54,$AB,$00,$FF,$00,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$00,$00
.DB $40,$BF,$04,$FB,$52,$AD,$00,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$03,$00
.DB $87,$7F,$47,$BF,$17,$EF,$0F,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FB,$07
.DB $FF,$FF,$FF,$FF,$FF,$FF,$BE,$C1,$E0,$80,$DA,$84,$DF,$80,$D4,$8B
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$E7,$1F,$1F,$00,$60,$80,$CA,$35
.DB $00,$00,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$F0,$0F,$00,$00,$B5,$4A
.DB $00,$00,$99,$C6,$80,$FF,$FF,$FF,$FF,$FF,$3F,$FF,$7F,$00,$C1,$00
.DB $00,$00,$51,$AE,$0B,$F4,$F8,$FF,$FF,$FF,$FF,$FF,$7F,$FF,$78,$F8
.DB $00,$00,$54,$AB,$00,$FF,$00,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$00,$00
.DB $10,$EF,$8A,$75,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.DB $AE,$51,$AF,$51,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.DB $FF,$F8,$FB,$F8,$FF,$F8,$FF,$F8,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.DB $F5,$0A,$2E,$D1,$EF,$10,$FB,$04,$F3,$FC,$FF,$FF,$FF,$FF,$FF,$FF
.DB $DA,$25,$B7,$48,$FF,$00,$2E,$D1,$FF,$00,$FF,$FF,$FF,$FF,$FF,$FF
.DB $E3,$1F,$53,$AF,$F3,$0F,$AF,$57,$E7,$1F,$FF,$FF,$FF,$FF,$FF,$FF
.DB $DF,$80,$F4,$8B,$DF,$BF,$BF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.DB $59,$A6,$DC,$23,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FB,$F0,$FB,$FD,$FB,$FD,$FB,$FD,$FB,$FD
.DB $FF,$FF,$FF,$FF,$FF,$FF,$1F,$0F,$FF,$CF,$FF,$CF,$BF,$8F,$F8,$88
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$60,$C1
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FC,$F8,$F1,$FB,$F7,$F3,$F7,$F7,$FF,$E7
.DB $FF,$FF,$FF,$FF,$FF,$FF,$7F,$1F,$BF,$1F,$FF,$9F,$FF,$9F,$F0,$98
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$F1,$40
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$9C,$0E
.DB $FF,$FF,$FF,$FF,$FF,$FF,$F7,$E3,$FB,$F7,$FF,$F3,$FB,$F7,$1C,$30
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$E0,$71
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$81,$11
.DB $FF,$FF,$FF,$FF,$FF,$FF,$F9,$F0,$F3,$E6,$E7,$EF,$DF,$EF,$FF,$CF
.DB $FF,$FF,$FF,$FF,$FF,$FF,$BF,$7F,$7F,$7F,$7F,$7F,$BF,$7F,$B3,$61
.DB $FF,$FF,$FF,$FF,$FF,$FF,$BF,$1F,$FF,$9F,$BF,$DF,$FF,$9F,$BC,$D8
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$F0,$F8
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$69,$C0
.DB $FF,$FF,$FF,$FF,$FF,$FF,$CF,$8F,$EF,$EF,$EF,$EF,$EF,$EF,$E1,$E8
.DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$9F,$0F
.DB $FB,$FD,$F8,$FC,$FB,$FD,$FB,$FD,$FB,$FD,$FB,$FD,$F8,$F0,$FF,$FF
.DB $7F,$B2,$67,$37,$6F,$B7,$FF,$A7,$B7,$B7,$F7,$F2,$F0,$78,$FF,$FF
.DB $77,$64,$F9,$24,$77,$AF,$FF,$27,$F7,$2F,$7F,$67,$47,$C3,$FF,$FF
.DB $FF,$E7,$FF,$E7,$FF,$E7,$EF,$F7,$F3,$F7,$F9,$F3,$FC,$F8,$FF,$FF
.DB $FA,$F3,$0F,$0F,$FF,$9E,$F2,$99,$FF,$97,$B7,$12,$70,$18,$FF,$FF
.DB $70,$66,$6F,$76,$7F,$66,$6F,$76,$3F,$46,$7F,$06,$80,$00,$FF,$FF
.DB $0D,$6C,$EB,$6D,$78,$EC,$7F,$E9,$7F,$ED,$75,$EC,$44,$02,$FF,$FF
.DB $98,$D3,$EF,$D3,$0B,$17,$FF,$F3,$EF,$D3,$D8,$93,$1C,$30,$FF,$FF
.DB $0F,$64,$FF,$0E,$7F,$8E,$6F,$9E,$FE,$0E,$2F,$64,$E0,$71,$FF,$FE
.DB $FB,$BB,$57,$BB,$BB,$57,$77,$D7,$6F,$D7,$FF,$C7,$CF,$EF,$7F,$4F
.DB $FF,$CF,$FF,$CF,$FF,$CF,$EF,$EF,$E7,$EF,$F3,$E6,$F8,$F0,$FF,$FF
.DB $C5,$EC,$FE,$CE,$1E,$DE,$DE,$1E,$BC,$4E,$45,$6C,$73,$E1,$FF,$FF
.DB $FA,$93,$B7,$D7,$F7,$97,$B7,$D7,$F7,$97,$BA,$D3,$88,$08,$FF,$FF
.DB $31,$66,$6D,$B4,$BF,$A7,$AF,$B7,$FF,$27,$2F,$77,$E3,$43,$FF,$FF
.DB $FF,$F2,$E7,$F7,$EF,$F7,$FF,$E7,$F7,$F7,$F7,$F2,$F0,$F8,$FF,$FF
.DB $72,$66,$FF,$26,$77,$AE,$F7,$2E,$F7,$2E,$77,$6E,$44,$C0,$FF,$FF
.DB $6D,$EB,$6B,$ED,$EF,$6D,$6F,$ED,$ED,$6E,$EF,$6E,$03,$06,$F6,$F2
.DB $FF,$9F,$DF,$BF,$7F,$BF,$FF,$3F,$BF,$7F,$7F,$7F,$FF,$7F,$7F,$FF
.DB $FF,$FE,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.DB $5F,$4F,$3F,$1F,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.DB $F6,$F0,$F8,$F1,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
|
agra-uni-bremen/microrv32
| 1,590
|
microrv32/sw/basic-uart-asm/uart.S
|
.globl _start
.equ SYSCALL_ADDR, 0x02010000
.equ LED_ADDR, 0x81000000
.equ UART_TX_DATA_ADDR, 0x82000000
.equ UART_TX_CTRL_ADDR, 0x82000004
.equ UART_RX_DATA_ADDR, 0x82000008
.macro SYS_EXIT, exit_code
li a7, 93
li x10, \exit_code
li x5, SYSCALL_ADDR
sw a7, 0(x5)
.endm
.macro LED_WRITE, led_val
li x10, \led_val
li x5, LED_ADDR
sw x10, 0(x5)
.endm
# .macro UART_WRITE, chr_val
# # load up x10 with character, write x10 to tx register
# li x10, \chr_val
# li x5, UART_TX_DATA_ADDR
# sw x10, 0(x5)
# # load up x10 with 1, write x10 to tx ctrl register
# li x10, 1
# li x5, UART_TX_CTRL_ADDR
# sw x10, 0(x5)
# .endm
# program entry-point
_start:
li x5, 0
li x6, 0
li x7, 0
LED_WRITE 10
# load x6 with address of hello string label
la x6, hello
hello_loop:
# load up x10 with character from string
lb x10, 0(x6)
beqz x10, end_hello_loop
# load x5 with address of uart tx data register
li x5, UART_TX_DATA_ADDR
# store character (loaded in x10) at tx data register (x5)
sw x10, 0(x5)
# load up x10 with 1, write x10 to tx ctrl register
li x28, 1
li x5, UART_TX_CTRL_ADDR
sw x28, 0(x5)
# increment string label pointer +1
addi x6,x6,1
# read transmit status from uart and wait until character is sent
wait_chr_send:
li x5, UART_TX_CTRL_ADDR
lw x7, 0(x5)
beqz x7, wait_chr_send
# string is NUL terminated, if x10 not 0x0(\NUL) then continue sending characters, else terminate program
j hello_loop
end_hello_loop:
# call exit (SYS_EXIT=93) with exit code 0 (argument in x10)
SYS_EXIT 0
end:
j end
#.data
hello: .string "hello"
|
agra-uni-bremen/microrv32
| 2,172
|
microrv32/sw/instructionTests/instr.S
|
.globl _start
# program entry-point
_start:
# test nop, should result in addi x0,x0,0
nop
# load some constants
li x4,0x01
li x5,0xAA
li x6,0x55
# write to x0 should never work
li x0, 0xff
## register register integer instructions
# add and subtract
# add should result 0xFF
# sub should result 0x55
add x7, x5, x6
sub x8, x5, x6
# and or xor
# and should result 0x00
and x9, x5, x6
# or should result 0xFF
or x10, x5, x6
# xor should result 0xFF
xor x11, x5, x6
# shift left of 0x55 by 1 result in 0xAA
sll x12, x6, x4
# shift right of 0xAA by 1 result in 0x55
srl x13, x5, x4
## register immediate integer instructions
# add immediate of x5 = 0xAA and immediate 0x55 result in 0xFF
addi x14, x5, 0x55
# load upper immediate
lui x15, 0xefe
# and
andi x16, x5, 0x55
# or
ori x17, x6, 0xAA
# xor
xori x18, x5, 0x55
# shift left of 0x55 by immediate 0x01 result in 0xAA
slli x19, x6, 0x01
# shift right of 0xAA by immediate 0x01 result in 0x55
srli x20, x5, 0x01
# store and load tests
# load some constants to registers
li x2, 0xDE
li x3, 0xAD
li x3, 0xBE
li x4, 0xEF
li x5, 0x00
# try storing a register value to some offset that should be far enough away in ram
# this can change once this test gets bigger!
sw x2, 250(x5)
lw x6, 250(x0)
# build some 32 bit constant in x4 by hand
lui x2, 0xDEAD
slli x2,x2, 4
lui x3, 0xBEEF
srli x3,x3,12
add x4,x2,x3
# try store and load operations of 32 bit values and see how it behaves
sw x4, 250(x5)
lw x6, 250(x0)
sh x4, 260(x5)
lh x7, 260(x0)
lhu x7, 260(x0)
sb x4, 260(x5)
lb x8, 260(x0)
lbu x8, 260(x0)
auipc x9, 0x1
auipc x9, 0xFFFFF
# branch and jump tests
li x1, 0x30
li x2, 0x2F
li x3, 0x30
# branch will get stuck in endless loop if instruction doesnt work properly
br1:
beq x1,x2,br1 # x1 == x2 : 0x30 == 0x2F is false
br2:
bne x1,x3,br2 # x1 != x3 : 0x30 != 0x30 is false
br3:
blt x1,x2,br3 # x1 < x2 : 0x30 < 0x2F is false
br4:
bge x2,x1,br4 # x2 >= x1 : 0x2F >= 0x30 is false
br5:
bltu x1,x2,br5 # x1 < x2 : 0x30 < 0x2F is false
br6:
bgeu x2,x1,br6 # x2 >= x1 : 0x2F >= 0x30 is false
jalr x20,x0,0x04 # should skip next instruction, if not this causes an endless loop
j br6
nop
# endless loop
end:
j end
|
agra-uni-bremen/microrv32
| 3,646
|
microrv32/sw/basic-timerirq/timer.S
|
.globl _start
.equ SYSCALL_ADDR, 0x02010000
.equ LED_ADDR, 0x81000000
.equ UART_TX_DATA_ADDR, 0x82000000
.equ UART_TX_CTRL_ADDR, 0x82000004
.equ UART_RX_DATA_ADDR, 0x82000008
.equ CLIC_MTIME_LO, 0x0200bff8
.equ CLIC_MTIME_HI, 0x0200bffc
.equ CLIC_MTIMECMP_LO, 0x02004000
.equ CLIC_MTIMECMP_HI, 0x02004004
.macro INIT_HW_PLATFORM
and x1,x0,x0
and x2,x0,x0
and x3,x0,x0
and x4,x0,x0
and x5,x0,x0
and x6,x0,x0
and x7,x0,x0
and x8,x0,x0
and x9,x0,x0
and x10,x0,x0
and x11,x0,x0
and x12,x0,x0
and x13,x0,x0
and x14,x0,x0
and x15,x0,x0
and x16,x0,x0
and x17,x0,x0
and x18,x0,x0
and x19,x0,x0
and x20,x0,x0
and x21,x0,x0
and x22,x0,x0
and x23,x0,x0
and x24,x0,x0
and x25,x0,x0
and x26,x0,x0
and x27,x0,x0
and x28,x0,x0
and x29,x0,x0
and x30,x0,x0
and x31,x0,x0
.endm
.macro SYS_EXIT, exit_code
li a7, 93
li x10, \exit_code
li x5, SYSCALL_ADDR
sw a7, 0(x5)
.endm
.macro LED_WRITE, led_val
li x10, \led_val
li x5, LED_ADDR
sw x10, 0(x5)
.endm
# program entry-point
_start:
INIT_HW_PLATFORM
li x18, 0 ## some random counter that is available in traphandler
li x9, 3 ## counter limit
li x10, 0
li x11, 0
la sp, stack_end
la x5, level_0_interrupt_handler
csrw mtvec, x5
# load val for timercmp -- based on r5-priv-spec
# load -1 into upper timercmp so irq is 0
li x5, -1
li x11, 0
li x10, 240
la x6, CLIC_MTIMECMP_LO
sw x5, 0(x6)
sw x5, 4(x6)
sw x10, 0(x6)
sw x11, 4(x6)
# enable interrupts, mie.mti and mstatus.mie
li x6, 0x80
csrw mie, x6 # mie.mtie = 1
li x6, 0x8
csrw mstatus, x6 # mstatus.mie = 1
LED_WRITE 10
loop:
bgt x18, x9, exit_loop # if x8 > x9 then exit_loop
j loop
exit_loop:
csrw mstatus, x0 # mstatus.mie = 0
csrw mie, x0 # mie.mtie = 0
# call exit (SYS_EXIT=93) with exit code 0 (argument in x10)
SYS_EXIT 0
end:
j end
/*
* Interrupt handler for non-nested interrupts. Only selected registers are stored/re-stored, i.e. those not preserved on function calls.
*/
# //#define STORE sw
# //#define LOAD lw
.equ REGBYTES, 4
level_0_interrupt_handler:
# store execution context on the stack (register content)
addi sp, sp, -REGBYTES * 32
sw x1, 0x0(sp)
sw x4, 3 * REGBYTES(sp)
sw x5, 4 * REGBYTES(sp)
sw x6, 5 * REGBYTES(sp)
sw x7, 6 * REGBYTES(sp)
sw x10, 9 * REGBYTES(sp)
sw x11, 10 * REGBYTES(sp)
sw x12, 11 * REGBYTES(sp)
sw x13, 12 * REGBYTES(sp)
sw x14, 13 * REGBYTES(sp)
sw x15, 14 * REGBYTES(sp)
sw x16, 15 * REGBYTES(sp)
sw x17, 16 * REGBYTES(sp)
sw x28, 27 * REGBYTES(sp)
sw x29, 28 * REGBYTES(sp)
sw x30, 29 * REGBYTES(sp)
sw x31, 30 * REGBYTES(sp)
# todo: some more trapcause handling, technically we could end here for illegal instructions and would increase mtimecmp
#csrr a0, mcause # a0 containing cause for trap
la x6, CLIC_MTIME_LO
li x5, -1
lw x10, 0(x6)
lw x11, 4(x6)
# techically: check x10 for overflow and increase x11 by 1, since its 64 bits, but this is experimental
# would be easier to do in C than ASM anyway
addi x10, x10, 200
addi x18, x18, 1
la x6, CLIC_MTIMECMP_LO
sw x5, 0(x6)
sw x5, 4(x6)
sw x10, 0(x6)
sw x11, 4(x6)
# re-store the saved context
lw x1, 0x0(sp)
lw x4, 3 * REGBYTES(sp)
lw x5, 4 * REGBYTES(sp)
lw x6, 5 * REGBYTES(sp)
lw x7, 6 * REGBYTES(sp)
lw x10, 9 * REGBYTES(sp)
lw x11, 10 * REGBYTES(sp)
lw x12, 11 * REGBYTES(sp)
lw x13, 12 * REGBYTES(sp)
lw x14, 13 * REGBYTES(sp)
lw x15, 14 * REGBYTES(sp)
lw x16, 15 * REGBYTES(sp)
lw x17, 16 * REGBYTES(sp)
lw x28, 27 * REGBYTES(sp)
lw x29, 28 * REGBYTES(sp)
lw x30, 29 * REGBYTES(sp)
lw x31, 30 * REGBYTES(sp)
addi sp, sp, REGBYTES * 32
mret
stack_begin:
.zero 2048
stack_end:
|
agra-uni-bremen/microrv32
| 1,183
|
microrv32/sw/benchmarks/dhrystone/crt.S
|
.section ".text.init"
.globl _start
_start:
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10,0
li x11,0
li x12,0
li x13,0
li x14,0
li x15,0
li x16,0
li x17,0
li x18,0
li x19,0
li x20,0
li x21,0
li x22,0
li x23,0
li x24,0
li x25,0
li x26,0
li x27,0
li x28,0
li x29,0
li x30,0
li x31,0
# initialize global pointer
.option push
.option norelax
la gp, __global_pointer$
.option pop
la tp, _end + 63
and tp, tp, -64
# get core id
csrr a0, mhartid
li a1, 4
# give each core 128KB of stack + TLS
#define STKSHIFT 17
sll a2, a0, STKSHIFT
add tp, tp, a2
add sp, a0, 1
sll sp, sp, STKSHIFT
add sp, sp, tp
jal main
.equ SYSCALL_ADDR, 0x02010000
terminate_platform:
li a7, 93
li t0, SYSCALL_ADDR
csrr a6, mhartid
sw a6, 0(t0)
.section ".tdata.begin"
.globl _tdata_begin
_tdata_begin:
.section ".tdata.end"
.globl _tdata_end
_tdata_end:
.section ".tbss.end"
.globl _tbss_end
_tbss_end:
.section ".tohost","aw",@progbits
.align 6
.globl tohost
tohost: .dword 0
.align 6
.globl fromhost
fromhost: .dword 0
|
agra-uni-bremen/microrv32
| 1,200
|
microrv32/sw/benchmarks/qsort/crt.S
|
.section ".text.init"
.globl _start
_start:
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10,0
li x11,0
li x12,0
li x13,0
li x14,0
li x15,0
li x16,0
li x17,0
li x18,0
li x19,0
li x20,0
li x21,0
li x22,0
li x23,0
li x24,0
li x25,0
li x26,0
li x27,0
li x28,0
li x29,0
li x30,0
li x31,0
# initialize global pointer
.option push
.option norelax
la gp, __global_pointer$
.option pop
la tp, _end + 63
and tp, tp, -64
# get core id
csrr a0, mhartid
li a1, 4
# give each core 128KB of stack + TLS
#define STKSHIFT 17
sll a2, a0, STKSHIFT
add tp, tp, a2
add sp, a0, 1
sll sp, sp, STKSHIFT
add sp, sp, tp
jal main
.equ SYSCALL_ADDR, 0x02010000
terminate_platform:
li a7, 93
li t0, SYSCALL_ADDR
csrr a6, mhartid
sw a6, 0(t0)
sw a7, 0(t0)
.section ".tdata.begin"
.globl _tdata_begin
_tdata_begin:
.section ".tdata.end"
.globl _tdata_end
_tdata_end:
.section ".tbss.end"
.globl _tbss_end
_tbss_end:
.section ".tohost","aw",@progbits
.align 6
.globl tohost
tohost: .dword 0
.align 6
.globl fromhost
fromhost: .dword 0
|
AGProjects/python-sipsimple
| 20,023
|
deps/pjsip/third_party/opus/celt/arm/celt_pitch_xcorr_arm.s
|
; Copyright (c) 2007-2008 CSIRO
; Copyright (c) 2007-2009 Xiph.Org Foundation
; Copyright (c) 2013 Parrot
; Written by Aurélien Zanelli
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
;
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
;
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AREA |.text|, CODE, READONLY
GET celt/arm/armopts.s
IF OPUS_ARM_MAY_HAVE_EDSP
EXPORT celt_pitch_xcorr_edsp
ENDIF
IF OPUS_ARM_MAY_HAVE_NEON
EXPORT celt_pitch_xcorr_neon
ENDIF
IF OPUS_ARM_MAY_HAVE_NEON
; Compute sum[k]=sum(x[j]*y[j+k],j=0...len-1), k=0...3
xcorr_kernel_neon PROC
xcorr_kernel_neon_start
; input:
; r3 = int len
; r4 = opus_val16 *x
; r5 = opus_val16 *y
; q0 = opus_val32 sum[4]
; output:
; q0 = opus_val32 sum[4]
; preserved: r0-r3, r6-r11, d2, q4-q7, q9-q15
; internal usage:
; r12 = int j
; d3 = y_3|y_2|y_1|y_0
; q2 = y_B|y_A|y_9|y_8|y_7|y_6|y_5|y_4
; q3 = x_7|x_6|x_5|x_4|x_3|x_2|x_1|x_0
; q8 = scratch
;
; Load y[0...3]
; This requires len>0 to always be valid (which we assert in the C code).
VLD1.16 {d5}, [r5]!
SUBS r12, r3, #8
BLE xcorr_kernel_neon_process4
; Process 8 samples at a time.
; This loop loads one y value more than we actually need. Therefore we have to
; stop as soon as there are 8 or fewer samples left (instead of 7), to avoid
; reading past the end of the array.
xcorr_kernel_neon_process8
; This loop has 19 total instructions (10 cycles to issue, minimum), with
; - 2 cycles of ARM insrtuctions,
; - 10 cycles of load/store/byte permute instructions, and
; - 9 cycles of data processing instructions.
; On a Cortex A8, we dual-issue the maximum amount (9 cycles) between the
; latter two categories, meaning the whole loop should run in 10 cycles per
; iteration, barring cache misses.
;
; Load x[0...7]
VLD1.16 {d6, d7}, [r4]!
; Unlike VMOV, VAND is a data processsing instruction (and doesn't get
; assembled to VMOV, like VORR would), so it dual-issues with the prior VLD1.
VAND d3, d5, d5
SUBS r12, r12, #8
; Load y[4...11]
VLD1.16 {d4, d5}, [r5]!
VMLAL.S16 q0, d3, d6[0]
VEXT.16 d16, d3, d4, #1
VMLAL.S16 q0, d4, d7[0]
VEXT.16 d17, d4, d5, #1
VMLAL.S16 q0, d16, d6[1]
VEXT.16 d16, d3, d4, #2
VMLAL.S16 q0, d17, d7[1]
VEXT.16 d17, d4, d5, #2
VMLAL.S16 q0, d16, d6[2]
VEXT.16 d16, d3, d4, #3
VMLAL.S16 q0, d17, d7[2]
VEXT.16 d17, d4, d5, #3
VMLAL.S16 q0, d16, d6[3]
VMLAL.S16 q0, d17, d7[3]
BGT xcorr_kernel_neon_process8
; Process 4 samples here if we have > 4 left (still reading one extra y value).
xcorr_kernel_neon_process4
ADDS r12, r12, #4
BLE xcorr_kernel_neon_process2
; Load x[0...3]
VLD1.16 d6, [r4]!
; Use VAND since it's a data processing instruction again.
VAND d4, d5, d5
SUB r12, r12, #4
; Load y[4...7]
VLD1.16 d5, [r5]!
VMLAL.S16 q0, d4, d6[0]
VEXT.16 d16, d4, d5, #1
VMLAL.S16 q0, d16, d6[1]
VEXT.16 d16, d4, d5, #2
VMLAL.S16 q0, d16, d6[2]
VEXT.16 d16, d4, d5, #3
VMLAL.S16 q0, d16, d6[3]
; Process 2 samples here if we have > 2 left (still reading one extra y value).
xcorr_kernel_neon_process2
ADDS r12, r12, #2
BLE xcorr_kernel_neon_process1
; Load x[0...1]
VLD2.16 {d6[],d7[]}, [r4]!
; Use VAND since it's a data processing instruction again.
VAND d4, d5, d5
SUB r12, r12, #2
; Load y[4...5]
VLD1.32 {d5[]}, [r5]!
VMLAL.S16 q0, d4, d6
VEXT.16 d16, d4, d5, #1
; Replace bottom copy of {y5,y4} in d5 with {y3,y2} from d4, using VSRI
; instead of VEXT, since it's a data-processing instruction.
VSRI.64 d5, d4, #32
VMLAL.S16 q0, d16, d7
; Process 1 sample using the extra y value we loaded above.
xcorr_kernel_neon_process1
; Load next *x
VLD1.16 {d6[]}, [r4]!
ADDS r12, r12, #1
; y[0...3] are left in d5 from prior iteration(s) (if any)
VMLAL.S16 q0, d5, d6
MOVLE pc, lr
; Now process 1 last sample, not reading ahead.
; Load last *y
VLD1.16 {d4[]}, [r5]!
VSRI.64 d4, d5, #16
; Load last *x
VLD1.16 {d6[]}, [r4]!
VMLAL.S16 q0, d4, d6
MOV pc, lr
ENDP
; opus_val32 celt_pitch_xcorr_neon(opus_val16 *_x, opus_val16 *_y,
; opus_val32 *xcorr, int len, int max_pitch)
celt_pitch_xcorr_neon PROC
; input:
; r0 = opus_val16 *_x
; r1 = opus_val16 *_y
; r2 = opus_val32 *xcorr
; r3 = int len
; output:
; r0 = int maxcorr
; internal usage:
; r4 = opus_val16 *x (for xcorr_kernel_neon())
; r5 = opus_val16 *y (for xcorr_kernel_neon())
; r6 = int max_pitch
; r12 = int j
; q15 = int maxcorr[4] (q15 is not used by xcorr_kernel_neon())
STMFD sp!, {r4-r6, lr}
LDR r6, [sp, #16]
VMOV.S32 q15, #1
; if (max_pitch < 4) goto celt_pitch_xcorr_neon_process4_done
SUBS r6, r6, #4
BLT celt_pitch_xcorr_neon_process4_done
celt_pitch_xcorr_neon_process4
; xcorr_kernel_neon parameters:
; r3 = len, r4 = _x, r5 = _y, q0 = {0, 0, 0, 0}
MOV r4, r0
MOV r5, r1
VEOR q0, q0, q0
; xcorr_kernel_neon only modifies r4, r5, r12, and q0...q3.
; So we don't save/restore any other registers.
BL xcorr_kernel_neon_start
SUBS r6, r6, #4
VST1.32 {q0}, [r2]!
; _y += 4
ADD r1, r1, #8
VMAX.S32 q15, q15, q0
; if (max_pitch < 4) goto celt_pitch_xcorr_neon_process4_done
BGE celt_pitch_xcorr_neon_process4
; We have less than 4 sums left to compute.
celt_pitch_xcorr_neon_process4_done
ADDS r6, r6, #4
; Reduce maxcorr to a single value
VMAX.S32 d30, d30, d31
VPMAX.S32 d30, d30, d30
; if (max_pitch <= 0) goto celt_pitch_xcorr_neon_done
BLE celt_pitch_xcorr_neon_done
; Now compute each remaining sum one at a time.
celt_pitch_xcorr_neon_process_remaining
MOV r4, r0
MOV r5, r1
VMOV.I32 q0, #0
SUBS r12, r3, #8
BLT celt_pitch_xcorr_neon_process_remaining4
; Sum terms 8 at a time.
celt_pitch_xcorr_neon_process_remaining_loop8
; Load x[0...7]
VLD1.16 {q1}, [r4]!
; Load y[0...7]
VLD1.16 {q2}, [r5]!
SUBS r12, r12, #8
VMLAL.S16 q0, d4, d2
VMLAL.S16 q0, d5, d3
BGE celt_pitch_xcorr_neon_process_remaining_loop8
; Sum terms 4 at a time.
celt_pitch_xcorr_neon_process_remaining4
ADDS r12, r12, #4
BLT celt_pitch_xcorr_neon_process_remaining4_done
; Load x[0...3]
VLD1.16 {d2}, [r4]!
; Load y[0...3]
VLD1.16 {d3}, [r5]!
SUB r12, r12, #4
VMLAL.S16 q0, d3, d2
celt_pitch_xcorr_neon_process_remaining4_done
; Reduce the sum to a single value.
VADD.S32 d0, d0, d1
VPADDL.S32 d0, d0
ADDS r12, r12, #4
BLE celt_pitch_xcorr_neon_process_remaining_loop_done
; Sum terms 1 at a time.
celt_pitch_xcorr_neon_process_remaining_loop1
VLD1.16 {d2[]}, [r4]!
VLD1.16 {d3[]}, [r5]!
SUBS r12, r12, #1
VMLAL.S16 q0, d2, d3
BGT celt_pitch_xcorr_neon_process_remaining_loop1
celt_pitch_xcorr_neon_process_remaining_loop_done
VST1.32 {d0[0]}, [r2]!
VMAX.S32 d30, d30, d0
SUBS r6, r6, #1
; _y++
ADD r1, r1, #2
; if (--max_pitch > 0) goto celt_pitch_xcorr_neon_process_remaining
BGT celt_pitch_xcorr_neon_process_remaining
celt_pitch_xcorr_neon_done
VMOV.32 r0, d30[0]
LDMFD sp!, {r4-r6, pc}
ENDP
ENDIF
IF OPUS_ARM_MAY_HAVE_EDSP
; This will get used on ARMv7 devices without NEON, so it has been optimized
; to take advantage of dual-issuing where possible.
xcorr_kernel_edsp PROC
xcorr_kernel_edsp_start
; input:
; r3 = int len
; r4 = opus_val16 *_x (must be 32-bit aligned)
; r5 = opus_val16 *_y (must be 32-bit aligned)
; r6...r9 = opus_val32 sum[4]
; output:
; r6...r9 = opus_val32 sum[4]
; preserved: r0-r5
; internal usage
; r2 = int j
; r12,r14 = opus_val16 x[4]
; r10,r11 = opus_val16 y[4]
STMFD sp!, {r2,r4,r5,lr}
LDR r10, [r5], #4 ; Load y[0...1]
SUBS r2, r3, #4 ; j = len-4
LDR r11, [r5], #4 ; Load y[2...3]
BLE xcorr_kernel_edsp_process4_done
LDR r12, [r4], #4 ; Load x[0...1]
; Stall
xcorr_kernel_edsp_process4
; The multiplies must issue from pipeline 0, and can't dual-issue with each
; other. Every other instruction here dual-issues with a multiply, and is
; thus "free". There should be no stalls in the body of the loop.
SMLABB r6, r12, r10, r6 ; sum[0] = MAC16_16(sum[0],x_0,y_0)
LDR r14, [r4], #4 ; Load x[2...3]
SMLABT r7, r12, r10, r7 ; sum[1] = MAC16_16(sum[1],x_0,y_1)
SUBS r2, r2, #4 ; j-=4
SMLABB r8, r12, r11, r8 ; sum[2] = MAC16_16(sum[2],x_0,y_2)
SMLABT r9, r12, r11, r9 ; sum[3] = MAC16_16(sum[3],x_0,y_3)
SMLATT r6, r12, r10, r6 ; sum[0] = MAC16_16(sum[0],x_1,y_1)
LDR r10, [r5], #4 ; Load y[4...5]
SMLATB r7, r12, r11, r7 ; sum[1] = MAC16_16(sum[1],x_1,y_2)
SMLATT r8, r12, r11, r8 ; sum[2] = MAC16_16(sum[2],x_1,y_3)
SMLATB r9, r12, r10, r9 ; sum[3] = MAC16_16(sum[3],x_1,y_4)
LDRGT r12, [r4], #4 ; Load x[0...1]
SMLABB r6, r14, r11, r6 ; sum[0] = MAC16_16(sum[0],x_2,y_2)
SMLABT r7, r14, r11, r7 ; sum[1] = MAC16_16(sum[1],x_2,y_3)
SMLABB r8, r14, r10, r8 ; sum[2] = MAC16_16(sum[2],x_2,y_4)
SMLABT r9, r14, r10, r9 ; sum[3] = MAC16_16(sum[3],x_2,y_5)
SMLATT r6, r14, r11, r6 ; sum[0] = MAC16_16(sum[0],x_3,y_3)
LDR r11, [r5], #4 ; Load y[6...7]
SMLATB r7, r14, r10, r7 ; sum[1] = MAC16_16(sum[1],x_3,y_4)
SMLATT r8, r14, r10, r8 ; sum[2] = MAC16_16(sum[2],x_3,y_5)
SMLATB r9, r14, r11, r9 ; sum[3] = MAC16_16(sum[3],x_3,y_6)
BGT xcorr_kernel_edsp_process4
xcorr_kernel_edsp_process4_done
ADDS r2, r2, #4
BLE xcorr_kernel_edsp_done
LDRH r12, [r4], #2 ; r12 = *x++
SUBS r2, r2, #1 ; j--
; Stall
SMLABB r6, r12, r10, r6 ; sum[0] = MAC16_16(sum[0],x,y_0)
LDRHGT r14, [r4], #2 ; r14 = *x++
SMLABT r7, r12, r10, r7 ; sum[1] = MAC16_16(sum[1],x,y_1)
SMLABB r8, r12, r11, r8 ; sum[2] = MAC16_16(sum[2],x,y_2)
SMLABT r9, r12, r11, r9 ; sum[3] = MAC16_16(sum[3],x,y_3)
BLE xcorr_kernel_edsp_done
SMLABT r6, r14, r10, r6 ; sum[0] = MAC16_16(sum[0],x,y_1)
SUBS r2, r2, #1 ; j--
SMLABB r7, r14, r11, r7 ; sum[1] = MAC16_16(sum[1],x,y_2)
LDRH r10, [r5], #2 ; r10 = y_4 = *y++
SMLABT r8, r14, r11, r8 ; sum[2] = MAC16_16(sum[2],x,y_3)
LDRHGT r12, [r4], #2 ; r12 = *x++
SMLABB r9, r14, r10, r9 ; sum[3] = MAC16_16(sum[3],x,y_4)
BLE xcorr_kernel_edsp_done
SMLABB r6, r12, r11, r6 ; sum[0] = MAC16_16(sum[0],tmp,y_2)
CMP r2, #1 ; j--
SMLABT r7, r12, r11, r7 ; sum[1] = MAC16_16(sum[1],tmp,y_3)
LDRH r2, [r5], #2 ; r2 = y_5 = *y++
SMLABB r8, r12, r10, r8 ; sum[2] = MAC16_16(sum[2],tmp,y_4)
LDRHGT r14, [r4] ; r14 = *x
SMLABB r9, r12, r2, r9 ; sum[3] = MAC16_16(sum[3],tmp,y_5)
BLE xcorr_kernel_edsp_done
SMLABT r6, r14, r11, r6 ; sum[0] = MAC16_16(sum[0],tmp,y_3)
LDRH r11, [r5] ; r11 = y_6 = *y
SMLABB r7, r14, r10, r7 ; sum[1] = MAC16_16(sum[1],tmp,y_4)
SMLABB r8, r14, r2, r8 ; sum[2] = MAC16_16(sum[2],tmp,y_5)
SMLABB r9, r14, r11, r9 ; sum[3] = MAC16_16(sum[3],tmp,y_6)
xcorr_kernel_edsp_done
LDMFD sp!, {r2,r4,r5,pc}
ENDP
celt_pitch_xcorr_edsp PROC
; input:
; r0 = opus_val16 *_x (must be 32-bit aligned)
; r1 = opus_val16 *_y (only needs to be 16-bit aligned)
; r2 = opus_val32 *xcorr
; r3 = int len
; output:
; r0 = maxcorr
; internal usage
; r4 = opus_val16 *x
; r5 = opus_val16 *y
; r6 = opus_val32 sum0
; r7 = opus_val32 sum1
; r8 = opus_val32 sum2
; r9 = opus_val32 sum3
; r1 = int max_pitch
; r12 = int j
STMFD sp!, {r4-r11, lr}
MOV r5, r1
LDR r1, [sp, #36]
MOV r4, r0
TST r5, #3
; maxcorr = 1
MOV r0, #1
BEQ celt_pitch_xcorr_edsp_process1u_done
; Compute one sum at the start to make y 32-bit aligned.
SUBS r12, r3, #4
; r14 = sum = 0
MOV r14, #0
LDRH r8, [r5], #2
BLE celt_pitch_xcorr_edsp_process1u_loop4_done
LDR r6, [r4], #4
MOV r8, r8, LSL #16
celt_pitch_xcorr_edsp_process1u_loop4
LDR r9, [r5], #4
SMLABT r14, r6, r8, r14 ; sum = MAC16_16(sum, x_0, y_0)
LDR r7, [r4], #4
SMLATB r14, r6, r9, r14 ; sum = MAC16_16(sum, x_1, y_1)
LDR r8, [r5], #4
SMLABT r14, r7, r9, r14 ; sum = MAC16_16(sum, x_2, y_2)
SUBS r12, r12, #4 ; j-=4
SMLATB r14, r7, r8, r14 ; sum = MAC16_16(sum, x_3, y_3)
LDRGT r6, [r4], #4
BGT celt_pitch_xcorr_edsp_process1u_loop4
MOV r8, r8, LSR #16
celt_pitch_xcorr_edsp_process1u_loop4_done
ADDS r12, r12, #4
celt_pitch_xcorr_edsp_process1u_loop1
LDRHGE r6, [r4], #2
; Stall
SMLABBGE r14, r6, r8, r14 ; sum = MAC16_16(sum, *x, *y)
SUBSGE r12, r12, #1
LDRHGT r8, [r5], #2
BGT celt_pitch_xcorr_edsp_process1u_loop1
; Restore _x
SUB r4, r4, r3, LSL #1
; Restore and advance _y
SUB r5, r5, r3, LSL #1
; maxcorr = max(maxcorr, sum)
CMP r0, r14
ADD r5, r5, #2
MOVLT r0, r14
SUBS r1, r1, #1
; xcorr[i] = sum
STR r14, [r2], #4
BLE celt_pitch_xcorr_edsp_done
celt_pitch_xcorr_edsp_process1u_done
; if (max_pitch < 4) goto celt_pitch_xcorr_edsp_process2
SUBS r1, r1, #4
BLT celt_pitch_xcorr_edsp_process2
celt_pitch_xcorr_edsp_process4
; xcorr_kernel_edsp parameters:
; r3 = len, r4 = _x, r5 = _y, r6...r9 = sum[4] = {0, 0, 0, 0}
MOV r6, #0
MOV r7, #0
MOV r8, #0
MOV r9, #0
BL xcorr_kernel_edsp_start ; xcorr_kernel_edsp(_x, _y+i, xcorr+i, len)
; maxcorr = max(maxcorr, sum0, sum1, sum2, sum3)
CMP r0, r6
; _y+=4
ADD r5, r5, #8
MOVLT r0, r6
CMP r0, r7
MOVLT r0, r7
CMP r0, r8
MOVLT r0, r8
CMP r0, r9
MOVLT r0, r9
STMIA r2!, {r6-r9}
SUBS r1, r1, #4
BGE celt_pitch_xcorr_edsp_process4
celt_pitch_xcorr_edsp_process2
ADDS r1, r1, #2
BLT celt_pitch_xcorr_edsp_process1a
SUBS r12, r3, #4
; {r10, r11} = {sum0, sum1} = {0, 0}
MOV r10, #0
MOV r11, #0
LDR r8, [r5], #4
BLE celt_pitch_xcorr_edsp_process2_loop_done
LDR r6, [r4], #4
LDR r9, [r5], #4
celt_pitch_xcorr_edsp_process2_loop4
SMLABB r10, r6, r8, r10 ; sum0 = MAC16_16(sum0, x_0, y_0)
LDR r7, [r4], #4
SMLABT r11, r6, r8, r11 ; sum1 = MAC16_16(sum1, x_0, y_1)
SUBS r12, r12, #4 ; j-=4
SMLATT r10, r6, r8, r10 ; sum0 = MAC16_16(sum0, x_1, y_1)
LDR r8, [r5], #4
SMLATB r11, r6, r9, r11 ; sum1 = MAC16_16(sum1, x_1, y_2)
LDRGT r6, [r4], #4
SMLABB r10, r7, r9, r10 ; sum0 = MAC16_16(sum0, x_2, y_2)
SMLABT r11, r7, r9, r11 ; sum1 = MAC16_16(sum1, x_2, y_3)
SMLATT r10, r7, r9, r10 ; sum0 = MAC16_16(sum0, x_3, y_3)
LDRGT r9, [r5], #4
SMLATB r11, r7, r8, r11 ; sum1 = MAC16_16(sum1, x_3, y_4)
BGT celt_pitch_xcorr_edsp_process2_loop4
celt_pitch_xcorr_edsp_process2_loop_done
ADDS r12, r12, #2
BLE celt_pitch_xcorr_edsp_process2_1
LDR r6, [r4], #4
; Stall
SMLABB r10, r6, r8, r10 ; sum0 = MAC16_16(sum0, x_0, y_0)
LDR r9, [r5], #4
SMLABT r11, r6, r8, r11 ; sum1 = MAC16_16(sum1, x_0, y_1)
SUB r12, r12, #2
SMLATT r10, r6, r8, r10 ; sum0 = MAC16_16(sum0, x_1, y_1)
MOV r8, r9
SMLATB r11, r6, r9, r11 ; sum1 = MAC16_16(sum1, x_1, y_2)
celt_pitch_xcorr_edsp_process2_1
LDRH r6, [r4], #2
ADDS r12, r12, #1
; Stall
SMLABB r10, r6, r8, r10 ; sum0 = MAC16_16(sum0, x_0, y_0)
LDRHGT r7, [r4], #2
SMLABT r11, r6, r8, r11 ; sum1 = MAC16_16(sum1, x_0, y_1)
BLE celt_pitch_xcorr_edsp_process2_done
LDRH r9, [r5], #2
SMLABT r10, r7, r8, r10 ; sum0 = MAC16_16(sum0, x_0, y_1)
SMLABB r11, r7, r9, r11 ; sum1 = MAC16_16(sum1, x_0, y_2)
celt_pitch_xcorr_edsp_process2_done
; Restore _x
SUB r4, r4, r3, LSL #1
; Restore and advance _y
SUB r5, r5, r3, LSL #1
; maxcorr = max(maxcorr, sum0)
CMP r0, r10
ADD r5, r5, #2
MOVLT r0, r10
SUB r1, r1, #2
; maxcorr = max(maxcorr, sum1)
CMP r0, r11
; xcorr[i] = sum
STR r10, [r2], #4
MOVLT r0, r11
STR r11, [r2], #4
celt_pitch_xcorr_edsp_process1a
ADDS r1, r1, #1
BLT celt_pitch_xcorr_edsp_done
SUBS r12, r3, #4
; r14 = sum = 0
MOV r14, #0
BLT celt_pitch_xcorr_edsp_process1a_loop_done
LDR r6, [r4], #4
LDR r8, [r5], #4
LDR r7, [r4], #4
LDR r9, [r5], #4
celt_pitch_xcorr_edsp_process1a_loop4
SMLABB r14, r6, r8, r14 ; sum = MAC16_16(sum, x_0, y_0)
SUBS r12, r12, #4 ; j-=4
SMLATT r14, r6, r8, r14 ; sum = MAC16_16(sum, x_1, y_1)
LDRGE r6, [r4], #4
SMLABB r14, r7, r9, r14 ; sum = MAC16_16(sum, x_2, y_2)
LDRGE r8, [r5], #4
SMLATT r14, r7, r9, r14 ; sum = MAC16_16(sum, x_3, y_3)
LDRGE r7, [r4], #4
LDRGE r9, [r5], #4
BGE celt_pitch_xcorr_edsp_process1a_loop4
celt_pitch_xcorr_edsp_process1a_loop_done
ADDS r12, r12, #2
LDRGE r6, [r4], #4
LDRGE r8, [r5], #4
; Stall
SMLABBGE r14, r6, r8, r14 ; sum = MAC16_16(sum, x_0, y_0)
SUBGE r12, r12, #2
SMLATTGE r14, r6, r8, r14 ; sum = MAC16_16(sum, x_1, y_1)
ADDS r12, r12, #1
LDRHGE r6, [r4], #2
LDRHGE r8, [r5], #2
; Stall
SMLABBGE r14, r6, r8, r14 ; sum = MAC16_16(sum, *x, *y)
; maxcorr = max(maxcorr, sum)
CMP r0, r14
; xcorr[i] = sum
STR r14, [r2], #4
MOVLT r0, r14
celt_pitch_xcorr_edsp_done
LDMFD sp!, {r4-r11, pc}
ENDP
ENDIF
END
|
AGProjects/python-sipsimple
| 20,415
|
deps/pjsip/third_party/opus/celt/arm/celt_pitch_xcorr_arm-gnu.S
|
.syntax unified
@ Copyright (c) 2007-2008 CSIRO
@ Copyright (c) 2007-2009 Xiph.Org Foundation
@ Copyright (c) 2013 Parrot
@ Written by Aurélien Zanelli
@
@ Redistribution and use in source and binary forms, with or without
@ modification, are permitted provided that the following conditions
@ are met:
@
@ - Redistributions of source code must retain the above copyright
@ notice, this list of conditions and the following disclaimer.
@
@ - Redistributions in binary form must reproduce the above copyright
@ notice, this list of conditions and the following disclaimer in the
@ documentation and/or other materials provided with the distribution.
@
@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
@ ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
@ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
@ OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
@ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
@ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
@ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
@ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
@ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
.text; .p2align 2; .arch armv7-a
.fpu neon
.object_arch armv4t
.include "celt/arm/armopts-gnu.S"
.if OPUS_ARM_MAY_HAVE_EDSP
.global celt_pitch_xcorr_edsp
.endif
.if OPUS_ARM_MAY_HAVE_NEON
.global celt_pitch_xcorr_neon
.endif
.if OPUS_ARM_MAY_HAVE_NEON
@ Compute sum[k]=sum(x[j]*y[j+k],j=0...len-1), k=0...3
; xcorr_kernel_neon: @ PROC
xcorr_kernel_neon_start:
@ input:
@ r3 = int len
@ r4 = opus_val16 *x
@ r5 = opus_val16 *y
@ q0 = opus_val32 sum[4]
@ output:
@ q0 = opus_val32 sum[4]
@ preserved: r0-r3, r6-r11, d2, q4-q7, q9-q15
@ internal usage:
@ r12 = int j
@ d3 = y_3|y_2|y_1|y_0
@ q2 = y_B|y_A|y_9|y_8|y_7|y_6|y_5|y_4
@ q3 = x_7|x_6|x_5|x_4|x_3|x_2|x_1|x_0
@ q8 = scratch
@
@ Load y[0...3]
@ This requires len>0 to always be valid (which we assert in the C code).
VLD1.16 {d5}, [r5]!
SUBS r12, r3, #8
BLE xcorr_kernel_neon_process4
@ Process 8 samples at a time.
@ This loop loads one y value more than we actually need. Therefore we have to
@ stop as soon as there are 8 or fewer samples left (instead of 7), to avoid
@ reading past the end of the array.
xcorr_kernel_neon_process8:
@ This loop has 19 total instructions (10 cycles to issue, minimum), with
@ - 2 cycles of ARM insrtuctions,
@ - 10 cycles of load/store/byte permute instructions, and
@ - 9 cycles of data processing instructions.
@ On a Cortex A8, we dual-issue the maximum amount (9 cycles) between the
@ latter two categories, meaning the whole loop should run in 10 cycles per
@ iteration, barring cache misses.
@
@ Load x[0...7]
VLD1.16 {d6, d7}, [r4]!
@ Unlike VMOV, VAND is a data processsing instruction (and doesn't get
@ assembled to VMOV, like VORR would), so it dual-issues with the prior VLD1.
VAND d3, d5, d5
SUBS r12, r12, #8
@ Load y[4...11]
VLD1.16 {d4, d5}, [r5]!
VMLAL.S16 q0, d3, d6[0]
VEXT.16 d16, d3, d4, #1
VMLAL.S16 q0, d4, d7[0]
VEXT.16 d17, d4, d5, #1
VMLAL.S16 q0, d16, d6[1]
VEXT.16 d16, d3, d4, #2
VMLAL.S16 q0, d17, d7[1]
VEXT.16 d17, d4, d5, #2
VMLAL.S16 q0, d16, d6[2]
VEXT.16 d16, d3, d4, #3
VMLAL.S16 q0, d17, d7[2]
VEXT.16 d17, d4, d5, #3
VMLAL.S16 q0, d16, d6[3]
VMLAL.S16 q0, d17, d7[3]
BGT xcorr_kernel_neon_process8
@ Process 4 samples here if we have > 4 left (still reading one extra y value).
xcorr_kernel_neon_process4:
ADDS r12, r12, #4
BLE xcorr_kernel_neon_process2
@ Load x[0...3]
VLD1.16 d6, [r4]!
@ Use VAND since it's a data processing instruction again.
VAND d4, d5, d5
SUB r12, r12, #4
@ Load y[4...7]
VLD1.16 d5, [r5]!
VMLAL.S16 q0, d4, d6[0]
VEXT.16 d16, d4, d5, #1
VMLAL.S16 q0, d16, d6[1]
VEXT.16 d16, d4, d5, #2
VMLAL.S16 q0, d16, d6[2]
VEXT.16 d16, d4, d5, #3
VMLAL.S16 q0, d16, d6[3]
@ Process 2 samples here if we have > 2 left (still reading one extra y value).
xcorr_kernel_neon_process2:
ADDS r12, r12, #2
BLE xcorr_kernel_neon_process1
@ Load x[0...1]
VLD2.16 {d6[],d7[]}, [r4]!
@ Use VAND since it's a data processing instruction again.
VAND d4, d5, d5
SUB r12, r12, #2
@ Load y[4...5]
VLD1.32 {d5[]}, [r5]!
VMLAL.S16 q0, d4, d6
VEXT.16 d16, d4, d5, #1
@ Replace bottom copy of {y5,y4} in d5 with {y3,y2} from d4, using VSRI
@ instead of VEXT, since it's a data-processing instruction.
VSRI.64 d5, d4, #32
VMLAL.S16 q0, d16, d7
@ Process 1 sample using the extra y value we loaded above.
xcorr_kernel_neon_process1:
@ Load next *x
VLD1.16 {d6[]}, [r4]!
ADDS r12, r12, #1
@ y[0...3] are left in d5 from prior iteration(s) (if any)
VMLAL.S16 q0, d5, d6
MOVLE pc, lr
@ Now process 1 last sample, not reading ahead.
@ Load last *y
VLD1.16 {d4[]}, [r5]!
VSRI.64 d4, d5, #16
@ Load last *x
VLD1.16 {d6[]}, [r4]!
VMLAL.S16 q0, d4, d6
MOV pc, lr
.size xcorr_kernel_neon, .-xcorr_kernel_neon @ ENDP
@ opus_val32 celt_pitch_xcorr_neon(opus_val16 *_x, opus_val16 *_y,
@ opus_val32 *xcorr, int len, int max_pitch)
; celt_pitch_xcorr_neon: @ PROC
@ input:
@ r0 = opus_val16 *_x
@ r1 = opus_val16 *_y
@ r2 = opus_val32 *xcorr
@ r3 = int len
@ output:
@ r0 = int maxcorr
@ internal usage:
@ r4 = opus_val16 *x (for xcorr_kernel_neon())
@ r5 = opus_val16 *y (for xcorr_kernel_neon())
@ r6 = int max_pitch
@ r12 = int j
@ q15 = int maxcorr[4] (q15 is not used by xcorr_kernel_neon())
STMFD sp!, {r4-r6, lr}
LDR r6, [sp, #16]
VMOV.S32 q15, #1
@ if (max_pitch < 4) goto celt_pitch_xcorr_neon_process4_done
SUBS r6, r6, #4
BLT celt_pitch_xcorr_neon_process4_done
celt_pitch_xcorr_neon_process4:
@ xcorr_kernel_neon parameters:
@ r3 = len, r4 = _x, r5 = _y, q0 = {0, 0, 0, 0}
MOV r4, r0
MOV r5, r1
VEOR q0, q0, q0
@ xcorr_kernel_neon only modifies r4, r5, r12, and q0...q3.
@ So we don't save/restore any other registers.
BL xcorr_kernel_neon_start
SUBS r6, r6, #4
VST1.32 {q0}, [r2]!
@ _y += 4
ADD r1, r1, #8
VMAX.S32 q15, q15, q0
@ if (max_pitch < 4) goto celt_pitch_xcorr_neon_process4_done
BGE celt_pitch_xcorr_neon_process4
@ We have less than 4 sums left to compute.
celt_pitch_xcorr_neon_process4_done:
ADDS r6, r6, #4
@ Reduce maxcorr to a single value
VMAX.S32 d30, d30, d31
VPMAX.S32 d30, d30, d30
@ if (max_pitch <= 0) goto celt_pitch_xcorr_neon_done
BLE celt_pitch_xcorr_neon_done
@ Now compute each remaining sum one at a time.
celt_pitch_xcorr_neon_process_remaining:
MOV r4, r0
MOV r5, r1
VMOV.I32 q0, #0
SUBS r12, r3, #8
BLT celt_pitch_xcorr_neon_process_remaining4
@ Sum terms 8 at a time.
celt_pitch_xcorr_neon_process_remaining_loop8:
@ Load x[0...7]
VLD1.16 {q1}, [r4]!
@ Load y[0...7]
VLD1.16 {q2}, [r5]!
SUBS r12, r12, #8
VMLAL.S16 q0, d4, d2
VMLAL.S16 q0, d5, d3
BGE celt_pitch_xcorr_neon_process_remaining_loop8
@ Sum terms 4 at a time.
celt_pitch_xcorr_neon_process_remaining4:
ADDS r12, r12, #4
BLT celt_pitch_xcorr_neon_process_remaining4_done
@ Load x[0...3]
VLD1.16 {d2}, [r4]!
@ Load y[0...3]
VLD1.16 {d3}, [r5]!
SUB r12, r12, #4
VMLAL.S16 q0, d3, d2
celt_pitch_xcorr_neon_process_remaining4_done:
@ Reduce the sum to a single value.
VADD.S32 d0, d0, d1
VPADDL.S32 d0, d0
ADDS r12, r12, #4
BLE celt_pitch_xcorr_neon_process_remaining_loop_done
@ Sum terms 1 at a time.
celt_pitch_xcorr_neon_process_remaining_loop1:
VLD1.16 {d2[]}, [r4]!
VLD1.16 {d3[]}, [r5]!
SUBS r12, r12, #1
VMLAL.S16 q0, d2, d3
BGT celt_pitch_xcorr_neon_process_remaining_loop1
celt_pitch_xcorr_neon_process_remaining_loop_done:
VST1.32 {d0[0]}, [r2]!
VMAX.S32 d30, d30, d0
SUBS r6, r6, #1
@ _y++
ADD r1, r1, #2
@ if (--max_pitch > 0) goto celt_pitch_xcorr_neon_process_remaining
BGT celt_pitch_xcorr_neon_process_remaining
celt_pitch_xcorr_neon_done:
VMOV.32 r0, d30[0]
LDMFD sp!, {r4-r6, pc}
.size celt_pitch_xcorr_neon, .-celt_pitch_xcorr_neon @ ENDP
.endif
.if OPUS_ARM_MAY_HAVE_EDSP
@ This will get used on ARMv7 devices without NEON, so it has been optimized
@ to take advantage of dual-issuing where possible.
; xcorr_kernel_edsp: @ PROC
xcorr_kernel_edsp_start:
@ input:
@ r3 = int len
@ r4 = opus_val16 *_x (must be 32-bit aligned)
@ r5 = opus_val16 *_y (must be 32-bit aligned)
@ r6...r9 = opus_val32 sum[4]
@ output:
@ r6...r9 = opus_val32 sum[4]
@ preserved: r0-r5
@ internal usage
@ r2 = int j
@ r12,r14 = opus_val16 x[4]
@ r10,r11 = opus_val16 y[4]
STMFD sp!, {r2,r4,r5,lr}
LDR r10, [r5], #4 @ Load y[0...1]
SUBS r2, r3, #4 @ j = len-4
LDR r11, [r5], #4 @ Load y[2...3]
BLE xcorr_kernel_edsp_process4_done
LDR r12, [r4], #4 @ Load x[0...1]
@ Stall
xcorr_kernel_edsp_process4:
@ The multiplies must issue from pipeline 0, and can't dual-issue with each
@ other. Every other instruction here dual-issues with a multiply, and is
@ thus "free". There should be no stalls in the body of the loop.
SMLABB r6, r12, r10, r6 @ sum[0] = MAC16_16(sum[0],x_0,y_0)
LDR r14, [r4], #4 @ Load x[2...3]
SMLABT r7, r12, r10, r7 @ sum[1] = MAC16_16(sum[1],x_0,y_1)
SUBS r2, r2, #4 @ j-=4
SMLABB r8, r12, r11, r8 @ sum[2] = MAC16_16(sum[2],x_0,y_2)
SMLABT r9, r12, r11, r9 @ sum[3] = MAC16_16(sum[3],x_0,y_3)
SMLATT r6, r12, r10, r6 @ sum[0] = MAC16_16(sum[0],x_1,y_1)
LDR r10, [r5], #4 @ Load y[4...5]
SMLATB r7, r12, r11, r7 @ sum[1] = MAC16_16(sum[1],x_1,y_2)
SMLATT r8, r12, r11, r8 @ sum[2] = MAC16_16(sum[2],x_1,y_3)
SMLATB r9, r12, r10, r9 @ sum[3] = MAC16_16(sum[3],x_1,y_4)
LDRGT r12, [r4], #4 @ Load x[0...1]
SMLABB r6, r14, r11, r6 @ sum[0] = MAC16_16(sum[0],x_2,y_2)
SMLABT r7, r14, r11, r7 @ sum[1] = MAC16_16(sum[1],x_2,y_3)
SMLABB r8, r14, r10, r8 @ sum[2] = MAC16_16(sum[2],x_2,y_4)
SMLABT r9, r14, r10, r9 @ sum[3] = MAC16_16(sum[3],x_2,y_5)
SMLATT r6, r14, r11, r6 @ sum[0] = MAC16_16(sum[0],x_3,y_3)
LDR r11, [r5], #4 @ Load y[6...7]
SMLATB r7, r14, r10, r7 @ sum[1] = MAC16_16(sum[1],x_3,y_4)
SMLATT r8, r14, r10, r8 @ sum[2] = MAC16_16(sum[2],x_3,y_5)
SMLATB r9, r14, r11, r9 @ sum[3] = MAC16_16(sum[3],x_3,y_6)
BGT xcorr_kernel_edsp_process4
xcorr_kernel_edsp_process4_done:
ADDS r2, r2, #4
BLE xcorr_kernel_edsp_done
LDRH r12, [r4], #2 @ r12 = *x++
SUBS r2, r2, #1 @ j--
@ Stall
SMLABB r6, r12, r10, r6 @ sum[0] = MAC16_16(sum[0],x,y_0)
LDRHGT r14, [r4], #2 @ r14 = *x++
SMLABT r7, r12, r10, r7 @ sum[1] = MAC16_16(sum[1],x,y_1)
SMLABB r8, r12, r11, r8 @ sum[2] = MAC16_16(sum[2],x,y_2)
SMLABT r9, r12, r11, r9 @ sum[3] = MAC16_16(sum[3],x,y_3)
BLE xcorr_kernel_edsp_done
SMLABT r6, r14, r10, r6 @ sum[0] = MAC16_16(sum[0],x,y_1)
SUBS r2, r2, #1 @ j--
SMLABB r7, r14, r11, r7 @ sum[1] = MAC16_16(sum[1],x,y_2)
LDRH r10, [r5], #2 @ r10 = y_4 = *y++
SMLABT r8, r14, r11, r8 @ sum[2] = MAC16_16(sum[2],x,y_3)
LDRHGT r12, [r4], #2 @ r12 = *x++
SMLABB r9, r14, r10, r9 @ sum[3] = MAC16_16(sum[3],x,y_4)
BLE xcorr_kernel_edsp_done
SMLABB r6, r12, r11, r6 @ sum[0] = MAC16_16(sum[0],tmp,y_2)
CMP r2, #1 @ j--
SMLABT r7, r12, r11, r7 @ sum[1] = MAC16_16(sum[1],tmp,y_3)
LDRH r2, [r5], #2 @ r2 = y_5 = *y++
SMLABB r8, r12, r10, r8 @ sum[2] = MAC16_16(sum[2],tmp,y_4)
LDRHGT r14, [r4] @ r14 = *x
SMLABB r9, r12, r2, r9 @ sum[3] = MAC16_16(sum[3],tmp,y_5)
BLE xcorr_kernel_edsp_done
SMLABT r6, r14, r11, r6 @ sum[0] = MAC16_16(sum[0],tmp,y_3)
LDRH r11, [r5] @ r11 = y_6 = *y
SMLABB r7, r14, r10, r7 @ sum[1] = MAC16_16(sum[1],tmp,y_4)
SMLABB r8, r14, r2, r8 @ sum[2] = MAC16_16(sum[2],tmp,y_5)
SMLABB r9, r14, r11, r9 @ sum[3] = MAC16_16(sum[3],tmp,y_6)
xcorr_kernel_edsp_done:
LDMFD sp!, {r2,r4,r5,pc}
.size xcorr_kernel_edsp, .-xcorr_kernel_edsp @ ENDP
; celt_pitch_xcorr_edsp: @ PROC
@ input:
@ r0 = opus_val16 *_x (must be 32-bit aligned)
@ r1 = opus_val16 *_y (only needs to be 16-bit aligned)
@ r2 = opus_val32 *xcorr
@ r3 = int len
@ output:
@ r0 = maxcorr
@ internal usage
@ r4 = opus_val16 *x
@ r5 = opus_val16 *y
@ r6 = opus_val32 sum0
@ r7 = opus_val32 sum1
@ r8 = opus_val32 sum2
@ r9 = opus_val32 sum3
@ r1 = int max_pitch
@ r12 = int j
STMFD sp!, {r4-r11, lr}
MOV r5, r1
LDR r1, [sp, #36]
MOV r4, r0
TST r5, #3
@ maxcorr = 1
MOV r0, #1
BEQ celt_pitch_xcorr_edsp_process1u_done
@ Compute one sum at the start to make y 32-bit aligned.
SUBS r12, r3, #4
@ r14 = sum = 0
MOV r14, #0
LDRH r8, [r5], #2
BLE celt_pitch_xcorr_edsp_process1u_loop4_done
LDR r6, [r4], #4
MOV r8, r8, LSL #16
celt_pitch_xcorr_edsp_process1u_loop4:
LDR r9, [r5], #4
SMLABT r14, r6, r8, r14 @ sum = MAC16_16(sum, x_0, y_0)
LDR r7, [r4], #4
SMLATB r14, r6, r9, r14 @ sum = MAC16_16(sum, x_1, y_1)
LDR r8, [r5], #4
SMLABT r14, r7, r9, r14 @ sum = MAC16_16(sum, x_2, y_2)
SUBS r12, r12, #4 @ j-=4
SMLATB r14, r7, r8, r14 @ sum = MAC16_16(sum, x_3, y_3)
LDRGT r6, [r4], #4
BGT celt_pitch_xcorr_edsp_process1u_loop4
MOV r8, r8, LSR #16
celt_pitch_xcorr_edsp_process1u_loop4_done:
ADDS r12, r12, #4
celt_pitch_xcorr_edsp_process1u_loop1:
LDRHGE r6, [r4], #2
@ Stall
SMLABBGE r14, r6, r8, r14 @ sum = MAC16_16(sum, *x, *y)
SUBSGE r12, r12, #1
LDRHGT r8, [r5], #2
BGT celt_pitch_xcorr_edsp_process1u_loop1
@ Restore _x
SUB r4, r4, r3, LSL #1
@ Restore and advance _y
SUB r5, r5, r3, LSL #1
@ maxcorr = max(maxcorr, sum)
CMP r0, r14
ADD r5, r5, #2
MOVLT r0, r14
SUBS r1, r1, #1
@ xcorr[i] = sum
STR r14, [r2], #4
BLE celt_pitch_xcorr_edsp_done
celt_pitch_xcorr_edsp_process1u_done:
@ if (max_pitch < 4) goto celt_pitch_xcorr_edsp_process2
SUBS r1, r1, #4
BLT celt_pitch_xcorr_edsp_process2
celt_pitch_xcorr_edsp_process4:
@ xcorr_kernel_edsp parameters:
@ r3 = len, r4 = _x, r5 = _y, r6...r9 = sum[4] = {0, 0, 0, 0}
MOV r6, #0
MOV r7, #0
MOV r8, #0
MOV r9, #0
BL xcorr_kernel_edsp_start @ xcorr_kernel_edsp(_x, _y+i, xcorr+i, len)
@ maxcorr = max(maxcorr, sum0, sum1, sum2, sum3)
CMP r0, r6
@ _y+=4
ADD r5, r5, #8
MOVLT r0, r6
CMP r0, r7
MOVLT r0, r7
CMP r0, r8
MOVLT r0, r8
CMP r0, r9
MOVLT r0, r9
STMIA r2!, {r6-r9}
SUBS r1, r1, #4
BGE celt_pitch_xcorr_edsp_process4
celt_pitch_xcorr_edsp_process2:
ADDS r1, r1, #2
BLT celt_pitch_xcorr_edsp_process1a
SUBS r12, r3, #4
@ {r10, r11} = {sum0, sum1} = {0, 0}
MOV r10, #0
MOV r11, #0
LDR r8, [r5], #4
BLE celt_pitch_xcorr_edsp_process2_loop_done
LDR r6, [r4], #4
LDR r9, [r5], #4
celt_pitch_xcorr_edsp_process2_loop4:
SMLABB r10, r6, r8, r10 @ sum0 = MAC16_16(sum0, x_0, y_0)
LDR r7, [r4], #4
SMLABT r11, r6, r8, r11 @ sum1 = MAC16_16(sum1, x_0, y_1)
SUBS r12, r12, #4 @ j-=4
SMLATT r10, r6, r8, r10 @ sum0 = MAC16_16(sum0, x_1, y_1)
LDR r8, [r5], #4
SMLATB r11, r6, r9, r11 @ sum1 = MAC16_16(sum1, x_1, y_2)
LDRGT r6, [r4], #4
SMLABB r10, r7, r9, r10 @ sum0 = MAC16_16(sum0, x_2, y_2)
SMLABT r11, r7, r9, r11 @ sum1 = MAC16_16(sum1, x_2, y_3)
SMLATT r10, r7, r9, r10 @ sum0 = MAC16_16(sum0, x_3, y_3)
LDRGT r9, [r5], #4
SMLATB r11, r7, r8, r11 @ sum1 = MAC16_16(sum1, x_3, y_4)
BGT celt_pitch_xcorr_edsp_process2_loop4
celt_pitch_xcorr_edsp_process2_loop_done:
ADDS r12, r12, #2
BLE celt_pitch_xcorr_edsp_process2_1
LDR r6, [r4], #4
@ Stall
SMLABB r10, r6, r8, r10 @ sum0 = MAC16_16(sum0, x_0, y_0)
LDR r9, [r5], #4
SMLABT r11, r6, r8, r11 @ sum1 = MAC16_16(sum1, x_0, y_1)
SUB r12, r12, #2
SMLATT r10, r6, r8, r10 @ sum0 = MAC16_16(sum0, x_1, y_1)
MOV r8, r9
SMLATB r11, r6, r9, r11 @ sum1 = MAC16_16(sum1, x_1, y_2)
celt_pitch_xcorr_edsp_process2_1:
LDRH r6, [r4], #2
ADDS r12, r12, #1
@ Stall
SMLABB r10, r6, r8, r10 @ sum0 = MAC16_16(sum0, x_0, y_0)
LDRHGT r7, [r4], #2
SMLABT r11, r6, r8, r11 @ sum1 = MAC16_16(sum1, x_0, y_1)
BLE celt_pitch_xcorr_edsp_process2_done
LDRH r9, [r5], #2
SMLABT r10, r7, r8, r10 @ sum0 = MAC16_16(sum0, x_0, y_1)
SMLABB r11, r7, r9, r11 @ sum1 = MAC16_16(sum1, x_0, y_2)
celt_pitch_xcorr_edsp_process2_done:
@ Restore _x
SUB r4, r4, r3, LSL #1
@ Restore and advance _y
SUB r5, r5, r3, LSL #1
@ maxcorr = max(maxcorr, sum0)
CMP r0, r10
ADD r5, r5, #2
MOVLT r0, r10
SUB r1, r1, #2
@ maxcorr = max(maxcorr, sum1)
CMP r0, r11
@ xcorr[i] = sum
STR r10, [r2], #4
MOVLT r0, r11
STR r11, [r2], #4
celt_pitch_xcorr_edsp_process1a:
ADDS r1, r1, #1
BLT celt_pitch_xcorr_edsp_done
SUBS r12, r3, #4
@ r14 = sum = 0
MOV r14, #0
BLT celt_pitch_xcorr_edsp_process1a_loop_done
LDR r6, [r4], #4
LDR r8, [r5], #4
LDR r7, [r4], #4
LDR r9, [r5], #4
celt_pitch_xcorr_edsp_process1a_loop4:
SMLABB r14, r6, r8, r14 @ sum = MAC16_16(sum, x_0, y_0)
SUBS r12, r12, #4 @ j-=4
SMLATT r14, r6, r8, r14 @ sum = MAC16_16(sum, x_1, y_1)
LDRGE r6, [r4], #4
SMLABB r14, r7, r9, r14 @ sum = MAC16_16(sum, x_2, y_2)
LDRGE r8, [r5], #4
SMLATT r14, r7, r9, r14 @ sum = MAC16_16(sum, x_3, y_3)
LDRGE r7, [r4], #4
LDRGE r9, [r5], #4
BGE celt_pitch_xcorr_edsp_process1a_loop4
celt_pitch_xcorr_edsp_process1a_loop_done:
ADDS r12, r12, #2
LDRGE r6, [r4], #4
LDRGE r8, [r5], #4
@ Stall
SMLABBGE r14, r6, r8, r14 @ sum = MAC16_16(sum, x_0, y_0)
SUBGE r12, r12, #2
SMLATTGE r14, r6, r8, r14 @ sum = MAC16_16(sum, x_1, y_1)
ADDS r12, r12, #1
LDRHGE r6, [r4], #2
LDRHGE r8, [r5], #2
@ Stall
SMLABBGE r14, r6, r8, r14 @ sum = MAC16_16(sum, *x, *y)
@ maxcorr = max(maxcorr, sum)
CMP r0, r14
@ xcorr[i] = sum
STR r14, [r2], #4
MOVLT r0, r14
celt_pitch_xcorr_edsp_done:
LDMFD sp!, {r4-r11, pc}
.size celt_pitch_xcorr_edsp, .-celt_pitch_xcorr_edsp @ ENDP
.endif
@ END:
.section .note.GNU-stack,"",%progbits
|
agsb/milliForth-6502
| 27,489
|
tsts/sector-6502-tst.s
|
;----------------------------------------------------------------------
;
; A MilliForth for 6502
;
; original for the 6502, by Alvaro G. S. Barcellos, 2023
;
; https://github.com/agsb
; see the disclaimer file in this repo for more information.
;
; SectorForth and MilliForth was made for x86 arch
; and uses full 16-bit registers
;
; The way at 6502 is use page zero and lots of lda/sta
;
; Focus in size not performance.
;
; why ? For understand better my skills, 6502 code and thread codes
;
; how ? Programming a new Forth for old 8-bit cpu emulator
;
; what ? Design the best minimal Forth engine and vocabulary
;
;----------------------------------------------------------------------
; Changes:
;
; all data (36 cells) and return (36 cells) stacks, TIB (80 bytes)
; and PIC (32 bytes) are in same page $200, 256 bytes;
;
; TIB and PIC grows forward, stacks grows backwards;
;
; no overflow or underflow checks;
;
; the header order is LINK, SIZE+FLAG, NAME.
;
; only IMMEDIATE flag used as $80, no hide, no compile;
;
; As ANSI Forth 1994: FALSE is $0000 ; TRUE is $FFFF ;
;
;----------------------------------------------------------------------
; Remarks:
;
; this code uses
; Direct Thread Code, aka DTC or
; Minimal Thread Code, aka MTC.
;
; use a classic cell with 16-bits.
;
; no TOS register, all values keeped at stacks;
;
; TIB (terminal input buffer) is like a stream;
;
; Chuck Moore uses 64 columns, be wise, obey rule 72 CPL;
;
; words must be between spaces, before and after;
;
; no line wrap, do not break words between lines;
;
; only 7-bit ASCII characters, plus \n, no controls;
; ( later maybe \b backspace and \u cancel )
;
; words are case-sensitivy and less than 16 characters;
;
; no need named-'pad' at end of even names;
;
; no multiuser, no multitask, no checks, not faster;
;
;----------------------------------------------------------------------
; For 6502:
;
; a 8-bit processor with 16-bit address space;
;
; the most significant byte is the page count;
;
; page zero and page one hardware reserved;
;
; hardware stack not used for this Forth;
;
; page zero is used as pseudo registers;
;
;----------------------------------------------------------------------
; For stacks:
;
; "when the heap moves forward, move the stack backward"
;
; as hardware stacks do:
; push is 'store and decrease', pull is 'increase and fetch',
;
; but see the notes for Devs.
;
; common memory model organization of Forth:
; [tib->...<-spt: user forth dictionary :here->pad...<-rpt]
; then backward stacks allow to use the slack space ...
;
; this 6502 Forth memory model blocked in pages of 256 bytes:
; [page0][page1][page2][core ... forth dictionary ...here...]
;
; At page2:
;
; |$00 tib> .. $50| <spt..sp0 $98| <rpt..rp0 $E0|pic> ..$FF|
;
; From page 3 onwards:
;
; |$0300 cold:, warm:, forth code, init: here> heap ... tail|
;
; PIC is a transient area of 32 bytes
; PAD could be allocated from here
;
;----------------------------------------------------------------------
; For Devs:
;
; the hello_world.forth file states that stacks works
; to allow : dup sp@ @ ; so sp must point to actual TOS.
;
; The movement will be:
; pull is 'fetch and increase'
; push is 'decrease and store'
;
; Never mess with two underscore variables;
;
; Not using smudge,
; colon saves "here" into "back" and
; semis loads "lastest" from "back";
;
; Do not risk to put stacks with $FF.
;
; Also carefull inspect if any label ends with $FF and move it;
;
; This source is hacked for use with Ca65.
;
;----------------------------------------------------------------------
;
; Stacks represented as (standart)
; S:(w1 w2 w3 -- u1 u2) R:(w1 w2 w3 -- u1 u2)
; before -- after, top at left.
;
;----------------------------------------------------------------------
;
; Stuff for ca65 compiler
;
.p02
.feature c_comments
.feature string_escapes
.feature org_per_seg
.feature dollar_is_pc
.feature pc_assignment
;---------------------------------------------------------------------
; macros for dictionary, makes:
;
; h_name:
; .word link_to_previous_entry
; .byte strlen(name) + flags
; .byte name
; name:
;
; label for primitives
.macro makelabel arg1, arg2
.ident (.concat (arg1, arg2)):
.endmacro
; header for primitives
; the entry point for dictionary is h_~name~
; the entry point for code is ~name~
.macro def_word name, label, flag
makelabel "h_", label
.ident(.sprintf("H%04X", hcount + 1)) = *
.word .ident (.sprintf ("H%04X", hcount))
hcount .set hcount + 1
.byte .strlen(name) + flag + 0 ; nice trick !
.byte name
makelabel "", label
.endmacro
;---------------------------------------------------------------------
; variables for macros
hcount .set 0
H0000 = 0
;---------------------------------------------------------------------
; define thread code model
; MTC is default
; use_DTC = 1
; uncomment to include the extras (sic)
; use_extras = 1
; uncomment to include the extensions (sic)
; use_extensions = 1
; uncomment to use full pages for tib, sp, rp
use_full_pages = 1
;---------------------------------------------------------------------
/*
NOTES:
not finished yet :)
*/
;----------------------------------------------------------------------
;
; alias
;
; cell size, two bytes, 16-bit
CELL = 2
; highlander, immediate flag.
FLAG_IMM = 1<<7
;----------------------------------------------------------------------
.ifdef use_full_pages
;
tib = $0200 ; forwards
sp0 = $03FE ; backwards, 127 cells
rp0 = $04FE ; backwards, 127 cells
;
.else
;----------------------------------------------------------------------
; "all in" page $200
; terminal input buffer, at least 80 bytes, (72 is enough)
; moves forwards
; getline, token, skip, scan, depends on page boundary
tib = $0200
; reserve 80 bytes, (72 is enough)
; moves forwards
tib_end = $50
; data stack, 36 cells,
; moves backwards, push decreases before copy
sp0 = $0299
; return stack, 36 cells,
; moves backwards, push decreases before copy,
rp0 = $02E1
; reserved for scribbles
; moves forwards
pic = rp0
.endif
;----------------------------------------------------------------------
;----------------------------------------------------------------------
; no values here or must be a BSS
.segment "ZERO"
* = $E0
nil: ; empty for fixed reference
; as user variables
; order matters for hello_world.forth !
; internal Forth
stat: .word $0 ; state at lsb, last size+flag at msb
toin: .word $0 ; toin next free byte in TIB
last: .word $0 ; last link cell
here: .word $0 ; next free cell in heap dictionary, aka dpt
; pointers registers
spt: .word $0 ; data stack base,
rpt: .word $0 ; return stack base
ipt: .word $0 ; instruction pointer
wrd: .word $0 ; word pointer
* = $F0
; free for use
fst: .word $0 ; first
snd: .word $0 ; second
trd: .word $0 ; third
fth: .word $0 ; fourth
; used, reserved
tout: .word $0 ; next token in TIB
back: .word $0 ; hold 'here while compile
; for future expansion, reserved
head: .word $0 ; heap forward, also DP
tail: .word $0 ; heap backward
;----------------------------------------------------------------------
;.segment "ONCE"
; no rom code
;----------------------------------------------------------------------
;.segment "VECTORS"
; no boot code
;----------------------------------------------------------------------
.segment "CODE"
;
; leave space for page zero, hard stack,
; and buffer, locals, forth stacks
;
.ifdef use_full_pages
* = $500
.else
* = $300
.endif
;----------------------------------------------------------------------
main:
;----------------------------------------------------------------------
; common must
;
cold:
; disable interrupts
sei
; clear BCD
cld
; set real stack
ldx #$FF
txs
; enable interrupts
cli
;----------------------------------------------------------------------
warm:
; link list of headers
lda #>h_exit
sta last + 1
lda #<h_exit
sta last + 0
; next heap free cell, same as init:
lda #>ends + 1
sta here + 1
lda #0
sta here + 0
;---------------------------------------------------------------------
; supose never change
reset:
ldy #>tib
sty toin + 1
sty tout + 1
.ifdef use_full_pages
ldy #>sp0
.endif
sty spt + 1
.ifdef use_full_pages
ldy #>rp0
.endif
sty rpt + 1
abort:
ldy #<sp0
sty spt + 0
quit:
ldy #<rp0
sty rpt + 0
; reset tib
ldy #0 ; already
; clear tib stuff
sty tib + 0
; clear cursor
sty toin + 0
; stat is 'interpret' == \0
sty stat + 0
.byte $2c ; mask next two bytes, nice trick !
;---------------------------------------------------------------------
; the outer loop
resolvept:
.word okey
;---------------------------------------------------------------------
okey:
;; uncomment for feedback
; lda stat + 0
; bne resolve
; lda #'O'
; jsr putchar
; lda #'K'
; jsr putchar
; lda #10
; jsr putchar
resolve:
; get a token
jsr token
; lda #'P'
; jsr putchar
find:
; load last
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
@loop:
; lsb linked list
lda snd + 0
sta wrd + 0
; verify \0x0
ora snd + 1
beq abort
; maybe to place a code for number?
; but not for now.
;; uncomment for feedback, comment out "beq abort" above
; lda #'?'
; jsr putchar
; lda #'?'
; jsr putchar
; lda #10
; jsr putchar
; jmp abort ; end of dictionary, no more words to search, abort
@each:
; msb linked list
lda snd + 1
sta wrd + 1
; update next link
ldx #(wrd) ; from
ldy #(snd) ; into
jsr copyfrom
; compare words
ldy #0
; save the flag, first byte is (size and flag)
lda (wrd), y
sta stat + 1
; compare chars
@equal:
lda (tout), y
; space ends
cmp #32
beq @done
; verify
sec
sbc (wrd), y
; clean 7-bit ascii
asl
bne @loop
; next char
iny
bne @equal
@done:
; update wrd
tya
;; ldx #(wrd) ; set already
;; addwx also clear carry
jsr addwx
eval:
; executing ? if == \0
lda stat + 0
beq execute
; immediate ? if < \0
lda stat + 1
bmi immediate
compile:
; lda #'C'
; jsr putchar
jsr wcomma
bcc resolve
immediate:
execute:
; lda #'E'
; jsr putchar
lda #>resolvept
sta ipt + 1
lda #<resolvept
sta ipt + 0
;~~~~~~~~
.ifdef use_DTC
jmp (wrd)
.else
jmp pick
.endif
;~~~~~~~~
;---------------------------------------------------------------------
try:
lda tib, y
beq getline ; if \0
iny
eor #' '
rts
;---------------------------------------------------------------------
getline:
; drop rts of try
pla
pla
; leave the first
ldy #0
@loop:
; is valid
sta tib, y ; dummy store on first pass, overwritten
iny
; would be better with
; end of buffer ?
; cpy #tib_end
; beq @ends
; then
jsr getchar
; would be better with
; 7-bit ascii only
; and #$7F
; unix \n
cmp #10
bne @loop
; would be better with
; no controls
; cmp #' '
; bmi @loop
; clear all if y eq \0
@ends:
; grace \b
lda #32
sta tib + 0 ; start with space
sta tib, y ; ends with space
; mark eol with \0
lda #0
sta tib + 1, y
; start it
sta toin + 0
;---------------------------------------------------------------------
; in place every token,
; the counter is placed at last space before word
; no rewinds
token:
; last position on tib
ldy toin + 0
@skip:
; skip spaces
jsr try
beq @skip
; keep y == start + 1
dey
sty tout + 0
@scan:
; scan spaces
jsr try
bne @scan
; keep y == stop + 1
dey
sty toin + 0
@done:
; sizeof
tya
sec
sbc tout + 0
; keep it
ldy tout + 0
dey
sta tib, y ; store size for counted string
sty tout + 0
; setup token
clc ; clean
rts
;---------------------------------------------------------------------
; this code depends on systems or emulators
;
; lib6502 emulator
;
getchar:
lda $E000
eofs:
; EOF ?
cmp #$FF ; also clean carry :)
beq byes
putchar:
sta $E000
rts
; exit for emulator
byes:
jmp $0000
;
; lib6502 emulator
;---------------------------------------------------------------------
;---------------------------------------------------------------------
; decrement a word in page zero. offset by X
decwx:
lda 0, x
bne @ends
dec 1, x
@ends:
dec 0, x
rts
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
;incwx:
; inc 0, x
; bne @ends
; inc 1, x
;@ends:
; rts
;---------------------------------------------------------------------
; classic heap moves always forward
;
stawrd:
sta wrd + 1
wcomma:
ldy #(wrd)
comma:
ldx #(here)
; fall throught
;---------------------------------------------------------------------
; from a page zero address indexed by Y
; into a page zero indirect address indexed by X
copyinto:
lda 0, y
sta (0, x)
jsr incwx
lda 1, y
sta (0, x)
jmp incwx
;---------------------------------------------------------------------
;
; generics
;
;---------------------------------------------------------------------
spush1:
ldy #(fst)
;---------------------------------------------------------------------
; push a cell
; from a page zero address indexed by Y
; into a page zero indirect address indexed by X
spush:
ldx #(spt)
; jmp push
.byte $2c ; mask next two bytes, nice trick !
rpush:
ldx #(rpt)
;---------------------------------------------------------------------
; classic stack backwards
push:
jsr decwx
lda 1, y
sta (0, x)
jsr decwx
lda 0, y
sta (0, x)
rts
;---------------------------------------------------------------------
spull2:
ldy #(snd)
jsr spull
; fall through
;---------------------------------------------------------------------
spull1:
ldy #(fst)
; fall through
;---------------------------------------------------------------------
; pull a cell
; from a page zero indirect address indexed by X
; into a page zero address indexed by y
spull:
ldx #(spt)
; jmp pull
.byte $2c ; mask next two bytes, nice trick !
rpull:
ldx #(rpt)
;---------------------------------------------------------------------
; classic stack backwards
pull: ; fall through, same as copyfrom
;---------------------------------------------------------------------
; from a page zero indirect address indexed by X
; into a page zero address indexed by y
copyfrom:
lda (0, x)
sta 0, y
jsr incwx
lda (0, x)
sta 1, y
; jmp incwx ; fall through
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
incwx:
lda #01
;---------------------------------------------------------------------
; add a byte to a word in page zero. offset by X
addwx:
clc
adc 0, x
sta 0, x
bcc @ends
inc 1, x
clc ; keep carry clean
@ends:
rts
;---------------------------------------------------------------------
;
; the primitives,
; for stacks uses
; a address, c byte ascii, w signed word, u unsigned word
; cs counted string < 256, sz string with nul ends
;
;----------------------------------------------------------------------
.ifdef use_extras
;----------------------------------------------------------------------
; extras
;----------------------------------------------------------------------
; ( -- ) ae exit forth
def_word "bye", "bye", 0
jmp byes
;----------------------------------------------------------------------
; ( -- ) ae abort
def_word "abort", "abort_", 0
jmp abort
;----------------------------------------------------------------------
; ( -- ) ae list of data stack
def_word ".S", "splist", 0
lda spt + 0
sta fst + 0
lda spt + 1
sta fst + 1
lda #'S'
jsr putchar
lda #sp0
jsr list
jmp next
;----------------------------------------------------------------------
; ( -- ) ae list of return stack
def_word ".R", "rplist", 0
lda rpt + 0
sta fst + 0
lda rpt + 1
sta fst + 1
lda #'R'
jsr putchar
lda #rp0
jsr list
jmp next
;----------------------------------------------------------------------
; ae list a sequence of references
list:
sec
sbc fst + 0
lsr
tax
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #' '
jsr putchar
txa
jsr puthex
lda #' '
jsr putchar
txa
beq @ends
ldy #0
@loop:
lda #' '
jsr putchar
iny
lda (fst),y
jsr puthex
dey
lda (fst),y
jsr puthex
iny
iny
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ( -- ) dumps the user dictionary
def_word "dump", "dump", 0
lda #$0
sta fst + 0
lda #>ends + 1
sta fst + 1
ldx #(fst)
ldy #0
@loop:
lda (fst),y
jsr putchar
jsr incwx
lda fst + 0
cmp here + 0
bne @loop
lda fst + 1
cmp here + 1
bne @loop
clc ; clean
jmp next
;----------------------------------------------------------------------
; ( -- ) words in dictionary,
def_word "words", "words", 0
; load lastest
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
; load here
lda here + 1
sta trd + 1
lda here + 0
sta trd + 0
@loop:
; lsb linked list
lda snd + 0
sta fst + 0
; verify \0x0
ora snd + 1
beq @ends
; msb linked list
lda snd + 1
sta fst + 1
@each:
lda #10
jsr putchar
; put address
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; put link
lda #' '
jsr putchar
ldy #1
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
ldx #(fst)
lda #2
jsr addwx
; put size + flag, name
ldy #0
jsr show_name
; update
iny
tya
ldx #(fst)
jsr addwx
; show CFA
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; check if is a primitive
lda fst + 1
cmp #>ends + 1
bmi @continue
; list references
ldy #0
jsr show_refer
@continue:
lda snd + 0
sta trd + 0
lda snd + 1
sta trd + 1
ldy #0
lda (trd), y
sta snd + 0
iny
lda (trd), y
sta snd + 1
ldx #(trd)
lda #2
jsr addwx
jmp @loop
@ends:
clc ; clean
jmp next
;----------------------------------------------------------------------
; ae put size and name
show_name:
lda #' '
jsr putchar
lda (fst), y
jsr puthex
lda #' '
jsr putchar
lda (fst), y
and #$7F
tax
@loop:
iny
lda (fst), y
jsr putchar
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
show_refer:
; ae put references PFA ...
ldx #(fst)
@loop:
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #':'
jsr putchar
iny
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
lda #2
jsr addwx
; check if ends
lda fst + 0
cmp trd + 0
bne @loop
lda fst + 1
cmp trd + 1
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ae seek for 'exit to ends a sequence of references
; max of 254 references in list
;
seek:
ldy #0
@loop1:
iny
beq @ends
lda (fst), y
cmp #>exit
bne @loop1
dey
lda (fst), y
cmp #<exit
beq @ends
iny
bne @loop1
@ends:
tya
lsr
clc ; clean
rts
;----------------------------------------------------------------------
; ( u -- u ) print tos in hexadecimal, swaps order
def_word ".", "dot", 0
lda #' '
jsr putchar
jsr spull1
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
jsr spush1
jmp next
;----------------------------------------------------------------------
; code a byte in ASCII hexadecimal
puthex:
pha
lsr
ror
ror
ror
jsr @conv
pla
@conv:
and #$0F
ora #$30
cmp #$3A
bcc @ends
adc #$06
@ends:
clc ; clean
jmp putchar
.endif
.ifdef numbers
;----------------------------------------------------------------------
; code a ASCII $FFFF hexadecimal in a byte
;
number:
ldy #0
jsr @very
asl
asl
asl
asl
sta fst + 1
iny
jsr @very
ora fst + 1
sta fst + 1
iny
jsr @very
asl
asl
asl
asl
sta fst + 0
iny
jsr @very
ora fst + 0
sta fst + 0
clc ; clean
rts
@very:
lda (tout), y
sec
sbc #$30
bmi @erro
cmp #10
bcc @ends
sbc #$07
; any valid digit, A-Z, do not care
@ends:
rts
@erro:
pla
pla
rts
.endif
;---------------------------------------------------------------------
;
; extensions
;
;---------------------------------------------------------------------
.ifdef use_extensions
;---------------------------------------------------------------------
; ( w -- w/2 ) ; shift right
def_word "2/", "shr", 0
jsr spull1
lsr fst + 1
ror fst + 0
jmp this
;---------------------------------------------------------------------
; ( a -- ) execute a jump to a reference at top of data stack
def_word "exec", "exec", 0
jsr spull1
jmp (fst)
;---------------------------------------------------------------------
; ( -- ) execute a jump to a reference at IP
def_word ":$", "docode", 0
jmp (ipt)
;---------------------------------------------------------------------
; ( -- ) execute a jump to next
def_word ";$", "donext", 0
jmp next
.endif
;---------------------------------------------------------------------
; core primitives minimal
; start of dictionary
;---------------------------------------------------------------------
; ( -- u ) ; tos + 1 unchanged
def_word "key", "key", 0
jsr getchar
sta fst + 0
; jmp this ; uncomment if char could be \0
bne this ; always taken
;---------------------------------------------------------------------
; ( u -- ) ; tos + 1 unchanged
def_word "emit", "emit", 0
jsr spull1
lda fst + 0
jsr putchar
; jmp next ; uncomment if carry could be set
bcc jmpnext ; always taken
;---------------------------------------------------------------------
; ( a w -- ) ; [a] = w
def_word "!", "store", 0
storew:
jsr spull2
ldx #(snd)
ldy #(fst)
jsr copyinto
; jmp next ; uncomment if carry could be set
bcc jmpnext ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- NOT(w1 AND w2) )
def_word "nand", "nand", 0
jsr spull2
lda snd + 0
and fst + 0
eor #$FF
sta fst + 0
lda snd + 1
and fst + 1
eor #$FF
; jmp keeps ; uncomment if carry could be set
bcc keeps ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- w1+w2 )
def_word "+", "plus", 0
jsr spull2
clc ; better safe than sorry
lda snd + 0
adc fst + 0
sta fst + 0
lda snd + 1
adc fst + 1
jmp keeps
;---------------------------------------------------------------------
; ( a -- w ) ; w = [a]
def_word "@", "fetch", 0
fetchw:
jsr spull1
ldx #(fst)
ldy #(snd)
jsr copyfrom
; fall throught
;---------------------------------------------------------------------
copys:
lda 0, y
sta fst + 0
lda 1, y
keeps:
sta fst + 1
this:
jsr spush1
jmpnext:
jmp next
;---------------------------------------------------------------------
; ( 0 -- $0000) | ( n -- $FFFF) not zero at top ?
def_word "0#", "zeroq", 0
jsr spull1
lda fst + 1
ora fst + 0
beq isfalse ; is \0 ?
istrue:
lda #$FF
isfalse:
sta fst + 0
jmp keeps
;---------------------------------------------------------------------
; ( -- state ) a variable return an reference
def_word "s@", "state", 0
lda #<stat
sta fst + 0
lda #>stat
; jmp keeps ; uncomment if stats not in page $0
beq keeps ; always taken
;---------------------------------------------------------------------
def_word ";", "semis", FLAG_IMM
; update last, panic if colon not lead elsewhere
lda back + 0
sta last + 0
lda back + 1
sta last + 1
; stat is 'interpret'
lda #0
sta stat + 0
; compound words must ends with exit
finish:
lda #<exit
sta wrd + 0
lda #>exit
sta wrd + 1
jsr wcomma
; jmp next
bcc next ; always taken
;---------------------------------------------------------------------
def_word ":", "colon", 0
; save here, panic if semis not follow elsewhere
lda here + 0
sta back + 0
lda here + 1
sta back + 1
; stat is 'compile'
lda #1
sta stat + 0
@header:
; copy last into (here)
ldy #(last)
jsr comma
; get following token
jsr token
; copy it
ldy #0
@loop:
lda (tout), y
cmp #32 ; stops at space
beq @ends
sta (here), y
iny
bne @loop
@ends:
; update here
tya
ldx #(here)
jsr addwx
;~~~~~~~~
.ifdef use_DTC
; magic NOP (EA) JSR (20), at CFA cell
; magic = $EA20
magic = $20EA
; inserts the nop call
lda #<magic
sta wrd + 0
lda #>magic
jsr stawrd
; inserts the reference
lda #<nest
sta wrd + 0
lda #>nest
jsr stawrd
.endif
;~~~~~~~~
; done
; jmp next
bcc next ; always taken
;---------------------------------------------------------------------
; Thread Code Engine
;
; ipt is IP, wrd is W
;
; for reference:
;
; nest aka enter or docol,
; unnest aka exit or semis;
;
;---------------------------------------------------------------------
; ( -- )
def_word "exit", "exit", 0
unnest: ; exit
; pull, ipt = (rpt), rpt += 2
ldy #(ipt)
jsr rpull
next:
; wrd = (ipt) ; ipt += 2
ldx #(ipt)
ldy #(wrd)
jsr copyfrom
;~~~~~~~~
.ifdef use_DTC
pick:
jmp (wrd)
nest: ; enter
; push, *rp = ipt, rp -=2
ldy #(ipt)
jsr rpush
; pull (ip),
pla
sta ipt + 0
pla
sta ipt + 1
; 6502 trick: must increase return address
ldx #(ipt)
jsr incwx
bcc next
.else
pick:
; compare pages (MSBs)
lda wrd + 1
cmp #>ends + 1
; cmp #>init
bmi jump
nest: ; enter
; push, *rp = ipt, rp -=2
ldy #(ipt)
jsr rpush
lda wrd + 0
sta ipt + 0
lda wrd + 1
sta ipt + 1
jmp next
jump:
jmp (wrd)
.endif
;~~~~~~~~
;----------------------------------------------------------------------
; end of code
ends:
;----------------------------------------------------------------------
; anything above is not a primitive
; needed for MTC
; same as #>end+1
;.align $100
;init:
;----------------------------------------------------------------------
|
agsb/milliForth-6502
| 6,385
|
tsts/alts.s
|
;----------------------------------------------------------------------
;
; original for the 6502, by Alvaro G. S. Barcellos, 2023
;
; https://github.com/agsb
; see the disclaimer file in this repo for more information.
;
; The way at 6502 is use page zero and lots of lda/sta
;
; why ? For understand better my skills, 6502 code and thread codes
;
; how ? Programming a new Forth for old 8-bit cpu emulator
;
; what ? Design the best minimal Forth engine and vocabulary
;
;----------------------------------------------------------------------
;
; Stacks represented as (standart)
; S:(w1 w2 w3 -- u1 u2) R:(w1 w2 w3 -- u1 u2)
; before -- after, top at left.
;
;----------------------------------------------------------------------
;
; Stuff for ca65 compiler
;
.p02
.feature c_comments
.feature string_escapes
.feature org_per_seg
.feature dollar_is_pc
.feature pc_assignment
;---------------------------------------------------------------------
; macros for dictionary, makes:
;
; h_name:
; .word link_to_previous_entry
; .byte strlen(name) + flags
; .byte name
; name:
;
; label for primitives
.macro makelabel arg1, arg2
.ident (.concat (arg1, arg2)):
.endmacro
; header for primitives
; the entry point for dictionary is h_~name~
; the entry point for code is ~name~
.macro def_word name, label, flag
makelabel "h_", label
.ident(.sprintf("H%04X", hcount + 1)) = *
.word .ident (.sprintf ("H%04X", hcount))
hcount .set hcount + 1
.byte .strlen(name) + flag + 0 ; nice trick !
.byte name
makelabel "", label
.endmacro
;---------------------------------------------------------------------
; variables for macros
hcount .set 0
H0000 = 0
;---------------------------------------------------------------------
/*
NOTES:
not finished yet :)
*/
;----------------------------------------------------------------------
;
; alias
; cell size, two bytes, 16-bit
CELL = 2
;----------------------------------------------------------------------
; no values here or must be a BSS
.segment "ZERO"
* = $E0
; pointers registers
spt: .word $0 ; data stack base,
rpt: .word $0 ; return stack base
ipt: .word $0 ; instruction pointer
wrd: .word $0 ; word pointer
ptr: .word $0
tos: .word $0
nos: .word $0
tmp: .word $0
* = $F0
w: .word $0
tp: .word $0
sp0: .word $0
sp1: .word $0
;----------------------------------------------------------------------
;.segment "ONCE"
; no rom code
;----------------------------------------------------------------------
;.segment "VECTORS"
; no boot code
;----------------------------------------------------------------------
.segment "CODE"
;
; leave space for page zero, hard stack,
; and buffer, locals, forth stacks
;
* = $300
;spz = $40
;rpz = $80
; data stack, 36 cells,
; moves backwards, push decreases before copy
;.word spz
; return stack, 36 cells,
; moves backwards, push decreases before copy
;.word rpz
;---------------------------------------------------------------------
main:
;
; compare stack models in 6502
;
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
incwx:
inc 0, x
bne @ends
inc 1, x
@ends:
rts
;---------------------------------------------------------------------
; decrement a word in page zero. offset by X
decwx:
lda 0, x
bne @ends
dec 1, x
@ends:
dec 0, x
rts
;---------------------------------------------------------------------
; add a 8bit to a 16bit
addbx:
clc
adc 0, x
sta 0, x
lda 1, x
adc #$00
sta 1, x
clc ; keep carry clean
@ends:
rts
;---------------------------------------------------------------------
; sub a 8bit to a 16bit
subbx:
clc
adc 0, x
sta 0, x
lda 1, x
sbc #$00
sta 1, x
clc ; keep carry clean
@ends:
rts
;---------------------------------------------------------------------
; add a 16bit to a 16bit
; ( w1 w2 -- w1 w1+w2 )
addwx:
clc
lda 0, x
adc 2, x
sta 2, x
lda 1, x
adc 3, x
sta 3, x
clc ; keep carry clean
rts
;---------------------------------------------------------------------
; sub a 16bit to a 16bit
; 0,1 tos 2,3 nos
; ( w1 w2 -- w1 w1-w2 )
subwx:
sec
lda 0, x
sbc 2, x
sta 2, x
lda 1, x
sbc 3, x
sta 3, x
clc ; keep carry clean
rts
;---------------------------------------------------------------------
.macro copy into, from
lda from + 0
sta into + 0
lda from + 1
sta into + 1
.endmacro
;---------------------------------------------------------------------
; using stack at any page
; minimal use of page zero and page one
; x byte, word in page zero
; y byte, index of stack
; z word, pointer to top of stack, grows downsize
;---------------------------------------------------------------------
; Eg:
;
; ldx from
; ldy index
; copy z, stack
;
; jsr jolt
;
; ldx z
; jsr decwx
; jsr decwx
;
; copy stack, z
;
;---------------------------------------------------------------------
; R = --(M)
;
jolt:
dey
lda (tp), y
sta 1, x
dey
lda (tp), y
sta 0, x
rts
;---------------------------------------------------------------------
; (M)++ = R
;
yank:
lda 0, x
sta (tp), y
iny
lda 1, x
sta (tp), y
iny
rts
;---------------------------------------------------------------------
; R = (M)++
;
pull:
lda (tp), y
iny
sta 0, x
lda (tp), y
iny
sta 1, x
rts
;---------------------------------------------------------------------
; --(M) = R
;
push:
lda 1, x
dey
sta (tp), y
lda 0, x
dey
sta (tp), y
rts
;---------------------------------------------------------------------
; using hardware stack
;
;
pushs:
lda #40 ; word to use
ldy #80 ; stack to use
clc ; to push
;sec ; to pull
jsr stack
;
pulls:
lda #40 ; word to use
ldy #80 ; stack to use
; clc ; to push
sec ; to pull
jsr stack
;
stack:
tsx
stx sp0
ldx 0, y
txs
tax
bcc @push
@pull:
pla
sta 1, x
pla
sta 0, x
bcs @ends
@push:
lda 0, x
pha
lda 1, x
pha
tsx
@ends:
tsx
stx 0, y
ldx sp0
txs
rts
;---------------------------------------------------------------------
ends:
|
agsb/milliForth-6502
| 21,825
|
tsts/sector-6502-hard.s
|
;----------------------------------------------------------------------
;
; A MilliForth for 6502
;
; original for the 6502, by Alvaro G. S. Barcellos, 2023
;
; https://github.com/agsb
; see the disclaimer file in this repo for more information.
;
; SectorForth and MilliForth was made for x86 arch
; and uses full 16-bit registers
;
; The way at 6502 is use page zero and lots of lda/sta
;
; Focus in size not performance.
;
; why ? For understand better my skills, 6502 code and thread codes
;
; how ? Programming a new Forth for old 8-bit cpu emulator
;
; what ? Design the best minimal Forth engine and vocabulary
;
;----------------------------------------------------------------------
; Changes:
;
; Version for 65C02, using page zero and page one for stacks
;
; IT WILL NOT WORK BECAUSE EXTRA WORDS DEPENDS ON
; SP@ RP@ AS CELL POINTERS, JUST FOR CHECK SIZE
;
; TIB (80 bytes) and PIC (32 bytes) are in same page $200, 256 bytes;
;
; TIB and PIC grows forward, stacks grows backwards;
;
; no overflow or underflow checks;
;
; the header order is LINK, SIZE+FLAG, NAME.
;
; only IMMEDIATE flag used as $80, no hide, no compile;
;
; As ANSI Forth 1994: FALSE is $0000 ; TRUE is $FFFF ;
;
;----------------------------------------------------------------------
; Remarks:
;
; this code uses Minimal Thread Code, aka MTC.
;
; use a classic cell with 16-bits.
;
; no TOS register, all values keeped at stacks;
;
; TIB (terminal input buffer) is like a stream;
;
; Chuck Moore uses 64 columns, be wise, obey rule 72 CPL;
;
; words must be between spaces, before and after;
;
; no line wrap, do not break words between lines;
;
; only 7-bit ASCII characters, plus \n, no controls;
; ( later maybe \b backspace and \u cancel )
;
; words are case-sensitivy and less than 16 characters;
;
; no need named-'pad' at end of even names;
;
; no multiuser, no multitask, no checks, not faster;
;
;----------------------------------------------------------------------
; For 6502:
;
; a 8-bit processor with 16-bit address space;
;
; the most significant byte is the page count;
;
; page zero and page one hardware reserved;
;
; hardware stack not used for this Forth;
;
; page zero is used as pseudo registers;
;
;----------------------------------------------------------------------
; For stacks:
;
; "when the heap moves forward, move the stack backward"
;
; as hardware stacks do:
; push is 'store and decrease', pull is 'increase and fetch',
;
; but see the notes for Devs.
;
; common memory model organization of Forth:
; [tib->...<-spt: user forth dictionary :here->pad...<-rpt]
; then backward stacks allow to use the slack space ...
;
; this 6502 Forth memory model blocked in pages of 256 bytes:
; [page0][page1][page2][core ... forth dictionary ...here...]
;
; At page2:
;
; |$00 tib> .. $50| <spt..sp0 $98| <rpt..rp0 $E0|pic> ..$FF|
;
; From page 3 onwards:
;
; |$0300 cold:, warm:, forth code, init: here> heap ... tail|
;
; PIC is a transient area of 32 bytes
; PAD could be allocated from here
;
;----------------------------------------------------------------------
; For Devs:
;
; the hello_world.forth file states that stacks works
; to allow : dup sp@ @ ; so sp must point to actual TOS.
;
; The movement will be:
; pull is 'fetch and increase'
; push is 'decrease and store'
;
; Never mess with two underscore variables;
;
; Not using smudge,
; colon saves "here" into "back" and
; semis loads "lastest" from "back";
;
; Do not risk to put stacks with $FF.
;
; Also carefull inspect if any label ends with $FF and move it;
;
; This source is hacked for use with Ca65.
;
;----------------------------------------------------------------------
;
; Stacks represented as (standart)
; S:(w1 w2 w3 -- u1 u2) R:(w1 w2 w3 -- u1 u2)
; before -- after, top at left.
;
;----------------------------------------------------------------------
;
; Stuff for ca65 compiler
;
.pC02
.feature c_comments
.feature string_escapes
.feature org_per_seg
.feature dollar_is_pc
.feature pc_assignment
;---------------------------------------------------------------------
; macros for dictionary, makes:
;
; h_name:
; .word link_to_previous_entry
; .byte strlen(name) + flags
; .byte name
; name:
;
; label for primitives
.macro makelabel arg1, arg2
.ident (.concat (arg1, arg2)):
.endmacro
; header for primitives
; the entry point for dictionary is h_~name~
; the entry point for code is ~name~
.macro def_word name, label, flag
makelabel "h_", label
.ident(.sprintf("H%04X", hcount + 1)) = *
.word .ident (.sprintf ("H%04X", hcount))
hcount .set hcount + 1
.byte .strlen(name) + flag + 0 ; nice trick !
.byte name
makelabel "", label
.endmacro
;---------------------------------------------------------------------
; variables for macros
hcount .set 0
H0000 = 0
;---------------------------------------------------------------------
; define thread code model
; MTC is default
; use_DTC = 1
; uncomment to include the extras (sic)
; use_extras = 1
; uncomment to include the extensions (sic)
; use_extensions = 1
;---------------------------------------------------------------------
/*
NOTES:
not finished yet :)
*/
;----------------------------------------------------------------------
;
; alias
; cell size, two bytes, 16-bit
CELL = 2
; highlander, immediate flag.
FLAG_IMM = 1<<7
; "all in" page $200
; terminal input buffer, forward
; getline, token, skip, scan, depends on page boundary
tib = $0200
; reserve 80 bytes, (72 is enough)
; moves forwards
tib_end = $50
; data stack, 36 cells,
; moves backwards, push decreases before copy
sp0 = $00FF
; return stack, 36 cells,
; moves backwards, push decreases before copy
rp0 = $01FF
;----------------------------------------------------------------------
; no values here or must be a BSS
.segment "ZERO"
* = $E0
; as user variables
; order matters for hello_world.forth !
; forth variables
up: .word $0 ; user area
ip: .word $0 ; instruction pointer
wrd: .word $0 ; word pointer
; free for use
nil: ; empty for fixed reference
fst: .word $0 ; first
snd: .word $0 ; second
trd: .word $0 ; third
fth: .word $0 ; fourth
; internal Forth
stat: .word $0 ; state at lsb, last size+flag at msb
toin: .word $0 ; toin next free byte in TIB
last: .word $0 ; last link cell
here: .word $0 ; next free cell in heap dictionary, aka dpt
;----------------------------------------------------------------------
;.segment "ONCE"
; no rom code
;----------------------------------------------------------------------
;.segment "VECTORS"
; no boot code
;----------------------------------------------------------------------
.segment "CODE"
;
; leave space for page zero, hard stack,
; and buffer, locals, forth stacks
;
* = $300
main:
;----------------------------------------------------------------------
; common must
;
cold:
; disable interrupts
sei
; clear BCD
cld
; set real stack
ldx #$FF
txs
; enable interrupts
cli
;----------------------------------------------------------------------
warm:
; link list of headers
lda #>h_exit
sta last + 1
lda #<h_exit
sta last + 0
; next heap free cell, same as init:
lda #>ends + 1
sta here + 1
lda #0
sta here + 0
;---------------------------------------------------------------------
; supose never change
reset:
ldy #>tibz
sty toin + 1
sty tout + 1
abort:
ldx #$FF
quit:
stx wrd + 0
lda #$FF
tax
txs
ldx wrd + 0
; reset tib
ldy #0
; clear tib stuff
sty tib + 0
; clear cursor
sty toin + 0
; stat is 'interpret' == \0
sty stat + 0
.byte $2c ; mask next two bytes, nice trick !
;---------------------------------------------------------------------
; the outer loop
resolvept:
.word okey
;---------------------------------------------------------------------
okey:
;; uncomment for feedback
; lda stat + 0
; bne resolve
; lda #'O'
; jsr putchar
; lda #'K'
; jsr putchar
; lda #10
; jsr putchar
resolve:
; get a token
jsr token
find:
; load last
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
@loop:
; lsb linked list
lda snd + 0
sta wrd + 0
; verify \0x0
ora snd + 1
beq abort
; maybe to place a code for number?
; but not for now.
;; uncomment for feedback, comment out "beq abort" above
; lda #'?'
; jsr putchar
; lda #'?'
; jsr putchar
; lda #10
; jsr putchar
; jmp abort ; end of dictionary, no more words to search, abort
@each:
; msb linked list
lda snd + 1
sta wrd + 1
; update next link
lda (wrd, x)
sta snd + 0
inc wrd + 0
bcc @bccs
inc wrd + 1
@bccs:
lda (wrd, x)
sta snd + 1
; compare words
ldy #0
; save the flag, first byte is (size and flag)
lda (wrd), y
sta stat + 1
; compare sizes
asl
lsr
cmp (tout), y
bne @loop
iny
; compare chars
@equal:
lda (tout), y
; space ends
cmp #33
bmi @done
; verify
cmp (wrd), y
; clean 7-bit ascii
bne @loop
; next char
iny
bne @equal
@done:
; update wrd
tya
;; ldx #(wrd) ; set already
;; addwx also clear carry
jsr addwx
eval:
; executing ? if == \0
lda stat + 0
beq execute
; immediate ? if < \0
lda stat + 1
bmi immediate
compile:
; lda #'C'
; jsr putchar
jsr wcomma
bcc resolve
immediate:
execute:
; lda #'E'
; jsr putchar
lda #>resolvept
sta ipt + 1
lda #<resolvept
sta ipt + 0
jmp pick
;---------------------------------------------------------------------
try:
lda tib, y
beq getline ; if \0
iny
eor #' '
rts
;---------------------------------------------------------------------
getline:
; drop rts of try
pla
pla
; leave the first
ldy #0
@loop:
; is valid
sta tib, y ; dummy store on first pass, overwritten
iny
; would be better with
; end of buffer ?
; cpy #tib_end
; beq @ends
; then
jsr getchar
; would be better with
; 7-bit ascii only
; and #$7F
; any control exits
cmp #32
bpl @loop
; would be better with
; no controls
; cmp #' '
; bmi @loop
; clear all if y eq \0
@ends:
; grace \b
lda #32
sta tib + 0 ; start with space
sta tib, y ; ends with space
; mark eol with \0
lda #0
sta tib + 1, y
; start it
sta toin + 0
;---------------------------------------------------------------------
; in place every token,
; the counter is placed at last space before word
; no rewinds
token:
; last position on tib
ldy toin + 0
@skip:
; skip spaces
jsr try
beq @skip
; keep y == start + 1
dey
sty tout + 0
@scan:
; scan spaces
jsr try
bne @scan
; keep y == stop + 1
dey
sty toin + 0
@done:
; sizeof
tya
sec
sbc tout + 0
; keep it
ldy tout + 0
dey
sta tib, y ; store size for counted string
sty tout + 0
; setup token
rts
;---------------------------------------------------------------------
; this code depends on systems or emulators
;
; lib6502 emulator
;
getchar:
lda $E000
eofs:
; EOF ?
cmp #$FF ; also clean carry :)
beq byes
putchar:
sta $E000
rts
; exit for emulator
byes:
jmp $0000
;
; lib6502 emulator
;---------------------------------------------------------------------
;---------------------------------------------------------------------
;
; generics
;
;---------------------------------------------------------------------
;---------------------------------------------------------------------
;
; the primitives,
; for stacks uses
; a address, c byte ascii, w signed word, u unsigned word
; cs counted string < 256, sz string with nul ends
;
;----------------------------------------------------------------------
;---------------------------------------------------------------------
; core primitives minimal
; start of dictionary
;---------------------------------------------------------------------
; ( -- u ) ; tos + 1 unchanged
def_word "key", "key", 0
jsr getchar
sta 0, x
jmp next
;---------------------------------------------------------------------
; ( u -- ) ; tos + 1 unchanged
def_word "emit", "emit", 0
lda 0, x
jsr putchar
jmp next
;---------------------------------------------------------------------
; ( w1 w2 -- NOT(w1 AND w2) )
def_word "nand", "nand", 0
lda 0, x
and 2, x
eor #$FF
sta 2, x
lda 1, x
and 3, x
eor #$FF
jmp pushed
;---------------------------------------------------------------------
; ( w1 w2 -- w1+w2 )
def_word "+", "plus", 0
clc ; better safe than sorry
lda 0, x
adc 2, x
sta 2, x
lda 1, x
adc 3, x
pushed:
sta 3, x
inx
inx
jmp next
;---------------------------------------------------------------------
; ( a w -- ) ; [a] = w
def_word "!", "store", 0
lda 2, x
sta (0, x)
inc 0, x
bne @bne
inc 1, x
@bne:
lda 3, x
sta (0, x)
inx
inx
jmp pushed
;---------------------------------------------------------------------
; ( a -- w ) ; w = [a]
def_word "@", "fetch", 0
lda (0,x)
pha
inc 0, x
bne @bne
inc 1, x
@bne:
lda (0,x)
sta 1, x
pla
sta 0, x
jmp next
;---------------------------------------------------------------------
; ( 0 -- $0000) | ( n -- $FFFF) not zero at top ?
def_word "0#", "zeroq", 0
lda 0, x
ora 1, x
beq isfalse
istrue:
lda #$FF
isfalse:
sta 0, x
sta 1, x
jmp next
;---------------------------------------------------------------------
; ( -- state ) a variable return an reference
def_word "s@", "state", 0
inx
inx
lda #<stat
sta 0, x
lda #>stat
sta 1, x
jmp next
;---------------------------------------------------------------------
def_word ";", "semis", FLAG_IMM
; update last, panic if colon not lead elsewhere
lda back + 0
sta last + 0
lda back + 1
sta last + 1
; stat is 'interpret'
lda #0
sta stat + 0
; compound words must ends with exit
finish:
lda #<exit
sta wrd + 0
lda #>exit
sta wrd + 1
jsr wcomma
; jmp next
bcc next ; always taken
;---------------------------------------------------------------------
def_word ":", "colon", 0
; save here, panic if semis not follow elsewhere
lda here + 0
sta back + 0
lda here + 1
sta back + 1
; stat is 'compile'
lda #1
sta stat + 0
@header:
; copy last into (here)
ldy #1
lda last + 1
sta (here), y
dey
lda last + 0
sta (here), y
; get following token
jsr token
; copy it
ldy #0
@loop:
lda (tout), y
cmp #33 ; stops at controls
bmi @ends
sta (here), y
iny
bne @loop
@ends:
; update here
tya
clc
adc here + 0
sta here + 0
bcc @bccs
inc here + 1
@bccs:
; done
; jmp next
clc
bcc next ; always taken
;---------------------------------------------------------------------
; Thread Code Engine
;
; ipt is IP, wrd is W
;
; for reference:
;
; nest aka enter or docol,
; unnest aka exit or semis;
;
;---------------------------------------------------------------------
; ( -- )
def_word "exit", "exit", 0
unnest: ; exit
; pull, ipt = (rpt), rpt += 2
pla
sta ip + 1
pla
sta ip + 0
next:
; wrd = (ipt) ; ipt += 2
ldy #1
lda ipt, y
sta wrd + 1
dey
lda ipt + 0
sta wrd + 0
clc
lda #2
adc ipt + 0
sta ipt + 0
bcc @bccs
inc ipt + 1
@bccs:
pick:
; compare pages (MSBs)
lda wrd + 1
cmp #>ends + 1
; cmp #>init
bmi jump
nest: ; enter
lda ip + 0
pha
lda ip + 1
pha
lda wrd + 0
sta ip + 0
lda wrd + 1
sta ip + 1
jmp next
jump:
jmp (wrd)
;----------------------------------------------------------------------
.ifdef use_extras
;----------------------------------------------------------------------
; extras
;----------------------------------------------------------------------
; ( -- ) ae exit forth
def_word "bye", "bye", 0
jmp byes
;----------------------------------------------------------------------
; ( -- ) ae abort
def_word "abort", "abort_", 0
jmp abort
;----------------------------------------------------------------------
; ( -- ) ae list of data stack
def_word ".S", "splist", 0
lda spt + 0
sta fst + 0
lda spt + 1
sta fst + 1
lda #'S'
jsr putchar
lda #sp0
jsr list
jmp next
;----------------------------------------------------------------------
; ( -- ) ae list of return stack
def_word ".R", "rplist", 0
lda rpt + 0
sta fst + 0
lda rpt + 1
sta fst + 1
lda #'R'
jsr putchar
lda #rp0
jsr list
jmp next
;----------------------------------------------------------------------
; ae list a sequence of references
list:
sec
sbc fst + 0
lsr
tax
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #' '
jsr putchar
txa
jsr puthex
lda #' '
jsr putchar
txa
beq @ends
ldy #0
@loop:
lda #' '
jsr putchar
iny
lda (fst),y
jsr puthex
dey
lda (fst),y
jsr puthex
iny
iny
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ( -- ) dumps the user dictionary
def_word "dump", "dump", 0
lda #$0
sta fst + 0
lda #>ends + 1
sta fst + 1
ldx #(fst)
ldy #0
@loop:
lda (fst),y
jsr putchar
jsr incwx
lda fst + 0
cmp here + 0
bne @loop
lda fst + 1
cmp here + 1
bne @loop
clc ; clean
jmp next
;----------------------------------------------------------------------
; ( -- ) words in dictionary,
def_word "words", "words", 0
; load lastest
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
; load here
lda here + 1
sta trd + 1
lda here + 0
sta trd + 0
@loop:
; lsb linked list
lda snd + 0
sta fst + 0
; verify \0x0
ora snd + 1
beq @ends
; msb linked list
lda snd + 1
sta fst + 1
@each:
lda #10
jsr putchar
; put address
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; put link
lda #' '
jsr putchar
ldy #1
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
ldx #(fst)
lda #2
jsr addwx
; put size + flag, name
ldy #0
jsr show_name
; update
iny
tya
ldx #(fst)
jsr addwx
; show CFA
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; check if is a primitive
lda fst + 1
cmp #>ends + 1
bmi @continue
; list references
ldy #0
jsr show_refer
@continue:
lda snd + 0
sta trd + 0
lda snd + 1
sta trd + 1
ldy #0
lda (trd), y
sta snd + 0
iny
lda (trd), y
sta snd + 1
ldx #(trd)
lda #2
jsr addwx
jmp @loop
@ends:
clc ; clean
jmp next
;----------------------------------------------------------------------
; ae put size and name
show_name:
lda #' '
jsr putchar
lda (fst), y
jsr puthex
lda #' '
jsr putchar
lda (fst), y
and #$7F
tax
@loop:
iny
lda (fst), y
jsr putchar
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
show_refer:
; ae put references PFA ...
ldx #(fst)
@loop:
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #':'
jsr putchar
iny
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
lda #2
jsr addwx
; check if ends
lda fst + 0
cmp trd + 0
bne @loop
lda fst + 1
cmp trd + 1
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ae seek for 'exit to ends a sequence of references
; max of 254 references in list
;
seek:
ldy #0
@loop1:
iny
beq @ends
lda (fst), y
cmp #>exit
bne @loop1
dey
lda (fst), y
cmp #<exit
beq @ends
iny
bne @loop1
@ends:
tya
lsr
clc ; clean
rts
;----------------------------------------------------------------------
; ( u -- u ) print tos in hexadecimal, swaps order
def_word ".", "dot", 0
lda #' '
jsr putchar
jsr spull1
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
jsr spush1
jmp next
;----------------------------------------------------------------------
; code a byte in ASCII hexadecimal
puthex:
pha
lsr
ror
ror
ror
jsr @conv
pla
@conv:
and #$0F
ora #$30
cmp #$3A
bcc @ends
adc #$06
@ends:
clc ; clean
jmp putchar
.endif
.ifdef numbers
;----------------------------------------------------------------------
; code a ASCII $FFFF hexadecimal in a byte
;
number:
ldy #0
jsr @very
asl
asl
asl
asl
sta fst + 1
iny
jsr @very
ora fst + 1
sta fst + 1
iny
jsr @very
asl
asl
asl
asl
sta fst + 0
iny
jsr @very
ora fst + 0
sta fst + 0
clc ; clean
rts
@very:
lda (tout), y
sec
sbc #$30
bmi @erro
cmp #10
bcc @ends
sbc #$07
; any valid digit, A-Z, do not care
@ends:
rts
@erro:
pla
pla
rts
.endif
;---------------------------------------------------------------------
;
; extensions
;
;---------------------------------------------------------------------
.ifdef use_extensions
;---------------------------------------------------------------------
; ( w -- w/2 ) ; shift right
def_word "2/", "shr", 0
jsr spull1
lsr fst + 1
ror fst + 0
jmp this
;---------------------------------------------------------------------
; ( a -- ) execute a jump to a reference at top of data stack
def_word "exec", "exec", 0
jsr spull1
jmp (fst)
;---------------------------------------------------------------------
; ( -- ) execute a jump to a reference at IP
def_word ":$", "docode", 0
jmp (ipt)
;---------------------------------------------------------------------
; ( -- ) execute a jump to next
def_word ";$", "donext", 0
jmp next
.endif
;----------------------------------------------------------------------
; end of code
ends:
;----------------------------------------------------------------------
; anything above is not a primitive
; needed for MTC
; same as #>end+1
;.align $100
;init:
;----------------------------------------------------------------------
|
agsb/milliForth-6502
| 26,757
|
6502/sector-6502.s
|
;----------------------------------------------------------------------
;
; A MilliForth for 6502
;
; original for the 6502, by Alvaro G. S. Barcellos, 2023
;
; https://github.com/agsb
; see the disclaimer file in this repo for more information.
;
; SectorForth and MilliForth was made for x86 arch
; and uses full 16-bit registers
;
; The way at 6502 is use page zero and lots of lda/sta
;
; Focus in size not performance.
;
; why ? For understand better my skills, 6502 code and thread codes
;
; how ? Programming a new Forth for old 8-bit cpu emulator
;
; what ? Design the best minimal Forth engine and vocabulary
;
;----------------------------------------------------------------------
; Changes:
;
; all data (36 cells) and return (36 cells) stacks, TIB (80 bytes)
; and PIC (32 bytes) are in same page $200, 256 bytes;
;
; TIB and PIC grows forward, stacks grows backwards;
;
; no overflow or underflow checks;
;
; the header order is LINK, SIZE+FLAG, NAME.
;
; only IMMEDIATE flag used as $80, no hide, no compile;
;
; As ANSI Forth 1994: FALSE is $0000 ; TRUE is $FFFF ;
;
;----------------------------------------------------------------------
; Remarks:
;
; this code uses
; Direct Thread Code, aka DTC or
; Minimal Thread Code, aka MTC.
;
; use a classic cell with 16-bits.
;
; no TOS register, all values keeped at stacks;
;
; TIB (terminal input buffer) is like a stream;
;
; Chuck Moore uses 64 columns, be wise, obey rule 72 CPL;
;
; words must be between spaces, before and after;
;
; no line wrap, do not break words between lines;
;
; only 7-bit ASCII characters, plus \n, no controls;
; ( later maybe \b backspace and \u cancel )
;
; words are case-sensitivy and less than 16 characters;
;
; no need named-'pad' at end of even names;
;
; no multiuser, no multitask, no checks, not faster;
;
;----------------------------------------------------------------------
; For 6502:
;
; a 8-bit processor with 16-bit address space;
;
; the most significant byte is the page count;
;
; page zero and page one hardware reserved;
;
; hardware stack not used for this Forth;
;
; page zero is used as pseudo registers;
;
;----------------------------------------------------------------------
; For stacks:
;
; "when the heap moves forward, move the stack backward"
;
; as hardware stacks do:
; push is 'store and decrease', pull is 'increase and fetch',
;
; but see the notes for Devs.
;
; common memory model organization of Forth:
; [tib->...<-spt: user forth dictionary :here->pad...<-rpt]
; then backward stacks allow to use the slack space ...
;
; this 6502 Forth memory model blocked in pages of 256 bytes:
; [page0][page1][page2][core ... forth dictionary ...here...]
;
; At page2:
;
; |$00 tib> .. $50| <spt..sp0 $98| <rpt..rp0 $E0|pic> ..$FF|
;
; From page 3 onwards:
;
; |$0300 cold:, warm:, forth code, init: here> heap ... tail|
;
; PIC is a transient area of 32 bytes
; PAD could be allocated from here
;
;----------------------------------------------------------------------
; For Devs:
;
; the hello_world.forth file states that stacks works
; to allow : dup sp@ @ ; so sp must point to actual TOS.
;
; The movement will be:
; pull is 'fetch and increase'
; push is 'decrease and store'
;
; Never mess with two underscore variables;
;
; Not using smudge,
; colon saves "here" into "back" and
; semis loads "lastest" from "back";
;
; Do not risk to put stacks with $FF.
;
; Also carefull inspect if any label ends with $FF and move it;
;
; This source is hacked for use with Ca65.
;
;----------------------------------------------------------------------
;
; Stacks represented as (standart)
; S:(w1 w2 w3 -- u1 u2) R:(w1 w2 w3 -- u1 u2)
; before -- after, top at left.
;
;----------------------------------------------------------------------
;
; Stuff for ca65 compiler
;
.p02
.feature c_comments
.feature string_escapes
.feature org_per_seg
.feature dollar_is_pc
.feature pc_assignment
;---------------------------------------------------------------------
; macros for dictionary, makes:
;
; h_name:
; .word link_to_previous_entry
; .byte strlen(name) + flags
; .byte name
; name:
;
; label for primitives
.macro makelabel arg1, arg2
.ident (.concat (arg1, arg2)):
.endmacro
; header for primitives
; the entry point for dictionary is h_~name~
; the entry point for code is ~name~
.macro def_word name, label, flag
makelabel "h_", label
.ident(.sprintf("H%04X", hcount + 1)) = *
.word .ident (.sprintf ("H%04X", hcount))
hcount .set hcount + 1
.byte .strlen(name) + flag + 0 ; nice trick !
.byte name
makelabel "", label
.endmacro
;---------------------------------------------------------------------
; variables for macros
hcount .set 0
H0000 = 0
;---------------------------------------------------------------------
; define thread code model
; MTC is default
; use_DTC = 1
; uncomment to include the extras (sic)
; use_extras = 1
; uncomment to include the extensions (sic)
; use_extensions = 1
;---------------------------------------------------------------------
/*
NOTES:
not finished yet :)
*/
;----------------------------------------------------------------------
;
; alias
; cell size, two bytes, 16-bit
CELL = 2
; highlander, immediate flag.
FLAG_IMM = 1<<7
; "all in" page $200
; terminal input buffer, forward
; getline, token, skip, scan, depends on page boundary
tib = $0200
; reserve 80 bytes, (72 is enough)
; moves forwards
tib_end = $50
; data stack, 36 cells,
; moves backwards, push decreases before copy
sp0 = $98
; return stack, 36 cells,
; moves backwards, push decreases before copy
rp0 = $E0
; reserved for scribbles
pic = rp0
;----------------------------------------------------------------------
; no values here or must be a BSS
.segment "ZERO"
* = $E0
nil: ; empty for fixed reference
; as user variables
; order matters for hello_world.forth !
; internal Forth
stat: .word $0 ; state at lsb, last size+flag at msb
toin: .word $0 ; toin next free byte in TIB
last: .word $0 ; last link cell
here: .word $0 ; next free cell in heap dictionary, aka dpt
; pointers registers
spt: .word $0 ; data stack base,
rpt: .word $0 ; return stack base
ipt: .word $0 ; instruction pointer
wrd: .word $0 ; word pointer
* = $F0
; free for use
fst: .word $0 ; first
snd: .word $0 ; second
trd: .word $0 ; third
fth: .word $0 ; fourth
; used, reserved
tout: .word $0 ; next token in TIB
back: .word $0 ; hold 'here while compile
; for future expansion, reserved
head: .word $0 ; heap forward, also DP
tail: .word $0 ; heap backward
;----------------------------------------------------------------------
;.segment "ONCE"
; no rom code
;----------------------------------------------------------------------
;.segment "VECTORS"
; no boot code
;----------------------------------------------------------------------
.segment "CODE"
;
; leave space for page zero, hard stack,
; and buffer, locals, forth stacks
;
* = $300
main:
;----------------------------------------------------------------------
; common must
;
cold:
; disable interrupts
sei
; clear BCD
cld
; set real stack
ldx #$FF
txs
; enable interrupts
cli
;----------------------------------------------------------------------
warm:
; link list of headers
lda #>h_exit
sta last + 1
lda #<h_exit
sta last + 0
; next heap free cell, same as init:
lda #>ends + 1
sta here + 1
lda #0
sta here + 0
;---------------------------------------------------------------------
; supose never change
reset:
ldy #>tib
sty spt + 1
sty rpt + 1
sty toin + 1
sty tout + 1
abort:
ldy #<sp0
sty spt + 0
quit:
ldy #<rp0
sty rpt + 0
; reset tib
ldy #0
; clear tib stuff
sty tib + 0
; clear cursor
sty toin + 0
; stat is 'interpret' == \0
sty stat + 0
.byte $2c ; mask next two bytes, nice trick !
;---------------------------------------------------------------------
; the outer loop
resolvept:
.word okey
;---------------------------------------------------------------------
okey:
;; uncomment for feedback
; lda stat + 0
; bne resolve
; lda #'O'
; jsr putchar
; lda #'K'
; jsr putchar
; lda #10
; jsr putchar
resolve:
; get a token
jsr token
; lda #'P'
; jsr putchar
find:
; load last
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
@loop:
; lsb linked list
lda snd + 0
sta wrd + 0
; verify \0x0
ora snd + 1
beq abort
; maybe to place a code for number?
; but not for now.
;; uncomment for feedback, comment out "beq abort" above
; lda #'?'
; jsr putchar
; lda #'?'
; jsr putchar
; lda #10
; jsr putchar
; jmp abort ; end of dictionary, no more words to search, abort
@each:
; msb linked list
lda snd + 1
sta wrd + 1
; update next link
ldx #(wrd) ; from
ldy #(snd) ; into
jsr copyfrom
; compare words
ldy #0
; save the flag, first byte is (size and flag)
lda (wrd), y
sta stat + 1
; compare chars
@equal:
lda (tout), y
; space ends
cmp #32
beq @done
; verify
sec
sbc (wrd), y
; clean 7-bit ascii
asl
bne @loop
; next char
iny
bne @equal
@done:
; update wrd
tya
;; ldx #(wrd) ; set already
;; addwx also clear carry
jsr addwx
eval:
; executing ? if == \0
lda stat + 0
beq execute
; immediate ? if < \0
lda stat + 1
bmi immediate
compile:
; lda #'C'
; jsr putchar
jsr wcomma
bcc resolve
immediate:
execute:
; lda #'E'
; jsr putchar
lda #>resolvept
sta ipt + 1
lda #<resolvept
sta ipt + 0
;~~~~~~~~
.ifdef use_DTC
jmp (wrd)
.else
jmp pick
.endif
;~~~~~~~~
;---------------------------------------------------------------------
try:
lda tib, y
beq getline ; if \0
iny
eor #' '
rts
;---------------------------------------------------------------------
getline:
; drop rts of try
pla
pla
; leave the first
ldy #0
@loop:
; is valid
sta tib, y ; dummy store on first pass, overwritten
iny
; would be better with
; end of buffer ?
; cpy #tib_end
; beq @ends
; then
jsr getchar
; would be better with
; 7-bit ascii only
; and #$7F
; unix \n
cmp #10
bne @loop
; would be better with
; no controls
; cmp #' '
; bmi @loop
; clear all if y eq \0
@ends:
; grace \b
lda #32
sta tib + 0 ; start with space
sta tib, y ; ends with space
; mark eol with \0
lda #0
sta tib + 1, y
; start it
sta toin + 0
;---------------------------------------------------------------------
; in place every token,
; the counter is placed at last space before word
; no rewinds
token:
; last position on tib
ldy toin + 0
@skip:
; skip spaces
jsr try
beq @skip
; keep y == start + 1
dey
sty tout + 0
@scan:
; scan spaces
jsr try
bne @scan
; keep y == stop + 1
dey
sty toin + 0
@done:
; sizeof
tya
sec
sbc tout + 0
; keep it
ldy tout + 0
dey
sta tib, y ; store size for counted string
sty tout + 0
; setup token
clc ; clean
rts
;---------------------------------------------------------------------
; this code depends on systems or emulators
;
; lib6502 emulator
;
getchar:
lda $E000
eofs:
; EOF ?
cmp #$FF ; also clean carry :)
beq byes
putchar:
sta $E000
rts
; exit for emulator
byes:
jmp $0000
;
; lib6502 emulator
;---------------------------------------------------------------------
;---------------------------------------------------------------------
; decrement a word in page zero. offset by X
decwx:
lda 0, x
bne @ends
dec 1, x
@ends:
dec 0, x
rts
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
;incwx:
; inc 0, x
; bne @ends
; inc 1, x
;@ends:
; rts
;---------------------------------------------------------------------
; classic heap moves always forward
;
stawrd:
sta wrd + 1
wcomma:
ldy #(wrd)
comma:
ldx #(here)
; fall throught
;---------------------------------------------------------------------
; from a page zero address indexed by Y
; into a page zero indirect address indexed by X
copyinto:
lda 0, y
sta (0, x)
jsr incwx
lda 1, y
sta (0, x)
jmp incwx
;---------------------------------------------------------------------
;
; generics
;
;---------------------------------------------------------------------
spush1:
ldy #(fst)
;---------------------------------------------------------------------
; push a cell
; from a page zero address indexed by Y
; into a page zero indirect address indexed by X
spush:
ldx #(spt)
; jmp push
.byte $2c ; mask next two bytes, nice trick !
rpush:
ldx #(rpt)
;---------------------------------------------------------------------
; classic stack backwards
push:
jsr decwx
lda 1, y
sta (0, x)
jsr decwx
lda 0, y
sta (0, x)
rts
;---------------------------------------------------------------------
spull2:
ldy #(snd)
jsr spull
; fall through
;---------------------------------------------------------------------
spull1:
ldy #(fst)
; fall through
;---------------------------------------------------------------------
; pull a cell
; from a page zero indirect address indexed by X
; into a page zero address indexed by y
spull:
ldx #(spt)
; jmp pull
.byte $2c ; mask next two bytes, nice trick !
rpull:
ldx #(rpt)
;---------------------------------------------------------------------
; classic stack backwards
pull: ; fall through, same as copyfrom
;---------------------------------------------------------------------
; from a page zero indirect address indexed by X
; into a page zero address indexed by y
copyfrom:
lda (0, x)
sta 0, y
jsr incwx
lda (0, x)
sta 1, y
; jmp incwx ; fall through
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
incwx:
lda #01
;---------------------------------------------------------------------
; add a byte to a word in page zero. offset by X
addwx:
clc
adc 0, x
sta 0, x
bcc @ends
inc 1, x
clc ; keep carry clean
@ends:
rts
;---------------------------------------------------------------------
;
; the primitives,
; for stacks uses
; a address, c byte ascii, w signed word, u unsigned word
; cs counted string < 256, sz string with nul ends
;
;----------------------------------------------------------------------
.ifdef use_extras
;----------------------------------------------------------------------
; extras
;----------------------------------------------------------------------
; ( -- ) ae exit forth
def_word "bye", "bye", 0
jmp byes
;----------------------------------------------------------------------
; ( -- ) ae abort
def_word "abort", "abort_", 0
jmp abort
;----------------------------------------------------------------------
; ( -- ) ae list of data stack
def_word "%S", "splist", 0
lda spt + 0
sta fst + 0
lda spt + 1
sta fst + 1
lda #'S'
jsr putchar
lda #sp0
jsr list
jmp next
;----------------------------------------------------------------------
; ( -- ) ae list of return stack
def_word "%R", "rplist", 0
lda rpt + 0
sta fst + 0
lda rpt + 1
sta fst + 1
lda #'R'
jsr putchar
lda #rp0
jsr list
jmp next
;----------------------------------------------------------------------
; ae list a sequence of references
list:
sec
sbc fst + 0
lsr
tax
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #' '
jsr putchar
txa
jsr puthex
lda #' '
jsr putchar
txa
beq @ends
ldy #0
@loop:
lda #' '
jsr putchar
iny
lda (fst),y
jsr puthex
dey
lda (fst),y
jsr puthex
iny
iny
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ( -- ) dumps the user dictionary
def_word "dump", "dump", 0
lda #$0
sta fst + 0
lda #>ends + 1
sta fst + 1
ldx #(fst)
ldy #0
@loop:
lda (fst),y
jsr putchar
jsr incwx
lda fst + 0
cmp here + 0
bne @loop
lda fst + 1
cmp here + 1
bne @loop
clc ; clean
jmp next
;----------------------------------------------------------------------
; ( -- ) words in dictionary,
def_word "words", "words", 0
; load lastest
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
; load here
lda here + 1
sta trd + 1
lda here + 0
sta trd + 0
@loop:
; lsb linked list
lda snd + 0
sta fst + 0
; verify \0x0
ora snd + 1
beq @ends
; msb linked list
lda snd + 1
sta fst + 1
@each:
lda #10
jsr putchar
; put address
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; put link
lda #' '
jsr putchar
ldy #1
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
ldx #(fst)
lda #2
jsr addwx
; put size + flag, name
ldy #0
jsr show_name
; update
iny
tya
ldx #(fst)
jsr addwx
; show CFA
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; check if is a primitive
lda fst + 1
cmp #>ends + 1
bmi @continue
; list references
ldy #0
jsr show_refer
@continue:
lda snd + 0
sta trd + 0
lda snd + 1
sta trd + 1
ldy #0
lda (trd), y
sta snd + 0
iny
lda (trd), y
sta snd + 1
ldx #(trd)
lda #2
jsr addwx
jmp @loop
@ends:
clc ; clean
jmp next
;----------------------------------------------------------------------
; ae put size and name
show_name:
lda #' '
jsr putchar
lda (fst), y
jsr puthex
lda #' '
jsr putchar
lda (fst), y
and #$7F
tax
@loop:
iny
lda (fst), y
jsr putchar
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
show_refer:
; ae put references PFA ...
ldx #(fst)
@loop:
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #':'
jsr putchar
iny
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
lda #2
jsr addwx
; check if ends
lda fst + 0
cmp trd + 0
bne @loop
lda fst + 1
cmp trd + 1
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ae seek for 'exit to ends a sequence of references
; max of 254 references in list
;
seek:
ldy #0
@loop1:
iny
beq @ends
lda (fst), y
cmp #>exit
bne @loop1
dey
lda (fst), y
cmp #<exit
beq @ends
iny
bne @loop1
@ends:
tya
lsr
clc ; clean
rts
;----------------------------------------------------------------------
; ( u -- u ) print tos in hexadecimal, swaps order
def_word ".", "dot", 0
lda #' '
jsr putchar
jsr spull1
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
jsr spush1
jmp next
;----------------------------------------------------------------------
; code a byte in ASCII hexadecimal
puthex:
pha
lsr
ror
ror
ror
jsr @conv
pla
@conv:
and #$0F
ora #$30
cmp #$3A
bcc @ends
adc #$06
@ends:
clc ; clean
jmp putchar
.endif
.ifdef numbers
;----------------------------------------------------------------------
; code a ASCII $FFFF hexadecimal in a byte
;
number:
ldy #0
jsr @very
asl
asl
asl
asl
sta fst + 1
iny
jsr @very
ora fst + 1
sta fst + 1
iny
jsr @very
asl
asl
asl
asl
sta fst + 0
iny
jsr @very
ora fst + 0
sta fst + 0
clc ; clean
rts
@very:
lda (tout), y
sec
sbc #$30
bmi @erro
cmp #10
bcc @ends
sbc #$07
; any valid digit, A-Z, do not care
@ends:
rts
@erro:
pla
pla
rts
.endif
;---------------------------------------------------------------------
;
; extensions
;
;---------------------------------------------------------------------
.ifdef use_extensions
;---------------------------------------------------------------------
; ( w -- w/2 ) ; shift right
def_word "2/", "shr", 0
jsr spull1
lsr fst + 1
ror fst + 0
jmp this
;---------------------------------------------------------------------
; ( a -- ) execute a jump to a reference at top of data stack
def_word "exec", "exec", 0
jsr spull1
jmp (fst)
;---------------------------------------------------------------------
; ( -- ) execute a jump to a reference at IP
def_word ":$", "docode", 0
jmp (ipt)
;---------------------------------------------------------------------
; ( -- ) execute a jump to next
def_word ";$", "donext", 0
jmp next
.endif
;---------------------------------------------------------------------
; core primitives minimal
; start of dictionary
;---------------------------------------------------------------------
; ( -- u ) ; tos + 1 unchanged
def_word "key", "key", 0
jsr getchar
sta fst + 0
; jmp this ; uncomment if char could be \0
bne this ; always taken
;---------------------------------------------------------------------
; ( u -- ) ; tos + 1 unchanged
def_word "emit", "emit", 0
jsr spull1
lda fst + 0
jsr putchar
; jmp next ; uncomment if carry could be set
bcc jmpnext ; always taken
;---------------------------------------------------------------------
; ( a w -- ) ; [a] = w
def_word "!", "store", 0
storew:
jsr spull2
ldx #(snd)
ldy #(fst)
jsr copyinto
; jmp next ; uncomment if carry could be set
bcc jmpnext ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- NOT(w1 AND w2) )
def_word "nand", "nand", 0
jsr spull2
lda snd + 0
and fst + 0
eor #$FF
sta fst + 0
lda snd + 1
and fst + 1
eor #$FF
; jmp keeps ; uncomment if carry could be set
bcc keeps ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- w1+w2 )
def_word "+", "plus", 0
jsr spull2
clc ; better safe than sorry
lda snd + 0
adc fst + 0
sta fst + 0
lda snd + 1
adc fst + 1
jmp keeps
;---------------------------------------------------------------------
; ( a -- w ) ; w = [a]
def_word "@", "fetch", 0
fetchw:
jsr spull1
ldx #(fst)
ldy #(snd)
jsr copyfrom
; fall throught
;---------------------------------------------------------------------
copys:
lda 0, y
sta fst + 0
lda 1, y
keeps:
sta fst + 1
this:
jsr spush1
jmpnext:
jmp next
;---------------------------------------------------------------------
; ( 0 -- $0000) | ( n -- $FFFF) not zero at top ?
def_word "0#", "zeroq", 0
jsr spull1
lda fst + 1
ora fst + 0
beq isfalse ; is \0 ?
istrue:
lda #$FF
isfalse:
sta fst + 0
jmp keeps
;---------------------------------------------------------------------
; ( -- state ) a variable return an reference
def_word "s@", "state", 0
lda #<stat
sta fst + 0
lda #>stat
; jmp keeps ; uncomment if stats not in page $0
beq keeps ; always taken
;---------------------------------------------------------------------
def_word ";", "semis", FLAG_IMM
; update last, panic if colon not lead elsewhere
lda back + 0
sta last + 0
lda back + 1
sta last + 1
; stat is 'interpret'
lda #0
sta stat + 0
; compound words must ends with exit
finish:
lda #<exit
sta wrd + 0
lda #>exit
sta wrd + 1
jsr wcomma
; jmp next
bcc next ; always taken
;---------------------------------------------------------------------
def_word ":", "colon", 0
; save here, panic if semis not follow elsewhere
lda here + 0
sta back + 0
lda here + 1
sta back + 1
; stat is 'compile'
lda #1
sta stat + 0
@header:
; copy last into (here)
ldy #(last)
jsr comma
; get following token
jsr token
; copy it
ldy #0
@loop:
lda (tout), y
cmp #32 ; stops at space
beq @ends
sta (here), y
iny
bne @loop
@ends:
; update here
tya
ldx #(here)
jsr addwx
;~~~~~~~~
.ifdef use_DTC
; magic NOP (EA) JSR (20), at CFA cell
; magic = $EA20
magic = $20EA
; inserts the nop call
lda #<magic
sta wrd + 0
lda #>magic
jsr stawrd
; inserts the reference
lda #<nest
sta wrd + 0
lda #>nest
jsr stawrd
.endif
;~~~~~~~~
; done
; jmp next
bcc next ; always taken
;---------------------------------------------------------------------
; Thread Code Engine
;
; ipt is IP, wrd is W
;
; for reference:
;
; nest aka enter or docol,
; unnest aka exit or semis;
;
;---------------------------------------------------------------------
; ( -- )
def_word "exit", "exit", 0
unnest: ; exit
; pull, ipt = (rpt), rpt += 2
ldy #(ipt)
jsr rpull
next:
; wrd = (ipt) ; ipt += 2
ldx #(ipt)
ldy #(wrd)
jsr copyfrom
;~~~~~~~~
.ifdef use_DTC
pick:
jmp (wrd)
nest: ; enter
; push, *rp = ipt, rp -=2
ldy #(ipt)
jsr rpush
; pull (ip),
pla
sta ipt + 0
pla
sta ipt + 1
; 6502 trick: must increase return address
ldx #(ipt)
jsr incwx
bcc next
.else
pick:
; compare pages (MSBs)
lda wrd + 1
cmp #>ends + 1
bmi jump
nest: ; enter
; push, *rp = ipt, rp -=2
ldy #(ipt)
jsr rpush
lda wrd + 0
sta ipt + 0
lda wrd + 1
sta ipt + 1
jmp next
jump:
jmp (wrd)
.endif
;~~~~~~~~
;-----------------------------------------------------------------------
; BEWARE, MUST BE AT END! MINIMAL THREAD CODE DEPENDS ON IT!
ends:
;-----------------------------------------------------------------------
; anything above is not a primitive
;----------------------------------------------------------------------
|
agsb/milliForth-6502
| 26,860
|
6502/sector-6502-zero.s
|
;----------------------------------------------------------------------
;
; A MilliForth for 6502
;
; original for the 6502, by Alvaro G. S. Barcellos, 2023
;
; https://github.com/agsb
; see the disclaimer file in this repo for more information.
;
; SectorForth and MilliForth was made for x86 arch
; and uses full 16-bit registers
;
; The way at 6502 is use page zero and lots of lda/sta
;
; Focus in size not performance.
;
; why ? For understand better my skills, 6502 code and thread codes
;
; how ? Programming a new Forth for old 8-bit cpu emulator
;
; what ? Design the best minimal Forth engine and vocabulary
;
;----------------------------------------------------------------------
; Changes:
;
; all data (36 cells) and return (36 cells) stacks, TIB (80 bytes)
; and PIC (32 bytes) are in same page $200, 256 bytes;
;
; TIB and PIC grows forward, stacks grows backwards;
;
; no overflow or underflow checks;
;
; the header order is LINK, SIZE+FLAG, NAME.
;
; only IMMEDIATE flag used as $80, no hide, no compile;
;
; As ANSI Forth 1994: FALSE is $0000 ; TRUE is $FFFF ;
;
;----------------------------------------------------------------------
; Remarks:
;
; this code uses
; Direct Thread Code, aka DTC or
; Minimal Thread Code, aka MTC.
;
; use a classic cell with 16-bits.
;
; no TOS register, all values keeped at stacks;
;
; TIB (terminal input buffer) is like a stream;
;
; Chuck Moore uses 64 columns, be wise, obey rule 72 CPL;
;
; words must be between spaces, before and after;
;
; no line wrap, do not break words between lines;
;
; only 7-bit ASCII characters, plus \n, no controls;
; ( later maybe \b backspace and \u cancel )
;
; words are case-sensitivy and less than 16 characters;
;
; no need named-'pad' at end of even names;
;
; no multiuser, no multitask, no checks, not faster;
;
;----------------------------------------------------------------------
; For 6502:
;
; a 8-bit processor with 16-bit address space;
;
; the most significant byte is the page count;
;
; page zero and page one hardware reserved;
;
; hardware stack not used for this Forth;
;
; page zero is used as pseudo registers;
;
;----------------------------------------------------------------------
; For stacks:
;
; "when the heap moves forward, move the stack backward"
;
; as hardware stacks do:
; push is 'store and decrease', pull is 'increase and fetch',
;
; but see the notes for Devs.
;
; common memory model organization of Forth:
; [tib->...<-spt: user forth dictionary :here->pad...<-rpt]
; then backward stacks allow to use the slack space ...
;
; this 6502 Forth memory model blocked in pages of 256 bytes:
; [page0][page1][page2][core ... forth dictionary ...here...]
;
; At page2:
;
; |$00 tib> .. $50| <spt..sp0 $98| <rpt..rp0 $E0|pic> ..$FF|
;
; From page 3 onwards:
;
; |$0300 cold:, warm:, forth code, init: here> heap ... tail|
;
; PIC is a transient area of 32 bytes
; PAD could be allocated from here
;
;----------------------------------------------------------------------
; For Devs:
;
; the hello_world.forth file states that stacks works
; to allow : dup sp@ @ ; so sp must point to actual TOS.
;
; The movement will be:
; pull is 'fetch and increase'
; push is 'decrease and store'
;
; Never mess with two underscore variables;
;
; Not using smudge,
; colon saves "here" into "back" and
; semis loads "lastest" from "back";
;
; Do not risk to put stacks with $FF.
;
; Also carefull inspect if any label ends with $FF and move it;
;
; This source is hacked for use with Ca65.
;
;----------------------------------------------------------------------
;
; Stacks represented as (standart)
; S:(w1 w2 w3 -- u1 u2) R:(w1 w2 w3 -- u1 u2)
; before -- after, top at left.
;
;----------------------------------------------------------------------
;
; Stuff for ca65 compiler
;
.p02
.feature c_comments
.feature string_escapes
.feature org_per_seg
.feature dollar_is_pc
.feature pc_assignment
;---------------------------------------------------------------------
; macros for dictionary, makes:
;
; h_name:
; .word link_to_previous_entry
; .byte strlen(name) + flags
; .byte name
; name:
;
; label for primitives
.macro makelabel arg1, arg2
.ident (.concat (arg1, arg2)):
.endmacro
; header for primitives
; the entry point for dictionary is h_~name~
; the entry point for code is ~name~
.macro def_word name, label, flag
makelabel "h_", label
.ident(.sprintf("H%04X", hcount + 1)) = *
.word .ident (.sprintf ("H%04X", hcount))
hcount .set hcount + 1
.byte .strlen(name) + flag + 0 ; nice trick !
.byte name
makelabel "", label
.endmacro
;---------------------------------------------------------------------
; variables for macros
hcount .set 0
H0000 = 0
;---------------------------------------------------------------------
; define thread code model
; MTC is default
; use_DTC = 1
; uncomment to include the extras (sic)
use_extras = 1
; uncomment to include the extensions (sic)
use_extensions = 1
;---------------------------------------------------------------------
/*
NOTES:
not finished yet :)
*/
;----------------------------------------------------------------------
;
; alias
; cell size, two bytes, 16-bit
CELL = 2
; highlander, immediate flag.
FLAG_IMM = 1<<7
; "all in" page $200
; terminal input buffer, forward
; getline, token, skip, scan, depends on page boundary
tib = $0200
; reserve 80 bytes, (72 is enough)
; moves forwards
tib_end = $50
; reserved for scribbles
pic = tib_end
; data stack, 36 cells,
; moves backwards, push decreases before copy
DATA_SIZE = 24 * 2
; return stack, 36 cells,
; moves backwards, push decreases before copy
RETURN_SIZE = 24 * 2
;----------------------------------------------------------------------
; "What happens in Vegas, stays in Vegas", like in page zero
; but no values here or must be at BSS
.segment "ZERO"
; * = $TAKE_ME
; empty for fixed reference
nil:
; cascate allocation
; stacks
sp0 = nil + DATA_SIZE
rp0 = sp0 + RETURN_SIZE
spi = rp0 + 1
rpi = spi + 1
; pointers registers
ipt = rpi + 2 ; instruction pointer
wrd = ipt + 2 ; word pointer
; for future expansion, reserved
head = wrd + 2 ; heap forward, also DP
tail = head + 2 ; heap backward
; used, reserved
tout = tail + 2 ; next token in TIB
back = tout + 2 ; hold 'here while compile
; classic, free for use
fst = back + 2 ; first
snd = fst + 2 ; second
trd = snd + 2 ; third
fth = trd + 2 ; fourth
; as user variables
; sure, order matters for hello_world.forth !
; internal Forth
stat = fth + 2 ; state at lsb, last size+flag at msb
toin = stat + 2 ; toin next free byte in TIB
last = toin + 2 ; last link cell
here = last + 2 ; next free cell in heap dictionary, aka dpt
.end
;----------------------------------------------------------------------
;.segment "ONCE"
; no rom code
;----------------------------------------------------------------------
;.segment "VECTORS"
; no boot code
;----------------------------------------------------------------------
.segment "CODE"
; ram code here
;
; leave space for page zero, hard stack,
; and buffer, locals, forth stacks
;
* = $300
main:
;----------------------------------------------------------------------
; common must
;
cold:
; disable interrupts
sei
; clear BCD
cld
; set real stack
ldx #$FF
txs
; enable interrupts
cli
;----------------------------------------------------------------------
warm:
; link list of headers
lda #>h_exit
sta last + 1
lda #<h_exit
sta last + 0
; next heap free cell, same as init:
lda #>ends + 1
sta here + 1
lda #0
sta here + 0
;---------------------------------------------------------------------
; supose never change
reset:
ldy #02
sty toin + 1
sty tout + 1
abort:
ldy #sp0
sty spi
quit:
ldy #rp0
sty rpi
clean:
; reset tib
ldy #0
; clear tib stuff
sty tib + 0
; clear cursor
sty toin + 0
; stat is 'interpret' == \0
sty stat + 0
.byte $2c ; mask next two bytes, nice trick !
;---------------------------------------------------------------------
; the outer loop
resolvept:
.word okey
;---------------------------------------------------------------------
okey:
;; uncomment for feedback
; lda stat + 0
; bne resolve
; lda #'O'
; jsr putchar
; lda #'K'
; jsr putchar
; lda #10
; jsr putchar
resolve:
; get a token
jsr token
; lda #'P'
; jsr putchar
find:
; load last
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
@loop:
; lsb linked list
lda snd + 0
sta wrd + 0
; verify \0x0
ora snd + 1
beq abort
; maybe to place a code for number?
; but not for now.
;; uncomment for feedback, comment out "beq abort" above
; lda #'?'
; jsr putchar
; lda #'?'
; jsr putchar
; lda #10
; jsr putchar
; jmp abort ; end of dictionary, no more words to search, abort
@each:
; msb linked list
lda snd + 1
sta wrd + 1
; update next link
ldx #(wrd) ; from
ldy #(snd) ; into
jsr copyfrom
; compare words
ldy #0
; save the flag, first byte is (size and flag)
lda (wrd), y
sta stat + 1
; compare chars
@equal:
lda (tout), y
; space ends
cmp #32
beq @done
; verify
sec
sbc (wrd), y
; clean 7-bit ascii
asl
bne @loop
; next char
iny
bne @equal
@done:
; update wrd
tya
;; ldx #(wrd) ; set already
;; addwx also clear carry
jsr addwx
eval:
; executing ? if == \0
lda stat + 0
beq execute
; immediate ? if < \0
lda stat + 1
bmi immediate
compile:
; lda #'C'
; jsr putchar
jsr wcomma
bcc resolve
immediate:
execute:
; lda #'E'
; jsr putchar
lda #>resolvept
sta ipt + 1
lda #<resolvept
sta ipt + 0
;~~~~~~~~
.ifdef use_DTC
jmp (wrd)
.else
jmp pick
.endif
;~~~~~~~~
;---------------------------------------------------------------------
try:
lda tib, y
beq getline ; if \0
iny
eor #' '
rts
;---------------------------------------------------------------------
getline:
; drop rts of try
pla
pla
; leave the first
ldy #0
@loop:
; is valid
sta tib, y ; dummy store on first pass, overwritten
iny
; would be better with
; end of buffer ?
; cpy #tib_end
; beq @ends
; then
jsr getchar
; would be better with
; 7-bit ascii only
; and #$7F
; unix \n
cmp #10
bne @loop
; would be better with
; no controls
; cmp #' '
; bmi @loop
; clear all if y eq \0
@ends:
; grace \b
lda #32
sta tib + 0 ; start with space
sta tib, y ; ends with space
; mark eol with \0
lda #0
sta tib + 1, y
; start it
sta toin + 0
;---------------------------------------------------------------------
; in place every token,
; the counter is placed at last space before word
; no rewinds
token:
; last position on tib
ldy toin + 0
@skip:
; skip spaces
jsr try
beq @skip
; keep y == start + 1
dey
sty tout + 0
@scan:
; scan spaces
jsr try
bne @scan
; keep y == stop + 1
dey
sty toin + 0
@done:
; sizeof
tya
sec
sbc tout + 0
; keep it
ldy tout + 0
dey
sta tib, y ; store size for counted string
sty tout + 0
; setup token
clc ; clean
rts
;---------------------------------------------------------------------
; this code depends on systems or emulators
;
; lib6502 emulator
;
getchar:
lda $E000
eofs:
; EOF ?
cmp #$FF ; also clean carry :)
beq byes
putchar:
sta $E000
rts
; exit for emulator
byes:
jmp $0000
;
; lib6502 emulator
;---------------------------------------------------------------------
;---------------------------------------------------------------------
; decrement a word in page zero. offset by X
decwx:
lda 0, x
bne @ends
dec 1, x
@ends:
dec 0, x
rts
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
;incwx:
; inc 0, x
; bne @ends
; inc 1, x
;@ends:
; rts
;---------------------------------------------------------------------
; classic heap moves always forward
;
stawrd:
sta wrd + 1
wcomma:
ldy #(wrd)
comma:
ldx #(here)
; fall throught
;---------------------------------------------------------------------
; from a page zero address indexed by Y
; into a page zero indirect address indexed by X
copyinto:
lda 0, y
sta (0, x)
jsr incwx
lda 1, y
sta (0, x)
jmp incwx
;---------------------------------------------------------------------
;
; generics
;
;---------------------------------------------------------------------
spush1:
ldy #(fst)
;---------------------------------------------------------------------
; push a cell
; from a page zero address indexed by Y
; into a page zero address indexed by X
spush:
ldx #(spi)
; jmp push
.byte $2c ; mask next two bytes, nice trick !
rpush:
ldx #(rpi)
;---------------------------------------------------------------------
; classic stack backwards
push:
dex
lda 1, y
sta 0, x
dex
lda 0, y
sta 0, x
rts
;---------------------------------------------------------------------
spull2:
ldy #(snd)
jsr spull
; fall through
;---------------------------------------------------------------------
spull1:
ldy #(fst)
; fall through
;---------------------------------------------------------------------
; pull a cell
; from a page zero indirect address indexed by X
; into a page zero address indexed by y
spull:
ldx #(spi)
; jmp pull
.byte $2c ; mask next two bytes, nice trick !
rpull:
ldx #(rpi)
;---------------------------------------------------------------------
; classic stack backwards
pull: ; fall through, same as copyfrom
;---------------------------------------------------------------------
; from a page zero address indexed by X
; into a page zero address indexed by y
copyfrom:
lda 0, x
sta 0, y
inx
lda 0, x
sta 1, y
; jmp incwx ; fall through
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
incwx:
lda #01
;---------------------------------------------------------------------
; add a byte to a word in page zero. offset by X
addwx:
clc
adc 0, x
sta 0, x
bcc @ends
inc 1, x
clc ; keep carry clean
@ends:
rts
;---------------------------------------------------------------------
;
; the primitives,
; for stacks uses
; a address, c byte ascii, w signed word, u unsigned word
; cs counted string < 256, sz string with nul ends
;
;----------------------------------------------------------------------
.ifdef use_extras
;----------------------------------------------------------------------
; extras
;----------------------------------------------------------------------
; ( -- ) ae exit forth
def_word "bye", "bye", 0
jmp byes
;----------------------------------------------------------------------
; ( -- ) ae abort
def_word "abort", "abort_", 0
jmp abort
;----------------------------------------------------------------------
; ( -- ) ae list of data stack
def_word ".S", "splist", 0
lda spi + 0
sta fst + 0
lda #00
sta fst + 1
lda #'S'
jsr putchar
lda #sp0
jsr list
jmp next
;----------------------------------------------------------------------
; ( -- ) ae list of return stack
def_word ".R", "rplist", 0
lda rpi
sta fst + 0
lda #00
sta fst + 1
lda #'R'
jsr putchar
lda #rp0
jsr list
jmp next
;----------------------------------------------------------------------
; ae list a sequence of references
list:
sec
sbc fst + 0
lsr
tax
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #' '
jsr putchar
txa
jsr puthex
lda #' '
jsr putchar
txa
beq @ends
ldy #0
@loop:
lda #' '
jsr putchar
iny
lda (fst),y
jsr puthex
dey
lda (fst),y
jsr puthex
iny
iny
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ( -- ) dumps the user dictionary
def_word "dump", "dump", 0
lda #$0
sta fst + 0
lda #>ends + 1
sta fst + 1
ldx #(fst)
ldy #0
@loop:
lda (fst),y
jsr putchar
jsr incwx
lda fst + 0
cmp here + 0
bne @loop
lda fst + 1
cmp here + 1
bne @loop
clc ; clean
jmp next
;----------------------------------------------------------------------
; ( -- ) words in dictionary,
def_word "words", "words", 0
; load lastest
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
; load here
lda here + 1
sta trd + 1
lda here + 0
sta trd + 0
@loop:
; lsb linked list
lda snd + 0
sta fst + 0
; verify \0x0
ora snd + 1
beq @ends
; msb linked list
lda snd + 1
sta fst + 1
@each:
lda #10
jsr putchar
; put address
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; put link
lda #' '
jsr putchar
ldy #1
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
ldx #(fst)
lda #2
jsr addwx
; put size + flag, name
ldy #0
jsr show_name
; update
iny
tya
ldx #(fst)
jsr addwx
; show CFA
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; check if is a primitive
lda fst + 1
cmp #>ends + 1
bmi @continue
; list references
ldy #0
jsr show_refer
@continue:
lda snd + 0
sta trd + 0
lda snd + 1
sta trd + 1
ldy #0
lda (trd), y
sta snd + 0
iny
lda (trd), y
sta snd + 1
ldx #(trd)
lda #2
jsr addwx
jmp @loop
@ends:
clc ; clean
jmp next
;----------------------------------------------------------------------
; ae put size and name
show_name:
lda #' '
jsr putchar
lda (fst), y
jsr puthex
lda #' '
jsr putchar
lda (fst), y
and #$7F
tax
@loop:
iny
lda (fst), y
jsr putchar
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
show_refer:
; ae put references PFA ...
ldx #(fst)
@loop:
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #':'
jsr putchar
iny
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
lda #2
jsr addwx
; check if ends
lda fst + 0
cmp trd + 0
bne @loop
lda fst + 1
cmp trd + 1
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ae seek for 'exit to ends a sequence of references
; max of 254 references in list
;
seek:
ldy #0
@loop1:
iny
beq @ends
lda (fst), y
cmp #>exit
bne @loop1
dey
lda (fst), y
cmp #<exit
beq @ends
iny
bne @loop1
@ends:
tya
lsr
clc ; clean
rts
;----------------------------------------------------------------------
; ( u -- u ) print tos in hexadecimal, swaps order
def_word ".", "dot", 0
lda #' '
jsr putchar
jsr spull1
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
jsr spush1
jmp next
;----------------------------------------------------------------------
; code a byte in ASCII hexadecimal
puthex:
pha
lsr
ror
ror
ror
jsr @conv
pla
@conv:
and #$0F
ora #$30
cmp #$3A
bcc @ends
adc #$06
@ends:
clc ; clean
jmp putchar
.endif
; .ifdef use_extras
.ifdef numbers
;----------------------------------------------------------------------
; code a ASCII $FFFF hexadecimal in a byte
;
number:
ldy #0
jsr @very
asl
asl
asl
asl
sta fst + 1
iny
jsr @very
ora fst + 1
sta fst + 1
iny
jsr @very
asl
asl
asl
asl
sta fst + 0
iny
jsr @very
ora fst + 0
sta fst + 0
clc ; clean
rts
@very:
lda (tout), y
sec
sbc #$30
bmi @erro
cmp #10
bcc @ends
sbc #$07
; any valid digit, A-Z, do not care
@ends:
rts
@erro:
pla
pla
rts
.endif
; .ifdef numbers
;---------------------------------------------------------------------
;
; extensions
;
;---------------------------------------------------------------------
.ifdef use_extensions
;---------------------------------------------------------------------
; ( w -- w/2 ) ; shift right
def_word "2/", "shr", 0
jsr spull1
lsr fst + 1
ror fst + 0
jmp this
;---------------------------------------------------------------------
; ( a -- ) execute a jump to a reference at top of data stack
def_word "exec", "exec", 0
jsr spull1
jmp (fst)
;---------------------------------------------------------------------
; ( -- ) execute a jump to a reference at IP
def_word ":$", "docode", 0
jmp (ipt)
;---------------------------------------------------------------------
; ( -- ) execute a jump to next
def_word ";$", "donext", 0
jmp next
.endif
; .ifdef use_extensions
;---------------------------------------------------------------------
; core primitives minimal
; start of dictionary
;---------------------------------------------------------------------
; ( -- u ) ; tos + 1 unchanged
def_word "key", "key", 0
jsr getchar
sta fst + 0
; jmp this ; uncomment if char could be \0
bne this ; always taken
;---------------------------------------------------------------------
; ( u -- ) ; tos + 1 unchanged
def_word "emit", "emit", 0
jsr spull1
lda fst + 0
jsr putchar
; jmp next ; uncomment if carry could be set
bcc jmpnext ; always taken
;---------------------------------------------------------------------
; ( a w -- ) ; [a] = w
def_word "!", "store", 0
storew:
jsr spull2
ldx #(snd)
ldy #(fst)
jsr copyinto
; jmp next ; uncomment if carry could be set
bcc jmpnext ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- NOT(w1 AND w2) )
def_word "nand", "nand", 0
jsr spull2
lda snd + 0
and fst + 0
eor #$FF
sta fst + 0
lda snd + 1
and fst + 1
eor #$FF
; jmp keeps ; uncomment if carry could be set
bcc keeps ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- w1+w2 )
def_word "+", "plus", 0
jsr spull2
clc ; better safe than sorry
lda snd + 0
adc fst + 0
sta fst + 0
lda snd + 1
adc fst + 1
jmp keeps
;---------------------------------------------------------------------
; ( a -- w ) ; w = [a]
def_word "@", "fetch", 0
fetchw:
jsr spull1
ldx #(fst)
ldy #(snd)
jsr copyfrom
; fall throught
;---------------------------------------------------------------------
copys:
lda 0, y
sta fst + 0
lda 1, y
keeps:
sta fst + 1
this:
jsr spush1
jmpnext:
jmp next
;---------------------------------------------------------------------
; ( 0 -- $0000) | ( n -- $FFFF) not zero at top ?
def_word "0#", "zeroq", 0
jsr spull1
lda fst + 1
ora fst + 0
beq isfalse ; is \0 ?
istrue:
lda #$FF
isfalse:
sta fst + 0
jmp keeps
;---------------------------------------------------------------------
; ( -- state ) a variable return an reference
def_word "s@", "state", 0
lda #<stat
sta fst + 0
lda #>stat
; jmp keeps ; uncomment if stats not in page $0
beq keeps ; always taken
;---------------------------------------------------------------------
def_word ";", "semis", FLAG_IMM
; update last, panic if colon not lead elsewhere
lda back + 0
sta last + 0
lda back + 1
sta last + 1
; stat is 'interpret'
lda #0
sta stat + 0
; compound words must ends with exit
finish:
lda #<exit
sta wrd + 0
lda #>exit
sta wrd + 1
jsr wcomma
; jmp next
bcc next ; always taken
;---------------------------------------------------------------------
def_word ":", "colon", 0
; save here, panic if semis not follow elsewhere
lda here + 0
sta back + 0
lda here + 1
sta back + 1
; stat is 'compile'
lda #1
sta stat + 0
@header:
; copy last into (here)
ldy #(last)
jsr comma
; get following token
jsr token
; copy it
ldy #0
@loop:
lda (tout), y
cmp #32 ; stops at space
beq @ends
sta (here), y
iny
bne @loop
@ends:
; update here
tya
ldx #(here)
jsr addwx
;~~~~~~~~
.ifdef use_DTC
; magic NOP (EA) JSR (20), at CFA cell
; magic = $EA20
magic = $20EA
; inserts the nop call
lda #<magic
sta wrd + 0
lda #>magic
jsr stawrd
; inserts the reference
lda #<nest
sta wrd + 0
lda #>nest
jsr stawrd
.endif
;~~~~~~~~
; done
; jmp next
bcc next ; always taken
;---------------------------------------------------------------------
; Thread Code Engine
;
; ipt is IP, wrd is W
;
; for reference:
;
; nest aka enter or docol,
; unnest aka exit or semis;
;
;---------------------------------------------------------------------
; ( -- )
def_word "exit", "exit", 0
unnest: ; exit
; pull, ipt = (rpt), rpt += 2
ldy #(ipt)
jsr rpull
next:
; wrd = (ipt) ; ipt += 2
ldx #(ipt)
ldy #(wrd)
jsr copyfrom
;~~~~~~~~
.ifdef use_DTC
pick:
jmp (wrd)
nest: ; enter
; push, *rp = ipt, rp -=2
ldy #(ipt)
jsr rpush
; pull (ip),
pla
sta ipt + 0
pla
sta ipt + 1
; 6502 trick: must increase return address
ldx #(ipt)
jsr incwx
bcc next
.else
pick:
; compare pages (MSBs)
lda wrd + 1
cmp #>ends + 1
bmi jump
nest: ; enter
; push, *rp = ipt, rp -=2
ldy #(ipt)
jsr rpush
lda wrd + 0
sta ipt + 0
lda wrd + 1
sta ipt + 1
jmp next
jump:
jmp (wrd)
.endif
;~~~~~~~~
;-----------------------------------------------------------------------
; BEWARE, MUST BE AT END! MINIMAL THREAD CODE DEPENDS ON IT!
ends:
;-----------------------------------------------------------------------
; anything above is not a primitive
;----------------------------------------------------------------------
|
agsb/milliForth-6502
| 82,783
|
refs/jonesforth.S
|
/* A sometimes minimal FORTH compiler and tutorial for Linux / i386 systems. -*- asm -*-
By Richard W.M. Jones <rich@annexia.org> http://annexia.org/forth
This is PUBLIC DOMAIN (see public domain release statement below).
$Id: jonesforth.S,v 1.47 2009-09-11 08:33:13 rich Exp $
gcc -m32 -nostdlib -static -Wl,-Ttext,0 -Wl,--build-id=none -o jonesforth jonesforth.S
*/
.set JONES_VERSION,47
/*
INTRODUCTION ----------------------------------------------------------------------
FORTH is one of those alien languages which most working programmers regard in the same
way as Haskell, LISP, and so on. Something so strange that they'd rather any thoughts
of it just go away so they can get on with writing this paying code. But that's wrong
and if you care at all about programming then you should at least understand all these
languages, even if you will never use them.
LISP is the ultimate high-level language, and features from LISP are being added every
decade to the more common languages. But FORTH is in some ways the ultimate in low level
programming. Out of the box it lacks features like dynamic memory management and even
strings. In fact, at its primitive level it lacks even basic concepts like IF-statements
and loops.
Why then would you want to learn FORTH? There are several very good reasons. First
and foremost, FORTH is minimal. You really can write a complete FORTH in, say, 2000
lines of code. I don't just mean a FORTH program, I mean a complete FORTH operating
system, environment and language. You could boot such a FORTH on a bare PC and it would
come up with a prompt where you could start doing useful work. The FORTH you have here
isn't minimal and uses a Linux process as its 'base PC' (both for the purposes of making
it a good tutorial). It's possible to completely understand the system. Who can say they
completely understand how Linux works, or gcc?
Secondly FORTH has a peculiar bootstrapping property. By that I mean that after writing
a little bit of assembly to talk to the hardware and implement a few primitives, all the
rest of the language and compiler is written in FORTH itself. Remember I said before
that FORTH lacked IF-statements and loops? Well of course it doesn't really because
such a lanuage would be useless, but my point was rather that IF-statements and loops are
written in FORTH itself.
Now of course this is common in other languages as well, and in those languages we call
them 'libraries'. For example in C, 'printf' is a library function written in C. But
in FORTH this goes way beyond mere libraries. Can you imagine writing C's 'if' in C?
And that brings me to my third reason: If you can write 'if' in FORTH, then why restrict
yourself to the usual if/while/for/switch constructs? You want a construct that iterates
over every other element in a list of numbers? You can add it to the language. What
about an operator which pulls in variables directly from a configuration file and makes
them available as FORTH variables? Or how about adding Makefile-like dependencies to
the language? No problem in FORTH. How about modifying the FORTH compiler to allow
complex inlining strategies -- simple. This concept isn't common in programming languages,
but it has a name (in fact two names): "macros" (by which I mean LISP-style macros, not
the lame C preprocessor) and "domain specific languages" (DSLs).
This tutorial isn't about learning FORTH as the language. I'll point you to some references
you should read if you're not familiar with using FORTH. This tutorial is about how to
write FORTH. In fact, until you understand how FORTH is written, you'll have only a very
superficial understanding of how to use it.
So if you're not familiar with FORTH or want to refresh your memory here are some online
references to read:
http://en.wikipedia.org/wiki/Forth_%28programming_language%29
http://galileo.phys.virginia.edu/classes/551.jvn.fall01/primer.htm
http://wiki.laptop.org/go/Forth_Lessons
http://www.albany.net/~hello/simple.htm
Here is another "Why FORTH?" essay: http://www.jwdt.com/~paysan/why-forth.html
Discussion and criticism of this FORTH here: http://lambda-the-ultimate.org/node/2452
ACKNOWLEDGEMENTS ----------------------------------------------------------------------
This code draws heavily on the design of LINA FORTH (http://home.hccnet.nl/a.w.m.van.der.horst/lina.html)
by Albert van der Horst. Any similarities in the code are probably not accidental.
Some parts of this FORTH are also based on this IOCCC entry from 1992:
http://ftp.funet.fi/pub/doc/IOCCC/1992/buzzard.2.design.
I was very proud when Sean Barrett, the original author of the IOCCC entry, commented in the LtU thread
http://lambda-the-ultimate.org/node/2452#comment-36818 about this FORTH.
And finally I'd like to acknowledge the (possibly forgotten?) authors of ARTIC FORTH because their
original program which I still have on original cassette tape kept nagging away at me all these years.
http://en.wikipedia.org/wiki/Artic_Software
PUBLIC DOMAIN ----------------------------------------------------------------------
I, the copyright holder of this work, hereby release it into the public domain. This applies worldwide.
In case this is not legally possible, I grant any entity the right to use this work for any purpose,
without any conditions, unless such conditions are required by law.
SETTING UP ----------------------------------------------------------------------
Let's get a few housekeeping things out of the way. Firstly because I need to draw lots of
ASCII-art diagrams to explain concepts, the best way to look at this is using a window which
uses a fixed width font and is at least this wide:
<------------------------------------------------------------------------------------------------------------------------>
Secondly make sure TABS are set to 8 characters. The following should be a vertical
line. If not, sort out your tabs.
|
|
|
Thirdly I assume that your screen is at least 50 characters high.
ASSEMBLING ----------------------------------------------------------------------
If you want to actually run this FORTH, rather than just read it, you will need Linux on an
i386. Linux because instead of programming directly to the hardware on a bare PC which I
could have done, I went for a simpler tutorial by assuming that the 'hardware' is a Linux
process with a few basic system calls (read, write and exit and that's about all). i386
is needed because I had to write the assembly for a processor, and i386 is by far the most
common. (Of course when I say 'i386', any 32- or 64-bit x86 processor will do. I'm compiling
this on a 64 bit AMD Opteron).
Again, to assemble this you will need gcc and gas (the GNU assembler). The commands to
assemble and run the code (save this file as 'jonesforth.S') are:
gcc -m32 -nostdlib -static -Wl,-Ttext,0 -Wl,--build-id=none -o jonesforth jonesforth.S
cat jonesforth.f - | ./jonesforth
If you want to run your own FORTH programs you can do:
cat jonesforth.f myprog.f | ./jonesforth
If you want to load your own FORTH code and then continue reading user commands, you can do:
cat jonesforth.f myfunctions.f - | ./jonesforth
ASSEMBLER ----------------------------------------------------------------------
(You can just skip to the next section -- you don't need to be able to read assembler to
follow this tutorial).
However if you do want to read the assembly code here are a few notes about gas (the GNU assembler):
(1) Register names are prefixed with '%', so %eax is the 32 bit i386 accumulator. The registers
available on i386 are: %eax, %ebx, %ecx, %edx, %esi, %edi, %ebp and %esp, and most of them
have special purposes.
(2) Add, mov, etc. take arguments in the form SRC,DEST. So mov %eax,%ecx moves %eax -> %ecx
(3) Constants are prefixed with '$', and you mustn't forget it! If you forget it then it
causes a read from memory instead, so:
mov $2,%eax moves number 2 into %eax
mov 2,%eax reads the 32 bit word from address 2 into %eax (ie. most likely a mistake)
(4) gas has a funky syntax for local labels, where '1f' (etc.) means label '1:' "forwards"
and '1b' (etc.) means label '1:' "backwards". Notice that these labels might be mistaken
for hex numbers (eg. you might confuse 1b with $0x1b).
(5) 'ja' is "jump if above", 'jb' for "jump if below", 'je' "jump if equal" etc.
(6) gas has a reasonably nice .macro syntax, and I use them a lot to make the code shorter and
less repetitive.
For more help reading the assembler, do "info gas" at the Linux prompt.
Now the tutorial starts in earnest.
THE DICTIONARY ----------------------------------------------------------------------
In FORTH as you will know, functions are called "words", and just as in other languages they
have a name and a definition. Here are two FORTH words:
: DOUBLE DUP + ; \ name is "DOUBLE", definition is "DUP +"
: QUADRUPLE DOUBLE DOUBLE ; \ name is "QUADRUPLE", definition is "DOUBLE DOUBLE"
Words, both built-in ones and ones which the programmer defines later, are stored in a dictionary
which is just a linked list of dictionary entries.
<--- DICTIONARY ENTRY (HEADER) ----------------------->
+------------------------+--------+---------- - - - - +----------- - - - -
| LINK POINTER | LENGTH/| NAME | DEFINITION
| | FLAGS | |
+--- (4 bytes) ----------+- byte -+- n bytes - - - - +----------- - - - -
I'll come to the definition of the word later. For now just look at the header. The first
4 bytes are the link pointer. This points back to the previous word in the dictionary, or, for
the first word in the dictionary it is just a NULL pointer. Then comes a length/flags byte.
The length of the word can be up to 31 characters (5 bits used) and the top three bits are used
for various flags which I'll come to later. This is followed by the name itself, and in this
implementation the name is rounded up to a multiple of 4 bytes by padding it with zero bytes.
That's just to ensure that the definition starts on a 32 bit boundary.
A FORTH variable called LATEST contains a pointer to the most recently defined word, in
other words, the head of this linked list.
DOUBLE and QUADRUPLE might look like this:
pointer to previous word
^
|
+--|------+---+---+---+---+---+---+---+---+------------- - - - -
| LINK | 6 | D | O | U | B | L | E | 0 | (definition ...)
+---------+---+---+---+---+---+---+---+---+------------- - - - -
^ len padding
|
+--|------+---+---+---+---+---+---+---+---+---+---+---+---+------------- - - - -
| LINK | 9 | Q | U | A | D | R | U | P | L | E | 0 | 0 | (definition ...)
+---------+---+---+---+---+---+---+---+---+---+---+---+---+------------- - - - -
^ len padding
|
|
LATEST
You should be able to see from this how you might implement functions to find a word in
the dictionary (just walk along the dictionary entries starting at LATEST and matching
the names until you either find a match or hit the NULL pointer at the end of the dictionary);
and add a word to the dictionary (create a new definition, set its LINK to LATEST, and set
LATEST to point to the new word). We'll see precisely these functions implemented in
assembly code later on.
One interesting consequence of using a linked list is that you can redefine words, and
a newer definition of a word overrides an older one. This is an important concept in
FORTH because it means that any word (even "built-in" or "standard" words) can be
overridden with a new definition, either to enhance it, to make it faster or even to
disable it. However because of the way that FORTH words get compiled, which you'll
understand below, words defined using the old definition of a word continue to use
the old definition. Only words defined after the new definition use the new definition.
DIRECT THREADED CODE ----------------------------------------------------------------------
Now we'll get to the really crucial bit in understanding FORTH, so go and get a cup of tea
or coffee and settle down. It's fair to say that if you don't understand this section, then you
won't "get" how FORTH works, and that would be a failure on my part for not explaining it well.
So if after reading this section a few times you don't understand it, please email me
(rich@annexia.org).
Let's talk first about what "threaded code" means. Imagine a peculiar version of C where
you are only allowed to call functions without arguments. (Don't worry for now that such a
language would be completely useless!) So in our peculiar C, code would look like this:
f ()
{
a ();
b ();
c ();
}
and so on. How would a function, say 'f' above, be compiled by a standard C compiler?
Probably into assembly code like this. On the right hand side I've written the actual
i386 machine code.
f:
CALL a E8 08 00 00 00
CALL b E8 1C 00 00 00
CALL c E8 2C 00 00 00
; ignore the return from the function for now
"E8" is the x86 machine code to "CALL" a function. In the first 20 years of computing
memory was hideously expensive and we might have worried about the wasted space being used
by the repeated "E8" bytes. We can save 20% in code size (and therefore, in expensive memory)
by compressing this into just:
08 00 00 00 Just the function addresses, without
1C 00 00 00 the CALL prefix.
2C 00 00 00
On a 16-bit machine like the ones which originally ran FORTH the savings are even greater - 33%.
[Historical note: If the execution model that FORTH uses looks strange from the following
paragraphs, then it was motivated entirely by the need to save memory on early computers.
This code compression isn't so important now when our machines have more memory in their L1
caches than those early computers had in total, but the execution model still has some
useful properties].
Of course this code won't run directly on the CPU any more. Instead we need to write an
interpreter which takes each set of bytes and calls it.
On an i386 machine it turns out that we can write this interpreter rather easily, in just
two assembly instructions which turn into just 3 bytes of machine code. Let's store the
pointer to the next word to execute in the %esi register:
08 00 00 00 <- We're executing this one now. %esi is the _next_ one to execute.
%esi -> 1C 00 00 00
2C 00 00 00
The all-important i386 instruction is called LODSL (or in Intel manuals, LODSW). It does
two things. Firstly it reads the memory at %esi into the accumulator (%eax). Secondly it
increments %esi by 4 bytes. So after LODSL, the situation now looks like this:
08 00 00 00 <- We're still executing this one
1C 00 00 00 <- %eax now contains this address (0x0000001C)
%esi -> 2C 00 00 00
Now we just need to jump to the address in %eax. This is again just a single x86 instruction
written JMP *(%eax). And after doing the jump, the situation looks like:
08 00 00 00
1C 00 00 00 <- Now we're executing this subroutine.
%esi -> 2C 00 00 00
To make this work, each subroutine is followed by the two instructions 'LODSL; JMP *(%eax)'
which literally make the jump to the next subroutine.
And that brings us to our first piece of actual code! Well, it's a macro.
*/
/* NEXT macro. */
.macro NEXT
lodsl
jmp *(%eax)
.endm
/* The macro is called NEXT. That's a FORTH-ism. It expands to those two instructions.
Every FORTH primitive that we write has to be ended by NEXT. Think of it kind of like
a return.
The above describes what is known as direct threaded code.
To sum up: We compress our function calls down to a list of addresses and use a somewhat
magical macro to act as a "jump to next function in the list". We also use one register (%esi)
to act as a kind of instruction pointer, pointing to the next function in the list.
I'll just give you a hint of what is to come by saying that a FORTH definition such as:
: QUADRUPLE DOUBLE DOUBLE ;
actually compiles (almost, not precisely but we'll see why in a moment) to a list of
function addresses for DOUBLE, DOUBLE and a special function called EXIT to finish off.
At this point, REALLY EAGLE-EYED ASSEMBLY EXPERTS are saying "JONES, YOU'VE MADE A MISTAKE!".
I lied about JMP *(%eax).
INDIRECT THREADED CODE ----------------------------------------------------------------------
It turns out that direct threaded code is interesting but only if you want to just execute
a list of functions written in assembly language. So QUADRUPLE would work only if DOUBLE
was an assembly language function. In the direct threaded code, QUADRUPLE would look like:
+------------------+
| addr of DOUBLE --------------------> (assembly code to do the double)
+------------------+ NEXT
%esi -> | addr of DOUBLE |
+------------------+
We can add an extra indirection to allow us to run both words written in assembly language
(primitives written for speed) and words written in FORTH themselves as lists of addresses.
The extra indirection is the reason for the brackets in JMP *(%eax).
Let's have a look at how QUADRUPLE and DOUBLE really look in FORTH:
: QUADRUPLE DOUBLE DOUBLE ;
+------------------+
| codeword | : DOUBLE DUP + ;
+------------------+
| addr of DOUBLE ---------------> +------------------+
+------------------+ | codeword |
| addr of DOUBLE | +------------------+
+------------------+ | addr of DUP --------------> +------------------+
| addr of EXIT | +------------------+ | codeword -------+
+------------------+ %esi -> | addr of + --------+ +------------------+ |
+------------------+ | | assembly to <-----+
| addr of EXIT | | | implement DUP |
+------------------+ | | .. |
| | .. |
| | NEXT |
| +------------------+
|
+-----> +------------------+
| codeword -------+
+------------------+ |
| assembly to <------+
| implement + |
| .. |
| .. |
| NEXT |
+------------------+
This is the part where you may need an extra cup of tea/coffee/favourite caffeinated
beverage. What has changed is that I've added an extra pointer to the beginning of
the definitions. In FORTH this is sometimes called the "codeword". The codeword is
a pointer to the interpreter to run the function. For primitives written in
assembly language, the "interpreter" just points to the actual assembly code itself.
They don't need interpreting, they just run.
In words written in FORTH (like QUADRUPLE and DOUBLE), the codeword points to an interpreter
function.
I'll show you the interpreter function shortly, but let's recall our indirect
JMP *(%eax) with the "extra" brackets. Take the case where we're executing DOUBLE
as shown, and DUP has been called. Note that %esi is pointing to the address of +
The assembly code for DUP eventually does a NEXT. That:
(1) reads the address of + into %eax %eax points to the codeword of +
(2) increments %esi by 4
(3) jumps to the indirect %eax jumps to the address in the codeword of +,
ie. the assembly code to implement +
+------------------+
| codeword |
+------------------+
| addr of DOUBLE ---------------> +------------------+
+------------------+ | codeword |
| addr of DOUBLE | +------------------+
+------------------+ | addr of DUP --------------> +------------------+
| addr of EXIT | +------------------+ | codeword -------+
+------------------+ | addr of + --------+ +------------------+ |
+------------------+ | | assembly to <-----+
%esi -> | addr of EXIT | | | implement DUP |
+------------------+ | | .. |
| | .. |
| | NEXT |
| +------------------+
|
+-----> +------------------+
| codeword -------+
+------------------+ |
now we're | assembly to <-----+
executing | implement + |
this | .. |
function | .. |
| NEXT |
+------------------+
So I hope that I've convinced you that NEXT does roughly what you'd expect. This is
indirect threaded code.
I've glossed over four things. I wonder if you can guess without reading on what they are?
.
.
.
My list of four things are: (1) What does "EXIT" do? (2) which is related to (1) is how do
you call into a function, ie. how does %esi start off pointing at part of QUADRUPLE, but
then point at part of DOUBLE. (3) What goes in the codeword for the words which are written
in FORTH? (4) How do you compile a function which does anything except call other functions
ie. a function which contains a number like : DOUBLE 2 * ; ?
THE INTERPRETER AND RETURN STACK ------------------------------------------------------------
Going at these in no particular order, let's talk about issues (3) and (2), the interpreter
and the return stack.
Words which are defined in FORTH need a codeword which points to a little bit of code to
give them a "helping hand" in life. They don't need much, but they do need what is known
as an "interpreter", although it doesn't really "interpret" in the same way that, say,
Java bytecode used to be interpreted (ie. slowly). This interpreter just sets up a few
machine registers so that the word can then execute at full speed using the indirect
threaded model above.
One of the things that needs to happen when QUADRUPLE calls DOUBLE is that we save the old
%esi ("instruction pointer") and create a new one pointing to the first word in DOUBLE.
Because we will need to restore the old %esi at the end of DOUBLE (this is, after all, like
a function call), we will need a stack to store these "return addresses" (old values of %esi).
As you will have seen in the background documentation, FORTH has two stacks, an ordinary
stack for parameters, and a return stack which is a bit more mysterious. But our return
stack is just the stack I talked about in the previous paragraph, used to save %esi when
calling from a FORTH word into another FORTH word.
In this FORTH, we are using the normal stack pointer (%esp) for the parameter stack.
We will use the i386's "other" stack pointer (%ebp, usually called the "frame pointer")
for our return stack.
I've got two macros which just wrap up the details of using %ebp for the return stack.
You use them as for example "PUSHRSP %eax" (push %eax on the return stack) or "POPRSP %ebx"
(pop top of return stack into %ebx).
*/
/* Macros to deal with the return stack. */
.macro PUSHRSP reg
lea -4(%ebp),%ebp // push reg on to return stack
movl \reg,(%ebp)
.endm
.macro POPRSP reg
mov (%ebp),\reg // pop top of return stack to reg
lea 4(%ebp),%ebp
.endm
/*
And with that we can now talk about the interpreter.
In FORTH the interpreter function is often called DOCOL (I think it means "DO COLON" because
all FORTH definitions start with a colon, as in : DOUBLE DUP + ;
The "interpreter" (it's not really "interpreting") just needs to push the old %esi on the
stack and set %esi to the first word in the definition. Remember that we jumped to the
function using JMP *(%eax)? Well a consequence of that is that conveniently %eax contains
the address of this codeword, so just by adding 4 to it we get the address of the first
data word. Finally after setting up %esi, it just does NEXT which causes that first word
to run.
*/
/* DOCOL - the interpreter! */
.text
.align 4
DOCOL:
PUSHRSP %esi // push %esi on to the return stack
addl $4,%eax // %eax points to codeword, so make
movl %eax,%esi // %esi point to first data word
NEXT
/*
Just to make this absolutely clear, let's see how DOCOL works when jumping from QUADRUPLE
into DOUBLE:
QUADRUPLE:
+------------------+
| codeword |
+------------------+ DOUBLE:
| addr of DOUBLE ---------------> +------------------+
+------------------+ %eax -> | addr of DOCOL |
%esi -> | addr of DOUBLE | +------------------+
+------------------+ | addr of DUP |
| addr of EXIT | +------------------+
+------------------+ | etc. |
First, the call to DOUBLE calls DOCOL (the codeword of DOUBLE). DOCOL does this: It
pushes the old %esi on the return stack. %eax points to the codeword of DOUBLE, so we
just add 4 on to it to get our new %esi:
QUADRUPLE:
+------------------+
| codeword |
+------------------+ DOUBLE:
| addr of DOUBLE ---------------> +------------------+
top of return +------------------+ %eax -> | addr of DOCOL |
stack points -> | addr of DOUBLE | + 4 = +------------------+
+------------------+ %esi -> | addr of DUP |
| addr of EXIT | +------------------+
+------------------+ | etc. |
Then we do NEXT, and because of the magic of threaded code that increments %esi again
and calls DUP.
Well, it seems to work.
One minor point here. Because DOCOL is the first bit of assembly actually to be defined
in this file (the others were just macros), and because I usually compile this code with the
text segment starting at address 0, DOCOL has address 0. So if you are disassembling the
code and see a word with a codeword of 0, you will immediately know that the word is
written in FORTH (it's not an assembler primitive) and so uses DOCOL as the interpreter.
STARTING UP ----------------------------------------------------------------------
Now let's get down to nuts and bolts. When we start the program we need to set up
a few things like the return stack. But as soon as we can, we want to jump into FORTH
code (albeit much of the "early" FORTH code will still need to be written as
assembly language primitives).
This is what the set up code does. Does a tiny bit of house-keeping, sets up the
separate return stack (NB: Linux gives us the ordinary parameter stack already), then
immediately jumps to a FORTH word called QUIT. Despite its name, QUIT doesn't quit
anything. It resets some internal state and starts reading and interpreting commands.
(The reason it is called QUIT is because you can call QUIT from your own FORTH code
to "quit" your program and go back to interpreting).
*/
/* Assembler entry point. */
.text
.globl _start
_start:
cld
mov %esp,var_S0 // Save the initial data stack pointer in FORTH variable S0.
mov $return_stack_top,%ebp // Initialise the return stack.
call set_up_data_segment
mov $cold_start,%esi // Initialise interpreter.
NEXT // Run interpreter!
.section .rodata
cold_start: // High-level code without a codeword.
.int QUIT
/*
BUILT-IN WORDS ----------------------------------------------------------------------
Remember our dictionary entries (headers)? Let's bring those together with the codeword
and data words to see how : DOUBLE DUP + ; really looks in memory.
pointer to previous word
^
|
+--|------+---+---+---+---+---+---+---+---+------------+------------+------------+------------+
| LINK | 6 | D | O | U | B | L | E | 0 | DOCOL | DUP | + | EXIT |
+---------+---+---+---+---+---+---+---+---+------------+--|---------+------------+------------+
^ len pad codeword |
| V
LINK in next word points to codeword of DUP
Initially we can't just write ": DOUBLE DUP + ;" (ie. that literal string) here because we
don't yet have anything to read the string, break it up at spaces, parse each word, etc. etc.
So instead we will have to define built-in words using the GNU assembler data constructors
(like .int, .byte, .string, .ascii and so on -- look them up in the gas info page if you are
unsure of them).
The long way would be:
.int <link to previous word>
.byte 6 // len
.ascii "DOUBLE" // string
.byte 0 // padding
DOUBLE: .int DOCOL // codeword
.int DUP // pointer to codeword of DUP
.int PLUS // pointer to codeword of +
.int EXIT // pointer to codeword of EXIT
That's going to get quite tedious rather quickly, so here I define an assembler macro
so that I can just write:
defword "DOUBLE",6,,DOUBLE
.int DUP,PLUS,EXIT
and I'll get exactly the same effect.
Don't worry too much about the exact implementation details of this macro - it's complicated!
*/
/* Flags - these are discussed later. */
.set F_IMMED,0x80
.set F_HIDDEN,0x20
.set F_LENMASK,0x1f // length mask
// Store the chain of links.
.set link,0
.macro defword name, namelen, flags=0, label
.section .rodata
.align 4
.globl name_\label
name_\label :
.int link // link
.set link,name_\label
.byte \flags+\namelen // flags + length byte
.ascii "\name" // the name
.align 4 // padding to next 4 byte boundary
.globl \label
\label :
.int DOCOL // codeword - the interpreter
// list of word pointers follow
.endm
/*
Similarly I want a way to write words written in assembly language. There will be quite a few
of these to start with because, well, everything has to start in assembly before there's
enough "infrastructure" to be able to start writing FORTH words, but also I want to define
some common FORTH words in assembly language for speed, even though I could write them in FORTH.
This is what DUP looks like in memory:
pointer to previous word
^
|
+--|------+---+---+---+---+------------+
| LINK | 3 | D | U | P | code_DUP ---------------------> points to the assembly
+---------+---+---+---+---+------------+ code used to write DUP,
^ len codeword which ends with NEXT.
|
LINK in next word
Again, for brevity in writing the header I'm going to write an assembler macro called defcode.
As with defword above, don't worry about the complicated details of the macro.
*/
.macro defcode name, namelen, flags=0, label
.section .rodata
.align 4
.globl name_\label
name_\label :
.int link // link
.set link,name_\label
.byte \flags+\namelen // flags + length byte
.ascii "\name" // the name
.align 4 // padding to next 4 byte boundary
.globl \label
\label :
.int code_\label // codeword
.text
//.align 4
.globl code_\label
code_\label : // assembler code follows
.endm
/*
Now some easy FORTH primitives. These are written in assembly for speed. If you understand
i386 assembly language then it is worth reading these. However if you don't understand assembly
you can skip the details.
*/
defcode "DROP",4,,DROP
pop %eax // drop top of stack
NEXT
defcode "SWAP",4,,SWAP
pop %eax // swap top two elements on stack
pop %ebx
push %eax
push %ebx
NEXT
defcode "DUP",3,,DUP
mov (%esp),%eax // duplicate top of stack
push %eax
NEXT
defcode "OVER",4,,OVER
mov 4(%esp),%eax // get the second element of stack
push %eax // and push it on top
NEXT
defcode "ROT",3,,ROT
pop %eax
pop %ebx
pop %ecx
push %ebx
push %eax
push %ecx
NEXT
defcode "-ROT",4,,NROT
pop %eax
pop %ebx
pop %ecx
push %eax
push %ecx
push %ebx
NEXT
defcode "2DROP",5,,TWODROP // drop top two elements of stack
pop %eax
pop %eax
NEXT
defcode "2DUP",4,,TWODUP // duplicate top two elements of stack
mov (%esp),%eax
mov 4(%esp),%ebx
push %ebx
push %eax
NEXT
defcode "2SWAP",5,,TWOSWAP // swap top two pairs of elements of stack
pop %eax
pop %ebx
pop %ecx
pop %edx
push %ebx
push %eax
push %edx
push %ecx
NEXT
defcode "?DUP",4,,QDUP // duplicate top of stack if non-zero
movl (%esp),%eax
test %eax,%eax
jz 1f
push %eax
1: NEXT
defcode "1+",2,,INCR
incl (%esp) // increment top of stack
NEXT
defcode "1-",2,,DECR
decl (%esp) // decrement top of stack
NEXT
defcode "4+",2,,INCR4
addl $4,(%esp) // add 4 to top of stack
NEXT
defcode "4-",2,,DECR4
subl $4,(%esp) // subtract 4 from top of stack
NEXT
defcode "+",1,,ADD
pop %eax // get top of stack
addl %eax,(%esp) // and add it to next word on stack
NEXT
defcode "-",1,,SUB
pop %eax // get top of stack
subl %eax,(%esp) // and subtract it from next word on stack
NEXT
defcode "*",1,,MUL
pop %eax
pop %ebx
imull %ebx,%eax
push %eax // ignore overflow
NEXT
/*
In this FORTH, only /MOD is primitive. Later we will define the / and MOD words in
terms of the primitive /MOD. The design of the i386 assembly instruction idiv which
leaves both quotient and remainder makes this the obvious choice.
*/
defcode "/MOD",4,,DIVMOD
xor %edx,%edx
pop %ebx
pop %eax
idivl %ebx
push %edx // push remainder
push %eax // push quotient
NEXT
/*
Lots of comparison operations like =, <, >, etc..
ANS FORTH says that the comparison words should return all (binary) 1's for
TRUE and all 0's for FALSE. However this is a bit of a strange convention
so this FORTH breaks it and returns the more normal (for C programmers ...)
1 meaning TRUE and 0 meaning FALSE.
*/
defcode "=",1,,EQU // top two words are equal?
pop %eax
pop %ebx
cmp %ebx,%eax
sete %al
movzbl %al,%eax
pushl %eax
NEXT
defcode "<>",2,,NEQU // top two words are not equal?
pop %eax
pop %ebx
cmp %ebx,%eax
setne %al
movzbl %al,%eax
pushl %eax
NEXT
defcode "<",1,,LT
pop %eax
pop %ebx
cmp %eax,%ebx
setl %al
movzbl %al,%eax
pushl %eax
NEXT
defcode ">",1,,GT
pop %eax
pop %ebx
cmp %eax,%ebx
setg %al
movzbl %al,%eax
pushl %eax
NEXT
defcode "<=",2,,LE
pop %eax
pop %ebx
cmp %eax,%ebx
setle %al
movzbl %al,%eax
pushl %eax
NEXT
defcode ">=",2,,GE
pop %eax
pop %ebx
cmp %eax,%ebx
setge %al
movzbl %al,%eax
pushl %eax
NEXT
defcode "0=",2,,ZEQU // top of stack equals 0?
pop %eax
test %eax,%eax
setz %al
movzbl %al,%eax
pushl %eax
NEXT
defcode "0<>",3,,ZNEQU // top of stack not 0?
pop %eax
test %eax,%eax
setnz %al
movzbl %al,%eax
pushl %eax
NEXT
defcode "0<",2,,ZLT // comparisons with 0
pop %eax
test %eax,%eax
setl %al
movzbl %al,%eax
pushl %eax
NEXT
defcode "0>",2,,ZGT
pop %eax
test %eax,%eax
setg %al
movzbl %al,%eax
pushl %eax
NEXT
defcode "0<=",3,,ZLE
pop %eax
test %eax,%eax
setle %al
movzbl %al,%eax
pushl %eax
NEXT
defcode "0>=",3,,ZGE
pop %eax
test %eax,%eax
setge %al
movzbl %al,%eax
pushl %eax
NEXT
defcode "AND",3,,AND // bitwise AND
pop %eax
andl %eax,(%esp)
NEXT
defcode "OR",2,,OR // bitwise OR
pop %eax
orl %eax,(%esp)
NEXT
defcode "XOR",3,,XOR // bitwise XOR
pop %eax
xorl %eax,(%esp)
NEXT
defcode "INVERT",6,,INVERT // this is the FORTH bitwise "NOT" function (cf. NEGATE and NOT)
notl (%esp)
NEXT
/*
RETURNING FROM FORTH WORDS ----------------------------------------------------------------------
Time to talk about what happens when we EXIT a function. In this diagram QUADRUPLE has called
DOUBLE, and DOUBLE is about to exit (look at where %esi is pointing):
QUADRUPLE
+------------------+
| codeword |
+------------------+ DOUBLE
| addr of DOUBLE ---------------> +------------------+
+------------------+ | codeword |
| addr of DOUBLE | +------------------+
+------------------+ | addr of DUP |
| addr of EXIT | +------------------+
+------------------+ | addr of + |
+------------------+
%esi -> | addr of EXIT |
+------------------+
What happens when the + function does NEXT? Well, the following code is executed.
*/
defcode "EXIT",4,,EXIT
POPRSP %esi // pop return stack into %esi
NEXT
/*
EXIT gets the old %esi which we saved from before on the return stack, and puts it in %esi.
So after this (but just before NEXT) we get:
QUADRUPLE
+------------------+
| codeword |
+------------------+ DOUBLE
| addr of DOUBLE ---------------> +------------------+
+------------------+ | codeword |
%esi -> | addr of DOUBLE | +------------------+
+------------------+ | addr of DUP |
| addr of EXIT | +------------------+
+------------------+ | addr of + |
+------------------+
| addr of EXIT |
+------------------+
And NEXT just completes the job by, well, in this case just by calling DOUBLE again :-)
LITERALS ----------------------------------------------------------------------
The final point I "glossed over" before was how to deal with functions that do anything
apart from calling other functions. For example, suppose that DOUBLE was defined like this:
: DOUBLE 2 * ;
It does the same thing, but how do we compile it since it contains the literal 2? One way
would be to have a function called "2" (which you'd have to write in assembler), but you'd need
a function for every single literal that you wanted to use.
FORTH solves this by compiling the function using a special word called LIT:
+---------------------------+-------+-------+-------+-------+-------+
| (usual header of DOUBLE) | DOCOL | LIT | 2 | * | EXIT |
+---------------------------+-------+-------+-------+-------+-------+
LIT is executed in the normal way, but what it does next is definitely not normal. It
looks at %esi (which now points to the number 2), grabs it, pushes it on the stack, then
manipulates %esi in order to skip the number as if it had never been there.
What's neat is that the whole grab/manipulate can be done using a single byte single
i386 instruction, our old friend LODSL. Rather than me drawing more ASCII-art diagrams,
see if you can find out how LIT works:
*/
defcode "LIT",3,,LIT
// %esi points to the next command, but in this case it points to the next
// literal 32 bit integer. Get that literal into %eax and increment %esi.
// On x86, it's a convenient single byte instruction! (cf. NEXT macro)
lodsl
push %eax // push the literal number on to stack
NEXT
/*
MEMORY ----------------------------------------------------------------------
An important point about FORTH is that it gives you direct access to the lowest levels
of the machine. Manipulating memory directly is done frequently in FORTH, and these are
the primitive words for doing it.
*/
defcode "!",1,,STORE
pop %ebx // address to store at
pop %eax // data to store there
mov %eax,(%ebx) // store it
NEXT
defcode "@",1,,FETCH
pop %ebx // address to fetch
mov (%ebx),%eax // fetch it
push %eax // push value onto stack
NEXT
defcode "+!",2,,ADDSTORE
pop %ebx // address
pop %eax // the amount to add
addl %eax,(%ebx) // add it
NEXT
defcode "-!",2,,SUBSTORE
pop %ebx // address
pop %eax // the amount to subtract
subl %eax,(%ebx) // add it
NEXT
/*
! and @ (STORE and FETCH) store 32-bit words. It's also useful to be able to read and write bytes
so we also define standard words C@ and C!.
Byte-oriented operations only work on architectures which permit them (i386 is one of those).
*/
defcode "C!",2,,STOREBYTE
pop %ebx // address to store at
pop %eax // data to store there
movb %al,(%ebx) // store it
NEXT
defcode "C@",2,,FETCHBYTE
pop %ebx // address to fetch
xor %eax,%eax
movb (%ebx),%al // fetch it
push %eax // push value onto stack
NEXT
/* C@C! is a useful byte copy primitive. */
defcode "C@C!",4,,CCOPY
movl 4(%esp),%ebx // source address
movb (%ebx),%al // get source character
pop %edi // destination address
stosb // copy to destination
push %edi // increment destination address
incl 4(%esp) // increment source address
NEXT
/* and CMOVE is a block copy operation. */
defcode "CMOVE",5,,CMOVE
mov %esi,%edx // preserve %esi
pop %ecx // length
pop %edi // destination address
pop %esi // source address
rep movsb // copy source to destination
mov %edx,%esi // restore %esi
NEXT
/*
BUILT-IN VARIABLES ----------------------------------------------------------------------
These are some built-in variables and related standard FORTH words. Of these, the only one that we
have discussed so far was LATEST, which points to the last (most recently defined) word in the
FORTH dictionary. LATEST is also a FORTH word which pushes the address of LATEST (the variable)
on to the stack, so you can read or write it using @ and ! operators. For example, to print
the current value of LATEST (and this can apply to any FORTH variable) you would do:
LATEST @ . CR
To make defining variables shorter, I'm using a macro called defvar, similar to defword and
defcode above. (In fact the defvar macro uses defcode to do the dictionary header).
*/
.macro defvar name, namelen, flags=0, label, initial=0
defcode \name,\namelen,\flags,\label
push $var_\name
NEXT
.data
.align 4
var_\name :
.int \initial
.endm
/*
The built-in variables are:
STATE Is the interpreter executing code (0) or compiling a word (non-zero)?
LATEST Points to the latest (most recently defined) word in the dictionary.
HERE Points to the next free byte of memory. When compiling, compiled words go here.
S0 Stores the address of the top of the parameter stack.
BASE The current base for printing and reading numbers.
*/
defvar "STATE",5,,STATE
defvar "HERE",4,,HERE
defvar "LATEST",6,,LATEST,name_SYSCALL0 // SYSCALL0 must be last in built-in dictionary
defvar "S0",2,,SZ
defvar "BASE",4,,BASE,10
/*
BUILT-IN CONSTANTS ----------------------------------------------------------------------
It's also useful to expose a few constants to FORTH. When the word is executed it pushes a
constant value on the stack.
The built-in constants are:
VERSION Is the current version of this FORTH.
R0 The address of the top of the return stack.
DOCOL Pointer to DOCOL.
F_IMMED The IMMEDIATE flag's actual value.
F_HIDDEN The HIDDEN flag's actual value.
F_LENMASK The length mask in the flags/len byte.
SYS_* and the numeric codes of various Linux syscalls (from <asm/unistd.h>)
*/
//#include <asm-i386/unistd.h> // you might need this instead
#include <asm/unistd.h>
.macro defconst name, namelen, flags=0, label, value
defcode \name,\namelen,\flags,\label
push $\value
NEXT
.endm
defconst "VERSION",7,,VERSION,JONES_VERSION
defconst "R0",2,,RZ,return_stack_top
defconst "DOCOL",5,,__DOCOL,DOCOL
defconst "F_IMMED",7,,__F_IMMED,F_IMMED
defconst "F_HIDDEN",8,,__F_HIDDEN,F_HIDDEN
defconst "F_LENMASK",9,,__F_LENMASK,F_LENMASK
defconst "SYS_EXIT",8,,SYS_EXIT,__NR_exit
defconst "SYS_OPEN",8,,SYS_OPEN,__NR_open
defconst "SYS_CLOSE",9,,SYS_CLOSE,__NR_close
defconst "SYS_READ",8,,SYS_READ,__NR_read
defconst "SYS_WRITE",9,,SYS_WRITE,__NR_write
defconst "SYS_CREAT",9,,SYS_CREAT,__NR_creat
defconst "SYS_BRK",7,,SYS_BRK,__NR_brk
defconst "O_RDONLY",8,,__O_RDONLY,0
defconst "O_WRONLY",8,,__O_WRONLY,1
defconst "O_RDWR",6,,__O_RDWR,2
defconst "O_CREAT",7,,__O_CREAT,0100
defconst "O_EXCL",6,,__O_EXCL,0200
defconst "O_TRUNC",7,,__O_TRUNC,01000
defconst "O_APPEND",8,,__O_APPEND,02000
defconst "O_NONBLOCK",10,,__O_NONBLOCK,04000
/*
RETURN STACK ----------------------------------------------------------------------
These words allow you to access the return stack. Recall that the register %ebp always points to
the top of the return stack.
*/
defcode ">R",2,,TOR
pop %eax // pop parameter stack into %eax
PUSHRSP %eax // push it on to the return stack
NEXT
defcode "R>",2,,FROMR
POPRSP %eax // pop return stack on to %eax
push %eax // and push on to parameter stack
NEXT
defcode "RSP@",4,,RSPFETCH
push %ebp
NEXT
defcode "RSP!",4,,RSPSTORE
pop %ebp
NEXT
defcode "RDROP",5,,RDROP
addl $4,%ebp // pop return stack and throw away
NEXT
/*
PARAMETER (DATA) STACK ----------------------------------------------------------------------
These functions allow you to manipulate the parameter stack. Recall that Linux sets up the parameter
stack for us, and it is accessed through %esp.
*/
defcode "DSP@",4,,DSPFETCH
mov %esp,%eax
push %eax
NEXT
defcode "DSP!",4,,DSPSTORE
pop %esp
NEXT
/*
INPUT AND OUTPUT ----------------------------------------------------------------------
These are our first really meaty/complicated FORTH primitives. I have chosen to write them in
assembler, but surprisingly in "real" FORTH implementations these are often written in terms
of more fundamental FORTH primitives. I chose to avoid that because I think that just obscures
the implementation. After all, you may not understand assembler but you can just think of it
as an opaque block of code that does what it says.
Let's discuss input first.
The FORTH word KEY reads the next byte from stdin (and pushes it on the parameter stack).
So if KEY is called and someone hits the space key, then the number 32 (ASCII code of space)
is pushed on the stack.
In FORTH there is no distinction between reading code and reading input. We might be reading
and compiling code, we might be reading words to execute, we might be asking for the user
to type their name -- ultimately it all comes in through KEY.
The implementation of KEY uses an input buffer of a certain size (defined at the end of this
file). It calls the Linux read(2) system call to fill this buffer and tracks its position
in the buffer using a couple of variables, and if it runs out of input buffer then it refills
it automatically. The other thing that KEY does is if it detects that stdin has closed, it
exits the program, which is why when you hit ^D the FORTH system cleanly exits.
buffer bufftop
| |
V V
+-------------------------------+--------------------------------------+
| INPUT READ FROM STDIN ....... | unused part of the buffer |
+-------------------------------+--------------------------------------+
^
|
currkey (next character to read)
<---------------------- BUFFER_SIZE (4096 bytes) ---------------------->
*/
defcode "KEY",3,,KEY
call _KEY
push %eax // push return value on stack
NEXT
_KEY:
mov (currkey),%ebx
cmp (bufftop),%ebx
jge 1f // exhausted the input buffer?
xor %eax,%eax
mov (%ebx),%al // get next key from input buffer
inc %ebx
mov %ebx,(currkey) // increment currkey
ret
1: // Out of input; use read(2) to fetch more input from stdin.
xor %ebx,%ebx // 1st param: stdin
mov $buffer,%ecx // 2nd param: buffer
mov %ecx,currkey
mov $BUFFER_SIZE,%edx // 3rd param: max length
mov $__NR_read,%eax // syscall: read
int $0x80
test %eax,%eax // If %eax <= 0, then exit.
jbe 2f
addl %eax,%ecx // buffer+%eax = bufftop
mov %ecx,bufftop
jmp _KEY
2: // Error or end of input: exit the program.
xor %ebx,%ebx
mov $__NR_exit,%eax // syscall: exit
int $0x80
.data
.align 4
currkey:
.int buffer // Current place in input buffer (next character to read).
bufftop:
.int buffer // Last valid data in input buffer + 1.
/*
By contrast, output is much simpler. The FORTH word EMIT writes out a single byte to stdout.
This implementation just uses the write system call. No attempt is made to buffer output, but
it would be a good exercise to add it.
*/
defcode "EMIT",4,,EMIT
pop %eax
call _EMIT
NEXT
_EMIT:
mov $1,%ebx // 1st param: stdout
// write needs the address of the byte to write
mov %al,emit_scratch
mov $emit_scratch,%ecx // 2nd param: address
mov $1,%edx // 3rd param: nbytes = 1
mov $__NR_write,%eax // write syscall
int $0x80
ret
.data // NB: easier to fit in the .data section
emit_scratch:
.space 1 // scratch used by EMIT
/*
Back to input, WORD is a FORTH word which reads the next full word of input.
What it does in detail is that it first skips any blanks (spaces, tabs, newlines and so on).
Then it calls KEY to read characters into an internal buffer until it hits a blank. Then it
calculates the length of the word it read and returns the address and the length as
two words on the stack (with the length at the top of stack).
Notice that WORD has a single internal buffer which it overwrites each time (rather like
a static C string). Also notice that WORD's internal buffer is just 32 bytes long and
there is NO checking for overflow. 31 bytes happens to be the maximum length of a
FORTH word that we support, and that is what WORD is used for: to read FORTH words when
we are compiling and executing code. The returned strings are not NUL-terminated.
Start address+length is the normal way to represent strings in FORTH (not ending in an
ASCII NUL character as in C), and so FORTH strings can contain any character including NULs
and can be any length.
WORD is not suitable for just reading strings (eg. user input) because of all the above
peculiarities and limitations.
Note that when executing, you'll see:
WORD FOO
which puts "FOO" and length 3 on the stack, but when compiling:
: BAR WORD FOO ;
is an error (or at least it doesn't do what you might expect). Later we'll talk about compiling
and immediate mode, and you'll understand why.
*/
defcode "WORD",4,,WORD
call _WORD
push %edi // push base address
push %ecx // push length
NEXT
_WORD:
/* Search for first non-blank character. Also skip \ comments. */
1:
call _KEY // get next key, returned in %eax
cmpb $'\\',%al // start of a comment?
je 3f // if so, skip the comment
cmpb $' ',%al
jbe 1b // if so, keep looking
/* Search for the end of the word, storing chars as we go. */
mov $word_buffer,%edi // pointer to return buffer
2:
stosb // add character to return buffer
call _KEY // get next key, returned in %al
cmpb $' ',%al // is blank?
ja 2b // if not, keep looping
/* Return the word (well, the static buffer) and length. */
sub $word_buffer,%edi
mov %edi,%ecx // return length of the word
mov $word_buffer,%edi // return address of the word
ret
/* Code to skip \ comments to end of the current line. */
3:
call _KEY
cmpb $'\n',%al // end of line yet?
jne 3b
jmp 1b
.data // NB: easier to fit in the .data section
// A static buffer where WORD returns. Subsequent calls
// overwrite this buffer. Maximum word length is 32 chars.
word_buffer:
.space 32
/*
As well as reading in words we'll need to read in numbers and for that we are using a function
called NUMBER. This parses a numeric string such as one returned by WORD and pushes the
number on the parameter stack.
The function uses the variable BASE as the base (radix) for conversion, so for example if
BASE is 2 then we expect a binary number. Normally BASE is 10.
If the word starts with a '-' character then the returned value is negative.
If the string can't be parsed as a number (or contains characters outside the current BASE)
then we need to return an error indication. So NUMBER actually returns two items on the stack.
At the top of stack we return the number of unconverted characters (ie. if 0 then all characters
were converted, so there is no error). Second from top of stack is the parsed number or a
partial value if there was an error.
*/
defcode "NUMBER",6,,NUMBER
pop %ecx // length of string
pop %edi // start address of string
call _NUMBER
push %eax // parsed number
push %ecx // number of unparsed characters (0 = no error)
NEXT
_NUMBER:
xor %eax,%eax
xor %ebx,%ebx
test %ecx,%ecx // trying to parse a zero-length string is an error, but will return 0.
jz 5f
movl var_BASE,%edx // get BASE (in %dl)
// Check if first character is '-'.
movb (%edi),%bl // %bl = first character in string
inc %edi
push %eax // push 0 on stack
cmpb $'-',%bl // negative number?
jnz 2f
pop %eax
push %ebx // push <> 0 on stack, indicating negative
dec %ecx
jnz 1f
pop %ebx // error: string is only '-'.
movl $1,%ecx
ret
// Loop reading digits.
1: imull %edx,%eax // %eax *= BASE
movb (%edi),%bl // %bl = next character in string
inc %edi
// Convert 0-9, A-Z to a number 0-35.
2: subb $'0',%bl // < '0'?
jb 4f
cmp $10,%bl // <= '9'?
jb 3f
subb $17,%bl // < 'A'? (17 is 'A'-'0')
jb 4f
addb $10,%bl
3: cmp %dl,%bl // >= BASE?
jge 4f
// OK, so add it to %eax and loop.
add %ebx,%eax
dec %ecx
jnz 1b
// Negate the result if first character was '-' (saved on the stack).
4: pop %ebx
test %ebx,%ebx
jz 5f
neg %eax
5: ret
/*
DICTIONARY LOOK UPS ----------------------------------------------------------------------
We're building up to our prelude on how FORTH code is compiled, but first we need yet more infrastructure.
The FORTH word FIND takes a string (a word as parsed by WORD -- see above) and looks it up in the
dictionary. What it actually returns is the address of the dictionary header, if it finds it,
or 0 if it didn't.
So if DOUBLE is defined in the dictionary, then WORD DOUBLE FIND returns the following pointer:
pointer to this
|
|
V
+---------+---+---+---+---+---+---+---+---+------------+------------+------------+------------+
| LINK | 6 | D | O | U | B | L | E | 0 | DOCOL | DUP | + | EXIT |
+---------+---+---+---+---+---+---+---+---+------------+------------+------------+------------+
See also >CFA and >DFA.
FIND doesn't find dictionary entries which are flagged as HIDDEN. See below for why.
*/
defcode "FIND",4,,FIND
pop %ecx // %ecx = length
pop %edi // %edi = address
call _FIND
push %eax // %eax = address of dictionary entry (or NULL)
NEXT
_FIND:
push %esi // Save %esi so we can use it in string comparison.
// Now we start searching backwards through the dictionary for this word.
mov var_LATEST,%edx // LATEST points to name header of the latest word in the dictionary
1: test %edx,%edx // NULL pointer? (end of the linked list)
je 4f
// Compare the length expected and the length of the word.
// Note that if the F_HIDDEN flag is set on the word, then by a bit of trickery
// this won't pick the word (the length will appear to be wrong).
xor %eax,%eax
movb 4(%edx),%al // %al = flags+length field
andb $(F_HIDDEN|F_LENMASK),%al // %al = name length
cmpb %cl,%al // Length is the same?
jne 2f
// Compare the strings in detail.
push %ecx // Save the length
push %edi // Save the address (repe cmpsb will move this pointer)
lea 5(%edx),%esi // Dictionary string we are checking against.
repe cmpsb // Compare the strings.
pop %edi
pop %ecx
jne 2f // Not the same.
// The strings are the same - return the header pointer in %eax
pop %esi
mov %edx,%eax
ret
2: mov (%edx),%edx // Move back through the link field to the previous word
jmp 1b // .. and loop.
4: // Not found.
pop %esi
xor %eax,%eax // Return zero to indicate not found.
ret
/*
FIND returns the dictionary pointer, but when compiling we need the codeword pointer (recall
that FORTH definitions are compiled into lists of codeword pointers). The standard FORTH
word >CFA turns a dictionary pointer into a codeword pointer.
The example below shows the result of:
WORD DOUBLE FIND >CFA
FIND returns a pointer to this
| >CFA converts it to a pointer to this
| |
V V
+---------+---+---+---+---+---+---+---+---+------------+------------+------------+------------+
| LINK | 6 | D | O | U | B | L | E | 0 | DOCOL | DUP | + | EXIT |
+---------+---+---+---+---+---+---+---+---+------------+------------+------------+------------+
codeword
Notes:
Because names vary in length, this isn't just a simple increment.
In this FORTH you cannot easily turn a codeword pointer back into a dictionary entry pointer, but
that is not true in most FORTH implementations where they store a back pointer in the definition
(with an obvious memory/complexity cost). The reason they do this is that it is useful to be
able to go backwards (codeword -> dictionary entry) in order to decompile FORTH definitions
quickly.
What does CFA stand for? My best guess is "Code Field Address".
*/
defcode ">CFA",4,,TCFA
pop %edi
call _TCFA
push %edi
NEXT
_TCFA:
xor %eax,%eax
add $4,%edi // Skip link pointer.
movb (%edi),%al // Load flags+len into %al.
inc %edi // Skip flags+len byte.
andb $F_LENMASK,%al // Just the length, not the flags.
add %eax,%edi // Skip the name.
addl $3,%edi // The codeword is 4-byte aligned.
andl $~3,%edi
ret
/*
Related to >CFA is >DFA which takes a dictionary entry address as returned by FIND and
returns a pointer to the first data field.
FIND returns a pointer to this
| >CFA converts it to a pointer to this
| |
| | >DFA converts it to a pointer to this
| | |
V V V
+---------+---+---+---+---+---+---+---+---+------------+------------+------------+------------+
| LINK | 6 | D | O | U | B | L | E | 0 | DOCOL | DUP | + | EXIT |
+---------+---+---+---+---+---+---+---+---+------------+------------+------------+------------+
codeword
(Note to those following the source of FIG-FORTH / ciforth: My >DFA definition is
different from theirs, because they have an extra indirection).
You can see that >DFA is easily defined in FORTH just by adding 4 to the result of >CFA.
*/
defword ">DFA",4,,TDFA
.int TCFA // >CFA (get code field address)
.int INCR4 // 4+ (add 4 to it to get to next word)
.int EXIT // EXIT (return from FORTH word)
/*
COMPILING ----------------------------------------------------------------------
Now we'll talk about how FORTH compiles words. Recall that a word definition looks like this:
: DOUBLE DUP + ;
and we have to turn this into:
pointer to previous word
^
|
+--|------+---+---+---+---+---+---+---+---+------------+------------+------------+------------+
| LINK | 6 | D | O | U | B | L | E | 0 | DOCOL | DUP | + | EXIT |
+---------+---+---+---+---+---+---+---+---+------------+--|---------+------------+------------+
^ len pad codeword |
| V
LATEST points here points to codeword of DUP
There are several problems to solve. Where to put the new word? How do we read words? How
do we define the words : (COLON) and ; (SEMICOLON)?
FORTH solves this rather elegantly and as you might expect in a very low-level way which
allows you to change how the compiler works on your own code.
FORTH has an INTERPRET function (a true interpreter this time, not DOCOL) which runs in a
loop, reading words (using WORD), looking them up (using FIND), turning them into codeword
pointers (using >CFA) and deciding what to do with them.
What it does depends on the mode of the interpreter (in variable STATE).
When STATE is zero, the interpreter just runs each word as it looks them up. This is known as
immediate mode.
The interesting stuff happens when STATE is non-zero -- compiling mode. In this mode the
interpreter appends the codeword pointer to user memory (the HERE variable points to the next
free byte of user memory -- see DATA SEGMENT section below).
So you may be able to see how we could define : (COLON). The general plan is:
(1) Use WORD to read the name of the function being defined.
(2) Construct the dictionary entry -- just the header part -- in user memory:
pointer to previous word (from LATEST) +-- Afterwards, HERE points here, where
^ | the interpreter will start appending
| V codewords.
+--|------+---+---+---+---+---+---+---+---+------------+
| LINK | 6 | D | O | U | B | L | E | 0 | DOCOL |
+---------+---+---+---+---+---+---+---+---+------------+
len pad codeword
(3) Set LATEST to point to the newly defined word, ...
(4) .. and most importantly leave HERE pointing just after the new codeword. This is where
the interpreter will append codewords.
(5) Set STATE to 1. This goes into compile mode so the interpreter starts appending codewords to
our partially-formed header.
After : has run, our input is here:
: DOUBLE DUP + ;
^
|
Next byte returned by KEY will be the 'D' character of DUP
so the interpreter (now it's in compile mode, so I guess it's really the compiler) reads "DUP",
looks it up in the dictionary, gets its codeword pointer, and appends it:
+-- HERE updated to point here.
|
V
+---------+---+---+---+---+---+---+---+---+------------+------------+
| LINK | 6 | D | O | U | B | L | E | 0 | DOCOL | DUP |
+---------+---+---+---+---+---+---+---+---+------------+------------+
len pad codeword
Next we read +, get the codeword pointer, and append it:
+-- HERE updated to point here.
|
V
+---------+---+---+---+---+---+---+---+---+------------+------------+------------+
| LINK | 6 | D | O | U | B | L | E | 0 | DOCOL | DUP | + |
+---------+---+---+---+---+---+---+---+---+------------+------------+------------+
len pad codeword
The issue is what happens next. Obviously what we _don't_ want to happen is that we
read ";" and compile it and go on compiling everything afterwards.
At this point, FORTH uses a trick. Remember the length byte in the dictionary definition
isn't just a plain length byte, but can also contain flags. One flag is called the
IMMEDIATE flag (F_IMMED in this code). If a word in the dictionary is flagged as
IMMEDIATE then the interpreter runs it immediately _even if it's in compile mode_.
This is how the word ; (SEMICOLON) works -- as a word flagged in the dictionary as IMMEDIATE.
And all it does is append the codeword for EXIT on to the current definition and switch
back to immediate mode (set STATE back to 0). Shortly we'll see the actual definition
of ; and we'll see that it's really a very simple definition, declared IMMEDIATE.
After the interpreter reads ; and executes it 'immediately', we get this:
+---------+---+---+---+---+---+---+---+---+------------+------------+------------+------------+
| LINK | 6 | D | O | U | B | L | E | 0 | DOCOL | DUP | + | EXIT |
+---------+---+---+---+---+---+---+---+---+------------+------------+------------+------------+
len pad codeword ^
|
HERE
STATE is set to 0.
And that's it, job done, our new definition is compiled, and we're back in immediate mode
just reading and executing words, perhaps including a call to test our new word DOUBLE.
The only last wrinkle in this is that while our word was being compiled, it was in a
half-finished state. We certainly wouldn't want DOUBLE to be called somehow during
this time. There are several ways to stop this from happening, but in FORTH what we
do is flag the word with the HIDDEN flag (F_HIDDEN in this code) just while it is
being compiled. This prevents FIND from finding it, and thus in theory stops any
chance of it being called.
The above explains how compiling, : (COLON) and ; (SEMICOLON) works and in a moment I'm
going to define them. The : (COLON) function can be made a little bit more general by writing
it in two parts. The first part, called CREATE, makes just the header:
+-- Afterwards, HERE points here.
|
V
+---------+---+---+---+---+---+---+---+---+
| LINK | 6 | D | O | U | B | L | E | 0 |
+---------+---+---+---+---+---+---+---+---+
len pad
and the second part, the actual definition of : (COLON), calls CREATE and appends the
DOCOL codeword, so leaving:
+-- Afterwards, HERE points here.
|
V
+---------+---+---+---+---+---+---+---+---+------------+
| LINK | 6 | D | O | U | B | L | E | 0 | DOCOL |
+---------+---+---+---+---+---+---+---+---+------------+
len pad codeword
CREATE is a standard FORTH word and the advantage of this split is that we can reuse it to
create other types of words (not just ones which contain code, but words which contain variables,
constants and other data).
*/
defcode "CREATE",6,,CREATE
// Get the name length and address.
pop %ecx // %ecx = length
pop %ebx // %ebx = address of name
// Link pointer.
movl var_HERE,%edi // %edi is the address of the header
movl var_LATEST,%eax // Get link pointer
stosl // and store it in the header.
// Length byte and the word itself.
mov %cl,%al // Get the length.
stosb // Store the length/flags byte.
push %esi
mov %ebx,%esi // %esi = word
rep movsb // Copy the word
pop %esi
addl $3,%edi // Align to next 4 byte boundary.
andl $~3,%edi
// Update LATEST and HERE.
movl var_HERE,%eax
movl %eax,var_LATEST
movl %edi,var_HERE
NEXT
/*
Because I want to define : (COLON) in FORTH, not assembler, we need a few more FORTH words
to use.
The first is , (COMMA) which is a standard FORTH word which appends a 32 bit integer to the user
memory pointed to by HERE, and adds 4 to HERE. So the action of , (COMMA) is:
previous value of HERE
|
V
+---------+---+---+---+---+---+---+---+---+-- - - - - --+------------+
| LINK | 6 | D | O | U | B | L | E | 0 | | <data> |
+---------+---+---+---+---+---+---+---+---+-- - - - - --+------------+
len pad ^
|
new value of HERE
and <data> is whatever 32 bit integer was at the top of the stack.
, (COMMA) is quite a fundamental operation when compiling. It is used to append codewords
to the current word that is being compiled.
*/
defcode ",",1,,COMMA
pop %eax // Code pointer to store.
call _COMMA
NEXT
_COMMA:
movl var_HERE,%edi // HERE
stosl // Store it.
movl %edi,var_HERE // Update HERE (incremented)
ret
/*
Our definitions of : (COLON) and ; (SEMICOLON) will need to switch to and from compile mode.
Immediate mode vs. compile mode is stored in the global variable STATE, and by updating this
variable we can switch between the two modes.
For various reasons which may become apparent later, FORTH defines two standard words called
[ and ] (LBRAC and RBRAC) which switch between modes:
Word Assembler Action Effect
[ LBRAC STATE := 0 Switch to immediate mode.
] RBRAC STATE := 1 Switch to compile mode.
[ (LBRAC) is an IMMEDIATE word. The reason is as follows: If we are in compile mode and the
interpreter saw [ then it would compile it rather than running it. We would never be able to
switch back to immediate mode! So we flag the word as IMMEDIATE so that even in compile mode
the word runs immediately, switching us back to immediate mode.
*/
defcode "[",1,F_IMMED,LBRAC
xor %eax,%eax
movl %eax,var_STATE // Set STATE to 0.
NEXT
defcode "]",1,,RBRAC
movl $1,var_STATE // Set STATE to 1.
NEXT
/*
Now we can define : (COLON) using CREATE. It just calls CREATE, appends DOCOL (the codeword), sets
the word HIDDEN and goes into compile mode.
*/
defword ":",1,,COLON
.int WORD // Get the name of the new word
.int CREATE // CREATE the dictionary entry / header
.int LIT, DOCOL, COMMA // Append DOCOL (the codeword).
.int LATEST, FETCH, HIDDEN // Make the word hidden (see below for definition).
.int RBRAC // Go into compile mode.
.int EXIT // Return from the function.
/*
; (SEMICOLON) is also elegantly simple. Notice the F_IMMED flag.
*/
defword ";",1,F_IMMED,SEMICOLON
.int LIT, EXIT, COMMA // Append EXIT (so the word will return).
.int LATEST, FETCH, HIDDEN // Toggle hidden flag -- unhide the word (see below for definition).
.int LBRAC // Go back to IMMEDIATE mode.
.int EXIT // Return from the function.
/*
EXTENDING THE COMPILER ----------------------------------------------------------------------
Words flagged with IMMEDIATE (F_IMMED) aren't just for the FORTH compiler to use. You can define
your own IMMEDIATE words too, and this is a crucial aspect when extending basic FORTH, because
it allows you in effect to extend the compiler itself. Does gcc let you do that?
Standard FORTH words like IF, WHILE, ." and so on are all written as extensions to the basic
compiler, and are all IMMEDIATE words.
The IMMEDIATE word toggles the F_IMMED (IMMEDIATE flag) on the most recently defined word,
or on the current word if you call it in the middle of a definition.
Typical usage is:
: MYIMMEDWORD IMMEDIATE
...definition...
;
but some FORTH programmers write this instead:
: MYIMMEDWORD
...definition...
; IMMEDIATE
The two usages are equivalent, to a first approximation.
*/
defcode "IMMEDIATE",9,F_IMMED,IMMEDIATE
movl var_LATEST,%edi // LATEST word.
addl $4,%edi // Point to name/flags byte.
xorb $F_IMMED,(%edi) // Toggle the IMMED bit.
NEXT
/*
'addr HIDDEN' toggles the hidden flag (F_HIDDEN) of the word defined at addr. To hide the
most recently defined word (used above in : and ; definitions) you would do:
LATEST @ HIDDEN
'HIDE word' toggles the flag on a named 'word'.
Setting this flag stops the word from being found by FIND, and so can be used to make 'private'
words. For example, to break up a large word into smaller parts you might do:
: SUB1 ... subword ... ;
: SUB2 ... subword ... ;
: SUB3 ... subword ... ;
: MAIN ... defined in terms of SUB1, SUB2, SUB3 ... ;
HIDE SUB1
HIDE SUB2
HIDE SUB3
After this, only MAIN is 'exported' or seen by the rest of the program.
*/
defcode "HIDDEN",6,,HIDDEN
pop %edi // Dictionary entry.
addl $4,%edi // Point to name/flags byte.
xorb $F_HIDDEN,(%edi) // Toggle the HIDDEN bit.
NEXT
defword "HIDE",4,,HIDE
.int WORD // Get the word (after HIDE).
.int FIND // Look up in the dictionary.
.int HIDDEN // Set F_HIDDEN flag.
.int EXIT // Return.
/*
' (TICK) is a standard FORTH word which returns the codeword pointer of the next word.
The common usage is:
' FOO ,
which appends the codeword of FOO to the current word we are defining (this only works in compiled code).
You tend to use ' in IMMEDIATE words. For example an alternate (and rather useless) way to define
a literal 2 might be:
: LIT2 IMMEDIATE
' LIT , \ Appends LIT to the currently-being-defined word
2 , \ Appends the number 2 to the currently-being-defined word
;
So you could do:
: DOUBLE LIT2 * ;
(If you don't understand how LIT2 works, then you should review the material about compiling words
and immediate mode).
This definition of ' uses a cheat which I copied from buzzard92. As a result it only works in
compiled code. It is possible to write a version of ' based on WORD, FIND, >CFA which works in
immediate mode too.
*/
defcode "'",1,,TICK
lodsl // Get the address of the next word and skip it.
pushl %eax // Push it on the stack.
NEXT
/*
BRANCHING ----------------------------------------------------------------------
It turns out that all you need in order to define looping constructs, IF-statements, etc.
are two primitives.
BRANCH is an unconditional branch. 0BRANCH is a conditional branch (it only branches if the
top of stack is zero).
The diagram below shows how BRANCH works in some imaginary compiled word. When BRANCH executes,
%esi starts by pointing to the offset field (compare to LIT above):
+---------------------+-------+---- - - ---+------------+------------+---- - - - ----+------------+
| (Dictionary header) | DOCOL | | BRANCH | offset | (skipped) | word |
+---------------------+-------+---- - - ---+------------+-----|------+---- - - - ----+------------+
^ | ^
| | |
| +-----------------------+
%esi added to offset
The offset is added to %esi to make the new %esi, and the result is that when NEXT runs, execution
continues at the branch target. Negative offsets work as expected.
0BRANCH is the same except the branch happens conditionally.
Now standard FORTH words such as IF, THEN, ELSE, WHILE, REPEAT, etc. can be implemented entirely
in FORTH. They are IMMEDIATE words which append various combinations of BRANCH or 0BRANCH
into the word currently being compiled.
As an example, code written like this:
condition-code IF true-part THEN rest-code
compiles to:
condition-code 0BRANCH OFFSET true-part rest-code
| ^
| |
+-------------+
*/
defcode "BRANCH",6,,BRANCH
add (%esi),%esi // add the offset to the instruction pointer
NEXT
defcode "0BRANCH",7,,ZBRANCH
pop %eax
test %eax,%eax // top of stack is zero?
jz code_BRANCH // if so, jump back to the branch function above
lodsl // otherwise we need to skip the offset
NEXT
/*
LITERAL STRINGS ----------------------------------------------------------------------
LITSTRING is a primitive used to implement the ." and S" operators (which are written in
FORTH). See the definition of those operators later.
TELL just prints a string. It's more efficient to define this in assembly because we
can make it a single Linux syscall.
*/
defcode "LITSTRING",9,,LITSTRING
lodsl // get the length of the string
push %esi // push the address of the start of the string
push %eax // push it on the stack
addl %eax,%esi // skip past the string
addl $3,%esi // but round up to next 4 byte boundary
andl $~3,%esi
NEXT
defcode "TELL",4,,TELL
mov $1,%ebx // 1st param: stdout
pop %edx // 3rd param: length of string
pop %ecx // 2nd param: address of string
mov $__NR_write,%eax // write syscall
int $0x80
NEXT
/*
QUIT AND INTERPRET ----------------------------------------------------------------------
QUIT is the first FORTH function called, almost immediately after the FORTH system "boots".
As explained before, QUIT doesn't "quit" anything. It does some initialisation (in particular
it clears the return stack) and it calls INTERPRET in a loop to interpret commands. The
reason it is called QUIT is because you can call it from your own FORTH words in order to
"quit" your program and start again at the user prompt.
INTERPRET is the FORTH interpreter ("toploop", "toplevel" or "REPL" might be a more accurate
description -- see: http://en.wikipedia.org/wiki/REPL).
*/
// QUIT must not return (ie. must not call EXIT).
defword "QUIT",4,,QUIT
.int RZ,RSPSTORE // R0 RSP!, clear the return stack
.int INTERPRET // interpret the next word
.int BRANCH,-8 // and loop (indefinitely)
/*
This interpreter is pretty simple, but remember that in FORTH you can always override
it later with a more powerful one!
*/
defcode "INTERPRET",9,,INTERPRET
call _WORD // Returns %ecx = length, %edi = pointer to word.
// Is it in the dictionary?
xor %eax,%eax
movl %eax,interpret_is_lit // Not a literal number (not yet anyway ...)
call _FIND // Returns %eax = pointer to header or 0 if not found.
test %eax,%eax // Found?
jz 1f
// In the dictionary. Is it an IMMEDIATE codeword?
mov %eax,%edi // %edi = dictionary entry
movb 4(%edi),%al // Get name+flags.
push %ax // Just save it for now.
call _TCFA // Convert dictionary entry (in %edi) to codeword pointer.
pop %ax
andb $F_IMMED,%al // Is IMMED flag set?
mov %edi,%eax
jnz 4f // If IMMED, jump straight to executing.
jmp 2f
1: // Not in the dictionary (not a word) so assume it's a literal number.
incl interpret_is_lit
call _NUMBER // Returns the parsed number in %eax, %ecx > 0 if error
test %ecx,%ecx
jnz 6f
mov %eax,%ebx
mov $LIT,%eax // The word is LIT
2: // Are we compiling or executing?
movl var_STATE,%edx
test %edx,%edx
jz 4f // Jump if executing.
// Compiling - just append the word to the current dictionary definition.
call _COMMA
mov interpret_is_lit,%ecx // Was it a literal?
test %ecx,%ecx
jz 3f
mov %ebx,%eax // Yes, so LIT is followed by a number.
call _COMMA
3: NEXT
4: // Executing - run it!
mov interpret_is_lit,%ecx // Literal?
test %ecx,%ecx // Literal?
jnz 5f
// Not a literal, execute it now. This never returns, but the codeword will
// eventually call NEXT which will reenter the loop in QUIT.
jmp *(%eax)
5: // Executing a literal, which means push it on the stack.
push %ebx
NEXT
6: // Parse error (not a known word or a number in the current BASE).
// Print an error message followed by up to 40 characters of context.
mov $2,%ebx // 1st param: stderr
mov $errmsg,%ecx // 2nd param: error message
mov $errmsgend-errmsg,%edx // 3rd param: length of string
mov $__NR_write,%eax // write syscall
int $0x80
mov (currkey),%ecx // the error occurred just before currkey position
mov %ecx,%edx
sub $buffer,%edx // %edx = currkey - buffer (length in buffer before currkey)
cmp $40,%edx // if > 40, then print only 40 characters
jle 7f
mov $40,%edx
7: sub %edx,%ecx // %ecx = start of area to print, %edx = length
mov $__NR_write,%eax // write syscall
int $0x80
mov $errmsgnl,%ecx // newline
mov $1,%edx
mov $__NR_write,%eax // write syscall
int $0x80
NEXT
.section .rodata
errmsg: .ascii "PARSE ERROR: "
errmsgend:
errmsgnl: .ascii "\n"
.data // NB: easier to fit in the .data section
.align 4
interpret_is_lit:
.int 0 // Flag used to record if reading a literal
/*
ODDS AND ENDS ----------------------------------------------------------------------
CHAR puts the ASCII code of the first character of the following word on the stack. For example
CHAR A puts 65 on the stack.
EXECUTE is used to run execution tokens. See the discussion of execution tokens in the
FORTH code for more details.
SYSCALL0, SYSCALL1, SYSCALL2, SYSCALL3 make a standard Linux system call. (See <asm/unistd.h>
for a list of system call numbers). As their name suggests these forms take between 0 and 3
syscall parameters, plus the system call number.
In this FORTH, SYSCALL0 must be the last word in the built-in (assembler) dictionary because we
initialise the LATEST variable to point to it. This means that if you want to extend the assembler
part, you must put new words before SYSCALL0, or else change how LATEST is initialised.
*/
defcode "CHAR",4,,CHAR
call _WORD // Returns %ecx = length, %edi = pointer to word.
xor %eax,%eax
movb (%edi),%al // Get the first character of the word.
push %eax // Push it onto the stack.
NEXT
defcode "EXECUTE",7,,EXECUTE
pop %eax // Get xt into %eax
jmp *(%eax) // and jump to it.
// After xt runs its NEXT will continue executing the current word.
defcode "SYSCALL3",8,,SYSCALL3
pop %eax // System call number (see <asm/unistd.h>)
pop %ebx // First parameter.
pop %ecx // Second parameter
pop %edx // Third parameter
int $0x80
push %eax // Result (negative for -errno)
NEXT
defcode "SYSCALL2",8,,SYSCALL2
pop %eax // System call number (see <asm/unistd.h>)
pop %ebx // First parameter.
pop %ecx // Second parameter
int $0x80
push %eax // Result (negative for -errno)
NEXT
defcode "SYSCALL1",8,,SYSCALL1
pop %eax // System call number (see <asm/unistd.h>)
pop %ebx // First parameter.
int $0x80
push %eax // Result (negative for -errno)
NEXT
defcode "SYSCALL0",8,,SYSCALL0
pop %eax // System call number (see <asm/unistd.h>)
int $0x80
push %eax // Result (negative for -errno)
NEXT
/*
DATA SEGMENT ----------------------------------------------------------------------
Here we set up the Linux data segment, used for user definitions and variously known as just
the 'data segment', 'user memory' or 'user definitions area'. It is an area of memory which
grows upwards and stores both newly-defined FORTH words and global variables of various
sorts.
It is completely analogous to the C heap, except there is no generalised 'malloc' and 'free'
(but as with everything in FORTH, writing such functions would just be a Simple Matter
Of Programming). Instead in normal use the data segment just grows upwards as new FORTH
words are defined/appended to it.
There are various "features" of the GNU toolchain which make setting up the data segment
more complicated than it really needs to be. One is the GNU linker which inserts a random
"build ID" segment. Another is Address Space Randomization which means we can't tell
where the kernel will choose to place the data segment (or the stack for that matter).
Therefore writing this set_up_data_segment assembler routine is a little more complicated
than it really needs to be. We ask the Linux kernel where it thinks the data segment starts
using the brk(2) system call, then ask it to reserve some initial space (also using brk(2)).
You don't need to worry about this code.
*/
.text
.set INITIAL_DATA_SEGMENT_SIZE,65536
set_up_data_segment:
xor %ebx,%ebx // Call brk(0)
movl $__NR_brk,%eax
int $0x80
movl %eax,var_HERE // Initialise HERE to point at beginning of data segment.
addl $INITIAL_DATA_SEGMENT_SIZE,%eax // Reserve nn bytes of memory for initial data segment.
movl %eax,%ebx // Call brk(HERE+INITIAL_DATA_SEGMENT_SIZE)
movl $__NR_brk,%eax
int $0x80
ret
/*
We allocate static buffers for the return static and input buffer (used when
reading in files and text that the user types in).
*/
.set RETURN_STACK_SIZE,8192
.set BUFFER_SIZE,4096
.bss
/* FORTH return stack. */
.align 4096
return_stack:
.space RETURN_STACK_SIZE
return_stack_top: // Initial top of return stack.
/* This is used as a temporary input buffer when reading from files or the terminal. */
.align 4096
buffer:
.space BUFFER_SIZE
/*
START OF FORTH CODE ----------------------------------------------------------------------
We've now reached the stage where the FORTH system is running and self-hosting. All further
words can be written as FORTH itself, including words like IF, THEN, .", etc which in most
languages would be considered rather fundamental.
I used to append this here in the assembly file, but I got sick of fighting against gas's
crack-smoking (lack of) multiline string syntax. So now that is in a separate file called
jonesforth.f
If you don't already have that file, download it from http://annexia.org/forth in order
to continue the tutorial.
*/
/* END OF jonesforth.S */
|
agsb/milliForth-6502
| 7,755
|
refs/monitor.s
|
; AlexMon Monitor by Adumont
;
; Copyright (C) 2021-2023 Alexandre Dumont <adumont@gmail.com>
;
; SPDX-License-Identifier: GPL-3.0-only
;
; Monitor will show content at ADDR.
; You can type:
; - an ADDR (4 char, hex) --> set ADDR
; - a value (2 char, hex) --> store value at ADDR
; - ' followed by a char --> store the char at ADDR
; - j --> restore registers to saved values and jump to ADDR
; - c --> continue (after a BRK). restore registers to saved values, set ADDR to saved PC (after BRK) and jump to ADDR
;
; Registers manipulation (saved values):
; - aXX : store XX (hex) in A
; - xXX : store XX (hex) in X
; - yXX : store XX (hex) in Y
; - sXX : store XX (hex) in S
; - pXX : store XX (hex) in P
; - r : print registers value
;
; help: https://cc65.github.io/doc/ca65.html
.pc02 ; 65C02 mode
.debuginfo + ; Generate debug info
.segment "CODE"
_init:
BRA loop
inc_addr:
; we increment ADDR
INC z:MON_ADDR ; ADDR LO++
BNE put_newline ; show_addr
INC z:MON_ADDR+1 ; ADDR HI++
; fallback to put_newline
put_newline:
JSR CRLF
; fallback to loop
loop:
; show address
LDA z:MON_ADDR+1
JSR print_byte
LDA z:MON_ADDR
JSR print_byte
; show value at addr
LDA #':'
JSR putc
LDY #0
LDA (MON_ADDR),y
TAX ; we use X to save the VALUE
JSR print_byte ; print byte at ADDR
LDA #' '
JSR putc
CPX #$20
BMI non_printable ; not printable (too low)
CPX #$7E
BPL non_printable ; not printable (too low)
TXA
JSR putc
JMP prompt
non_printable:
; print a blank char
LDA #' '
JSR putc
prompt:
LDA #' '
JSR putc
LDA #'?'
JSR putc
LDA #' '
JSR putc
JSR getline
CMP #$0d ; LF
BEQ cmd_return
; here user hit ESC
cmd_esc:
; here we do whatever to handle an ESC
LDA #'E'
JSR putc
lda #'S'
JSR putc
lda #'C'
JSR putc
JMP put_newline
cmd_return:
; here we do whatever to handle a RETURN
; decision tree depending on the length
; (length is still stored in X at this pointtp)
CPX #0 ; user has just hit return again?
BEQ inc_addr
LDA CMD ; first char
CMP #'r' ; Print Registers
BEQ preg_cmd
CMP #$27 ; starts with simple quote '
BEQ it_is_a_char
CMP #'j' ; Jmp
BEQ exec_cmd
CPX #2 ; 2 chars --> a value
BEQ it_is_a_value
CPX #4 ; 4 chars --> an addr
BEQ it_is_an_addr
CMP #'c' ; Continue
BEQ cont_cmd
CPX #3
BNE error
TAY ; we store the letter in Y
LDX #1
JSR scan_ascii_byte
CPY #'a' ; edit A
BEQ editA_cmd
CPY #'x' ; edit X
BEQ editX_cmd
CPY #'y' ; edit Y
BEQ editY_cmd
CPY #'s' ; edit S
BEQ editS_cmd
CPY #'p' ; edit P
BEQ editP_cmd
; ELSE
JMP error
cont_cmd:
LDA MON_PC
STA z:MON_ADDR
LDA MON_PC+1
STA z:MON_ADDR+1
; fallback to exec_cmd
exec_cmd:
LDA MON_P
PHA
PLP ; transfer to P
LDX MON_S
TXS
LDY MON_Y
LDX MON_X
LDA MON_A
JMP (MON_ADDR)
; we don't know were wi'll end up...
it_is_a_char:
LDX #1 ; we load the 2nd byte of CMD
LDA CMD,x ; into A
STA (MON_ADDR),y ; and store at ADDR
JMP inc_addr
it_is_a_value:
LDX #0
JSR scan_ascii_byte
LDY #0
STA (MON_ADDR),y
JMP inc_addr
it_is_an_addr:
LDX #0
JSR scan_ascii_addr
JMP put_newline
preg_cmd:
JSR Print_Registers
JMP put_newline
editA_cmd:
sta MON_A
JMP put_newline
editX_cmd:
sta MON_X
JMP put_newline
error:
LDA #'E'
JSR putc
lda #'R'
JSR putc
lda #'R'
JSR putc
JMP put_newline ; and loop
editY_cmd:
sta MON_Y
JMP put_newline
editS_cmd:
sta MON_S
JMP put_newline
editP_cmd:
ORA #$30 ; we force bits 4 and 5 to 1
STA MON_P
JMP put_newline
print_byte:
PHA ; save A for 2nd nibble
LSR ; here we shift right
LSR ; to get HI nibble
LSR
LSR
JSR nibble_value_to_asc
JSR putc
PLA
AND #$0F ; LO nibble
JSR nibble_value_to_asc
JMP putc
CRLF:
; output a CR+LF
LDA #$0a ; CR
JSR putc
LDA #$0d ; LF
JMP putc
getline:
LDX #0
next:
JSR getc
CMP #$0D ; LF (enter)?
BEQ eol
CMP #$1B ; ESC
BEQ eol
CMP #$08 ; Backspace
BEQ backspace
; CMP #'9'+1
; BMI skip_uppercase
; AND #$DF ; make upper case
;skip_uppercase:
STA CMD,x ; save in buffer
CPX #$0F ; x=15 -> end line
BEQ eol
INX
JSR putc ; echo char
JMP next ; wait for next
backspace:
CPX #0
BEQ next
DEX
JSR putc ; echo char
JMP next
eol:
STX LEN
RTS
nibble_asc_to_value:
; converts a char representing a hex-digit (nibble)
; into the corresponding hex value
CMP #$41
BMI less
SBC #$37
less:
AND #$0F
RTS
nibble_value_to_asc:
CMP #$0A
BCC skip
ADC #$66
skip:
EOR #$30
RTS
scan_ascii_addr:
LDA CMD,X ; load char into A
JSR nibble_asc_to_value
ASL
ASL
ASL
ASL
STA z:MON_ADDR+1
INX
LDA CMD,X ; load char into A
JSR nibble_asc_to_value
ORA z:MON_ADDR+1
STA z:MON_ADDR+1
INX
LDA CMD,X ; load char into A
JSR nibble_asc_to_value
ASL
ASL
ASL
ASL
STA z:MON_ADDR
INX
LDA CMD,X ; load char into A
JSR nibble_asc_to_value
ORA z:MON_ADDR
STA z:MON_ADDR
RTS
scan_ascii_byte:
LDA CMD,X ; load char into A
JSR nibble_asc_to_value
ASL
ASL
ASL
ASL
STA BYTE
INX
LDA CMD,X ; load char into A
JSR nibble_asc_to_value
ORA BYTE
STA BYTE
RTS
Print_Registers:
JSR CRLF
LDA #'A'
JSR putc
LDA MON_A
JSR print_byte
LDA #' '
JSR putc
LDA #'X'
JSR putc
LDA MON_X
JSR print_byte
LDA #' '
JSR putc
LDA #'Y'
JSR putc
LDA MON_Y
JSR print_byte
LDA #' '
JSR putc
LDA #'P'
JSR putc
LDA MON_P
JSR print_byte
LDA #' '
JSR putc
LDA #'S'
JSR putc
LDA MON_S
JSR print_byte
LDA #' '
JSR putc
LDA #'P'
JSR putc
LDA #'C'
JSR putc
LDA MON_PC+1
JSR print_byte
LDA MON_PC
JSR print_byte
RTS
IO_AREA = $F000
getc:
LDA IO_AREA+4
BEQ getc
RTS
putc:
STA IO_AREA+1
RTS
; -----------------------------------------------------------------------
; -----------------------------------------------------------------------
; Non-maskable interrupt (NMI) service routine
_nmi_int: RTI ; Return from all NMI interrupts
; -----------------------------------------------------------------------
; Maskable interrupt (IRQ) service routine
_irq_int:
; Save registers
STX MON_X ; before | xx | after the
STY MON_Y ; interrupt | xx | interrupt
STA MON_A ; | xx |
TSX ; get current SP into X ; old SP ->| PC HI | SP+3
; | PC LO | SP+2
LDA $0102,X ; SP+2 -> PC LO ; | P | SP+1
STA MON_PC ; | | <- SP (new SP)
;
LDA $0103,X ; SP+3 -> PC HI ;
STA MON_PC+1 ;
LDA $0101,X ; SP+1 -> P
STA MON_P
INX ; add 3 to get
INX ; SP before IRQ
INX
STX MON_S
; is it a BRK?
LDA #$10 ; position of B bit
BIT MON_P ; is B bit set, indicating BRK and not IRQ?
BNE BRKhandler
; here it's not a BRK
; Another type of IRQ then...
LDA #'i'
JSR putc
LDA #'r'
JSR putc
LDA #'q'
JSR putc
LDY MON_Y
LDX MON_X
LDA MON_A
RTI
BRKhandler:
CLI ; we reenable Interrupts (in case other more urgent IRQ arrives)
JSR Print_Registers
LDX MON_S
TXS
LDY MON_Y
LDX MON_X
LDA MON_A
CLI
JMP put_newline
;RTI
; -----------------------------------------------------------------------
; Constants! (for variables, see .DATA)
.RODATA
MSG: .asciiz "adumont 6502"
; -----------------------------------------------------------------------
; reserve space for global variables
.ZEROPAGE
MON_ADDR: .res 2 ; // NOTICE remember to use z:MON_ADDR to force zeropage addressing.
; for variables we want to have initialized, and be able to modify later. Requires copydata.s!
; for reserving space only, use .BSS
.DATA
.BSS
BYTE: .res 1
LEN: .res 1 ; Length of CMD
CMD: .res 16 ; CMD string
MON_A: .res 1
MON_X: .res 1
MON_Y: .res 1
MON_S: .res 1
MON_P: .res 1
MON_PC: .res 2
.segment "VECTORS"
.addr _nmi_int ; NMI vector
.addr _init ; Reset vector
.addr _irq_int ; IRQ/BRK vector
|
agsb/milliForth-6502
| 26,861
|
stub/6502-zero/sector-6502.s
|
;----------------------------------------------------------------------
;
; A MilliForth for 6502
;
; original for the 6502, by Alvaro G. S. Barcellos, 2023
;
; https://github.com/agsb
; see the disclaimer file in this repo for more information.
;
; SectorForth and MilliForth was made for x86 arch
; and uses full 16-bit registers
;
; The way at 6502 is use page zero and lots of lda/sta
;
; Focus in size not performance.
;
; why ? For understand better my skills, 6502 code and thread codes
;
; how ? Programming a new Forth for old 8-bit cpu emulator
;
; what ? Design the best minimal Forth engine and vocabulary
;
;----------------------------------------------------------------------
; Changes:
;
; all data (36 cells) and return (36 cells) stacks, TIB (80 bytes)
; and PIC (32 bytes) are in same page $200, 256 bytes;
;
; TIB and PIC grows forward, stacks grows backwards;
;
; no overflow or underflow checks;
;
; the header order is LINK, SIZE+FLAG, NAME.
;
; only IMMEDIATE flag used as $80, no hide, no compile;
;
; As ANSI Forth 1994: FALSE is $0000 ; TRUE is $FFFF ;
;
;----------------------------------------------------------------------
; Remarks:
;
; this code uses
; Direct Thread Code, aka DTC or
; Minimal Thread Code, aka MTC.
;
; use a classic cell with 16-bits.
;
; no TOS register, all values keeped at stacks;
;
; TIB (terminal input buffer) is like a stream;
;
; Chuck Moore uses 64 columns, be wise, obey rule 72 CPL;
;
; words must be between spaces, before and after;
;
; no line wrap, do not break words between lines;
;
; only 7-bit ASCII characters, plus \n, no controls;
; ( later maybe \b backspace and \u cancel )
;
; words are case-sensitivy and less than 16 characters;
;
; no need named-'pad' at end of even names;
;
; no multiuser, no multitask, no checks, not faster;
;
;----------------------------------------------------------------------
; For 6502:
;
; a 8-bit processor with 16-bit address space;
;
; the most significant byte is the page count;
;
; page zero and page one hardware reserved;
;
; hardware stack not used for this Forth;
;
; page zero is used as pseudo registers;
;
;----------------------------------------------------------------------
; For stacks:
;
; "when the heap moves forward, move the stack backward"
;
; as hardware stacks do:
; push is 'store and decrease', pull is 'increase and fetch',
;
; but see the notes for Devs.
;
; common memory model organization of Forth:
; [tib->...<-spt: user forth dictionary :here->pad...<-rpt]
; then backward stacks allow to use the slack space ...
;
; this 6502 Forth memory model blocked in pages of 256 bytes:
; [page0][page1][page2][core ... forth dictionary ...here...]
;
; At page2:
;
; |$00 tib> .. $50| <spt..sp0 $98| <rpt..rp0 $E0|pic> ..$FF|
;
; From page 3 onwards:
;
; |$0300 cold:, warm:, forth code, init: here> heap ... tail|
;
; PIC is a transient area of 32 bytes
; PAD could be allocated from here
;
;----------------------------------------------------------------------
; For Devs:
;
; the hello_world.forth file states that stacks works
; to allow : dup sp@ @ ; so sp must point to actual TOS.
;
; The movement will be:
; pull is 'fetch and increase'
; push is 'decrease and store'
;
; Never mess with two underscore variables;
;
; Not using smudge,
; colon saves "here" into "back" and
; semis loads "lastest" from "back";
;
; Do not risk to put stacks with $FF.
;
; Also carefull inspect if any label ends with $FF and move it;
;
; This source is hacked for use with Ca65.
;
;----------------------------------------------------------------------
;
; Stacks represented as (standart)
; S:(w1 w2 w3 -- u1 u2) R:(w1 w2 w3 -- u1 u2)
; before -- after, top at left.
;
;----------------------------------------------------------------------
;
; Stuff for ca65 compiler
;
.p02
.feature c_comments
.feature string_escapes
.feature org_per_seg
.feature dollar_is_pc
.feature pc_assignment
;---------------------------------------------------------------------
; macros for dictionary, makes:
;
; h_name:
; .word link_to_previous_entry
; .byte strlen(name) + flags
; .byte name
; name:
;
; label for primitives
.macro makelabel arg1, arg2
.ident (.concat (arg1, arg2)):
.endmacro
; header for primitives
; the entry point for dictionary is h_~name~
; the entry point for code is ~name~
.macro def_word name, label, flag
makelabel "h_", label
.ident(.sprintf("H%04X", hcount + 1)) = *
.word .ident (.sprintf ("H%04X", hcount))
hcount .set hcount + 1
.byte .strlen(name) + flag + 0 ; nice trick !
.byte name
makelabel "", label
.endmacro
;---------------------------------------------------------------------
; variables for macros
hcount .set 0
H0000 = 0
;---------------------------------------------------------------------
; define thread code model
; MTC is default
; use_DTC = 1
; uncomment to include the extras (sic)
use_extras = 1
; uncomment to include the extensions (sic)
use_extensions = 1
;---------------------------------------------------------------------
/*
NOTES:
not finished yet :)
*/
;----------------------------------------------------------------------
;
; alias
; cell size, two bytes, 16-bit
CELL = 2
; highlander, immediate flag.
FLAG_IMM = 1<<7
; "all in" page $200
; terminal input buffer, forward
; getline, token, skip, scan, depends on page boundary
tib = $0200
; reserve 80 bytes, (72 is enough)
; moves forwards
tib_end = $50
; reserved for scribbles
pic = tib_end
; data stack, 36 cells,
; moves backwards, push decreases before copy
DATA_SIZE = 24 * 2
; return stack, 36 cells,
; moves backwards, push decreases before copy
RETURN_SIZE = 24 * 2
;----------------------------------------------------------------------
; "What happens in Vegas, stays in Vegas", like in page zero
; but no values here or must be at BSS
.segment "ZERO"
; * = $TAKE_ME
; empty for fixed reference
nil:
; cascate allocation
; stacks
sp0 = nil + DATA_SIZE
rp0 = sp0 + RETURN_SIZE
spi = rp0 + 1
rpi = spi + 1
; pointers registers
ipt = rpi + 2 ; instruction pointer
wrd = ipt + 2 ; word pointer
; for future expansion, reserved
head = wrd + 2 ; heap forward, also DP
tail = head + 2 ; heap backward
; used, reserved
tout = tail + 2 ; next token in TIB
back = tout + 2 ; hold 'here while compile
; classic, free for use
fst = back + 2 ; first
snd = fst + 2 ; second
trd = snd + 2 ; third
fth = trd + 2 ; fourth
; as user variables
; sure, order matters for hello_world.forth !
; internal Forth
stat = fth + 2 ; state at lsb, last size+flag at msb
toin = stat + 2 ; toin next free byte in TIB
last = toin + 2 ; last link cell
here = last + 2 ; next free cell in heap dictionary, aka dpt
;.end
;----------------------------------------------------------------------
;.segment "ONCE"
; no rom code
;----------------------------------------------------------------------
;.segment "VECTORS"
; no boot code
;----------------------------------------------------------------------
.segment "CODE"
; ram code here
;
; leave space for page zero, hard stack,
; and buffer, locals, forth stacks
;
* = $300
main:
;----------------------------------------------------------------------
; common must
;
cold:
; disable interrupts
sei
; clear BCD
cld
; set real stack
ldx #$FF
txs
; enable interrupts
cli
;----------------------------------------------------------------------
warm:
; link list of headers
lda #>h_exit
sta last + 1
lda #<h_exit
sta last + 0
; next heap free cell, same as init:
lda #>ends + 1
sta here + 1
lda #0
sta here + 0
;---------------------------------------------------------------------
; supose never change
reset:
ldy #02
sty toin + 1
sty tout + 1
abort:
ldy #sp0
sty spi
quit:
ldy #rp0
sty rpi
clean:
; reset tib
ldy #0
; clear tib stuff
sty tib + 0
; clear cursor
sty toin + 0
; stat is 'interpret' == \0
sty stat + 0
.byte $2c ; mask next two bytes, nice trick !
;---------------------------------------------------------------------
; the outer loop
resolvept:
.word okey
;---------------------------------------------------------------------
okey:
;; uncomment for feedback
; lda stat + 0
; bne resolve
; lda #'O'
; jsr putchar
; lda #'K'
; jsr putchar
; lda #10
; jsr putchar
resolve:
; get a token
jsr token
; lda #'P'
; jsr putchar
find:
; load last
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
@loop:
; lsb linked list
lda snd + 0
sta wrd + 0
; verify \0x0
ora snd + 1
beq abort
; maybe to place a code for number?
; but not for now.
;; uncomment for feedback, comment out "beq abort" above
; lda #'?'
; jsr putchar
; lda #'?'
; jsr putchar
; lda #10
; jsr putchar
; jmp abort ; end of dictionary, no more words to search, abort
@each:
; msb linked list
lda snd + 1
sta wrd + 1
; update next link
ldx #(wrd) ; from
ldy #(snd) ; into
jsr copyfrom
; compare words
ldy #0
; save the flag, first byte is (size and flag)
lda (wrd), y
sta stat + 1
; compare chars
@equal:
lda (tout), y
; space ends
cmp #32
beq @done
; verify
sec
sbc (wrd), y
; clean 7-bit ascii
asl
bne @loop
; next char
iny
bne @equal
@done:
; update wrd
tya
;; ldx #(wrd) ; set already
;; addwx also clear carry
jsr addwx
eval:
; executing ? if == \0
lda stat + 0
beq execute
; immediate ? if < \0
lda stat + 1
bmi immediate
compile:
; lda #'C'
; jsr putchar
jsr wcomma
bcc resolve
immediate:
execute:
; lda #'E'
; jsr putchar
lda #>resolvept
sta ipt + 1
lda #<resolvept
sta ipt + 0
;~~~~~~~~
.ifdef use_DTC
jmp (wrd)
.else
jmp pick
.endif
;~~~~~~~~
;---------------------------------------------------------------------
try:
lda tib, y
beq getline ; if \0
iny
eor #' '
rts
;---------------------------------------------------------------------
getline:
; drop rts of try
pla
pla
; leave the first
ldy #0
@loop:
; is valid
sta tib, y ; dummy store on first pass, overwritten
iny
; would be better with
; end of buffer ?
; cpy #tib_end
; beq @ends
; then
jsr getchar
; would be better with
; 7-bit ascii only
; and #$7F
; unix \n
cmp #10
bne @loop
; would be better with
; no controls
; cmp #' '
; bmi @loop
; clear all if y eq \0
@ends:
; grace \b
lda #32
sta tib + 0 ; start with space
sta tib, y ; ends with space
; mark eol with \0
lda #0
sta tib + 1, y
; start it
sta toin + 0
;---------------------------------------------------------------------
; in place every token,
; the counter is placed at last space before word
; no rewinds
token:
; last position on tib
ldy toin + 0
@skip:
; skip spaces
jsr try
beq @skip
; keep y == start + 1
dey
sty tout + 0
@scan:
; scan spaces
jsr try
bne @scan
; keep y == stop + 1
dey
sty toin + 0
@done:
; sizeof
tya
sec
sbc tout + 0
; keep it
ldy tout + 0
dey
sta tib, y ; store size for counted string
sty tout + 0
; setup token
clc ; clean
rts
;---------------------------------------------------------------------
; this code depends on systems or emulators
;
; lib6502 emulator
;
getchar:
lda $E000
eofs:
; EOF ?
cmp #$FF ; also clean carry :)
beq byes
putchar:
sta $E000
rts
; exit for emulator
byes:
jmp $0000
;
; lib6502 emulator
;---------------------------------------------------------------------
;---------------------------------------------------------------------
; decrement a word in page zero. offset by X
decwx:
lda 0, x
bne @ends
dec 1, x
@ends:
dec 0, x
rts
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
;incwx:
; inc 0, x
; bne @ends
; inc 1, x
;@ends:
; rts
;---------------------------------------------------------------------
; classic heap moves always forward
;
stawrd:
sta wrd + 1
wcomma:
ldy #(wrd)
comma:
ldx #(here)
; fall throught
;---------------------------------------------------------------------
; from a page zero address indexed by Y
; into a page zero indirect address indexed by X
copyinto:
lda 0, y
sta (0, x)
jsr incwx
lda 1, y
sta (0, x)
jmp incwx
;---------------------------------------------------------------------
;
; generics
;
;---------------------------------------------------------------------
spush1:
ldy #(fst)
;---------------------------------------------------------------------
; push a cell
; from a page zero address indexed by Y
; into a page zero address indexed by X
spush:
ldx #(spi)
; jmp push
.byte $2c ; mask next two bytes, nice trick !
rpush:
ldx #(rpi)
;---------------------------------------------------------------------
; classic stack backwards
push:
dex
lda 1, y
sta 0, x
dex
lda 0, y
sta 0, x
rts
;---------------------------------------------------------------------
spull2:
ldy #(snd)
jsr spull
; fall through
;---------------------------------------------------------------------
spull1:
ldy #(fst)
; fall through
;---------------------------------------------------------------------
; pull a cell
; from a page zero indirect address indexed by X
; into a page zero address indexed by y
spull:
ldx #(spi)
; jmp pull
.byte $2c ; mask next two bytes, nice trick !
rpull:
ldx #(rpi)
;---------------------------------------------------------------------
; classic stack backwards
pull: ; fall through, same as copyfrom
;---------------------------------------------------------------------
; from a page zero address indexed by X
; into a page zero address indexed by y
copyfrom:
lda 0, x
sta 0, y
inx
lda 0, x
sta 1, y
; jmp incwx ; fall through
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
incwx:
lda #01
;---------------------------------------------------------------------
; add a byte to a word in page zero. offset by X
addwx:
clc
adc 0, x
sta 0, x
bcc @ends
inc 1, x
clc ; keep carry clean
@ends:
rts
;---------------------------------------------------------------------
;
; the primitives,
; for stacks uses
; a address, c byte ascii, w signed word, u unsigned word
; cs counted string < 256, sz string with nul ends
;
;----------------------------------------------------------------------
.ifdef use_extras
;----------------------------------------------------------------------
; extras
;----------------------------------------------------------------------
; ( -- ) ae exit forth
def_word "bye", "bye", 0
jmp byes
;----------------------------------------------------------------------
; ( -- ) ae abort
def_word "abort", "abort_", 0
jmp abort
;----------------------------------------------------------------------
; ( -- ) ae list of data stack
def_word ".S", "splist", 0
lda spi + 0
sta fst + 0
lda #00
sta fst + 1
lda #'S'
jsr putchar
lda #sp0
jsr list
jmp next
;----------------------------------------------------------------------
; ( -- ) ae list of return stack
def_word ".R", "rplist", 0
lda rpi
sta fst + 0
lda #00
sta fst + 1
lda #'R'
jsr putchar
lda #rp0
jsr list
jmp next
;----------------------------------------------------------------------
; ae list a sequence of references
list:
sec
sbc fst + 0
lsr
tax
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #' '
jsr putchar
txa
jsr puthex
lda #' '
jsr putchar
txa
beq @ends
ldy #0
@loop:
lda #' '
jsr putchar
iny
lda (fst),y
jsr puthex
dey
lda (fst),y
jsr puthex
iny
iny
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ( -- ) dumps the user dictionary
def_word "dump", "dump", 0
lda #$0
sta fst + 0
lda #>ends + 1
sta fst + 1
ldx #(fst)
ldy #0
@loop:
lda (fst),y
jsr putchar
jsr incwx
lda fst + 0
cmp here + 0
bne @loop
lda fst + 1
cmp here + 1
bne @loop
clc ; clean
jmp next
;----------------------------------------------------------------------
; ( -- ) words in dictionary,
def_word "words", "words", 0
; load lastest
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
; load here
lda here + 1
sta trd + 1
lda here + 0
sta trd + 0
@loop:
; lsb linked list
lda snd + 0
sta fst + 0
; verify \0x0
ora snd + 1
beq @ends
; msb linked list
lda snd + 1
sta fst + 1
@each:
lda #10
jsr putchar
; put address
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; put link
lda #' '
jsr putchar
ldy #1
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
ldx #(fst)
lda #2
jsr addwx
; put size + flag, name
ldy #0
jsr show_name
; update
iny
tya
ldx #(fst)
jsr addwx
; show CFA
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; check if is a primitive
lda fst + 1
cmp #>ends + 1
bmi @continue
; list references
ldy #0
jsr show_refer
@continue:
lda snd + 0
sta trd + 0
lda snd + 1
sta trd + 1
ldy #0
lda (trd), y
sta snd + 0
iny
lda (trd), y
sta snd + 1
ldx #(trd)
lda #2
jsr addwx
jmp @loop
@ends:
clc ; clean
jmp next
;----------------------------------------------------------------------
; ae put size and name
show_name:
lda #' '
jsr putchar
lda (fst), y
jsr puthex
lda #' '
jsr putchar
lda (fst), y
and #$7F
tax
@loop:
iny
lda (fst), y
jsr putchar
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
show_refer:
; ae put references PFA ...
ldx #(fst)
@loop:
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #':'
jsr putchar
iny
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
lda #2
jsr addwx
; check if ends
lda fst + 0
cmp trd + 0
bne @loop
lda fst + 1
cmp trd + 1
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ae seek for 'exit to ends a sequence of references
; max of 254 references in list
;
seek:
ldy #0
@loop1:
iny
beq @ends
lda (fst), y
cmp #>exit
bne @loop1
dey
lda (fst), y
cmp #<exit
beq @ends
iny
bne @loop1
@ends:
tya
lsr
clc ; clean
rts
;----------------------------------------------------------------------
; ( u -- u ) print tos in hexadecimal, swaps order
def_word ".", "dot", 0
lda #' '
jsr putchar
jsr spull1
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
jsr spush1
jmp next
;----------------------------------------------------------------------
; code a byte in ASCII hexadecimal
puthex:
pha
lsr
ror
ror
ror
jsr @conv
pla
@conv:
and #$0F
ora #$30
cmp #$3A
bcc @ends
adc #$06
@ends:
clc ; clean
jmp putchar
.endif
; .ifdef use_extras
.ifdef numbers
;----------------------------------------------------------------------
; code a ASCII $FFFF hexadecimal in a byte
;
number:
ldy #0
jsr @very
asl
asl
asl
asl
sta fst + 1
iny
jsr @very
ora fst + 1
sta fst + 1
iny
jsr @very
asl
asl
asl
asl
sta fst + 0
iny
jsr @very
ora fst + 0
sta fst + 0
clc ; clean
rts
@very:
lda (tout), y
sec
sbc #$30
bmi @erro
cmp #10
bcc @ends
sbc #$07
; any valid digit, A-Z, do not care
@ends:
rts
@erro:
pla
pla
rts
.endif
; .ifdef numbers
;---------------------------------------------------------------------
;
; extensions
;
;---------------------------------------------------------------------
.ifdef use_extensions
;---------------------------------------------------------------------
; ( w -- w/2 ) ; shift right
def_word "2/", "shr", 0
jsr spull1
lsr fst + 1
ror fst + 0
jmp this
;---------------------------------------------------------------------
; ( a -- ) execute a jump to a reference at top of data stack
def_word "exec", "exec", 0
jsr spull1
jmp (fst)
;---------------------------------------------------------------------
; ( -- ) execute a jump to a reference at IP
def_word ":$", "docode", 0
jmp (ipt)
;---------------------------------------------------------------------
; ( -- ) execute a jump to next
def_word ";$", "donext", 0
jmp next
.endif
; .ifdef use_extensions
;---------------------------------------------------------------------
; core primitives minimal
; start of dictionary
;---------------------------------------------------------------------
; ( -- u ) ; tos + 1 unchanged
def_word "key", "key", 0
jsr getchar
sta fst + 0
; jmp this ; uncomment if char could be \0
bne this ; always taken
;---------------------------------------------------------------------
; ( u -- ) ; tos + 1 unchanged
def_word "emit", "emit", 0
jsr spull1
lda fst + 0
jsr putchar
; jmp next ; uncomment if carry could be set
bcc jmpnext ; always taken
;---------------------------------------------------------------------
; ( a w -- ) ; [a] = w
def_word "!", "store", 0
storew:
jsr spull2
ldx #(snd)
ldy #(fst)
jsr copyinto
; jmp next ; uncomment if carry could be set
bcc jmpnext ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- NOT(w1 AND w2) )
def_word "nand", "nand", 0
jsr spull2
lda snd + 0
and fst + 0
eor #$FF
sta fst + 0
lda snd + 1
and fst + 1
eor #$FF
; jmp keeps ; uncomment if carry could be set
bcc keeps ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- w1+w2 )
def_word "+", "plus", 0
jsr spull2
clc ; better safe than sorry
lda snd + 0
adc fst + 0
sta fst + 0
lda snd + 1
adc fst + 1
jmp keeps
;---------------------------------------------------------------------
; ( a -- w ) ; w = [a]
def_word "@", "fetch", 0
fetchw:
jsr spull1
ldx #(fst)
ldy #(snd)
jsr copyfrom
; fall throught
;---------------------------------------------------------------------
copys:
lda 0, y
sta fst + 0
lda 1, y
keeps:
sta fst + 1
this:
jsr spush1
jmpnext:
jmp next
;---------------------------------------------------------------------
; ( 0 -- $0000) | ( n -- $FFFF) not zero at top ?
def_word "0#", "zeroq", 0
jsr spull1
lda fst + 1
ora fst + 0
beq isfalse ; is \0 ?
istrue:
lda #$FF
isfalse:
sta fst + 0
jmp keeps
;---------------------------------------------------------------------
; ( -- state ) a variable return an reference
def_word "s@", "state", 0
lda #<stat
sta fst + 0
lda #>stat
; jmp keeps ; uncomment if stats not in page $0
beq keeps ; always taken
;---------------------------------------------------------------------
def_word ";", "semis", FLAG_IMM
; update last, panic if colon not lead elsewhere
lda back + 0
sta last + 0
lda back + 1
sta last + 1
; stat is 'interpret'
lda #0
sta stat + 0
; compound words must ends with exit
finish:
lda #<exit
sta wrd + 0
lda #>exit
sta wrd + 1
jsr wcomma
; jmp next
bcc next ; always taken
;---------------------------------------------------------------------
def_word ":", "colon", 0
; save here, panic if semis not follow elsewhere
lda here + 0
sta back + 0
lda here + 1
sta back + 1
; stat is 'compile'
lda #1
sta stat + 0
@header:
; copy last into (here)
ldy #(last)
jsr comma
; get following token
jsr token
; copy it
ldy #0
@loop:
lda (tout), y
cmp #32 ; stops at space
beq @ends
sta (here), y
iny
bne @loop
@ends:
; update here
tya
ldx #(here)
jsr addwx
;~~~~~~~~
.ifdef use_DTC
; magic NOP (EA) JSR (20), at CFA cell
; magic = $EA20
magic = $20EA
; inserts the nop call
lda #<magic
sta wrd + 0
lda #>magic
jsr stawrd
; inserts the reference
lda #<nest
sta wrd + 0
lda #>nest
jsr stawrd
.endif
;~~~~~~~~
; done
; jmp next
bcc next ; always taken
;---------------------------------------------------------------------
; Thread Code Engine
;
; ipt is IP, wrd is W
;
; for reference:
;
; nest aka enter or docol,
; unnest aka exit or semis;
;
;---------------------------------------------------------------------
; ( -- )
def_word "exit", "exit", 0
unnest: ; exit
; pull, ipt = (rpt), rpt += 2
ldy #(ipt)
jsr rpull
next:
; wrd = (ipt) ; ipt += 2
ldx #(ipt)
ldy #(wrd)
jsr copyfrom
;~~~~~~~~
.ifdef use_DTC
pick:
jmp (wrd)
nest: ; enter
; push, *rp = ipt, rp -=2
ldy #(ipt)
jsr rpush
; pull (ip),
pla
sta ipt + 0
pla
sta ipt + 1
; 6502 trick: must increase return address
ldx #(ipt)
jsr incwx
bcc next
.else
pick:
; compare pages (MSBs)
lda wrd + 1
cmp #>ends + 1
bmi jump
nest: ; enter
; push, *rp = ipt, rp -=2
ldy #(ipt)
jsr rpush
lda wrd + 0
sta ipt + 0
lda wrd + 1
sta ipt + 1
jmp next
jump:
jmp (wrd)
.endif
;~~~~~~~~
;-----------------------------------------------------------------------
; BEWARE, MUST BE AT END! MINIMAL THREAD CODE DEPENDS ON IT!
ends:
;-----------------------------------------------------------------------
; anything above is not a primitive
;----------------------------------------------------------------------
|
agsb/milliForth-6502
| 24,662
|
stub/65C02/sector-65C02.s
|
;----------------------------------------------------------------------
;
; A MilliForth for 65C02
;
; original for the 6502, by Alvaro G. S. Barcellos, 2023
;
; this one for 65C02
;
; https://github.com/agsb
; see the disclaimer file in this repo for more information.
;
; SectorForth and MilliForth was made for x86 arch
; and uses full 16-bit registers
;
; The way at 6502 is use page zero and lots of lda/sta
;
; Focus in size not performance.
;
; why ? For understand better my skills, 6502 code and thread codes
;
; how ? Programming a new Forth for old 8-bit cpu emulator
;
; what ? Design the best minimal Forth engine and vocabulary
;
;----------------------------------------------------------------------
; Changes:
;
; all data (36 cells) and return (36 cells) stacks, TIB (80 bytes)
; and PIC (32 bytes) are in same page $200, 256 bytes;
;
; TIB and PIC grows forward, stacks grows backwards;
;
; no overflow or underflow checks;
;
; the header order is LINK, SIZE+FLAG, NAME.
;
; only IMMEDIATE flag used as $80, no hide, no compile;
;
; As ANSI Forth 1994: FALSE is $0000 ; TRUE is $FFFF ;
;
;----------------------------------------------------------------------
; Remarks:
;
; this code uses
; Direct Thread Code, aka DTC or
; Minimal Thread Code, aka MTC.
;
; use a classic cell with 16-bits.
;
; no TOS register, all values keeped at stacks;
;
; TIB (terminal input buffer) is like a stream;
;
; Chuck Moore uses 64 columns, be wise, obey rule 72 CPL;
;
; words must be between spaces, before and after;
;
; no line wrap, do not break words between lines;
;
; only 7-bit ASCII characters, plus \n, no controls;
; ( later maybe \b backspace and \u cancel )
;
; words are case-sensitivy and less than 16 characters;
;
; no need named-'pad' at end of even names;
;
; no multiuser, no multitask, no checks, not faster;
;
;----------------------------------------------------------------------
; For 6502:
;
; a 8-bit processor with 16-bit address space;
;
; the most significant byte is the page count;
;
; page zero and page one hardware reserved;
;
; hardware stack not used for this Forth;
;
; page zero is used as pseudo registers;
;
;----------------------------------------------------------------------
; For stacks:
;
; "when the heap moves forward, move the stack backward"
;
; as hardware stacks do:
; push is 'store and decrease', pull is 'increase and fetch',
;
; but see the notes for Devs.
;
; common memory model organization of Forth:
; [tib->...<-spt: user forth dictionary :here->pad...<-rpt]
; then backward stacks allow to use the slack space ...
;
; this 6502 Forth memory model blocked in pages of 256 bytes:
; [page0][page1][page2][core ... forth dictionary ...here...]
;
; At page2:
;
; |$00 tib> .. $50| <spt..sp0 $98| <rpt..rp0 $E0|pic> ..$FF|
;
; From page 3 onwards:
;
; |$0300 cold:, warm:, forth code, init: here> heap ... tail|
;
; PIC is a transient area of 32 bytes
; PAD could be allocated from here
;
;----------------------------------------------------------------------
; For Devs:
;
; the hello_world.forth file states that stacks works
; to allow : dup sp@ @ ; so sp must point to actual TOS.
;
; The movement will be:
; pull is 'fetch and increase'
; push is 'decrease and store'
;
; Never mess with two underscore variables;
;
; Not using smudge,
; colon saves "here" into "back" and
; semis loads "lastest" from "back";
;
; The dictionary needs SP and RP as full word.
;
; Do not risk to put stacks with $FF.
;
; Also carefull inspect if any label ends with $FF and move it;
;
; This source is hacked for use with Ca65.
;
;----------------------------------------------------------------------
;
; Stacks represented as (standart)
; S:(w1 w2 w3 -- u1 u2) R:(w1 w2 w3 -- u1 u2)
; before -- after, top at left.
;
;----------------------------------------------------------------------
;
; Stuff for ca65 compiler
;
.pC02
.feature c_comments
.feature string_escapes
.feature org_per_seg
.feature dollar_is_pc
.feature pc_assignment
;---------------------------------------------------------------------
; macros for dictionary, makes:
;
; h_name:
; .word link_to_previous_entry
; .byte strlen(name) + flags
; .byte name
; name:
;
; label for primitives
.macro makelabel arg1, arg2
.ident (.concat (arg1, arg2)):
.endmacro
; header for primitives
; the entry point for dictionary is h_~name~
; the entry point for code is ~name~
.macro def_word name, label, flag
makelabel "h_", label
.ident(.sprintf("H%04X", hcount + 1)) = *
.word .ident (.sprintf ("H%04X", hcount))
hcount .set hcount + 1
.byte .strlen(name) + flag + 0 ; nice trick !
.byte name
makelabel "", label
.endmacro
;---------------------------------------------------------------------
; variables for macros
hcount .set 0
H0000 = 0
;---------------------------------------------------------------------
; define thread code model
; MTC is default
; use_DTC = 1
; uncomment to include the extras (sic)
; use_extras = 1
; uncomment to include the extensions (sic)
; use_extensions = 1
;---------------------------------------------------------------------
/*
NOTES:
not finished yet :)
*/
;----------------------------------------------------------------------
;
; alias
; cell size, two bytes, 16-bit
CELL = 2
; highlander, immediate flag.
FLAG_IMM = 1<<7
; "all in" page $200
; terminal input buffer, forward
; getline, token, skip, scan, depends on page boundary $XX00
tib = $0200
; reserve 80 bytes, (72 is enough)
; moves forwards
tib_end = $50
; data stack, 36 cells,
; moves backwards, push decreases before copy
sp0 = $98
; return stack, 36 cells,
; moves backwards, push decreases before copy
rp0 = $E0
;----------------------------------------------------------------------
; no values here or must be a BSS
.segment "ZERO"
* = $40
nil: ; empty for fixed reference
; as user variables
; order matters for hello_world.forth !
; internal Forth
stat: .word $0 ; state at lsb, last size+flag at msb
toin: .word $0 ; toin next free byte in TIB
last: .word $0 ; last link cell
here: .word $0 ; next free cell in heap dictionary, aka dpt
; pointers registers
spt: .word $0 ; data stack base,
rpt: .word $0 ; return stack base
ipt: .word $0 ; instruction pointer
wrd: .word $0 ; word pointer
; free for use
fst: .word $0 ; first
snd: .word $0 ; second
trd: .word $0 ; third
fth: .word $0 ; fourth
; used, reserved
back: .word $0 ; hold 'here while compile
; for future expansion, reserved
head: .word $0 ; heap forward, also DP
tail: .word $0 ; heap backward
;----------------------------------------------------------------------
;.segment "ONCE"
; no rom code
;----------------------------------------------------------------------
;.segment "VECTORS"
; no boot code
;----------------------------------------------------------------------
.segment "CODE"
;
; leave space for page zero, hard stack,
; and buffer, locals, forth stacks
;
* = $300
main:
;----------------------------------------------------------------------
; common must
;
cold:
; disable interrupts
sei
; clear BCD
cld
; set real stack
ldx #$FF
txs
; enable interrupts
cli
;----------------------------------------------------------------------
warm:
; link list of headers
lda #>h_exit
sta last + 1
lda #<h_exit
sta last + 0
; next heap free cell, same as init:
lda #>end_of_forth + 1
sta here + 1
lda #0
sta here + 0
;---------------------------------------------------------------------
; supose never change
reset:
ldy #>tib
sty toin + 1
sty spt + 1
sty rpt + 1
abort:
ldy #<sp0
sty spt + 0
quit:
ldy #<rp0
sty rpt + 0
; clear tib stuff
stz tib + 0
; clear cursor
stz toin + 0
; stat is 'interpret' == \0
stz stat + 0
.byte $2c ; mask next two bytes, nice trick !
;---------------------------------------------------------------------
; the outer loop
resolvept:
.word okey
;---------------------------------------------------------------------
okey:
;; uncomment for feedback
; lda stat + 0
; bne resolve
; lda #'O'
; jsr putc
; lda #'K'
; jsr putc
; lda #10
; jsr putc
resolve:
; get a token
jsr token
sec
lda toin + 0
sub one + 0
sta trd + 0
;---------------------------------------------------------------------
find:
; load last
lda last + 0
sta snd + 0
lda last + 1
sta snd + 1
@loop:
; lsb linked list
lda snd + 0
sta wrd + 0
; verify \0x0
ora snd + 1
beq abort
; maybe to place a code for number?
; but not for now.
@each:
; msb linked list
lda snd + 1
sta wrd + 1
; update next link
ldx #(wrd) ; from
ldy #(snd) ; into
jsr copyfrom
; compare words
ldy #0
@equal:
lda (one), y
iny
cmp (wrd), y
beq @equal
cpy trd + 0
bne @loop
@done:
; save the flag, first byte is (size and flag)
lda (wrd), y
sta stat + 1
and #$7F ; mask immediate
; update wrd
;; ldx #(wrd) ; set already
;; addwx also clear carry
jsr addwx
;---------------------------------------------------------------------
eval:
; executing ? if == \0
lda stat + 0
beq execute
; immediate ? if < \0
lda stat + 1
bmi immediate
compile:
jsr wcomma
bra resolve
immediate:
execute:
lda #>resolvept
sta ipt + 1
lda #<resolvept
sta ipt + 0
;~~~~~~~~
.ifdef use_DTC
jmp (wrd)
.else
jmp pick
.endif
;~~~~~~~~
;---------------------------------------------------------------------
getch:
iny
lda tib, y
beq getline ; if \0
cmp #' '
rts
;---------------------------------------------------------------------
getline:
tay
; drop rts of getch
pla
pla
; leave the first
lda #' '
@loop:
; is valid
sta tib, y ; dummy store on first pass, overwritten
;tya
;adc #' '
;jsr putc
; end of buffer ?
; cpy #tib_end
; beq @ends
jsr getc
; 7-bit ascii only
; and #$7F
; less than space ends
cmp #' '
bpl @loop
; clear all if y eq \0
@ends:
; mark eol with \0
lda #0
sta tib, y
; start it
sta toin + 0
;---------------------------------------------------------------------
; in place every token,
; the counter is placed at last space before word
; no rewinds
; TIB must start at $XX00
token:
; last position on tib
ldy toin + 0
dey
@skip:
; skip spaces
jsr getch
beq @skip
; keep y == first non space
sty one + 0
@scan:
; scan spaces
jsr getch
bne @scan
; keep y == first space after
sty toin + 0
@done:
ldy toin + 1
sta one + 1
; done token
rts
;---------------------------------------------------------------------
; this code depends on systems or emulators
;
; lib6502 emulator
;
getc:
lda $E000
eofs:
; EOF ?
cmp #$FF ; also clean carry :)
beq byes
putc:
sta $E000
rts
; exit for emulator
byes:
jmp $0000
;
; lib6502 emulator
;---------------------------------------------------------------------
;---------------------------------------------------------------------
; decrement a word in page zero. offset by X
decwx:
lda 0, x
bne @ends
dec 1, x
@ends:
dec 0, x
rts
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
;incwx:
; inc 0, x
; bne @ends
; inc 1, x
;@ends:
; rts
;---------------------------------------------------------------------
; classic heap moves always forward
;
stawrd:
sta wrd + 1
wcomma:
ldy #(wrd)
comma:
ldx #(here)
; fall throught
;---------------------------------------------------------------------
; from a page zero address indexed by Y
; into a page zero indirect address indexed by X
copyinto:
lda 0, y
sta (0, x)
jsr incwx
lda 1, y
sta (0, x)
bra incwx
;---------------------------------------------------------------------
;
; generics
;
;---------------------------------------------------------------------
spush1:
ldy #(fst)
;---------------------------------------------------------------------
; push a cell
; from a page zero address indexed by Y
; into a page zero indirect address indexed by X
spush:
ldx #(spt)
; jmp push
.byte $2c ; mask next two bytes, nice trick !
rpush:
ldx #(rpt)
;---------------------------------------------------------------------
; classic stack backwards
push:
jsr decwx
lda 1, y
sta (0, x)
jsr decwx
lda 0, y
sta (0, x)
rts
;---------------------------------------------------------------------
spull2:
ldy #(snd)
jsr spull
; fall through
;---------------------------------------------------------------------
spull1:
ldy #(fst)
; fall through
;---------------------------------------------------------------------
; pull a cell
; from a page zero indirect address indexed by X
; into a page zero address indexed by y
spull:
ldx #(spt)
; jmp pull
.byte $2c ; mask next two bytes, nice trick !
rpull:
ldx #(rpt)
;---------------------------------------------------------------------
; classic stack backwards
pull: ; fall through, same as copyfrom
;---------------------------------------------------------------------
; from a page zero indirect address indexed by X
; into a page zero address indexed by y
copyfrom:
lda (0, x)
sta 0, y
jsr incwx
lda (0, x)
sta 1, y
; jmp incwx ; fall through
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
incwx:
lda #01
;---------------------------------------------------------------------
; add a byte to a word in page zero. offset by X
addwx:
clc
adc 0, x
sta 0, x
bcc @ends
inc 1, x
@ends:
rts
;---------------------------------------------------------------------
;
; the primitives,
; for stacks uses
; a address, c byte ascii, w signed word, u unsigned word
; cs counted string < 256, sz string with nul ends
;
;----------------------------------------------------------------------
.ifdef use_extras
;----------------------------------------------------------------------
; extras
;----------------------------------------------------------------------
; ( -- ) ae exit forth
def_word "bye", "bye", 0
jmp byes
;----------------------------------------------------------------------
; ( -- ) ae abort
def_word "abort", "abort_", 0
jmp abort
;----------------------------------------------------------------------
; ( -- ) ae list of data stack
def_word ".S", "splist", 0
lda spt + 0
sta fst + 0
lda spt + 1
sta fst + 1
lda #'S'
jsr putc
lda #sp0
jsr list
jmp next
;----------------------------------------------------------------------
; ( -- ) ae list of return stack
def_word ".R", "rplist", 0
lda rpt + 0
sta fst + 0
lda rpt + 1
sta fst + 1
lda #'R'
jsr putc
lda #>rp0
jsr list
jmp next
;----------------------------------------------------------------------
; ae list a sequence of references
list:
sec
sbc fst + 0
lsr
tax
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #' '
jsr putc
txa
jsr puthex
lda #' '
jsr putc
txa
beq @ends
ldy #0
@loop:
lda #' '
jsr putc
iny
lda (fst),y
jsr puthex
dey
lda (fst),y
jsr puthex
iny
iny
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ( -- ) dumps the user dictionary
def_word "dump", "dump", 0
lda #$0
sta fst + 0
lda #>ends + 1
sta fst + 1
ldx #(fst)
ldy #0
@loop:
lda (fst),y
jsr putc
jsr incwx
lda fst + 0
cmp here + 0
bne @loop
lda fst + 1
cmp here + 1
bne @loop
jmp next
;----------------------------------------------------------------------
; ( -- ) words in dictionary,
def_word "words", "words", 0
; load lastest
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
; load here
lda here + 1
sta trd + 1
lda here + 0
sta trd + 0
@loop:
; lsb linked list
lda snd + 0
sta fst + 0
; verify \0x0
ora snd + 1
beq @ends
; msb linked list
lda snd + 1
sta fst + 1
@each:
lda #10
jsr putc
; put address
lda #' '
jsr putc
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; put link
lda #' '
jsr putc
ldy #1
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
ldx #(fst)
lda #2
jsr addwx
; put size + flag, name
ldy #0
jsr show_name
; update
iny
tya
ldx #(fst)
jsr addwx
; show CFA
lda #' '
jsr putc
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; check if is a primitive
lda fst + 1
cmp #>ends + 1
bmi @continue
; list references
ldy #0
jsr show_refer
@continue:
lda snd + 0
sta trd + 0
lda snd + 1
sta trd + 1
ldy #0
lda (trd), y
sta snd + 0
iny
lda (trd), y
sta snd + 1
ldx #(trd)
lda #2
jsr addwx
jmp @loop
@ends:
jmp next
;----------------------------------------------------------------------
; ae put size and name
show_name:
lda #' '
jsr putc
lda (fst), y
jsr puthex
lda #' '
jsr putc
lda (fst), y
and #$7F
tax
@loop:
iny
lda (fst), y
jsr putc
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
show_refer:
; ae put references PFA ...
ldx #(fst)
@loop:
lda #' '
jsr putc
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #':'
jsr putc
iny
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
lda #2
jsr addwx
; check if ends
lda fst + 0
cmp trd + 0
bne @loop
lda fst + 1
cmp trd + 1
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ae seek for 'exit to ends a sequence of references
; max of 254 references in list
;
seek:
ldy #0
@loop1:
iny
beq @ends
lda (fst), y
cmp #>exit
bne @loop1
dey
lda (fst), y
cmp #<exit
beq @ends
iny
bne @loop1
@ends:
tya
lsr
rts
;----------------------------------------------------------------------
; ( u -- u ) print tos in hexadecimal, swaps order
def_word ".", "dot", 0
lda #' '
jsr putc
jsr spull1
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
jsr spush1
jmp next
;----------------------------------------------------------------------
; code a byte in ASCII hexadecimal
puthex:
pha
lsr
ror
ror
ror
jsr @conv
pla
@conv:
and #$0F
ora #$30
cmp #$3A
bcc @ends
adc #$06
@ends:
jmp putc
.endif
.ifdef numbers
;----------------------------------------------------------------------
; code a ASCII $FFFF hexadecimal in a byte
;
number:
ldy #0
jsr @very
asl
asl
asl
asl
sta fst + 1
iny
jsr @very
ora fst + 1
sta fst + 1
iny
jsr @very
asl
asl
asl
asl
sta fst + 0
iny
jsr @very
ora fst + 0
sta fst + 0
rts
@very:
lda (tout), y
sec
sbc #$30
bmi @erro
cmp #10
bcc @ends
sbc #$07
; any valid digit, A-Z, do not care
@ends:
rts
@erro:
pla
pla
rts
.endif
;---------------------------------------------------------------------
;
; extensions
;
;---------------------------------------------------------------------
.ifdef use_extensions
;---------------------------------------------------------------------
; ( w -- w/2 ) ; shift right
def_word "2/", "shr", 0
jsr spull1
lsr fst + 1
ror fst + 0
jmp this
;---------------------------------------------------------------------
; ( a -- ) execute a jump to a reference at top of data stack
def_word "exec", "exec", 0
jsr spull1
jmp (fst)
;---------------------------------------------------------------------
; ( -- ) execute a jump to a reference at IP
def_word ":$", "docode", 0
jmp (ipt)
;---------------------------------------------------------------------
; ( -- ) execute a jump to next
def_word ";$", "donext", 0
jmp next
.endif
;---------------------------------------------------------------------
; core primitives minimal
; start of dictionary
;---------------------------------------------------------------------
; ( -- u ) ; tos + 1 unchanged
def_word "key", "key", 0
jsr getc
sta fst + 0
; jmp this ; uncomment if char could be \0
bra this ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- NOT(w1 AND w2) )
def_word "nand", "nand", 0
jsr spull2
lda snd + 0
and fst + 0
eor #$FF
sta fst + 0
lda snd + 1
and fst + 1
eor #$FF
; jmp keeps ; uncomment if carry could be set
bra keeps ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- w1+w2 )
def_word "+", "plus", 0
jsr spull2
clc ; better safe than sorry
lda snd + 0
adc fst + 0
sta fst + 0
lda snd + 1
adc fst + 1
jmp keeps
;---------------------------------------------------------------------
; ( 0 -- $0000) | ( n -- $FFFF) not zero at top ?
def_word "0#", "zeroq", 0
jsr spull1
lda fst + 1
ora fst + 0
beq isfalse ; is \0 ?
istrue:
lda #$FF
isfalse:
sta fst + 0
jmp keeps
;---------------------------------------------------------------------
; ( -- state ) a variable return an reference
def_word "s@", "state", 0
lda #<stat
sta fst + 0
lda #>stat
; jmp keeps ; uncomment if stats not in page $0
beq keeps ; always taken
;---------------------------------------------------------------------
; ( a -- w ) ; w = [a]
def_word "@", "fetch", 0
fetchw:
jsr spull1
ldx #(fst)
ldy #(snd)
jsr copyfrom
; fall throught
;---------------------------------------------------------------------
copys:
lda 0, y
sta fst + 0
lda 1, y
keeps:
sta fst + 1
this:
jsr spush1
jmpnext:
bra next
;---------------------------------------------------------------------
; ( u -- ) ; tos + 1 unchanged
def_word "emit", "emit", 0
jsr spull1
lda fst + 0
jsr putc
; jmp next ; uncomment if carry could be set
bra next ; always taken
;---------------------------------------------------------------------
; ( a w -- ) ; [a] = w
def_word "!", "store", 0
storew:
jsr spull2
ldx #(snd)
ldy #(fst)
jsr copyinto
bra next ; always taken
;---------------------------------------------------------------------
; Thread Code Engine
;
; ipt is IP, wrd is W
;
; for reference:
;
; nest aka enter or docol,
; unnest aka exit or semis;
;
;---------------------------------------------------------------------
; ( -- )
def_word "exit", "exit", 0
unnest: ; exit
; pull, ipt = (rpt), rpt += 2
ldy #(ipt)
jsr rpull
next:
; wrd = (ipt) ; ipt += 2
ldx #(ipt)
ldy #(wrd)
jsr copyfrom
;~~~~~~~~
.ifdef use_DTC
pick:
jmp (wrd)
nest: ; enter
; push, *rp = ipt, rp -=2
ldy #(ipt)
jsr rpush
; pull (ip),
pla
sta ipt + 0
pla
sta ipt + 1
; 6502 trick: must increase return address
ldx #(ipt)
jsr incwx
bra next
.else
pick:
; compare pages (MSBs)
lda wrd + 1
cmp #>end_of_forth + 1
bmi jump
nest: ; enter
; push, *rp = ipt, rp -=2
ldy #(ipt)
jsr rpush
lda wrd + 0
sta ipt + 0
lda wrd + 1
sta ipt + 1
bra next
jump:
jmp (wrd)
.endif
;~~~~~~~~
;---------------------------------------------------------------------
def_word ";", "semis", FLAG_IMM
; update last, panic if colon not lead elsewhere
lda back + 0
sta last + 0
lda back + 1
sta last + 1
; stat is 'interpret'
lda #0
sta stat + 0
; compound words must ends with exit
finish:
lda #<exit
sta wrd + 0
lda #>exit
sta wrd + 1
jsr wcomma
bra next ; always taken
;---------------------------------------------------------------------
def_word ":", "colon", 0
; save here, panic if semis not follow elsewhere
lda here + 0
sta back + 0
lda here + 1
sta back + 1
; stat is 'compile'
lda #1
sta stat + 0
lda #'C'
jsr putc
@header:
; copy last into (here)
ldy #(last)
jsr comma
; get following token
jsr token
; copy it
ldy #0
@loop:
lda (tout), y
cmp #33 ; stops at space + 1
bmi @ends
sta (here), y
iny
bne @loop
@ends:
; update here
tya
ldx #(here)
jsr addwx
;~~~~~~~~
.ifdef use_DTC
; magic NOP (EA) JSR (20), at CFA cell
; magic = $EA20
magic = $20EA
; inserts the nop call
lda #<magic
sta wrd + 0
lda #>magic
jsr stawrd
; inserts the reference
lda #<nest
sta wrd + 0
lda #>nest
jsr stawrd
.endif
;~~~~~~~~
; done
bra next ; always taken
;----------------------------------------------------------------------
; ( -- ) dumps all
def_word "dump", "dump", 0
lda #$0
sta fst + 0
sta fst + 1
ldx #(fst)
ldy #0
@loop:
lda (fst), y
jsr putc
jsr incwx
lda fst + 0
cmp here + 0
bne @loop
lda fst + 1
cmp here + 1
bne @loop
jmp next
;-----------------------------------------------------------------------
; BEWARE, MUST BE AT END! MINIMAL THREAD CODE DEPENDS ON IT!
end_of_forth:
;-----------------------------------------------------------------------
; anything above is not a primitive
;----------------------------------------------------------------------
|
agsb/milliForth-6502
| 29,612
|
stub/6502-hash/sector-6502.s
|
;---------------------------------------------------------------------
;
; Copyright 2023 Alvaro Gomes Sobral Barcellos <@agsb>
;
; This program is free software: you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation, either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
;
;----------------------------------------------------------------------
;
;----------------------------------------------------------------------
;
; A MilliForth for 6502
;
; original for the 6502, by Alvaro G. S. Barcellos, 2023
;
; https://github.com/agsb
; see the disclaimer file in this repo for more information.
;
; SectorForth and MilliForth was made for x86 arch
; and uses full 16-bit registers
;
; The way at 6502 is use page zero and lots of lda/sta
;
; Focus in size not performance.
;
; why ? For understand better my skills, 6502 code and thread codes
;
; how ? Programming a new Forth for old 8-bit cpu emulator
;
; what ? Design the best minimal Forth engine and vocabulary
;
;----------------------------------------------------------------------
; Changes:
;
; all data (36 cells) and return (36 cells) stacks, TIB (80 bytes)
; and PIC (32 bytes) are in same page $200, 256 bytes;
;
; TIB and PIC grows forward, stacks grows backwards;
;
; no overflow or underflow checks;
;
; the header order is LINK, SIZE+FLAG, NAME.
;
; only IMMEDIATE flag used as $80, no hide, no compile;
;
; As ANSI Forth 1994: FALSE is $0000 ; TRUE is $FFFF ;
;
; This version uses hash djb2 instead of size+name
;
;----------------------------------------------------------------------
; Remarks:
;
; this code uses Minimal Indirect Thread Code.
;
; use a classic cell with 16-bits.
;
; no TOS register, all values keeped at stacks;
;
; TIB (terminal input buffer) is like a stream;
;
; Chuck Moore uses 64 columns, be wise, obey rule 72 CPL;
;
; words must be between spaces, before and after;
;
; no line wrap, do not break words between lines;
;
; only 7-bit ASCII characters, plus \n, no controls;
; ( later maybe \b backspace and \u cancel )
;
; words are case-sensitivy and less than 16 characters;
;
; no need named-'pad' at end of even names;
;
; no multiuser, no multitask, no checks, not faster;
;
;----------------------------------------------------------------------
; For 6502:
;
; a 8-bit processor with 16-bit address space;
;
; the most significant byte is the page count;
;
; page zero and page one hardware reserved;
;
; hardware stack not used for this Forth;
;
; page zero is used as pseudo registers;
;
;----------------------------------------------------------------------
; For stacks:
;
; "when the heap moves forward, move the stack backward"
;
; as hardware stacks do:
; push is 'store and decrease', pull is 'increase and fetch',
;
; but see the notes for Devs.
;
; common memory model organization of Forth:
; [tib->...<-spt: user forth dictionary :here->pad...<-rpt]
; then backward stacks allow to use the slack space ...
;
; this 6502 Forth memory model blocked in pages of 256 bytes:
; [page0][page1][page2][core ... forth dictionary ...here...]
;
; At page2:
;
; |$00 tib> .. $50| <spt..sp0 $98| <rpt..rp0 $E0|pic> ..$FF|
;
; From page 3 onwards:
;
; |$0300 cold:, warm:, forth code, init: here> heap ... tail|
;
; PIC is a transient area of 32 bytes
; PAD could be allocated from here
;
;----------------------------------------------------------------------
; For Devs:
;
; the hello_world.forth file states that stacks works
; to allow : dup sp@ @ ; so sp must point to actual TOS.
;
; The movement will be:
; pull is 'fetch and increase'
; push is 'decrease and store'
;
; Never mess with two underscore variables;
;
; Not using smudge,
; colon saves "here" into "head" and
; semis loads "lastest" from "head";
;
; Do not risk to put stacks with $FF.
;
; Also carefull inspect if any label ends with $FF and move it;
;
; This source is hacked for use with Ca65.
;
;----------------------------------------------------------------------
;
; Stacks represented as (standart)
; S:(w1 w2 w3 -- u1 u2) R:(w1 w2 w3 -- u1 u2)
; before -- after, top at left.
;
;----------------------------------------------------------------------
;
; Stuff for ca65 compiler
;
.p02
.feature c_comments
.feature string_escapes
.feature org_per_seg
.feature dollar_is_pc
.feature pc_assignment
;---------------------------------------------------------------------
; macros for dictionary, makes:
;
; h_name:
; .word link_to_previous_entry
; .dword hash
; name:
;
; label for primitives
.macro makelabel arg1, arg2
.ident (.concat (arg1, arg2)):
.endmacro
; header for primitives
; the entry point for dictionary is h_~name~
; the entry point for code is ~name~
.macro def_word name, label, hashed
makelabel "h_", label
.ident(.sprintf("H%04X", hcount + 1)) = *
.word .ident (.sprintf ("H%04X", hcount))
hcount .set hcount + 1
.dword hashed
makelabel "", label
.endmacro
;---------------------------------------------------------------------
; variables for macro def_word
hcount .set 0
H0000 = 0
;---------------------------------------------------------------------
; uncomment to include the extras (sic)
; use_extras = 1
; uncomment to include the extensions (sic)
; use_extensions = 1
;----------------------------------------------------------------------
;
; alias
; cell size, two bytes, 16-bit
CELL = 2
; highlander, immediate flag.
FLAG_IMM = $8000
;---------------------------------------------------------------------
; primitives djb2 hash cleared of bit 16
; semmis is immediate (ORA $8000)
;
hash_emit = $07D0
hash_store = $3584
hash_plus = $358E
hash_colon = $359F
hash_semis = $B59E
hash_fetch = $35E5
hash_exit = $3E85
hash_bye = $4AFB
hash_zeroq = $6816
hash_key = $6D32
hash_userq = $6F90
hash_nand = $7500
;----------------------------------------------------------------------
.segment "ZERO"
; order matters for hello_world.forth !
;----------------------------------------------------------------------
* = $D0
; as user variables
stat: .word $0 ; state at lsb, last size+flag at msb
toin: .word $0 ; toin next free byte in TIB
last: .word $0 ; last link cell
here: .word $0 ; next free cell in heap dictionary, aka dpt
sptr: .word $0 ; data stack base,
rptr: .word $0 ; return stack base
head: .word $0 ; heap forward
tail: .word $0 ; heap backward
;----------------------------------------------------------------------
* = $E0
; free for locals
locals:
.word $0
.word $0
.word $0
.word $0
.word $0
.word $0
; hash djb2 buffer
hashs:
.word $0
.word $0
;----------------------------------------------------------------------
* = $F0
; pointers registers
ipt: .word $0 ; instruction pointer
wrd: .word $0 ; word pointer
fst: .word $0 ; first
snd: .word $0 ; second
trd: .word $0 ; third
fth: .word $0 ; fourth
; temporary
a_save: .byte $0
y_save: .byte $0
x_save: .byte $0
s_save: .byte $0
;----------------------------------------------------------------------
* = $100
; system stack, reserve
;
system: .res 256
;----------------------------------------------------------------------
;.segment "ONCE"
; no rom code
;----------------------------------------------------------------------
;.segment "VECTORS"
; no boot code
;----------------------------------------------------------------------
.segment "CODE"
;----------------------------------------------------------------------
; leave space for page zero, hard stack,
; and buffer, locals, forth stacks
; "all in" page $200
* = $200
; terminal input buffer, forward, must be at page boundary $00
; reserve 80 bytes, (but 72 is enough), moves forwards
tib = $0200
; data stack, moves backwards, 36 words
sp0 = $98
; return stack, moves backwards, 36 words
rp0 = $E0
;----------------------------------------------------------------------
; code start
* = $300
;----------------------------------------------------------------------
main:
;----------------------------------------------------------------------
; common must
;
cold:
; disable interrupts
sei
; clear BCD
cld
; set real stack
ldx #$FF
txs
; enable interrupts
cli
;----------------------------------------------------------------------
h_last = h_exit
h_here = ends
;----------------------------------------------------------------------
warm:
; link list of headers
lda #>h_last
sta last + 1
lda #<h_last
sta last + 0
; next heap free cell, take a page
lda #>h_here
sta here + 1
lda #<h_here
sta here + 0
;---------------------------------------------------------------------
; supose never change
reset:
ldy #>tib
sty toin + 1
sty sptr + 1
sty rptr + 1
; when not found in dictionary
miss:
; maybe do numbers ?
abort:
ldy #<sp0
sty sptr + 0
quit:
ldy #<rp0
sty rptr + 0
; reset tib
ldy #0
; clear tib stuff
sty tib + 0
; clear cursor
sty toin + 0
; stat is 'interpret' == \0
sty stat + 0
.byte $2c ; mask next two bytes, nice trick !
;---------------------------------------------------------------------
; the outer loop
resolvept:
.word okey
;---------------------------------------------------------------------
okey:
; uncomment for feedback
; lda stat + 0
; bne resolve
;
; lda #'O'
; jsr putchar
; lda #'K'
; jsr putchar
; lda #10
; jsr putchar
resolve:
; get a token and receive a hash :)
;
jsr token
; lda #'P'
; jsr putchar
tick:
; load last entry
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
@loop:
; lsb linked list
lda snd + 0
sta wrd + 0
; verify \0x0
ora snd + 1
beq miss
; maybe to place a code for number?
; but not for now.
; msb linked list
lda snd + 1
sta wrd + 1
; update next link in snd
ldx #(wrd) ; from
ldy #(snd) ; into
jsr pull
; compare hashes
ldy #0
lda (wrd), y
cmp (hashs), y
bne @loop
iny
lda (wrd), y
and #127
cmp (hashs), y
bne @loop
@done:
; update wrd to code
lda #2
ldx #(wrd)
jsr addwx
eval:
; executing ? if == \0
lda stat + 0
beq execute
; immediate ? if < \0
lda stat + 1
bmi immediate
compile:
; lda #'C'
; jsr putchar
jsr docomma
bcc resolve
immediate:
execute:
; lda #'E'
; jsr putchar
lda #>resolvept
sta ipt + 1
lda #<resolvept
sta ipt + 0
jmp pick
;---------------------------------------------------------------------
; in place every token,
; the counter is placed at last space before word
; no rewinds
token:
; last position on tib
ldy toin + 0
@skip:
lda tib, y
beq gets
iny
eor #' '
beq @skip
hashs_DJB2 = 5381
@hash:
lda #<hashs_DJB2
sta hashs + 2
sta hashs + 0
lda #>hashs_DJB2
sta hashs + 3
sta hashs + 1
@read:
lda tib, y
cmp #' '
beq @ends
pha
; multiply by 32
ldx #5
clc
@loop:
lda hashs + 0
rol
sta hashs + 0
lda hashs + 1
rol
sta hashs + 1
dex
bne @loop
; then add, total 33
clc
lda hashs + 2
adc hashs + 0
sta hashs + 0
lda hashs + 3
adc hashs + 1
sta hashs + 1
; xor with character
pla
eor hashs + 0
sta hashs + 0
iny
bne @read
@ends:
; clear MSB bit
lda #127
and hashs + 1
sta hashs + 1
; save toin
sty toin + 0
rts
;---------------------------------------------------------------------
gets:
; start with space
ldy #0
lda #' '
@loop:
; is valid
sta tib, y
iny
jsr getchar
; 7-bit ascii only
and #$7F
; unix \n, ^J
cmp #10
bne @loop
@ends:
; grace \b
lda #' '
sta tib, y ; ends with space
; grace \0
lda #0
sta tib + 1, y
; start it
sta toin + 0
bcc token
;---------------------------------------------------------------------
; this code depends on systems or emulators
;
; lib6502 emulator
;
getchar:
lda $E000
eofs:
; EOF ?
cmp #$FF ; also clean carry :)
beq byes
putchar:
sta $E000
rts
; exit for emulator
byes:
jmp $0000
;
; lib6502 emulator
;---------------------------------------------------------------------
;---------------------------------------------------------------------
; decrement a word in page zero. offset by X
decwx:
lda 0, x
bne @ends
dec 1, x
@ends:
dec 0, x
rts
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
;incwx:
; inc 0, x
; bne @ends
; inc 1, x
;@ends:
; rts
;---------------------------------------------------------------------
; classic heap moves always forward
;
docomma:
ldx #(here)
; fall throught
;---------------------------------------------------------------------
; from a page zero address indexed by Y
; into a page zero indirect address indexed by X
copyinto:
lda 0, y
sta (0, x)
jsr incwx
lda 1, y
sta (0, x)
jmp incwx
;---------------------------------------------------------------------
;
; generics
;
;---------------------------------------------------------------------
; push a cell
; from a page zero address indexed by Y
; into a page zero indirect address indexed by X
spush1:
ldy #(fst)
;---------------------------------------------------------------------
spush:
ldx #(sptr)
; jmp push
.byte $2c ; mask next two bytes, nice trick !
;---------------------------------------------------------------------
rpush:
ldx #(rptr)
;---------------------------------------------------------------------
; from a page zero indirect address indexed by Y
; into a page zero address indexed by X
; also decrease address in X
push:
jsr decwx
lda 1, y
sta (0, x)
jsr decwx
lda 0, y
sta (0, x)
rts
;---------------------------------------------------------------------
; pull a cell
; from a page zero indirect address indexed by X
; into a page zero address indexed by y
;---------------------------------------------------------------------
spull2:
ldy #(snd)
jsr spull
; fall through
;---------------------------------------------------------------------
spull1:
ldy #(fst)
; fall through
;---------------------------------------------------------------------
spull:
ldx #(sptr)
; jmp pull
.byte $2c ; mask next two bytes, nice trick !
;---------------------------------------------------------------------
rpull:
ldx #(rptr)
;---------------------------------------------------------------------
; from a page zero indirect address indexed by X
; into a page zero address indexed by y
; also decrease address in X
pull:
lda (0, x)
sta 0, y
jsr incwx
lda (0, x)
sta 1, y
; jmp incwx ; fall through
;---------------------------------------------------------------------
; increment a word in page zero. offset by X
incwx:
lda #01
;---------------------------------------------------------------------
; add a byte to a word in page zero. offset by X
addwx:
clc
adc 0, x
sta 0, x
bcc @ends
inc 1, x
clc ; keep carry clean
@ends:
rts
;---------------------------------------------------------------------
;
; the primitives,
; for stacks uses
; a address, c byte ascii, w signed word, u unsigned word
; cs counted string < 256, sz string with nul ends
;
;----------------------------------------------------------------------
.ifdef use_extras
;----------------------------------------------------------------------
; extras
;----------------------------------------------------------------------
; ( -- ) ae exit forth
def_word "bye", "bye", 0
jmp byes
;----------------------------------------------------------------------
; ( -- ) ae abort
def_word "abort", "abort_", 0
jmp abort
;----------------------------------------------------------------------
; ( -- ) ae list of data stack
def_word ".S", "splist", 0
lda spt + 0
sta fst + 0
lda spt + 1
sta fst + 1
lda #'S'
jsr putchar
lda #<sp0
jsr list
jmp next
;----------------------------------------------------------------------
; ( -- ) ae list of return stack
def_word ".R", "rplist", 0
lda rpt + 0
sta fst + 0
lda rpt + 1
sta fst + 1
lda #'R'
jsr putchar
lda #<rp0
jsr list
jmp next
;----------------------------------------------------------------------
; ae list a sequence of references
list:
sec
sbc fst + 0
lsr
tax
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #' '
jsr putchar
txa
jsr puthex
lda #' '
jsr putchar
txa
beq @ends
ldy #0
@loop:
lda #' '
jsr putchar
iny
lda (fst),y
jsr puthex
dey
lda (fst),y
jsr puthex
iny
iny
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ( -- ) dumps the user dictionary
def_word "dump", "dump", 0
lda #$0
sta fst + 0
lda #>ends + 1
sta fst + 1
ldx #(fst)
ldy #0
@loop:
lda (fst),y
jsr putchar
jsr incwx
lda fst + 0
cmp here + 0
bne @loop
lda fst + 1
cmp here + 1
bne @loop
clc ; clean
jmp next
;----------------------------------------------------------------------
; ( -- ) words in dictionary,
def_word "words", "words", 0
; load lastest
lda last + 1
sta snd + 1
lda last + 0
sta snd + 0
; load here
lda here + 1
sta trd + 1
lda here + 0
sta trd + 0
@loop:
; lsb linked list
lda snd + 0
sta fst + 0
; verify \0x0
ora snd + 1
beq @ends
; msb linked list
lda snd + 1
sta fst + 1
@each:
lda #10
jsr putchar
; put address
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; put link
lda #' '
jsr putchar
ldy #1
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
ldx #(fst)
lda #2
jsr addwx
; put size + flag, name
ldy #0
jsr show_name
; update
iny
tya
ldx #(fst)
jsr addwx
; show CFA
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
; check if is a primitive
lda fst + 1
cmp #>ends + 1
bmi @continue
; list references
ldy #0
jsr show_refer
@continue:
lda snd + 0
sta trd + 0
lda snd + 1
sta trd + 1
ldy #0
lda (trd), y
sta snd + 0
iny
lda (trd), y
sta snd + 1
ldx #(trd)
lda #2
jsr addwx
jmp @loop
@ends:
clc ; clean
jmp next
;----------------------------------------------------------------------
; ae put size and name
show_name:
lda #' '
jsr putchar
lda (fst), y
jsr puthex
lda #' '
jsr putchar
lda (fst), y
and #$7F
tax
@loop:
iny
lda (fst), y
jsr putchar
dex
bne @loop
@ends:
rts
;----------------------------------------------------------------------
show_refer:
; ae put references PFA ...
ldx #(fst)
@loop:
lda #' '
jsr putchar
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
lda #':'
jsr putchar
iny
lda (fst), y
jsr puthex
dey
lda (fst), y
jsr puthex
lda #2
jsr addwx
; check if ends
lda fst + 0
cmp trd + 0
bne @loop
lda fst + 1
cmp trd + 1
bne @loop
@ends:
rts
;----------------------------------------------------------------------
; ae seek for 'exit to ends a sequence of references
; max of 254 references in list
;
seek:
ldy #0
@loop1:
iny
beq @ends
lda (fst), y
cmp #>exit
bne @loop1
dey
lda (fst), y
cmp #<exit
beq @ends
iny
bne @loop1
@ends:
tya
lsr
clc ; clean
rts
;----------------------------------------------------------------------
; ( u -- u ) print tos in hexadecimal, swaps order
def_word ".", "dot", 0
lda #' '
jsr putchar
jsr spull1
lda fst + 1
jsr puthex
lda fst + 0
jsr puthex
jsr spush1
jmp next
;----------------------------------------------------------------------
; code a byte in ASCII hexadecimal
puthex:
pha
lsr
ror
ror
ror
jsr @conv
pla
@conv:
and #$0F
ora #$30
cmp #$3A
bcc @ends
adc #$06
@ends:
clc ; clean
jmp putchar
.endif
.ifdef numbers
;----------------------------------------------------------------------
; code a ASCII $FFFF hexadecimal in a byte
;
number:
ldy #0
jsr @very
asl
asl
asl
asl
sta fst + 1
iny
jsr @very
ora fst + 1
sta fst + 1
iny
jsr @very
asl
asl
asl
asl
sta fst + 0
iny
jsr @very
ora fst + 0
sta fst + 0
clc ; clean
rts
@very:
lda (tout), y
sec
sbc #$30
bmi @erro
cmp #10
bcc @ends
sbc #$07
; any valid digit, A-Z, do not care
@ends:
rts
@erro:
pla
pla
rts
.endif
;---------------------------------------------------------------------
;
; extensions
;
;---------------------------------------------------------------------
.ifdef use_extensions
;---------------------------------------------------------------------
; ( w -- w/2 ) ; shift right
def_word "2/", "shr", 0
jsr spull1
lsr fst + 1
ror fst + 0
jmp this
;---------------------------------------------------------------------
; ( a -- ) execute a jump to a reference at top of data stack
def_word "exec", "exec", 0
jsr spull1
jmp (fst)
;---------------------------------------------------------------------
; ( -- ) execute a jump to a reference at IP
def_word ":$", "docode", 0
jmp (ipt)
;---------------------------------------------------------------------
; ( -- ) execute a jump to next
def_word ";$", "donext", 0
jmp next
.endif
;---------------------------------------------------------------------
; core primitives minimal
; start of dictionary
;---------------------------------------------------------------------
; ( -- u ) ; tos + 1 unchanged
def_word "key", "key", hash_key
jsr getchar
sta fst + 0
; jmp this ; uncomment if char could be \0
bne this ; always taken
;---------------------------------------------------------------------
; ( u -- ) ; tos + 1 unchanged
def_word "emit", "emit", hash_emit
jsr spull1
lda fst + 0
jsr putchar
; jmp next ; uncomment if carry could be set
bcc jmpnext ; always taken
;---------------------------------------------------------------------
; ( a w -- ) ; [a] = w
def_word "!", "store", hash_store
storew:
jsr spull2
ldx #(snd)
ldy #(fst)
jsr copyinto
; jmp next ; uncomment if carry could be set
bcc jmpnext ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- NOT(w1 AND w2) )
def_word "nand", "nand", hash_nand
jsr spull2
lda snd + 0
and fst + 0
eor #$FF
sta fst + 0
lda snd + 1
and fst + 1
eor #$FF
; jmp keeps ; uncomment if carry could be set
bcc keeps ; always taken
;---------------------------------------------------------------------
; ( w1 w2 -- w1+w2 )
def_word "+", "plus", hash_plus
jsr spull2
clc ; better safe than sorry
lda snd + 0
adc fst + 0
sta fst + 0
lda snd + 1
adc fst + 1
jmp keeps
;---------------------------------------------------------------------
; ( a -- w ) ; w = [a]
def_word "@", "fetch", hash_fetch
fetchw:
jsr spull1
ldx #(fst)
ldy #(snd)
jsr pull
; fall throught
;---------------------------------------------------------------------
copys:
lda 0, y
sta fst + 0
lda 1, y
keeps:
sta fst + 1
this:
jsr spush1
jmpnext:
jmp next
;---------------------------------------------------------------------
; ( 0 -- $0000) | ( n -- $FFFF) not zero at top ?
def_word "0#", "zeroq", hash_zeroq
jsr spull1
lda fst + 1
ora fst + 0
beq isfalse ; is \0 ?
istrue:
lda #$FF
isfalse:
sta fst + 0
jmp keeps
;---------------------------------------------------------------------
; ( -- state ) a variable return an reference
def_word "u@", "state", hash_userq
lda #<stat
sta fst + 0
lda #>stat
beq keeps ; always taken
;---------------------------------------------------------------------
def_word ";", "semis", hash_semis
; update last, panic if colon not lead elsewhere
lda head + 0
sta last + 0
lda head + 1
sta last + 1
; stat is 'interpret'
lda #0
sta stat + 0
; compound words must ends with exit
lda #<exit
sta fst + 0
lda #>exit
sta fst + 1
ldy #(fst)
finish:
jsr docomma
bcc next ; always taken
;---------------------------------------------------------------------
def_word ":", "colon", hash_colon
; save here, panic if semis not follow elsewhere
lda here + 0
sta head + 0
lda here + 1
sta head + 1
; stat is 'compile'
lda #1
sta stat + 0
@header:
; copy last into (here)
ldy #(last)
jsr docomma
; get a token and receive a hash :)
jsr token
ldy #(hashs)
@ends:
bcc finish
;---------------------------------------------------------------------
; Thread Code Engine
;
; ipt is IP, wrd is W
;
; for reference:
;
; nest aka enter or docol,
; unnest aka exit or semis;
;
;---------------------------------------------------------------------
; ( -- )
def_word "exit", "exit", hash_exit
unnest: ; exit
; pull, ipt = (rpt), rpt += 2
ldy #(ipt)
jsr rpull
next:
; wrd = (ipt) ; ipt += 2
ldx #(ipt)
ldy #(wrd)
jsr pull
pick:
; compare pages (MSBs)
lda wrd + 1
cmp #>ends + 1
bmi jump
nest: ; enter
; push, *rp = ipt, rp -=2
ldy #(ipt)
jsr rpush
lda wrd + 0
sta ipt + 0
lda wrd + 1
sta ipt + 1
jmp next
jump:
jmp (wrd)
;-----------------------------------------------------------------------
; BEWARE, MUST BE AT END! MINIMAL THREAD CODE DEPENDS ON IT!
ends:
;-----------------------------------------------------------------------
; anything above is not a primitive
;----------------------------------------------------------------------
|
AgoraIO-Usecase/HQ
| 7,228
|
libobs-for-HQ-Windows/deps/lzma/liblzma/check/crc32_x86.S
|
/*
* Speed-optimized CRC32 using slicing-by-eight algorithm
*
* This uses only i386 instructions, but it is optimized for i686 and later
* (including e.g. Pentium II/III/IV, Athlon XP, and Core 2). For i586
* (e.g. Pentium), slicing-by-four would be better, and even the C version
* of slicing-by-eight built with gcc -march=i586 tends to be a little bit
* better than this. Very few probably run this code on i586 or older x86
* so this shouldn't be a problem in practice.
*
* Authors: Igor Pavlov (original version)
* Lasse Collin (AT&T syntax, PIC support, better portability)
*
* This file has been put into the public domain.
* You can do whatever you want with this file.
*
* This code needs lzma_crc32_table, which can be created using the
* following C code:
uint32_t lzma_crc32_table[8][256];
void
init_table(void)
{
// IEEE-802.3
static const uint32_t poly32 = UINT32_C(0xEDB88320);
// Castagnoli
// static const uint32_t poly32 = UINT32_C(0x82F63B78);
// Koopman
// static const uint32_t poly32 = UINT32_C(0xEB31D82E);
for (size_t s = 0; s < 8; ++s) {
for (size_t b = 0; b < 256; ++b) {
uint32_t r = s == 0 ? b : lzma_crc32_table[s - 1][b];
for (size_t i = 0; i < 8; ++i) {
if (r & 1)
r = (r >> 1) ^ poly32;
else
r >>= 1;
}
lzma_crc32_table[s][b] = r;
}
}
}
* The prototype of the CRC32 function:
* extern uint32_t lzma_crc32(const uint8_t *buf, size_t size, uint32_t crc);
*/
/*
* On some systems, the functions need to be prefixed. The prefix is
* usually an underscore.
*/
#ifndef __USER_LABEL_PREFIX__
# define __USER_LABEL_PREFIX__
#endif
#define MAKE_SYM_CAT(prefix, sym) prefix ## sym
#define MAKE_SYM(prefix, sym) MAKE_SYM_CAT(prefix, sym)
#define LZMA_CRC32 MAKE_SYM(__USER_LABEL_PREFIX__, lzma_crc32)
#define LZMA_CRC32_TABLE MAKE_SYM(__USER_LABEL_PREFIX__, lzma_crc32_table)
/*
* Solaris assembler doesn't have .p2align, and Darwin uses .align
* differently than GNU/Linux and Solaris.
*/
#if defined(__APPLE__) || defined(__MSDOS__)
# define ALIGN(pow2, abs) .align pow2
#else
# define ALIGN(pow2, abs) .align abs
#endif
.text
.globl LZMA_CRC32
#if !defined(__APPLE__) && !defined(_WIN32) && !defined(__CYGWIN__) \
&& !defined(__MSDOS__)
.type LZMA_CRC32, @function
#endif
ALIGN(4, 16)
LZMA_CRC32:
/*
* Register usage:
* %eax crc
* %esi buf
* %edi size or buf + size
* %ebx lzma_crc32_table
* %ebp Table index
* %ecx Temporary
* %edx Temporary
*/
pushl %ebx
pushl %esi
pushl %edi
pushl %ebp
movl 0x14(%esp), %esi /* buf */
movl 0x18(%esp), %edi /* size */
movl 0x1C(%esp), %eax /* crc */
/*
* Store the address of lzma_crc32_table to %ebx. This is needed to
* get position-independent code (PIC).
*
* The PIC macro is defined by libtool, while __PIC__ is defined
* by GCC but only on some systems. Testing for both makes it simpler
* to test this code without libtool, and keeps the code working also
* when built with libtool but using something else than GCC.
*
* I understood that libtool may define PIC on Windows even though
* the code in Windows DLLs is not PIC in sense that it is in ELF
* binaries, so we need a separate check to always use the non-PIC
* code on Windows.
*/
#if (!defined(PIC) && !defined(__PIC__)) \
|| (defined(_WIN32) || defined(__CYGWIN__))
/* Not PIC */
movl $ LZMA_CRC32_TABLE, %ebx
#elif defined(__APPLE__)
/* Mach-O */
call .L_get_pc
.L_pic:
leal .L_lzma_crc32_table$non_lazy_ptr-.L_pic(%ebx), %ebx
movl (%ebx), %ebx
#else
/* ELF */
call .L_get_pc
addl $_GLOBAL_OFFSET_TABLE_, %ebx
movl LZMA_CRC32_TABLE@GOT(%ebx), %ebx
#endif
/* Complement the initial value. */
notl %eax
ALIGN(4, 16)
.L_align:
/*
* Check if there is enough input to use slicing-by-eight.
* We need 16 bytes, because the loop pre-reads eight bytes.
*/
cmpl $16, %edi
jb .L_rest
/* Check if we have reached alignment of eight bytes. */
testl $7, %esi
jz .L_slice
/* Calculate CRC of the next input byte. */
movzbl (%esi), %ebp
incl %esi
movzbl %al, %ecx
xorl %ecx, %ebp
shrl $8, %eax
xorl (%ebx, %ebp, 4), %eax
decl %edi
jmp .L_align
ALIGN(2, 4)
.L_slice:
/*
* If we get here, there's at least 16 bytes of aligned input
* available. Make %edi multiple of eight bytes. Store the possible
* remainder over the "size" variable in the argument stack.
*/
movl %edi, 0x18(%esp)
andl $-8, %edi
subl %edi, 0x18(%esp)
/*
* Let %edi be buf + size - 8 while running the main loop. This way
* we can compare for equality to determine when exit the loop.
*/
addl %esi, %edi
subl $8, %edi
/* Read in the first eight aligned bytes. */
xorl (%esi), %eax
movl 4(%esi), %ecx
movzbl %cl, %ebp
.L_loop:
movl 0x0C00(%ebx, %ebp, 4), %edx
movzbl %ch, %ebp
xorl 0x0800(%ebx, %ebp, 4), %edx
shrl $16, %ecx
xorl 8(%esi), %edx
movzbl %cl, %ebp
xorl 0x0400(%ebx, %ebp, 4), %edx
movzbl %ch, %ebp
xorl (%ebx, %ebp, 4), %edx
movzbl %al, %ebp
/*
* Read the next four bytes, for which the CRC is calculated
* on the next interation of the loop.
*/
movl 12(%esi), %ecx
xorl 0x1C00(%ebx, %ebp, 4), %edx
movzbl %ah, %ebp
shrl $16, %eax
xorl 0x1800(%ebx, %ebp, 4), %edx
movzbl %ah, %ebp
movzbl %al, %eax
movl 0x1400(%ebx, %eax, 4), %eax
addl $8, %esi
xorl %edx, %eax
xorl 0x1000(%ebx, %ebp, 4), %eax
/* Check for end of aligned input. */
cmpl %edi, %esi
movzbl %cl, %ebp
jne .L_loop
/*
* Process the remaining eight bytes, which we have already
* copied to %ecx and %edx.
*/
movl 0x0C00(%ebx, %ebp, 4), %edx
movzbl %ch, %ebp
xorl 0x0800(%ebx, %ebp, 4), %edx
shrl $16, %ecx
movzbl %cl, %ebp
xorl 0x0400(%ebx, %ebp, 4), %edx
movzbl %ch, %ebp
xorl (%ebx, %ebp, 4), %edx
movzbl %al, %ebp
xorl 0x1C00(%ebx, %ebp, 4), %edx
movzbl %ah, %ebp
shrl $16, %eax
xorl 0x1800(%ebx, %ebp, 4), %edx
movzbl %ah, %ebp
movzbl %al, %eax
movl 0x1400(%ebx, %eax, 4), %eax
addl $8, %esi
xorl %edx, %eax
xorl 0x1000(%ebx, %ebp, 4), %eax
/* Copy the number of remaining bytes to %edi. */
movl 0x18(%esp), %edi
.L_rest:
/* Check for end of input. */
testl %edi, %edi
jz .L_return
/* Calculate CRC of the next input byte. */
movzbl (%esi), %ebp
incl %esi
movzbl %al, %ecx
xorl %ecx, %ebp
shrl $8, %eax
xorl (%ebx, %ebp, 4), %eax
decl %edi
jmp .L_rest
.L_return:
/* Complement the final value. */
notl %eax
popl %ebp
popl %edi
popl %esi
popl %ebx
ret
#if defined(PIC) || defined(__PIC__)
ALIGN(4, 16)
.L_get_pc:
movl (%esp), %ebx
ret
#endif
#if defined(__APPLE__) && (defined(PIC) || defined(__PIC__))
/* Mach-O PIC */
.section __IMPORT,__pointers,non_lazy_symbol_pointers
.L_lzma_crc32_table$non_lazy_ptr:
.indirect_symbol LZMA_CRC32_TABLE
.long 0
#elif defined(_WIN32) || defined(__CYGWIN__)
# ifdef DLL_EXPORT
/* This is equivalent of __declspec(dllexport). */
.section .drectve
.ascii " -export:lzma_crc32"
# endif
#elif !defined(__MSDOS__)
/* ELF */
.size LZMA_CRC32, .-LZMA_CRC32
#endif
/*
* This is needed to support non-executable stack. It's ugly to
* use __linux__ here, but I don't know a way to detect when
* we are using GNU assembler.
*/
#if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",@progbits
#endif
|
AgoraIO-Usecase/HQ
| 6,761
|
libobs-for-HQ-Windows/deps/lzma/liblzma/check/crc64_x86.S
|
/*
* Speed-optimized CRC64 using slicing-by-four algorithm
*
* This uses only i386 instructions, but it is optimized for i686 and later
* (including e.g. Pentium II/III/IV, Athlon XP, and Core 2).
*
* Authors: Igor Pavlov (original CRC32 assembly code)
* Lasse Collin (CRC64 adaptation of the modified CRC32 code)
*
* This file has been put into the public domain.
* You can do whatever you want with this file.
*
* This code needs lzma_crc64_table, which can be created using the
* following C code:
uint64_t lzma_crc64_table[4][256];
void
init_table(void)
{
// ECMA-182
static const uint64_t poly64 = UINT64_C(0xC96C5795D7870F42);
for (size_t s = 0; s < 4; ++s) {
for (size_t b = 0; b < 256; ++b) {
uint64_t r = s == 0 ? b : lzma_crc64_table[s - 1][b];
for (size_t i = 0; i < 8; ++i) {
if (r & 1)
r = (r >> 1) ^ poly64;
else
r >>= 1;
}
lzma_crc64_table[s][b] = r;
}
}
}
* The prototype of the CRC64 function:
* extern uint64_t lzma_crc64(const uint8_t *buf, size_t size, uint64_t crc);
*/
/*
* On some systems, the functions need to be prefixed. The prefix is
* usually an underscore.
*/
#ifndef __USER_LABEL_PREFIX__
# define __USER_LABEL_PREFIX__
#endif
#define MAKE_SYM_CAT(prefix, sym) prefix ## sym
#define MAKE_SYM(prefix, sym) MAKE_SYM_CAT(prefix, sym)
#define LZMA_CRC64 MAKE_SYM(__USER_LABEL_PREFIX__, lzma_crc64)
#define LZMA_CRC64_TABLE MAKE_SYM(__USER_LABEL_PREFIX__, lzma_crc64_table)
/*
* Solaris assembler doesn't have .p2align, and Darwin uses .align
* differently than GNU/Linux and Solaris.
*/
#if defined(__APPLE__) || defined(__MSDOS__)
# define ALIGN(pow2, abs) .align pow2
#else
# define ALIGN(pow2, abs) .align abs
#endif
.text
.globl LZMA_CRC64
#if !defined(__APPLE__) && !defined(_WIN32) && !defined(__CYGWIN__) \
&& !defined(__MSDOS__)
.type LZMA_CRC64, @function
#endif
ALIGN(4, 16)
LZMA_CRC64:
/*
* Register usage:
* %eax crc LSB
* %edx crc MSB
* %esi buf
* %edi size or buf + size
* %ebx lzma_crc64_table
* %ebp Table index
* %ecx Temporary
*/
pushl %ebx
pushl %esi
pushl %edi
pushl %ebp
movl 0x14(%esp), %esi /* buf */
movl 0x18(%esp), %edi /* size */
movl 0x1C(%esp), %eax /* crc LSB */
movl 0x20(%esp), %edx /* crc MSB */
/*
* Store the address of lzma_crc64_table to %ebx. This is needed to
* get position-independent code (PIC).
*
* The PIC macro is defined by libtool, while __PIC__ is defined
* by GCC but only on some systems. Testing for both makes it simpler
* to test this code without libtool, and keeps the code working also
* when built with libtool but using something else than GCC.
*
* I understood that libtool may define PIC on Windows even though
* the code in Windows DLLs is not PIC in sense that it is in ELF
* binaries, so we need a separate check to always use the non-PIC
* code on Windows.
*/
#if (!defined(PIC) && !defined(__PIC__)) \
|| (defined(_WIN32) || defined(__CYGWIN__))
/* Not PIC */
movl $ LZMA_CRC64_TABLE, %ebx
#elif defined(__APPLE__)
/* Mach-O */
call .L_get_pc
.L_pic:
leal .L_lzma_crc64_table$non_lazy_ptr-.L_pic(%ebx), %ebx
movl (%ebx), %ebx
#else
/* ELF */
call .L_get_pc
addl $_GLOBAL_OFFSET_TABLE_, %ebx
movl LZMA_CRC64_TABLE@GOT(%ebx), %ebx
#endif
/* Complement the initial value. */
notl %eax
notl %edx
.L_align:
/*
* Check if there is enough input to use slicing-by-four.
* We need eight bytes, because the loop pre-reads four bytes.
*/
cmpl $8, %edi
jb .L_rest
/* Check if we have reached alignment of four bytes. */
testl $3, %esi
jz .L_slice
/* Calculate CRC of the next input byte. */
movzbl (%esi), %ebp
incl %esi
movzbl %al, %ecx
xorl %ecx, %ebp
shrdl $8, %edx, %eax
xorl (%ebx, %ebp, 8), %eax
shrl $8, %edx
xorl 4(%ebx, %ebp, 8), %edx
decl %edi
jmp .L_align
.L_slice:
/*
* If we get here, there's at least eight bytes of aligned input
* available. Make %edi multiple of four bytes. Store the possible
* remainder over the "size" variable in the argument stack.
*/
movl %edi, 0x18(%esp)
andl $-4, %edi
subl %edi, 0x18(%esp)
/*
* Let %edi be buf + size - 4 while running the main loop. This way
* we can compare for equality to determine when exit the loop.
*/
addl %esi, %edi
subl $4, %edi
/* Read in the first four aligned bytes. */
movl (%esi), %ecx
.L_loop:
xorl %eax, %ecx
movzbl %cl, %ebp
movl 0x1800(%ebx, %ebp, 8), %eax
xorl %edx, %eax
movl 0x1804(%ebx, %ebp, 8), %edx
movzbl %ch, %ebp
xorl 0x1000(%ebx, %ebp, 8), %eax
xorl 0x1004(%ebx, %ebp, 8), %edx
shrl $16, %ecx
movzbl %cl, %ebp
xorl 0x0800(%ebx, %ebp, 8), %eax
xorl 0x0804(%ebx, %ebp, 8), %edx
movzbl %ch, %ebp
addl $4, %esi
xorl (%ebx, %ebp, 8), %eax
xorl 4(%ebx, %ebp, 8), %edx
/* Check for end of aligned input. */
cmpl %edi, %esi
/*
* Copy the next input byte to %ecx. It is slightly faster to
* read it here than at the top of the loop.
*/
movl (%esi), %ecx
jb .L_loop
/*
* Process the remaining four bytes, which we have already
* copied to %ecx.
*/
xorl %eax, %ecx
movzbl %cl, %ebp
movl 0x1800(%ebx, %ebp, 8), %eax
xorl %edx, %eax
movl 0x1804(%ebx, %ebp, 8), %edx
movzbl %ch, %ebp
xorl 0x1000(%ebx, %ebp, 8), %eax
xorl 0x1004(%ebx, %ebp, 8), %edx
shrl $16, %ecx
movzbl %cl, %ebp
xorl 0x0800(%ebx, %ebp, 8), %eax
xorl 0x0804(%ebx, %ebp, 8), %edx
movzbl %ch, %ebp
addl $4, %esi
xorl (%ebx, %ebp, 8), %eax
xorl 4(%ebx, %ebp, 8), %edx
/* Copy the number of remaining bytes to %edi. */
movl 0x18(%esp), %edi
.L_rest:
/* Check for end of input. */
testl %edi, %edi
jz .L_return
/* Calculate CRC of the next input byte. */
movzbl (%esi), %ebp
incl %esi
movzbl %al, %ecx
xorl %ecx, %ebp
shrdl $8, %edx, %eax
xorl (%ebx, %ebp, 8), %eax
shrl $8, %edx
xorl 4(%ebx, %ebp, 8), %edx
decl %edi
jmp .L_rest
.L_return:
/* Complement the final value. */
notl %eax
notl %edx
popl %ebp
popl %edi
popl %esi
popl %ebx
ret
#if defined(PIC) || defined(__PIC__)
ALIGN(4, 16)
.L_get_pc:
movl (%esp), %ebx
ret
#endif
#if defined(__APPLE__) && (defined(PIC) || defined(__PIC__))
/* Mach-O PIC */
.section __IMPORT,__pointers,non_lazy_symbol_pointers
.L_lzma_crc64_table$non_lazy_ptr:
.indirect_symbol LZMA_CRC64_TABLE
.long 0
#elif defined(_WIN32) || defined(__CYGWIN__)
# ifdef DLL_EXPORT
/* This is equivalent of __declspec(dllexport). */
.section .drectve
.ascii " -export:lzma_crc64"
# endif
#elif !defined(__MSDOS__)
/* ELF */
.size LZMA_CRC64, .-LZMA_CRC64
#endif
/*
* This is needed to support non-executable stack. It's ugly to
* use __linux__ here, but I don't know a way to detect when
* we are using GNU assembler.
*/
#if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",@progbits
#endif
|
agural/FPGA-Oscilloscope
| 10,074
|
osc/software/osc/keyint.S
|
################################################################################
# #
# Key Interrupt Handler #
# Rotary Encoder and Menu Button Routines #
# EE/CS 52 #
# #
################################################################################
/*
* Albert Gural
* EE/CS 52
* TA: Dan Pipe-Mazo
*
* File Description: TODO
*
* Table of Contents: TODO
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo Initial Revision.
* 05/14/2014 Albert Gural Begain writing assembly functions to handle
* keypress interrupts.
*
*/
/* Local Include Files */
#include "macros.m"
#include "keyint.m"
#include "interfac.h"
//#include "menuact.h"
#include "../osc_bsp/system.h"
.section .text #start code section
/*
* key_int_installer
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 05/18/2014 Albert Gural Initial revision.
*
*/
.global key_int_installer
.type key_int_installer, @function
key_int_installer:
SAVE
# asdf
movia r8, adc_speed
movi r9, 0x040000
stw r9, (r8)
movia r8, trig_level
movi r9, 0
stb r9, (r8)
movia r8, trig_delay
movi r9, 240
sth r9, (r8)
# asdf
# Enable all switch interrupts.
movhi r8, %hi(KEY_INPUT_BASE)
ori r8, r8, %lo(KEY_INPUT_BASE)
movhi r9, %hi(SWITCH_ALL)
ori r9, r9, %lo(SWITCH_ALL)
stw r9, PIO_IRQ_MASK(r8)
# Install the interrupt handler
mov r4, r0
movi r5, KEY_INPUT_IRQ
movhi r6, %hi(key_handler)
ori r6, r6, %lo(key_handler)
mov r7, r0
PUSH r0
call alt_ic_isr_register
POP r0
key_int_installer_done:
RESTORE
ret
/*
* key_handler
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 05/18/2014 Albert Gural Initial revision.
*
*/
.type key_handler,@function
key_handler:
SAVE
# Key should now be available. Update key_press.
movi r8, 1
movia r9, key_press
stb r8, (r9)
# Clear interrupts.
movhi r8, %hi(KEY_INPUT_BASE)
ori r8, r8, %lo(KEY_INPUT_BASE)
stw r0, PIO_IRQ_MASK(r8)
# Get the edge capture register.
movhi r8, %hi(KEY_INPUT_BASE)
ori r8, r8, %lo(KEY_INPUT_BASE)
ldw r8, PIO_EDGE_CAP(r8)
# Check each bit (starting at 0) and see if set.
movi r9, 1
movi r11, 0
loop_keys:
and r10, r8, r9
bne r10, r0, key_lookup
slli r9, r9, 1
addi r11, r11, 1
br loop_keys
# Once the key is found (r11), use the lookup table to set key_value.
key_lookup:
movia r8, key_map
add r8, r8, r11
ldb r8, (r8)
movia r10, key_value
stb r8, (r10)
# Do a lookup (can't figure out how to get it to work with a table...).
movia r4, set_trigger_normal
movi r12, 5
beq r11, r12, call_action
movia r4, set_trigger_single
movi r12, 6
beq r11, r12, call_action
movia r4, trg_slope_toggle
movi r12, 7
beq r11, r12, call_action
movia r4, trg_slope_toggle
movi r12, 8
beq r11, r12, call_action
movia r4, sweep_down
movi r12, 10
beq r11, r12, call_action
movia r4, sweep_up
movi r12, 11
beq r11, r12, call_action
movia r4, trg_level_up
movi r12, 16
beq r11, r12, call_action
movia r4, trg_level_down
movi r12, 17
beq r11, r12, call_action
movia r4, trg_delay_up
movi r12, 18
beq r11, r12, call_action
movia r4, trg_delay_down
movi r12, 19
beq r11, r12, call_action
key_lookup_cont:
# Clear the edge capture register (write 1 to clear).
movhi r8, %hi(KEY_INPUT_BASE)
ori r8, r8, %lo(KEY_INPUT_BASE)
movhi r9, %hi(SWITCH_ALL)
ori r9, r9, %lo(SWITCH_ALL)
stw r9, PIO_EDGE_CAP(r8)
# Re-enable interrupts.
movhi r8, %hi(KEY_INPUT_BASE)
ori r8, r8, %lo(KEY_INPUT_BASE)
movhi r9, %hi(SWITCH_ALL)
ori r9, r9, %lo(SWITCH_ALL)
stw r9, PIO_IRQ_MASK(r8)
key_handler_done:
RESTORE
ret
call_action:
PUSH r8
PUSH r9
PUSH r10
PUSH r11
PUSH r12
PUSH r13
PUSH r14
PUSH r15
callr r4
POP r15
POP r14
POP r13
POP r12
POP r11
POP r10
POP r9
POP r8
br key_lookup_cont
/*
dec_speed:
movia r13, adc_speed
ldw r14, (r13)
slli r14, r14, 1
MOVWI r15, 0x00FFFFFF
and r14, r14, r15
beq r14, r0, set_speed_2
dec_speed_cont:
MOVWI r15, ADC_RATE_BASE
stw r14, (r15)
stw r14, (r13)
# Turn on FIFO write
STWI ADC_CTRL_BASE, 0x04
STWI ADC_CTRL_BASE, 0x02
br key_lookup_cont
inc_speed:
movia r13, adc_speed
ldwio r14, (r13)
srli r14, r14, 1
beq r14, r0, set_speed_1
inc_speed_cont:
MOVWI r15, ADC_RATE_BASE
stwio r14, (r15)
stwio r14, (r13)
# Turn on FIFO write
STWI ADC_CTRL_BASE, 0x04
STWI ADC_CTRL_BASE, 0x02
br key_lookup_cont
set_speed_1:
movi r14, 1
br inc_speed_cont
set_speed_2:
MOVWI r14, 0x00800000
br dec_speed_cont
dec_level:
movia r13, trig_level
ldb r14, (r13)
subi r14, r14, 5
movi r15, -128
blt r14, r15, set_level_2
dec_level_cont:
MOVWI r15, TRIG_LEVEL_BASE
stw r14, (r15)
stb r14, (r13)
# Turn on FIFO write
STWI ADC_CTRL_BASE, 0x04
STWI ADC_CTRL_BASE, 0x02
br key_lookup_cont
inc_level:
movia r13, trig_level
ldb r14, (r13)
addi r14, r14, 5
movi r15, 127
bgt r14, r15, set_level_1
inc_level_cont:
MOVWI r15, TRIG_LEVEL_BASE
stw r14, (r15)
stb r14, (r13)
# Turn on FIFO write
STWI ADC_CTRL_BASE, 0x04
STWI ADC_CTRL_BASE, 0x02
br key_lookup_cont
set_level_1:
movi r14, 127
br inc_level_cont
set_level_2:
MOVWI r14, -128
br dec_level_cont
dec_delay:
movia r13, trig_delay
ldh r14, (r13)
subi r14, r14, 10
ble r14, r0, set_delay_2
dec_delay_cont:
MOVWI r15, TRIG_DELAY_BASE
stw r14, (r15)
sth r14, (r13)
# Turn on FIFO write
STWI ADC_CTRL_BASE, 0x04
STWI ADC_CTRL_BASE, 0x02
br key_lookup_cont
inc_delay:
movia r13, trig_delay
ldh r14, (r13)
addi r14, r14, 10
movi r15, 1000
bgeu r14, r15, set_delay_1
inc_delay_cont:
MOVWI r15, TRIG_DELAY_BASE
stw r14, (r15)
sth r14, (r13)
# Turn on FIFO write
STWI ADC_CTRL_BASE, 0x04
STWI ADC_CTRL_BASE, 0x02
br key_lookup_cont
set_delay_1:
MOVWI r14, 50000
br inc_delay_cont
set_delay_2:
mov r14, r0
br dec_delay_cont
change_scale_up:
MOVWI r8, VSCALE_CTRL_BASE
movi r9, 1
stw r9, PIO_OUTSET(r8)
br key_lookup_cont
change_scale_down:
MOVWI r8, VSCALE_CTRL_BASE
movi r9, 1
stw r9, PIO_OUTCLR(r8)
br key_lookup_cont
*/
# hashtag
/*
* key_available
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 05/18/2014 Albert Gural Initial revision.
*
*/
.global key_available
.type key_available, @function
key_available:
SAVE
# Simply return the value in key_press.
movia r2, key_press
ldb r2, (r2)
key_available_done:
RESTORE
ret
/*
* key_available
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 05/18/2014 Albert Gural Initial revision.
*
*/
.global getkey
.type getkey, @function
getkey:
SAVE
# Block until legal key arrives (which is also when key_press = TRUE).
movia r8, key_value
ldb r8, (r8)
movi r9, KEY_ILLEGAL
beq r8, r9, getkey
# Get return value.
movia r2, key_value
ldb r2, (r2)
# Update key_value with KEY_ILLEGAL.
movia r10, key_value
stb r9, (r10)
# Update key_press with FALSE.
movia r10, key_press
stb r0, (r10)
getkey_done:
RESTORE
ret
/*
* key_map
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 05/18/2014 Albert Gural Initial revision.
*
*/
key_map:
.byte KEY_MENU
.byte KEY_UP
.byte KEY_DOWN
.byte KEY_LEFT
.byte KEY_RIGHT
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_ILLEGAL
/*
key_func:
.word no_menu_action
.align 4
.word no_menu_action
.word no_menu_action
.word no_menu_action
.word no_menu_action
.word clr_single_mode
.word set_single_mode
.word trg_slope_toggle
.word trg_slope_toggle
.word no_menu_action
.word sweep_up
.word sweep_down
.word no_menu_action # Vert sensitivity up (B)
.word no_menu_action # Vert sensitivity down (B)
.word no_menu_action # Vert sensitivity up (A)
.word no_menu_action # Vert sensitivity down (A)
.word trig_level_up
.word trig_level_down
.word trig_delay_up
.word trig_delay_down
.word no_menu_action*/
.section .data #start data section
key_press: .byte 0 # Gives whether a key has been pressed.
key_value: .byte 0 # Gives the value of the pressed key.
.align 4
adc_speed: .word 0 # Gives compare value for ADC clock speed.
trig_delay: .hword 0 # Gives trigger delay.
trig_level: .byte 0 # Gives trigger level.
|
agural/FPGA-Oscilloscope
| 10,313
|
osc/software/osc/sampleint.S
|
################################################################################
# #
# sampleint.S #
# Handles new samples and triggering #
# EE/CS 52 #
# #
################################################################################
/*
* Albert Gural
* EE/CS 52
* TA: Dan Pipe-Mazo
*
* File Description: This file contains functions for handling
* interrupts generated by new triggered samples, and provides
* the accessor functions for the main C code to access the sampled
* data. Samples are stored in a char** buffer first indexed by which
* input (A, B, logic analyzer), then indexed by the samples.
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo Initial Revision.
* 05/14/2014 Albert Gural Begain writing adc code assembly.
* 06/02/2014 Albert Gural Added accessor functions for C code interface.
*
*/
/* Local Include Files */
#include "macros.m"
#include "pio.m"
#include "../osc_bsp/system.h"
.section .text #start code section
/*
* adc_int_installer
*
* Description: Installs the interrupt handler for trigger interrupts.
*
* Arguments: (none)
*
* Return Value: (none)
*
*/
.global adc_int_installer
.type adc_int_installer, @function
adc_int_installer:
SAVE
# Install the interrupt handler
mov r4, r0
movi r5, 6
MOVWI r6, adc_int_handler
mov r7, r0
PUSH r0
call alt_ic_isr_register
POP r0
# Clear the edge capture register (write 1 to clear).
MOVWI r8, TRIG_INT_BASE
MOVWI r9, 0xFFFFFFFF
stw r9, PIO_EDGE_CAP(r8)
adc_int_installer_done:
RESTORE
ret
/*
* adc_int_handler
*
* Description: Handles a trigger interrupt. When a trigger occurs, we need
* to move all the data from the FIFO onto a local buffer (which can then be
* used by the C code in higher level functions).
*
* Arguments: (none)
*
* Return Value: (none)
*
*/
.global adc_int_handler
.type adc_int_handler, @function
adc_int_handler:
SAVE
# Clear interrupts.
MOVWI r8, TRIG_INT_BASE
stw r0, PIO_IRQ_MASK(r8)
# Get the edge capture register.
ldw r9, PIO_EDGE_CAP(r8)
# Pause FIFO write.
STWI ADC_CTRL_BASE, 0x00
# Loop variable to clear front of fifo
mov r10, r0
# Set specially-designed delay offsets based on which fifo source clock is being used.
movia r8, fifo_clk_src
ldb r9, (r8)
beq r9, r0, adc_int_handler_fast_clk_offset
adc_int_handler_1M_clk_offset:
movi r13, 15
br adc_int_handler_clear_front
adc_int_handler_fast_clk_offset:
movi r13, 22
adc_int_handler_clear_front:
# Bitbang clock pulse.
STWI ADC_CTRL_BASE, 0x01
STWI ADC_CTRL_BASE, 0x00
# Keep going until 480 good remaining points (for display)
addi r10, r10, 1
bltu r10, r13, adc_int_handler_clear_front
movia r8, sample_buffer_A
mov r10, r0
adc_int_handler_loop:
# Bitbang clock pulse.
STWI ADC_CTRL_BASE, 0x01
STWI ADC_CTRL_BASE, 0x00
# Get ch. A, ch. B, and logic data.
MOVWI r11, ADC_RAW_BASE
ldwio r12, (r11)
# r12 for ch. A, r13 for ch. B, r14 for logic.
srli r13, r12, 8
srli r14, r13, 8
movui r15, 128
# Convert analog channels to non-signed values.
add r12, r12, r15
add r13, r13, r15
# Keep only the bottom byte.
andi r12, r12, 0xFF
andi r13, r13, 0xFF
andi r14, r14, 0xFF
# CH. A
# Retrieve the current buffer contents.
# Then update the current buffer with the new value.
movia r8, sample_buffer_A
add r8, r8, r10
stb r12, (r8)
# CH. B
# Retrieve the current buffer contents.
# Then update the current buffer with the new value.
movia r8, sample_buffer_B
add r8, r8, r10
stb r13, (r8)
# LOGIC ANALYZER
# Retrieve the current buffer contents.
# Then update the current buffer with the new value.
movia r8, sample_buffer_L
add r8, r8, r10
stb r14, (r8)
addi r10, r10, 1
movi r15, 480
bltu r10, r15, adc_int_handler_loop
# Sample done.
movia r8, sample_complete
movi r9, 1
stb r9, (r8)
adc_int_handler_done:
RESTORE
ret
/*
* clear_display
*
* Description: Clears the display.
*
* Arguments: (none)
*
* Return Value: (none)
*
*/
.global clear_display
.type clear_display, @function
clear_display:
SAVE
# Get display address and background color.
MOVWI r8, VRAM_CTRL_BASE
movui r9, 272
slli r9, r9, 10
add r9, r8, r9
movui r15, 0x001C
# Loop over all screen pixels, clearing them.
clear_display_loop:
sthio r15, (r8)
addi r8, r8, 2
bltu r8, r9, clear_display_loop
clear_display_done:
RESTORE
ret
/*
* plot_pixel
*
* Description: Plots a pixel of the specified color at the specified location.
*
* Arguments:
* r4 - The x coordinate (from left)
* r5 - The y coordinate (from top)
* r6 - The color
*
* Return Value: (none)
*
*/
.global plot_pixel
.type plot_pixel, @function
plot_pixel:
SAVE
push r4
push r5
# Each row takes 1024 bytes, so shift row var by 10 bits.
slli r5, r5, 10
# Add twice to account for 16-bit VRAM storage.
add r5, r5, r4
add r5, r5, r4
# Now get the absolute address.
MOVWI r4, VRAM_CTRL_BASE
add r5, r5, r4
# Store the color.
sth r6, (r5)
pop r5
pop r4
plot_pixel_done:
RESTORE
ret
/*
* set_sample_rate
*
* Description: Given the desired sample frequency, computes what compare value
* value would be needed on the FIFO sample clock to get that frequency. The
* computed value is sent to the control register.
*
* Arguments:
* r4 - The desired frequency (Hz)
*
* Return Value: (none)
*
*/
.global set_sample_rate
.type set_sample_rate, @function
set_sample_rate:
SAVE
MOVWI r9, 100000
bleu r4, r9, slow_sample_rate
fast_sample_rate:
# Divide fastest sample rate by desired sample rate
# to get number of ticks to pause (not collect samples)
# between collecting samples.
MOVWI r8, ADC_RATE_BASE
MOVWI r9, 400000000
divu r9, r9, r4
subi r9, r9, 1
stw r9, (r8)
# Set fast clock for FIFO clock counter.
MOVWI r8, TRIG_CTRL_BASE
MOVWI r9, 0x00000080
stw r9, PIO_OUTCLR(r8)
# Update fifo source flag.
movia r8, fifo_clk_src
stb r0, (r8)
br set_sample_rate_done
slow_sample_rate:
# Divide fastest sample rate by desired sample rate
# to get number of ticks to pause (not collect samples)
# between collecting samples.
MOVWI r8, ADC_RATE_BASE
MOVWI r9, 1000000
divu r9, r9, r4
subi r9, r9, 1
stw r9, (r8)
# Set 1MHz clock for FIFO clock counter.
MOVWI r8, TRIG_CTRL_BASE
MOVWI r9, 0x00000080
stw r9, PIO_OUTSET(r8)
# Update fifo source flag.
movia r8, fifo_clk_src
movi r9, 1
stb r9, (r8)
set_sample_rate_done:
# Always return 480 samples.
movui r2, 480
RESTORE
ret
/*
* set_trigger
*
* Description: Sets the trigger level (7 bit precision) and slope.
*
* Arguments:
* r4 - Trigger level
* r5 - Slope
*
* Return Value: (none)
*
*/
.global set_trigger
.type set_trigger, @function
set_trigger:
SAVE
# Convert [0 to 127] to signed 8-bit [-127 to 127].
# Then update trigger level.
MOVWI r8, TRIG_LEVEL_BASE
slli r9, r4, 1
subi r9, r9, 127
andi r9, r9, 0xFF
stw r9, (r8)
# Slope is second bit of TRIG_CTRL. Modify the given
# argument, then update slope.
beq r5, r0, set_trigger_slope_pos
movi r8, 0x02
MOVWI r9, TRIG_CTRL_BASE
stw r8, PIO_OUTSET(r9)
br set_trigger_done
set_trigger_slope_pos:
movi r8, 0x02
MOVWI r9, TRIG_CTRL_BASE
stw r8, PIO_OUTCLR(r9)
set_trigger_done:
RESTORE
ret
/*
* set_delay
*
* Description: Sets the delay (positive or negative)
*
* Arguments:
* r4 - Delay in samples
*
* Return Value: (none)
*
*/
.global set_delay
.type set_delay, @function
set_delay:
SAVE
# Simply set the delay (240 offset means delay 0 is in the middle).
addi r9, r4, 240
MOVWI r8, TRIG_DELAY_BASE
stw r9, (r8)
set_delay_done:
RESTORE
ret
/*
* start_sample
*
* Description: Prepares the FPGA logic for finding the next trigger event.
*
* Arguments:
* r4 - Type of trigger (0 for normal, 1 for auto-trigger)
*
* Return Value: (none)
*
*/
.global start_sample
.type start_sample, @function
start_sample:
SAVE
# Clear the edge capture register (write 1 to clear).
MOVWI r8, TRIG_INT_BASE
MOVWI r9, 0xFFFFFFFF
stw r9, PIO_EDGE_CAP(r8)
# Enable trigger interrupts.
MOVWI r9, 0x00000002
# If auto-trigger, enable time-outs as well.
slli r8, r4, 2
add r9, r8, r9
MOVWI r8, TRIG_INT_BASE
stw r9, PIO_IRQ_MASK(r8)
# Clear FIFO, turn on FIFO write.
STWI ADC_CTRL_BASE, 0x04
STWI ADC_CTRL_BASE, 0x02
# Restart trigger counter [ch. A], [+ slope]
MOVWI r8, TRIG_CTRL_BASE
movi r9, 1
stw r9, PIO_OUTSET(r8)
stw r9, PIO_OUTCLR(r8)
start_sample_done:
RESTORE
ret
/*
* sample_done
*
* Description: Returns a pointer to the sample buffer, which is an array
* of an array of samples. If the sample is not done, returns null.
*
* Arguments: (none)
*
* Return Value: Pointer to the buffer, or null if the sample is not finished
*
*/
.global sample_done
.type sample_done, @function
sample_done:
SAVE
# Test if sample occurred.
movia r8, sample_complete
ldb r9, (r8)
beq r9, r0, sample_null
# If so, reset sample complete variable and return map to buffers.
stb r0, (r8)
movia r2, sample_map
br sample_done_done
sample_null:
# Otherwise, return null.
mov r2, r0
sample_done_done:
RESTORE
ret
/*
* Contains the three sample buffers. In this way, sample_map is an array of an array of samples,
* or a char**. The first index [0..2] gives which input we want, while the second index [0..479]
* gives which sample we want.
*
*/
sample_map:
.word sample_buffer_A
.word sample_buffer_B
.word sample_buffer_L
.section .data #start data section
sample_complete: .word 0 # 0 = still trying to get sample; 1 = sample done.
fifo_clk_src: .word 0 # 0 = fast_clk, 1 = 1M_clk. This is useful for fine-tuning the trigger delay.
sample_buffer_A: .skip 480 # Buffer stores display-worth of ADC samples (ch. A).
sample_buffer_B: .skip 480 # Buffer stores display-worth of ADC samples (ch. B).
sample_buffer_L: .skip 480 # Buffer stores display-worth of ADC samples (Logic).
|
agural/FPGA-Oscilloscope
| 2,525
|
osc/software/osc/testvram.S
|
################################################################################
# #
# VRAM Test Code #
# Test code for VRAM #
# EE/CS 52 #
# #
################################################################################
/*
* Albert Gural
* EE/CS 52
* TA: Dan Pipe-Mazo
*
* File Description: Tests VRAM (minimally)
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo Initial Revision.
* 05/14/2014 Albert Gural Begain writing testcode assembly.
*
*/
/* Local Include Files */
#include "macros.m"
#include "../osc_bsp/system.h"
.section .text #start code section
/*
* test_vram
*
* Description: Tests the VRAM in a couple different scenarios:
* - sequentially write/reading each value
* - sequentially writing all values then immediately reading all values
* - writing all values, waiting, then reading all values
*
* Arguments: (none)
*
* Return Value: (none)
*
*/
.global test_vram
.type test_vram,@function
test_vram:
SAVE
movhi r8, %hi(VRAM_CTRL_BASE)
ori r8, r8, %lo(VRAM_CTRL_BASE)
movhi r9, %hi(VRAM_CTRL_SPAN)
ori r9, r9, %lo(VRAM_CTRL_SPAN)
add r9, r8, r9
movui r12, 0x7000 # Test value to write to VRAM
# Quick W/R test
call write_read_all
# Slower W/R test
call write_all
call read_all
# Place a breakpoint here and wait as long as necessary (1 minute or more).
nop
call read_all # Verify there is no corrputed data.
# Failed tests
test_vram_fail:
nop
br test_vram_fail
# Succeeded tests
test_vram_done:
RESTORE
ret
write_all:
mov r10, r8
mov r11, r0
write_all_loop:
# Write to each element sequentially
sthio r11, (r10)
addi r10, r10, 2
addi r11, r11, 1
bgeu r10, r9, write_all_done
bgeu r11, r12, write_all_reset_cnt
br write_all_loop
write_all_reset_cnt:
mov r11, r0
br write_all_loop
write_all_done:
ret
read_all:
mov r10, r8
mov r11, r0
read_all_loop:
# Read and verify each element sequentially
ldhio r13, (r10)
bne r13, r11, test_vram_fail
addi r10, r10, 2
addi r11, r11, 1
bgeu r10, r9, read_all_done
bgeu r11, r12, read_all_reset_cnt
br read_all_loop
read_all_reset_cnt:
mov r11, r0
br write_all_loop
read_all_done:
ret
|
agural/FPGA-Oscilloscope
| 13,240
|
osc/software/osc/testadc.S
|
################################################################################
# #
# ADC Test Code #
# Test code for ADC (requires display) #
# EE/CS 52 #
# #
################################################################################
/*
* Albert Gural
* EE/CS 52
* TA: Dan Pipe-Mazo
*
* File Description: TODO
*
* Table of Contents: TODO
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo Initial Revision.
* 05/14/2014 Albert Gural Begain writing testcode assembly.
*
*/
/* Local Include Files */
#include "macros.m"
#include "keyint.m"
#include "../osc_bsp/system.h"
.section .text #start code section
/*
* adc_int_installer
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 05/18/2014 Albert Gural Initial revision.
*
*/
.global adc_int_installer
.type adc_int_installer, @function
adc_int_installer:
SAVE
# Set FIFO speed
STWI ADC_RATE_BASE, 0x040000
# Set Trigger default level (2's complement), delay
STWI TRIG_LEVEL_BASE, 0
STWI TRIG_DELAY_BASE, 240
STWI TRIG_ERROR_BASE, 8
# Install the interrupt handler
mov r4, r0
movi r5, 6
MOVWI r6, adc_int_handler
mov r7, r0
PUSH r0
call alt_ic_isr_register
POP r0
# Clear the edge capture register (write 1 to clear).
MOVWI r8, TRIG_INT_BASE
MOVWI r9, 0xFFFFFFFF
stw r9, PIO_EDGE_CAP(r8)
adc_int_installer_done:
RESTORE
ret
/*
* adc_int_handler
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 06/13/2014 Albert Gural initial revision
*
*/
.global adc_int_handler
.type adc_int_handler, @function
adc_int_handler:
SAVE
# Clear interrupts.
MOVWI r8, TRIG_INT_BASE
stw r0, PIO_IRQ_MASK(r8)
# Get the edge capture register.
ldw r9, PIO_EDGE_CAP(r8)
# Pause FIFO write.
STWI ADC_CTRL_BASE, 0x00
# Loop variable to clear front of fifo
mov r10, r0
# Set specially-designed delay offsets based on which fifo source clock is being used.
movia r8, fifo_clk_src
ldb r9, (r8)
beq r9, r0, adc_int_handler_fast_clk_offset
adc_int_handler_1M_clk_offset:
movi r13, 15
br adc_int_handler_clear_front
adc_int_handler_fast_clk_offset:
movi r13, 22
adc_int_handler_clear_front:
# Bitbang clock pulse.
STWI ADC_CTRL_BASE, 0x01
STWI ADC_CTRL_BASE, 0x00
# Keep going until 480 good remaining points (for display)
addi r10, r10, 1
bltu r10, r13, adc_int_handler_clear_front
movia r8, sample_buffer_A
mov r10, r0
adc_int_handler_loop:
# Bitbang clock pulse.
STWI ADC_CTRL_BASE, 0x01
STWI ADC_CTRL_BASE, 0x00
# Get ch. A, ch. B, and logic data.
MOVWI r11, ADC_RAW_BASE
ldwio r12, (r11)
# r12 for ch. A, r13 for ch. B, r14 for logic.
srli r13, r12, 8
srli r14, r13, 8
movui r15, 128
# Convert analog channels to non-signed values.
add r12, r12, r15
add r13, r13, r15
# Keep only the bottom byte.
andi r12, r12, 0xFF
andi r13, r13, 0xFF
andi r14, r14, 0xFF
# CH. A
# Retrieve the current buffer contents.
# Then update the current buffer with the new value.
movia r8, sample_buffer_A
add r8, r8, r10
stb r12, (r8)
# CH. B
# Retrieve the current buffer contents.
# Then update the current buffer with the new value.
movia r8, sample_buffer_B
add r8, r8, r10
stb r13, (r8)
# LOGIC ANALYZER
# Retrieve the current buffer contents.
# Then update the current buffer with the new value.
movia r8, sample_buffer_L
add r8, r8, r10
stb r14, (r8)
addi r10, r10, 1
movi r15, 480
bltu r10, r15, adc_int_handler_loop
# Sample done.
movia r8, sample_complete
movi r9, 1
stb r9, (r8)
adc_int_handler_done:
RESTORE
ret
.global draw_trace
.type draw_trace, @function
draw_trace:
SAVE
push r4
push r5
push r6
movia r8, sample_buffer_A
mov r10, r0
draw_trace_loop:
ldb r12, (r8)
movui r15, 255
sub r12, r15, r12
andi r12, r12, 0xFF
addi r12, r12, 8
MOVWI r9, VRAM_CTRL_BASE
add r9, r9, r10
add r9, r9, r10
mov r11, r0
draw_trace_col_loop:
MOVWI r15, 0x001C
sthio r15, (r9)
movi r15, 136
beq r11, r15, draw_grid_pt
movi r15, 240
beq r10, r15, draw_grid_pt
beq r11, r12, draw_trace_pt
draw_trace_col_loop_continue:
addi r9, r9, 0x400
addi r11, r11, 1
movi r15, 272
bltu r11, r15, draw_trace_col_loop
addi r8, r8, 1
addi r10, r10, 1
movi r15, 480
bltu r10, r15, draw_trace_loop
draw_trace_done:
pop r6
pop r5
pop r4
RESTORE
ret
draw_grid_pt:
MOVWI r15, 0x1F00
sthio r15, (r9)
br draw_trace_col_loop_continue
draw_trace_pt:
MOVWI r15, 0xE07F
sthio r15, (r9)
br draw_trace_col_loop_continue
.global draw_grid
.type draw_grid, @function
draw_grid:
SAVE
push r4
push r5
push r6
movui r6, 0x1F00
movui r4, 136
mov r5, r0
draw_grid_horiz:
call draw_pixel
movui r6, 0x003C
addi r4, r4, 1
call draw_pixel
addi r4, r4, 1
call draw_pixel
addi r4, r4, 1
call draw_pixel
movui r6, 0x1F00
subi r4, r4, 3
addi r5, r5, 1
movi r8, 480
bltu r5, r8, draw_grid_horiz
mov r4, r0
movui r5, 240
draw_grid_vert:
call draw_pixel
addi r4, r4, 1
movi r8, 272
bltu r4, r8, draw_grid_vert
draw_grid_done:
pop r6
pop r5
pop r4
RESTORE
ret
draw_pixel:
SAVE
push r4
push r5
slli r4, r4, 10
add r4, r4, r5
add r4, r4, r5
MOVWI r5, VRAM_CTRL_BASE
add r4, r4, r5
sth r6, (r4)
pop r5
pop r4
draw_pixel_done:
RESTORE
ret
/*
* adc_int_handler
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo initial revision
*
*/
.global clear_display
.type clear_display, @function
clear_display:
SAVE
# Get display address and background color.
MOVWI r8, VRAM_CTRL_BASE
movui r9, 272
slli r9, r9, 10
add r9, r8, r9
movui r15, 0x001C
# Loop over all screen pixels, clearing them.
clear_display_loop:
sthio r15, (r8)
addi r8, r8, 2
bltu r8, r9, clear_display_loop
clear_display_done:
RESTORE
ret
/*
* adc_int_handler
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo initial revision
*
*/
.global plot_pixel
.type plot_pixel, @function
plot_pixel:
SAVE
push r4
push r5
# Each row takes 1024 bytes, so shift row var by 10 bits.
slli r5, r5, 10
# Add twice to account for 16-bit VRAM storage.
add r5, r5, r4
add r5, r5, r4
# Now get the absolute address.
MOVWI r4, VRAM_CTRL_BASE
add r5, r5, r4
# Store the color.
sth r6, (r5)
pop r5
pop r4
plot_pixel_done:
RESTORE
ret
/*
* adc_int_handler
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo initial revision
*
*/
.global set_sample_rate
.type set_sample_rate, @function
set_sample_rate:
SAVE
MOVWI r9, 100000
bleu r4, r9, slow_sample_rate
fast_sample_rate:
# Divide fastest sample rate by desired sample rate
# to get number of ticks to pause (not collect samples)
# between collecting samples.
MOVWI r8, ADC_RATE_BASE
MOVWI r9, 400000000
divu r9, r9, r4
subi r9, r9, 1
stw r9, (r8)
# Set fast clock for FIFO clock counter.
MOVWI r8, TRIG_CTRL_BASE
MOVWI r9, 0x00000080
stw r9, PIO_OUTCLR(r8)
# Update fifo source flag.
movia r8, fifo_clk_src
stb r0, (r8)
br set_sample_rate_done
slow_sample_rate:
# Divide fastest sample rate by desired sample rate
# to get number of ticks to pause (not collect samples)
# between collecting samples.
MOVWI r8, ADC_RATE_BASE
MOVWI r9, 1000000
divu r9, r9, r4
subi r9, r9, 1
stw r9, (r8)
# Set 1MHz clock for FIFO clock counter.
MOVWI r8, TRIG_CTRL_BASE
MOVWI r9, 0x00000080
stw r9, PIO_OUTSET(r8)
# Update fifo source flag.
movia r8, fifo_clk_src
movi r9, 1
stb r9, (r8)
set_sample_rate_done:
# Always return 480 samples.
movui r2, 480
RESTORE
ret
/*
* adc_int_handler
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo initial revision
*
*/
.global set_trigger
.type set_trigger, @function
set_trigger:
SAVE
# Convert [0 to 127] to signed 8-bit [-127 to 127].
# Then update trigger level.
MOVWI r8, TRIG_LEVEL_BASE
slli r9, r4, 1
subi r9, r9, 127
andi r9, r9, 0xFF
stw r9, (r8)
# Slope is second bit of TRIG_CTRL. Modify the given
# argument, then update slope.
beq r5, r0, set_trigger_slope_pos
movi r8, 0x02
MOVWI r9, TRIG_CTRL_BASE
stw r8, PIO_OUTSET(r9)
br set_trigger_done
set_trigger_slope_pos:
movi r8, 0x02
MOVWI r9, TRIG_CTRL_BASE
stw r8, PIO_OUTCLR(r9)
set_trigger_done:
RESTORE
ret
/*
* adc_int_handler
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo initial revision
*
*/
.global set_delay
.type set_delay, @function
set_delay:
SAVE
# Simply set the delay (240 offset means delay 0 is in the middle).
addi r9, r4, 240
MOVWI r8, TRIG_DELAY_BASE
stw r9, (r8)
set_delay_done:
RESTORE
ret
/*
* adc_int_handler
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo initial revision
*
*/
.global start_sample
.type start_sample, @function
start_sample:
SAVE
# Clear the edge capture register (write 1 to clear).
MOVWI r8, TRIG_INT_BASE
MOVWI r9, 0xFFFFFFFF
stw r9, PIO_EDGE_CAP(r8)
# Enable trigger interrupts.
MOVWI r9, 0x00000002
# If auto-trigger, enable time-outs as well.
slli r8, r4, 2
add r9, r8, r9
MOVWI r8, TRIG_INT_BASE
stw r9, PIO_IRQ_MASK(r8)
# Clear FIFO, turn on FIFO write.
STWI ADC_CTRL_BASE, 0x04
STWI ADC_CTRL_BASE, 0x02
# Restart trigger counter [ch. A], [+ slope]
MOVWI r8, TRIG_CTRL_BASE
movi r9, 1
stw r9, PIO_OUTSET(r8)
stw r9, PIO_OUTCLR(r8)
start_sample_done:
RESTORE
ret
/*
* adc_int_handler
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo initial revision
*
*/
.global sample_done
.type sample_done, @function
sample_done:
SAVE
# Test if sample occurred.
movia r8, sample_complete
ldb r9, (r8)
beq r9, r0, sample_null
# If so, reset sample complete variable and return map to buffers.
stb r0, (r8)
movia r2, sample_map
br sample_done_done
sample_null:
# Otherwise, return null.
mov r2, r0
sample_done_done:
RESTORE
ret
sample_map:
.word sample_buffer_A
.word sample_buffer_B
.word sample_buffer_L
.section .data #start data section
sample_complete: .word 0 # 0 = still trying to get sample; 1 = sample done.
fifo_clk_src: .word 0 # 0 = fast_clk, 1 = 1M_clk. This is useful for fine-tuning the trigger delay.
sample_buffer_A: .skip 480 # Buffer stores display-worth of ADC samples (ch. A).
sample_buffer_B: .skip 480 # Buffer stores display-worth of ADC samples (ch. B).
sample_buffer_L: .skip 480 # Buffer stores display-worth of ADC samples (Logic).
|
agural/FPGA-Oscilloscope
| 3,141
|
osc/software/osc/testdisp.S
|
################################################################################
# #
# Display Test Code #
# Test code for display #
# EE/CS 52 #
# #
################################################################################
/*
* Albert Gural
* EE/CS 52
* TA: Dan Pipe-Mazo
*
* File Description: Tests the display with a simple 4-square pattern and border
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo Initial Revision.
* 05/14/2014 Albert Gural Begain writing testcode assembly.
*
*/
/* Local Include Files */
#include "../osc_bsp/system.h"
.section .text #start code section
/*
* test_disp
*
* Description: Draws four rectangles in a 2x2 configuration, then draws a border.
* This tests for correct color being displayed, as well as no display timing issues.
*
* This is a quick and dirty implementation, not meant to be well-commented.
*
* Arguments: (none)
*
* Return Value: (none)
*
*/
.global test_disp
.type test_disp,@function
test_disp:
movhi r8, %hi(VRAM_CTRL_BASE)
ori r8, r8, %lo(VRAM_CTRL_BASE)
mov r11, r0
mov r12, r0
disp:
movi r13, 136
bltu r12, r13, draw_top
br draw_bot
disp_cont:
addi r8, r8, 2
addi r11, r11, 1
movi r13, 272
bgeu r12, r13, draw_border
movi r13, 0x0200
bgeu r11, r13, disp_reset
br disp
draw_top:
movi r13, 240
bltu r11, r13, draw_red
br draw_yellow
draw_bot:
movi r13, 240
bltu r11, r13, draw_green
br draw_blue
draw_red:
movi r9, 0x1F00
sthio r9, (r8)
br disp_cont
draw_yellow:
movui r9, 0xFF03
sthio r9, (r8)
br disp_cont
draw_green:
movui r9, 0xE003
sthio r9, (r8)
br disp_cont
draw_blue:
movi r9, 0x007C
sthio r9, (r8)
br disp_cont
draw_border:
movi r9, 0x1F7C
movi r12, 272
movi r13, 480
draw_border_top:
movhi r8, %hi(VRAM_CTRL_BASE)
ori r8, r8, %lo(VRAM_CTRL_BASE)
addi r8, r8, 0x0400
mov r11, r0
dbt_loop:
sthio r9, (r8)
addi r8, r8, 2
addi r11, r11, 1
bgeu r11, r13, draw_border_bot
br dbt_loop
draw_border_bot:
movhi r8, %hi(VRAM_CTRL_BASE)
ori r8, r8, %lo(VRAM_CTRL_BASE)
movhi r14, %hi(277504)
ori r14, r14, %lo(277504)
add r8, r8, r14
mov r11, r0
dbb_loop:
sthio r9, (r8)
addi r8, r8, 2
addi r11, r11, 1
bgeu r11, r13, draw_border_left
br dbb_loop
draw_border_left:
movhi r8, %hi(VRAM_CTRL_BASE)
ori r8, r8, %lo(VRAM_CTRL_BASE)
mov r11, r0
dbl_loop:
sthio r9, (r8)
addi r8, r8, 0x0400
addi r11, r11, 1
bgeu r11, r12, draw_border_right
br dbl_loop
draw_border_right:
movhi r8, %hi(VRAM_CTRL_BASE)
ori r8, r8, %lo(VRAM_CTRL_BASE)
add r8, r8, r13
add r8, r8, r13
subi r8, r8, 1
mov r11, r0
dbr_loop:
sthio r9, (r8)
addi r8, r8, 0x0400
addi r11, r11, 1
bgeu r11, r12, test_disp_done
br dbr_loop
disp_reset:
mov r11, r0
addi r12, r12, 1
br disp
test_disp_done:
ret
|
agural/FPGA-Oscilloscope
| 3,594
|
osc/software/osc_bsp/HAL/src/alt_exception_trap.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the trap exception handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_trap
alt_exception_trap:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
.Ltrap_handler:
/*
* Did a trap instruction cause the exception?
*
* The instruction which the exception occurred on has been loaded
* into r2 by code in alt_exception_entry.S
*
*/
movhi r3,0x003b /* upper half of trap opcode */
ori r3,r3,0x683a /* lower half of trap opcode */
bne r2,r3,.Lnot_trap
/*
* There is no trap handler defined here, and so executing a trap
* instruction causes a software break. If you provide a trap handler,
* then you must replace the break instruction below with your handler.
* Your handler must preserve ea and the usual callee saved registers.
*/
break
br .Lexception_exit
.Lnot_trap:
.section .exceptions.exit.label
.Lexception_exit:
|
agural/FPGA-Oscilloscope
| 4,685
|
osc/software/osc_bsp/HAL/src/alt_irq_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the interrupt exception entry point code, which saves all the
* registers and calls the interrupt handler. It should be pulled in using
* a .globl from alt_irq_register.c. This scheme is used so that if an
* interrupt is never registered, then this code will not appear in the
* generated executable, thereby improving code footprint.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the compiler.
*/
.set noat
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.globl alt_irq_entry
.section .exceptions.entry.label, "xa"
alt_irq_entry:
/*
* Section .exceptions.entry is in alt_exception_entry.S
* This saves all the caller saved registers and reads estatus into r5
*/
.section .exceptions.irqtest, "xa"
#ifdef ALT_CI_INTERRUPT_VECTOR_N
/*
* Use the interrupt vector custom instruction if present to accelerate
* this code.
* If the interrupt vector custom instruction returns a negative
* value, there are no interrupts active (estatus.pie is 0
* or ipending is 0) so assume it is a software exception.
*/
custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0
blt r4, r0, .Lnot_irq
#else
/*
* Test to see if the exception was a software exception or caused
* by an external interrupt, and vector accordingly.
*/
rdctl r4, ipending
andi r2, r5, 1
beq r2, zero, .Lnot_irq
beq r4, zero, .Lnot_irq
#endif /* ALT_CI_INTERRUPT_VECTOR_N */
.section .exceptions.irqhandler, "xa"
/*
* Now that all necessary registers have been preserved, call
* alt_irq_handler() to process the interrupts.
*/
call alt_irq_handler
.section .exceptions.irqreturn, "xa"
br .Lexception_exit
.section .exceptions.notirq.label, "xa"
.Lnot_irq:
/*
* Section .exceptions.exit is in alt_exception_entry.S
* This restores all the caller saved registers
*/
.section .exceptions.exit.label
.Lexception_exit:
|
agural/FPGA-Oscilloscope
| 1,742
|
osc/software/osc_bsp/HAL/src/alt_log_macro.S
|
/* alt_log_macro.S
*
* Implements the function tx_log_str, called by the assembly macro
* ALT_LOG_PUTS(). The macro will be empty when logging is turned off,
* and this function will not be compiled. When logging is on,
* this function is used to print out the strings defined in the beginning
* of alt_log_printf.c, using port information taken from system.h and
* alt_log_printf.h.
*
* This routine only handles strings, and sends a character into the defined
* output device's output buffer when the device is ready. It's intended for
* debugging purposes, where messages can be set to print out at certain
* points in the boot code to indicate the progress of the program.
*
*/
#ifndef __ALT_LOG_MACROS__
#define __ALT_LOG_MACROS__
/* define this flag to skip assembly-incompatible parts
* of various include files. */
#define ALT_ASM_SRC
#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined.
#include "system.h"
#include "sys/alt_log_printf.h"
.global tx_log_str
tx_log_str:
/* load base uart / jtag uart address into r6 */
movhi r6, %hiadj(ALT_LOG_PORT_BASE)
addi r6, r6, %lo(ALT_LOG_PORT_BASE)
tx_next_char:
/* if pointer points to null, return
* r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */
ldb r7, (r4)
beq r0, r7, end_tx
/* check device transmit ready */
wait_tx_ready_loop:
ldwio r5, ALT_LOG_PRINT_REG_OFFSET(r6)
andi r5, r5, ALT_LOG_PRINT_MSK
beq r5, r0, wait_tx_ready_loop
/* write char */
stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6)
/* advance string pointer */
addi r4, r4, 1
br tx_next_char
end_tx:
ret
#endif
#endif /* __ALT_LOG_MACROS__ */
|
agural/FPGA-Oscilloscope
| 14,886
|
osc/software/osc_bsp/HAL/src/alt_exception_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the exception entry point code, which saves all the caller saved
* registers and then handles the appropriate exception. It should be pulled
* in using a .globl from all the exception handler routines. This scheme is
* used so that if an interrupt is never registered, then this code will not
* appear in the generated executable, thereby improving code footprint.
*
* If an external interrpt controller (EIC) is present, it will supply an
* interrupt vector address to the processor when an interrupt occurs. For
* The Altera Vectored Interrupt Controller (VIC) driver will establish a
* vector table and the processor will jump directly to the appropriate
* table entry, funnel routine, and then user ISR. This will bypass this code
* in entirety. This code might still be linked into a system with an EIC,
* but would then be used only for non-interrupt exceptions.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* The top and bottom of the exception stack.
*/
#ifdef ALT_EXCEPTION_STACK
.globl __alt_exception_stack_pointer
#ifdef ALT_STACK_CHECK
.globl __alt_exception_stack_limit
/*
* Store the value of the stack limit after interrupt somewhere.
*/
.globl alt_exception_old_stack_limit
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* The code at alt_exception is located at the Nios II exception
* handler address.
*/
.section .exceptions.entry.label, "xa"
.globl alt_exception
.type alt_exception, @function
alt_exception:
/*
* The code for detecting a likely fatal ECC exception is
* linked here before the normal exception handler code if required.
* This is handled by the linker script and putting that code
* in the .exceptions.entry.ecc_fatal section.
*/
/*
* Now start the normal exception handler code.
*/
.section .exceptions.entry, "xa"
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
/*
* When runtime stack checking is enabled, the et register
* contains the stack limit. Save this in memory before
* overwriting the et register.
*/
stw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
/*
* Switch to the exception stack and save the current stack pointer
* in memory. Uses the et register as a scratch register.
*/
movhi et, %hi(__alt_exception_stack_pointer - 80)
ori et, et, %lo(__alt_exception_stack_pointer - 80)
stw sp, 76(et)
mov sp, et
#ifdef ALT_STACK_CHECK
/*
* Restore the stack limit from memory to the et register.
*/
movhi et, %hi(__alt_exception_stack_limit)
ori et, et, %lo(__alt_exception_stack_limit)
stw et, %gprel(alt_stack_limit_value)(gp)
#endif /* ALT_STACK_CHECK */
#else /* ALT_EXCEPTION_STACK disabled */
/*
* Reserve space on normal stack for registers about to be pushed.
*/
addi sp, sp, -76
#ifdef ALT_STACK_CHECK
/* Ensure stack didn't just overflow. */
bltu sp, et, .Lstack_overflow
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* Process an exception. For all exceptions we must preserve all
* caller saved registers on the stack (See the Nios II ABI
* documentation for details).
*
* Leave a gap in the stack frame at 4(sp) for the muldiv handler to
* store zero into.
*/
stw ra, 0(sp)
stw r1, 8(sp)
stw r2, 12(sp)
stw r3, 16(sp)
stw r4, 20(sp)
stw r5, 24(sp)
stw r6, 28(sp)
stw r7, 32(sp)
rdctl r5, estatus /* Read early to avoid usage stall */
stw r8, 36(sp)
stw r9, 40(sp)
stw r10, 44(sp)
stw r11, 48(sp)
stw r12, 52(sp)
stw r13, 56(sp)
stw r14, 60(sp)
stw r15, 64(sp)
/*
* ea-4 contains the address of the instruction being executed
* when the exception occured. For interrupt exceptions, we will
* will be re-issue the isntruction. Store it in 72(sp)
*/
stw r5, 68(sp) /* estatus */
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
/*
* The interrupt testing code (.exceptions.irqtest) will be
* linked here. If the Internal Interrupt Controller (IIC) is
* present (an EIC is not present), the presense of an interrupt
* is determined by examining CPU control registers or an interrupt
* custom instruction, if present.
*
* If the IIC is used and an interrupt is active, the code linked
* here will call the HAL IRQ handler (alt_irq_handler()) which
* successively calls registered interrupt handler(s) until no
* interrupts remain pending. It then jumps to .exceptions.exit. If
* there is no interrupt then it continues to .exception.notirq, below.
*/
.section .exceptions.notirq, "xa"
/*
* Prepare to service unimplemtned instructions or traps,
* each of which is optionally inked into section .exceptions.soft,
* which will preceed .exceptions.unknown below.
*
* Unlike interrupts, we want to skip the exception-causing instructon
* upon completion, so we write ea (address of instruction *after*
* the one where the exception occured) into 72(sp). The actual
* instruction that caused the exception is written in r2, which these
* handlers will utilize.
*/
stw ea, 72(sp) /* Don't re-issue */
ldw r2, -4(ea) /* Instruction that caused exception */
/*
* Other exception handling code, if enabled, will be linked here.
* This includes unimplemted (multiply/divide) instruction support
* (a BSP generaton option), and a trap handler (that would typically
* be augmented with user-specific code). These are not linked in by
* default.
*/
/*
* In the context of linker sections, "unknown" are all exceptions
* not handled by the built-in handlers above (interupt, and trap or
* unimplemented instruction decoding, if enabled).
*
* Advanced exception types can be serviced by registering a handler.
* To do so, enable the "Enable Instruction-related Exception API" HAL
* BSP setting. If this setting is disabled, this handler code will
* either break (if the debug core is present) or enter an infinite
* loop because we don't how how to handle the exception.
*/
.section .exceptions.unknown
#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
/*
* The C-based HAL routine alt_instruction_exception_entry() will
* attempt to service the exception by calling a user-registered
* exception handler using alt_instruction_exception_register().
* If no handler was registered it will either break (if the
* debugger is present) or go into an infinite loop since the
* handling behavior is undefined; in that case we will not return here.
*/
/* Load exception-causing address as first argument (r4) */
addi r4, ea, -4
/* Call the instruction-exception entry */
call alt_instruction_exception_entry
/*
* If alt_instruction_exception_entry() returned, the exception was
* serviced by a user-registered routine. Its return code (now in r2)
* indicates whether to re-issue or skip the exception-causing
* instruction
*
* Return code was 0: Skip. The instruction after the exception is
* already stored in 72(sp).
*/
bne r2, r0, .Lexception_exit
/*
* Otherwise, modify 72(sp) to re-issue the instruction that caused the
* exception.
*/
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */
/*
* We got here because an instruction-related exception occured, but the
* handler API was not compiled in. We do not presume to know how to
* handle it. If the debugger is present, break, otherwise hang.
*
* If you get here then one of the following could have happened:
*
* - An instruction-generated exception occured, and the processor
* does not have the extra exceptions feature enabled, or you
* have not registered a handler using
* alt_instruction_exception_register()
*
* Some examples of instruction-generated exceptions and why they
* might occur:
*
* - Your program could have been compiled for a full-featured
* Nios II core, but it is running on a smaller core, and
* instruction emulation has been disabled by defining
* ALT_NO_INSTRUCTION_EMULATION.
*
* You can work around the problem by re-enabling instruction
* emulation, or you can figure out why your program is being
* compiled for a system other than the one that it is running on.
*
* - Your program has executed a trap instruction, but has not
* implemented a handler for this instruction.
*
* - Your program has executed an illegal instruction (one which is
* not defined in the instruction set).
*
* - Your processor includes an MMU or MPU, and you have enabled it
* before registering an exception handler to service exceptions it
* generates.
*
* The problem could also be hardware related:
* - If your hardware is broken and is generating spurious interrupts
* (a peripheral which negates its interrupt output before its
* interrupt handler has been executed will cause spurious
* interrupts)
*/
alt_exception_unknown:
#ifdef NIOS2_HAS_DEBUG_STUB
/*
* Either tell the user now (if there is a debugger attached) or go into
* the debug monitor which will loop until a debugger is attached.
*/
break
#else /* NIOS2_HAS_DEBUG_STUB disabled */
/*
* If there is no debug stub, an infinite loop is more useful.
*/
br alt_exception_unknown
#endif /* NIOS2_HAS_DEBUG_STUB */
#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
.section .exceptions.exit.label
.Lexception_exit:
.section .exceptions.exit, "xa"
/*
* Restore the saved registers, so that all general purpose registers
* have been restored to their state at the time the interrupt occured.
*/
ldw r5, 68(sp)
ldw ea, 72(sp) /* This becomes the PC once eret is executed */
ldw ra, 0(sp)
wrctl estatus, r5
ldw r1, 8(sp)
ldw r2, 12(sp)
ldw r3, 16(sp)
ldw r4, 20(sp)
ldw r5, 24(sp)
ldw r6, 28(sp)
ldw r7, 32(sp)
#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
ldw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif
ldw r8, 36(sp)
ldw r9, 40(sp)
ldw r10, 44(sp)
ldw r11, 48(sp)
ldw r12, 52(sp)
ldw r13, 56(sp)
ldw r14, 60(sp)
ldw r15, 64(sp)
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
stw et, %gprel(alt_stack_limit_value)(gp)
stw zero, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
ldw sp, 76(sp)
#else /* ALT_EXCEPTION_STACK disabled */
addi sp, sp, 76
#endif /* ALT_EXCEPTION_STACK */
/*
* Return to the interrupted instruction.
*/
eret
#ifdef ALT_STACK_CHECK
.Lstack_overflow:
break 3
#endif /* ALT_STACK_CHECK */
|
agural/FPGA-Oscilloscope
| 21,315
|
osc/software/osc_bsp/HAL/src/alt_exception_muldiv.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the software multiply/divide handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_muldiv
alt_exception_muldiv:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
/* INSTRUCTION EMULATION
* ---------------------
*
* Nios II processors generate exceptions for unimplemented instructions.
* The routines below emulate these instructions. Depending on the
* processor core, the only instructions that might need to be emulated
* are div, divu, mul, muli, mulxss, mulxsu, and mulxuu.
*
* The emulations match the instructions, except for the following
* limitations:
*
* 1) The emulation routines do not emulate the use of the exception
* temporary register (et) as a source operand because the exception
* handler already has modified it.
*
* 2) The routines do not emulate the use of the stack pointer (sp) or the
* exception return address register (ea) as a destination because
* modifying these registers crashes the exception handler or the
* interrupted routine.
*
* 3) To save code size, the routines do not emulate the use of the
* breakpoint registers (ba and bt) as operands.
*
* Detailed Design
* ---------------
*
* The emulation routines expect the contents of integer registers r0-r31
* to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The
* routines retrieve source operands from the stack and modify the
* destination register's value on the stack prior to the end of the
* exception handler. Then all registers except the destination register
* are restored to their previous values.
*
* The instruction that causes the exception is found at address -4(ea).
* The instruction's OP and OPX fields identify the operation to be
* performed.
*
* One instruction, muli, is an I-type instruction that is identified by
* an OP field of 0x24.
*
* muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24-
* 27 22 6 0 <-- LSB of field
*
* The remaining emulated instructions are R-type and have an OP field
* of 0x3a. Their OPX fields identify them.
*
* R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a-
* 27 22 17 11 6 0 <-- LSB of field
*
*
*/
/*
* Split the instruction into its fields. We need 4*A, 4*B, and 4*C as
* offsets to the stack pointer for access to the stored register values.
*/
/* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */
roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */
roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */
roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */
srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */
xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */
roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */
andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */
xori r3, r3, 0x40
andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */
andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */
andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */
/* Now either
* r5 = OP
* r3 = 4*(A^16)
* r4 = IMM16 (sign extended)
* r6 = 4*(B^16)
* r7 = 4*(C^16)
* or
* r5 = OP
*/
/*
* Save everything on the stack to make it easy for the emulation routines
* to retrieve the source register operands. The exception entry code has
* already saved some of this so we don't need to do it all again.
*/
addi sp, sp, -60
stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */
/* Register at and r2-r15 have already been saved. */
stw r16, 0(sp)
stw r17, 4(sp)
stw r18, 8(sp)
stw r19, 12(sp)
stw r20, 16(sp)
stw r21, 20(sp)
stw r22, 24(sp)
stw r23, 28(sp)
/* et @ 32 - Has already been changed.*/
/* bt @ 36 - Usually isn't an operand. */
stw gp, 40(sp)
stw sp, 44(sp)
stw fp, 48(sp)
/* ea @ 52 - Don't bother to save - it's already been changed */
/* ba @ 56 - Breakpoint register usually isn't an operand */
/* ra @ 60 - Has already been saved */
/*
* Prepare for either multiplication or division loop.
* They both loop 32 times.
*/
movi r14, 32
/*
* Get the operands.
*
* It is necessary to check for muli because it uses an I-type instruction
* format, while the other instructions are have an R-type format.
*/
add r3, r3, sp /* r3 = address of A-operand. */
ldw r3, 0(r3) /* r3 = A-operand. */
movi r15, 0x24 /* muli opcode (I-type instruction format) */
beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */
add r6, r6, sp /* r6 = address of B-operand. */
ldw r6, 0(r6) /* r6 = B-operand. */
/* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */
/* IMM16 not needed, align OPX portion */
/* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */
/* Now
* r5 = OP
* r3 = src1
* r6 = src2
* r4 = OPX (no longer can be muli)
* r7 = 4*(C^16)
* r14 = loop counter
*/
/* ILLEGAL-INSTRUCTION EXCEPTION
* -----------------------------
*
* This code is for Nios II cores that generate exceptions when attempting
* to execute illegal instructions. Nios II cores that support an
* illegal-instruction exception are identified by the presence of the
* macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h .
*
* Remember that illegal instructions are different than unimplemented
* instructions. Illegal instructions are instruction encodings that
* have not been defined by the Nios II ISA. Unimplemented instructions
* are legal instructions that must be emulated by some Nios II cores.
*
* If we get here, all instructions except multiplies and divides
* are illegal.
*
* This code assumes that OP is not muli (because muli was tested above).
* All other multiplies and divides are legal. Anything else is illegal.
*/
movi r8, 0x3a /* OP for R-type mul* and div* */
bne r5, r8, .Lnot_muldiv
/* r15 already is 0x24 */ /* OPX of divu */
beq r4, r15, .Ldivide
movi r15,0x27 /* OPX of mul */
beq r4, r15, .Lmultiply
movi r15,0x07 /* OPX of mulxuu */
beq r4, r15, .Lmultiply
movi r15,0x17 /* OPX of mulxsu */
beq r4, r15, .Lmultiply
movi r15,0x1f /* OPX of mulxss */
beq r4, r15, .Lmultiply
movi r15,0x25 /* OPX of div */
bne r4, r15, .Lnot_muldiv
/* DIVISION
*
* Divide an unsigned dividend by an unsigned divisor using
* a shift-and-subtract algorithm. The example below shows
* 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a
* single register to store both the dividend and the quotient,
* allowing both values to be shifted with a single instruction.
*
* remainder dividend:quotient
* --------- -----------------
* initialize 00000000 00101011:
* shift 00000000 0101011:_
* remainder >= divisor? no 00000000 0101011:0
* shift 00000000 101011:0_
* remainder >= divisor? no 00000000 101011:00
* shift 00000001 01011:00_
* remainder >= divisor? no 00000001 01011:000
* shift 00000010 1011:000_
* remainder >= divisor? no 00000010 1011:0000
* shift 00000101 011:0000_
* remainder >= divisor? no 00000101 011:00000
* shift 00001010 11:00000_
* remainder >= divisor? yes 00001010 11:000001
* remainder -= divisor - 00000111
* ----------
* 00000011 11:000001
* shift 00000111 1:000001_
* remainder >= divisor? yes 00000111 1:0000011
* remainder -= divisor - 00000111
* ----------
* 00000000 1:0000011
* shift 00000001 :0000011_
* remainder >= divisor? no 00000001 :00000110
*
* The quotient is 00000110.
*/
.Ldivide:
/*
* Prepare for division by assuming the result
* is unsigned, and storing its "sign" as 0.
*/
movi r17, 0
/* Which division opcode? */
xori r15, r4, 0x25 /* OPX of div */
bne r15, zero, .Lunsigned_division
/*
* OPX is div. Determine and store the sign of the quotient.
* Then take the absolute value of both operands.
*/
xor r17, r3, r6 /* MSB contains sign of quotient */
bge r3, zero, 0f
sub r3, zero, r3 /* -r3 */
0:
bge r6, zero, 0f
sub r6, zero, r6 /* -r6 */
0:
.Lunsigned_division:
/* Initialize the unsigned-division loop. */
movi r13, 0 /* remainder = 0 */
/* Now
* r3 = dividend : quotient
* r4 = 0x25 for div, 0x24 for divu
* r6 = divisor
* r13 = remainder
* r14 = loop counter (already initialized to 32)
* r17 = MSB contains sign of quotient
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Ldivide_loop:
/*
* Division:
*
* (remainder:dividend:quotient) <<= 1;
*/
slli r13, r13, 1
cmplt r15, r3, zero /* r15 = MSB of r3 */
or r13, r13, r15
slli r3, r3, 1
/*
* if (remainder >= divisor)
* {
* set LSB of quotient
* remainder -= divisor;
* }
*/
bltu r13, r6, .Ldiv_skip
ori r3, r3, 1
sub r13, r13, r6
.Ldiv_skip:
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Ldivide_loop
mov r9, r3
/* Now
* r9 = quotient
* r4 = 0x25 for div, 0x24 for divu
* r7 = 4*(C^16)
* r17 = MSB contains sign of quotient
*/
/*
* Conditionally negate signed quotient. If quotient is unsigned,
* the sign already is initialized to 0.
*/
bge r17, zero, .Lstore_result
sub r9, zero, r9 /* -r9 */
br .Lstore_result
/* MULTIPLICATION
*
* A "product" is the number that one gets by summing a "multiplicand"
* several times. The "multiplier" specifies the number of copies of the
* multiplicand that are summed.
*
* Actual multiplication algorithms don't use repeated addition, however.
* Shift-and-add algorithms get the same answer as repeated addition, and
* they are faster. To compute the lower half of a product (pppp below)
* one shifts the product left before adding in each of the partial products
* (a * mmmm) through (d * mmmm).
*
* To compute the upper half of a product (PPPP below), one adds in the
* partial products (d * mmmm) through (a * mmmm), each time following the
* add by a right shift of the product.
*
* mmmm
* * abcd
* ------
* #### = d * mmmm
* #### = c * mmmm
* #### = b * mmmm
* #### = a * mmmm
* --------
* PPPPpppp
*
* The example above shows 4 partial products. Computing actual Nios II
* products requires 32 partials.
*
* It is possible to compute the result of mulxsu from the result of mulxuu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rA.
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*
* It is possible to compute the result of mulxss from the result of mulxsu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rB.
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*
*/
.Lmul_immed:
/* Opcode is muli. Change it into mul for remainder of algorithm. */
mov r7, r6 /* Field B is dest register, not field C. */
mov r6, r4 /* Field IMM16 is src2, not field B. */
movi r4, 0x27 /* OPX of mul is 0x27 */
.Lmultiply:
/* Initialize the multiplication loop. */
movi r9, 0 /* mul_product = 0 */
movi r10, 0 /* mulxuu_product = 0 */
mov r11, r6 /* save original multiplier for mulxsu and mulxss */
mov r12, r6 /* mulxuu_multiplier (will be shifted) */
movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */
/* Now
* r3 = multiplicand
* r6 = mul_multiplier
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r12 = mulxuu_multiplier
* r14 = loop counter (already initialized)
* r15 = temp
* r16 = 1
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Lmultiply_loop:
/*
* mul_product <<= 1;
* lsb = multiplier & 1;
*/
slli r9, r9, 1
andi r15, r12, 1
/*
* if (lsb == 1)
* {
* mulxuu_product += multiplicand;
* }
*/
beq r15, zero, .Lmulx_skip
add r10, r10, r3
cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */
ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */
.Lmulx_skip:
/*
* if (MSB of mul_multiplier == 1)
* {
* mul_product += multiplicand;
* }
*/
bge r6, zero, .Lmul_skip
add r9, r9, r3
.Lmul_skip:
/*
* mulxuu_product >>= 1; logical shift
* mul_multiplier <<= 1; done with MSB
* mulx_multiplier >>= 1; done with LSB
*/
srli r10, r10, 1
or r10, r10, r15 /* OR in the saved carry bit. */
slli r6, r6, 1
srli r12, r12, 1
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Lmultiply_loop
/*
* Multiply emulation loop done.
*/
/* Now
* r3 = multiplicand
* r4 = OPX
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r15 = temp
*/
/*
* Select/compute the result based on OPX.
*/
/* OPX == mul? Then store. */
xori r15, r4, 0x27
beq r15, zero, .Lstore_result
/* It's one of the mulx.. opcodes. Move over the result. */
mov r9, r10
/* OPX == mulxuu? Then store. */
xori r15, r4, 0x07
beq r15, zero, .Lstore_result
/* Compute mulxsu
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*/
bge r3, zero, .Lmulxsu_skip
sub r9, r9, r11
.Lmulxsu_skip:
/* OPX == mulxsu? Then store. */
xori r15, r4, 0x17
beq r15, zero, .Lstore_result
/* Compute mulxss
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*/
bge r11, zero, .Lmulxss_skip
sub r9, r9, r3
.Lmulxss_skip:
/* At this point, assume that OPX is mulxss, so store */
.Lstore_result:
add r7, r7, sp
stw r9, 0(r7)
ldw r16, 0(sp)
ldw r17, 4(sp)
ldw r18, 8(sp)
ldw r19, 12(sp)
ldw r20, 16(sp)
ldw r21, 20(sp)
ldw r22, 24(sp)
ldw r23, 28(sp)
/* bt @ 32 - Breakpoint register usually isn't an operand. */
/* et @ 36 - Don't corrupt et. */
/* gp @ 40 - Don't corrupt gp. */
/* sp @ 44 - Don't corrupt sp. */
ldw fp, 48(sp)
/* ea @ 52 - Don't corrupt ea. */
/* ba @ 56 - Breakpoint register usually isn't an operand. */
addi sp, sp, 60
br .Lexception_exit
.Lnot_muldiv:
addi sp, sp, 60
.section .exceptions.exit.label
.Lexception_exit:
|
agural/FPGA-Oscilloscope
| 2,989
|
osc/software/osc_bsp/HAL/src/alt_software_exception.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This file provides the global symbol: software_exception. It is provided to
* support legacy code, and should not be used by new software.
*
* It is used by legacy code to invoke the software exception handler as
* defined by version 1.0 of the Nios II kit. It should only be used when you
* are providing your own interrupt entry point, i.e. you are not using
* alt_irq_entry.
*/
#include "system.h"
/*
* Pull in the exception handler.
*/
.globl alt_exception
.section .exceptions.entry.label, "xa"
.globl software_exception
.type software_exception, @function
software_exception:
|
agural/FPGA-Oscilloscope
| 16,254
|
osc/software/osc_bsp/HAL/src/crt0.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
#include "nios2.h"
/* Setup header files to work with assembler code. */
#define ALT_ASM_SRC
/* Debug logging facility */
#include "sys/alt_log_printf.h"
/*************************************************************************\
| MACROS |
\*************************************************************************/
/*
* The new build tools explicitly define macros when alt_load()
* must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that
* those macros are controlling if alt_load() needs to be called.
*/
#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED
/* Need to call alt_load() if any of these sections are being copied. */
#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS)
#define CALL_ALT_LOAD
#endif
#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* The legacy build tools use the following macros to detect when alt_load()
* needs to be called.
*/
#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \
((res##_BASE != rodata##_BASE) || \
(res##_BASE != rwdata##_BASE) || \
(res##_BASE != exc##_BASE))
#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \
__ALT_LOAD_SECTIONS(res, text, rodata, exc)
#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \
ALT_RODATA_DEVICE, \
ALT_RWDATA_DEVICE, \
ALT_EXCEPTIONS_DEVICE)
/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */
#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS
#define CALL_ALT_LOAD
#endif
#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* When the legacy build tools define a macro called ALT_NO_BOOTLOADER,
* it indicates that initialization code is allowed at the reset address.
* The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for
* the same purpose.
*/
#ifdef ALT_NO_BOOTLOADER
#define ALT_ALLOW_CODE_AT_RESET
#endif
/*************************************************************************\
| EXTERNAL REFERENCES |
\*************************************************************************/
/*
* The entry point for user code is either "main" in hosted mode, or
* "alt_main" in standalone mode. These are explicitly referenced here,
* to ensure they are built into the executable. This allows the user
* to build them into libraries, rather than supplying them in object
* files at link time.
*/
.globl main
.globl alt_main
/*
* Create a reference to the software multiply/divide and trap handers,
* so that if they are provided, they will appear in the executable.
*/
#ifndef ALT_NO_INSTRUCTION_EMULATION
.globl alt_exception_muldiv
#endif
#ifdef ALT_TRAP_HANDLER
.globl alt_exception_trap
#endif
/*
* Linker defined symbols used to initialize bss.
*/
.globl __bss_start
.globl __bss_end
/*************************************************************************\
| RESET SECTION (.entry) |
\*************************************************************************/
/*
* This is the reset entry point for Nios II.
*
* At reset, only the cache line which contain the reset vector is
* initialized by the hardware. The code within the first cache line
* initializes the remainder of the instruction cache.
*/
.section .entry, "xa"
.align 5
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* Some tools want to know where the reset vector is.
* Code isn't always provided at the reset vector but at least the
* __reset label always contains the reset vector address because
* it is defined at the start of the .entry section.
*/
.globl __reset
.type __reset, @function
__reset:
/*
* Initialize the instruction cache if present (i.e. size > 0) and
* reset code is allowed unless optimizing for RTL simulation.
* RTL simulations can ensure the instruction cache is already initialized
* so skipping this loop speeds up RTL simulation.
*/
#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE)
/* Assume the instruction cache size is always a power of two. */
#if NIOS2_ICACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_ICACHE_SIZE)
#else
movui r2, NIOS2_ICACHE_SIZE
#endif
0:
initi r2
addi r2, r2, -NIOS2_ICACHE_LINE_SIZE
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 1, 1, 0b, 1b
.popsection
#endif /* Initialize Instruction Cache */
/*
* Jump to the _start entry point in the .text section if reset code
* is allowed or if optimizing for RTL simulation.
*/
#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
/* Jump to the _start entry point in the .text section. */
movhi r1, %hi(_start)
ori r1, r1, %lo(_start)
jmp r1
.size __reset, . - __reset
#endif /* Jump to _start */
/*
* When not using exit, provide an _exit symbol to prevent unresolved
* references to _exit from the linker script.
*/
#ifdef ALT_NO_EXIT
.globl _exit
_exit:
#endif
/*************************************************************************\
| TEXT SECTION (.text) |
\*************************************************************************/
/*
* Start of the .text section, and also the code entry point when
* the code is executed by a bootloader rather than directly from reset.
*/
.section .text
.align 2
.globl _start
.type _start, @function
_start:
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Ensure that the current register set is 0 upon
* entry to this code. Switch register set to 0 by
* writing zero to SSTATUS register and executing an ERET instruction
* to set STATUS.CRS to 0.
*/
/* Get the current register set number (STATUS.CRS). */
rdctl r2, status
andi r2, r2, NIOS2_STATUS_CRS_MSK
/* Skip switching register set if STATUS.CRS is 0. */
beq r2, zero, 0f
/* Set SSTATUS to 0 to get to set SSTATUS.PRS to 0. */
.set nobreak
movui sstatus, 0
.set break
/* Switch to register set 0 and jump to label. */
movhi ea, %hi(0f)
ori ea, ea, %lo(0f)
eret
0:
#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */
/*
* Initialize the data cache if present (i.e. size > 0).
* Skip initialization if optimizing for RTL simulation and ECC isn't present.
* RTL simulations can ensure the data cache tag RAM is already initialized
* (but not the data RAM for ECC) so skipping this speeds up RTL simulation.
*
* When ECC is present, need to execute initd for each word address
* to ensure ECC parity bits in data RAM get initialized.
* Otherwise, only need to execute initd for each line address.
*/
#if NIOS2_DCACHE_SIZE > 0 && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
/* Assume the data cache size is always a power of two. */
#if NIOS2_DCACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_DCACHE_SIZE)
#else
movui r2, NIOS2_DCACHE_SIZE
#endif
0:
initd 0(r2)
#ifdef NIOS2_ECC_PRESENT
addi r2, r2, -4
#else
addi r2, r2, -NIOS2_DCACHE_LINE_SIZE
#endif
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 2, 1, 0b, 1b
.popsection
#endif /* Initialize Data Cache */
/* Log that caches have been initialized. */
ALT_LOG_PUTS(alt_log_msg_cache)
/* Log that the stack pointer is about to be setup. */
ALT_LOG_PUTS(alt_log_msg_stackpointer)
/*
* Now that the caches are initialized, set up the stack pointer and global pointer.
* The values provided by the linker are assumed to be correctly aligned.
*/
movhi sp, %hi(__alt_stack_pointer)
ori sp, sp, %lo(__alt_stack_pointer)
movhi gp, %hi(_gp)
ori gp, gp, %lo(_gp)
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
movui r1, 0
movui r2, 0
movui r3, 0
movui r4, 0
movui r5, 0
movui r6, 0
movui r7, 0
movui r8, 0
movui r9, 0
movui r10, 0
movui r11, 0
movui r12, 0
movui r13, 0
movui r14, 0
movui r15, 0
movui r16, 0
movui r17, 0
movui r18, 0
movui r19, 0
movui r20, 0
movui r21, 0
movui r22, 0
movui r23, 0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it is already been initialized. */
movui r28, 0 /* fp */
movui r29, 0 /* ea */
.set nobreak
movui r30, 0 /* sstatus */
.set break
movui r31, 0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Setup registers in shadow register sets
* from 1 to NIOS2_NUM_OF_SHADOW_REG_SETS.
*/
movui r2, 0 /* Contains value written into STATUS */
movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS /* counter */
movhi r4, 1 /* Constant to increment STATUS.PRS */
.Linitialize_shadow_registers:
/* Increment STATUS.PRS */
add r2, r2, r4
wrctl status, r2
/* Clear r0 in the shadow register set (not done by hardware) */
wrprs r0, r0
/* Write the GP in previous register set */
wrprs gp, gp
/*
* Only write the SP in previous register set
* if using the separate exception stack. For normal case (single stack),
* funnel code would read the SP from previous register set with a RDPRS.
*/
#ifdef ALT_INTERRUPT_STACK
movhi et, %hiadj(__alt_interrupt_stack_pointer)
addi et, et, %lo(__alt_interrupt_stack_pointer)
wrprs sp, et
#endif /* ALT_INTERRUPT_STACK */
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
wrprs r1, r0
wrprs r2, r0
wrprs r3, r0
wrprs r4, r0
wrprs r5, r0
wrprs r6, r0
wrprs r7, r0
wrprs r8, r0
wrprs r9, r0
wrprs r10, r0
wrprs r11, r0
wrprs r12, r0
wrprs r13, r0
wrprs r14, r0
wrprs r15, r0
wrprs r16, r0
wrprs r17, r0
wrprs r18, r0
wrprs r19, r0
wrprs r20, r0
wrprs r21, r0
wrprs r22, r0
wrprs r23, r0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it was initialized above or will be by a rdprs if not above */
wrprs r28, r0 /* fp */
wrprs r29, r0 /* ea */
wrprs r30, r0 /* ba */
wrprs r31, r0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
/* Decrement shadow register set counter */
addi r3, r3, -1
/* Done if index is 0. */
bne r3, zero, .Linitialize_shadow_registers
#endif /* (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) */
/*
* Clear the BSS if not optimizing for RTL simulation.
*
* This uses the symbols: __bss_start and __bss_end, which are defined
* by the linker script. They mark the begining and the end of the bss
* region. The linker script guarantees that these values are word aligned.
*/
#ifndef ALT_SIM_OPTIMIZE
/* Log that the BSS is about to be cleared. */
ALT_LOG_PUTS(alt_log_msg_bss)
movhi r2, %hi(__bss_start)
ori r2, r2, %lo(__bss_start)
movhi r3, %hi(__bss_end)
ori r3, r3, %lo(__bss_end)
beq r2, r3, 1f
0:
stw zero, (r2)
addi r2, r2, 4
bltu r2, r3, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 3, 1, 0b, 1b
.popsection
#endif /* ALT_SIM_OPTIMIZE */
/*
* The alt_load() facility is normally used when there is no bootloader.
* It copies some sections into RAM so it acts like a mini-bootloader.
*/
#ifdef CALL_ALT_LOAD
#ifdef ALT_STACK_CHECK
/*
* If the user has selected stack checking then we need to set up a safe
* value in the stack limit register so that the relocation functions
* don't think the stack has overflowed (the contents of the rwdata
* section aren't defined until alt_load() has been called).
*/
mov et, zero
#endif
call alt_load
#endif /* CALL_ALT_LOAD */
#ifdef ALT_STACK_CHECK
/*
* Set up the stack limit (if required). The linker has set up the
* copy of the variable which is in memory.
*/
ldw et, %gprel(alt_stack_limit_value)(gp)
#endif
/* Log that alt_main is about to be called. */
ALT_LOG_PUTS(alt_log_msg_alt_main)
/* Call the C entry point. It should never return. */
call alt_main
/* Wait in infinite loop in case alt_main does return. */
alt_after_alt_main:
br alt_after_alt_main
.size _start, . - _start
/*
* Add information about the stack base if stack overflow checking is enabled.
*/
#ifdef ALT_STACK_CHECK
.globl alt_stack_limit_value
.section .sdata,"aws",@progbits
.align 2
.type alt_stack_limit_value, @object
.size alt_stack_limit_value, 4
alt_stack_limit_value:
.long __alt_stack_limit
#endif
|
agural/FPGA-Oscilloscope
| 8,293
|
osc/software/osc_bsp/HAL/src/alt_mcount.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/* mcount or _mcount is inserted by GCC before the function prologue of every
* function when a program is compiled for profiling. At the start of mcount,
* we guarantee that:
* ra = self_pc (an address in the function which called mcount)
* r8 = from_pc (an address in the function which called mcount's caller)
*
* Because this is always called at the start of a function we can corrupt
* r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain
* function arguments for the instrumented function) or r8 (which holds ra
* for the instrumented function).
*/
.global __mcount_fn_head
.global mcount
/* _mcount is used by gcc4 */
.global _mcount
_mcount:
mcount:
/* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose
* the bucket because bits 1:0 will always be 0, and because the distribution
* of values for bits 4:2 won't be even (aligning on cache line boundaries
* will skew it). Higher bits should be fairly random.
*/
/* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */
srli r2, ra, 3
movhi r3, %hiadj(__mcount_fn_head)
addi r3, r3, %lo(__mcount_fn_head)
andi r2, r2, 0xFC
add r11, r2, r3
/* The fast case is where we have already allocated a function arc, and so
* also a function pointer.
*/
/* First find the function being called (using self_pc) */
mov r10, r11
0:
ldw r10, 0(r10)
beq r10, zero, .Lnew_arc
ldw r2, 4(r10)
bne r2, ra, 0b
/* Found a function entry for this PC. Now look for an arc with a matching
* from_pc value. There will always be at least one arc. */
ldw r3, 8(r10)
0:
ldw r2, 4(r3)
beq r2, r8, .Lfound_arc
ldw r3, 0(r3)
bne r3, zero, 0b
.Lnew_arc:
addi sp, sp, -24
.LCFI0:
stw ra, 0(sp)
stw r4, 4(sp)
stw r5, 8(sp)
stw r6, 12(sp)
stw r7, 16(sp)
stw r8, 20(sp)
.LCFI1:
/* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */
mov r4, ra
mov r5, r8
mov r6, r10
mov r7, r11
call __mcount_record
/* restore registers from the stack */
ldw ra, 0(sp)
ldw r4, 4(sp)
ldw r5, 8(sp)
ldw r6, 12(sp)
ldw r7, 16(sp)
ldw r8, 20(sp)
addi sp, sp, 24
.LCFI2:
ret
.Lfound_arc:
/* We've found the correct arc record. Increment the count and return */
ldw r2, 8(r3)
addi r2, r2, 1
stw r2, 8(r3)
ret
.Lmcount_end:
/*
* Dwarf2 debug information for the function. This provides GDB with the
* information it needs to backtrace out of this function.
*/
.section .debug_frame,"",@progbits
.LCIE:
.4byte 2f - 1f /* Length */
1:
.4byte 0xffffffff /* CIE id */
.byte 0x1 /* Version */
.string "" /* Augmentation */
.uleb128 0x1 /* Code alignment factor */
.sleb128 -4 /* Data alignment factor */
.byte 0x1f /* Return address register */
.byte 0xc /* Define CFA */
.uleb128 0x1b /* Register 27 (sp) */
.uleb128 0x0 /* Offset 0 */
.align 2 /* Padding */
2:
.LFDE_mcount:
.4byte 2f - 1f /* Length */
1:
.4byte .LCIE /* Pointer to CIE */
.4byte mcount /* Start of table entry */
.4byte .Lmcount_end - mcount /* Size of table entry */
.byte 0x4 /* Advance location */
.4byte .LCFI0 - mcount /* to .LCFI0 */
.byte 0xe /* Define CFA offset */
.uleb128 24 /* to 24 */
.byte 0x4 /* Advance location */
.4byte .LCFI1 - .LCFI0 /* to .LCFI1 */
.byte 0x9f /* Store ra */
.uleb128 0x6 /* at CFA-24 */
.byte 0x84 /* Store r4 */
.uleb128 0x5 /* at CFA-20 */
.byte 0x85 /* Store r5 */
.uleb128 0x4 /* at CFA-16 */
.byte 0x86 /* Store r6 */
.uleb128 0x3 /* at CFA-12 */
.byte 0x87 /* Store r7 */
.uleb128 0x2 /* at CFA-8 */
.byte 0x88 /* Store r8 */
.uleb128 0x1 /* at CFA-4 */
.byte 0x4 /* Advance location */
.4byte .LCFI2 - .LCFI1 /* to .LCFI2 */
.byte 0xe /* Define CFA offset */
.uleb128 0 /* to 0 */
.byte 0x8 /* Same value */
.uleb128 31 /* for ra */
.byte 0x8 /* Same value */
.uleb128 4 /* for r4 */
.byte 0x8 /* Same value */
.uleb128 5 /* for r5 */
.byte 0x8 /* Same value */
.uleb128 6 /* for r6 */
.byte 0x8 /* Same value */
.uleb128 7 /* for r7 */
.byte 0x8 /* Same value */
.uleb128 8 /* for r8 */
.align 2
2:
|
agural/FPGA-Oscilloscope
| 5,245
|
osc/software/osc_bsp/HAL/src/alt_ecc_fatal_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the code called at the beginning of the exception handler
* to detect a likely fatal ECC error exception and then jump to
* user-provided code to handle it.
*
* This code is pulled in from a .globl in alt_ecc_fatal_exception.c.
* This scheme is used so that if a handler is never registered, then this
* code will not appear in the generated executable, thereby improving
* code footprint.
*
* This code is located in its own section that the linker script
* explicitly mentions and ensures it gets linked at the beginning
* of the exception handler.
*/
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.section .exceptions.entry.ecc_fatal, "xa"
/*
* This might be handling an unrecoverable ECC error exception
* in the register file and/or data cache.
* Must avoid reading registers or performing load/store instructions
* before this is determined because they could trigger another
* unrecoverable ECC error exception and create an infinite loop.
*
* The EXCEPTION register is always present when ECC is present.
* Bit 31 of this register indicates that there was an unrecoverable
* ECC error exception in the register file and/or data cache.
* Test this (using blt to check sign bit) to determine if this is
* what we are dealing with. Otherwise, just do normal processing.
*
* Jump to an application-provided routine to handle this condition.
* Pass in the return address in the et register in case this code
* can clean up the ECC error and then return here (unlikely).
*
* Runtime stack checking can't be enabled when ECC is present
* because they both want to use the et register.
*/
rdctl et, exception
bge et, r0, alt_exception_not_ecc_fatal /* Not ECCFTL if bit 31 is 0 */
/*
* Load ECC fatal handler pointer into et register.
* Using a ldwio is safe because it completely bypasses the data cache.
*/
movhi et, %hi(alt_exception_ecc_fatal_handler)
ori et, et, %lo(alt_exception_ecc_fatal_handler)
ldwio et, 0(et)
/*
* If ECC fatal handler pointer is not 0, assume a handler
* has been provided by the application.
*/
beq et, r0, alt_exception_not_ecc_fatal
/*
* The et register contains the address of the ECC fatal handler.
* Jump to this address to invoke the handler.
*/
jmp et
/*
* An ECC fatal handler can jump to this label if it able
* to recover from the fatal error (rare) and wants to continue
* with normal exception processing.
*/
.globl alt_exception_not_ecc_fatal
alt_exception_not_ecc_fatal:
|
agural/FPGA-Oscilloscope
| 6,366
|
osc/Copy of software/keytest/keyint.S
|
################################################################################
# #
# Key Interrupt Handler #
# Rotary Encoder and Menu Button Routines #
# EE/CS 52 #
# #
################################################################################
/*
* Albert Gural
* EE/CS 52
* TA: Dan Pipe-Mazo
*
* File Description: TODO
*
* Table of Contents: TODO
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo Initial Revision.
* 05/14/2014 Albert Gural Begain writing assembly functions to handle
* keypress interrupts.
*
*/
/* Local Include Files */
#include "keyint.m"
#include "interfac.h"
#include "../keytest_bsp/system.h"
/*#include "../keytest_bsp/drivers/inc/altera_avalon_pio_regs.h"
#include "../keytest_bsp/HAL/inc/sys/alt_irq.h"
*/
.section .text #start code section
.macro PUSH reg
subi sp, sp, 4
stw \reg, 0(sp)
.endm
.macro POP reg
ldw \reg, 0(sp)
addi sp, sp, 4
.endm
.macro SAVE
PUSH r31
PUSH fp
mov fp, sp
.endm
.macro RESTORE
mov sp, fp
POP fp
POP r31
.endm
/*
* key_int_installer
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 05/18/2014 Albert Gural Initial revision.
*
*/
.global key_int_installer
.type key_int_installer, @function
key_int_installer:
SAVE
# Enable all switch interrupts.
movhi r8, %hi(KEY_INPUT_BASE)
ori r8, r8, %lo(KEY_INPUT_BASE)
movhi r9, %hi(SWITCH_ALL)
ori r9, r9, %lo(SWITCH_ALL)
stw r9, PIO_IRQ_MASK(r8)
# Install the interrupt handler
mov r4, r0
movi r5, KEY_INPUT_IRQ
movhi r6, %hi(key_handler)
ori r6, r6, %lo(key_handler)
mov r7, r0
PUSH r0
call alt_ic_isr_register
POP r0
key_int_installer_done:
RESTORE
ret
/*
* key_handler
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 05/18/2014 Albert Gural Initial revision.
*
*/
/*void gen_pb_interrupt_handler(void* isr_context) {
IOWR_ALTERA_AVALON_PIO_IRQ_MASK(0x00051010, 0);
int edge_cap = IORD_ALTERA_AVALON_PIO_EDGE_CAP(0x00051010);
int x = (edge_cap & 0x0002) >> 1;
x *= 2;
IOWR_ALTERA_AVALON_PIO_EDGE_CAP(0x00051010, 0x000fffff);
IOWR_ALTERA_AVALON_PIO_IRQ_MASK(0x00051010, 0x000fffff);
return;
}*/
.type key_handler,@function
key_handler:
SAVE
# Key should now be available. Update key_press.
movi r8, 1
movia r9, key_press
stb r8, (r9)
# Clear interrupts.
movhi r8, %hi(KEY_INPUT_BASE)
ori r8, r8, %lo(KEY_INPUT_BASE)
stw r0, PIO_IRQ_MASK(r8)
# Get the edge capture register.
movhi r8, %hi(KEY_INPUT_BASE)
ori r8, r8, %lo(KEY_INPUT_BASE)
ldw r8, PIO_EDGE_CAP(r8)
# Check each bit (starting at 0) and see if set.
movi r9, 1
movi r11, 0
loop_keys:
and r10, r8, r9
bne r10, r0, key_lookup
slli r9, r9, 1
addi r11, r11, 1
br loop_keys
key_lookup:
movia r8, key_map
add r8, r8, r11
ldb r8, (r8)
movia r10, key_value
stb r8, (r10)
# Clear the edge capture register (write 1 to clear).
movhi r8, %hi(KEY_INPUT_BASE)
ori r8, r8, %lo(KEY_INPUT_BASE)
movhi r9, %hi(SWITCH_ALL)
ori r9, r9, %lo(SWITCH_ALL)
stw r9, PIO_EDGE_CAP(r8)
# Re-enable interrupts.
movhi r8, %hi(KEY_INPUT_BASE)
ori r8, r8, %lo(KEY_INPUT_BASE)
movhi r9, %hi(SWITCH_ALL)
ori r9, r9, %lo(SWITCH_ALL)
stw r9, PIO_IRQ_MASK(r8)
key_hndler_done:
RESTORE
ret
/*
* key_available
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 05/18/2014 Albert Gural Initial revision.
*
*/
.global key_available
.type key_available, @function
key_available:
SAVE
movia r2, key_press
ldb r2, (r2)
key_available_done:
RESTORE
ret
/*
* key_available
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 05/18/2014 Albert Gural Initial revision.
*
*/
.global getkey
.type getkey, @function
getkey:
SAVE
# Block until legal key arrives (which is also when key_press = TRUE).
movia r8, key_value
ldb r8, (r8)
movi r9, KEY_ILLEGAL
beq r8, r9, getkey
# Get return value.
movia r2, key_value
ldb r2, (r2)
# Update key_value with KEY_ILLEGAL.
movia r10, key_value
stb r9, (r10)
# Update key_press with FALSE.
movia r10, key_press
stb r0, (r10)
getkey_done:
RESTORE
ret
/*
* key_map
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 05/18/2014 Albert Gural Initial revision.
*
*/
key_map: .byte KEY_MENU
.byte KEY_UP
.byte KEY_DOWN
.byte KEY_LEFT
.byte KEY_RIGHT
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_MENU
.byte KEY_ILLEGAL
.section .data #start data section
key_press: .byte 0 # Gives whether a key has been pressed.
key_value: .byte 0 # Gives the value of the pressed key.
|
agural/FPGA-Oscilloscope
| 1,624
|
osc/Copy of software/osc/testvram.S
|
################################################################################
# #
# VRAM Test Code #
# Test code for VRAM #
# EE/CS 52 #
# #
################################################################################
/*
* Albert Gural
* EE/CS 52
* TA: Dan Pipe-Mazo
*
* File Description: TODO
*
* Table of Contents: TODO
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo Initial Revision.
* 05/14/2014 Albert Gural Begain writing testcode assembly.
*
*/
/* Local Include Files */
#include "../osc_bsp/system.h"
.equ VRAM_OFFSET, 0x00080000
.section .text #start code section
/*
* key_handler
*
* Description:
*
* Operation:
*
* Arguments:
*
* Return Value:
*
* Local Variables:
*
* Shared Variables:
*
* Global Variables:
*
* Input:
*
* Output:
*
* Error Handling:
*
* Limitations:
*
* Algorithms:
* Data Structures:
*
* Registers Changed:
*
* Revision History:
* 02/09/2012 Dan Pipe-Mazo initial revision
*
*/
.global TestVRAM
.type TestVRAM,@function
TestVRAM:
movhi r8, %hi(VRAM_OFFSET)
ori r8, r8, %lo(VRAM_OFFSET)
mov r9, r0
sthio r9, (r8)
addi r8, r8, 2
addi r9, r9, 1
jmpi TestVRAM
TestVRAMdone:
ret
.section .data #start data section
#TODO
|
agural/FPGA-Oscilloscope
| 3,594
|
osc/Copy of software/keytest_bsp/HAL/src/alt_exception_trap.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the trap exception handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_trap
alt_exception_trap:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
.Ltrap_handler:
/*
* Did a trap instruction cause the exception?
*
* The instruction which the exception occurred on has been loaded
* into r2 by code in alt_exception_entry.S
*
*/
movhi r3,0x003b /* upper half of trap opcode */
ori r3,r3,0x683a /* lower half of trap opcode */
bne r2,r3,.Lnot_trap
/*
* There is no trap handler defined here, and so executing a trap
* instruction causes a software break. If you provide a trap handler,
* then you must replace the break instruction below with your handler.
* Your handler must preserve ea and the usual callee saved registers.
*/
break
br .Lexception_exit
.Lnot_trap:
.section .exceptions.exit.label
.Lexception_exit:
|
agural/FPGA-Oscilloscope
| 4,685
|
osc/Copy of software/keytest_bsp/HAL/src/alt_irq_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the interrupt exception entry point code, which saves all the
* registers and calls the interrupt handler. It should be pulled in using
* a .globl from alt_irq_register.c. This scheme is used so that if an
* interrupt is never registered, then this code will not appear in the
* generated executable, thereby improving code footprint.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the compiler.
*/
.set noat
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.globl alt_irq_entry
.section .exceptions.entry.label, "xa"
alt_irq_entry:
/*
* Section .exceptions.entry is in alt_exception_entry.S
* This saves all the caller saved registers and reads estatus into r5
*/
.section .exceptions.irqtest, "xa"
#ifdef ALT_CI_INTERRUPT_VECTOR_N
/*
* Use the interrupt vector custom instruction if present to accelerate
* this code.
* If the interrupt vector custom instruction returns a negative
* value, there are no interrupts active (estatus.pie is 0
* or ipending is 0) so assume it is a software exception.
*/
custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0
blt r4, r0, .Lnot_irq
#else
/*
* Test to see if the exception was a software exception or caused
* by an external interrupt, and vector accordingly.
*/
rdctl r4, ipending
andi r2, r5, 1
beq r2, zero, .Lnot_irq
beq r4, zero, .Lnot_irq
#endif /* ALT_CI_INTERRUPT_VECTOR_N */
.section .exceptions.irqhandler, "xa"
/*
* Now that all necessary registers have been preserved, call
* alt_irq_handler() to process the interrupts.
*/
call alt_irq_handler
.section .exceptions.irqreturn, "xa"
br .Lexception_exit
.section .exceptions.notirq.label, "xa"
.Lnot_irq:
/*
* Section .exceptions.exit is in alt_exception_entry.S
* This restores all the caller saved registers
*/
.section .exceptions.exit.label
.Lexception_exit:
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