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agural/FPGA-Oscilloscope
| 1,742
|
osc/Copy of software/keytest_bsp/HAL/src/alt_log_macro.S
|
/* alt_log_macro.S
*
* Implements the function tx_log_str, called by the assembly macro
* ALT_LOG_PUTS(). The macro will be empty when logging is turned off,
* and this function will not be compiled. When logging is on,
* this function is used to print out the strings defined in the beginning
* of alt_log_printf.c, using port information taken from system.h and
* alt_log_printf.h.
*
* This routine only handles strings, and sends a character into the defined
* output device's output buffer when the device is ready. It's intended for
* debugging purposes, where messages can be set to print out at certain
* points in the boot code to indicate the progress of the program.
*
*/
#ifndef __ALT_LOG_MACROS__
#define __ALT_LOG_MACROS__
/* define this flag to skip assembly-incompatible parts
* of various include files. */
#define ALT_ASM_SRC
#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined.
#include "system.h"
#include "sys/alt_log_printf.h"
.global tx_log_str
tx_log_str:
/* load base uart / jtag uart address into r6 */
movhi r6, %hiadj(ALT_LOG_PORT_BASE)
addi r6, r6, %lo(ALT_LOG_PORT_BASE)
tx_next_char:
/* if pointer points to null, return
* r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */
ldb r7, (r4)
beq r0, r7, end_tx
/* check device transmit ready */
wait_tx_ready_loop:
ldwio r5, ALT_LOG_PRINT_REG_OFFSET(r6)
andi r5, r5, ALT_LOG_PRINT_MSK
beq r5, r0, wait_tx_ready_loop
/* write char */
stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6)
/* advance string pointer */
addi r4, r4, 1
br tx_next_char
end_tx:
ret
#endif
#endif /* __ALT_LOG_MACROS__ */
|
agural/FPGA-Oscilloscope
| 14,886
|
osc/Copy of software/keytest_bsp/HAL/src/alt_exception_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the exception entry point code, which saves all the caller saved
* registers and then handles the appropriate exception. It should be pulled
* in using a .globl from all the exception handler routines. This scheme is
* used so that if an interrupt is never registered, then this code will not
* appear in the generated executable, thereby improving code footprint.
*
* If an external interrpt controller (EIC) is present, it will supply an
* interrupt vector address to the processor when an interrupt occurs. For
* The Altera Vectored Interrupt Controller (VIC) driver will establish a
* vector table and the processor will jump directly to the appropriate
* table entry, funnel routine, and then user ISR. This will bypass this code
* in entirety. This code might still be linked into a system with an EIC,
* but would then be used only for non-interrupt exceptions.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* The top and bottom of the exception stack.
*/
#ifdef ALT_EXCEPTION_STACK
.globl __alt_exception_stack_pointer
#ifdef ALT_STACK_CHECK
.globl __alt_exception_stack_limit
/*
* Store the value of the stack limit after interrupt somewhere.
*/
.globl alt_exception_old_stack_limit
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* The code at alt_exception is located at the Nios II exception
* handler address.
*/
.section .exceptions.entry.label, "xa"
.globl alt_exception
.type alt_exception, @function
alt_exception:
/*
* The code for detecting a likely fatal ECC exception is
* linked here before the normal exception handler code if required.
* This is handled by the linker script and putting that code
* in the .exceptions.entry.ecc_fatal section.
*/
/*
* Now start the normal exception handler code.
*/
.section .exceptions.entry, "xa"
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
/*
* When runtime stack checking is enabled, the et register
* contains the stack limit. Save this in memory before
* overwriting the et register.
*/
stw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
/*
* Switch to the exception stack and save the current stack pointer
* in memory. Uses the et register as a scratch register.
*/
movhi et, %hi(__alt_exception_stack_pointer - 80)
ori et, et, %lo(__alt_exception_stack_pointer - 80)
stw sp, 76(et)
mov sp, et
#ifdef ALT_STACK_CHECK
/*
* Restore the stack limit from memory to the et register.
*/
movhi et, %hi(__alt_exception_stack_limit)
ori et, et, %lo(__alt_exception_stack_limit)
stw et, %gprel(alt_stack_limit_value)(gp)
#endif /* ALT_STACK_CHECK */
#else /* ALT_EXCEPTION_STACK disabled */
/*
* Reserve space on normal stack for registers about to be pushed.
*/
addi sp, sp, -76
#ifdef ALT_STACK_CHECK
/* Ensure stack didn't just overflow. */
bltu sp, et, .Lstack_overflow
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* Process an exception. For all exceptions we must preserve all
* caller saved registers on the stack (See the Nios II ABI
* documentation for details).
*
* Leave a gap in the stack frame at 4(sp) for the muldiv handler to
* store zero into.
*/
stw ra, 0(sp)
stw r1, 8(sp)
stw r2, 12(sp)
stw r3, 16(sp)
stw r4, 20(sp)
stw r5, 24(sp)
stw r6, 28(sp)
stw r7, 32(sp)
rdctl r5, estatus /* Read early to avoid usage stall */
stw r8, 36(sp)
stw r9, 40(sp)
stw r10, 44(sp)
stw r11, 48(sp)
stw r12, 52(sp)
stw r13, 56(sp)
stw r14, 60(sp)
stw r15, 64(sp)
/*
* ea-4 contains the address of the instruction being executed
* when the exception occured. For interrupt exceptions, we will
* will be re-issue the isntruction. Store it in 72(sp)
*/
stw r5, 68(sp) /* estatus */
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
/*
* The interrupt testing code (.exceptions.irqtest) will be
* linked here. If the Internal Interrupt Controller (IIC) is
* present (an EIC is not present), the presense of an interrupt
* is determined by examining CPU control registers or an interrupt
* custom instruction, if present.
*
* If the IIC is used and an interrupt is active, the code linked
* here will call the HAL IRQ handler (alt_irq_handler()) which
* successively calls registered interrupt handler(s) until no
* interrupts remain pending. It then jumps to .exceptions.exit. If
* there is no interrupt then it continues to .exception.notirq, below.
*/
.section .exceptions.notirq, "xa"
/*
* Prepare to service unimplemtned instructions or traps,
* each of which is optionally inked into section .exceptions.soft,
* which will preceed .exceptions.unknown below.
*
* Unlike interrupts, we want to skip the exception-causing instructon
* upon completion, so we write ea (address of instruction *after*
* the one where the exception occured) into 72(sp). The actual
* instruction that caused the exception is written in r2, which these
* handlers will utilize.
*/
stw ea, 72(sp) /* Don't re-issue */
ldw r2, -4(ea) /* Instruction that caused exception */
/*
* Other exception handling code, if enabled, will be linked here.
* This includes unimplemted (multiply/divide) instruction support
* (a BSP generaton option), and a trap handler (that would typically
* be augmented with user-specific code). These are not linked in by
* default.
*/
/*
* In the context of linker sections, "unknown" are all exceptions
* not handled by the built-in handlers above (interupt, and trap or
* unimplemented instruction decoding, if enabled).
*
* Advanced exception types can be serviced by registering a handler.
* To do so, enable the "Enable Instruction-related Exception API" HAL
* BSP setting. If this setting is disabled, this handler code will
* either break (if the debug core is present) or enter an infinite
* loop because we don't how how to handle the exception.
*/
.section .exceptions.unknown
#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
/*
* The C-based HAL routine alt_instruction_exception_entry() will
* attempt to service the exception by calling a user-registered
* exception handler using alt_instruction_exception_register().
* If no handler was registered it will either break (if the
* debugger is present) or go into an infinite loop since the
* handling behavior is undefined; in that case we will not return here.
*/
/* Load exception-causing address as first argument (r4) */
addi r4, ea, -4
/* Call the instruction-exception entry */
call alt_instruction_exception_entry
/*
* If alt_instruction_exception_entry() returned, the exception was
* serviced by a user-registered routine. Its return code (now in r2)
* indicates whether to re-issue or skip the exception-causing
* instruction
*
* Return code was 0: Skip. The instruction after the exception is
* already stored in 72(sp).
*/
bne r2, r0, .Lexception_exit
/*
* Otherwise, modify 72(sp) to re-issue the instruction that caused the
* exception.
*/
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */
/*
* We got here because an instruction-related exception occured, but the
* handler API was not compiled in. We do not presume to know how to
* handle it. If the debugger is present, break, otherwise hang.
*
* If you get here then one of the following could have happened:
*
* - An instruction-generated exception occured, and the processor
* does not have the extra exceptions feature enabled, or you
* have not registered a handler using
* alt_instruction_exception_register()
*
* Some examples of instruction-generated exceptions and why they
* might occur:
*
* - Your program could have been compiled for a full-featured
* Nios II core, but it is running on a smaller core, and
* instruction emulation has been disabled by defining
* ALT_NO_INSTRUCTION_EMULATION.
*
* You can work around the problem by re-enabling instruction
* emulation, or you can figure out why your program is being
* compiled for a system other than the one that it is running on.
*
* - Your program has executed a trap instruction, but has not
* implemented a handler for this instruction.
*
* - Your program has executed an illegal instruction (one which is
* not defined in the instruction set).
*
* - Your processor includes an MMU or MPU, and you have enabled it
* before registering an exception handler to service exceptions it
* generates.
*
* The problem could also be hardware related:
* - If your hardware is broken and is generating spurious interrupts
* (a peripheral which negates its interrupt output before its
* interrupt handler has been executed will cause spurious
* interrupts)
*/
alt_exception_unknown:
#ifdef NIOS2_HAS_DEBUG_STUB
/*
* Either tell the user now (if there is a debugger attached) or go into
* the debug monitor which will loop until a debugger is attached.
*/
break
#else /* NIOS2_HAS_DEBUG_STUB disabled */
/*
* If there is no debug stub, an infinite loop is more useful.
*/
br alt_exception_unknown
#endif /* NIOS2_HAS_DEBUG_STUB */
#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
.section .exceptions.exit.label
.Lexception_exit:
.section .exceptions.exit, "xa"
/*
* Restore the saved registers, so that all general purpose registers
* have been restored to their state at the time the interrupt occured.
*/
ldw r5, 68(sp)
ldw ea, 72(sp) /* This becomes the PC once eret is executed */
ldw ra, 0(sp)
wrctl estatus, r5
ldw r1, 8(sp)
ldw r2, 12(sp)
ldw r3, 16(sp)
ldw r4, 20(sp)
ldw r5, 24(sp)
ldw r6, 28(sp)
ldw r7, 32(sp)
#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
ldw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif
ldw r8, 36(sp)
ldw r9, 40(sp)
ldw r10, 44(sp)
ldw r11, 48(sp)
ldw r12, 52(sp)
ldw r13, 56(sp)
ldw r14, 60(sp)
ldw r15, 64(sp)
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
stw et, %gprel(alt_stack_limit_value)(gp)
stw zero, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
ldw sp, 76(sp)
#else /* ALT_EXCEPTION_STACK disabled */
addi sp, sp, 76
#endif /* ALT_EXCEPTION_STACK */
/*
* Return to the interrupted instruction.
*/
eret
#ifdef ALT_STACK_CHECK
.Lstack_overflow:
break 3
#endif /* ALT_STACK_CHECK */
|
agural/FPGA-Oscilloscope
| 21,315
|
osc/Copy of software/keytest_bsp/HAL/src/alt_exception_muldiv.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the software multiply/divide handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_muldiv
alt_exception_muldiv:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
/* INSTRUCTION EMULATION
* ---------------------
*
* Nios II processors generate exceptions for unimplemented instructions.
* The routines below emulate these instructions. Depending on the
* processor core, the only instructions that might need to be emulated
* are div, divu, mul, muli, mulxss, mulxsu, and mulxuu.
*
* The emulations match the instructions, except for the following
* limitations:
*
* 1) The emulation routines do not emulate the use of the exception
* temporary register (et) as a source operand because the exception
* handler already has modified it.
*
* 2) The routines do not emulate the use of the stack pointer (sp) or the
* exception return address register (ea) as a destination because
* modifying these registers crashes the exception handler or the
* interrupted routine.
*
* 3) To save code size, the routines do not emulate the use of the
* breakpoint registers (ba and bt) as operands.
*
* Detailed Design
* ---------------
*
* The emulation routines expect the contents of integer registers r0-r31
* to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The
* routines retrieve source operands from the stack and modify the
* destination register's value on the stack prior to the end of the
* exception handler. Then all registers except the destination register
* are restored to their previous values.
*
* The instruction that causes the exception is found at address -4(ea).
* The instruction's OP and OPX fields identify the operation to be
* performed.
*
* One instruction, muli, is an I-type instruction that is identified by
* an OP field of 0x24.
*
* muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24-
* 27 22 6 0 <-- LSB of field
*
* The remaining emulated instructions are R-type and have an OP field
* of 0x3a. Their OPX fields identify them.
*
* R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a-
* 27 22 17 11 6 0 <-- LSB of field
*
*
*/
/*
* Split the instruction into its fields. We need 4*A, 4*B, and 4*C as
* offsets to the stack pointer for access to the stored register values.
*/
/* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */
roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */
roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */
roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */
srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */
xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */
roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */
andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */
xori r3, r3, 0x40
andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */
andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */
andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */
/* Now either
* r5 = OP
* r3 = 4*(A^16)
* r4 = IMM16 (sign extended)
* r6 = 4*(B^16)
* r7 = 4*(C^16)
* or
* r5 = OP
*/
/*
* Save everything on the stack to make it easy for the emulation routines
* to retrieve the source register operands. The exception entry code has
* already saved some of this so we don't need to do it all again.
*/
addi sp, sp, -60
stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */
/* Register at and r2-r15 have already been saved. */
stw r16, 0(sp)
stw r17, 4(sp)
stw r18, 8(sp)
stw r19, 12(sp)
stw r20, 16(sp)
stw r21, 20(sp)
stw r22, 24(sp)
stw r23, 28(sp)
/* et @ 32 - Has already been changed.*/
/* bt @ 36 - Usually isn't an operand. */
stw gp, 40(sp)
stw sp, 44(sp)
stw fp, 48(sp)
/* ea @ 52 - Don't bother to save - it's already been changed */
/* ba @ 56 - Breakpoint register usually isn't an operand */
/* ra @ 60 - Has already been saved */
/*
* Prepare for either multiplication or division loop.
* They both loop 32 times.
*/
movi r14, 32
/*
* Get the operands.
*
* It is necessary to check for muli because it uses an I-type instruction
* format, while the other instructions are have an R-type format.
*/
add r3, r3, sp /* r3 = address of A-operand. */
ldw r3, 0(r3) /* r3 = A-operand. */
movi r15, 0x24 /* muli opcode (I-type instruction format) */
beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */
add r6, r6, sp /* r6 = address of B-operand. */
ldw r6, 0(r6) /* r6 = B-operand. */
/* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */
/* IMM16 not needed, align OPX portion */
/* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */
/* Now
* r5 = OP
* r3 = src1
* r6 = src2
* r4 = OPX (no longer can be muli)
* r7 = 4*(C^16)
* r14 = loop counter
*/
/* ILLEGAL-INSTRUCTION EXCEPTION
* -----------------------------
*
* This code is for Nios II cores that generate exceptions when attempting
* to execute illegal instructions. Nios II cores that support an
* illegal-instruction exception are identified by the presence of the
* macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h .
*
* Remember that illegal instructions are different than unimplemented
* instructions. Illegal instructions are instruction encodings that
* have not been defined by the Nios II ISA. Unimplemented instructions
* are legal instructions that must be emulated by some Nios II cores.
*
* If we get here, all instructions except multiplies and divides
* are illegal.
*
* This code assumes that OP is not muli (because muli was tested above).
* All other multiplies and divides are legal. Anything else is illegal.
*/
movi r8, 0x3a /* OP for R-type mul* and div* */
bne r5, r8, .Lnot_muldiv
/* r15 already is 0x24 */ /* OPX of divu */
beq r4, r15, .Ldivide
movi r15,0x27 /* OPX of mul */
beq r4, r15, .Lmultiply
movi r15,0x07 /* OPX of mulxuu */
beq r4, r15, .Lmultiply
movi r15,0x17 /* OPX of mulxsu */
beq r4, r15, .Lmultiply
movi r15,0x1f /* OPX of mulxss */
beq r4, r15, .Lmultiply
movi r15,0x25 /* OPX of div */
bne r4, r15, .Lnot_muldiv
/* DIVISION
*
* Divide an unsigned dividend by an unsigned divisor using
* a shift-and-subtract algorithm. The example below shows
* 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a
* single register to store both the dividend and the quotient,
* allowing both values to be shifted with a single instruction.
*
* remainder dividend:quotient
* --------- -----------------
* initialize 00000000 00101011:
* shift 00000000 0101011:_
* remainder >= divisor? no 00000000 0101011:0
* shift 00000000 101011:0_
* remainder >= divisor? no 00000000 101011:00
* shift 00000001 01011:00_
* remainder >= divisor? no 00000001 01011:000
* shift 00000010 1011:000_
* remainder >= divisor? no 00000010 1011:0000
* shift 00000101 011:0000_
* remainder >= divisor? no 00000101 011:00000
* shift 00001010 11:00000_
* remainder >= divisor? yes 00001010 11:000001
* remainder -= divisor - 00000111
* ----------
* 00000011 11:000001
* shift 00000111 1:000001_
* remainder >= divisor? yes 00000111 1:0000011
* remainder -= divisor - 00000111
* ----------
* 00000000 1:0000011
* shift 00000001 :0000011_
* remainder >= divisor? no 00000001 :00000110
*
* The quotient is 00000110.
*/
.Ldivide:
/*
* Prepare for division by assuming the result
* is unsigned, and storing its "sign" as 0.
*/
movi r17, 0
/* Which division opcode? */
xori r15, r4, 0x25 /* OPX of div */
bne r15, zero, .Lunsigned_division
/*
* OPX is div. Determine and store the sign of the quotient.
* Then take the absolute value of both operands.
*/
xor r17, r3, r6 /* MSB contains sign of quotient */
bge r3, zero, 0f
sub r3, zero, r3 /* -r3 */
0:
bge r6, zero, 0f
sub r6, zero, r6 /* -r6 */
0:
.Lunsigned_division:
/* Initialize the unsigned-division loop. */
movi r13, 0 /* remainder = 0 */
/* Now
* r3 = dividend : quotient
* r4 = 0x25 for div, 0x24 for divu
* r6 = divisor
* r13 = remainder
* r14 = loop counter (already initialized to 32)
* r17 = MSB contains sign of quotient
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Ldivide_loop:
/*
* Division:
*
* (remainder:dividend:quotient) <<= 1;
*/
slli r13, r13, 1
cmplt r15, r3, zero /* r15 = MSB of r3 */
or r13, r13, r15
slli r3, r3, 1
/*
* if (remainder >= divisor)
* {
* set LSB of quotient
* remainder -= divisor;
* }
*/
bltu r13, r6, .Ldiv_skip
ori r3, r3, 1
sub r13, r13, r6
.Ldiv_skip:
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Ldivide_loop
mov r9, r3
/* Now
* r9 = quotient
* r4 = 0x25 for div, 0x24 for divu
* r7 = 4*(C^16)
* r17 = MSB contains sign of quotient
*/
/*
* Conditionally negate signed quotient. If quotient is unsigned,
* the sign already is initialized to 0.
*/
bge r17, zero, .Lstore_result
sub r9, zero, r9 /* -r9 */
br .Lstore_result
/* MULTIPLICATION
*
* A "product" is the number that one gets by summing a "multiplicand"
* several times. The "multiplier" specifies the number of copies of the
* multiplicand that are summed.
*
* Actual multiplication algorithms don't use repeated addition, however.
* Shift-and-add algorithms get the same answer as repeated addition, and
* they are faster. To compute the lower half of a product (pppp below)
* one shifts the product left before adding in each of the partial products
* (a * mmmm) through (d * mmmm).
*
* To compute the upper half of a product (PPPP below), one adds in the
* partial products (d * mmmm) through (a * mmmm), each time following the
* add by a right shift of the product.
*
* mmmm
* * abcd
* ------
* #### = d * mmmm
* #### = c * mmmm
* #### = b * mmmm
* #### = a * mmmm
* --------
* PPPPpppp
*
* The example above shows 4 partial products. Computing actual Nios II
* products requires 32 partials.
*
* It is possible to compute the result of mulxsu from the result of mulxuu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rA.
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*
* It is possible to compute the result of mulxss from the result of mulxsu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rB.
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*
*/
.Lmul_immed:
/* Opcode is muli. Change it into mul for remainder of algorithm. */
mov r7, r6 /* Field B is dest register, not field C. */
mov r6, r4 /* Field IMM16 is src2, not field B. */
movi r4, 0x27 /* OPX of mul is 0x27 */
.Lmultiply:
/* Initialize the multiplication loop. */
movi r9, 0 /* mul_product = 0 */
movi r10, 0 /* mulxuu_product = 0 */
mov r11, r6 /* save original multiplier for mulxsu and mulxss */
mov r12, r6 /* mulxuu_multiplier (will be shifted) */
movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */
/* Now
* r3 = multiplicand
* r6 = mul_multiplier
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r12 = mulxuu_multiplier
* r14 = loop counter (already initialized)
* r15 = temp
* r16 = 1
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Lmultiply_loop:
/*
* mul_product <<= 1;
* lsb = multiplier & 1;
*/
slli r9, r9, 1
andi r15, r12, 1
/*
* if (lsb == 1)
* {
* mulxuu_product += multiplicand;
* }
*/
beq r15, zero, .Lmulx_skip
add r10, r10, r3
cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */
ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */
.Lmulx_skip:
/*
* if (MSB of mul_multiplier == 1)
* {
* mul_product += multiplicand;
* }
*/
bge r6, zero, .Lmul_skip
add r9, r9, r3
.Lmul_skip:
/*
* mulxuu_product >>= 1; logical shift
* mul_multiplier <<= 1; done with MSB
* mulx_multiplier >>= 1; done with LSB
*/
srli r10, r10, 1
or r10, r10, r15 /* OR in the saved carry bit. */
slli r6, r6, 1
srli r12, r12, 1
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Lmultiply_loop
/*
* Multiply emulation loop done.
*/
/* Now
* r3 = multiplicand
* r4 = OPX
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r15 = temp
*/
/*
* Select/compute the result based on OPX.
*/
/* OPX == mul? Then store. */
xori r15, r4, 0x27
beq r15, zero, .Lstore_result
/* It's one of the mulx.. opcodes. Move over the result. */
mov r9, r10
/* OPX == mulxuu? Then store. */
xori r15, r4, 0x07
beq r15, zero, .Lstore_result
/* Compute mulxsu
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*/
bge r3, zero, .Lmulxsu_skip
sub r9, r9, r11
.Lmulxsu_skip:
/* OPX == mulxsu? Then store. */
xori r15, r4, 0x17
beq r15, zero, .Lstore_result
/* Compute mulxss
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*/
bge r11, zero, .Lmulxss_skip
sub r9, r9, r3
.Lmulxss_skip:
/* At this point, assume that OPX is mulxss, so store */
.Lstore_result:
add r7, r7, sp
stw r9, 0(r7)
ldw r16, 0(sp)
ldw r17, 4(sp)
ldw r18, 8(sp)
ldw r19, 12(sp)
ldw r20, 16(sp)
ldw r21, 20(sp)
ldw r22, 24(sp)
ldw r23, 28(sp)
/* bt @ 32 - Breakpoint register usually isn't an operand. */
/* et @ 36 - Don't corrupt et. */
/* gp @ 40 - Don't corrupt gp. */
/* sp @ 44 - Don't corrupt sp. */
ldw fp, 48(sp)
/* ea @ 52 - Don't corrupt ea. */
/* ba @ 56 - Breakpoint register usually isn't an operand. */
addi sp, sp, 60
br .Lexception_exit
.Lnot_muldiv:
addi sp, sp, 60
.section .exceptions.exit.label
.Lexception_exit:
|
agural/FPGA-Oscilloscope
| 2,989
|
osc/Copy of software/keytest_bsp/HAL/src/alt_software_exception.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This file provides the global symbol: software_exception. It is provided to
* support legacy code, and should not be used by new software.
*
* It is used by legacy code to invoke the software exception handler as
* defined by version 1.0 of the Nios II kit. It should only be used when you
* are providing your own interrupt entry point, i.e. you are not using
* alt_irq_entry.
*/
#include "system.h"
/*
* Pull in the exception handler.
*/
.globl alt_exception
.section .exceptions.entry.label, "xa"
.globl software_exception
.type software_exception, @function
software_exception:
|
agural/FPGA-Oscilloscope
| 16,254
|
osc/Copy of software/keytest_bsp/HAL/src/crt0.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
#include "nios2.h"
/* Setup header files to work with assembler code. */
#define ALT_ASM_SRC
/* Debug logging facility */
#include "sys/alt_log_printf.h"
/*************************************************************************\
| MACROS |
\*************************************************************************/
/*
* The new build tools explicitly define macros when alt_load()
* must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that
* those macros are controlling if alt_load() needs to be called.
*/
#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED
/* Need to call alt_load() if any of these sections are being copied. */
#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS)
#define CALL_ALT_LOAD
#endif
#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* The legacy build tools use the following macros to detect when alt_load()
* needs to be called.
*/
#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \
((res##_BASE != rodata##_BASE) || \
(res##_BASE != rwdata##_BASE) || \
(res##_BASE != exc##_BASE))
#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \
__ALT_LOAD_SECTIONS(res, text, rodata, exc)
#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \
ALT_RODATA_DEVICE, \
ALT_RWDATA_DEVICE, \
ALT_EXCEPTIONS_DEVICE)
/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */
#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS
#define CALL_ALT_LOAD
#endif
#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* When the legacy build tools define a macro called ALT_NO_BOOTLOADER,
* it indicates that initialization code is allowed at the reset address.
* The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for
* the same purpose.
*/
#ifdef ALT_NO_BOOTLOADER
#define ALT_ALLOW_CODE_AT_RESET
#endif
/*************************************************************************\
| EXTERNAL REFERENCES |
\*************************************************************************/
/*
* The entry point for user code is either "main" in hosted mode, or
* "alt_main" in standalone mode. These are explicitly referenced here,
* to ensure they are built into the executable. This allows the user
* to build them into libraries, rather than supplying them in object
* files at link time.
*/
.globl main
.globl alt_main
/*
* Create a reference to the software multiply/divide and trap handers,
* so that if they are provided, they will appear in the executable.
*/
#ifndef ALT_NO_INSTRUCTION_EMULATION
.globl alt_exception_muldiv
#endif
#ifdef ALT_TRAP_HANDLER
.globl alt_exception_trap
#endif
/*
* Linker defined symbols used to initialize bss.
*/
.globl __bss_start
.globl __bss_end
/*************************************************************************\
| RESET SECTION (.entry) |
\*************************************************************************/
/*
* This is the reset entry point for Nios II.
*
* At reset, only the cache line which contain the reset vector is
* initialized by the hardware. The code within the first cache line
* initializes the remainder of the instruction cache.
*/
.section .entry, "xa"
.align 5
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* Some tools want to know where the reset vector is.
* Code isn't always provided at the reset vector but at least the
* __reset label always contains the reset vector address because
* it is defined at the start of the .entry section.
*/
.globl __reset
.type __reset, @function
__reset:
/*
* Initialize the instruction cache if present (i.e. size > 0) and
* reset code is allowed unless optimizing for RTL simulation.
* RTL simulations can ensure the instruction cache is already initialized
* so skipping this loop speeds up RTL simulation.
*/
#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE)
/* Assume the instruction cache size is always a power of two. */
#if NIOS2_ICACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_ICACHE_SIZE)
#else
movui r2, NIOS2_ICACHE_SIZE
#endif
0:
initi r2
addi r2, r2, -NIOS2_ICACHE_LINE_SIZE
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 1, 1, 0b, 1b
.popsection
#endif /* Initialize Instruction Cache */
/*
* Jump to the _start entry point in the .text section if reset code
* is allowed or if optimizing for RTL simulation.
*/
#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
/* Jump to the _start entry point in the .text section. */
movhi r1, %hi(_start)
ori r1, r1, %lo(_start)
jmp r1
.size __reset, . - __reset
#endif /* Jump to _start */
/*
* When not using exit, provide an _exit symbol to prevent unresolved
* references to _exit from the linker script.
*/
#ifdef ALT_NO_EXIT
.globl _exit
_exit:
#endif
/*************************************************************************\
| TEXT SECTION (.text) |
\*************************************************************************/
/*
* Start of the .text section, and also the code entry point when
* the code is executed by a bootloader rather than directly from reset.
*/
.section .text
.align 2
.globl _start
.type _start, @function
_start:
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Ensure that the current register set is 0 upon
* entry to this code. Switch register set to 0 by
* writing zero to SSTATUS register and executing an ERET instruction
* to set STATUS.CRS to 0.
*/
/* Get the current register set number (STATUS.CRS). */
rdctl r2, status
andi r2, r2, NIOS2_STATUS_CRS_MSK
/* Skip switching register set if STATUS.CRS is 0. */
beq r2, zero, 0f
/* Set SSTATUS to 0 to get to set SSTATUS.PRS to 0. */
.set nobreak
movui sstatus, 0
.set break
/* Switch to register set 0 and jump to label. */
movhi ea, %hi(0f)
ori ea, ea, %lo(0f)
eret
0:
#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */
/*
* Initialize the data cache if present (i.e. size > 0).
* Skip initialization if optimizing for RTL simulation and ECC isn't present.
* RTL simulations can ensure the data cache tag RAM is already initialized
* (but not the data RAM for ECC) so skipping this speeds up RTL simulation.
*
* When ECC is present, need to execute initd for each word address
* to ensure ECC parity bits in data RAM get initialized.
* Otherwise, only need to execute initd for each line address.
*/
#if NIOS2_DCACHE_SIZE > 0 && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
/* Assume the data cache size is always a power of two. */
#if NIOS2_DCACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_DCACHE_SIZE)
#else
movui r2, NIOS2_DCACHE_SIZE
#endif
0:
initd 0(r2)
#ifdef NIOS2_ECC_PRESENT
addi r2, r2, -4
#else
addi r2, r2, -NIOS2_DCACHE_LINE_SIZE
#endif
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 2, 1, 0b, 1b
.popsection
#endif /* Initialize Data Cache */
/* Log that caches have been initialized. */
ALT_LOG_PUTS(alt_log_msg_cache)
/* Log that the stack pointer is about to be setup. */
ALT_LOG_PUTS(alt_log_msg_stackpointer)
/*
* Now that the caches are initialized, set up the stack pointer and global pointer.
* The values provided by the linker are assumed to be correctly aligned.
*/
movhi sp, %hi(__alt_stack_pointer)
ori sp, sp, %lo(__alt_stack_pointer)
movhi gp, %hi(_gp)
ori gp, gp, %lo(_gp)
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
movui r1, 0
movui r2, 0
movui r3, 0
movui r4, 0
movui r5, 0
movui r6, 0
movui r7, 0
movui r8, 0
movui r9, 0
movui r10, 0
movui r11, 0
movui r12, 0
movui r13, 0
movui r14, 0
movui r15, 0
movui r16, 0
movui r17, 0
movui r18, 0
movui r19, 0
movui r20, 0
movui r21, 0
movui r22, 0
movui r23, 0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it is already been initialized. */
movui r28, 0 /* fp */
movui r29, 0 /* ea */
.set nobreak
movui r30, 0 /* sstatus */
.set break
movui r31, 0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Setup registers in shadow register sets
* from 1 to NIOS2_NUM_OF_SHADOW_REG_SETS.
*/
movui r2, 0 /* Contains value written into STATUS */
movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS /* counter */
movhi r4, 1 /* Constant to increment STATUS.PRS */
.Linitialize_shadow_registers:
/* Increment STATUS.PRS */
add r2, r2, r4
wrctl status, r2
/* Clear r0 in the shadow register set (not done by hardware) */
wrprs r0, r0
/* Write the GP in previous register set */
wrprs gp, gp
/*
* Only write the SP in previous register set
* if using the separate exception stack. For normal case (single stack),
* funnel code would read the SP from previous register set with a RDPRS.
*/
#ifdef ALT_INTERRUPT_STACK
movhi et, %hiadj(__alt_interrupt_stack_pointer)
addi et, et, %lo(__alt_interrupt_stack_pointer)
wrprs sp, et
#endif /* ALT_INTERRUPT_STACK */
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
wrprs r1, r0
wrprs r2, r0
wrprs r3, r0
wrprs r4, r0
wrprs r5, r0
wrprs r6, r0
wrprs r7, r0
wrprs r8, r0
wrprs r9, r0
wrprs r10, r0
wrprs r11, r0
wrprs r12, r0
wrprs r13, r0
wrprs r14, r0
wrprs r15, r0
wrprs r16, r0
wrprs r17, r0
wrprs r18, r0
wrprs r19, r0
wrprs r20, r0
wrprs r21, r0
wrprs r22, r0
wrprs r23, r0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it was initialized above or will be by a rdprs if not above */
wrprs r28, r0 /* fp */
wrprs r29, r0 /* ea */
wrprs r30, r0 /* ba */
wrprs r31, r0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
/* Decrement shadow register set counter */
addi r3, r3, -1
/* Done if index is 0. */
bne r3, zero, .Linitialize_shadow_registers
#endif /* (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) */
/*
* Clear the BSS if not optimizing for RTL simulation.
*
* This uses the symbols: __bss_start and __bss_end, which are defined
* by the linker script. They mark the begining and the end of the bss
* region. The linker script guarantees that these values are word aligned.
*/
#ifndef ALT_SIM_OPTIMIZE
/* Log that the BSS is about to be cleared. */
ALT_LOG_PUTS(alt_log_msg_bss)
movhi r2, %hi(__bss_start)
ori r2, r2, %lo(__bss_start)
movhi r3, %hi(__bss_end)
ori r3, r3, %lo(__bss_end)
beq r2, r3, 1f
0:
stw zero, (r2)
addi r2, r2, 4
bltu r2, r3, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 3, 1, 0b, 1b
.popsection
#endif /* ALT_SIM_OPTIMIZE */
/*
* The alt_load() facility is normally used when there is no bootloader.
* It copies some sections into RAM so it acts like a mini-bootloader.
*/
#ifdef CALL_ALT_LOAD
#ifdef ALT_STACK_CHECK
/*
* If the user has selected stack checking then we need to set up a safe
* value in the stack limit register so that the relocation functions
* don't think the stack has overflowed (the contents of the rwdata
* section aren't defined until alt_load() has been called).
*/
mov et, zero
#endif
call alt_load
#endif /* CALL_ALT_LOAD */
#ifdef ALT_STACK_CHECK
/*
* Set up the stack limit (if required). The linker has set up the
* copy of the variable which is in memory.
*/
ldw et, %gprel(alt_stack_limit_value)(gp)
#endif
/* Log that alt_main is about to be called. */
ALT_LOG_PUTS(alt_log_msg_alt_main)
/* Call the C entry point. It should never return. */
call alt_main
/* Wait in infinite loop in case alt_main does return. */
alt_after_alt_main:
br alt_after_alt_main
.size _start, . - _start
/*
* Add information about the stack base if stack overflow checking is enabled.
*/
#ifdef ALT_STACK_CHECK
.globl alt_stack_limit_value
.section .sdata,"aws",@progbits
.align 2
.type alt_stack_limit_value, @object
.size alt_stack_limit_value, 4
alt_stack_limit_value:
.long __alt_stack_limit
#endif
|
agural/FPGA-Oscilloscope
| 8,293
|
osc/Copy of software/keytest_bsp/HAL/src/alt_mcount.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/* mcount or _mcount is inserted by GCC before the function prologue of every
* function when a program is compiled for profiling. At the start of mcount,
* we guarantee that:
* ra = self_pc (an address in the function which called mcount)
* r8 = from_pc (an address in the function which called mcount's caller)
*
* Because this is always called at the start of a function we can corrupt
* r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain
* function arguments for the instrumented function) or r8 (which holds ra
* for the instrumented function).
*/
.global __mcount_fn_head
.global mcount
/* _mcount is used by gcc4 */
.global _mcount
_mcount:
mcount:
/* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose
* the bucket because bits 1:0 will always be 0, and because the distribution
* of values for bits 4:2 won't be even (aligning on cache line boundaries
* will skew it). Higher bits should be fairly random.
*/
/* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */
srli r2, ra, 3
movhi r3, %hiadj(__mcount_fn_head)
addi r3, r3, %lo(__mcount_fn_head)
andi r2, r2, 0xFC
add r11, r2, r3
/* The fast case is where we have already allocated a function arc, and so
* also a function pointer.
*/
/* First find the function being called (using self_pc) */
mov r10, r11
0:
ldw r10, 0(r10)
beq r10, zero, .Lnew_arc
ldw r2, 4(r10)
bne r2, ra, 0b
/* Found a function entry for this PC. Now look for an arc with a matching
* from_pc value. There will always be at least one arc. */
ldw r3, 8(r10)
0:
ldw r2, 4(r3)
beq r2, r8, .Lfound_arc
ldw r3, 0(r3)
bne r3, zero, 0b
.Lnew_arc:
addi sp, sp, -24
.LCFI0:
stw ra, 0(sp)
stw r4, 4(sp)
stw r5, 8(sp)
stw r6, 12(sp)
stw r7, 16(sp)
stw r8, 20(sp)
.LCFI1:
/* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */
mov r4, ra
mov r5, r8
mov r6, r10
mov r7, r11
call __mcount_record
/* restore registers from the stack */
ldw ra, 0(sp)
ldw r4, 4(sp)
ldw r5, 8(sp)
ldw r6, 12(sp)
ldw r7, 16(sp)
ldw r8, 20(sp)
addi sp, sp, 24
.LCFI2:
ret
.Lfound_arc:
/* We've found the correct arc record. Increment the count and return */
ldw r2, 8(r3)
addi r2, r2, 1
stw r2, 8(r3)
ret
.Lmcount_end:
/*
* Dwarf2 debug information for the function. This provides GDB with the
* information it needs to backtrace out of this function.
*/
.section .debug_frame,"",@progbits
.LCIE:
.4byte 2f - 1f /* Length */
1:
.4byte 0xffffffff /* CIE id */
.byte 0x1 /* Version */
.string "" /* Augmentation */
.uleb128 0x1 /* Code alignment factor */
.sleb128 -4 /* Data alignment factor */
.byte 0x1f /* Return address register */
.byte 0xc /* Define CFA */
.uleb128 0x1b /* Register 27 (sp) */
.uleb128 0x0 /* Offset 0 */
.align 2 /* Padding */
2:
.LFDE_mcount:
.4byte 2f - 1f /* Length */
1:
.4byte .LCIE /* Pointer to CIE */
.4byte mcount /* Start of table entry */
.4byte .Lmcount_end - mcount /* Size of table entry */
.byte 0x4 /* Advance location */
.4byte .LCFI0 - mcount /* to .LCFI0 */
.byte 0xe /* Define CFA offset */
.uleb128 24 /* to 24 */
.byte 0x4 /* Advance location */
.4byte .LCFI1 - .LCFI0 /* to .LCFI1 */
.byte 0x9f /* Store ra */
.uleb128 0x6 /* at CFA-24 */
.byte 0x84 /* Store r4 */
.uleb128 0x5 /* at CFA-20 */
.byte 0x85 /* Store r5 */
.uleb128 0x4 /* at CFA-16 */
.byte 0x86 /* Store r6 */
.uleb128 0x3 /* at CFA-12 */
.byte 0x87 /* Store r7 */
.uleb128 0x2 /* at CFA-8 */
.byte 0x88 /* Store r8 */
.uleb128 0x1 /* at CFA-4 */
.byte 0x4 /* Advance location */
.4byte .LCFI2 - .LCFI1 /* to .LCFI2 */
.byte 0xe /* Define CFA offset */
.uleb128 0 /* to 0 */
.byte 0x8 /* Same value */
.uleb128 31 /* for ra */
.byte 0x8 /* Same value */
.uleb128 4 /* for r4 */
.byte 0x8 /* Same value */
.uleb128 5 /* for r5 */
.byte 0x8 /* Same value */
.uleb128 6 /* for r6 */
.byte 0x8 /* Same value */
.uleb128 7 /* for r7 */
.byte 0x8 /* Same value */
.uleb128 8 /* for r8 */
.align 2
2:
|
agural/FPGA-Oscilloscope
| 5,245
|
osc/Copy of software/keytest_bsp/HAL/src/alt_ecc_fatal_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the code called at the beginning of the exception handler
* to detect a likely fatal ECC error exception and then jump to
* user-provided code to handle it.
*
* This code is pulled in from a .globl in alt_ecc_fatal_exception.c.
* This scheme is used so that if a handler is never registered, then this
* code will not appear in the generated executable, thereby improving
* code footprint.
*
* This code is located in its own section that the linker script
* explicitly mentions and ensures it gets linked at the beginning
* of the exception handler.
*/
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.section .exceptions.entry.ecc_fatal, "xa"
/*
* This might be handling an unrecoverable ECC error exception
* in the register file and/or data cache.
* Must avoid reading registers or performing load/store instructions
* before this is determined because they could trigger another
* unrecoverable ECC error exception and create an infinite loop.
*
* The EXCEPTION register is always present when ECC is present.
* Bit 31 of this register indicates that there was an unrecoverable
* ECC error exception in the register file and/or data cache.
* Test this (using blt to check sign bit) to determine if this is
* what we are dealing with. Otherwise, just do normal processing.
*
* Jump to an application-provided routine to handle this condition.
* Pass in the return address in the et register in case this code
* can clean up the ECC error and then return here (unlikely).
*
* Runtime stack checking can't be enabled when ECC is present
* because they both want to use the et register.
*/
rdctl et, exception
bge et, r0, alt_exception_not_ecc_fatal /* Not ECCFTL if bit 31 is 0 */
/*
* Load ECC fatal handler pointer into et register.
* Using a ldwio is safe because it completely bypasses the data cache.
*/
movhi et, %hi(alt_exception_ecc_fatal_handler)
ori et, et, %lo(alt_exception_ecc_fatal_handler)
ldwio et, 0(et)
/*
* If ECC fatal handler pointer is not 0, assume a handler
* has been provided by the application.
*/
beq et, r0, alt_exception_not_ecc_fatal
/*
* The et register contains the address of the ECC fatal handler.
* Jump to this address to invoke the handler.
*/
jmp et
/*
* An ECC fatal handler can jump to this label if it able
* to recover from the fatal error (rare) and wants to continue
* with normal exception processing.
*/
.globl alt_exception_not_ecc_fatal
alt_exception_not_ecc_fatal:
|
agural/FPGA-Oscilloscope
| 3,594
|
osc/Copy of software/osc_bsp/HAL/src/alt_exception_trap.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the trap exception handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_trap
alt_exception_trap:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
.Ltrap_handler:
/*
* Did a trap instruction cause the exception?
*
* The instruction which the exception occurred on has been loaded
* into r2 by code in alt_exception_entry.S
*
*/
movhi r3,0x003b /* upper half of trap opcode */
ori r3,r3,0x683a /* lower half of trap opcode */
bne r2,r3,.Lnot_trap
/*
* There is no trap handler defined here, and so executing a trap
* instruction causes a software break. If you provide a trap handler,
* then you must replace the break instruction below with your handler.
* Your handler must preserve ea and the usual callee saved registers.
*/
break
br .Lexception_exit
.Lnot_trap:
.section .exceptions.exit.label
.Lexception_exit:
|
agural/FPGA-Oscilloscope
| 4,685
|
osc/Copy of software/osc_bsp/HAL/src/alt_irq_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the interrupt exception entry point code, which saves all the
* registers and calls the interrupt handler. It should be pulled in using
* a .globl from alt_irq_register.c. This scheme is used so that if an
* interrupt is never registered, then this code will not appear in the
* generated executable, thereby improving code footprint.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the compiler.
*/
.set noat
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.globl alt_irq_entry
.section .exceptions.entry.label, "xa"
alt_irq_entry:
/*
* Section .exceptions.entry is in alt_exception_entry.S
* This saves all the caller saved registers and reads estatus into r5
*/
.section .exceptions.irqtest, "xa"
#ifdef ALT_CI_INTERRUPT_VECTOR_N
/*
* Use the interrupt vector custom instruction if present to accelerate
* this code.
* If the interrupt vector custom instruction returns a negative
* value, there are no interrupts active (estatus.pie is 0
* or ipending is 0) so assume it is a software exception.
*/
custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0
blt r4, r0, .Lnot_irq
#else
/*
* Test to see if the exception was a software exception or caused
* by an external interrupt, and vector accordingly.
*/
rdctl r4, ipending
andi r2, r5, 1
beq r2, zero, .Lnot_irq
beq r4, zero, .Lnot_irq
#endif /* ALT_CI_INTERRUPT_VECTOR_N */
.section .exceptions.irqhandler, "xa"
/*
* Now that all necessary registers have been preserved, call
* alt_irq_handler() to process the interrupts.
*/
call alt_irq_handler
.section .exceptions.irqreturn, "xa"
br .Lexception_exit
.section .exceptions.notirq.label, "xa"
.Lnot_irq:
/*
* Section .exceptions.exit is in alt_exception_entry.S
* This restores all the caller saved registers
*/
.section .exceptions.exit.label
.Lexception_exit:
|
agural/FPGA-Oscilloscope
| 1,742
|
osc/Copy of software/osc_bsp/HAL/src/alt_log_macro.S
|
/* alt_log_macro.S
*
* Implements the function tx_log_str, called by the assembly macro
* ALT_LOG_PUTS(). The macro will be empty when logging is turned off,
* and this function will not be compiled. When logging is on,
* this function is used to print out the strings defined in the beginning
* of alt_log_printf.c, using port information taken from system.h and
* alt_log_printf.h.
*
* This routine only handles strings, and sends a character into the defined
* output device's output buffer when the device is ready. It's intended for
* debugging purposes, where messages can be set to print out at certain
* points in the boot code to indicate the progress of the program.
*
*/
#ifndef __ALT_LOG_MACROS__
#define __ALT_LOG_MACROS__
/* define this flag to skip assembly-incompatible parts
* of various include files. */
#define ALT_ASM_SRC
#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined.
#include "system.h"
#include "sys/alt_log_printf.h"
.global tx_log_str
tx_log_str:
/* load base uart / jtag uart address into r6 */
movhi r6, %hiadj(ALT_LOG_PORT_BASE)
addi r6, r6, %lo(ALT_LOG_PORT_BASE)
tx_next_char:
/* if pointer points to null, return
* r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */
ldb r7, (r4)
beq r0, r7, end_tx
/* check device transmit ready */
wait_tx_ready_loop:
ldwio r5, ALT_LOG_PRINT_REG_OFFSET(r6)
andi r5, r5, ALT_LOG_PRINT_MSK
beq r5, r0, wait_tx_ready_loop
/* write char */
stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6)
/* advance string pointer */
addi r4, r4, 1
br tx_next_char
end_tx:
ret
#endif
#endif /* __ALT_LOG_MACROS__ */
|
agural/FPGA-Oscilloscope
| 14,886
|
osc/Copy of software/osc_bsp/HAL/src/alt_exception_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the exception entry point code, which saves all the caller saved
* registers and then handles the appropriate exception. It should be pulled
* in using a .globl from all the exception handler routines. This scheme is
* used so that if an interrupt is never registered, then this code will not
* appear in the generated executable, thereby improving code footprint.
*
* If an external interrpt controller (EIC) is present, it will supply an
* interrupt vector address to the processor when an interrupt occurs. For
* The Altera Vectored Interrupt Controller (VIC) driver will establish a
* vector table and the processor will jump directly to the appropriate
* table entry, funnel routine, and then user ISR. This will bypass this code
* in entirety. This code might still be linked into a system with an EIC,
* but would then be used only for non-interrupt exceptions.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* The top and bottom of the exception stack.
*/
#ifdef ALT_EXCEPTION_STACK
.globl __alt_exception_stack_pointer
#ifdef ALT_STACK_CHECK
.globl __alt_exception_stack_limit
/*
* Store the value of the stack limit after interrupt somewhere.
*/
.globl alt_exception_old_stack_limit
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* The code at alt_exception is located at the Nios II exception
* handler address.
*/
.section .exceptions.entry.label, "xa"
.globl alt_exception
.type alt_exception, @function
alt_exception:
/*
* The code for detecting a likely fatal ECC exception is
* linked here before the normal exception handler code if required.
* This is handled by the linker script and putting that code
* in the .exceptions.entry.ecc_fatal section.
*/
/*
* Now start the normal exception handler code.
*/
.section .exceptions.entry, "xa"
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
/*
* When runtime stack checking is enabled, the et register
* contains the stack limit. Save this in memory before
* overwriting the et register.
*/
stw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
/*
* Switch to the exception stack and save the current stack pointer
* in memory. Uses the et register as a scratch register.
*/
movhi et, %hi(__alt_exception_stack_pointer - 80)
ori et, et, %lo(__alt_exception_stack_pointer - 80)
stw sp, 76(et)
mov sp, et
#ifdef ALT_STACK_CHECK
/*
* Restore the stack limit from memory to the et register.
*/
movhi et, %hi(__alt_exception_stack_limit)
ori et, et, %lo(__alt_exception_stack_limit)
stw et, %gprel(alt_stack_limit_value)(gp)
#endif /* ALT_STACK_CHECK */
#else /* ALT_EXCEPTION_STACK disabled */
/*
* Reserve space on normal stack for registers about to be pushed.
*/
addi sp, sp, -76
#ifdef ALT_STACK_CHECK
/* Ensure stack didn't just overflow. */
bltu sp, et, .Lstack_overflow
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* Process an exception. For all exceptions we must preserve all
* caller saved registers on the stack (See the Nios II ABI
* documentation for details).
*
* Leave a gap in the stack frame at 4(sp) for the muldiv handler to
* store zero into.
*/
stw ra, 0(sp)
stw r1, 8(sp)
stw r2, 12(sp)
stw r3, 16(sp)
stw r4, 20(sp)
stw r5, 24(sp)
stw r6, 28(sp)
stw r7, 32(sp)
rdctl r5, estatus /* Read early to avoid usage stall */
stw r8, 36(sp)
stw r9, 40(sp)
stw r10, 44(sp)
stw r11, 48(sp)
stw r12, 52(sp)
stw r13, 56(sp)
stw r14, 60(sp)
stw r15, 64(sp)
/*
* ea-4 contains the address of the instruction being executed
* when the exception occured. For interrupt exceptions, we will
* will be re-issue the isntruction. Store it in 72(sp)
*/
stw r5, 68(sp) /* estatus */
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
/*
* The interrupt testing code (.exceptions.irqtest) will be
* linked here. If the Internal Interrupt Controller (IIC) is
* present (an EIC is not present), the presense of an interrupt
* is determined by examining CPU control registers or an interrupt
* custom instruction, if present.
*
* If the IIC is used and an interrupt is active, the code linked
* here will call the HAL IRQ handler (alt_irq_handler()) which
* successively calls registered interrupt handler(s) until no
* interrupts remain pending. It then jumps to .exceptions.exit. If
* there is no interrupt then it continues to .exception.notirq, below.
*/
.section .exceptions.notirq, "xa"
/*
* Prepare to service unimplemtned instructions or traps,
* each of which is optionally inked into section .exceptions.soft,
* which will preceed .exceptions.unknown below.
*
* Unlike interrupts, we want to skip the exception-causing instructon
* upon completion, so we write ea (address of instruction *after*
* the one where the exception occured) into 72(sp). The actual
* instruction that caused the exception is written in r2, which these
* handlers will utilize.
*/
stw ea, 72(sp) /* Don't re-issue */
ldw r2, -4(ea) /* Instruction that caused exception */
/*
* Other exception handling code, if enabled, will be linked here.
* This includes unimplemted (multiply/divide) instruction support
* (a BSP generaton option), and a trap handler (that would typically
* be augmented with user-specific code). These are not linked in by
* default.
*/
/*
* In the context of linker sections, "unknown" are all exceptions
* not handled by the built-in handlers above (interupt, and trap or
* unimplemented instruction decoding, if enabled).
*
* Advanced exception types can be serviced by registering a handler.
* To do so, enable the "Enable Instruction-related Exception API" HAL
* BSP setting. If this setting is disabled, this handler code will
* either break (if the debug core is present) or enter an infinite
* loop because we don't how how to handle the exception.
*/
.section .exceptions.unknown
#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
/*
* The C-based HAL routine alt_instruction_exception_entry() will
* attempt to service the exception by calling a user-registered
* exception handler using alt_instruction_exception_register().
* If no handler was registered it will either break (if the
* debugger is present) or go into an infinite loop since the
* handling behavior is undefined; in that case we will not return here.
*/
/* Load exception-causing address as first argument (r4) */
addi r4, ea, -4
/* Call the instruction-exception entry */
call alt_instruction_exception_entry
/*
* If alt_instruction_exception_entry() returned, the exception was
* serviced by a user-registered routine. Its return code (now in r2)
* indicates whether to re-issue or skip the exception-causing
* instruction
*
* Return code was 0: Skip. The instruction after the exception is
* already stored in 72(sp).
*/
bne r2, r0, .Lexception_exit
/*
* Otherwise, modify 72(sp) to re-issue the instruction that caused the
* exception.
*/
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */
/*
* We got here because an instruction-related exception occured, but the
* handler API was not compiled in. We do not presume to know how to
* handle it. If the debugger is present, break, otherwise hang.
*
* If you get here then one of the following could have happened:
*
* - An instruction-generated exception occured, and the processor
* does not have the extra exceptions feature enabled, or you
* have not registered a handler using
* alt_instruction_exception_register()
*
* Some examples of instruction-generated exceptions and why they
* might occur:
*
* - Your program could have been compiled for a full-featured
* Nios II core, but it is running on a smaller core, and
* instruction emulation has been disabled by defining
* ALT_NO_INSTRUCTION_EMULATION.
*
* You can work around the problem by re-enabling instruction
* emulation, or you can figure out why your program is being
* compiled for a system other than the one that it is running on.
*
* - Your program has executed a trap instruction, but has not
* implemented a handler for this instruction.
*
* - Your program has executed an illegal instruction (one which is
* not defined in the instruction set).
*
* - Your processor includes an MMU or MPU, and you have enabled it
* before registering an exception handler to service exceptions it
* generates.
*
* The problem could also be hardware related:
* - If your hardware is broken and is generating spurious interrupts
* (a peripheral which negates its interrupt output before its
* interrupt handler has been executed will cause spurious
* interrupts)
*/
alt_exception_unknown:
#ifdef NIOS2_HAS_DEBUG_STUB
/*
* Either tell the user now (if there is a debugger attached) or go into
* the debug monitor which will loop until a debugger is attached.
*/
break
#else /* NIOS2_HAS_DEBUG_STUB disabled */
/*
* If there is no debug stub, an infinite loop is more useful.
*/
br alt_exception_unknown
#endif /* NIOS2_HAS_DEBUG_STUB */
#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
.section .exceptions.exit.label
.Lexception_exit:
.section .exceptions.exit, "xa"
/*
* Restore the saved registers, so that all general purpose registers
* have been restored to their state at the time the interrupt occured.
*/
ldw r5, 68(sp)
ldw ea, 72(sp) /* This becomes the PC once eret is executed */
ldw ra, 0(sp)
wrctl estatus, r5
ldw r1, 8(sp)
ldw r2, 12(sp)
ldw r3, 16(sp)
ldw r4, 20(sp)
ldw r5, 24(sp)
ldw r6, 28(sp)
ldw r7, 32(sp)
#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
ldw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif
ldw r8, 36(sp)
ldw r9, 40(sp)
ldw r10, 44(sp)
ldw r11, 48(sp)
ldw r12, 52(sp)
ldw r13, 56(sp)
ldw r14, 60(sp)
ldw r15, 64(sp)
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
stw et, %gprel(alt_stack_limit_value)(gp)
stw zero, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
ldw sp, 76(sp)
#else /* ALT_EXCEPTION_STACK disabled */
addi sp, sp, 76
#endif /* ALT_EXCEPTION_STACK */
/*
* Return to the interrupted instruction.
*/
eret
#ifdef ALT_STACK_CHECK
.Lstack_overflow:
break 3
#endif /* ALT_STACK_CHECK */
|
agural/FPGA-Oscilloscope
| 21,315
|
osc/Copy of software/osc_bsp/HAL/src/alt_exception_muldiv.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the software multiply/divide handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_muldiv
alt_exception_muldiv:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
/* INSTRUCTION EMULATION
* ---------------------
*
* Nios II processors generate exceptions for unimplemented instructions.
* The routines below emulate these instructions. Depending on the
* processor core, the only instructions that might need to be emulated
* are div, divu, mul, muli, mulxss, mulxsu, and mulxuu.
*
* The emulations match the instructions, except for the following
* limitations:
*
* 1) The emulation routines do not emulate the use of the exception
* temporary register (et) as a source operand because the exception
* handler already has modified it.
*
* 2) The routines do not emulate the use of the stack pointer (sp) or the
* exception return address register (ea) as a destination because
* modifying these registers crashes the exception handler or the
* interrupted routine.
*
* 3) To save code size, the routines do not emulate the use of the
* breakpoint registers (ba and bt) as operands.
*
* Detailed Design
* ---------------
*
* The emulation routines expect the contents of integer registers r0-r31
* to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The
* routines retrieve source operands from the stack and modify the
* destination register's value on the stack prior to the end of the
* exception handler. Then all registers except the destination register
* are restored to their previous values.
*
* The instruction that causes the exception is found at address -4(ea).
* The instruction's OP and OPX fields identify the operation to be
* performed.
*
* One instruction, muli, is an I-type instruction that is identified by
* an OP field of 0x24.
*
* muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24-
* 27 22 6 0 <-- LSB of field
*
* The remaining emulated instructions are R-type and have an OP field
* of 0x3a. Their OPX fields identify them.
*
* R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a-
* 27 22 17 11 6 0 <-- LSB of field
*
*
*/
/*
* Split the instruction into its fields. We need 4*A, 4*B, and 4*C as
* offsets to the stack pointer for access to the stored register values.
*/
/* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */
roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */
roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */
roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */
srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */
xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */
roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */
andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */
xori r3, r3, 0x40
andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */
andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */
andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */
/* Now either
* r5 = OP
* r3 = 4*(A^16)
* r4 = IMM16 (sign extended)
* r6 = 4*(B^16)
* r7 = 4*(C^16)
* or
* r5 = OP
*/
/*
* Save everything on the stack to make it easy for the emulation routines
* to retrieve the source register operands. The exception entry code has
* already saved some of this so we don't need to do it all again.
*/
addi sp, sp, -60
stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */
/* Register at and r2-r15 have already been saved. */
stw r16, 0(sp)
stw r17, 4(sp)
stw r18, 8(sp)
stw r19, 12(sp)
stw r20, 16(sp)
stw r21, 20(sp)
stw r22, 24(sp)
stw r23, 28(sp)
/* et @ 32 - Has already been changed.*/
/* bt @ 36 - Usually isn't an operand. */
stw gp, 40(sp)
stw sp, 44(sp)
stw fp, 48(sp)
/* ea @ 52 - Don't bother to save - it's already been changed */
/* ba @ 56 - Breakpoint register usually isn't an operand */
/* ra @ 60 - Has already been saved */
/*
* Prepare for either multiplication or division loop.
* They both loop 32 times.
*/
movi r14, 32
/*
* Get the operands.
*
* It is necessary to check for muli because it uses an I-type instruction
* format, while the other instructions are have an R-type format.
*/
add r3, r3, sp /* r3 = address of A-operand. */
ldw r3, 0(r3) /* r3 = A-operand. */
movi r15, 0x24 /* muli opcode (I-type instruction format) */
beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */
add r6, r6, sp /* r6 = address of B-operand. */
ldw r6, 0(r6) /* r6 = B-operand. */
/* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */
/* IMM16 not needed, align OPX portion */
/* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */
/* Now
* r5 = OP
* r3 = src1
* r6 = src2
* r4 = OPX (no longer can be muli)
* r7 = 4*(C^16)
* r14 = loop counter
*/
/* ILLEGAL-INSTRUCTION EXCEPTION
* -----------------------------
*
* This code is for Nios II cores that generate exceptions when attempting
* to execute illegal instructions. Nios II cores that support an
* illegal-instruction exception are identified by the presence of the
* macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h .
*
* Remember that illegal instructions are different than unimplemented
* instructions. Illegal instructions are instruction encodings that
* have not been defined by the Nios II ISA. Unimplemented instructions
* are legal instructions that must be emulated by some Nios II cores.
*
* If we get here, all instructions except multiplies and divides
* are illegal.
*
* This code assumes that OP is not muli (because muli was tested above).
* All other multiplies and divides are legal. Anything else is illegal.
*/
movi r8, 0x3a /* OP for R-type mul* and div* */
bne r5, r8, .Lnot_muldiv
/* r15 already is 0x24 */ /* OPX of divu */
beq r4, r15, .Ldivide
movi r15,0x27 /* OPX of mul */
beq r4, r15, .Lmultiply
movi r15,0x07 /* OPX of mulxuu */
beq r4, r15, .Lmultiply
movi r15,0x17 /* OPX of mulxsu */
beq r4, r15, .Lmultiply
movi r15,0x1f /* OPX of mulxss */
beq r4, r15, .Lmultiply
movi r15,0x25 /* OPX of div */
bne r4, r15, .Lnot_muldiv
/* DIVISION
*
* Divide an unsigned dividend by an unsigned divisor using
* a shift-and-subtract algorithm. The example below shows
* 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a
* single register to store both the dividend and the quotient,
* allowing both values to be shifted with a single instruction.
*
* remainder dividend:quotient
* --------- -----------------
* initialize 00000000 00101011:
* shift 00000000 0101011:_
* remainder >= divisor? no 00000000 0101011:0
* shift 00000000 101011:0_
* remainder >= divisor? no 00000000 101011:00
* shift 00000001 01011:00_
* remainder >= divisor? no 00000001 01011:000
* shift 00000010 1011:000_
* remainder >= divisor? no 00000010 1011:0000
* shift 00000101 011:0000_
* remainder >= divisor? no 00000101 011:00000
* shift 00001010 11:00000_
* remainder >= divisor? yes 00001010 11:000001
* remainder -= divisor - 00000111
* ----------
* 00000011 11:000001
* shift 00000111 1:000001_
* remainder >= divisor? yes 00000111 1:0000011
* remainder -= divisor - 00000111
* ----------
* 00000000 1:0000011
* shift 00000001 :0000011_
* remainder >= divisor? no 00000001 :00000110
*
* The quotient is 00000110.
*/
.Ldivide:
/*
* Prepare for division by assuming the result
* is unsigned, and storing its "sign" as 0.
*/
movi r17, 0
/* Which division opcode? */
xori r15, r4, 0x25 /* OPX of div */
bne r15, zero, .Lunsigned_division
/*
* OPX is div. Determine and store the sign of the quotient.
* Then take the absolute value of both operands.
*/
xor r17, r3, r6 /* MSB contains sign of quotient */
bge r3, zero, 0f
sub r3, zero, r3 /* -r3 */
0:
bge r6, zero, 0f
sub r6, zero, r6 /* -r6 */
0:
.Lunsigned_division:
/* Initialize the unsigned-division loop. */
movi r13, 0 /* remainder = 0 */
/* Now
* r3 = dividend : quotient
* r4 = 0x25 for div, 0x24 for divu
* r6 = divisor
* r13 = remainder
* r14 = loop counter (already initialized to 32)
* r17 = MSB contains sign of quotient
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Ldivide_loop:
/*
* Division:
*
* (remainder:dividend:quotient) <<= 1;
*/
slli r13, r13, 1
cmplt r15, r3, zero /* r15 = MSB of r3 */
or r13, r13, r15
slli r3, r3, 1
/*
* if (remainder >= divisor)
* {
* set LSB of quotient
* remainder -= divisor;
* }
*/
bltu r13, r6, .Ldiv_skip
ori r3, r3, 1
sub r13, r13, r6
.Ldiv_skip:
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Ldivide_loop
mov r9, r3
/* Now
* r9 = quotient
* r4 = 0x25 for div, 0x24 for divu
* r7 = 4*(C^16)
* r17 = MSB contains sign of quotient
*/
/*
* Conditionally negate signed quotient. If quotient is unsigned,
* the sign already is initialized to 0.
*/
bge r17, zero, .Lstore_result
sub r9, zero, r9 /* -r9 */
br .Lstore_result
/* MULTIPLICATION
*
* A "product" is the number that one gets by summing a "multiplicand"
* several times. The "multiplier" specifies the number of copies of the
* multiplicand that are summed.
*
* Actual multiplication algorithms don't use repeated addition, however.
* Shift-and-add algorithms get the same answer as repeated addition, and
* they are faster. To compute the lower half of a product (pppp below)
* one shifts the product left before adding in each of the partial products
* (a * mmmm) through (d * mmmm).
*
* To compute the upper half of a product (PPPP below), one adds in the
* partial products (d * mmmm) through (a * mmmm), each time following the
* add by a right shift of the product.
*
* mmmm
* * abcd
* ------
* #### = d * mmmm
* #### = c * mmmm
* #### = b * mmmm
* #### = a * mmmm
* --------
* PPPPpppp
*
* The example above shows 4 partial products. Computing actual Nios II
* products requires 32 partials.
*
* It is possible to compute the result of mulxsu from the result of mulxuu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rA.
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*
* It is possible to compute the result of mulxss from the result of mulxsu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rB.
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*
*/
.Lmul_immed:
/* Opcode is muli. Change it into mul for remainder of algorithm. */
mov r7, r6 /* Field B is dest register, not field C. */
mov r6, r4 /* Field IMM16 is src2, not field B. */
movi r4, 0x27 /* OPX of mul is 0x27 */
.Lmultiply:
/* Initialize the multiplication loop. */
movi r9, 0 /* mul_product = 0 */
movi r10, 0 /* mulxuu_product = 0 */
mov r11, r6 /* save original multiplier for mulxsu and mulxss */
mov r12, r6 /* mulxuu_multiplier (will be shifted) */
movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */
/* Now
* r3 = multiplicand
* r6 = mul_multiplier
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r12 = mulxuu_multiplier
* r14 = loop counter (already initialized)
* r15 = temp
* r16 = 1
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Lmultiply_loop:
/*
* mul_product <<= 1;
* lsb = multiplier & 1;
*/
slli r9, r9, 1
andi r15, r12, 1
/*
* if (lsb == 1)
* {
* mulxuu_product += multiplicand;
* }
*/
beq r15, zero, .Lmulx_skip
add r10, r10, r3
cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */
ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */
.Lmulx_skip:
/*
* if (MSB of mul_multiplier == 1)
* {
* mul_product += multiplicand;
* }
*/
bge r6, zero, .Lmul_skip
add r9, r9, r3
.Lmul_skip:
/*
* mulxuu_product >>= 1; logical shift
* mul_multiplier <<= 1; done with MSB
* mulx_multiplier >>= 1; done with LSB
*/
srli r10, r10, 1
or r10, r10, r15 /* OR in the saved carry bit. */
slli r6, r6, 1
srli r12, r12, 1
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Lmultiply_loop
/*
* Multiply emulation loop done.
*/
/* Now
* r3 = multiplicand
* r4 = OPX
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r15 = temp
*/
/*
* Select/compute the result based on OPX.
*/
/* OPX == mul? Then store. */
xori r15, r4, 0x27
beq r15, zero, .Lstore_result
/* It's one of the mulx.. opcodes. Move over the result. */
mov r9, r10
/* OPX == mulxuu? Then store. */
xori r15, r4, 0x07
beq r15, zero, .Lstore_result
/* Compute mulxsu
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*/
bge r3, zero, .Lmulxsu_skip
sub r9, r9, r11
.Lmulxsu_skip:
/* OPX == mulxsu? Then store. */
xori r15, r4, 0x17
beq r15, zero, .Lstore_result
/* Compute mulxss
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*/
bge r11, zero, .Lmulxss_skip
sub r9, r9, r3
.Lmulxss_skip:
/* At this point, assume that OPX is mulxss, so store */
.Lstore_result:
add r7, r7, sp
stw r9, 0(r7)
ldw r16, 0(sp)
ldw r17, 4(sp)
ldw r18, 8(sp)
ldw r19, 12(sp)
ldw r20, 16(sp)
ldw r21, 20(sp)
ldw r22, 24(sp)
ldw r23, 28(sp)
/* bt @ 32 - Breakpoint register usually isn't an operand. */
/* et @ 36 - Don't corrupt et. */
/* gp @ 40 - Don't corrupt gp. */
/* sp @ 44 - Don't corrupt sp. */
ldw fp, 48(sp)
/* ea @ 52 - Don't corrupt ea. */
/* ba @ 56 - Breakpoint register usually isn't an operand. */
addi sp, sp, 60
br .Lexception_exit
.Lnot_muldiv:
addi sp, sp, 60
.section .exceptions.exit.label
.Lexception_exit:
|
agural/FPGA-Oscilloscope
| 2,989
|
osc/Copy of software/osc_bsp/HAL/src/alt_software_exception.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This file provides the global symbol: software_exception. It is provided to
* support legacy code, and should not be used by new software.
*
* It is used by legacy code to invoke the software exception handler as
* defined by version 1.0 of the Nios II kit. It should only be used when you
* are providing your own interrupt entry point, i.e. you are not using
* alt_irq_entry.
*/
#include "system.h"
/*
* Pull in the exception handler.
*/
.globl alt_exception
.section .exceptions.entry.label, "xa"
.globl software_exception
.type software_exception, @function
software_exception:
|
agural/FPGA-Oscilloscope
| 16,254
|
osc/Copy of software/osc_bsp/HAL/src/crt0.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
#include "nios2.h"
/* Setup header files to work with assembler code. */
#define ALT_ASM_SRC
/* Debug logging facility */
#include "sys/alt_log_printf.h"
/*************************************************************************\
| MACROS |
\*************************************************************************/
/*
* The new build tools explicitly define macros when alt_load()
* must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that
* those macros are controlling if alt_load() needs to be called.
*/
#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED
/* Need to call alt_load() if any of these sections are being copied. */
#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS)
#define CALL_ALT_LOAD
#endif
#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* The legacy build tools use the following macros to detect when alt_load()
* needs to be called.
*/
#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \
((res##_BASE != rodata##_BASE) || \
(res##_BASE != rwdata##_BASE) || \
(res##_BASE != exc##_BASE))
#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \
__ALT_LOAD_SECTIONS(res, text, rodata, exc)
#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \
ALT_RODATA_DEVICE, \
ALT_RWDATA_DEVICE, \
ALT_EXCEPTIONS_DEVICE)
/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */
#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS
#define CALL_ALT_LOAD
#endif
#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* When the legacy build tools define a macro called ALT_NO_BOOTLOADER,
* it indicates that initialization code is allowed at the reset address.
* The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for
* the same purpose.
*/
#ifdef ALT_NO_BOOTLOADER
#define ALT_ALLOW_CODE_AT_RESET
#endif
/*************************************************************************\
| EXTERNAL REFERENCES |
\*************************************************************************/
/*
* The entry point for user code is either "main" in hosted mode, or
* "alt_main" in standalone mode. These are explicitly referenced here,
* to ensure they are built into the executable. This allows the user
* to build them into libraries, rather than supplying them in object
* files at link time.
*/
.globl main
.globl alt_main
/*
* Create a reference to the software multiply/divide and trap handers,
* so that if they are provided, they will appear in the executable.
*/
#ifndef ALT_NO_INSTRUCTION_EMULATION
.globl alt_exception_muldiv
#endif
#ifdef ALT_TRAP_HANDLER
.globl alt_exception_trap
#endif
/*
* Linker defined symbols used to initialize bss.
*/
.globl __bss_start
.globl __bss_end
/*************************************************************************\
| RESET SECTION (.entry) |
\*************************************************************************/
/*
* This is the reset entry point for Nios II.
*
* At reset, only the cache line which contain the reset vector is
* initialized by the hardware. The code within the first cache line
* initializes the remainder of the instruction cache.
*/
.section .entry, "xa"
.align 5
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* Some tools want to know where the reset vector is.
* Code isn't always provided at the reset vector but at least the
* __reset label always contains the reset vector address because
* it is defined at the start of the .entry section.
*/
.globl __reset
.type __reset, @function
__reset:
/*
* Initialize the instruction cache if present (i.e. size > 0) and
* reset code is allowed unless optimizing for RTL simulation.
* RTL simulations can ensure the instruction cache is already initialized
* so skipping this loop speeds up RTL simulation.
*/
#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE)
/* Assume the instruction cache size is always a power of two. */
#if NIOS2_ICACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_ICACHE_SIZE)
#else
movui r2, NIOS2_ICACHE_SIZE
#endif
0:
initi r2
addi r2, r2, -NIOS2_ICACHE_LINE_SIZE
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 1, 1, 0b, 1b
.popsection
#endif /* Initialize Instruction Cache */
/*
* Jump to the _start entry point in the .text section if reset code
* is allowed or if optimizing for RTL simulation.
*/
#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
/* Jump to the _start entry point in the .text section. */
movhi r1, %hi(_start)
ori r1, r1, %lo(_start)
jmp r1
.size __reset, . - __reset
#endif /* Jump to _start */
/*
* When not using exit, provide an _exit symbol to prevent unresolved
* references to _exit from the linker script.
*/
#ifdef ALT_NO_EXIT
.globl _exit
_exit:
#endif
/*************************************************************************\
| TEXT SECTION (.text) |
\*************************************************************************/
/*
* Start of the .text section, and also the code entry point when
* the code is executed by a bootloader rather than directly from reset.
*/
.section .text
.align 2
.globl _start
.type _start, @function
_start:
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Ensure that the current register set is 0 upon
* entry to this code. Switch register set to 0 by
* writing zero to SSTATUS register and executing an ERET instruction
* to set STATUS.CRS to 0.
*/
/* Get the current register set number (STATUS.CRS). */
rdctl r2, status
andi r2, r2, NIOS2_STATUS_CRS_MSK
/* Skip switching register set if STATUS.CRS is 0. */
beq r2, zero, 0f
/* Set SSTATUS to 0 to get to set SSTATUS.PRS to 0. */
.set nobreak
movui sstatus, 0
.set break
/* Switch to register set 0 and jump to label. */
movhi ea, %hi(0f)
ori ea, ea, %lo(0f)
eret
0:
#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */
/*
* Initialize the data cache if present (i.e. size > 0).
* Skip initialization if optimizing for RTL simulation and ECC isn't present.
* RTL simulations can ensure the data cache tag RAM is already initialized
* (but not the data RAM for ECC) so skipping this speeds up RTL simulation.
*
* When ECC is present, need to execute initd for each word address
* to ensure ECC parity bits in data RAM get initialized.
* Otherwise, only need to execute initd for each line address.
*/
#if NIOS2_DCACHE_SIZE > 0 && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
/* Assume the data cache size is always a power of two. */
#if NIOS2_DCACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_DCACHE_SIZE)
#else
movui r2, NIOS2_DCACHE_SIZE
#endif
0:
initd 0(r2)
#ifdef NIOS2_ECC_PRESENT
addi r2, r2, -4
#else
addi r2, r2, -NIOS2_DCACHE_LINE_SIZE
#endif
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 2, 1, 0b, 1b
.popsection
#endif /* Initialize Data Cache */
/* Log that caches have been initialized. */
ALT_LOG_PUTS(alt_log_msg_cache)
/* Log that the stack pointer is about to be setup. */
ALT_LOG_PUTS(alt_log_msg_stackpointer)
/*
* Now that the caches are initialized, set up the stack pointer and global pointer.
* The values provided by the linker are assumed to be correctly aligned.
*/
movhi sp, %hi(__alt_stack_pointer)
ori sp, sp, %lo(__alt_stack_pointer)
movhi gp, %hi(_gp)
ori gp, gp, %lo(_gp)
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
movui r1, 0
movui r2, 0
movui r3, 0
movui r4, 0
movui r5, 0
movui r6, 0
movui r7, 0
movui r8, 0
movui r9, 0
movui r10, 0
movui r11, 0
movui r12, 0
movui r13, 0
movui r14, 0
movui r15, 0
movui r16, 0
movui r17, 0
movui r18, 0
movui r19, 0
movui r20, 0
movui r21, 0
movui r22, 0
movui r23, 0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it is already been initialized. */
movui r28, 0 /* fp */
movui r29, 0 /* ea */
.set nobreak
movui r30, 0 /* sstatus */
.set break
movui r31, 0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Setup registers in shadow register sets
* from 1 to NIOS2_NUM_OF_SHADOW_REG_SETS.
*/
movui r2, 0 /* Contains value written into STATUS */
movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS /* counter */
movhi r4, 1 /* Constant to increment STATUS.PRS */
.Linitialize_shadow_registers:
/* Increment STATUS.PRS */
add r2, r2, r4
wrctl status, r2
/* Clear r0 in the shadow register set (not done by hardware) */
wrprs r0, r0
/* Write the GP in previous register set */
wrprs gp, gp
/*
* Only write the SP in previous register set
* if using the separate exception stack. For normal case (single stack),
* funnel code would read the SP from previous register set with a RDPRS.
*/
#ifdef ALT_INTERRUPT_STACK
movhi et, %hiadj(__alt_interrupt_stack_pointer)
addi et, et, %lo(__alt_interrupt_stack_pointer)
wrprs sp, et
#endif /* ALT_INTERRUPT_STACK */
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
wrprs r1, r0
wrprs r2, r0
wrprs r3, r0
wrprs r4, r0
wrprs r5, r0
wrprs r6, r0
wrprs r7, r0
wrprs r8, r0
wrprs r9, r0
wrprs r10, r0
wrprs r11, r0
wrprs r12, r0
wrprs r13, r0
wrprs r14, r0
wrprs r15, r0
wrprs r16, r0
wrprs r17, r0
wrprs r18, r0
wrprs r19, r0
wrprs r20, r0
wrprs r21, r0
wrprs r22, r0
wrprs r23, r0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it was initialized above or will be by a rdprs if not above */
wrprs r28, r0 /* fp */
wrprs r29, r0 /* ea */
wrprs r30, r0 /* ba */
wrprs r31, r0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
/* Decrement shadow register set counter */
addi r3, r3, -1
/* Done if index is 0. */
bne r3, zero, .Linitialize_shadow_registers
#endif /* (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) */
/*
* Clear the BSS if not optimizing for RTL simulation.
*
* This uses the symbols: __bss_start and __bss_end, which are defined
* by the linker script. They mark the begining and the end of the bss
* region. The linker script guarantees that these values are word aligned.
*/
#ifndef ALT_SIM_OPTIMIZE
/* Log that the BSS is about to be cleared. */
ALT_LOG_PUTS(alt_log_msg_bss)
movhi r2, %hi(__bss_start)
ori r2, r2, %lo(__bss_start)
movhi r3, %hi(__bss_end)
ori r3, r3, %lo(__bss_end)
beq r2, r3, 1f
0:
stw zero, (r2)
addi r2, r2, 4
bltu r2, r3, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 3, 1, 0b, 1b
.popsection
#endif /* ALT_SIM_OPTIMIZE */
/*
* The alt_load() facility is normally used when there is no bootloader.
* It copies some sections into RAM so it acts like a mini-bootloader.
*/
#ifdef CALL_ALT_LOAD
#ifdef ALT_STACK_CHECK
/*
* If the user has selected stack checking then we need to set up a safe
* value in the stack limit register so that the relocation functions
* don't think the stack has overflowed (the contents of the rwdata
* section aren't defined until alt_load() has been called).
*/
mov et, zero
#endif
call alt_load
#endif /* CALL_ALT_LOAD */
#ifdef ALT_STACK_CHECK
/*
* Set up the stack limit (if required). The linker has set up the
* copy of the variable which is in memory.
*/
ldw et, %gprel(alt_stack_limit_value)(gp)
#endif
/* Log that alt_main is about to be called. */
ALT_LOG_PUTS(alt_log_msg_alt_main)
/* Call the C entry point. It should never return. */
call alt_main
/* Wait in infinite loop in case alt_main does return. */
alt_after_alt_main:
br alt_after_alt_main
.size _start, . - _start
/*
* Add information about the stack base if stack overflow checking is enabled.
*/
#ifdef ALT_STACK_CHECK
.globl alt_stack_limit_value
.section .sdata,"aws",@progbits
.align 2
.type alt_stack_limit_value, @object
.size alt_stack_limit_value, 4
alt_stack_limit_value:
.long __alt_stack_limit
#endif
|
agural/FPGA-Oscilloscope
| 8,293
|
osc/Copy of software/osc_bsp/HAL/src/alt_mcount.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/* mcount or _mcount is inserted by GCC before the function prologue of every
* function when a program is compiled for profiling. At the start of mcount,
* we guarantee that:
* ra = self_pc (an address in the function which called mcount)
* r8 = from_pc (an address in the function which called mcount's caller)
*
* Because this is always called at the start of a function we can corrupt
* r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain
* function arguments for the instrumented function) or r8 (which holds ra
* for the instrumented function).
*/
.global __mcount_fn_head
.global mcount
/* _mcount is used by gcc4 */
.global _mcount
_mcount:
mcount:
/* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose
* the bucket because bits 1:0 will always be 0, and because the distribution
* of values for bits 4:2 won't be even (aligning on cache line boundaries
* will skew it). Higher bits should be fairly random.
*/
/* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */
srli r2, ra, 3
movhi r3, %hiadj(__mcount_fn_head)
addi r3, r3, %lo(__mcount_fn_head)
andi r2, r2, 0xFC
add r11, r2, r3
/* The fast case is where we have already allocated a function arc, and so
* also a function pointer.
*/
/* First find the function being called (using self_pc) */
mov r10, r11
0:
ldw r10, 0(r10)
beq r10, zero, .Lnew_arc
ldw r2, 4(r10)
bne r2, ra, 0b
/* Found a function entry for this PC. Now look for an arc with a matching
* from_pc value. There will always be at least one arc. */
ldw r3, 8(r10)
0:
ldw r2, 4(r3)
beq r2, r8, .Lfound_arc
ldw r3, 0(r3)
bne r3, zero, 0b
.Lnew_arc:
addi sp, sp, -24
.LCFI0:
stw ra, 0(sp)
stw r4, 4(sp)
stw r5, 8(sp)
stw r6, 12(sp)
stw r7, 16(sp)
stw r8, 20(sp)
.LCFI1:
/* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */
mov r4, ra
mov r5, r8
mov r6, r10
mov r7, r11
call __mcount_record
/* restore registers from the stack */
ldw ra, 0(sp)
ldw r4, 4(sp)
ldw r5, 8(sp)
ldw r6, 12(sp)
ldw r7, 16(sp)
ldw r8, 20(sp)
addi sp, sp, 24
.LCFI2:
ret
.Lfound_arc:
/* We've found the correct arc record. Increment the count and return */
ldw r2, 8(r3)
addi r2, r2, 1
stw r2, 8(r3)
ret
.Lmcount_end:
/*
* Dwarf2 debug information for the function. This provides GDB with the
* information it needs to backtrace out of this function.
*/
.section .debug_frame,"",@progbits
.LCIE:
.4byte 2f - 1f /* Length */
1:
.4byte 0xffffffff /* CIE id */
.byte 0x1 /* Version */
.string "" /* Augmentation */
.uleb128 0x1 /* Code alignment factor */
.sleb128 -4 /* Data alignment factor */
.byte 0x1f /* Return address register */
.byte 0xc /* Define CFA */
.uleb128 0x1b /* Register 27 (sp) */
.uleb128 0x0 /* Offset 0 */
.align 2 /* Padding */
2:
.LFDE_mcount:
.4byte 2f - 1f /* Length */
1:
.4byte .LCIE /* Pointer to CIE */
.4byte mcount /* Start of table entry */
.4byte .Lmcount_end - mcount /* Size of table entry */
.byte 0x4 /* Advance location */
.4byte .LCFI0 - mcount /* to .LCFI0 */
.byte 0xe /* Define CFA offset */
.uleb128 24 /* to 24 */
.byte 0x4 /* Advance location */
.4byte .LCFI1 - .LCFI0 /* to .LCFI1 */
.byte 0x9f /* Store ra */
.uleb128 0x6 /* at CFA-24 */
.byte 0x84 /* Store r4 */
.uleb128 0x5 /* at CFA-20 */
.byte 0x85 /* Store r5 */
.uleb128 0x4 /* at CFA-16 */
.byte 0x86 /* Store r6 */
.uleb128 0x3 /* at CFA-12 */
.byte 0x87 /* Store r7 */
.uleb128 0x2 /* at CFA-8 */
.byte 0x88 /* Store r8 */
.uleb128 0x1 /* at CFA-4 */
.byte 0x4 /* Advance location */
.4byte .LCFI2 - .LCFI1 /* to .LCFI2 */
.byte 0xe /* Define CFA offset */
.uleb128 0 /* to 0 */
.byte 0x8 /* Same value */
.uleb128 31 /* for ra */
.byte 0x8 /* Same value */
.uleb128 4 /* for r4 */
.byte 0x8 /* Same value */
.uleb128 5 /* for r5 */
.byte 0x8 /* Same value */
.uleb128 6 /* for r6 */
.byte 0x8 /* Same value */
.uleb128 7 /* for r7 */
.byte 0x8 /* Same value */
.uleb128 8 /* for r8 */
.align 2
2:
|
agural/FPGA-Oscilloscope
| 5,245
|
osc/Copy of software/osc_bsp/HAL/src/alt_ecc_fatal_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the code called at the beginning of the exception handler
* to detect a likely fatal ECC error exception and then jump to
* user-provided code to handle it.
*
* This code is pulled in from a .globl in alt_ecc_fatal_exception.c.
* This scheme is used so that if a handler is never registered, then this
* code will not appear in the generated executable, thereby improving
* code footprint.
*
* This code is located in its own section that the linker script
* explicitly mentions and ensures it gets linked at the beginning
* of the exception handler.
*/
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.section .exceptions.entry.ecc_fatal, "xa"
/*
* This might be handling an unrecoverable ECC error exception
* in the register file and/or data cache.
* Must avoid reading registers or performing load/store instructions
* before this is determined because they could trigger another
* unrecoverable ECC error exception and create an infinite loop.
*
* The EXCEPTION register is always present when ECC is present.
* Bit 31 of this register indicates that there was an unrecoverable
* ECC error exception in the register file and/or data cache.
* Test this (using blt to check sign bit) to determine if this is
* what we are dealing with. Otherwise, just do normal processing.
*
* Jump to an application-provided routine to handle this condition.
* Pass in the return address in the et register in case this code
* can clean up the ECC error and then return here (unlikely).
*
* Runtime stack checking can't be enabled when ECC is present
* because they both want to use the et register.
*/
rdctl et, exception
bge et, r0, alt_exception_not_ecc_fatal /* Not ECCFTL if bit 31 is 0 */
/*
* Load ECC fatal handler pointer into et register.
* Using a ldwio is safe because it completely bypasses the data cache.
*/
movhi et, %hi(alt_exception_ecc_fatal_handler)
ori et, et, %lo(alt_exception_ecc_fatal_handler)
ldwio et, 0(et)
/*
* If ECC fatal handler pointer is not 0, assume a handler
* has been provided by the application.
*/
beq et, r0, alt_exception_not_ecc_fatal
/*
* The et register contains the address of the ECC fatal handler.
* Jump to this address to invoke the handler.
*/
jmp et
/*
* An ECC fatal handler can jump to this label if it able
* to recover from the fatal error (rare) and wants to continue
* with normal exception processing.
*/
.globl alt_exception_not_ecc_fatal
alt_exception_not_ecc_fatal:
|
agural/FPGA-Oscilloscope
| 3,594
|
FPGA/Test/software/code_bsp/HAL/src/alt_exception_trap.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the trap exception handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_trap
alt_exception_trap:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
.Ltrap_handler:
/*
* Did a trap instruction cause the exception?
*
* The instruction which the exception occurred on has been loaded
* into r2 by code in alt_exception_entry.S
*
*/
movhi r3,0x003b /* upper half of trap opcode */
ori r3,r3,0x683a /* lower half of trap opcode */
bne r2,r3,.Lnot_trap
/*
* There is no trap handler defined here, and so executing a trap
* instruction causes a software break. If you provide a trap handler,
* then you must replace the break instruction below with your handler.
* Your handler must preserve ea and the usual callee saved registers.
*/
break
br .Lexception_exit
.Lnot_trap:
.section .exceptions.exit.label
.Lexception_exit:
|
agural/FPGA-Oscilloscope
| 4,685
|
FPGA/Test/software/code_bsp/HAL/src/alt_irq_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the interrupt exception entry point code, which saves all the
* registers and calls the interrupt handler. It should be pulled in using
* a .globl from alt_irq_register.c. This scheme is used so that if an
* interrupt is never registered, then this code will not appear in the
* generated executable, thereby improving code footprint.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the compiler.
*/
.set noat
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.globl alt_irq_entry
.section .exceptions.entry.label, "xa"
alt_irq_entry:
/*
* Section .exceptions.entry is in alt_exception_entry.S
* This saves all the caller saved registers and reads estatus into r5
*/
.section .exceptions.irqtest, "xa"
#ifdef ALT_CI_INTERRUPT_VECTOR_N
/*
* Use the interrupt vector custom instruction if present to accelerate
* this code.
* If the interrupt vector custom instruction returns a negative
* value, there are no interrupts active (estatus.pie is 0
* or ipending is 0) so assume it is a software exception.
*/
custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0
blt r4, r0, .Lnot_irq
#else
/*
* Test to see if the exception was a software exception or caused
* by an external interrupt, and vector accordingly.
*/
rdctl r4, ipending
andi r2, r5, 1
beq r2, zero, .Lnot_irq
beq r4, zero, .Lnot_irq
#endif /* ALT_CI_INTERRUPT_VECTOR_N */
.section .exceptions.irqhandler, "xa"
/*
* Now that all necessary registers have been preserved, call
* alt_irq_handler() to process the interrupts.
*/
call alt_irq_handler
.section .exceptions.irqreturn, "xa"
br .Lexception_exit
.section .exceptions.notirq.label, "xa"
.Lnot_irq:
/*
* Section .exceptions.exit is in alt_exception_entry.S
* This restores all the caller saved registers
*/
.section .exceptions.exit.label
.Lexception_exit:
|
agural/FPGA-Oscilloscope
| 1,742
|
FPGA/Test/software/code_bsp/HAL/src/alt_log_macro.S
|
/* alt_log_macro.S
*
* Implements the function tx_log_str, called by the assembly macro
* ALT_LOG_PUTS(). The macro will be empty when logging is turned off,
* and this function will not be compiled. When logging is on,
* this function is used to print out the strings defined in the beginning
* of alt_log_printf.c, using port information taken from system.h and
* alt_log_printf.h.
*
* This routine only handles strings, and sends a character into the defined
* output device's output buffer when the device is ready. It's intended for
* debugging purposes, where messages can be set to print out at certain
* points in the boot code to indicate the progress of the program.
*
*/
#ifndef __ALT_LOG_MACROS__
#define __ALT_LOG_MACROS__
/* define this flag to skip assembly-incompatible parts
* of various include files. */
#define ALT_ASM_SRC
#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined.
#include "system.h"
#include "sys/alt_log_printf.h"
.global tx_log_str
tx_log_str:
/* load base uart / jtag uart address into r6 */
movhi r6, %hiadj(ALT_LOG_PORT_BASE)
addi r6, r6, %lo(ALT_LOG_PORT_BASE)
tx_next_char:
/* if pointer points to null, return
* r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */
ldb r7, (r4)
beq r0, r7, end_tx
/* check device transmit ready */
wait_tx_ready_loop:
ldwio r5, ALT_LOG_PRINT_REG_OFFSET(r6)
andi r5, r5, ALT_LOG_PRINT_MSK
beq r5, r0, wait_tx_ready_loop
/* write char */
stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6)
/* advance string pointer */
addi r4, r4, 1
br tx_next_char
end_tx:
ret
#endif
#endif /* __ALT_LOG_MACROS__ */
|
agural/FPGA-Oscilloscope
| 14,886
|
FPGA/Test/software/code_bsp/HAL/src/alt_exception_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the exception entry point code, which saves all the caller saved
* registers and then handles the appropriate exception. It should be pulled
* in using a .globl from all the exception handler routines. This scheme is
* used so that if an interrupt is never registered, then this code will not
* appear in the generated executable, thereby improving code footprint.
*
* If an external interrpt controller (EIC) is present, it will supply an
* interrupt vector address to the processor when an interrupt occurs. For
* The Altera Vectored Interrupt Controller (VIC) driver will establish a
* vector table and the processor will jump directly to the appropriate
* table entry, funnel routine, and then user ISR. This will bypass this code
* in entirety. This code might still be linked into a system with an EIC,
* but would then be used only for non-interrupt exceptions.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* The top and bottom of the exception stack.
*/
#ifdef ALT_EXCEPTION_STACK
.globl __alt_exception_stack_pointer
#ifdef ALT_STACK_CHECK
.globl __alt_exception_stack_limit
/*
* Store the value of the stack limit after interrupt somewhere.
*/
.globl alt_exception_old_stack_limit
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* The code at alt_exception is located at the Nios II exception
* handler address.
*/
.section .exceptions.entry.label, "xa"
.globl alt_exception
.type alt_exception, @function
alt_exception:
/*
* The code for detecting a likely fatal ECC exception is
* linked here before the normal exception handler code if required.
* This is handled by the linker script and putting that code
* in the .exceptions.entry.ecc_fatal section.
*/
/*
* Now start the normal exception handler code.
*/
.section .exceptions.entry, "xa"
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
/*
* When runtime stack checking is enabled, the et register
* contains the stack limit. Save this in memory before
* overwriting the et register.
*/
stw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
/*
* Switch to the exception stack and save the current stack pointer
* in memory. Uses the et register as a scratch register.
*/
movhi et, %hi(__alt_exception_stack_pointer - 80)
ori et, et, %lo(__alt_exception_stack_pointer - 80)
stw sp, 76(et)
mov sp, et
#ifdef ALT_STACK_CHECK
/*
* Restore the stack limit from memory to the et register.
*/
movhi et, %hi(__alt_exception_stack_limit)
ori et, et, %lo(__alt_exception_stack_limit)
stw et, %gprel(alt_stack_limit_value)(gp)
#endif /* ALT_STACK_CHECK */
#else /* ALT_EXCEPTION_STACK disabled */
/*
* Reserve space on normal stack for registers about to be pushed.
*/
addi sp, sp, -76
#ifdef ALT_STACK_CHECK
/* Ensure stack didn't just overflow. */
bltu sp, et, .Lstack_overflow
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* Process an exception. For all exceptions we must preserve all
* caller saved registers on the stack (See the Nios II ABI
* documentation for details).
*
* Leave a gap in the stack frame at 4(sp) for the muldiv handler to
* store zero into.
*/
stw ra, 0(sp)
stw r1, 8(sp)
stw r2, 12(sp)
stw r3, 16(sp)
stw r4, 20(sp)
stw r5, 24(sp)
stw r6, 28(sp)
stw r7, 32(sp)
rdctl r5, estatus /* Read early to avoid usage stall */
stw r8, 36(sp)
stw r9, 40(sp)
stw r10, 44(sp)
stw r11, 48(sp)
stw r12, 52(sp)
stw r13, 56(sp)
stw r14, 60(sp)
stw r15, 64(sp)
/*
* ea-4 contains the address of the instruction being executed
* when the exception occured. For interrupt exceptions, we will
* will be re-issue the isntruction. Store it in 72(sp)
*/
stw r5, 68(sp) /* estatus */
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
/*
* The interrupt testing code (.exceptions.irqtest) will be
* linked here. If the Internal Interrupt Controller (IIC) is
* present (an EIC is not present), the presense of an interrupt
* is determined by examining CPU control registers or an interrupt
* custom instruction, if present.
*
* If the IIC is used and an interrupt is active, the code linked
* here will call the HAL IRQ handler (alt_irq_handler()) which
* successively calls registered interrupt handler(s) until no
* interrupts remain pending. It then jumps to .exceptions.exit. If
* there is no interrupt then it continues to .exception.notirq, below.
*/
.section .exceptions.notirq, "xa"
/*
* Prepare to service unimplemtned instructions or traps,
* each of which is optionally inked into section .exceptions.soft,
* which will preceed .exceptions.unknown below.
*
* Unlike interrupts, we want to skip the exception-causing instructon
* upon completion, so we write ea (address of instruction *after*
* the one where the exception occured) into 72(sp). The actual
* instruction that caused the exception is written in r2, which these
* handlers will utilize.
*/
stw ea, 72(sp) /* Don't re-issue */
ldw r2, -4(ea) /* Instruction that caused exception */
/*
* Other exception handling code, if enabled, will be linked here.
* This includes unimplemted (multiply/divide) instruction support
* (a BSP generaton option), and a trap handler (that would typically
* be augmented with user-specific code). These are not linked in by
* default.
*/
/*
* In the context of linker sections, "unknown" are all exceptions
* not handled by the built-in handlers above (interupt, and trap or
* unimplemented instruction decoding, if enabled).
*
* Advanced exception types can be serviced by registering a handler.
* To do so, enable the "Enable Instruction-related Exception API" HAL
* BSP setting. If this setting is disabled, this handler code will
* either break (if the debug core is present) or enter an infinite
* loop because we don't how how to handle the exception.
*/
.section .exceptions.unknown
#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
/*
* The C-based HAL routine alt_instruction_exception_entry() will
* attempt to service the exception by calling a user-registered
* exception handler using alt_instruction_exception_register().
* If no handler was registered it will either break (if the
* debugger is present) or go into an infinite loop since the
* handling behavior is undefined; in that case we will not return here.
*/
/* Load exception-causing address as first argument (r4) */
addi r4, ea, -4
/* Call the instruction-exception entry */
call alt_instruction_exception_entry
/*
* If alt_instruction_exception_entry() returned, the exception was
* serviced by a user-registered routine. Its return code (now in r2)
* indicates whether to re-issue or skip the exception-causing
* instruction
*
* Return code was 0: Skip. The instruction after the exception is
* already stored in 72(sp).
*/
bne r2, r0, .Lexception_exit
/*
* Otherwise, modify 72(sp) to re-issue the instruction that caused the
* exception.
*/
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */
/*
* We got here because an instruction-related exception occured, but the
* handler API was not compiled in. We do not presume to know how to
* handle it. If the debugger is present, break, otherwise hang.
*
* If you get here then one of the following could have happened:
*
* - An instruction-generated exception occured, and the processor
* does not have the extra exceptions feature enabled, or you
* have not registered a handler using
* alt_instruction_exception_register()
*
* Some examples of instruction-generated exceptions and why they
* might occur:
*
* - Your program could have been compiled for a full-featured
* Nios II core, but it is running on a smaller core, and
* instruction emulation has been disabled by defining
* ALT_NO_INSTRUCTION_EMULATION.
*
* You can work around the problem by re-enabling instruction
* emulation, or you can figure out why your program is being
* compiled for a system other than the one that it is running on.
*
* - Your program has executed a trap instruction, but has not
* implemented a handler for this instruction.
*
* - Your program has executed an illegal instruction (one which is
* not defined in the instruction set).
*
* - Your processor includes an MMU or MPU, and you have enabled it
* before registering an exception handler to service exceptions it
* generates.
*
* The problem could also be hardware related:
* - If your hardware is broken and is generating spurious interrupts
* (a peripheral which negates its interrupt output before its
* interrupt handler has been executed will cause spurious
* interrupts)
*/
alt_exception_unknown:
#ifdef NIOS2_HAS_DEBUG_STUB
/*
* Either tell the user now (if there is a debugger attached) or go into
* the debug monitor which will loop until a debugger is attached.
*/
break
#else /* NIOS2_HAS_DEBUG_STUB disabled */
/*
* If there is no debug stub, an infinite loop is more useful.
*/
br alt_exception_unknown
#endif /* NIOS2_HAS_DEBUG_STUB */
#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
.section .exceptions.exit.label
.Lexception_exit:
.section .exceptions.exit, "xa"
/*
* Restore the saved registers, so that all general purpose registers
* have been restored to their state at the time the interrupt occured.
*/
ldw r5, 68(sp)
ldw ea, 72(sp) /* This becomes the PC once eret is executed */
ldw ra, 0(sp)
wrctl estatus, r5
ldw r1, 8(sp)
ldw r2, 12(sp)
ldw r3, 16(sp)
ldw r4, 20(sp)
ldw r5, 24(sp)
ldw r6, 28(sp)
ldw r7, 32(sp)
#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
ldw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif
ldw r8, 36(sp)
ldw r9, 40(sp)
ldw r10, 44(sp)
ldw r11, 48(sp)
ldw r12, 52(sp)
ldw r13, 56(sp)
ldw r14, 60(sp)
ldw r15, 64(sp)
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
stw et, %gprel(alt_stack_limit_value)(gp)
stw zero, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
ldw sp, 76(sp)
#else /* ALT_EXCEPTION_STACK disabled */
addi sp, sp, 76
#endif /* ALT_EXCEPTION_STACK */
/*
* Return to the interrupted instruction.
*/
eret
#ifdef ALT_STACK_CHECK
.Lstack_overflow:
break 3
#endif /* ALT_STACK_CHECK */
|
agural/FPGA-Oscilloscope
| 21,315
|
FPGA/Test/software/code_bsp/HAL/src/alt_exception_muldiv.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the software multiply/divide handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_muldiv
alt_exception_muldiv:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
/* INSTRUCTION EMULATION
* ---------------------
*
* Nios II processors generate exceptions for unimplemented instructions.
* The routines below emulate these instructions. Depending on the
* processor core, the only instructions that might need to be emulated
* are div, divu, mul, muli, mulxss, mulxsu, and mulxuu.
*
* The emulations match the instructions, except for the following
* limitations:
*
* 1) The emulation routines do not emulate the use of the exception
* temporary register (et) as a source operand because the exception
* handler already has modified it.
*
* 2) The routines do not emulate the use of the stack pointer (sp) or the
* exception return address register (ea) as a destination because
* modifying these registers crashes the exception handler or the
* interrupted routine.
*
* 3) To save code size, the routines do not emulate the use of the
* breakpoint registers (ba and bt) as operands.
*
* Detailed Design
* ---------------
*
* The emulation routines expect the contents of integer registers r0-r31
* to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The
* routines retrieve source operands from the stack and modify the
* destination register's value on the stack prior to the end of the
* exception handler. Then all registers except the destination register
* are restored to their previous values.
*
* The instruction that causes the exception is found at address -4(ea).
* The instruction's OP and OPX fields identify the operation to be
* performed.
*
* One instruction, muli, is an I-type instruction that is identified by
* an OP field of 0x24.
*
* muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24-
* 27 22 6 0 <-- LSB of field
*
* The remaining emulated instructions are R-type and have an OP field
* of 0x3a. Their OPX fields identify them.
*
* R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a-
* 27 22 17 11 6 0 <-- LSB of field
*
*
*/
/*
* Split the instruction into its fields. We need 4*A, 4*B, and 4*C as
* offsets to the stack pointer for access to the stored register values.
*/
/* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */
roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */
roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */
roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */
srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */
xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */
roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */
andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */
xori r3, r3, 0x40
andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */
andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */
andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */
/* Now either
* r5 = OP
* r3 = 4*(A^16)
* r4 = IMM16 (sign extended)
* r6 = 4*(B^16)
* r7 = 4*(C^16)
* or
* r5 = OP
*/
/*
* Save everything on the stack to make it easy for the emulation routines
* to retrieve the source register operands. The exception entry code has
* already saved some of this so we don't need to do it all again.
*/
addi sp, sp, -60
stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */
/* Register at and r2-r15 have already been saved. */
stw r16, 0(sp)
stw r17, 4(sp)
stw r18, 8(sp)
stw r19, 12(sp)
stw r20, 16(sp)
stw r21, 20(sp)
stw r22, 24(sp)
stw r23, 28(sp)
/* et @ 32 - Has already been changed.*/
/* bt @ 36 - Usually isn't an operand. */
stw gp, 40(sp)
stw sp, 44(sp)
stw fp, 48(sp)
/* ea @ 52 - Don't bother to save - it's already been changed */
/* ba @ 56 - Breakpoint register usually isn't an operand */
/* ra @ 60 - Has already been saved */
/*
* Prepare for either multiplication or division loop.
* They both loop 32 times.
*/
movi r14, 32
/*
* Get the operands.
*
* It is necessary to check for muli because it uses an I-type instruction
* format, while the other instructions are have an R-type format.
*/
add r3, r3, sp /* r3 = address of A-operand. */
ldw r3, 0(r3) /* r3 = A-operand. */
movi r15, 0x24 /* muli opcode (I-type instruction format) */
beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */
add r6, r6, sp /* r6 = address of B-operand. */
ldw r6, 0(r6) /* r6 = B-operand. */
/* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */
/* IMM16 not needed, align OPX portion */
/* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */
/* Now
* r5 = OP
* r3 = src1
* r6 = src2
* r4 = OPX (no longer can be muli)
* r7 = 4*(C^16)
* r14 = loop counter
*/
/* ILLEGAL-INSTRUCTION EXCEPTION
* -----------------------------
*
* This code is for Nios II cores that generate exceptions when attempting
* to execute illegal instructions. Nios II cores that support an
* illegal-instruction exception are identified by the presence of the
* macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h .
*
* Remember that illegal instructions are different than unimplemented
* instructions. Illegal instructions are instruction encodings that
* have not been defined by the Nios II ISA. Unimplemented instructions
* are legal instructions that must be emulated by some Nios II cores.
*
* If we get here, all instructions except multiplies and divides
* are illegal.
*
* This code assumes that OP is not muli (because muli was tested above).
* All other multiplies and divides are legal. Anything else is illegal.
*/
movi r8, 0x3a /* OP for R-type mul* and div* */
bne r5, r8, .Lnot_muldiv
/* r15 already is 0x24 */ /* OPX of divu */
beq r4, r15, .Ldivide
movi r15,0x27 /* OPX of mul */
beq r4, r15, .Lmultiply
movi r15,0x07 /* OPX of mulxuu */
beq r4, r15, .Lmultiply
movi r15,0x17 /* OPX of mulxsu */
beq r4, r15, .Lmultiply
movi r15,0x1f /* OPX of mulxss */
beq r4, r15, .Lmultiply
movi r15,0x25 /* OPX of div */
bne r4, r15, .Lnot_muldiv
/* DIVISION
*
* Divide an unsigned dividend by an unsigned divisor using
* a shift-and-subtract algorithm. The example below shows
* 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a
* single register to store both the dividend and the quotient,
* allowing both values to be shifted with a single instruction.
*
* remainder dividend:quotient
* --------- -----------------
* initialize 00000000 00101011:
* shift 00000000 0101011:_
* remainder >= divisor? no 00000000 0101011:0
* shift 00000000 101011:0_
* remainder >= divisor? no 00000000 101011:00
* shift 00000001 01011:00_
* remainder >= divisor? no 00000001 01011:000
* shift 00000010 1011:000_
* remainder >= divisor? no 00000010 1011:0000
* shift 00000101 011:0000_
* remainder >= divisor? no 00000101 011:00000
* shift 00001010 11:00000_
* remainder >= divisor? yes 00001010 11:000001
* remainder -= divisor - 00000111
* ----------
* 00000011 11:000001
* shift 00000111 1:000001_
* remainder >= divisor? yes 00000111 1:0000011
* remainder -= divisor - 00000111
* ----------
* 00000000 1:0000011
* shift 00000001 :0000011_
* remainder >= divisor? no 00000001 :00000110
*
* The quotient is 00000110.
*/
.Ldivide:
/*
* Prepare for division by assuming the result
* is unsigned, and storing its "sign" as 0.
*/
movi r17, 0
/* Which division opcode? */
xori r15, r4, 0x25 /* OPX of div */
bne r15, zero, .Lunsigned_division
/*
* OPX is div. Determine and store the sign of the quotient.
* Then take the absolute value of both operands.
*/
xor r17, r3, r6 /* MSB contains sign of quotient */
bge r3, zero, 0f
sub r3, zero, r3 /* -r3 */
0:
bge r6, zero, 0f
sub r6, zero, r6 /* -r6 */
0:
.Lunsigned_division:
/* Initialize the unsigned-division loop. */
movi r13, 0 /* remainder = 0 */
/* Now
* r3 = dividend : quotient
* r4 = 0x25 for div, 0x24 for divu
* r6 = divisor
* r13 = remainder
* r14 = loop counter (already initialized to 32)
* r17 = MSB contains sign of quotient
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Ldivide_loop:
/*
* Division:
*
* (remainder:dividend:quotient) <<= 1;
*/
slli r13, r13, 1
cmplt r15, r3, zero /* r15 = MSB of r3 */
or r13, r13, r15
slli r3, r3, 1
/*
* if (remainder >= divisor)
* {
* set LSB of quotient
* remainder -= divisor;
* }
*/
bltu r13, r6, .Ldiv_skip
ori r3, r3, 1
sub r13, r13, r6
.Ldiv_skip:
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Ldivide_loop
mov r9, r3
/* Now
* r9 = quotient
* r4 = 0x25 for div, 0x24 for divu
* r7 = 4*(C^16)
* r17 = MSB contains sign of quotient
*/
/*
* Conditionally negate signed quotient. If quotient is unsigned,
* the sign already is initialized to 0.
*/
bge r17, zero, .Lstore_result
sub r9, zero, r9 /* -r9 */
br .Lstore_result
/* MULTIPLICATION
*
* A "product" is the number that one gets by summing a "multiplicand"
* several times. The "multiplier" specifies the number of copies of the
* multiplicand that are summed.
*
* Actual multiplication algorithms don't use repeated addition, however.
* Shift-and-add algorithms get the same answer as repeated addition, and
* they are faster. To compute the lower half of a product (pppp below)
* one shifts the product left before adding in each of the partial products
* (a * mmmm) through (d * mmmm).
*
* To compute the upper half of a product (PPPP below), one adds in the
* partial products (d * mmmm) through (a * mmmm), each time following the
* add by a right shift of the product.
*
* mmmm
* * abcd
* ------
* #### = d * mmmm
* #### = c * mmmm
* #### = b * mmmm
* #### = a * mmmm
* --------
* PPPPpppp
*
* The example above shows 4 partial products. Computing actual Nios II
* products requires 32 partials.
*
* It is possible to compute the result of mulxsu from the result of mulxuu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rA.
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*
* It is possible to compute the result of mulxss from the result of mulxsu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rB.
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*
*/
.Lmul_immed:
/* Opcode is muli. Change it into mul for remainder of algorithm. */
mov r7, r6 /* Field B is dest register, not field C. */
mov r6, r4 /* Field IMM16 is src2, not field B. */
movi r4, 0x27 /* OPX of mul is 0x27 */
.Lmultiply:
/* Initialize the multiplication loop. */
movi r9, 0 /* mul_product = 0 */
movi r10, 0 /* mulxuu_product = 0 */
mov r11, r6 /* save original multiplier for mulxsu and mulxss */
mov r12, r6 /* mulxuu_multiplier (will be shifted) */
movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */
/* Now
* r3 = multiplicand
* r6 = mul_multiplier
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r12 = mulxuu_multiplier
* r14 = loop counter (already initialized)
* r15 = temp
* r16 = 1
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Lmultiply_loop:
/*
* mul_product <<= 1;
* lsb = multiplier & 1;
*/
slli r9, r9, 1
andi r15, r12, 1
/*
* if (lsb == 1)
* {
* mulxuu_product += multiplicand;
* }
*/
beq r15, zero, .Lmulx_skip
add r10, r10, r3
cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */
ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */
.Lmulx_skip:
/*
* if (MSB of mul_multiplier == 1)
* {
* mul_product += multiplicand;
* }
*/
bge r6, zero, .Lmul_skip
add r9, r9, r3
.Lmul_skip:
/*
* mulxuu_product >>= 1; logical shift
* mul_multiplier <<= 1; done with MSB
* mulx_multiplier >>= 1; done with LSB
*/
srli r10, r10, 1
or r10, r10, r15 /* OR in the saved carry bit. */
slli r6, r6, 1
srli r12, r12, 1
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Lmultiply_loop
/*
* Multiply emulation loop done.
*/
/* Now
* r3 = multiplicand
* r4 = OPX
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r15 = temp
*/
/*
* Select/compute the result based on OPX.
*/
/* OPX == mul? Then store. */
xori r15, r4, 0x27
beq r15, zero, .Lstore_result
/* It's one of the mulx.. opcodes. Move over the result. */
mov r9, r10
/* OPX == mulxuu? Then store. */
xori r15, r4, 0x07
beq r15, zero, .Lstore_result
/* Compute mulxsu
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*/
bge r3, zero, .Lmulxsu_skip
sub r9, r9, r11
.Lmulxsu_skip:
/* OPX == mulxsu? Then store. */
xori r15, r4, 0x17
beq r15, zero, .Lstore_result
/* Compute mulxss
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*/
bge r11, zero, .Lmulxss_skip
sub r9, r9, r3
.Lmulxss_skip:
/* At this point, assume that OPX is mulxss, so store */
.Lstore_result:
add r7, r7, sp
stw r9, 0(r7)
ldw r16, 0(sp)
ldw r17, 4(sp)
ldw r18, 8(sp)
ldw r19, 12(sp)
ldw r20, 16(sp)
ldw r21, 20(sp)
ldw r22, 24(sp)
ldw r23, 28(sp)
/* bt @ 32 - Breakpoint register usually isn't an operand. */
/* et @ 36 - Don't corrupt et. */
/* gp @ 40 - Don't corrupt gp. */
/* sp @ 44 - Don't corrupt sp. */
ldw fp, 48(sp)
/* ea @ 52 - Don't corrupt ea. */
/* ba @ 56 - Breakpoint register usually isn't an operand. */
addi sp, sp, 60
br .Lexception_exit
.Lnot_muldiv:
addi sp, sp, 60
.section .exceptions.exit.label
.Lexception_exit:
|
agural/FPGA-Oscilloscope
| 2,989
|
FPGA/Test/software/code_bsp/HAL/src/alt_software_exception.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This file provides the global symbol: software_exception. It is provided to
* support legacy code, and should not be used by new software.
*
* It is used by legacy code to invoke the software exception handler as
* defined by version 1.0 of the Nios II kit. It should only be used when you
* are providing your own interrupt entry point, i.e. you are not using
* alt_irq_entry.
*/
#include "system.h"
/*
* Pull in the exception handler.
*/
.globl alt_exception
.section .exceptions.entry.label, "xa"
.globl software_exception
.type software_exception, @function
software_exception:
|
agural/FPGA-Oscilloscope
| 16,254
|
FPGA/Test/software/code_bsp/HAL/src/crt0.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
#include "nios2.h"
/* Setup header files to work with assembler code. */
#define ALT_ASM_SRC
/* Debug logging facility */
#include "sys/alt_log_printf.h"
/*************************************************************************\
| MACROS |
\*************************************************************************/
/*
* The new build tools explicitly define macros when alt_load()
* must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that
* those macros are controlling if alt_load() needs to be called.
*/
#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED
/* Need to call alt_load() if any of these sections are being copied. */
#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS)
#define CALL_ALT_LOAD
#endif
#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* The legacy build tools use the following macros to detect when alt_load()
* needs to be called.
*/
#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \
((res##_BASE != rodata##_BASE) || \
(res##_BASE != rwdata##_BASE) || \
(res##_BASE != exc##_BASE))
#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \
__ALT_LOAD_SECTIONS(res, text, rodata, exc)
#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \
ALT_RODATA_DEVICE, \
ALT_RWDATA_DEVICE, \
ALT_EXCEPTIONS_DEVICE)
/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */
#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS
#define CALL_ALT_LOAD
#endif
#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* When the legacy build tools define a macro called ALT_NO_BOOTLOADER,
* it indicates that initialization code is allowed at the reset address.
* The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for
* the same purpose.
*/
#ifdef ALT_NO_BOOTLOADER
#define ALT_ALLOW_CODE_AT_RESET
#endif
/*************************************************************************\
| EXTERNAL REFERENCES |
\*************************************************************************/
/*
* The entry point for user code is either "main" in hosted mode, or
* "alt_main" in standalone mode. These are explicitly referenced here,
* to ensure they are built into the executable. This allows the user
* to build them into libraries, rather than supplying them in object
* files at link time.
*/
.globl main
.globl alt_main
/*
* Create a reference to the software multiply/divide and trap handers,
* so that if they are provided, they will appear in the executable.
*/
#ifndef ALT_NO_INSTRUCTION_EMULATION
.globl alt_exception_muldiv
#endif
#ifdef ALT_TRAP_HANDLER
.globl alt_exception_trap
#endif
/*
* Linker defined symbols used to initialize bss.
*/
.globl __bss_start
.globl __bss_end
/*************************************************************************\
| RESET SECTION (.entry) |
\*************************************************************************/
/*
* This is the reset entry point for Nios II.
*
* At reset, only the cache line which contain the reset vector is
* initialized by the hardware. The code within the first cache line
* initializes the remainder of the instruction cache.
*/
.section .entry, "xa"
.align 5
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* Some tools want to know where the reset vector is.
* Code isn't always provided at the reset vector but at least the
* __reset label always contains the reset vector address because
* it is defined at the start of the .entry section.
*/
.globl __reset
.type __reset, @function
__reset:
/*
* Initialize the instruction cache if present (i.e. size > 0) and
* reset code is allowed unless optimizing for RTL simulation.
* RTL simulations can ensure the instruction cache is already initialized
* so skipping this loop speeds up RTL simulation.
*/
#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE)
/* Assume the instruction cache size is always a power of two. */
#if NIOS2_ICACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_ICACHE_SIZE)
#else
movui r2, NIOS2_ICACHE_SIZE
#endif
0:
initi r2
addi r2, r2, -NIOS2_ICACHE_LINE_SIZE
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 1, 1, 0b, 1b
.popsection
#endif /* Initialize Instruction Cache */
/*
* Jump to the _start entry point in the .text section if reset code
* is allowed or if optimizing for RTL simulation.
*/
#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
/* Jump to the _start entry point in the .text section. */
movhi r1, %hi(_start)
ori r1, r1, %lo(_start)
jmp r1
.size __reset, . - __reset
#endif /* Jump to _start */
/*
* When not using exit, provide an _exit symbol to prevent unresolved
* references to _exit from the linker script.
*/
#ifdef ALT_NO_EXIT
.globl _exit
_exit:
#endif
/*************************************************************************\
| TEXT SECTION (.text) |
\*************************************************************************/
/*
* Start of the .text section, and also the code entry point when
* the code is executed by a bootloader rather than directly from reset.
*/
.section .text
.align 2
.globl _start
.type _start, @function
_start:
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Ensure that the current register set is 0 upon
* entry to this code. Switch register set to 0 by
* writing zero to SSTATUS register and executing an ERET instruction
* to set STATUS.CRS to 0.
*/
/* Get the current register set number (STATUS.CRS). */
rdctl r2, status
andi r2, r2, NIOS2_STATUS_CRS_MSK
/* Skip switching register set if STATUS.CRS is 0. */
beq r2, zero, 0f
/* Set SSTATUS to 0 to get to set SSTATUS.PRS to 0. */
.set nobreak
movui sstatus, 0
.set break
/* Switch to register set 0 and jump to label. */
movhi ea, %hi(0f)
ori ea, ea, %lo(0f)
eret
0:
#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */
/*
* Initialize the data cache if present (i.e. size > 0).
* Skip initialization if optimizing for RTL simulation and ECC isn't present.
* RTL simulations can ensure the data cache tag RAM is already initialized
* (but not the data RAM for ECC) so skipping this speeds up RTL simulation.
*
* When ECC is present, need to execute initd for each word address
* to ensure ECC parity bits in data RAM get initialized.
* Otherwise, only need to execute initd for each line address.
*/
#if NIOS2_DCACHE_SIZE > 0 && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
/* Assume the data cache size is always a power of two. */
#if NIOS2_DCACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_DCACHE_SIZE)
#else
movui r2, NIOS2_DCACHE_SIZE
#endif
0:
initd 0(r2)
#ifdef NIOS2_ECC_PRESENT
addi r2, r2, -4
#else
addi r2, r2, -NIOS2_DCACHE_LINE_SIZE
#endif
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 2, 1, 0b, 1b
.popsection
#endif /* Initialize Data Cache */
/* Log that caches have been initialized. */
ALT_LOG_PUTS(alt_log_msg_cache)
/* Log that the stack pointer is about to be setup. */
ALT_LOG_PUTS(alt_log_msg_stackpointer)
/*
* Now that the caches are initialized, set up the stack pointer and global pointer.
* The values provided by the linker are assumed to be correctly aligned.
*/
movhi sp, %hi(__alt_stack_pointer)
ori sp, sp, %lo(__alt_stack_pointer)
movhi gp, %hi(_gp)
ori gp, gp, %lo(_gp)
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
movui r1, 0
movui r2, 0
movui r3, 0
movui r4, 0
movui r5, 0
movui r6, 0
movui r7, 0
movui r8, 0
movui r9, 0
movui r10, 0
movui r11, 0
movui r12, 0
movui r13, 0
movui r14, 0
movui r15, 0
movui r16, 0
movui r17, 0
movui r18, 0
movui r19, 0
movui r20, 0
movui r21, 0
movui r22, 0
movui r23, 0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it is already been initialized. */
movui r28, 0 /* fp */
movui r29, 0 /* ea */
.set nobreak
movui r30, 0 /* sstatus */
.set break
movui r31, 0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Setup registers in shadow register sets
* from 1 to NIOS2_NUM_OF_SHADOW_REG_SETS.
*/
movui r2, 0 /* Contains value written into STATUS */
movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS /* counter */
movhi r4, 1 /* Constant to increment STATUS.PRS */
.Linitialize_shadow_registers:
/* Increment STATUS.PRS */
add r2, r2, r4
wrctl status, r2
/* Clear r0 in the shadow register set (not done by hardware) */
wrprs r0, r0
/* Write the GP in previous register set */
wrprs gp, gp
/*
* Only write the SP in previous register set
* if using the separate exception stack. For normal case (single stack),
* funnel code would read the SP from previous register set with a RDPRS.
*/
#ifdef ALT_INTERRUPT_STACK
movhi et, %hiadj(__alt_interrupt_stack_pointer)
addi et, et, %lo(__alt_interrupt_stack_pointer)
wrprs sp, et
#endif /* ALT_INTERRUPT_STACK */
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
wrprs r1, r0
wrprs r2, r0
wrprs r3, r0
wrprs r4, r0
wrprs r5, r0
wrprs r6, r0
wrprs r7, r0
wrprs r8, r0
wrprs r9, r0
wrprs r10, r0
wrprs r11, r0
wrprs r12, r0
wrprs r13, r0
wrprs r14, r0
wrprs r15, r0
wrprs r16, r0
wrprs r17, r0
wrprs r18, r0
wrprs r19, r0
wrprs r20, r0
wrprs r21, r0
wrprs r22, r0
wrprs r23, r0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it was initialized above or will be by a rdprs if not above */
wrprs r28, r0 /* fp */
wrprs r29, r0 /* ea */
wrprs r30, r0 /* ba */
wrprs r31, r0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
/* Decrement shadow register set counter */
addi r3, r3, -1
/* Done if index is 0. */
bne r3, zero, .Linitialize_shadow_registers
#endif /* (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) */
/*
* Clear the BSS if not optimizing for RTL simulation.
*
* This uses the symbols: __bss_start and __bss_end, which are defined
* by the linker script. They mark the begining and the end of the bss
* region. The linker script guarantees that these values are word aligned.
*/
#ifndef ALT_SIM_OPTIMIZE
/* Log that the BSS is about to be cleared. */
ALT_LOG_PUTS(alt_log_msg_bss)
movhi r2, %hi(__bss_start)
ori r2, r2, %lo(__bss_start)
movhi r3, %hi(__bss_end)
ori r3, r3, %lo(__bss_end)
beq r2, r3, 1f
0:
stw zero, (r2)
addi r2, r2, 4
bltu r2, r3, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 3, 1, 0b, 1b
.popsection
#endif /* ALT_SIM_OPTIMIZE */
/*
* The alt_load() facility is normally used when there is no bootloader.
* It copies some sections into RAM so it acts like a mini-bootloader.
*/
#ifdef CALL_ALT_LOAD
#ifdef ALT_STACK_CHECK
/*
* If the user has selected stack checking then we need to set up a safe
* value in the stack limit register so that the relocation functions
* don't think the stack has overflowed (the contents of the rwdata
* section aren't defined until alt_load() has been called).
*/
mov et, zero
#endif
call alt_load
#endif /* CALL_ALT_LOAD */
#ifdef ALT_STACK_CHECK
/*
* Set up the stack limit (if required). The linker has set up the
* copy of the variable which is in memory.
*/
ldw et, %gprel(alt_stack_limit_value)(gp)
#endif
/* Log that alt_main is about to be called. */
ALT_LOG_PUTS(alt_log_msg_alt_main)
/* Call the C entry point. It should never return. */
call alt_main
/* Wait in infinite loop in case alt_main does return. */
alt_after_alt_main:
br alt_after_alt_main
.size _start, . - _start
/*
* Add information about the stack base if stack overflow checking is enabled.
*/
#ifdef ALT_STACK_CHECK
.globl alt_stack_limit_value
.section .sdata,"aws",@progbits
.align 2
.type alt_stack_limit_value, @object
.size alt_stack_limit_value, 4
alt_stack_limit_value:
.long __alt_stack_limit
#endif
|
agural/FPGA-Oscilloscope
| 8,293
|
FPGA/Test/software/code_bsp/HAL/src/alt_mcount.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/* mcount or _mcount is inserted by GCC before the function prologue of every
* function when a program is compiled for profiling. At the start of mcount,
* we guarantee that:
* ra = self_pc (an address in the function which called mcount)
* r8 = from_pc (an address in the function which called mcount's caller)
*
* Because this is always called at the start of a function we can corrupt
* r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain
* function arguments for the instrumented function) or r8 (which holds ra
* for the instrumented function).
*/
.global __mcount_fn_head
.global mcount
/* _mcount is used by gcc4 */
.global _mcount
_mcount:
mcount:
/* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose
* the bucket because bits 1:0 will always be 0, and because the distribution
* of values for bits 4:2 won't be even (aligning on cache line boundaries
* will skew it). Higher bits should be fairly random.
*/
/* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */
srli r2, ra, 3
movhi r3, %hiadj(__mcount_fn_head)
addi r3, r3, %lo(__mcount_fn_head)
andi r2, r2, 0xFC
add r11, r2, r3
/* The fast case is where we have already allocated a function arc, and so
* also a function pointer.
*/
/* First find the function being called (using self_pc) */
mov r10, r11
0:
ldw r10, 0(r10)
beq r10, zero, .Lnew_arc
ldw r2, 4(r10)
bne r2, ra, 0b
/* Found a function entry for this PC. Now look for an arc with a matching
* from_pc value. There will always be at least one arc. */
ldw r3, 8(r10)
0:
ldw r2, 4(r3)
beq r2, r8, .Lfound_arc
ldw r3, 0(r3)
bne r3, zero, 0b
.Lnew_arc:
addi sp, sp, -24
.LCFI0:
stw ra, 0(sp)
stw r4, 4(sp)
stw r5, 8(sp)
stw r6, 12(sp)
stw r7, 16(sp)
stw r8, 20(sp)
.LCFI1:
/* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */
mov r4, ra
mov r5, r8
mov r6, r10
mov r7, r11
call __mcount_record
/* restore registers from the stack */
ldw ra, 0(sp)
ldw r4, 4(sp)
ldw r5, 8(sp)
ldw r6, 12(sp)
ldw r7, 16(sp)
ldw r8, 20(sp)
addi sp, sp, 24
.LCFI2:
ret
.Lfound_arc:
/* We've found the correct arc record. Increment the count and return */
ldw r2, 8(r3)
addi r2, r2, 1
stw r2, 8(r3)
ret
.Lmcount_end:
/*
* Dwarf2 debug information for the function. This provides GDB with the
* information it needs to backtrace out of this function.
*/
.section .debug_frame,"",@progbits
.LCIE:
.4byte 2f - 1f /* Length */
1:
.4byte 0xffffffff /* CIE id */
.byte 0x1 /* Version */
.string "" /* Augmentation */
.uleb128 0x1 /* Code alignment factor */
.sleb128 -4 /* Data alignment factor */
.byte 0x1f /* Return address register */
.byte 0xc /* Define CFA */
.uleb128 0x1b /* Register 27 (sp) */
.uleb128 0x0 /* Offset 0 */
.align 2 /* Padding */
2:
.LFDE_mcount:
.4byte 2f - 1f /* Length */
1:
.4byte .LCIE /* Pointer to CIE */
.4byte mcount /* Start of table entry */
.4byte .Lmcount_end - mcount /* Size of table entry */
.byte 0x4 /* Advance location */
.4byte .LCFI0 - mcount /* to .LCFI0 */
.byte 0xe /* Define CFA offset */
.uleb128 24 /* to 24 */
.byte 0x4 /* Advance location */
.4byte .LCFI1 - .LCFI0 /* to .LCFI1 */
.byte 0x9f /* Store ra */
.uleb128 0x6 /* at CFA-24 */
.byte 0x84 /* Store r4 */
.uleb128 0x5 /* at CFA-20 */
.byte 0x85 /* Store r5 */
.uleb128 0x4 /* at CFA-16 */
.byte 0x86 /* Store r6 */
.uleb128 0x3 /* at CFA-12 */
.byte 0x87 /* Store r7 */
.uleb128 0x2 /* at CFA-8 */
.byte 0x88 /* Store r8 */
.uleb128 0x1 /* at CFA-4 */
.byte 0x4 /* Advance location */
.4byte .LCFI2 - .LCFI1 /* to .LCFI2 */
.byte 0xe /* Define CFA offset */
.uleb128 0 /* to 0 */
.byte 0x8 /* Same value */
.uleb128 31 /* for ra */
.byte 0x8 /* Same value */
.uleb128 4 /* for r4 */
.byte 0x8 /* Same value */
.uleb128 5 /* for r5 */
.byte 0x8 /* Same value */
.uleb128 6 /* for r6 */
.byte 0x8 /* Same value */
.uleb128 7 /* for r7 */
.byte 0x8 /* Same value */
.uleb128 8 /* for r8 */
.align 2
2:
|
agural/FPGA-Oscilloscope
| 5,245
|
FPGA/Test/software/code_bsp/HAL/src/alt_ecc_fatal_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the code called at the beginning of the exception handler
* to detect a likely fatal ECC error exception and then jump to
* user-provided code to handle it.
*
* This code is pulled in from a .globl in alt_ecc_fatal_exception.c.
* This scheme is used so that if a handler is never registered, then this
* code will not appear in the generated executable, thereby improving
* code footprint.
*
* This code is located in its own section that the linker script
* explicitly mentions and ensures it gets linked at the beginning
* of the exception handler.
*/
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.section .exceptions.entry.ecc_fatal, "xa"
/*
* This might be handling an unrecoverable ECC error exception
* in the register file and/or data cache.
* Must avoid reading registers or performing load/store instructions
* before this is determined because they could trigger another
* unrecoverable ECC error exception and create an infinite loop.
*
* The EXCEPTION register is always present when ECC is present.
* Bit 31 of this register indicates that there was an unrecoverable
* ECC error exception in the register file and/or data cache.
* Test this (using blt to check sign bit) to determine if this is
* what we are dealing with. Otherwise, just do normal processing.
*
* Jump to an application-provided routine to handle this condition.
* Pass in the return address in the et register in case this code
* can clean up the ECC error and then return here (unlikely).
*
* Runtime stack checking can't be enabled when ECC is present
* because they both want to use the et register.
*/
rdctl et, exception
bge et, r0, alt_exception_not_ecc_fatal /* Not ECCFTL if bit 31 is 0 */
/*
* Load ECC fatal handler pointer into et register.
* Using a ldwio is safe because it completely bypasses the data cache.
*/
movhi et, %hi(alt_exception_ecc_fatal_handler)
ori et, et, %lo(alt_exception_ecc_fatal_handler)
ldwio et, 0(et)
/*
* If ECC fatal handler pointer is not 0, assume a handler
* has been provided by the application.
*/
beq et, r0, alt_exception_not_ecc_fatal
/*
* The et register contains the address of the ECC fatal handler.
* Jump to this address to invoke the handler.
*/
jmp et
/*
* An ECC fatal handler can jump to this label if it able
* to recover from the fatal error (rare) and wants to continue
* with normal exception processing.
*/
.globl alt_exception_not_ecc_fatal
alt_exception_not_ecc_fatal:
|
agraef/purr-data
| 1,899
|
externals/pdp/system/mmx/pixel_mix_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
.globl pixel_mix_s16
.type pixel_mix_s16,@function
# mmx rgba pixel gain
# void pixel_mix_s16(int *left, int *right, int nb_4pixel_vectors,
# short int gain_left[4], short int gain_right[4])
pixel_mix_s16:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 20(%ebp), %edi # int16[4] array of gains
movq (%edi), %mm6 # get left gain array
movl 24(%ebp), %edi # int16[4] array of gains
movq (%edi), %mm7 # get right gain array
movl 8(%ebp), %edi # left array
movl 12(%ebp), %esi # right array
movl 16(%ebp), %ecx # pixel count
.align 16
.loop_mix:
# prefetch 128(%esi)
movq (%esi), %mm1 # load right 4 pixels from memory
pmulhw %mm7, %mm1 # apply right gain
movq (%edi), %mm0 # load 4 left pixels from memory
pmulhw %mm6, %mm0 # apply left gain
# pslaw $1, %mm1 # shift left ((s).15 x (s).15 -> (s0).14))
# pslaw $1, %mm0
paddsw %mm0, %mm0 # no shift left arithmic, so use add instead
paddsw %mm1, %mm1
paddsw %mm1, %mm0 # mix
movq %mm0, (%edi)
addl $8, %esi
addl $8, %edi
decl %ecx
jnz .loop_mix # loop
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 2,931
|
externals/pdp/system/mmx/pixel_unpack_u8s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
.globl pixel_unpack_u8s16_y
.type pixel_unpack_u8s16_y,@function
# mmx rgba pixel gain
# void pixel_unpack_u8s16_y(char *input, char *output, int32 nb_pixels_div8)
pixel_unpack_u8s16_y:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
# movl 20(%ebp), %edi # int16[4] array of gains
# movq (%edi), %mm7 # get gain array
movl 8(%ebp), %esi # input uint8 pixel array
movl 12(%ebp), %edi # output sint16 pixel array
movl 16(%ebp), %ecx # nb of elements div 8
.align 16
.loop_unpack_y:
movq (%esi), %mm5 # load 8 pixels from memory
pxor %mm0, %mm0 # zero mm0 - mm3
pxor %mm1, %mm1
punpcklbw %mm5, %mm0 # unpack 1st 4 pixels
punpckhbw %mm5, %mm1 # unpack 2nd 4 pixles
psrlw $0x1, %mm0 # shift right to clear sign bit 9.7
psrlw $0x1, %mm1
# pmulhw %mm7, %mm0 # apply gain
# pmulhw %mm7, %mm1
# paddsw %mm0, %mm0 # correct factor 2
# paddsw %mm1, %mm1
movq %mm0, (%edi) # store
movq %mm1, 8(%edi)
addl $8, %esi # increment source pointer
addl $16, %edi # increment dest pointer
decl %ecx
jnz .loop_unpack_y # loop
emms
pop %edi
pop %esi
leave
ret
.globl pixel_unpack_u8s16_uv
.type pixel_unpack_u8s16_uv,@function
pixel_unpack_u8s16_uv:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
# movl 20(%ebp), %edi # int16[4] array of gains
# movq (%edi), %mm7 # get gain array
movl 8(%ebp), %esi # input uint8 pixel array
movl 12(%ebp), %edi # output sint16 pixel array
movl 16(%ebp), %ecx # nb of elements div 8
pcmpeqw %mm6, %mm6
psllw $15, %mm6
.align 16
.loop_unpack_uv:
movq (%esi), %mm5 # load 8 pixels from memory
pxor %mm0, %mm0 # zero mm0 - mm3
pxor %mm1, %mm1
punpcklbw %mm5, %mm0 # unpack 1st 4 pixels
punpckhbw %mm5, %mm1 # unpack 2nd 4 pixles
pxor %mm6, %mm0 # flip sign bit (Cr and Cb are ofset by 128)
pxor %mm6, %mm1
# pmulhw %mm7, %mm0 # apply gain
# pmulhw %mm7, %mm1
# paddsw %mm0, %mm0 # correct factor 2
# paddsw %mm1, %mm1
movq %mm0, (%edi) # store
movq %mm1, 8(%edi)
addl $8, %esi # increment source pointer
addl $16, %edi # increment dest pointer
decl %ecx
jnz .loop_unpack_uv # loop
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 4,205
|
externals/pdp/system/mmx/pixel_ca_s1.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
# this file contains assembler routines for 2D 1 bit cellular automata
# processing. it is organized around a feeder kernel and a
# stack based bit processor (virtual forth machine)
#
# the feeder kernel is responsable for loading/storing CA cells
# from/to memory. data in memory is organized as a scanline
# encoded toroidial bitplane (lsb = left). to simplify the kernel, the top
# left corner of the rectangular grid of pixels will shift down
# every processing step.
#
# the stack machine has the following architecture:
# CA stack: %esi, TOS: %mm0 (32x2 pixels. lsw = top row)
# CA horizon: %mm4-%mm7 (64x4 pixels. %mm4 = top row)
#
# the stack size / organization is not known to the stack machine.
# it can be thought of as operating on a 3x3 cell neightbourhood.
# the only purpose of forth program is to determine the CA local update rule.
#
# the machine is supposed to be very minimal. no looping control.
# no adressing modes. no conditional code (hey, this is an experiment!)
# so recursion is not allowed (no way to stop it)
# there are 9 words to load the cell neigbourhood on the stack.
# the rest is just logic and stack manips.
# this file contains pure asm macros. it is to be included before assembly
# after scaforth.pl has processed the .scaf file
# *************************** CA CELL ACCESS MACROS *****************************
# fetchTL - fetchBR
# shift / load rectangle macros:
# shift rectangle horizontal
# result is in reg1
.macro shift reg1 reg2 count
psllq $(32+\count), \reg1
psrlq $(32-\count), \reg2
psrlq $32, \reg1
psllq $32, \reg2
por \reg2, \reg1
.endm
.macro ldtop reg1 reg2
movq %mm4, \reg1
movq %mm5, \reg2
.endm
.macro ldcenter reg1 reg2
movq %mm5, \reg1
movq %mm6, \reg2
.endm
.macro ldbottom reg1 reg2
movq %mm6, \reg1
movq %mm7, \reg2
.endm
# fetch from top row
# fetch the top left square
.macro fetchTL
ldtop %mm0, %mm1
shift %mm0, %mm1, -1
.endm
# fetch the top mid square
.macro fetchTM
ldtop %mm0, %mm1
shift %mm0, %mm1, 0
.endm
# fetch the top right square
.macro fetchTR
ldtop %mm0, %mm1
shift %mm0, %mm1, 1
.endm
# fetch from center row
# fetch the mid left square
.macro fetchML
ldcenter %mm0, %mm1
shift %mm0, %mm1, -1
.endm
# fetch the mid mid square
.macro fetchMM
ldcenter %mm0, %mm1
shift %mm0, %mm1, 0
.endm
# fetch the mid right square
.macro fetchMR
ldcenter %mm0, %mm1
shift %mm0, %mm1, 1
.endm
# fetch from bottom row
# fetch the bottom left square
.macro fetchBL
ldbottom %mm0, %mm1
shift %mm0, %mm1, -1
.endm
# fetch the bottom mid square
.macro fetchBM
ldbottom %mm0, %mm1
shift %mm0, %mm1, 0
.endm
# fetch the bottom right square
.macro fetchBR
ldbottom %mm0, %mm1
shift %mm0, %mm1, 1
.endm
# *************************** CA STACK MANIP MACROS *****************************
# dup drop dropdup swap nip dropover
.macro dup
lea -8(%esi), %esi
movq %mm0, (%esi)
.endm
.macro drop
movq (%esi), %mm0
lea 8(%esi), %esi
.endm
.macro dropdup
movq (%esi), %mm0
.endm
.macro swap
movq (%esi), %mm1
movq %mm0, (%esi)
movq %mm1, %mm0
.endm
.macro nip
lea 8(%esi), %esi
.endm
.macro dropover
movq 8(%esi), %mm0
.endm
# *************************** CA BOOLEAN LOGIC MACROS *****************************
# overxor
.macro overxor
pxor (%esi), %mm0
.endm
|
agraef/purr-data
| 3,513
|
externals/pdp/system/mmx/pixel_crot_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
.globl pixel_crot3d_s16
.type pixel_crot3d_s16,@function
# 3 dimensional colour space rotation
# 3x3 matrix is column encoded, each coefficient is a 4x16 bit fixed point vector
# void pixel_crot3d_s16(int *buf, int nb_4pixel_vectors_per_plane, short int *matrix)
pixel_crot3d_s16:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 8(%ebp), %esi # input array
movl 12(%ebp), %ecx # pixel count
movl 16(%ebp), %edi # rotation matrix
movl %ecx, %edx
shll $3, %edx # %edx = plane spacing
.align 16
.loop_crot3d:
movq (%esi), %mm0 # get 1st component
movq (%esi,%edx,1), %mm6 # get 2nd component
movq (%esi,%edx,2), %mm7 # get 3rd component
movq %mm0, %mm1 # copy 1st component
movq %mm0, %mm2
pmulhw (%edi), %mm0 # mul first column
pmulhw 8(%edi), %mm1
pmulhw 16(%edi), %mm2
movq %mm6, %mm5 # copy 2nd component
movq %mm6, %mm3
pmulhw 24(%edi), %mm6 # mul second column
pmulhw 32(%edi), %mm5
pmulhw 40(%edi), %mm3
paddsw %mm6, %mm0 # accumulate
paddsw %mm5, %mm1
paddsw %mm3, %mm2
movq %mm7, %mm4 # copy 3rd component
movq %mm7, %mm6
pmulhw 48(%edi), %mm4 # mul third column
pmulhw 56(%edi), %mm6
pmulhw 64(%edi), %mm7
paddsw %mm4, %mm0 # accumulate
paddsw %mm6, %mm1
paddsw %mm7, %mm2
paddsw %mm0, %mm0 # double (fixed point normalization)
paddsw %mm1, %mm1
paddsw %mm2, %mm2
movq %mm0, (%esi) # store
movq %mm1, (%esi, %edx, 1)
movq %mm2, (%esi, %edx, 2)
addl $8, %esi # increment source pointer
decl %ecx
jnz .loop_crot3d # loop
emms
pop %edi
pop %esi
leave
ret
.globl pixel_crot2d_s16
.type pixel_crot2d_s16,@function
# 2 dimensional colour space rotation
# 2x2 matrix is column encoded, each coefficient is a 4x16 bit fixed point vector
# void pixel_crot2d_s16(int *buf, int nb_4pixel_vectors_per_plane, short int *matrix)
pixel_crot2d_s16:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 8(%ebp), %esi # input array
movl 12(%ebp), %ecx # pixel count
movl 16(%ebp), %edi # rotation matrix
movl %ecx, %edx
shll $3, %edx # %edx = plane spacing
.align 16
.loop_crot2d:
movq (%esi), %mm0 # get 1st component
movq (%esi,%edx,1), %mm2 # get 2nd component
movq %mm0, %mm1 # copy 1st component
movq %mm2, %mm3 # copy 2nd component
pmulhw (%edi), %mm0 # mul first column
pmulhw 8(%edi), %mm1
pmulhw 16(%edi), %mm2 # mul second column
pmulhw 24(%edi), %mm3
paddsw %mm2, %mm0 # accumulate
paddsw %mm3, %mm1
paddsw %mm0, %mm0 # fixed point gain correction
paddsw %mm1, %mm1
movq %mm0, (%esi) # store
movq %mm1, (%esi, %edx, 1)
addl $8, %esi # increment source pointer
decl %ecx
jnz .loop_crot2d # loop
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 2,987
|
externals/pdp/system/mmx/pixel_conv_ver_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
#TODO: fix out of bound acces in conv_ver and conv_hor
# intermediate function
# input in register:
# %mm0: top 4 pixels
# %mm1: middle 4 pixels
# %mm2: bottom 4 pixels
# %mm5: top 4 pixel mask
# %mm6: middle 4 pixel mask
# %mm7: bottom 4 pixel mask
# return in register:
# %mm0: middle 4 pixels result
.conv_ver_4_pixels:
.align 16
# compute quadruplet
# get top pixel
pmulhw %mm5, %mm0
psllw $1, %mm0
# get middle pixel
movq %mm1, %mm4
pmulhw %mm6, %mm4
psllw $1, %mm4
paddsw %mm4, %mm0
# get bottom pixel
movq %mm2, %mm3
pmulhw %mm7, %mm3
psllw $1, %mm3 # mm3 <- mm3/4
paddsw %mm3, %mm0
ret
.globl pixel_conv_ver_s16
.type pixel_conv_ver_s16,@function
# pixel_conv_ver_s16(short int *pixel_array, int nb_4_pixel_vectors, int row_byte_size, short int border[4])
# horizontal unsigned pixel conv (1/4 1/2 1/4) not tested
# NOT TESTED
pixel_conv_ver_s16:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 8(%ebp), %esi # pixel array offset
movl 12(%ebp), %ecx # nb of 4 pixel vectors in a row (at least 2)
movl 16(%ebp), %edx # rowsize in bytes
movl 24(%ebp), %edi # mask vector
movq (%edi), %mm5
movq 8(%edi), %mm6
movq 16(%edi), %mm7
movl 20(%ebp), %edi # edge vector
shll $1, %edx
decl %ecx # loop has a terminator stub
decl %ecx # loop has another terminator stub
movq (%edi), %mm0 # init regs (left edge, so mm0 is zero)
movq (%esi), %mm1
movq (%esi,%edx,1), %mm2
jmp .conv_line_loop
.align 16
.conv_line_loop:
call .conv_ver_4_pixels # compute conv
movq %mm0, (%esi) # store result
movq %mm1, %mm0 # mm0 <- prev (%esi)
movq %mm2, %mm1 # mm1 <- (%esi,%edx,1)
movq (%esi,%edx,2), %mm2 # mm2 <- (%esi,%edx,2)
addl %edx, %esi # increase pointer
decl %ecx
jnz .conv_line_loop
call .conv_ver_4_pixels # compute conv
movq %mm0, (%esi) # store result
movq %mm1, %mm0 # mm0 <- prev (%esi)
movq %mm2, %mm1 # mm1 <- (%esi,%edx,1)
movq (%edi), %mm2 # clear invalid edge vector
addl %edx, %esi # increase pointer
call .conv_ver_4_pixels # compute last vector
movq %mm0, (%esi) # store it
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 3,062
|
externals/pdp/system/mmx/pixel_conv_hor_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
# intermediate function
# input in register:
# %mm0: left 4 pixels
# %mm1: middle 4 pixels
# %mm2: right 4 pixels
# %mm5: left 4 pixel masks
# %mm6: middle 4 pixel masks
# %mm7: right 4 pixel masks
# return in register:
# %mm0: middle 4 pixels result
.conv_hor_4_pixels:
.align 16
# compute quadruplet
# get left pixels
psrlq $48, %mm0 # shift word 3 to byte 0
movq %mm1, %mm4
psllq $16, %mm4 # shift word 0,1,2 to 1,2,3
por %mm4, %mm0 # combine
pmulhw %mm5, %mm0
psllw $1, %mm0
# get middle pixels
movq %mm1, %mm4
pmulhw %mm6, %mm4
psllw $1, %mm4
paddsw %mm4, %mm0
# get right pixels
movq %mm2, %mm3
psllq $48, %mm3 # shift word 0 to word 3
movq %mm1, %mm4
psrlq $16, %mm4 # shift word 1,2,3 to 0,1,2
por %mm4, %mm3 # combine
pmulhw %mm7, %mm3
psllw $1, %mm3
paddsw %mm3, %mm0 # accumulate
ret
.globl pixel_conv_hor_s16
.type pixel_conv_hor_s16,@function
# pixel_conv_hor_s16(short int *pixel_array, int nb_4_pixel_vectors, short int border[4], short int mask[12])
# horizontal unsigned pixel conv (1/4 1/2 1/4) not tested
# NOT TESTED
pixel_conv_hor_s16:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 8(%ebp), %esi # pixel array offset
movl 12(%ebp), %ecx # nb of 8 pixel vectors in a row (at least 2)
movl 20(%ebp), %edi # mask vector
movq (%edi), %mm5
movq 8(%edi), %mm6
movq 16(%edi), %mm7
movl 16(%ebp), %edi # boundary pixel vector
movq (%edi), %mm0 # init regs (left edge, so mm0 is zero)
movq (%esi), %mm1
movq 8(%esi), %mm2
decl %ecx # loop has 2 terminator stubs
decl %ecx # todo: handle if ecx < 3
jmp .conv_line_loop
.align 16
.conv_line_loop:
call .conv_hor_4_pixels # compute conv
movq %mm0, (%esi) # store result
movq %mm1, %mm0 # mm0 <- prev (%esi)
movq %mm2, %mm1 # mm1 <- 8(%esi)
movq 16(%esi), %mm2 # mm2 <- 16(%esi)
addl $8, %esi # increase pointer
decl %ecx
jnz .conv_line_loop
call .conv_hor_4_pixels # compute conv
movq %mm0, (%esi) # store result
movq %mm1, %mm0 # mm0 <- prev (%esi)
movq %mm2, %mm1 # mm1 <- 8(%esi)
movq (%edi), %mm2 # mm2 <- border
call .conv_hor_4_pixels # compute last vector
movq %mm0, 8(%esi) # store it
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 2,427
|
externals/pdp/system/mmx/pixel_cheby_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
.globl pixel_cheby_s16_3plus
.type pixel_cheby_s16_3plus,@function
# void pixel_cheby_s16(int *buf, int nb_8pixel_vectors, int order+1, short int *coefs)
# coefs are s2.13 fixed point (-4->4)
pixel_cheby_s16_3plus:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
push %edx
movl 8(%ebp), %esi # input array
movl 12(%ebp), %ecx # vector count
movl 16(%ebp), %eax # get order+1
shll $3, %eax
movl 20(%ebp), %edx
addl %eax, %edx # edx = coef endx address
# jmp skip
.align 16
.loop_cheby:
movl 20(%ebp), %edi # get coefs
movq (%esi), %mm0 # load 4 pixels from memory (mm0 = x)
pcmpeqw %mm2, %mm2
movq %mm0, %mm1 # mm1 (T_n-1) <- x
psrlw $1, %mm2 # mm2 (T_n-2) <- 1
movq (%edi), %mm4 # mm4 (acc) == a0
psraw $1, %mm4 # mm4 == a0/2
movq %mm0, %mm5 # mm5 (intermediate)
pmulhw 8(%edi), %mm5 # mm5 == (x * a1)/2
paddsw %mm5, %mm4 # acc = c0 + c1 x
addl $16, %edi
.loop_cheby_inner:
movq %mm1, %mm3 # mm3 == T_n-1
psraw $2, %mm2 # mm2 == T_n-2 / 4
pmulhw %mm0, %mm3 # mm3 == (2 x T_n-1) / 4
psubsw %mm2, %mm3 # mm3 == (2 x T_n-1 - T_n-2) / 4
paddsw %mm3, %mm3
paddsw %mm3, %mm3 # mm3 == T_n
movq %mm1, %mm2 # mm2 == new T_n-1
movq %mm3, %mm1 # mm3 == new T_n-2
pmulhw (%edi), %mm3 # mm3 = a_n * T_n / 2
paddsw %mm3, %mm4 # accumulate
addl $8, %edi
cmpl %edx, %edi
jne .loop_cheby_inner
paddsw %mm4, %mm4 # compensate for 0.125 factor
paddsw %mm4, %mm4
paddsw %mm4, %mm4
movq %mm4, (%esi) # store result in memory
addl $8, %esi # increment source/dest pointer
decl %ecx
jnz .loop_cheby # loop
skip:
emms
pop %edx
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 2,326
|
externals/pdp/system/mmx/pixel_gain.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
.globl pixel_gain
.type pixel_gain,@function
# mmx rgba pixel gain
# void asmtest(char *pixelarray, int32 nbpixels, int *rgba_gain)
# gains are 7.9 fixed point for rgba
pixel_gain:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 8(%ebp), %esi # pixel array offset
movl 12(%ebp), %ecx # nb of elements
movl 16(%ebp), %edi # int16[4] array of gains
prefetch (%esi)
emms
sarl $2, %ecx # process 4 pixels per loop iteration
jz .exit
movq (%edi), %mm7 # read gain array from memory
jmp .loop_gain
.align 16
.loop_gain:
prefetch 128(%esi)
movq (%esi), %mm5 # load pixel 1-2 from memory
movq 8(%esi), %mm6 # load pixel 3-4 from memory
pxor %mm0, %mm0 # zero mm0 - mm3
pxor %mm1, %mm1
pxor %mm2, %mm2
pxor %mm3, %mm3
punpcklbw %mm5, %mm0 # unpack 1st pixel into 8.8 bit ints
punpckhbw %mm5, %mm1 # unpack 2nd
punpcklbw %mm6, %mm2 # unpack 3rd
punpckhbw %mm6, %mm3 # unpack 4th
psrlw $0x1, %mm0 # shift right to clear sign bit 9.7
psrlw $0x1, %mm1
psrlw $0x1, %mm2
psrlw $0x1, %mm3
pmulhw %mm7, %mm0 # multiply 1st pixel 9.7 * 7.9 -> 16.0
pmulhw %mm7, %mm1 # multiply 2nd
pmulhw %mm7, %mm2 # multiply 3rd
pmulhw %mm7, %mm3 # multiply 4th
packuswb %mm1, %mm0 # pack & saturate to 8bit vector
movq %mm0, (%esi) # store result in memory
packuswb %mm3, %mm2 # pack & saturate to 8bit vector
movq %mm2, 8(%esi) # store result in memory
addl $16, %esi # increment source pointer
decl %ecx
jnz .loop_gain # loop
.exit:
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 1,422
|
externals/pdp/system/mmx/pixel_add_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
.globl pixel_add_s16
.type pixel_add_s16,@function
# simple add
# void pixel_add_s16(int *left, int *right, int nb_4pixel_vectors)
pixel_add_s16:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 8(%ebp), %edi # left array
movl 12(%ebp), %esi # right array
movl 16(%ebp), %ecx # pixel count
.align 16
.loop_mix:
# prefetch 128(%esi)
movq (%esi), %mm1 # load right 4 pixels from memory
movq (%edi), %mm0 # load 4 left pixels from memory
paddsw %mm1, %mm0 # mix
movq %mm0, (%edi)
addl $8, %esi
addl $8, %edi
decl %ecx
jnz .loop_mix # loop
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 3,922
|
externals/pdp/system/mmx/pixel_s1.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
# this file contains ops for binary image processing
# 8x8 bit tile encoded
# low byte = bottom row
# low bit = right column
# %mm7 = scratch reg for all macros
# ************ load mask *******************
# compute bit masks for rows and columns
# %mm7: scratch reg
# load mask top
.macro ldmt count reg
pcmpeqb \reg, \reg
psllq $(64-(\count<<3)), \reg
.endm
# load mask bottom
.macro ldmb count reg
pcmpeqb \reg, \reg
psrlq $(64-(\count<<3)), \reg
.endm
# load mask top and bottom
.macro ldmtb count regt regb
ldmb \count, \regb
ldmt \count, \regt
.endm
# load mask right
.macro ldmr count reg
pcmpeqb %mm7, %mm7
psrlw $(16-\count), %mm7
movq %mm7, \reg
psllq $8, %mm7
por %mm7, \reg
.endm
# load mask left
.macro ldml count reg
pcmpeqb %mm7, %mm7
psllw $(16-\count), %mm7
movq %mm7, \reg
psrlq $8, %mm7
por %mm7, \reg
.endm
# load mask left and right
.macro ldmlr count regl regr
pcmpeqb %mm7, %mm7
psllw $(16-\count), %mm7
movq %mm7, \regl
psrlq $8, %mm7
por %mm7, \regl
movq \regl, \regr
psrlq $(8-\count), \regr
.endm
# ************* shift square **********
# shifts a square in reg, fills with zeros
# shift square top
.macro sst count reg
psllq $(\count<<3), \reg
.endm
# shift square bottom
.macro ssb count reg
psrlq $(\count<<3), \reg
.endm
# not tested
# shift square left
.macro ssl count reg
movq \reg, %mm7
pcmpeqb \reg, \reg
psllw $(16-\count), \reg
psrlw $8, \reg
pandn %mm7, \reg
psllw $(\count), \reg
.endm
# shift square right
.macro ssr count reg
movq \reg, %mm7
pcmpeqb \reg, \reg
psrlw $(16-\count), \reg
psllw $8, \reg
pandn %mm7, \reg
psrlw $(\count), \reg
.endm
# ********** combine square *************
# combines 2 squares
# combine right
.macro csr count regr reg
ssl \count, \reg
ssr (8-\count), \regr
por \regr, \reg
.endm
# combine left
.macro csl count regl reg
ssr \count, \reg
ssl (8-\count), \regl
por \regl, \reg
.endm
# combine top
.macro cst count regt reg
ssb \count, \reg
sst (8-\count), \regt
por \regt, \reg
.endm
# combine bottom
.macro csb count regb reg
sst \count, \reg
ssb (8-\count), \regb
por \regb, \reg
.endm
# ********** load combine square *************
# loads combined square using mask
# load combined square left
# mask should be count bits set right (i.e. 0x01)
.macro lcsml count mask source sourcel dstreg
movq \mask, \dstreg
movq \mask, %mm7
pandn \source, \dstreg
pand \sourcel, %mm7
psrlq $(\count), \dstreg
psllq $(8-\count), %mm7
por %mm7, \dstreg
.endm
.globl pixel_test_s1
.type pixel_test_s1,@function
# simple add
# void pixel_add_s16(void *dest, void *source, int nb_squares, int spacing)
#
pixel_test_s1:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 8(%ebp), %edi # dest
movl 12(%ebp), %esi # source
movl 16(%ebp), %ecx # count
movl 20(%ebp), %edx # row distance
ldmr 1, %mm6
lcsml 1, %mm6, (%esi), 8(%esi), %mm0
movq %mm0, (%edi)
# movq (%esi), %mm0
# movq 8(%esi), %mm1
# csl 4, %mm1, %mm0
# movq %mm0, (%edi)
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 8,164
|
externals/pdp/system/mmx/pixel_biquad_dirI_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
# TODO MOVE TO DIRECT FORM II
# y[k] = b0 * x[k] + u1[k-1]
# u1[k] = b1 * x[k] + u2[k-1] - a1 * y[k]
# u2[k] = b2 * x[k] - a2 * y[k]
# input in register:
# %mm0-mm3: input 4x4 pixels {x0 x1 x2 x3}
# %esi: coef memory (a1, a2, b0, b1, b2)
# %edi: state memory (u1, u2)
# return in register:
# %mm0-mm4: 4x4 pixels result
.biquad_4x4_pixels:
.align 16
# prescale
movq -8(%esi), %mm4
pmulhw %mm4, %mm0
pmulhw %mm4, %mm1
pmulhw %mm4, %mm2
pmulhw %mm4, %mm3
psllw $1, %mm0
psllw $1, %mm1
psllw $1, %mm2
psllw $1, %mm3
# first vector
movq 0(%edi), %mm4 # mm4 <- u[-1]
movq 8(%edi), %mm5 # mm5 <- u[-2]
movq %mm4, %mm6
movq %mm5, %mm7
pmulhw 0(%esi), %mm6 # multiply by a1
pmulhw 8(%esi), %mm7 # multiply by a2
paddsw %mm6, %mm0 # accumulate
paddsw %mm7, %mm0 # accumulate
paddsw %mm0, %mm0 # scale by 2 (since all fixed point muls are x*y/2)
movq %mm0, %mm6 # mm6 <- u[0]
movq %mm4, %mm7 # mm7 <- u[-1]
pmulhw 16(%esi), %mm0 # multiply by b0
pmulhw 24(%esi), %mm4 # multiply by b1
pmulhw 32(%esi), %mm5 # multiply by b2
paddsw %mm4, %mm0 # accumulate
paddsw %mm5, %mm0 # accumulate
# mm0 is result 0
# second vector
movq %mm6, %mm4 # mm4 <- u[0]
movq %mm7, %mm5 # mm5 <- u[-1]
pmulhw 0(%esi), %mm6 # multiply by a1
pmulhw 8(%esi), %mm7 # multiply by a2
paddsw %mm6, %mm1 # accumulate
paddsw %mm7, %mm1 # accumulate
paddsw %mm1, %mm1 # scale by 2
movq %mm1, %mm6 # mm6 <- u[1]
movq %mm4, %mm7 # mm7 <- u[0]
pmulhw 16(%esi), %mm1 # multiply by b0
pmulhw 24(%esi), %mm4 # multiply by b1
pmulhw 32(%esi), %mm5 # multiply by b2
paddsw %mm4, %mm1 # accumulate
paddsw %mm5, %mm1 # accumulate
# mm1 is result 1
# third vector
movq %mm6, %mm4 # mm4 <- u[1]
movq %mm7, %mm5 # mm5 <- u[0]
pmulhw 0(%esi), %mm6 # multiply by a1
pmulhw 8(%esi), %mm7 # multiply by a2
paddsw %mm6, %mm2 # accumulate
paddsw %mm7, %mm2 # accumulate
paddsw %mm2, %mm2 # scale by 2
movq %mm2, %mm6 # mm6 <- u[2]
movq %mm4, %mm7 # mm7 <- u[1]
pmulhw 16(%esi), %mm2 # multiply by b0
pmulhw 24(%esi), %mm4 # multiply by b1
pmulhw 32(%esi), %mm5 # multiply by b2
paddsw %mm4, %mm2 # accumulate
paddsw %mm5, %mm2 # accumulate
# mm2 is result 2
# fourth vector
movq %mm6, %mm4 # mm4 <- u[2]
movq %mm7, %mm5 # mm5 <- u[1]
pmulhw 0(%esi), %mm6 # multiply by a1
pmulhw 8(%esi), %mm7 # multiply by a2
paddsw %mm6, %mm3 # accumulate
paddsw %mm7, %mm3 # accumulate
paddsw %mm3, %mm3 # scale by 2
movq %mm3, 0(%edi) # store u[3]
movq %mm4, 8(%edi) # store u[2]
pmulhw 16(%esi), %mm3 # multiply by b0
pmulhw 24(%esi), %mm4 # multiply by b1
pmulhw 32(%esi), %mm5 # multiply by b2
paddsw %mm4, %mm3 # accumulate
paddsw %mm5, %mm3 # accumulate
# mm3 is result 3
ret
# in order to use the 4 line parallel biquad routine on horizontal
# lines, we need to reorder (rotate or transpose) the matrix, since
# images are scanline encoded, and we want to work in parallell
# on 4 lines.
#
# since the 4 lines are independent, it doesnt matter in which order
# the the vector elements are present.
#
# this allows us to use the same routine for left->right and right->left
# processing.
#
# some comments on the non-abelean group of square isometries consisting of
# (I) identity
# (H) horizontal axis mirror
# (V) vertical axis mirror
# (T) transpose (diagonal axis mirror)
# (A) antitranspose (antidiagonal axis mirror)
# (R1) 90deg anticlockwize rotation
# (R2) 180deg rotation
# (R3) 90deg clockwize rotation
#
#
# we basicly have two options: (R1,R3) or (T,A)
# we opt for T and A because they are self inverting, which improves locality
#
# use antitranspose for right to left an transpose
# for left to right (little endian)
# antitranspose 4x4
# input
# %mm3 == {d0 d1 d2 d3}
# %mm2 == {c0 c1 c2 c3}
# %mm1 == {b0 b1 b2 b3}
# %mm0 == {a0 a1 a2 a3}
# output
# %mm3 == {a3 b3 c3 d3}
# %mm2 == {a2 b2 c2 d2}
# %mm1 == {a1 b1 c1 d1}
# %mm0 == {a0 b0 c0 d0}
.antitranspose_4x4:
.align 16
movq %mm3, %mm4
punpcklwd %mm1, %mm4 # mm4 <- {b2 d2 b3 d3}
movq %mm3, %mm5
punpckhwd %mm1, %mm5 # mm5 <- {b0 d0 b1 d1}
movq %mm2, %mm6
punpcklwd %mm0, %mm6 # mm6 <- {a2 c2 a3 c3}
movq %mm2, %mm7
punpckhwd %mm0, %mm7 # mm7 <- {a0 c0 a1 c1}
movq %mm4, %mm3
punpcklwd %mm6, %mm3 # mm3 <- {a3 b3 c3 d3}
movq %mm4, %mm2
punpckhwd %mm6, %mm2 # mm2 <- {a2 b2 c2 d2}
movq %mm5, %mm1
punpcklwd %mm7, %mm1 # mm1 <- {a1 b1 c1 d1}
movq %mm5, %mm0
punpckhwd %mm7, %mm0 # mm0 <- {a0 b0 c0 d0}
ret
# transpose 4x4
# input
# %mm3 == {d3 d2 d1 d0}
# %mm2 == {c3 c2 c1 c0}
# %mm1 == {b3 b2 b1 b0}
# %mm0 == {a3 a2 a1 a0}
# output
# %mm3 == {d3 c3 b3 a3}
# %mm2 == {d2 c2 b2 a2}
# %mm1 == {d1 c1 b1 a1}
# %mm0 == {d0 c0 b0 a0}
.transpose_4x4:
.align 16
movq %mm0, %mm4
punpcklwd %mm2, %mm4 # mm4 <- {c1 a1 c0 a0}
movq %mm0, %mm5
punpckhwd %mm2, %mm5 # mm5 <- {c3 a3 c2 a2}
movq %mm1, %mm6
punpcklwd %mm3, %mm6 # mm6 <- {d1 b1 d0 b0}
movq %mm1, %mm7
punpckhwd %mm3, %mm7 # mm7 <- {d3 b3 d2 b2}
movq %mm4, %mm0
punpcklwd %mm6, %mm0 # mm0 <- {d0 c0 b0 a0}
movq %mm4, %mm1
punpckhwd %mm6, %mm1 # mm1 <- {d1 c1 b1 a1}
movq %mm5, %mm2
punpcklwd %mm7, %mm2 # mm2 <- {d2 c2 b2 a2}
movq %mm5, %mm3
punpckhwd %mm7, %mm3 # mm3 <- {d3 c3 b3 a3}
ret
.globl pixel_biquad_vertb_s16
.type pixel_biquad_vertb_s16,@function
# pixel_biquad_vertbr_s16(char *pixel_array, int nb_rows, int linewidth, short int coef[20], short int state[8])
pixel_biquad_vertb_s16:
pushl %ebp
movl %esp, %ebp
push %ebx
push %esi
push %edi
movl 8(%ebp), %ebx # pixel array offset
movl 12(%ebp), %ecx # nb of 4x4 pixblocks
movl 16(%ebp), %edx # line with
movl 20(%ebp), %esi # coefs
movl 24(%ebp), %edi # state
shll $1, %edx # short int addressing
movl %edx, %eax
shll $1, %eax
addl %edx, %eax # eax = 3 * edx
.align 16
.biquad_vertb_line_loop:
movq (%ebx), %mm0
movq (%ebx,%edx,1), %mm1
movq (%ebx,%edx,2), %mm2
movq (%ebx,%eax,1), %mm3
call .biquad_4x4_pixels
movq %mm0, (%ebx)
movq %mm1, (%ebx,%edx,1)
movq %mm2, (%ebx,%edx,2)
movq %mm3, (%ebx,%eax,1)
addl %edx, %ebx
addl %eax, %ebx
decl %ecx
jnz .biquad_vertb_line_loop
emms
pop %edi
pop %esi
pop %ebx
leave
ret
.globl pixel_biquad_horlr_s16
.type pixel_biquad_horlr_s16,@function
# pixel_biquad_hor_s16(char *pixel_array, int nb_rows, int linewidth, short int coef[20], short int state[8])
pixel_biquad_horlr_s16:
pushl %ebp
movl %esp, %ebp
push %ebx
push %esi
push %edi
movl 8(%ebp), %ebx # pixel array offset
movl 12(%ebp), %ecx # nb of 4x4 pixblocks
movl 16(%ebp), %edx # line with
movl 20(%ebp), %esi # coefs
movl 24(%ebp), %edi # state
shll $1, %edx # short int addressing
movl %edx, %eax
shll $1, %eax
addl %edx, %eax # eax = 3 * edx
.align 16
.biquad_horlr_line_loop:
movq (%ebx), %mm0
movq (%ebx,%edx,1), %mm1
movq (%ebx,%edx,2), %mm2
movq (%ebx,%eax,1), %mm3
call .transpose_4x4
call .biquad_4x4_pixels
call .transpose_4x4
movq %mm0, (%ebx)
movq %mm1, (%ebx,%edx,1)
movq %mm2, (%ebx,%edx,2)
movq %mm3, (%ebx,%eax,1)
addl $8, %ebx
decl %ecx
jnz .biquad_horlr_line_loop
emms
pop %edi
pop %esi
pop %ebx
leave
ret
|
agraef/purr-data
| 2,479
|
externals/pdp/system/mmx/pixel_randmix_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
.globl pixel_randmix_s16
.type pixel_randmix_s16,@function
# mmx rgba pixel gain
# void pixel_randmix_s16(int *left, int *right, int nb_4pixel_vectors, short int random_seed[4], short int threshold[4])
pixel_randmix_s16:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 20(%ebp), %edi # int16[4] array of random seeds
movq (%edi), %mm6
movl 24(%ebp), %edi # int16[4] array of thresholds
movq (%edi), %mm7
movl 8(%ebp), %edi # left array
movl 12(%ebp), %esi # right array
movl 16(%ebp), %ecx # pixel count
pcmpeqw %mm3, %mm3
psrlw $15, %mm3 # get bit mask 4 times 0x0001
.align 16
.loop_randmix:
# prefetch 128(%esi)
movq (%esi), %mm1 # load right 4 pixels from memory
movq (%edi), %mm0 # load 4 left pixels from memory
movq %mm6, %mm2 # get random vector
pcmpgtw %mm7, %mm2 # compare random vector with threshold
movq %mm2, %mm5
pand %mm0, %mm2 # get left array's components
pandn %mm1, %mm5 # get right array's components
por %mm2, %mm5
movq %mm5, (%edi) # store pixels
movq %mm6, %mm4 # get random vector
psrlw $15, %mm4 # get first component
movq %mm6, %mm5
psrlw $14, %mm5 # get second component
pxor %mm5, %mm4
movq %mm6, %mm5
psrlw $12, %mm5 # get third component
pxor %mm5, %mm4
movq %mm6, %mm5
psrlw $3, %mm5 # get forth component
pxor %mm5, %mm4
psllw $1, %mm6 # shift left original random vector
pand %mm3, %mm4 # isolate new bit
por %mm4, %mm6 # combine into new random vector
addl $8, %esi
addl $8, %edi
decl %ecx
jnz .loop_randmix # loop
movl 20(%ebp), %edi # int16[4] array of random seeds
movq %mm6, (%edi) # store random seeds
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 1,852
|
externals/pdp/system/mmx/pixel_gain_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
.globl pixel_gain_s16
.type pixel_gain_s16,@function
# gain is integer, shift count is down
# void pixel_gain_s16(int *buf, int nb_8pixel_vectors, short int gain[4], unsigned long long *shift)
pixel_gain_s16:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 20(%ebp), %edi
movq (%edi), %mm6 # get shift vector
movl 16(%ebp), %edi
movq (%edi), %mm7 # get gain vector
movl 8(%ebp), %esi # input array
movl 12(%ebp), %ecx # pixel count
.align 16
.loop_gain:
movq (%esi), %mm0 # load 4 pixels from memory
movq %mm0, %mm1
pmulhw %mm7, %mm1 # apply gain (s15.0) fixed point, high word
pmullw %mm7, %mm0 # low word
movq %mm0, %mm2 # copy
movq %mm1, %mm3
punpcklwd %mm1, %mm0 # unpack lsw components
punpckhwd %mm3, %mm2 # unpack msw components
psrad %mm6, %mm0 # apply signed shift
psrad %mm6, %mm2
packssdw %mm2, %mm0 # pack result & saturate
movq %mm0, (%esi) # store result
addl $8, %esi # increment source pointer
decl %ecx
jnz .loop_gain # loop
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 7,373
|
externals/pdp/system/mmx/pixel_resample_s16.s
|
#interpolation data:
#* 4 vectors: neighbourhood for samples (TL, TR, BL, BR)
#* 2 vectors: fractional part (unsigned)
#* 2 vectors: addresses of pixel blocks
#coord conversion data:
#1 vector: 32bit splatted address
#1 vector: 16bit splatted w-1
#1 vector: 16bit splatted h-1
#1 vector: 16bit splatted w (reuse w-1 with add?)
#1 dword: 32 bit line offset
#coord generation data: several vectors for parameter update stuff..
#coordinate systems: 16 bit virtual coordinates (signed, center relative)
#* 2 vectors: virtual coordinates
#(evt tussenstap + conversie naar 16 bit virtual)
#step 1: generate virtual coords
#step 2: virtual coords -> block adresses + fractional adresses
#* mulhigh: real coords (x,y) (center relative)
#* add center -> unsigned (top left relative)
#* mullow: fractional part (x_frac, y_frac)
#* mulhigh, mullow, pack 32bit: y_offset
#* pack 32bit: x_offset
#* add, shift, add start address: real addresses
#step3: data fetch using generated addresses:
# this step would be much simpler in 4x16bit rgba. life's a bitch..
#step4: billinear interpolation
#stat5: store
# this can be simplified by doing 32 bit unaligned moves
# and vector unpacking on the data
# cooked image data structure
# pixel environment temp storage
TL1 = 0x00
TL2 = 0x02
TL3 = 0x04
TL4 = 0x06
TR1 = 0x08
TR2 = 0x0A
TR3 = 0x0C
TR4 = 0x0E
BL1 = 0x10
BL2 = 0x12
BL3 = 0x14
BL4 = 0x16
BR1 = 0x18
BR2 = 0x1A
BR3 = 0x1C
BR4 = 0x1E
# addresses of pixel blocks
ADDRESS1 = 0x20
ADDRESS2 = 0x24
ADDRESS3 = 0x28
ADDRESS4 = 0x2C
# second env + address buffer (testing: not used)
SECONDBUFFER = 0x30
# 32bit splatted bitmap address
V2PLANEADDRESS = 0x60
# 16bit splatted image constants
V4TWOWIDTHM1 = 0x68
V4TWOHEIGHTM1 = 0x70
V4LINEOFFSET = 0x78
# data struct size
RESAMPLEDATASIZE = 0x80
# interpolation routine
# input: %mm0, %mm1 4 x 16bit unsigned top left relative virtual x and y coordinates
# %esi: temp & algo data structure
getpixelsbilin: psrlw $1, %mm0 # convert to range 0->0x7fff [0,0.5[
psrlw $1, %mm1
movq %mm0, %mm2
movq %mm1, %mm3
movq V4TWOWIDTHM1(%esi), %mm4 # 2 * (width - 1)
movq V4TWOHEIGHTM1(%esi), %mm5 # 2 * (height - 1)
pmulhw %mm5, %mm3 # mm3 == y coord (topleft relative)
pmulhw %mm4, %mm2 # mm2 == x coord (topleft relative)
pmullw %mm5, %mm1 # mm1 == y frac (unsigned)
pmullw %mm4, %mm0 # mm0 == x frac (unsigned)
movq %mm3, %mm5 # copy y coord
pmullw V4LINEOFFSET(%esi), %mm3 # low part of line offset
pmulhw V4LINEOFFSET(%esi), %mm5 # high part of line offset
movq %mm2, %mm7 # copy x coord vector
pxor %mm4, %mm4
punpcklwd %mm4, %mm2 # low part in %mm2
punpckhwd %mm4, %mm7 # hight part in %mm7
movq %mm3, %mm6 # copy
punpcklwd %mm5, %mm3 # unpack low part in %mm3
punpckhwd %mm5, %mm6 # high part int %mm6
paddd %mm2, %mm3
paddd %mm7, %mm6
pslld $1, %mm3 # convert to word adresses
pslld $1, %mm6
paddd V2PLANEADDRESS(%esi), %mm3 # add pixel plane address
paddd V2PLANEADDRESS(%esi), %mm6
movq %mm3, ADDRESS1(%esi) # store adresses
movq %mm6, ADDRESS3(%esi)
pcmpeqw %mm2, %mm2 # all ones
movq %mm0, %mm4 # copy x frac
movq %mm1, %mm5 # copy y frac
pxor %mm2, %mm4 # compute compliment (approx negative)
pxor %mm2, %mm5
psrlw $1, %mm0 # shift right (0.5 * (frac x)
psrlw $1, %mm1 # shift right (0.5 * (frac y)
psrlw $1, %mm4 # shift right (0.5 * (1 - frac x)
psrlw $1, %mm5 # shift right (0.5 * (1 - frac y)
movq %mm0, %mm2 # copy of frac x
movq %mm4, %mm3 # copy of (1-frac x)
# fetch data
#jmp skipfetch # seems the fetch is the real killer. try to optimize this
# using 32 bit accesses & shifts
# the src image data struct is padded to the cooked data struct
movl RESAMPLEDATASIZE(%esi), %edi
shll $1, %edi
movl ADDRESS1(%esi), %ecx
movl ADDRESS2(%esi), %edx
movw (%ecx), %ax
movw (%edx), %bx
movw %ax, TL1(%esi)
movw %bx, TL2(%esi)
movw 2(%ecx), %ax
movw 2(%edx), %bx
movw %ax, TR1(%esi)
movw %bx, TR2(%esi)
addl %edi, %ecx
addl %edi, %edx
movw (%ecx), %ax
movw (%edx), %bx
movw %ax, BL1(%esi)
movw %bx, BL2(%esi)
movw 2(%ecx), %ax
movw 2(%edx), %bx
movw %ax, BR1(%esi)
movw %bx, BR2(%esi)
movl ADDRESS3(%esi), %ecx
movl ADDRESS4(%esi), %edx
movw (%ecx), %ax
movw (%edx), %bx
movw %ax, TL3(%esi)
movw %bx, TL4(%esi)
movw 2(%ecx), %ax
movw 2(%edx), %bx
movw %ax, TR3(%esi)
movw %bx, TR4(%esi)
addl %edi, %ecx
addl %edi, %edx
movw (%ecx), %ax
movw (%edx), %bx
movw %ax, BL3(%esi)
movw %bx, BL4(%esi)
movw 2(%ecx), %ax
movw 2(%edx), %bx
movw %ax, BR3(%esi)
movw %bx, BR4(%esi)
skipfetch:
pmulhw TL1(%esi), %mm4 # bilin interpolation
pmulhw TR1(%esi), %mm0
pmulhw BL1(%esi), %mm3
pmulhw BR1(%esi), %mm2
paddw %mm4, %mm0
paddw %mm3, %mm2
pmulhw %mm5, %mm0
pmulhw %mm1, %mm2
paddw %mm2, %mm0
psllw $2, %mm0 # compensate for gain reduction
ret
// linear mapping data struct
ROWSTATEX = 0x0
ROWSTATEY = 0x8
COLSTATEX = 0x10
COLSTATEY = 0x18
ROWINCX = 0x20
ROWINCY = 0x28
COLINCX = 0x30
COLINCY = 0x38
// image data struct
LINEOFFSET = 0x0
IMAGEADDRESS = 0x4
WIDTH = 0x8
HEIGHT = 0xC
IMAGEDATASIZE = 0x10
# pixel_resample_linmap_s16(void *x)
.globl pixel_resample_linmap_s16
.type pixel_resample_linmap_s16,@function
SOURCEIMAGE = RESAMPLEDATASIZE
DESTIMAGE = SOURCEIMAGE + IMAGEDATASIZE
LINMAPDATA = DESTIMAGE + IMAGEDATASIZE
pixel_resample_linmap_s16:
pushl %ebp
movl %esp, %ebp
pushl %esi
pushl %edi
pushl %ebx
movl 8(%ebp), %esi # get data struct
movl DESTIMAGE+HEIGHT(%esi), %edx # image height
movl DESTIMAGE+IMAGEADDRESS(%esi), %edi # dest image address
movl DESTIMAGE+WIDTH(%esi), %ecx # image width
shrl $2, %ecx # vector count
.align 16
linmap_looprow:
movq LINMAPDATA+ROWSTATEX(%esi), %mm0 # get current coordinates
movq LINMAPDATA+ROWSTATEY(%esi), %mm1
linmap_loopcol:
movq %mm0, %mm4 # copy
movq %mm1, %mm5
paddd LINMAPDATA+ROWINCX(%esi), %mm4 # increment
paddd LINMAPDATA+ROWINCY(%esi), %mm5
movq %mm4, %mm6 # copy
movq %mm5, %mm7
paddd LINMAPDATA+ROWINCX(%esi), %mm6 # increment
paddd LINMAPDATA+ROWINCY(%esi), %mm7
movq %mm6, LINMAPDATA+ROWSTATEX(%esi) # store next state
movq %mm7, LINMAPDATA+ROWSTATEY(%esi)
psrad $16, %mm0 # round to 16 bit
psrad $16, %mm1
psrad $16, %mm4
psrad $16, %mm5
packssdw %mm4, %mm0 # pack new coordinates
packssdw %mm5, %mm1
push %ecx
push %edx
push %edi
call getpixelsbilin # do interpolation
pop %edi
pop %edx
pop %ecx
movq %mm0, (%edi) # store 4 pixels
addl $0x8, %edi # point to next 4 pixels
decl %ecx # dec row counter
jnz linmap_looprow
movq LINMAPDATA+COLSTATEX(%esi), %mm0 # get column state vector
movq LINMAPDATA+COLSTATEY(%esi), %mm1
movl DESTIMAGE+WIDTH(%esi), %ecx # image width
shrl $2, %ecx # vector count
paddd LINMAPDATA+COLINCX(%esi), %mm0 # increment
paddd LINMAPDATA+COLINCY(%esi), %mm1
movq %mm0, LINMAPDATA+COLSTATEX(%esi) # store
movq %mm1, LINMAPDATA+COLSTATEY(%esi)
decl %edx # dec column counter
jnz linmap_loopcol
emms
popl %ebx
popl %edi
popl %esi
leave
ret
|
agraef/purr-data
| 1,470
|
externals/pdp/system/mmx/pixel_mul_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
.globl pixel_mul_s16
.type pixel_mul_s16,@function
# simple add
# void pixel_mul_s16(int *left, int *right, int nb_4pixel_vectors)
pixel_mul_s16:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 8(%ebp), %edi # left array
movl 12(%ebp), %esi # right array
movl 16(%ebp), %ecx # pixel count
.align 16
.loop_mix:
# prefetch 128(%esi)
movq (%esi), %mm1 # load right 4 pixels from memory
movq (%edi), %mm0 # load 4 left pixels from memory
pmulhw %mm1, %mm0 # mul
psllw $1, %mm0 # fixed point shift correction
movq %mm0, (%edi)
addl $8, %esi
addl $8, %edi
decl %ecx
jnz .loop_mix # loop
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 3,101
|
externals/pdp/system/mmx/pixel_pack_s16u8.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
.globl pixel_pack_s16u8_y
.type pixel_pack_s16u8_y,@function
# mmx rgba pixel gain
# void pixel_pack_s16u8_y(int *input, int *output, int nb_8pixel_vectors)
pixel_pack_s16u8_y:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
# movl 20(%ebp), %edi # int16[4] array of gains
# movq (%edi), %mm7 # get gain array
# psllw $1, %mm7 # adjust for shifted sign bit
movl 8(%ebp), %esi # input array
movl 12(%ebp), %edi # output array
movl 16(%ebp), %ecx # pixel count
pxor %mm6, %mm6
.align 16
.loop_pack_y:
# prefetch 128(%esi)
movq (%esi), %mm0 # load 4 pixels from memory
# pmulhw %mm7, %mm0 # apply gain
movq 8(%esi), %mm1 # load 4 pixels from memory
# pmulhw %mm7, %mm1 # apply gain
# movq %mm0, %mm2
# pcmpgtw %mm6, %mm2 # mm2 > 0 ? 0xffff : 0
# pand %mm2, %mm0
# movq %mm1, %mm3
# pcmpgtw %mm6, %mm3 # mm3 > 0 ? 0xffff : 0
# pand %mm3, %mm1
# psllw $1, %mm0 # shift out sign bit
# psllw $1, %mm1 # shift out sign bit
psraw $7, %mm0 # shift to lsb
psraw $7, %mm1 # shift to lsb
packuswb %mm1, %mm0 # pack & saturate to 8bit vector
movq %mm0, (%edi) # store result in memory
addl $16, %esi # increment source pointer
addl $8, %edi # increment dest pointer
decl %ecx
jnz .loop_pack_y # loop
emms
pop %edi
pop %esi
leave
ret
.globl pixel_pack_s16u8_uv
.type pixel_pack_s16u8_uv,@function
pixel_pack_s16u8_uv:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
# movl 20(%ebp), %edi # int16[4] array of gains
# movq (%edi), %mm7 # get gain array
movl 8(%ebp), %esi # pixel array offset
movl 12(%ebp), %edi # nb of elements
movl 16(%ebp), %ecx # pixel count
pcmpeqw %mm6, %mm6
psllw $15, %mm6
movq %mm6, %mm5
psrlw $8, %mm5
por %mm5, %mm6 # mm6 <- 8 times 0x80
.align 16
.loop_pack_uv:
# prefetch 128(%esi)
movq (%esi), %mm0 # load 4 pixels from memory
# pmulhw %mm7, %mm0 # apply gain
movq 8(%esi), %mm1 # load 4 pixels from memory
# pmulhw %mm7, %mm1 # apply gain
psraw $8, %mm0 # shift to msb
psraw $8, %mm1
packsswb %mm1, %mm0 # pack & saturate to 8bit vector
pxor %mm6, %mm0 # flip sign bits
movq %mm0, (%edi) # store result in memory
addl $16, %esi # increment source pointer
addl $8, %edi # increment dest pointer
decl %ecx
jnz .loop_pack_uv # loop
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 9,964
|
externals/pdp/system/mmx/pixel_biquad_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
# DIRECT FORM II BIQUAD
#
# y[k] = b0 * x[k] + u1[k-1]
# u1[k] = b1 * x[k] + u2[k-1] - a1 * y[k]
# u2[k] = b2 * x[k] - a2 * y[k]
# MACRO: df2 <reg>
#
# computes a direct form 2 biquad
# does not use {mm0-mm3}\<inreg>
#
# input: <reg> == input
# %mm4 == state 1
# %mm5 == state 2
# (%esi) == biquad coefs (-a1 -a2 b0 b1 b2) in s1.14
# output: <reg> == output
# %mm4 == state 1
# %mm5 == state 2
.macro df2 reg
movq \reg, %mm6 # mm6 == x[k]
movq \reg, %mm7 # mm7 == x[k]
pmulhw 16(%esi), %mm6 # mm6 == x[k] * b0
pmulhw 24(%esi), %mm7 # mm7 == x[k] * b1
paddw %mm4, %mm6 # mm6 == x[k] * b0 + u1[k-1] == y[k]
paddw %mm5, %mm7 # mm7 == x[k] * b1 + u2[k-1]
paddsw %mm6, %mm6 # compensate for mul = x*y/4 (coefs are s1.14 fixed point)
paddsw %mm6, %mm6 # paddsw ensures saturation
movq \reg, %mm5 # mm5 == x[k]
movq %mm6, %mm4 # mm4 == y[k]
movq %mm6, \reg # reg == y[k] --------------------
pmulhw 0(%esi), %mm4 # mm4 == y[k] * (-a1)
pmulhw 8(%esi), %mm6 # mm6 == y[k] * (-a2)
pmulhw 32(%esi), %mm5 # mm5 == x[k] * b2
paddw %mm7, %mm4 # mm4 == u1[k] --------------------
paddw %mm6, %mm5 # mm5 == u2[k] --------------------
.endm
# input in register:
# %mm0-mm3: input 4x4 pixels {x0 x1 x2 x3}
# %esi: coef memory (-a1, -a2, b0, b1, b2) in s1.14
# %edi: state memory (u1, u2)
# return in register:
# %mm0-mm4: 4x4 pixels result
.macro biquad_4x4_pixels
.align 16
movq 0(%edi), %mm4 # get state
movq 8(%edi), %mm5
df2 %mm0 # compute 4 biquads
df2 %mm1
df2 %mm2
df2 %mm3
movq %mm4, 0(%edi) # store state
movq %mm5, 8(%edi)
.endm
# in order to use the 4 line parallel biquad routine on horizontal
# lines, we need to reorder (rotate or transpose) the matrix, since
# images are scanline encoded, and we want to work in parallell
# on 4 lines.
#
# since the 4 lines are independent, it doesnt matter in which order
# the the vector elements are present.
#
# this allows us to use the same routine for left->right and right->left
# processing.
#
# some comments on the non-abelean group of square isometries consisting of
# (I) identity
# (H) horizontal axis mirror
# (V) vertical axis mirror
# (T) transpose (diagonal axis mirror)
# (A) antitranspose (antidiagonal axis mirror)
# (R1) 90deg anticlockwize rotation
# (R2) 180deg rotation
# (R3) 90deg clockwize rotation
#
#
# we basicly have two options: (R1,R3) or (T,A)
# we opt for T and A because they are self inverting, which improves locality
#
# use antitranspose for right to left an transpose
# for left to right (little endian)
# antitranspose 4x4
# input
# %mm3 == {d0 d1 d2 d3}
# %mm2 == {c0 c1 c2 c3}
# %mm1 == {b0 b1 b2 b3}
# %mm0 == {a0 a1 a2 a3}
# output
# %mm3 == {a3 b3 c3 d3}
# %mm2 == {a2 b2 c2 d2}
# %mm1 == {a1 b1 c1 d1}
# %mm0 == {a0 b0 c0 d0}
.macro antitranspose_4x4
movq %mm3, %mm4
punpcklwd %mm1, %mm4 # mm4 <- {b2 d2 b3 d3}
movq %mm3, %mm5
punpckhwd %mm1, %mm5 # mm5 <- {b0 d0 b1 d1}
movq %mm2, %mm6
punpcklwd %mm0, %mm6 # mm6 <- {a2 c2 a3 c3}
movq %mm2, %mm7
punpckhwd %mm0, %mm7 # mm7 <- {a0 c0 a1 c1}
movq %mm4, %mm3
punpcklwd %mm6, %mm3 # mm3 <- {a3 b3 c3 d3}
movq %mm4, %mm2
punpckhwd %mm6, %mm2 # mm2 <- {a2 b2 c2 d2}
movq %mm5, %mm1
punpcklwd %mm7, %mm1 # mm1 <- {a1 b1 c1 d1}
movq %mm5, %mm0
punpckhwd %mm7, %mm0 # mm0 <- {a0 b0 c0 d0}
.endm
# transpose 4x4
# input
# %mm3 == {d3 d2 d1 d0}
# %mm2 == {c3 c2 c1 c0}
# %mm1 == {b3 b2 b1 b0}
# %mm0 == {a3 a2 a1 a0}
# output
# %mm3 == {d3 c3 b3 a3}
# %mm2 == {d2 c2 b2 a2}
# %mm1 == {d1 c1 b1 a1}
# %mm0 == {d0 c0 b0 a0}
.macro transpose_4x4
movq %mm0, %mm4
punpcklwd %mm2, %mm4 # mm4 <- {c1 a1 c0 a0}
movq %mm0, %mm5
punpckhwd %mm2, %mm5 # mm5 <- {c3 a3 c2 a2}
movq %mm1, %mm6
punpcklwd %mm3, %mm6 # mm6 <- {d1 b1 d0 b0}
movq %mm1, %mm7
punpckhwd %mm3, %mm7 # mm7 <- {d3 b3 d2 b2}
movq %mm4, %mm0
punpcklwd %mm6, %mm0 # mm0 <- {d0 c0 b0 a0}
movq %mm4, %mm1
punpckhwd %mm6, %mm1 # mm1 <- {d1 c1 b1 a1}
movq %mm5, %mm2
punpcklwd %mm7, %mm2 # mm2 <- {d2 c2 b2 a2}
movq %mm5, %mm3
punpckhwd %mm7, %mm3 # mm3 <- {d3 c3 b3 a3}
.endm
.globl pixel_biquad_vertb_s16
.type pixel_biquad_vertb_s16,@function
# pixel_biquad_vertbr_s16(char *pixel_array, int nb_rows, int linewidth, short int coef[20], short int state[8])
pixel_biquad_vertb_s16:
pushl %ebp
movl %esp, %ebp
push %ebx
push %esi
push %edi
movl 8(%ebp), %ebx # pixel array offset
movl 12(%ebp), %ecx # nb of 4x4 pixblocks
movl 16(%ebp), %edx # line with
movl 20(%ebp), %esi # coefs
movl 24(%ebp), %edi # state
shll $1, %edx # short int addressing
movl %edx, %eax
shll $1, %eax
addl %edx, %eax # eax = 3 * edx
.align 16
.biquad_vertb_line_loop:
movq (%ebx), %mm0
movq (%ebx,%edx,1), %mm1
movq (%ebx,%edx,2), %mm2
movq (%ebx,%eax,1), %mm3
biquad_4x4_pixels
movq %mm0, (%ebx)
movq %mm1, (%ebx,%edx,1)
movq %mm2, (%ebx,%edx,2)
movq %mm3, (%ebx,%eax,1)
addl %edx, %ebx
addl %eax, %ebx
decl %ecx
jnz .biquad_vertb_line_loop
emms
pop %edi
pop %esi
pop %ebx
leave
ret
.globl pixel_biquad_verbt_s16
.type pixel_biquad_verbt_s16,@function
# pixel_biquad_vertbt_s16(char *pixel_array, int nb_rows, int linewidth, short int coef[20], short int state[8])
pixel_biquad_verbt_s16:
pushl %ebp
movl %esp, %ebp
push %ebx
push %esi
push %edi
movl 8(%ebp), %ebx # pixel array offset
movl 12(%ebp), %ecx # nb of 4x4 pixblocks
movl 16(%ebp), %eax # line with
shll $3, %eax # 4 line byte spacing
decl %ecx
mul %ecx
incl %ecx
addl %eax, %ebx # ebx points to last pixblock
movl 16(%ebp), %edx # line with
movl 20(%ebp), %esi # coefs
movl 24(%ebp), %edi # state
shll $1, %edx # short int addressing
movl %edx, %eax
shll $1, %eax
addl %edx, %eax # eax = 3 * edx
.align 16
.biquad_verbt_line_loop:
movq (%ebx), %mm3
movq (%ebx,%edx,1), %mm2
movq (%ebx,%edx,2), %mm1
movq (%ebx,%eax,1), %mm0
biquad_4x4_pixels
movq %mm3, (%ebx)
movq %mm2, (%ebx,%edx,1)
movq %mm1, (%ebx,%edx,2)
movq %mm0, (%ebx,%eax,1)
subl %edx, %ebx
subl %eax, %ebx
decl %ecx
jnz .biquad_verbt_line_loop
emms
pop %edi
pop %esi
pop %ebx
leave
ret
.globl pixel_biquad_horlr_s16
.type pixel_biquad_horlr_s16,@function
# pixel_biquad_hor_s16(char *pixel_array, int nb_rows, int linewidth, short int coef[20], short int state[8])
pixel_biquad_horlr_s16:
pushl %ebp
movl %esp, %ebp
push %ebx
push %esi
push %edi
movl 8(%ebp), %ebx # pixel array offset
movl 12(%ebp), %ecx # nb of 4x4 pixblocks
movl 16(%ebp), %edx # line with
movl 20(%ebp), %esi # coefs
movl 24(%ebp), %edi # state
shll $1, %edx # short int addressing
movl %edx, %eax
shll $1, %eax
addl %edx, %eax # eax = 3 * edx
.align 16
.biquad_horlr_line_loop:
movq (%ebx), %mm0
movq (%ebx,%edx,1), %mm1
movq (%ebx,%edx,2), %mm2
movq (%ebx,%eax,1), %mm3
transpose_4x4
biquad_4x4_pixels
transpose_4x4
movq %mm0, (%ebx)
movq %mm1, (%ebx,%edx,1)
movq %mm2, (%ebx,%edx,2)
movq %mm3, (%ebx,%eax,1)
addl $8, %ebx
decl %ecx
jnz .biquad_horlr_line_loop
emms
pop %edi
pop %esi
pop %ebx
leave
ret
.globl pixel_biquad_horrl_s16
.type pixel_biquad_horrl_s16,@function
# pixel_biquad_horrl_s16(char *pixel_array, int nb_rows, int linewidth, short int coef[20], short int state[8])
pixel_biquad_horrl_s16:
pushl %ebp
movl %esp, %ebp
push %ebx
push %esi
push %edi
movl 8(%ebp), %ebx # pixel array offset
movl 12(%ebp), %ecx # nb of 4x4 pixblocks
movl 16(%ebp), %edx # line with
movl %ecx, %eax
decl %eax
shll $3, %eax
addl %eax, %ebx # ebx points to last pixblock
movl 20(%ebp), %esi # coefs
movl 24(%ebp), %edi # state
shll $1, %edx # short int addressing
movl %edx, %eax
shll $1, %eax
addl %edx, %eax # eax = 3 * edx
.align 16
.biquad_horrl_line_loop:
movq (%ebx), %mm0
movq (%ebx,%edx,1), %mm1
movq (%ebx,%edx,2), %mm2
movq (%ebx,%eax,1), %mm3
antitranspose_4x4
biquad_4x4_pixels
antitranspose_4x4
movq %mm0, (%ebx)
movq %mm1, (%ebx,%edx,1)
movq %mm2, (%ebx,%edx,2)
movq %mm3, (%ebx,%eax,1)
subl $8, %ebx
decl %ecx
jnz .biquad_horrl_line_loop
emms
pop %edi
pop %esi
pop %ebx
leave
ret
.globl pixel_biquad_time_s16
.type pixel_biquad_time_s16,@function
# pixel_biquad_time_s16(short int *pixel_array, short int *s1, short int *s2, short int *coefs, int nb_4_pix_vectors)
pixel_biquad_time_s16:
pushl %ebp
movl %esp, %ebp
push %ebx
push %esi
push %edi
movl 8(%ebp), %ebx # pixel array offset
movl 12(%ebp), %edx # state 1 array
movl 16(%ebp), %edi # state 2 array
movl 20(%ebp), %esi # coefs
movl 24(%ebp), %ecx # nb of 4 pixel vectors
.align 16
.biquad_time_loop:
movq (%ebx), %mm0 # get input
movq (%edx), %mm4 # get state 1
movq (%edi), %mm5 # get state 2
df2 %mm0 # compute direct form 2
movq %mm0, (%ebx) # write output
movq %mm5, (%edi) # write state 2
movq %mm4, (%edx) # write state 1
addl $8, %ebx
addl $8, %edi
addl $8, %edx
decl %ecx
jnz .biquad_time_loop
emms
pop %edi
pop %esi
pop %ebx
leave
ret
|
agraef/purr-data
| 7,161
|
externals/pdp/system/mmx/pixel_cascade_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
# TODO: COUPLED CASCADE SECOND ORDER SECTION
#
# s1[k] = ar * s1[k-1] + ai * s2[k-1] + x[k]
# s2[k] = ar * s2[k-1] - ai * s1[k-1]
# y[k] = c0 * x[k] + c1 * s1[k-1] + c2 * s2[k-1]
# MACRO: df2
#
# computes a coupled cascade
#
# input: %mm0 == input
# %mm1 == state 1
# %mm2 == state 2
# (%esi) == cascade coefs (ar ai c0 c1 c2) in s0.15
# output: %mm0 == output
# %mm1 == state 1
# %mm2 == state 2
.macro coupled
pmovq %mm1, %mm3 # mm3 == s1[k-1]
pmovq %mm1, %mm4 # mm4 == s1[k-1]
pmovq %mm2, %mm5 # mm5 == s2[k-1]
pmovq %mm2, %mm6 # mm5 == s2[k-1]
pmulhw (%esi), %mm1 # mm1 == s1[k-1] * ar
pmulhw 8(%esi), %mm3 # mm3 == s1[k-1] * ai
pmulhw 24(%esi), %mm4 # mm4 == s1[k-1] * c1
pmulhw (%esi), %mm2 # mm2 == s2[k-1] * ar
pmulhw 8(%esi), %mm5 # mm5 == s2[k-1] * ai
pmulhw 32(%esi), %mm6 # mm6 == s2[k-1] * c2
paddw %mm5, %mm1 # mm1 == s1[k-1] * ar + s2[k-1] * ai
psubw %mm3, %mm2 # mm2 == s2[k-1] * ar - s1[k-1] * ai == s2[k]
paddw %mm0, %mm1 # mm1 == s1[k]
pmulhw 16(%esi), %mm0 # mm0 == x[k] * c0
paddw %mm6, %mm4 # mm4 == s1[k-1] * c1 + s2[k-1] * c2
paddw %mm4, %mm0 # mm0 == y[k]
.endm
# in order to use the 4 line parallel cascade routine on horizontal
# lines, we need to reorder (rotate or transpose) the matrix, since
# images are scanline encoded, and we want to work in parallell
# on 4 lines.
#
# since the 4 lines are independent, it doesnt matter in which order
# the the vector elements are present.
#
# this allows us to use the same routine for left->right and right->left
# processing.
#
# some comments on the non-abelean group of square isometries consisting of
# (I) identity
# (H) horizontal axis mirror
# (V) vertical axis mirror
# (T) transpose (diagonal axis mirror)
# (A) antitranspose (antidiagonal axis mirror)
# (R1) 90deg anticlockwize rotation
# (R2) 180deg rotation
# (R3) 90deg clockwize rotation
#
#
# we basicly have two options: (R1,R3) or (T,A)
# we opt for T and A because they are self inverting, which improves locality
#
# use antitranspose for right to left an transpose
# for left to right (little endian)
# antitranspose 4x4
# input
# %mm3 == {d0 d1 d2 d3}
# %mm2 == {c0 c1 c2 c3}
# %mm1 == {b0 b1 b2 b3}
# %mm0 == {a0 a1 a2 a3}
# output
# %mm3 == {a3 b3 c3 d3}
# %mm2 == {a2 b2 c2 d2}
# %mm1 == {a1 b1 c1 d1}
# %mm0 == {a0 b0 c0 d0}
.macro antitranspose_4x4:
movq %mm3, %mm4
punpcklwd %mm1, %mm4 # mm4 <- {b2 d2 b3 d3}
movq %mm3, %mm5
punpckhwd %mm1, %mm5 # mm5 <- {b0 d0 b1 d1}
movq %mm2, %mm6
punpcklwd %mm0, %mm6 # mm6 <- {a2 c2 a3 c3}
movq %mm2, %mm7
punpckhwd %mm0, %mm7 # mm7 <- {a0 c0 a1 c1}
movq %mm4, %mm3
punpcklwd %mm6, %mm3 # mm3 <- {a3 b3 c3 d3}
movq %mm4, %mm2
punpckhwd %mm6, %mm2 # mm2 <- {a2 b2 c2 d2}
movq %mm5, %mm1
punpcklwd %mm7, %mm1 # mm1 <- {a1 b1 c1 d1}
movq %mm5, %mm0
punpckhwd %mm7, %mm0 # mm0 <- {a0 b0 c0 d0}
.endm
# transpose 4x4
# input
# %mm3 == {d3 d2 d1 d0}
# %mm2 == {c3 c2 c1 c0}
# %mm1 == {b3 b2 b1 b0}
# %mm0 == {a3 a2 a1 a0}
# output
# %mm3 == {d3 c3 b3 a3}
# %mm2 == {d2 c2 b2 a2}
# %mm1 == {d1 c1 b1 a1}
# %mm0 == {d0 c0 b0 a0}
.macro transpose_4x4:
movq %mm0, %mm4
punpcklwd %mm2, %mm4 # mm4 <- {c1 a1 c0 a0}
movq %mm0, %mm5
punpckhwd %mm2, %mm5 # mm5 <- {c3 a3 c2 a2}
movq %mm1, %mm6
punpcklwd %mm3, %mm6 # mm6 <- {d1 b1 d0 b0}
movq %mm1, %mm7
punpckhwd %mm3, %mm7 # mm7 <- {d3 b3 d2 b2}
movq %mm4, %mm0
punpcklwd %mm6, %mm0 # mm0 <- {d0 c0 b0 a0}
movq %mm4, %mm1
punpckhwd %mm6, %mm1 # mm1 <- {d1 c1 b1 a1}
movq %mm5, %mm2
punpcklwd %mm7, %mm2 # mm2 <- {d2 c2 b2 a2}
movq %mm5, %mm3
punpckhwd %mm7, %mm3 # mm3 <- {d3 c3 b3 a3}
.endm
.globl pixel_cascade_vertb_s16
.type pixel_cascade_vertb_s16,@function
# pixel_cascade_vertbr_s16(char *pixel_array, int nb_rows, int linewidth, short int coef[20], short int state[8])
pixel_cascade_vertb_s16:
pushl %ebp
movl %esp, %ebp
push %ebx
push %esi
push %edi
movl 8(%ebp), %ebx # pixel array offset
movl 12(%ebp), %ecx # nb of 4x4 pixblocks
movl 16(%ebp), %edx # line with
movl 20(%ebp), %esi # coefs
movl 24(%ebp), %edi # state
shll $1, %edx # short int addressing
subl %edx, %ebx
movq 0(%edi), %mm1 # s1[k-1]
movq 8(%edi), %mm2 # s2[k-1]
.align 16
.cascade_vertb_line_loop:
movq (%ebx,%edx,1), %mm3
movq %mm3, %mm0
addl %edx, %ebx
coupled
movq %mm0, (%ebx)
movq (%ebx,%edx,1), %mm3
movq %mm3, %mm0
addl %edx, %ebx
coupled
movq %mm0, (%ebx)
movq (%ebx,%edx,1), %mm3
movq %mm3, %mm0
addl %edx, %ebx
coupled
movq %mm0, (%ebx)
movq (%ebx,%edx,1), %mm3
movq %mm3, %mm0
addl %edx, %ebx
coupled
movq %mm0, (%ebx)
decl %ecx
jnz .cascade_vertb_line_loop
movq %mm1, 0(%edi) # s1[k-1]
movq %mm2, 8(%edi) # s2[k-1]
emms
pop %edi
pop %esi
pop %ebx
leave
ret
.globl pixel_cascade_horlr_s16
.type pixel_cascade_horlr_s16,@function
# pixel_cascade_hor_s16(char *pixel_array, int nb_rows, int linewidth, short int coef[20], short int state[8])
pixel_cascade_horlr_s16:
pushl %ebp
movl %esp, %ebp
push %ebx
push %esi
push %edi
movl 8(%ebp), %ebx # pixel array offset
movl 12(%ebp), %ecx # nb of 4x4 pixblocks
movl 16(%ebp), %edx # line with
movl 20(%ebp), %esi # coefs
movl 24(%ebp), %edi # state
shll $1, %edx # short int addressing
movl %edx, %eax
shll $1, %eax
addl %edx, %eax # eax = 3 * edx
.align 16
.cascade_horlr_line_loop:
movq (%edi), %mm1
movq 8(%edi), %mm2
movq (%ebx), %mm0
movq (%ebx,%edx,1), %mm1
movq (%ebx,%edx,2), %mm2
movq (%ebx,%eax,1), %mm3
transpose_4x4
movq %mm1, (%ebx,%edx,1)
movq %mm2, (%ebx,%edx,2)
movq %mm3, (%ebx,%eax,1)
coupled
movq %mm0, (%ebx)
movq (%ebx,%edx,1), %mm3
movq %mm3, %mm0
coupled
movq %mm0, (%ebx, %edx,1)
movq (%ebx,%edx,2), %mm3
movq %mm3, %mm0
coupled
movq %mm0, (%ebx, %edx,2)
movq (%ebx,%eax,1), %mm3
movq %mm3, %mm0
coupled
movq %mm1, 0(%edi) # s1[k-1]
movq %mm2, 8(%edi) # s2[k-1]
movq %mm0, %mm3
movq (%ebx), %mm0
movq (%ebx,%edx,1), %mm1
movq (%ebx,%edx,2), %mm2
transpose_4x4
movq %mm0, (%ebx)
movq %mm1, (%ebx,%edx,1)
movq %mm2, (%ebx,%edx,2)
movq %mm3, (%ebx,%eax,1)
addl $8, %ebx
decl %ecx
jnz .cascade_horlr_line_loop
emms
pop %edi
pop %esi
pop %ebx
leave
ret
|
agraef/purr-data
| 1,891
|
externals/pdp/system/mmx/pixel_rand_s16.s
|
# Pure Data Packet mmx routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
.globl pixel_rand_s16
.type pixel_rand_s16,@function
# mmx rgba pixel gain
# void pixel_rand_s16(int *dst, nb_4pixel_vectors, short int random_seed[4])
pixel_rand_s16:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 16(%ebp), %esi # int16[4] array of random seeds
movl 8(%ebp), %edi # dst array
movl 12(%ebp), %ecx # pixel count
movq (%esi), %mm6
pcmpeqw %mm3, %mm3
psrlw $15, %mm3 # get bit mask 4 times 0x0001
.align 16
.loop_rand:
# prefetch 128(%esi)
movq %mm6, %mm4 # get random vector
psrlw $15, %mm4 # get first component
movq %mm6, %mm5
psrlw $14, %mm5 # get second component
pxor %mm5, %mm4
movq %mm6, %mm5
psrlw $12, %mm5 # get third component
pxor %mm5, %mm4
movq %mm6, %mm5
psrlw $3, %mm5 # get forth component
pxor %mm5, %mm4
psllw $1, %mm6 # shift left original random vector
pand %mm3, %mm4 # isolate new bit
por %mm4, %mm6 # combine into new random vector
movq %mm6, (%edi)
addl $8, %edi
decl %ecx
jnz .loop_rand # loop
movq %mm6, (%esi) # store random seeds
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 1,544
|
externals/pdp/scaf/pdp/scaf_feeder.s
|
# Pure Data Packet - scaf feeder routine.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
# for dup
.include "../compiler/scafmacro.s"
# *rg is only used for returning the stack pointer
# the 4 bit counter is using registers mm4-mm7 now
# long long scaf_feeder(void *tos, void *rg, *void() ca_rule, void *env)
.globl scaf_feeder
.type scaf_feeder, @function
scaf_feeder:
pushl %ebp
movl %esp, %ebp
push %esi
push %edi
movl 20(%ebp), %edi # load env ptr
movl 8(%ebp), %esi # load TOS2 ptr
movl 16(%ebp), %eax # address of ca routine
pcmpeqw %mm3, %mm3 # load 1 reg
call *%eax # TOS = 32x2 cell result
dup # push %mm0 to memory
movl (%esi), %eax
movl 4(%esi), %edx
lea 16(%esi), %esi # discard stack
movl %esi, (%edi) # store for stack underflow check
emms
pop %edi
pop %esi
leave
ret
|
agraef/purr-data
| 7,548
|
externals/pdp/scaf/compiler/scafmacro.s
|
# Pure Data Packet - scaf assembler macros.
# Copyright (c) by Tom Schouten <tom@zwizwa.be>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
# this file contains pure asm macros. it is to be included before assembly
# after scaforth.pl has processed the .scaf file
# *************************** JMP CALL RET **************************************
# j c r
.macro j address
jmp \address
.endm
.macro c address
call \address
.endm
.macro r
ret
.endm
# *************************** CA CELL ACCESS MACROS *****************************
# dropldTL - dropldBR
# shift / load rectangle macros:
# shift rectangle horizontal
# result is in reg1
.macro shift reg1 reg2 count
psllq $(16-\count), \reg1
psrlq $(16+\count), \reg2
psrlq $32, \reg1
psllq $32, \reg2
por \reg2, \reg1
.endm
.macro ldtop reg1 reg2
movq (%edi), \reg1
movq 8(%edi), \reg2
.endm
.macro ldcenter reg1 reg2
movq 8(%edi), \reg1
movq 16(%edi), \reg2
.endm
.macro ldbottom reg1 reg2
movq 16(%edi), \reg1
movq 24(%edi), \reg2
.endm
# dropld from top row
# dropld the top left square
.macro dropldTL
ldtop %mm0, %mm1
shift %mm0, %mm1, -1
.endm
# dropld the top mid square
.macro dropldTM
ldtop %mm0, %mm1
shift %mm0, %mm1, 0
.endm
# dropld the top right square
.macro dropldTR
ldtop %mm0, %mm1
shift %mm0, %mm1, 1
.endm
# dropld from center row
# dropld the mid left square
.macro dropldML
ldcenter %mm0, %mm1
shift %mm0, %mm1, -1
.endm
# dropld the mid mid square
.macro dropldMM
ldcenter %mm0, %mm1
shift %mm0, %mm1, 0
.endm
# dropld the mid right square
.macro dropldMR
ldcenter %mm0, %mm1
shift %mm0, %mm1, 1
.endm
# dropld from bottom row
# dropld the bottom left square
.macro dropldBL
ldbottom %mm0, %mm1
shift %mm0, %mm1, -1
.endm
# dropld the bottom mid square
.macro dropldBM
ldbottom %mm0, %mm1
shift %mm0, %mm1, 0
.endm
# dropld the bottom right square
.macro dropldBR
ldbottom %mm0, %mm1
shift %mm0, %mm1, 1
.endm
# *************************** CA STACK MANIP MACROS *****************************
# these are the only asm macros that have a stack effect other than
# just replacing the TOS
#
# dup drop dropdup swap nip dropover
.macro dup
lea -8(%esi), %esi
movq %mm0, (%esi)
.endm
.macro drop
movq (%esi), %mm0
lea 8(%esi), %esi
.endm
.macro dropdup
movq (%esi), %mm0
.endm
.macro nipdup
movq %mm0, (%esi)
.endm
.macro swap
movq (%esi), %mm1
movq %mm0, (%esi)
movq %mm1, %mm0
.endm
.macro nip
lea 8(%esi), %esi
.endm
.macro dropover
movq 8(%esi), %mm0
.endm
# *************************** CA BOOLEAN LOGIC MACROS *****************************
# overxor overand overor not
.macro overxor
pxor (%esi), %mm0
.endm
.macro overand
pand (%esi), %mm0
.endm
.macro overor
por (%esi), %mm0
.endm
.macro not
pxor %mm3, %mm0
.endm
# *************************** CONSTANTS *****************************
# dropzero dropone
.macro dropzero
pxor %mm0, %mm0
.endm
.macro dropone
pcmpeqw %mm0, %mm0
.endm
# *************************** 4 BIT REG ACCESS ******************************
# dupsta0 - dupsta4 droplda0 - droplda4
# store bit in accumulator
# bit store
.macro dupsta0
movq %mm0, %mm4
.endm
.macro dupsta1
movq %mm0, %mm5
.endm
.macro dupsta2
movq %mm0, %mm6
.endm
.macro dupsta3
movq %mm0, %mm7
.endm
# load bit from accumulator
.macro droplda0
movq %mm4, %mm0
.endm
.macro droplda1
movq %mm5, %mm0
.endm
.macro droplda2
movq %mm6, %mm0
.endm
.macro droplda3
movq %mm7, %mm0
.endm
# *************************** LOAD 4 BIT CONSTANT IN REG ******************************
# a0000 - a1111
.macro ldbit0 value
.ifeq \value
movq %mm1, %mm4
.else
movq %mm3, %mm4
.endif
.endm
.macro ldbit1 value
.ifeq \value
movq %mm1, %mm5
.else
movq %mm3, %mm5
.endif
.endm
.macro ldbit2 value
.ifeq \value
movq %mm1, %mm6
.else
movq %mm3, %mm6
.endif
.endm
.macro ldbit3 value
.ifeq \value
movq %mm1, %mm7
.else
movq %mm3, %mm7
.endif
.endm
.macro ldbin b3 b2 b1 b0
pxor %mm1, %mm1
ldbit0 \b0
ldbit1 \b1
ldbit2 \b2
ldbit3 \b3
.endm
.macro a0000
ldbin 0 0 0 0
.endm
.macro a0001
ldbin 0 0 0 1
.endm
.macro a0010
ldbin 0 0 1 0
.endm
.macro a0011
ldbin 0 0 1 1
.endm
.macro a0100
ldbin 0 1 0 0
.endm
.macro a0101
ldbin 0 1 0 1
.endm
.macro a0110
ldbin 0 1 1 0
.endm
.macro a0111
ldbin 0 1 1 1
.endm
.macro a1000
ldbin 1 0 0 0
.endm
.macro a1001
ldbin 1 0 0 1
.endm
.macro a1010
ldbin 1 0 1 0
.endm
.macro a1011
ldbin 1 0 1 1
.endm
.macro a1100
ldbin 1 1 0 0
.endm
.macro a1101
ldbin 1 1 0 1
.endm
.macro a1110
ldbin 1 1 1 0
.endm
.macro a1111
ldbin 1 1 1 1
.endm
# *************************** 4 BIT COUNTER ******************************
# adds TOS to bit of counter and returns carry in TOS
#
# adb0 - adb3
.macro adb0
movq %mm4, %mm2
pxor %mm0, %mm4
pand %mm2, %mm0
.endm
.macro adb1
movq %mm5, %mm2
pxor %mm0, %mm5
pand %mm2, %mm0
.endm
.macro adb2
movq %mm6, %mm2
pxor %mm0, %mm6
pand %mm2, %mm0
.endm
.macro adb3
movq %mm7, %mm2
pxor %mm0, %mm7
pand %mm2, %mm0
.endm
# *************************** ACCUMULATOR TESTS ***************************
# dropisnonzero4 - dropisnonzero1
.macro dropisnonzero4
movq %mm4, %mm0
por %mm5, %mm0
por %mm6, %mm0
por %mm7, %mm0
.endm
.macro dropisnonzero3
movq %mm4, %mm0
por %mm5, %mm0
por %mm6, %mm0
.endm
.macro dropisnonzero2
movq %mm4, %mm0
por %mm5, %mm0
.endm
.macro dropisnonzero1
movq %mm4, %mm0
.endm
# *************************** REGISTER SHIFT OPERATIONS **********************
# shift and leave shifted out byte on stack
# rotate trough top of stack
.macro dropshiftright
movq %mm4, %mm0
movq %mm5, %mm4
movq %mm6, %mm5
movq %mm7, %mm6
pxor %mm7, %mm7
.endm
.macro dropshiftleft
movq %mm7, %mm0
movq %mm6, %mm7
movq %mm5, %mm6
movq %mm4, %mm5
pxor %mm4, %mm4
.endm
.macro dropshiftrighta
movq %mm4, %mm0
movq %mm5, %mm4
movq %mm6, %mm5
movq %mm7, %mm6
.endm
.macro rotateright
movq %mm4, %mm1
movq %mm5, %mm4
movq %mm6, %mm5
movq %mm7, %mm6
movq %mm1, %mm7
.endm
.macro rotateleft
movq %mm7, %mm1
movq %mm6, %mm7
movq %mm5, %mm6
movq %mm4, %mm5
movq %mm1, %mm4
.endm
.macro rotaterightstack
movq %mm0, %mm1
movq %mm4, %mm0
movq %mm5, %mm4
movq %mm6, %mm5
movq %mm7, %mm6
movq %mm1, %mm7
.endm
.macro rotateleftstack
movq %mm0, %mm1
movq %mm7, %mm0
movq %mm6, %mm7
movq %mm5, %mm6
movq %mm4, %mm5
movq %mm1, %mm4
.endm
# *************************** OTHER REGISTER OPERATIONS **********************
# anot : complement reg (can be used to implement subtraction)
.macro anot
pxor %mm3, %mm4
pxor %mm3, %mm5
pxor %mm3, %mm6
pxor %mm3, %mm7
.endm
|
AhnJihwan/AhnTri
| 2,711
|
arch/i386/isr.s
|
.global isr_0
.global isr_1
.global isr_2
.global isr_3
.global isr_4
.global isr_5
.global isr_6
.global isr_7
.global isr_8
.global isr_9
.global isr_10
.global isr_11
.global isr_12
.global isr_13
.global isr_14
.global isr_15
.global isr_16
.global isr_17
.global isr_18
.global isr_19
.global isr_20
.global isr_21
.global isr_22
.global isr_23
.global isr_24
.global isr_25
.global isr_26
.global isr_27
.global isr_28
.global isr_29
.global isr_30
.global isr_31
isr_0:
cli
push $0
push $0
jmp common_isr_stub_handler
isr_1:
cli
push $1
push $1
jmp common_isr_stub_handler
isr_2:
cli
push $2
push $2
jmp common_isr_stub_handler
isr_3:
cli
push $3
push $3
jmp common_isr_stub_handler
isr_4:
cli
push $4
push $4
jmp common_isr_stub_handler
isr_5:
cli
push $5
push $5
jmp common_isr_stub_handler
isr_6:
cli
push $6
push $6
jmp common_isr_stub_handler
isr_7:
cli
push $7
push $7
jmp common_isr_stub_handler
isr_8:
cli
push $8
push $8
jmp common_isr_stub_handler
isr_9:
cli
push $9
push $9
jmp common_isr_stub_handler
isr_10:
cli
push $10
push $10
jmp common_isr_stub_handler
isr_11:
cli
push $11
push $11
jmp common_isr_stub_handler
isr_12:
cli
push $12
push $12
jmp common_isr_stub_handler
isr_13:
cli
push $13
push $13
jmp common_isr_stub_handler
isr_14:
cli
push $14
push $14
jmp common_isr_stub_handler
isr_15:
cli
push $15
push $15
jmp common_isr_stub_handler
isr_16:
cli
push $16
push $16
jmp common_isr_stub_handler
isr_17:
cli
push $17
push $17
jmp common_isr_stub_handler
isr_18:
cli
push $18
push $18
jmp common_isr_stub_handler
isr_19:
cli
push $19
push $19
jmp common_isr_stub_handler
isr_20:
cli
push $20
push $20
jmp common_isr_stub_handler
isr_21:
cli
push $21
push $21
jmp common_isr_stub_handler
isr_22:
cli
push $22
push $22
jmp common_isr_stub_handler
isr_23:
cli
push $23
push $23
jmp common_isr_stub_handler
isr_24:
cli
push $24
push $24
jmp common_isr_stub_handler
isr_25:
cli
push $25
push $25
jmp common_isr_stub_handler
isr_26:
cli
push $26
push $26
jmp common_isr_stub_handler
isr_27:
cli
push $27
push $27
jmp common_isr_stub_handler
isr_28:
cli
push $28
push $28
jmp common_isr_stub_handler
isr_29:
cli
push $29
push $29
jmp common_isr_stub_handler
isr_30:
cli
push $30
push $30
jmp common_isr_stub_handler
isr_31:
cli
push $31
push $31
jmp common_isr_stub_handler
common_isr_stub_handler:
pusha
mov %ds, %eax
push %eax
mov $0x10, %eax
mov %eax, %ds
mov %eax, %es
mov %eax, %fs
mov %eax, %gs
call isr_handler
pop %eax
mov %eax, %ds
mov %eax, %es
mov %eax, %fs
mov %eax, %gs
popa
add $8, %esp
sti
iret
|
AhnJihwan/AhnTri
| 2,037
|
arch/i386/irq.s
|
.global irq0
.global irq1
.global irq2
.global irq3
.global irq4
.global irq5
.global irq6
.global irq7
.global irq8
.global irq9
.global irq10
.global irq11
.global irq12
.global irq13
.global irq14
.global irq15
.extern irq0handler
.extern irq1handler
.extern irq2handler
.extern irq3handler
.extern irq4handler
.extern irq5handler
.extern irq6handler
.extern irq7handler
.extern irq8handler
.extern irq9handler
.extern irq10handler
.extern irq11handler
.extern irq12handler
.extern irq13handler
.extern irq14handler
.extern irq15handler
irq0:
cli
push $0
push $32
jmp irq_stub
irq1:
cli
push $0
push $33
jmp irq_stub
irq2:
cli
push $0
push $34
jmp irq_stub
irq3:
cli
push $0
push $35
jmp irq_stub
irq4:
cli
push $0
push $36
jmp irq_stub
irq5:
cli
push $0
push $37
jmp irq_stub
irq6:
cli
push $0
push $38
jmp irq_stub
irq7:
cli
push $0
push $39
jmp irq_stub
irq8:
cli
push $0
push $40
jmp irq_stub
irq9:
cli
push $0
push $41
jmp irq_stub
irq10:
cli
push $0
push $42
jmp irq_stub
irq11:
cli
push $0
push $43
jmp irq_stub
irq12:
cli
push $0
push $44
jmp irq_stub
irq13:
cli
push $0
push $46
jmp irq_stub
irq14:
cli
push $0
push $47
jmp irq_stub
irq15:
cli
push $0
push $48
jmp irq_stub
irq_stub:
pusha # Pushes edi,esi,ebp,esp,ebx,edx,ecx,eax
movw %ds,%ax # Lower 16-bits of eax = ds.
pushl %eax # save the data segment descriptor
movw $0x10,%ax # load the kernel data segment descriptor
movw %ax,%ds
movw %ax,%es
movw %ax,%fs
movw %ax,%gs
call irq_handler
popl %ebx # reload the original data segment descriptor
movw %bx,%ds
movw %bx,%es
movw %bx,%fs
movw %bx,%gs
popa # Pops edi,esi,ebp...
addl $8,%esp # Cleans up the pushed error code and pushed ISR number
sti
iret # pops 5 things at once: CS, EIP, EFLAGS, SS, and ESP
|
ahorn/xv6
| 1,613
|
entry.S
|
# Multiboot header, for multiboot boot loaders like GNU Grub.
# http://www.gnu.org/software/grub/manual/multiboot/multiboot.html
#
# Using GRUB 2, you can boot xv6 from a file stored in a
# Linux file system by copying kernel or kernelmemfs to /boot
# and then adding this menu entry:
#
# menuentry "xv6" {
# insmod ext2
# set root='(hd0,msdos1)'
# set kernel='/boot/kernel'
# echo "Loading ${kernel}..."
# multiboot ${kernel} ${kernel}
# boot
# }
#include "asm.h"
#include "memlayout.h"
#include "mmu.h"
#include "param.h"
# Multiboot header. Data to direct multiboot loader.
.p2align 2
.text
.globl multiboot_header
multiboot_header:
#define magic 0x1badb002
#define flags 0
.long magic
.long flags
.long (-magic-flags)
# By convention, the _start symbol specifies the ELF entry point.
# Since we haven't set up virtual memory yet, our entry point is
# the physical address of 'entry'.
.globl _start
_start = V2P_WO(entry)
# Entering xv6 on boot processor, with paging off.
.globl entry
entry:
# Turn on page size extension for 4Mbyte pages
movl %cr4, %eax
orl $(CR4_PSE), %eax
movl %eax, %cr4
# Set page directory
movl $(V2P_WO(entrypgdir)), %eax
movl %eax, %cr3
# Turn on paging.
movl %cr0, %eax
orl $(CR0_PG|CR0_WP), %eax
movl %eax, %cr0
# Set up the stack pointer.
movl $(stack + KSTACKSIZE), %esp
# Jump to main(), and switch to executing at
# high addresses. The indirect call is needed because
# the assembler produces a PC-relative instruction
# for a direct jump.
mov $main, %eax
jmp *%eax
.comm stack, KSTACKSIZE
|
ahorn/xv6
| 2,044
|
entryother.S
|
#include "asm.h"
#include "memlayout.h"
#include "mmu.h"
# Each non-boot CPU ("AP") is started up in response to a STARTUP
# IPI from the boot CPU. Section B.4.2 of the Multi-Processor
# Specification says that the AP will start in real mode with CS:IP
# set to XY00:0000, where XY is an 8-bit value sent with the
# STARTUP. Thus this code must start at a 4096-byte boundary.
#
# Because this code sets DS to zero, it must sit
# at an address in the low 2^16 bytes.
#
# Startothers (in main.c) sends the STARTUPs one at a time.
# It copies this code (start) at 0x7000. It puts the address of
# a newly allocated per-core stack in start-4,the address of the
# place to jump to (mpenter) in start-8, and the physical address
# of entrypgdir in start-12.
#
# This code is identical to bootasm.S except:
# - it does not need to enable A20
# - it uses the address at start-4, start-8, and start-12
.code16
.globl start
start:
cli
xorw %ax,%ax
movw %ax,%ds
movw %ax,%es
movw %ax,%ss
lgdt gdtdesc
movl %cr0, %eax
orl $CR0_PE, %eax
movl %eax, %cr0
//PAGEBREAK!
ljmpl $(SEG_KCODE<<3), $(start32)
.code32
start32:
movw $(SEG_KDATA<<3), %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movw $0, %ax
movw %ax, %fs
movw %ax, %gs
# Turn on page size extension for 4Mbyte pages
movl %cr4, %eax
orl $(CR4_PSE), %eax
movl %eax, %cr4
# Use enterpgdir as our initial page table
movl (start-12), %eax
movl %eax, %cr3
# Turn on paging.
movl %cr0, %eax
orl $(CR0_PE|CR0_PG|CR0_WP), %eax
movl %eax, %cr0
# Switch to the stack allocated by startothers()
movl (start-4), %esp
# Call mpenter()
call *(start-8)
movw $0x8a00, %ax
movw %ax, %dx
outw %ax, %dx
movw $0x8ae0, %ax
outw %ax, %dx
spin:
jmp spin
.p2align 2
gdt:
SEG_NULLASM
SEG_ASM(STA_X|STA_R, 0, 0xffffffff)
SEG_ASM(STA_W, 0, 0xffffffff)
gdtdesc:
.word (gdtdesc - gdt - 1)
.long gdt
|
ahorn/xv6
| 2,979
|
bootasm.S
|
#include "asm.h"
#include "memlayout.h"
#include "mmu.h"
# Start the first CPU: switch to 32-bit protected mode, jump into C.
# The BIOS loads this code from the first sector of the hard disk into
# memory at physical address 0x7c00 and starts executing in real mode
# with %cs=0 %ip=7c00.
.code16 # Assemble for 16-bit mode
.globl start
start:
cli # BIOS enabled interrupts; disable
# Zero data segment registers DS, ES, and SS.
xorw %ax,%ax # Set %ax to zero
movw %ax,%ds # -> Data Segment
movw %ax,%es # -> Extra Segment
movw %ax,%ss # -> Stack Segment
# Physical address line A20 is tied to zero so that the first PCs
# with 2 MB would run software that assumed 1 MB. Undo that.
seta20.1:
inb $0x64,%al # Wait for not busy
testb $0x2,%al
jnz seta20.1
movb $0xd1,%al # 0xd1 -> port 0x64
outb %al,$0x64
seta20.2:
inb $0x64,%al # Wait for not busy
testb $0x2,%al
jnz seta20.2
movb $0xdf,%al # 0xdf -> port 0x60
outb %al,$0x60
# Switch from real to protected mode. Use a bootstrap GDT that makes
# virtual addresses map directly to physical addresses so that the
# effective memory map doesn't change during the transition.
lgdt gdtdesc
movl %cr0, %eax
orl $CR0_PE, %eax
movl %eax, %cr0
//PAGEBREAK!
# Complete transition to 32-bit protected mode by using long jmp
# to reload %cs and %eip. The segment descriptors are set up with no
# translation, so that the mapping is still the identity mapping.
ljmp $(SEG_KCODE<<3), $start32
.code32 # Tell assembler to generate 32-bit code now.
start32:
# Set up the protected-mode data segment registers
movw $(SEG_KDATA<<3), %ax # Our data segment selector
movw %ax, %ds # -> DS: Data Segment
movw %ax, %es # -> ES: Extra Segment
movw %ax, %ss # -> SS: Stack Segment
movw $0, %ax # Zero segments not ready for use
movw %ax, %fs # -> FS
movw %ax, %gs # -> GS
# Set up the stack pointer and call into C.
movl $start, %esp
call bootmain
# If bootmain returns (it shouldn't), trigger a Bochs
# breakpoint if running under Bochs, then loop.
movw $0x8a00, %ax # 0x8a00 -> port 0x8a00
movw %ax, %dx
outw %ax, %dx
movw $0x8ae0, %ax # 0x8ae0 -> port 0x8a00
outw %ax, %dx
spin:
jmp spin
# Bootstrap GDT
.p2align 2 # force 4 byte alignment
gdt:
SEG_NULLASM # null seg
SEG_ASM(STA_X|STA_R, 0x0, 0xffffffff) # code seg
SEG_ASM(STA_W, 0x0, 0xffffffff) # data seg
gdtdesc:
.word (gdtdesc - gdt - 1) # sizeof(gdt) - 1
.long gdt # address gdt
|
ahtn/keyplus
| 2,584
|
ports/atmega8/aes/avr-crypto-lib/aes_sbox-asm.S
|
/* aes_sbox-asm.S */
/*
This file is part of the AVR-Crypto-Lib.
Copyright (C) 2006-2015 Daniel Otte (bg@nerilex.org)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* \file aes_dec-asm.S
* \email bg@nerilex.org
* \author Daniel Otte
* \date 2009-01-10
* \license GPLv3 or later
*
*/
.balign 256
.global aes_sbox
aes_sbox:
.byte 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76
.byte 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0
.byte 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15
.byte 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75
.byte 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84
.byte 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf
.byte 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8
.byte 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2
.byte 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73
.byte 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb
.byte 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79
.byte 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08
.byte 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a
.byte 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e
.byte 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf
.byte 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
|
ahtn/keyplus
| 3,460
|
ports/atmega8/aes/avr-crypto-lib/aes_enc-asm.S
|
/* aes_enc-asm.S */
/*
This file is part of the AVR-Crypto-Lib.
Copyright (C) 2006-2015 Daniel Otte (bg@nerilex.org)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* \file aes_enc-asm.S
* \email bg@nerilex.org
* \author Daniel Otte
* \date 2009-01-10
* \license GPLv3 or later
*
*/
#include "avr-asm-macros.S"
/*
* param a: r24
* param b: r22
* param reducer: r0
*/
A = 28
B = 29
P = 0
xREDUCER = 25
.global aes256_enc
aes256_enc:
ldi r20, 14
rjmp aes_encrypt_core
.global aes192_enc
aes192_enc:
ldi r20, 12
rjmp aes_encrypt_core
.global aes128_enc
aes128_enc:
ldi r20, 10
/*
void aes_encrypt_core(aes_cipher_state_t *state, const aes_genctx_t *ks, uint8_t rounds)
*/
T0= 2
T1= 3
T2= 4
T3= 5
SBOX_SAVE0 = 6
SBOX_SAVE1 = 7
ST00 = 8
ST01 = 9
ST02 = 10
ST03 = 11
ST10 = 12
ST11 = 13
ST12 = 14
ST13 = 15
ST20 = 16
ST21 = 17
ST22 = 18
ST23 = 19
ST30 = 20
ST31 = 21
ST32 = 22
ST33 = 23
CTR = 24
/*
* param state: r24:r25
* param ks: r22:r23
* param rounds: r20
*/
.global aes_encrypt_core
aes_encrypt_core:
push_range 2, 17
push r28
push r29
push r24
push r25
movw r26, r22
movw r30, r24
mov CTR, r20
clt
.irp row, 0, 1, 2, 3
.irp col, 0, 1, 2, 3
ld ST\row\col, Z+
.endr
.endr
ldi xREDUCER, 0x1b /* load reducer */
ldi r31, hi8(aes_sbox)
/* key whitening */
1:
.irp row, 0, 1, 2, 3
.irp col, 0, 1, 2, 3
ld r0, X+
eor ST\row\col, r0
.endr
.endr
brtc 2f
exit:
pop r31
pop r30
.irp row, 0, 1, 2, 3
.irp col, 0, 1, 2, 3
st Z+, ST\row\col
.endr
.endr
pop r29
pop r28
pop_range 2, 17
ret
2: dec CTR
brne 3f
set
3:
/* encryption loop */
/* SBOX substitution and shifting */
mov r30, ST00
lpm ST00, Z
mov r30, ST10
lpm ST10, Z
mov r30, ST20
lpm ST20, Z
mov r30, ST30
lpm ST30, Z
mov r30, ST01
lpm T0, Z
mov r30, ST11
lpm ST01, Z
mov r30, ST21
lpm ST11, Z
mov r30, ST31
lpm ST21, Z
mov ST31, T0
mov r30, ST02
lpm T0, Z
mov r30, ST12
lpm T1, Z
mov r30, ST22
lpm ST02, Z
mov r30, ST32
lpm ST12, Z
mov ST22, T0
mov ST32, T1
mov r30, ST03
lpm T0, Z
mov r30, ST33
lpm ST03, Z
mov r30, ST23
lpm ST33, Z
mov r30, ST13
lpm ST23, Z
mov ST13, T0
/* mixcols (or rows in our case) */
brtc 2f
rjmp 1b
2:
/* mixrows */
.irp row, 0, 1, 2, 3
mov r0, ST\row\()2
eor r0, ST\row\()3
mov T2, r0
mov T0, ST\row\()0
eor ST\row\()0, ST\row\()1
eor r0, ST\row\()0
lsl ST\row\()0
brcc 3f
eor ST\row\()0, xREDUCER
3: eor ST\row\()0, r0
eor ST\row\()0, T0
mov T1, ST\row\()1
eor T1, ST\row\()2
lsl T1
brcc 3f
eor T1, xREDUCER
3: eor T1, r0
eor ST\row\()1, T1
lsl T2
brcc 3f
eor T2, xREDUCER
3: eor T2, r0
eor ST\row\()2, T2
eor T0, ST\row\()3
lsl T0
brcc 3f
eor T0, xREDUCER
3: eor T0, r0
eor ST\row\()3, T0
.endr
/* mix colums (rows) done */
/* add key*/
rjmp 1b
|
ahtn/keyplus
| 9,410
|
ports/atmega8/aes/avr-crypto-lib/aes_dec-asm_faster.S
|
/* aes_dec-asm.S */
/*
This file is part of the AVR-Crypto-Lib.
Copyright (C) 2006-2015 Daniel Otte (bg@nerilex.org)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* \file aes_dec-asm.S
* \email bg@nerilex.org
* \author Daniel Otte
* \date 2009-01-10
* \license GPLv3 or later
*
*/
#include "avr-asm-macros.S"
A = 28
B = 29
P = 0
xREDUCER = 25
.global aes256_dec
aes256_dec:
ldi r20, 14
rjmp aes_decrypt_core
.global aes192_dec
aes192_dec:
ldi r20, 12
rjmp aes_decrypt_core
.global aes128_dec
aes128_dec:
ldi r20, 10
/*
void aes_decrypt_core(aes_cipher_state_t *state, const aes_genctx_t *ks, uint8_t rounds)
*/
T0= 2
T1= 3
T2= 4
T3= 5
T4 = 6
T5 = 7
ST00 = 8
ST01 = 9
ST02 = 10
ST03 = 11
ST10 = 12
ST11 = 13
ST12 = 14
ST13 = 15
ST20 = 16
ST21 = 17
ST22 = 18
ST23 = 19
ST30 = 20
ST31 = 21
ST32 = 22
ST33 = 23
CTR = 24
/*
* param state: r24:r25
* param ks: r22:r23
* param rounds: r20
*/
.global aes_decrypt_core
aes_decrypt_core:
push_range 2, 17
push r28
push r29
push r24
push r25
movw r26, r22
movw r30, r24
mov CTR, r20
inc r20
swap r20 /* r20*16 */
add r26, r20
adc r27, r1
clt
.irp param, ST00, ST01, ST02, ST03, ST10, ST11, ST12, ST13, ST20, ST21, ST22, ST23, ST30, ST31, ST32, ST33
ld \param, Z+
.endr
ldi xREDUCER, 0x1b /* load reducer */
.irp param, ST33, ST32, ST31, ST30, ST23, ST22, ST21, ST20, ST13, ST12, ST11, ST10, ST03, ST02, ST01, ST00
ld r0, -X
eor \param, r0
.endr
1:
dec CTR
brne 2f
set
2:
ldi r31, hi8(aes_invsbox)
/* substitute and invShift */
.irp param, ST00, ST10, ST20, ST30
mov r30, \param
lpm \param, Z
.endr
mov r30, ST31
lpm T0, Z
mov r30, ST21
lpm ST31, Z
mov r30, ST11
lpm ST21, Z
mov r30, ST01
lpm ST11, Z
mov ST01, T0
mov r30, ST32
lpm T0, Z
mov r30, ST22
lpm T1,Z
mov r30, ST12
lpm ST32, Z
mov r30, ST02
lpm ST22, Z
mov ST12, T0
mov ST02, T1
mov r30, ST03
lpm T0, Z
mov r30, ST13
lpm ST03, Z
mov r30, ST23
lpm ST13, Z
mov r30, ST33
lpm ST23, Z
mov ST33, T0
/* key addition */
.irp param, ST33, ST32, ST31, ST30, ST23, ST22, ST21, ST20, ST13, ST12, ST11, ST10, ST03, ST02, ST01, ST00
ld r0, -X
eor \param, r0
.endr
brtc 2f
exit:
pop r31
pop r30
st Z+, ST00
st Z+, ST01
st Z+, ST02
st Z+, ST03
st Z+, ST10
st Z+, ST11
st Z+, ST12
st Z+, ST13
st Z+, ST20
st Z+, ST21
st Z+, ST22
st Z+, ST23
st Z+, ST30
st Z+, ST31
st Z+, ST32
st Z+, ST33
pop r29
pop r28
pop_range 2, 17
ret
2:
/* inv column (row) mixing*/
/* invMixCol (Row) 1 */
/* preparing */
ldi r31, hi8(lut_gf256mul_0x09)
mov T0, ST03
eor T0, ST02 ; T0 = t
mov T1, ST00
eor T1, ST01 ; T1 = u
mov r30, T0
eor r30, T1
lpm T2, Z ; T2 = v'
ldi r31, hi8(lut_gf256mul_0x04)
mov r30, ST02
eor r30, ST00
lpm T3, Z
eor T3, T2; T3 = w
mov r30, ST03
eor r30, ST01
lpm P, Z ; T2 = v
eor T2, P
/* now the big move */
mov T4, ST00
eor T4, ST03
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST03, T4
mov T4, ST02
eor T4, ST01
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST01, T4
lsl T0
brcc 3f
eor T0, xREDUCER
3: eor T0, T3
eor ST02, T0
lsl T1
brcc 3f
eor T1, xREDUCER
3: eor T1, T3
eor ST00, T1
/* invMixCol (Row) 2 */
/* preparing */
ldi r31, hi8(lut_gf256mul_0x09)
mov T0, ST13
eor T0, ST12 ; T0 = t
mov T1, ST10
eor T1, ST11 ; T1 = u
mov r30, T0
eor r30, T1
lpm T2, Z ; T2 = v'
ldi r31, hi8(lut_gf256mul_0x04)
mov r30, ST12
eor r30, ST10
lpm T3, Z
eor T3, T2; T3 = w
mov r30, ST13
eor r30, ST11
lpm P, Z
eor T2, P ; T2 = v
/* now the big move */
mov T4, ST10
eor T4, ST13
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST13, T4
mov T4, ST12
eor T4, ST11
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST11, T4
lsl T0
brcc 3f
eor T0, xREDUCER
3: eor T0, T3
eor ST12, T0
lsl T1
brcc 3f
eor T1, xREDUCER
3: eor T1, T3
eor ST10, T1
/* invMixCol (Row) 2 */
/* preparing */
ldi r31, hi8(lut_gf256mul_0x09)
mov T0, ST23
eor T0, ST22 ; T0 = t
mov T1, ST20
eor T1, ST21 ; T1 = u
mov r30, T0
eor r30, T1
lpm T2, Z ; T2 = v'
ldi r31, hi8(lut_gf256mul_0x04)
mov r30, ST22
eor r30, ST20
lpm T3, Z
eor T3, T2; T3 = w
mov r30, ST23
eor r30, ST21
lpm P, Z
eor T2, P ; T2 = v
/* now the big move */
mov T4, ST20
eor T4, ST23
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST23, T4
mov T4, ST22
eor T4, ST21
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST21, T4
lsl T0
brcc 3f
eor T0, xREDUCER
3: eor T0, T3
eor ST22, T0
lsl T1
brcc 3f
eor T1, xREDUCER
3: eor T1, T3
eor ST20, T1
/* invMixCol (Row) 3 */
/* preparing */
ldi r31, hi8(lut_gf256mul_0x09)
mov T0, ST33
eor T0, ST32 ; T0 = t
mov T1, ST30
eor T1, ST31 ; T1 = u
mov r30, T0
eor r30, T1
lpm T2, Z ; T2 = v'
ldi r31, hi8(lut_gf256mul_0x04)
mov r30, ST32
eor r30, ST30
lpm T3, Z
eor T3, T2; T3 = w
mov r30, ST33
eor r30, ST31
lpm P, Z
eor T2, P ; T2 = v
/* now the big move */
mov T4, ST30
eor T4, ST33
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST33, T4
mov T4, ST32
eor T4, ST31
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST31, T4
lsl T0
brcc 3f
eor T0, xREDUCER
3: eor T0, T3
eor ST32, T0
lsl T1
brcc 3f
eor T1, xREDUCER
3: eor T1, T3
eor ST30, T1
rjmp 1b
.balign 256
lut_gf256mul_0x09:
.byte 0x00, 0x09, 0x12, 0x1B, 0x24, 0x2D, 0x36, 0x3F
.byte 0x48, 0x41, 0x5A, 0x53, 0x6C, 0x65, 0x7E, 0x77
.byte 0x90, 0x99, 0x82, 0x8B, 0xB4, 0xBD, 0xA6, 0xAF
.byte 0xD8, 0xD1, 0xCA, 0xC3, 0xFC, 0xF5, 0xEE, 0xE7
.byte 0x3B, 0x32, 0x29, 0x20, 0x1F, 0x16, 0x0D, 0x04
.byte 0x73, 0x7A, 0x61, 0x68, 0x57, 0x5E, 0x45, 0x4C
.byte 0xAB, 0xA2, 0xB9, 0xB0, 0x8F, 0x86, 0x9D, 0x94
.byte 0xE3, 0xEA, 0xF1, 0xF8, 0xC7, 0xCE, 0xD5, 0xDC
.byte 0x76, 0x7F, 0x64, 0x6D, 0x52, 0x5B, 0x40, 0x49
.byte 0x3E, 0x37, 0x2C, 0x25, 0x1A, 0x13, 0x08, 0x01
.byte 0xE6, 0xEF, 0xF4, 0xFD, 0xC2, 0xCB, 0xD0, 0xD9
.byte 0xAE, 0xA7, 0xBC, 0xB5, 0x8A, 0x83, 0x98, 0x91
.byte 0x4D, 0x44, 0x5F, 0x56, 0x69, 0x60, 0x7B, 0x72
.byte 0x05, 0x0C, 0x17, 0x1E, 0x21, 0x28, 0x33, 0x3A
.byte 0xDD, 0xD4, 0xCF, 0xC6, 0xF9, 0xF0, 0xEB, 0xE2
.byte 0x95, 0x9C, 0x87, 0x8E, 0xB1, 0xB8, 0xA3, 0xAA
.byte 0xEC, 0xE5, 0xFE, 0xF7, 0xC8, 0xC1, 0xDA, 0xD3
.byte 0xA4, 0xAD, 0xB6, 0xBF, 0x80, 0x89, 0x92, 0x9B
.byte 0x7C, 0x75, 0x6E, 0x67, 0x58, 0x51, 0x4A, 0x43
.byte 0x34, 0x3D, 0x26, 0x2F, 0x10, 0x19, 0x02, 0x0B
.byte 0xD7, 0xDE, 0xC5, 0xCC, 0xF3, 0xFA, 0xE1, 0xE8
.byte 0x9F, 0x96, 0x8D, 0x84, 0xBB, 0xB2, 0xA9, 0xA0
.byte 0x47, 0x4E, 0x55, 0x5C, 0x63, 0x6A, 0x71, 0x78
.byte 0x0F, 0x06, 0x1D, 0x14, 0x2B, 0x22, 0x39, 0x30
.byte 0x9A, 0x93, 0x88, 0x81, 0xBE, 0xB7, 0xAC, 0xA5
.byte 0xD2, 0xDB, 0xC0, 0xC9, 0xF6, 0xFF, 0xE4, 0xED
.byte 0x0A, 0x03, 0x18, 0x11, 0x2E, 0x27, 0x3C, 0x35
.byte 0x42, 0x4B, 0x50, 0x59, 0x66, 0x6F, 0x74, 0x7D
.byte 0xA1, 0xA8, 0xB3, 0xBA, 0x85, 0x8C, 0x97, 0x9E
.byte 0xE9, 0xE0, 0xFB, 0xF2, 0xCD, 0xC4, 0xDF, 0xD6
.byte 0x31, 0x38, 0x23, 0x2A, 0x15, 0x1C, 0x07, 0x0E
.byte 0x79, 0x70, 0x6B, 0x62, 0x5D, 0x54, 0x4F, 0x46
lut_gf256mul_0x04:
.byte 0x00, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C
.byte 0x20, 0x24, 0x28, 0x2C, 0x30, 0x34, 0x38, 0x3C
.byte 0x40, 0x44, 0x48, 0x4C, 0x50, 0x54, 0x58, 0x5C
.byte 0x60, 0x64, 0x68, 0x6C, 0x70, 0x74, 0x78, 0x7C
.byte 0x80, 0x84, 0x88, 0x8C, 0x90, 0x94, 0x98, 0x9C
.byte 0xA0, 0xA4, 0xA8, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC
.byte 0xC0, 0xC4, 0xC8, 0xCC, 0xD0, 0xD4, 0xD8, 0xDC
.byte 0xE0, 0xE4, 0xE8, 0xEC, 0xF0, 0xF4, 0xF8, 0xFC
.byte 0x1B, 0x1F, 0x13, 0x17, 0x0B, 0x0F, 0x03, 0x07
.byte 0x3B, 0x3F, 0x33, 0x37, 0x2B, 0x2F, 0x23, 0x27
.byte 0x5B, 0x5F, 0x53, 0x57, 0x4B, 0x4F, 0x43, 0x47
.byte 0x7B, 0x7F, 0x73, 0x77, 0x6B, 0x6F, 0x63, 0x67
.byte 0x9B, 0x9F, 0x93, 0x97, 0x8B, 0x8F, 0x83, 0x87
.byte 0xBB, 0xBF, 0xB3, 0xB7, 0xAB, 0xAF, 0xA3, 0xA7
.byte 0xDB, 0xDF, 0xD3, 0xD7, 0xCB, 0xCF, 0xC3, 0xC7
.byte 0xFB, 0xFF, 0xF3, 0xF7, 0xEB, 0xEF, 0xE3, 0xE7
.byte 0x36, 0x32, 0x3E, 0x3A, 0x26, 0x22, 0x2E, 0x2A
.byte 0x16, 0x12, 0x1E, 0x1A, 0x06, 0x02, 0x0E, 0x0A
.byte 0x76, 0x72, 0x7E, 0x7A, 0x66, 0x62, 0x6E, 0x6A
.byte 0x56, 0x52, 0x5E, 0x5A, 0x46, 0x42, 0x4E, 0x4A
.byte 0xB6, 0xB2, 0xBE, 0xBA, 0xA6, 0xA2, 0xAE, 0xAA
.byte 0x96, 0x92, 0x9E, 0x9A, 0x86, 0x82, 0x8E, 0x8A
.byte 0xF6, 0xF2, 0xFE, 0xFA, 0xE6, 0xE2, 0xEE, 0xEA
.byte 0xD6, 0xD2, 0xDE, 0xDA, 0xC6, 0xC2, 0xCE, 0xCA
.byte 0x2D, 0x29, 0x25, 0x21, 0x3D, 0x39, 0x35, 0x31
.byte 0x0D, 0x09, 0x05, 0x01, 0x1D, 0x19, 0x15, 0x11
.byte 0x6D, 0x69, 0x65, 0x61, 0x7D, 0x79, 0x75, 0x71
.byte 0x4D, 0x49, 0x45, 0x41, 0x5D, 0x59, 0x55, 0x51
.byte 0xAD, 0xA9, 0xA5, 0xA1, 0xBD, 0xB9, 0xB5, 0xB1
.byte 0x8D, 0x89, 0x85, 0x81, 0x9D, 0x99, 0x95, 0x91
.byte 0xED, 0xE9, 0xE5, 0xE1, 0xFD, 0xF9, 0xF5, 0xF1
.byte 0xCD, 0xC9, 0xC5, 0xC1, 0xDD, 0xD9, 0xD5, 0xD1
|
ahtn/keyplus
| 3,880
|
ports/atmega8/aes/avr-crypto-lib/aes_keyschedule-asm.S
|
/* aes_keyschedule-asm */
/*
This file is part of the AVR-Crypto-Lib.
Copyright (C) 2006-2015 Daniel Otte (bg@nerilex.org)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* \file aes_keyschedule-asm.S
* \email bg@nerilex.org
* \author Daniel Otte
* \date 2009-01-09
* \license GPLv3 or later
*
*/
#include "avr-asm-macros.S"
.global aes256_init
aes256_init:
movw r20, r22
ldi r23, hi8(256)
ldi r22, lo8(256)
rjmp aes_init
.global aes192_init
aes192_init:
movw r20, r22
ldi r23, hi8(192)
ldi r22, lo8(192)
rjmp aes_init
.global aes128_init
aes128_init:
movw r20, r22
clr r23
ldi r22, 128
/*
void aes_init(const void *key, uint16_t keysize_b, aes_genctx_t *ctx){
uint8_t hi,i,nk, next_nk;
uint8_t rc=1;
uint8_t tmp[4];
nk=keysize_b>>5; / * 4, 6, 8 * /
hi=4*(nk+6+1);
memcpy(ctx, key, keysize_b/8);
next_nk = nk;
for(i=nk;i<hi;++i){
*((uint32_t*)tmp) = ((uint32_t*)(ctx->key[0].ks))[i-1];
if(i!=next_nk){
if(nk==8 && i%8==4){
tmp[0] = pgm_read_byte(aes_sbox+tmp[0]);
tmp[1] = pgm_read_byte(aes_sbox+tmp[1]);
tmp[2] = pgm_read_byte(aes_sbox+tmp[2]);
tmp[3] = pgm_read_byte(aes_sbox+tmp[3]);
}
} else {
next_nk += nk;
aes_rotword(tmp);
tmp[0] = pgm_read_byte(aes_sbox+tmp[0]);
tmp[1] = pgm_read_byte(aes_sbox+tmp[1]);
tmp[2] = pgm_read_byte(aes_sbox+tmp[2]);
tmp[3] = pgm_read_byte(aes_sbox+tmp[3]);
tmp[0] ^= rc;
rc<<=1;
}
((uint32_t*)(ctx->key[0].ks))[i] = ((uint32_t*)(ctx->key[0].ks))[i-nk]
^ *((uint32_t*)tmp);
}
}
*/
SBOX_SAVE0 = 14
SBOX_SAVE1 = 15
XRC = 17
NK = 22
C1 = 18
NEXT_NK = 19
HI = 23
T0 = 20
T1 = 21
T2 = 24
T3 = 25
/*
* param key: r24:r25
* param keysize_b: r22:r23
* param ctx: r20:r21
*/
.global aes_init
aes_init:
push_range 14, 17
push r28
push r29
movw r30, r20
movw r28, r20
movw r26, r24
lsr r23
ror r22
lsr r22
lsr r22 /* r22 contains keysize_b/8 */
mov C1, r22
1: /* copy key to ctx */
ld r0, X+
st Z+, r0
dec C1
brne 1b
lsr NK
lsr NK
bst NK,3 /* set T if NK==8 */
mov NEXT_NK, NK
mov HI, NK
subi HI, -7
lsl HI
lsl HI
movw r26, r30
sbiw r26, 4
mov C1, NK
ldi r30, lo8(aes_sbox)
ldi r31, hi8(aes_sbox)
movw SBOX_SAVE0, r30
ldi XRC, 1
1:
ld T0, X+
ld T1, X+
ld T2, X+
ld T3, X+
cp NEXT_NK, C1
breq 2f
brtc 5f
mov r16, C1
andi r16, 0x07
cpi r16, 0x04
brne 5f
movw r30, SBOX_SAVE0
add r30, T0
adc r31, r1
lpm T0, Z
movw r30, SBOX_SAVE0
add r30, T1
adc r31, r1
lpm T1, Z
movw r30, SBOX_SAVE0
add r30, T2
adc r31, r1
lpm T2, Z
movw r30, SBOX_SAVE0
add r30, T3
adc r31, r1
lpm T3, Z
rjmp 5f
2:
add NEXT_NK, NK
movw r30, SBOX_SAVE0
add r30, T0
adc r31, r1
lpm r16, Z
movw r30, SBOX_SAVE0
add r30, T1
adc r31, r1
lpm T0, Z
movw r30, SBOX_SAVE0
add r30, T2
adc r31, r1
lpm T1, Z
movw r30, SBOX_SAVE0
add r30, T3
adc r31, r1
lpm T2, Z
mov T3, r16
eor T0, XRC
lsl XRC
brcc 3f
ldi XRC, 0x1b
3:
5:
movw r30, r26
ld r0, Y+
eor r0, T0
st Z+, r0
ld r0, Y+
eor r0 ,T1
st Z+, r0
ld r0, Y+
eor r0, T2
st Z+, r0
ld r0, Y+
eor r0, T3
st Z+, r0
/*
st Z+, T0
st Z+, T1
st Z+, T2
st Z+, T3
*/
inc C1
cp C1, HI
breq 6f
rjmp 1b
6:
clt
pop r29
pop r28
pop_range 14, 17
ret
|
ahtn/keyplus
| 6,163
|
ports/atmega8/aes/avr-crypto-lib/aes_dec-asm.S
|
/* aes_dec-asm.S */
/*
This file is part of the AVR-Crypto-Lib.
Copyright (C) 2006-2015 Daniel Otte (bg@nerilex.org)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* \file aes_dec-asm.S
* \email bg@nerilex.org
* \author Daniel Otte
* \date 2009-01-10
* \license GPLv3 or later
*
*/
#include "avr-asm-macros.S"
A = 28
B = 29
P = 0
xREDUCER = 25
gf256mul:
clr P
1:
lsr A
breq 4f
brcc 2f
eor P, B
2:
lsl B
brcc 3f
eor B, xREDUCER
3:
rjmp 1b
4:
brcc 2f
eor P, B
2:
ret
.global aes256_dec
aes256_dec:
ldi r20, 14
rjmp aes_decrypt_core
.global aes192_dec
aes192_dec:
ldi r20, 12
rjmp aes_decrypt_core
.global aes128_dec
aes128_dec:
ldi r20, 10
/*
void aes_decrypt_core(aes_cipher_state_t *state, const aes_genctx_t *ks, uint8_t rounds)
*/
T0= 2
T1= 3
T2= 4
T3= 5
T4 = 6
T5 = 7
ST00 = 8
ST01 = 9
ST02 = 10
ST03 = 11
ST10 = 12
ST11 = 13
ST12 = 14
ST13 = 15
ST20 = 16
ST21 = 17
ST22 = 18
ST23 = 19
ST30 = 20
ST31 = 21
ST32 = 22
ST33 = 23
CTR = 24
/*
* param state: r24:r25
* param ks: r22:r23
* param rounds: r20
*/
.global aes_decrypt_core
aes_decrypt_core:
push_range 2, 17
push r28
push r29
push r24
push r25
movw r26, r22
movw r30, r24
mov CTR, r20
inc r20
swap r20 /* r20*16 */
add r26, r20
adc r27, r1
clt
; ldi CTR, 2
.irp param, ST00, ST01, ST02, ST03, ST10, ST11, ST12, ST13, ST20, ST21, ST22, ST23, ST30, ST31, ST32, ST33
ld \param, Z+
.endr
ldi xREDUCER, 0x1b /* load reducer */
ldi r31, hi8(aes_invsbox)
.irp param, ST33, ST32, ST31, ST30, ST23, ST22, ST21, ST20, ST13, ST12, ST11, ST10, ST03, ST02, ST01, ST00
ld r0, -X
eor \param, r0
.endr
1:
dec CTR
brne 2f
set
2:
/* substitute and invShift */
.irp param, ST00, ST10, ST20, ST30
mov r30, \param
lpm \param, Z
.endr
mov r30, ST31
lpm T0, Z
mov r30, ST21
lpm ST31, Z
mov r30, ST11
lpm ST21, Z
mov r30, ST01
lpm ST11, Z
mov ST01, T0
mov r30, ST32
lpm T0, Z
mov r30, ST22
lpm T1,Z
mov r30, ST12
lpm ST32, Z
mov r30, ST02
lpm ST22, Z
mov ST12, T0
mov ST02, T1
mov r30, ST03
lpm T0, Z
mov r30, ST13
lpm ST03, Z
mov r30, ST23
lpm ST13, Z
mov r30, ST33
lpm ST23, Z
mov ST33, T0
/* key addition */
.irp param, ST33, ST32, ST31, ST30, ST23, ST22, ST21, ST20, ST13, ST12, ST11, ST10, ST03, ST02, ST01, ST00
ld r0, -X
eor \param, r0
.endr
brtc 2f
exit:
pop r31
pop r30
st Z+, ST00
st Z+, ST01
st Z+, ST02
st Z+, ST03
st Z+, ST10
st Z+, ST11
st Z+, ST12
st Z+, ST13
st Z+, ST20
st Z+, ST21
st Z+, ST22
st Z+, ST23
st Z+, ST30
st Z+, ST31
st Z+, ST32
st Z+, ST33
pop r29
pop r28
pop_range 2, 17
ret
2:
/* inv column (row) mixing*/
/* invMixCol (Row) 1 */
/* preparing */
mov T0, ST03
eor T0, ST02 ; T0 = t
mov T1, ST00
eor T1, ST01 ; T1 = u
mov T2, T0
eor T2, T1
mov B, T2
ldi A, 0x08
rcall gf256mul
eor T2, P ; T2 = v'
mov B, ST02
eor B, ST00
ldi A, 0x04
rcall gf256mul
mov T3, P
eor T3, T2; T3 = w
mov B, ST03
eor B, ST01
ldi A, 0x04
rcall gf256mul
eor T2, P ; T2 = v
/* now the big move */
mov T4, ST00
eor T4, ST03
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST03, T4
mov T4, ST02
eor T4, ST01
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST01, T4
lsl T0
brcc 3f
eor T0, xREDUCER
3: eor T0, T3
eor ST02, T0
lsl T1
brcc 3f
eor T1, xREDUCER
3: eor T1, T3
eor ST00, T1
/* invMixCol (Row) 2 */
/* preparing */
mov T0, ST13
eor T0, ST12 ; T0 = t
mov T1, ST10
eor T1, ST11 ; T1 = u
mov T2, T0
eor T2, T1
mov B, T2
ldi A, 0x08
rcall gf256mul
eor T2, P ; T2 = v'
mov B, ST12
eor B, ST10
ldi A, 0x04
rcall gf256mul
mov T3, P
eor T3, T2; T3 = w
mov B, ST13
eor B, ST11
ldi A, 0x04
rcall gf256mul
eor T2, P ; T2 = v
/* now the big move */
mov T4, ST10
eor T4, ST13
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST13, T4
mov T4, ST12
eor T4, ST11
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST11, T4
lsl T0
brcc 3f
eor T0, xREDUCER
3: eor T0, T3
eor ST12, T0
lsl T1
brcc 3f
eor T1, xREDUCER
3: eor T1, T3
eor ST10, T1
/* invMixCol (Row) 2 */
/* preparing */
mov T0, ST23
eor T0, ST22 ; T0 = t
mov T1, ST20
eor T1, ST21 ; T1 = u
mov T2, T0
eor T2, T1
mov B, T2
ldi A, 0x08
rcall gf256mul
eor T2, P ; T2 = v'
mov B, ST22
eor B, ST20
ldi A, 0x04
rcall gf256mul
mov T3, P
eor T3, T2; T3 = w
mov B, ST23
eor B, ST21
ldi A, 0x04
rcall gf256mul
eor T2, P ; T2 = v
/* now the big move */
mov T4, ST20
eor T4, ST23
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST23, T4
mov T4, ST22
eor T4, ST21
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST21, T4
lsl T0
brcc 3f
eor T0, xREDUCER
3: eor T0, T3
eor ST22, T0
lsl T1
brcc 3f
eor T1, xREDUCER
3: eor T1, T3
eor ST20, T1
/* invMixCol (Row) 3 */
/* preparing */
mov T0, ST33
eor T0, ST32 ; T0 = t
mov T1, ST30
eor T1, ST31 ; T1 = u
mov T2, T0
eor T2, T1
mov B, T2
ldi A, 0x08
rcall gf256mul
eor T2, P ; T2 = v'
mov B, ST32
eor B, ST30
ldi A, 0x04
rcall gf256mul
mov T3, P
eor T3, T2; T3 = w
mov B, ST33
eor B, ST31
ldi A, 0x04
rcall gf256mul
eor T2, P ; T2 = v
/* now the big move */
mov T4, ST30
eor T4, ST33
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST33, T4
mov T4, ST32
eor T4, ST31
lsl T4
brcc 3f
eor T4, xREDUCER
3: eor T4, T2
eor ST31, T4
lsl T0
brcc 3f
eor T0, xREDUCER
3: eor T0, T3
eor ST32, T0
lsl T1
brcc 3f
eor T1, xREDUCER
3: eor T1, T3
eor ST30, T1
rjmp 1b
|
ahtn/keyplus
| 3,662
|
ports/atmega8/aes/avr-crypto-lib/avr-asm-macros.S
|
/* avr-asm-macros.S */
/*
This file is part of the AVR-Crypto-Lib.
Copyright (C) 2006-2015 Daniel Otte (bg@nerilex.org)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* File: avr-asm-macros.S
* Author: Daniel Otte
* Date: 2008-08-13
* License: GPLv3 or later
* Description: some macros which are quite usefull
*
*/
//#ifndef AVR_ASM_MACROS__S__
//#define AVR_ASM_MACROS__S__
.nolist
#include <avr/io.h>
.list
/*******************************************************************************
* MACRO SECTION *
*******************************************************************************/
.macro push_ p1:req, p2:vararg
push \p1
.ifnb \p2
push_ \p2
.endif
.endm
.macro pop_ p1:req, p2:vararg
pop \p1
.ifnb \p2
pop_ \p2
.endif
.endm
.macro push_range from:req, to:req
push \from
.if \to-\from
push_range "(\from+1)",\to
.endif
.endm
.macro pop_range from:req, to:req
pop \to
.if \to-\from
pop_range \from,"(\to-1)"
.endif
.endm
.macro stack_alloc size:req, reg1=r30, reg2=r31
in r0, _SFR_IO_ADDR(SREG)
in \reg1, _SFR_IO_ADDR(SPL)
in \reg2, _SFR_IO_ADDR(SPH)
sbiw \reg1, \size
cli
out _SFR_IO_ADDR(SPH), \reg2
out _SFR_IO_ADDR(SREG), r0
out _SFR_IO_ADDR(SPL), \reg1
.endm
.macro stack_free size:req, reg1=r30, reg2=r31
in r0, _SFR_IO_ADDR(SREG)
in \reg1, _SFR_IO_ADDR(SPL)
in \reg2, _SFR_IO_ADDR(SPH)
adiw \reg1, \size
cli
out _SFR_IO_ADDR(SPH), \reg2
out _SFR_IO_ADDR(SREG), r0
out _SFR_IO_ADDR(SPL), \reg1
.endm
.macro stack_alloc_large size:req, reg1=r30, reg2=r31
in r0, _SFR_IO_ADDR(SREG)
in \reg1, _SFR_IO_ADDR(SPL)
in \reg2, _SFR_IO_ADDR(SPH)
subi \reg1, lo8(\size)
sbci \reg2, hi8(\size)
cli
out _SFR_IO_ADDR(SPH), \reg2
out _SFR_IO_ADDR(SREG), r0
out _SFR_IO_ADDR(SPL), \reg1
.endm
.macro stack_free_large size:req, reg1=r30, reg2=r31
in r0, _SFR_IO_ADDR(SREG)
in \reg1, _SFR_IO_ADDR(SPL)
in \reg2, _SFR_IO_ADDR(SPH)
adiw \reg1, 63
adiw \reg1, (\size-63)
cli
out _SFR_IO_ADDR(SPH), \reg2
out _SFR_IO_ADDR(SREG), r0
out _SFR_IO_ADDR(SPL), \reg1
.endm
.macro stack_free_large2 size:req, reg1=r30, reg2=r31
in r0, _SFR_IO_ADDR(SREG)
in \reg1, _SFR_IO_ADDR(SPL)
in \reg2, _SFR_IO_ADDR(SPH)
adiw \reg1, 63
adiw \reg1, 63
adiw \reg1, (\size-63*2)
cli
out _SFR_IO_ADDR(SPH), \reg2
out _SFR_IO_ADDR(SREG), r0
out _SFR_IO_ADDR(SPL), \reg1
.endm
.macro stack_free_large3 size:req, reg1=r30, reg2=r31
in r0, _SFR_IO_ADDR(SREG)
in \reg1, _SFR_IO_ADDR(SPL)
in \reg2, _SFR_IO_ADDR(SPH)
push r16
push r17
ldi r16, lo8(\size)
ldi r17, hi8(\size)
add \reg1, r16
adc \reg2, r17
pop r17
pop r16
cli
out _SFR_IO_ADDR(SPH), \reg2
out _SFR_IO_ADDR(SREG), r0
out _SFR_IO_ADDR(SPL), \reg1
.endm
/*******************************************************************************
* END of MACRO SECTION *
*******************************************************************************/
//#endif /* AVR_ASM_MACROS__S__ */
|
ahtn/keyplus
| 3,635
|
ports/atmega8/aes/avr-crypto-lib/aes_aleph_keyschedule-asm.S
|
/* aes_keyschedule-asm */
/*
This file is part of the AVR-Crypto-Lib.
Copyright (C) 2006-2015 Daniel Otte (bg@nerilex.org)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* \file aes_keyschedule-asm.S
* \email bg@nerilex.org
* \author Daniel Otte
* \date 2009-01-09
* \license GPLv3 or later
*
*/
#include "avr-asm-macros.S"
.global aes256_init
aes256_init:
movw r20, r22
ldi r23, hi8(256)
ldi r22, lo8(256)
rjmp aes_init
.global aes192_init
aes192_init:
movw r20, r22
ldi r23, hi8(192)
ldi r22, lo8(192)
rjmp aes_init
.global aes128_init
aes128_init:
movw r20, r22
clr r23
ldi r22, 128
/*
void aes_init(const void *key, uint16_t keysize_b, aes_genctx_t *ctx){
uint8_t hi,i,nk, next_nk;
uint8_t rc=1;
uint8_t tmp[4];
nk=keysize_b>>5; / * 4, 6, 8 * /
hi=4*(nk+6+1);
memcpy(ctx, key, keysize_b/8);
next_nk = nk;
for(i=nk;i<hi;++i){
*((uint32_t*)tmp) = ((uint32_t*)(ctx->key[0].ks))[i-1];
if(i!=next_nk){
if(nk==8 && i%8==4){
tmp[0] = pgm_read_byte(aes_sbox+tmp[0]);
tmp[1] = pgm_read_byte(aes_sbox+tmp[1]);
tmp[2] = pgm_read_byte(aes_sbox+tmp[2]);
tmp[3] = pgm_read_byte(aes_sbox+tmp[3]);
}
} else {
next_nk += nk;
aes_rotword(tmp);
tmp[0] = pgm_read_byte(aes_sbox+tmp[0]);
tmp[1] = pgm_read_byte(aes_sbox+tmp[1]);
tmp[2] = pgm_read_byte(aes_sbox+tmp[2]);
tmp[3] = pgm_read_byte(aes_sbox+tmp[3]);
tmp[0] ^= rc;
rc<<=1;
}
((uint32_t*)(ctx->key[0].ks))[i] = ((uint32_t*)(ctx->key[0].ks))[i-nk]
^ *((uint32_t*)tmp);
}
}
*/
SBOX_SAVE0 = 14
SBOX_SAVE1 = 15
XRC = 17
NK = 22
C1 = 18
NEXT_NK = 19
HI = 23
T0 = 20
T1 = 21
T2 = 24
T3 = 25
/*
* param key: r24:r25
* param keysize_b: r22:r23
* param ctx: r20:r21
*/
.global aes_init
aes_init:
push_range 14, 17
push r28
push r29
movw r30, r20
movw r28, r20
movw r26, r24
lsr r23
ror r22
lsr r22
lsr r22 /* r22 contains keysize_b/8 */
mov C1, r22
1: /* copy key to ctx */
ld r0, X+
st Z+, r0
dec C1
brne 1b
lsr NK
lsr NK
/* NK is now the number of 32-bit words in the supplied key */
bst NK, 3 /* set T if NK==8 */
mov NEXT_NK, NK
mov HI, NK
subi HI, -7 /* HI += 7 */
lsl HI
lsl HI
movw r26, r30
sbiw r26, 4
mov C1, NK
ldi XRC, 1
1:
ld T0, X+
ld T1, X+
ld T2, X+
ld T3, X+
cp NEXT_NK, C1
breq 2f
brtc 5f
mov r16, C1
andi r16, 0x07
cpi r16, 0x04
brne 5f
rcall substitute
rjmp 5f
2:
add NEXT_NK, NK
rcall substitute
mov r16, T0
mov T0, T1
mov T1, T2
mov T2, T3
mov T3, r16
eor T0, XRC
lsl XRC
brcc 3f
ldi XRC, 0x1b
3:
5:
movw r30, r26
ld r0, Y+
eor r0, T0
st Z+, r0
ld r0, Y+
eor r0 ,T1
st Z+, r0
ld r0, Y+
eor r0, T2
st Z+, r0
ld r0, Y+
eor r0, T3
st Z+, r0
/*
st Z+, T0
st Z+, T1
st Z+, T2
st Z+, T3
*/
inc C1
cp C1, HI
breq 6f
rjmp 1b
6:
clt
pop r29
pop r28
pop_range 14, 17
ret
substitute:
ldi r31, hi8(aes_sbox)
mov r30, T0
lpm T0, Z
mov r30, T1
lpm T1, Z
mov r30, T2
lpm T2, Z
mov r30, T3
lpm T3, Z
ret
|
ahtn/keyplus
| 2,895
|
ports/atmega8/aes/avr-crypto-lib/aes_aleph_enc-asm.S
|
/* aes_enc-asm.S */
/*
This file is part of the AVR-Crypto-Lib.
Copyright (C) 2006-2015 Daniel Otte (bg@nerilex.org)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* \file aes_enc-asm.S
* \email bg@nerilex.org
* \author Daniel Otte
* \date 2009-01-10
* \license GPLv3 or later
*
*/
#include "avr-asm-macros.S"
xtime:
lsl r24
brcc 1f
eor r24, r27
1:
ret
shift_offset_table:
.byte 12, 8, 4, 0
.byte 9, 5, 1, 13
.byte 6, 2, 14, 10
.byte 3, 15, 11, 7
.global aes256_enc
aes256_enc:
ldi r20, 14
rjmp aes_encrypt_core
.global aes192_enc
aes192_enc:
ldi r20, 12
rjmp aes_encrypt_core
.global aes128_enc
aes128_enc:
ldi r20, 10
/*
void aes_encrypt_core(aes_cipher_state_t *state, const aes_genctx_t *ks, uint8_t rounds)
*/
/*
* param state: r24:r25
* param ks: r22:r23
* param rounds: r20
*/
.global aes_encrypt_core
aes_encrypt_core:
push r3
push r16
push r17
push r28
push r29
mov r3, r20
clt
movw r28, r24
x:
movw r24, r28
key_add:
clr r21
ldi r20, 16
call memxor
movw r22, r26 /* switch to next roundkey; r26 points after the end of src after memxor ;-) */
brtc sub_shift_bytes
4:
pop r29
pop r28
pop r17
pop r16
pop r3
ret
sub_shift_bytes:
ldi r30, lo8(shift_offset_table)
ldi r31, hi8(shift_offset_table)
ldi r20, 4 /* load counter for columns (rows in spec) */
movw r24, r28
1:
ldi r21, 4
2:
ld r16, Y
adiw r28, 4
push r16
dec r21
brne 2b
ldi r21, 4
2:
pop r16
movw r26, r24
lpm r0, Z+
add r26, r0
adc r27, r1
st X, r16
dec r21
brne 2b
sbiw r28, 15
dec r20
brne 1b
sbiw r28, 4 /* set Y back to the start of state */
dec r3
brne mix_rows
set
mix_rows:
ldi r31, hi8(aes_sbox)
ldi r27, 0x1B
ldi r20, 4
1:
ldd r30, Y+0
lpm r16, Z
ldd r30, Y+1
lpm r17, Z
ldd r30, Y+2
lpm r18, Z
ldd r30, Y+3
lpm r19, Z
brts 2f
mov r26, r16
mov r24, r16
eor r24, r17
mov r21, r24
eor r21, r18
eor r21, r19
rcall xtime
eor r16, r24
eor r16, r21
mov r24, r17
eor r24, r18
rcall xtime
eor r17, r24
eor r17, r21
mov r24, r18
eor r24, r19
rcall xtime
eor r18, r24
eor r18, r21
mov r24, r19
eor r24, r26
rcall xtime
eor r19, r24
eor r19, r21
2:
st Y+, r16
st Y+, r17
st Y+, r18
st Y+, r19
dec r20
brne 1b
sbiw r28, 16
rjmp x
|
ahtn/keyplus
| 2,588
|
ports/atmega8/aes/avr-crypto-lib/aes_invsbox-asm.S
|
/* aes_sbox-asm.S */
/*
This file is part of the AVR-Crypto-Lib.
Copyright (C) 2006-2015 Daniel Otte (bg@nerilex.org)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* \file aes_dec-asm.S
* \email bg@nerilex.org
* \author Daniel Otte
* \date 2009-01-10
* \license GPLv3 or later
*
*/
.balign 256
.global aes_invsbox
aes_invsbox:
.byte 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb
.byte 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb
.byte 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e
.byte 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25
.byte 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92
.byte 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84
.byte 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06
.byte 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b
.byte 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73
.byte 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e
.byte 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b
.byte 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4
.byte 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f
.byte 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef
.byte 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61
.byte 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
|
ahtn/keyplus
| 10,928
|
ports/atmega32u4/bootloaders/atmel_dfu/dfu_driver.S
|
;*A**************************************************************************
; $RCSfile: flash_boot_drv.s90,v $
;----------------------------------------------------------------------------
; Copyright (c) Atmel.
;----------------------------------------------------------------------------
; RELEASE: $Name: $
; REVISION: $Revision: 1.7 $
; FILE_CVSID: $Id: flash_boot_drv.s90,v 1.7 2005/10/03 15:50:12 $
;----------------------------------------------------------------------------
; PURPOSE:
; This file contains the low level driver for the flash access
;****************************************************************************
NAMEflash_drv(16)
;_____ I N C L U D E S ______________________________________________________
#define ASM_INCLUDE
#include "config.h"
;************************************************************************** **
; This is the absolute table entry points for low level flash drivers
; This table defines the entry points that can be called
; from the application section to perform on-chip flash operations:
;
; entry_flash_page_erase_and_write:
; R18:17:R16: The byte address of the page
;
; entry_flash_fill_temp_buffer:
; data16 : R16/R17: word to load in the temporary buffer.
; address: R18/R19: address of the word in the temp. buffer.
;
; entry_flash_prg_page:
; R18:17:R16: The byte address of the page
;
; entry_flash_page_erase:
; R18:17:R16: The byte address of the page
;
;************************************************************************** **
ASEG FLASH_END-0x0001B
entry_flash_page_erase_and_write:
JMP flash_page_erase_and_write
entry_flash_read_sig:
JMP flash_read_sig
entry_flash_read_fuse:
JMP flash_read_fuse
entry_flash_fill_temp_buffer:
JMP flash_fill_temp_buffer
entry_flash_prg_page:
JMP flash_prg_page
entry_flash_page_erase:
JMP flash_page_erase_public
entry_lock_wr_bits:
JMP lock_wr_bits
RSEGBOOT
;*F**************************************************************************
; NAME: flash_page_erase_and_write
;----------------------------------------------------------------------------
; PARAMS: R18:17:R16: The byte address of the page
;----------------------------------------------------------------------------
; PURPOSE: This function can be called for the user appplication
; This function performs an erase operation of the selected target page and
; the launch the prog sequence of the same target page.
; This function allows to save the 256 bytes software temporary buffer in
; the application section
;****************************************************************************
flash_page_erase_and_write:
PUSH R18
RCALL flash_page_erase
POP R18
RCALL flash_prg_page
RET
;*F**************************************************************************
; NAME: flash_prg_page
;----------------------------------------------------------------------------
; PARAMS: R18:17:R16: The byte address of the page
;----------------------------------------------------------------------------
; PURPOSE: Launch the prog sequence of the target pag
;****************************************************************************
flash_prg_page:
RCALL WAIT_SPMEN ;Wait for SPMEN flag cleared
MOV R31,R17
MOV R30,R16 ;move adress to z pointer (R31=ZH R30=ZL)
OUT RAMPZ, R18
LDI R20,$05 ;(1<<PGWRT) + (1<<SPMEN))
OUT SPMCSR,R20; argument 2 decides function (r18)
SPM ;Store program memory
RCALL WAIT_SPMEN ;Wait for SPMEN flag cleared
RCALL flash_rww_enable
RET
;*F**************************************************************************
; NAME: flash_page_erase
;----------------------------------------------------------------------------
; PARAMS: R18:17:R16: The byte address of the page
;----------------------------------------------------------------------------
; PURPOSE: Launch the erase sequence of the target page
;----------------------------------------------------------------------------
; NOTE: This function does nt set the RWWSE bit after erase. Thus it does
not
; erase the hardware temporary temp buffer.
; This function is for bootloader usage
;----------------------------------------------------------------------------
; REQUIREMENTS:
;****************************************************************************
flash_page_erase:
RCALL WAIT_SPMEN ;Wait for SPMEN flag cleared
MOV R31,R17
MOV R30,R16 ;move adress to z pointer (R31=ZH R30=ZL)
OUT RAMPZ, R18
LDI R20,$03 ;(1<<PGERS) + (1<<SPMEN)))
OUT SPMCSR, R20; argument 2 decides function (r18)
SPM ;Store program memory
RCALL WAIT_SPMEN ;Wait for SPMEN flag cleared
;RCALL flash_rww_enable CAUTION DO NOT ACTIVATE HERE or
; you will loose the entire page buffer content !!!
RET
;*F**************************************************************************
; NAME: flash_page_erase_public
;----------------------------------------------------------------------------
; PARAMS: R18:17:R16: The byte address of the page
;----------------------------------------------------------------------------
; PURPOSE: Launch the erase sequence of the target page
;----------------------------------------------------------------------------
; NOTE: !!!!This function set the RWWSE bit after erase. Thus it
; erase the hardware temporary temp buffer after page erase
;****************************************************************************
flash_page_erase_public:
RCALL WAIT_SPMEN ;Wait for SPMEN flag cleared
MOV R31,R17
MOV R30,R16 ;move adress to z pointer (R31=ZH R30=ZL)
OUT RAMPZ, R18
LDI R20,$03 ;(1<<PGERS) + (1<<SPMEN)))
OUTSPMCSR, R20; argument 2 decides function (r18)
SPM ;Store program memory
RCALL WAIT_SPMEN ;Wait for SPMEN flag cleared
RCALL flash_rww_enable
RET
;*F**************************************************************************
; NAME: flash_rww_enable
;----------------------------------------------------------------------------
; PARAMS: none
;----------------------------------------------------------------------------
; PURPOSE: Set RWSE bit. It allows to execute code in the application
section
; after a flash prog (erase or write page)
;****************************************************************************
flash_rww_enable:
RCALL WAIT_SPMEN ;Wait for SPMEN flag cleared
LDI R20,$11 ;(1<<WWSRE) + (1<<SPMEN)))
OUT SPMCSR, R20 ; argument 2 decides function (r18)
SPM ;Store program memory
RJMP WAIT_SPMEN ;Wait for SPMEN flag cleare
;*F**************************************************************************
; NAME: flash_read_sig
;----------------------------------------------------------------------------
; PARAMS:
; Return: R16: signature value
;----------------------------------------------------------------------------
; PURPOSE: Read harware signature byte. THe byte is selected trought the
addr
; passed as argument (see product data sheet)
;****************************************************************************
flash_read_sig:
RCALL WAIT_SPMEN ;Wait for SPMEN flag cleared
MOV R31,R17
MOV R30,R16 ;move adress to z pointer (R31=ZH R30=ZL)
OUT RAMPZ, R18
LDI R20,$21 ;(1<<SPMEN) | (1<<SIGRD))
OUT SPMCSR, R20; argument 2 decides function (r18)
LPM ;Store program memory
MOV R16, R0 ;Store return value (1byte->R16 register)
RJMP WAIT_SPMEN ;Wait for SPMEN flag cleared
;*F**************************************************************************
; NAME: flash_read_fuse
;----------------------------------------------------------------------------
; Return: R16: fuse value
;----------------------------------------------------------------------------
; PURPOSE: Read fuse byte. The fuse byte is elected through the address
passed
; as argument (See product datasheet for addr value)
;****************************************************************************
flash_read_fuse:
RCALL WAIT_SPMEN ;Wait for SPMEN flag cleared
MOV R31,R17
MOV R30,R16 ;move adress to z pointer (R31=ZH R30=ZL)
OUT RAMPZ, R18
LDI R20,$09 ;(1<<SPMEN) | (1<<BLBSET))
OUT SPMCSR, R20; argument 2 decides function (r18)
LPM ;Store program memory
MOV R16, R0 ;Store return value (1byte->R16 register)
RJMP WAIT_SPMEN ;Wait for SPMEN flag cleared
/*F**************************************************************************
* NAME: flash_fill_temp_buffer
*----------------------------------------------------------------------------
* PARAMS:
* data16 : R16/R17: word to load in the temporary buffer.
* address: R18/R19: address of the word.
* return: none
*----------------------------------------------------------------------------
* PURPOSE:
* This function allows to load a word in the temporary flash buffer.
*----------------------------------------------------------------------------
* EXAMPLE:
* fill_temp_buffer(data16, address);
*----------------------------------------------------------------------------
* NOTE:
* the first paramater used the registers R16, R17
* The second parameter used the registers R18, R19
*****************************************************************************/
flash_fill_temp_buffer:
MOV R31,R19 ;move adress to z pointer (R31=ZH R30=ZL)
MOV R30,R18
MOV R0,R17 ;move data16 to reg 0 and 1
MOV R1,R16
LDI R20,(1<<SPMEN)
OUT SPMCSR, R20; r18 decides function
SPM ; Store program memory
RJMP WAIT_SPMEN ; Wait for SPMEN flag cleared
;*F**************************************************************************
; NAME: lock_wr_bits
;----------------------------------------------------------------------------
; PARAMS: R16: value to write
;----------------------------------------------------------------------------
; PURPOSE:
;****************************************************************************
lock_wr_bits:
RCALL WAIT_SPMEN ; Wait for SPMEN flag cleared
MOV R0,R16
LDI R18,((1<<BLBSET)|(1<<SPMEN))
OUT SPMCSR, R18 ; r18 decides function
SPM ; write lockbits
RJMP WAIT_SPMEN ; Wait for SPMEN flag cleared
;*F**************************************************************************
; NAME: wait_spmen
;----------------------------------------------------------------------------
; PARAMS: none
;----------------------------------------------------------------------------
; PURPOSE: Performs an active wait on SPME flag
;****************************************************************************
WAIT_SPMEN:
MOVR0, R18
INR18, SPMCSR ; get SPMCR into r18
SBRC R18,SPMEN
RJMP WAIT_SPMEN ; Wait for SPMEN flag cleared
MOVR18, R0
RET
END
|
AhmetEkmell/Ders-Notlari
| 1,128
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Arrays4.s
|
.data
liste: .word 'a','b','g','c','c','f'
char: .byte 'c'
size: .word 6
ileti: .asciiz "\nprogram sonlandi"
temp: .byte 'z'
.text
main:
jal subFunction
li $v0,4
la $a0,ileti
syscall
j exit
subFunction:
la $t0,liste # t3 registerine list in adresi geldi.
lw $t1,size # dizi boyutu hafizan geldi.
lb $t2,char # kontrolu yapilacak karakter hafizadan getirildi.
li $t7,0 # count yani return 0
li $t3,0 # i = 0
loop:
bge $t3,$t1,donguden_cik # i > size(dizi boyutu)
sll $t4,$t3,2 # i * 4
addu $t4,$t4,$t0 # t4 = list[i] adresi geldi.
lw $t6,0($t4) # t6 = list[i] oldu.
add $s2,$t6,$zero # dizi elemanlarini gecici bir diziye atiyorum.
sb $s2,temp
bne $t6,$t2,loop_skip # list[i] != c ise loop_skip e git.
addi $t7,$t7,1 # count++
add $v0,$t7,$zero # return count
loop_skip:
addi $t3,$t3,1 # i++
li $v0,4 # dizi elemanlari ekrana yazdiriyorum.
la $a0,temp
syscall
j loop
donguden_cik:
jr $ra # main de kaldigin yere git.
exit:
li $v0,10 # programi sonlandir
syscall
|
AhmetEkmell/Ders-Notlari
| 1,376
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/UEodev2Cevabi.s
|
.data
.text
# Bu soruda 10000000H adresli dizide 10 sayinin tanımlı oldugu
# dusunulerek yapildi.
main:
addi $t0,$zero,0x10000000 # dizi baslangic adresi
addi $t1,$zero,0x10005000 # sayi > 0 ise dizisi
addi $t2,$zero,0x10006000 # sayi < 0 ise dizisi
addi $s0,$zero,0 # dizi indeksi i = 0
addi $s1,$zero,10 # dizi uzunlugu = 10
dongu:
bgt $s0,$s1,exit # eger i > diziUzunluk ise exit e git
sll $t1,$s0,2 # i * 4
add $t2,$t1,$t0 # dizi[i] adresi geldi
lw $t3,0($t2) # dizimizin elemanlari sirasiyla t3 registerine gelecek.
bltz $t3,kucukSayilar # $t5 < 0 ise etikete git
bgtz $t3,buyukSayilar # $t5 > 0 ise etikete git
buyukSayilar:
sll $t4,$s0,2 # t4 = i*4
add $t4,$t4,$t1 # t4 = buyukSayilar[i] adresi
sw $t3,0($t4) # t3 de bulunan sayi 0 dan buyuk oldugundan t4 registerinde yer alan dizi adresimize sayı taşınıyor.
addi $s0,$s0,1 # indeks++ yani i++
j dongu # dongu ye sartsiz dallan
kucukSayilar:
sll $t5,$s0,2 # t5 = i*4
add $t5,$t5,$t2 # t5 = kucukSayilar[i] adresi
sw $t3,0($t5) # t3 de bulunan sayi 0 dan buyuk oldugundan t5 registerinde yer alan dizi adresimize sayı taşınıyor.
addi $s0,$s0,1 # indeks++ yani i++
j dongu # dongu ye sartsiz dallan
exit:
li $v0,10 # programı sonlandır.
syscall
|
AhmetEkmell/Ders-Notlari
| 1,101
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/UEodev1Cevabi.s
|
.data
dizi: .word 1000
.text
subProcedure:
addi $sp,$sp,-8 # s registerlerini kullandigim icin
sw $s0,4($sp) # yedekleme islemi yaptim
sw $s1,0($sp)
lw $s0,dizi($zero) # s0 = 10000000H adres
addi $s1,$zero,0 # sonuc = 0
addi $t0,$zero,1 # i = 1
addi $t1,$zero,0 # siradaki = 0
addi $s2,$zero,10 # uzunluk = 10
forDongusu:
sll $t3,$t0,2 # i*4
add $t5,$t3,$s0 # t5 = dizi[i] nin adresi
lw $t6,0($t5) # t6 = dizi[i] elemani var.
add $t1,$t1,$t6 # siradaki = dizi[0]
blt $t0,$s2,kontrol # i < uzunluk ise kontrole git.
j exit
kontrol:
blt $t1,$t6,esit # siradaki < dizi[i] ise esit etiketine git
j exit # eger dizi sirali degilse zaten exit e gidecek ve sonuc = 0 yazacak.
esit:
addi $s1,$s1,1 # sonuc = 1 yapiliyor
j forDongusu # tekrar dizi kontrolu icin donguye giriliyor
exit:
add $v0,$zero,$s1 # sonuc degerimiz hangi degere yani 1 veya 0 a sahipsa o deger return ediliyor.
lw $s1,4($sp)
lw $s0,0($sp) # stack eski haline getiriliyor.
addi $sp,$sp,8
jr $ra # ana programda kaldigin yer+4. satira git.
|
AhmetEkmell/Ders-Notlari
| 2,314
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/RecursiveFunction.s
|
.data
EkranaSayiGirisi: .asciiz "Lutfen sayi girisi yapiniz => "
EkranaSonucYaz: .asciiz "Girilen sayinin faktoriyeli => "
sayi: .word 0
sonuc: .word 0
.text
.globl main
main:
li $v0,4 # Ekranda kullaniciya uyari mesaji veriliyor
la $a0,EkranaSayiGirisi
syscall
li $v0,5 # Kullanici bir sayi girisi yapiyor
syscall
sw $v0,sayi # Kullanicinin girdigi sayi, sayi etiketimize kaydediliyor.
lw $a0,sayi # Daha sonra bu sayiyi kullanmak özere lw komutu ile tekrar hafizadan getirdik.
jal FaktoriyelHesapla # girdigimiz sayinin faktoriyelini hesaplama uzere dallaniyoruz.
sw $v0,sonuc # FaktoriyelHesapla metodunun en son sonucu v0 registeri ile sonuc etiketine kaydediliyor.
li $v0,4 # Ekrana String ifademiz yazdiriliyor.
la $a0,EkranaSonucYaz
syscall
li $v0,1 # Ardindan Ekrana kullanicinin girmis oldugu sayinin faktoriyel hesabinin sonucu ekrana yazdiriliyor.
lw $a0,sonuc
syscall
li $v0,10
syscall
#---------------------------------------------
#Faktoriyel Hesaplama kismi
.globl FaktoriyelHesapla
FaktoriyelHesapla:
subu $sp,$sp,8 # Stack de ra registeri ve s0 registeri icin yer aciyoruz. Videolu anlatimlarimda bu kisimlari aciklayacagim.
sw $ra,0($sp)
sw $s0,4($sp)
li $v0,1 #simdi kullanici yukarida bir sayi girmisti o sayiyi burada kontrol ediyoruz eger sayimiz 0 a esitse Faktoriyel bitecek.
beq $a0,0,FaktoriyelBitir
move $s0,$a0 # s0 registerine yukarida girdigimiz sayi atandi.
# burada aslinda yapilan islem su => n * FaktoriyelHesapla(n-1) islemi
sub $a0,$a0,1
jal FaktoriyelHesapla
mul $v0,$s0,$v0
FaktoriyelBitir:
# son olarak metotdan cikarken stack eski haline geri getiriliyor.
lw $ra,0($sp)
lw $s0,4($sp)
addu $sp,$sp,8
jr $ra # aslinda carpma islemine buradan gidiliyor stack her eski haline donerken v0 degerlerini carpmak uzere mul komutuna gidiyor
# ve en son main metodun da nerede kaldiysa oraya gidiyor ve programi sonlandiriyor.
# bu kisimlari videolu bir sekilde youtube üzerinde anlatacagim ilgilenen arkadaslar Ahmet Yesilyurt isimli kanalimi takip edebilirler.
#kanal linki => https://www.youtube.com/channel/UCyWYkM9_-gtdzf0Odd_RY7Q?view_as=subscriber
|
AhmetEkmell/Ders-Notlari
| 1,147
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/nestedProcedure.s
|
.data
altSatir: .asciiz "\n"
.text
main:
addi $s0,$zero,60 # s0 = 60
jal metot # sartsiz metot a dallan
li $v0,4 # metot da isin bittikten sonra bu satira gel ve \n yap
la $a0,altSatir
syscall
jal ekranaYazdirMetodu # main metodunda ki s0 register degeri yani 60 ı ekrana yazmak için ekranaYazdirMetodu na git.
j exit # programi sonlandirmak için exit etiketine git.
metot:
addi $sp,$sp,-8 # ic ice procedure kullandigimizdan dolayı ra registerini de yedeklememiz gerekiyor.
sw $ra,4($sp)
sw $s0,0($sp)
addi $s0,$s0,40 # s0 registerine bu metot da 100 degeri atandı.
jal ekranaYazdirMetodu # belirtilen etikete git ve ekrana bu metodun yani 100 degerini ekrana yaz.
lw $s0,0($sp) # ekrana yazma isleminden sonra stack eski haline getir.
lw $ra,4($sp)
addi $sp,$sp,8
jr $ra # main metodun da kaldığın yerden+4 devam et.
ekranaYazdirMetodu:
li $v0,1 # s0 register degerleri ekrana yazdirma islemi yapiliyor.
move $a0,$s0
syscall
jr $ra # metot isimli etikette kaldigin yerden+4 devam et.
exit:
li $v0,10 # programı sonlandir.
syscall
|
AhmetEkmell/Ders-Notlari
| 1,400
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/ABS.s
|
#Firat University the dept. of Computer Engineering
#Lesson ..: Example of multiplication without using the multiplication operator "*". (For the 32-bits results)
# Remark: Note that the numbers entered are positive or negative, because it will affect the result
# As you guess, we will use addition operation and a loop
# Don' use stack for the saved register (for this question, there is no need)
#-----------------------------------------------------------
.data #the global variable field
#For text printing
SystemMessage1: .asciiz "Enter the number : "
SystemMessageF: .asciiz "The answer : "
NextLine: .ascii "\n"
#------------------------------------------------------------
.text #the user codes
main:
li $v0,4
la $a0,SystemMessage1
syscall
li $v0,5
syscall
move $t0, $v0
slt $t7, $t0, $zero
beq $t7, 1, CH # negatif ise CH ye dallan ve pozitif yap
j PRINT # zaten positif ise sadece ekrana yaz
CH: sub $t0,$zero,$t0
#veya
# nor $t0,$t0,0
# addi $t0,$t0,1
PRINT:
li $v0, 4
la $a0, SystemMessageF
syscall
li $v0, 1
move $a0, $t0
syscall
#--------------------------------------------------------------
#terminate the main program
li $v0,10 # For exit, load 10 decimal into v0
syscall # Execute the last operation
#--------------------------------------------------------------
|
AhmetEkmell/Ders-Notlari
| 3,149
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/DiziElemanArttir.s
|
#Lesson ..: Bu örnekte kullanıcıdan alınan 10 tane intieger degerden bir dizi olusturulacak ve her bir elemanı
# bir arttiran bir alt program cagrilacak donuste bu dizi ekrana yazdirilacak
#-----------------------------------------------------------
.data #the global variable field
dizi: .space 40 #10 tane integer elemanlı bir dizi alanı olustur (int 4 byte böylece toplam alan 40 byte)
SystemMessage1: .asciiz "Bir integer deger giriniz : "
SystemMessageF: .asciiz "Dizinin son hali: "
#------------------------------------------------------------
.text #the user codes
main:
# dizide index takibi için bir register kullanalım, t0 olsun mesela, başlangıç değeri 0
li $t0,0
Loop:
li $v0, 4 # Ekrana text yazmak için
la $a0, SystemMessage1
syscall
#Girilen değeri al
li $v0, 5
syscall
move $t1, $v0 # Girilen değer t1 de tutulsun
sw $t1,dizi($t0) #bu değeri dizinin o anki indeks ofset degerine gore yukle
addi $t0,$t0,4 # indeks i 4 arttır (cunku int word uzunlugundadır)
bne $t0,40, Loop
# Her bir elemanı bir arttiracak sub procedure cagir. Parametre dizinin baslangic adresi ve dizi uzunlugudur
# donus degeri v1 den alinacak ancak burada her hangi bir donus degeri kullanılmayacak bu nedenle onu kaydetmeye
# gerek yok
la $a0, dizi
li $a1, 40
jal OPR
la $a2, dizi # yazma alt programı a0 'ı başka bir iş için kullanıyor o yüzden a2 ve a3 ü kullanalim
li $a3, 40 # dizi boyutu a3 'e
jal YAZ
#--------------------------------------------------------------
#terminate the main program
li $v0,10 # For exit, load 10 decimal into v0
syscall # Execute the last operation
OPR:
# bu sub procedure s0 saved register 'ini kullanacak bu nedenle onun önceki degerini
# stack da saklayın
addi $sp, $sp, -4 # 32 bit veri için yer aç
sw $s0, 0($sp) # eski degeri stack de saklayın
li $t0, 0 #indeksi tekrar 0 'a set edelim
Loop2:
add $t1, $a0,$t0 # dizinin baslangic adresine offseti ekle
lw $s0, 0($t1) # dizinin bu adresteki degerini s0 'ye al
addi $s0, $s0,1 # bu degeri 1 arttir
sw $s0, 0($t1) # arttirilan bu degeri tekrar aynı hafiza alanina yaz
addi $t0, $t0,4 # indeks i 4 arttır (cunku int word uzunlugundadır)
bne $t0, $a1, Loop2 # dizi elemanları tamamlanana kadar donguye devam (a1=40 idi)
lw $s0, 0($sp) # cikmadan tekrar s0 'ı eski degerine set edelim
addi $sp, $sp, -4 # Acilan alani tekrar kapat
jr $ra
YAZ:
# Simdi dizinin son halini gorelim. Bu alt prosedür bunu consol a yazdiracak
# bu herhangi bir saved register kullanmıyor o nedenle stack 'i kullanmaya gerek yok
li $v0, 4 # text yaz
la $a0, SystemMessageF
syscall
li $t0, 0 #indeksi tekrar 0 'a set edelim
Loop3:
add $t2, $a2,$t0 # dizinin baslangic adresine offseti ekle
lw $t1, 0($t2) # dizinin bu adresteki degerini t1 'ye al
li $v0, 1 # int yaz
move $a0, $t1 # yazilacak degeri gonder
syscall
addi $t0, $t0,4 # indeks i 4 arttır (cunku int word uzunlugundadır)
bne $t0, $a3, Loop3 # dizi elemanları tamamlanana kadar donguye devam (a1=40 idi)
jr $ra
|
AhmetEkmell/Ders-Notlari
| 3,418
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/CarpmaPositif.s
|
#Firat University the dept. of Computer Engineering
#Lesson ..: Example of multiplication without using the multiplication operator "*". (For positive x,y and the 32-bits results)
# Remark: Note that the numbers entered are positive or negative, because it will affect the result
# As you guess, we will use addition operation and a loop
# Don' use the stack for the saved register (for this question, there is no need)
#-----------------------------------------------------------
.data #the global variable field
#For text printing
SystemMessage1: .asciiz "Enter the first number : "
SystemMessage2: .asciiz "Enter the second number : "
SystemMessageF: .asciiz "The answer : "
NextLine: .ascii "\n"
#------------------------------------------------------------
.text #the user codes
main:
# In the program, $t0=the first number, $t1= the second, $t3= the result
# we use a sub procedure for the multiplication operation
# So we will send t0 and t1 as parameters. For the return value, $v1 register will be used
# The text message that wants the first number to be entered
li $v0,4 # A text message will be written
la $a0,SystemMessage1 # ask for the base number
syscall
# get the first number
li $v0,5 # An integer will be read
syscall
move $t0, $v0 # The number entered is stored in v0, so this value is copied into another register
# The text message that wants the second number to be entered
li $v0,4 # A text message will be written
la $a0,SystemMessage1 # ask for the exponent number
syscall
# get the base number
li $v0,5 # An integer will be read
syscall
move $t1, $v0 # The number entered is stored in v0, so this value is copied into another register
#Now, let's send the parameters (Remember! a0, a1, a2 and a3 are the parameter registers)
move $a0, $t0
move $a1, $t1
jal OPR
move $t3,$v1
# Now, we can print the result
# First a an explanation message
li $v0, 4
la $a0, SystemMessageF
syscall
# the result
li $v0, 1 # for integer printing
move $a0, $t3 # print the result
syscall
# Let's put a new line
li $v0,4
la $a0,NextLine
syscall
#--------------------------------------------------------------
#terminate the main program
li $v0,10 # For exit, load 10 decimal into v0
syscall # Execute the last operation
#--------------------------------------------------------------
#Sub-procedure
OPR:
# for the operation, we will use a loop. This loop will continue "the second number" times.
# Remember! a0=the first number, a1=the second number v1=return value
beq $a0,0,AA # if the first or second number are zero, the result will be v1=0
beq $a1,0,AA
beq $a0,1,B0 # if the first is 1, the result will be the second
beq $a1,1,B1 # if the second is 1, the result will be the first
move $v1, $a0 # for the result
li $t4, 1 #for the loop counting
Loop:
add $v1, $v1, $a0 # multiply the result by itself
addi $t4, 1 # increase the loop count
slt $t5, $t4, $a1 # if the loop number is greater than the exponent,
bne $t5, 0, Loop # then exit
jr $ra #return
AA: li $v1, 0 # if the any number is zero, the result is 0
jr $ra # return
B0: move $v1, $a1 # v1= a1
jr $ra
B1: move $v1, $a0 # v1= a0
jr $ra
|
AhmetEkmell/Ders-Notlari
| 2,133
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/IfElseIf.s
|
#Firat University the dept. of Computer Engineering
#Lesson ..: J instruction and if - else if - else
#Explanation : This program check the integer entered, if the number is positive, then it increases another variable "i" by 1.
# if the number is negative, then it decreases "i" by 1. If the number is zero, it will multiply "i" by 2
# For this, we use jump instruction
#-----------------------------------------------------------
.data #the global variable field
SystemMessage1: .asciiz "Enter your number : "
SystemMessage2: .asciiz "The variable i: "
NextLine: .asciiz "\n"
#------------------------------------------------------------
.text #the user codes
main:
li $s0,20 # Assume that s0 is "i=20"
li $v0, 4 # for text printing
la $a0, SystemMessage1 # the system message address is sent to a0 paramter register (la = load address)
syscall
#Get the user input
li $v0, 5 # for int reading
syscall # the obtained value is stored in v0 again
move $t0, $v0 # So it could be copied to a temporary register
beq $t0,0,DBL # First, check the number entered is zero (WHY?)
slt $t1, $t0, $zero # check if the number is positive
beq $t1,0, INC # positive, i++
beq $t1,1, DEC # negative, i--
PRINT:
li $v0, 4 # for text printing
la $a0, SystemMessage2 # the system message address is sent to a0 paramter register (la = load address)
syscall
li $v0, 1 # for int printing
move $a0, $s0 # show the "i"
syscall
# Let's put a new line
li $v0, 4
la $a0, NextLine
syscall
#--------------------------------------------------------------
#terminate the main program
li $v0,10 # For exit, load 10 decimal into v0
syscall # Execute the last operation
#--------------------------------------------------------------
INC : addi $s0, $s0, 1
j PRINT
DEC : addi $s0, $s0, -1
j PRINT
DBL : li $t2, 2 # In MIPS, there is no "muli" instruction. You can use multi and mflo
mult $s0,$t2 # zero, i *=2
mflo $s0 # load the multiplication result into s0 again
j PRINT
|
AhmetEkmell/Ders-Notlari
| 4,800
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/CarpmaALL.s
|
#Firat University the dept. of Computer Engineering
#Lesson ..: Example of multiplication without using the multiplication operator "*". (For the 32-bits results)
# Remark: Note that the numbers entered are positive or negative, because it will affect the result
# As you guess, we will use addition operation and a loop
# Don' use stack for the saved register (for this question, there is no need)
#-----------------------------------------------------------
.data #the global variable field
#For text printing
SystemMessage1: .asciiz "Enter the first number : "
SystemMessage2: .asciiz "Enter the second number : "
SystemMessageF: .asciiz "The answer : "
NextLine: .ascii "\n"
#------------------------------------------------------------
.text #the user codes
main:
# In the program, $t0=the first number, $t1= the second, $t3= the result
# we use a sub procedure for the multiplication operation
# So we will send t0 and t1 as parameters. For the return value, $v1 register will be used
# The text message that wants the first number to be entered
li $v0,4 # A text message will be written
la $a0,SystemMessage1 # ask for the base number
syscall
# get the first number
li $v0,5 # An integer will be read
syscall
move $t0, $v0 # The number entered is stored in v0, so this value is copied into another register
# The text message that wants the second number to be entered
li $v0,4 # A text message will be written
la $a0,SystemMessage2 # ask for the exponent number
syscall
# get the base number
li $v0,5 # An integer will be read
syscall
move $t1, $v0 # The number entered is stored in v0, so this value is copied into another register
#Now, let's send the parameters (Remember! a0, a1, a2 and a3 are the parameter registers)
move $a0, $t0
move $a1, $t1
jal OPR # Brunch the sub procedure
move $t3, $v1 # copy the return value into t3
#check the sign of the answer
slt $t5, $t0, $zero # check if the first number is negative
slt $t6, $t1, $zero # check if the second number is negative
beq $t5,$t6,PRINT # Both is negative or positive, then the result is positive, do not change the sign
move $a0, $t3 # If they are not the same, then make the sign of the result negative
jal SIGN # change the sign of t3 (the result)
move $t3, $v1 # copy the return value into t3
PRINT:
# Now, we can print the result
# First a an explanation message
li $v0, 4
la $a0, SystemMessageF
syscall
# the result
li $v0, 1 # for integer printing
move $a0, $t3 # print the result
syscall
# Let's put a new line
li $v0,4
la $a0,NextLine
syscall
#--------------------------------------------------------------
#terminate the main program
li $v0,10 # For exit, load 10 decimal into v0
syscall # Execute the last operation
#--------------------------------------------------------------
SIGN:
sub $v1,$zero,$a0
jr $ra
ABS :
slt $t7, $a2, $zero
beq $t7, 1, CH
move $v1, $a2
jr $ra
CH: sub $v1,$zero,$a2
jr $ra
#Sub-procedure
OPR:
# for the operation, we will use a loop. This loop will continue "the second number" times.
# Remember! a0=the first number, a1=the second number v1=return value
# First, let's make the two coming parameters positive (because the sign will be evaluated later)
# BUT!!! Here in this sub procedure, we will call another sub procedure, that is, a nested sub procedure
# So we have to keep the $ra register in the stack (For this question saved registers are ignored)
addi $sp, $sp, -4 # for only $ra register
sw $ra, 0($sp) # store the main program return addres
move $a2, $a0 #make the first parameter positive
jal ABS
move $a0, $v1
move $a2, $a1 #make the first parameter positive
jal ABS
move $a1, $v1
lw $ra, 0($sp) # Get the main program return address
addi $sp, $sp, 4 # Close the stack field created
beq $a0,0,AA # if the first or second number are zero, the result will be v1=0
beq $a1,0,AA
beq $a0,1,B0 # if the first is 1, the result will be the second
beq $a1,1,B1 # if the second is 1, the result will be the first
move $v1, $a0 # for the result
li $t4, 1 #for the loop counting
Loop:
add $v1, $v1, $a0 # multiply the result by itself
addi $t4, 1 # increase the loop count
slt $t5, $t4, $a1 # if the loop number is greater than the exponent,
bne $t5, 0, Loop # then exit
jr $ra #return
AA: li $v1, 0 # if the any number is zero, the result is 0
jr $ra # return
B0: move $v1, $a1 # v1= a1
jr $ra
B1: move $v1, $a0 # v1= a0
jr $ra
|
AhmetEkmell/Ders-Notlari
| 1,728
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/DiziToplam.s
|
#Lesson ..: Bu örnekte kullanıcıdan alınan 10 tane intieger degerden bir dizi olusturulacak ve ekrana dizi
# elemanlarının toplamı yazılacak
#-----------------------------------------------------------
.data #the global variable field
dizi: .space 40 #10 tane integer elemanlı bir dizi alanı olustur (int 4 byte böylece toplam alan 40 byte)
SystemMessage1: .asciiz "Bir integer deger giriniz : "
SystemMessageF: .asciiz "Dizi elemanlarinin toplami: "
#------------------------------------------------------------
.text #the user codes
main:
# dizide index takibi için bir register kullanalım, t0 olsun mesela, başlangıç değeri 0
li $t0,0
Loop:
li $v0, 4 # Ekrana text yazmak için
la $a0, SystemMessage1
syscall
#Girilen değeri al
li $v0, 5
syscall
move $t1, $v0 # Girilen değer t1 de tutulsun
sw $t1,dizi($t0) #bu değeri dizinin o anki indeks ofset degerine gore yukle
addi $t0,$t0,4 # indeks i 4 arttır (cunku int word uzunlugundadır)
bne $t0,40, Loop
#Simdi toplayalım
li $s0,0 # Toplam sonucu s0 'da tutulsun
li $t0,0 # indeksi tekrar 0 a ayarlayalım
Loop2:
lw $t2,dizi($t0) #dizinin bu adresteki degerini t2 'ye al
add $s0,$s0,$t2
addi $t0,$t0,4 # indeks i 4 arttır (cunku int word uzunlugundadır)
bne $t0,40, Loop2 # dizi elemanları tamamlanana kadar donguye devam
#Sonucu yazdır
li $v0, 4 # Ekrana text yazmak için
la $a0, SystemMessageF
syscall
li $v0, 1 # Ekrana integer yazmak için
move $a0, $s0
syscall
#--------------------------------------------------------------
#terminate the main program
li $v0,10 # For exit, load 10 decimal into v0
syscall # Execute the last operation
|
AhmetEkmell/Ders-Notlari
| 1,118
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/DiziOlusturma.s
|
#Lesson ..: Bu örnekte hafızada array oluşturma yapilacaktir. Dizi değerleri klavyeden alınacaktır
#-----------------------------------------------------------
.data #the global variable field
dizi: .space 40 #10 tane integer elemanlı bir dizi alanı olustur (int 4 byte böylece toplam alan 40 byte)
SystemMessage1: .asciiz "Bir integer deger giriniz : "
#------------------------------------------------------------
.text #the user codes
main:
# dizide index takibi için bir register kullanalım, t0 olsun mesela, başlangıç değeri 0
li $t0,0
Loop:
li $v0, 4 # Ekrana text yazmak için
la $a0, SystemMessage1
syscall
#Girilen değeri al
li $v0, 5
syscall
move $t1, $v0 # Girilen değer t1 de tutulsun
sw $t1,dizi($t0) #bu değeri dizinin o anki indeks ofset degerine gore yukle
addi $t0,$t0,4 # indeks i 4 arttır (cunku int word uzunlugundadır)
bne $t0,40, Loop
#--------------------------------------------------------------
#terminate the main program
li $v0,10 # For exit, load 10 decimal into v0
syscall # Execute the last operation
|
AhmetEkmell/Ders-Notlari
| 1,067
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/faktoryel.s
|
######### $v0'a atanacak değerler ########
# #
# Konsola Yazma Konsoldan Deger Alma
# Integer 1 5
# Float 2 6
# Double 3 7
# Text 4 8
#-----------------------------------------------------------
.data #the global variable field
mesaj: .asciiz "Faktoryel Alinacak Sayi Girin: "
#------------------------------------------------------------
.text #the user codes
main:
li $v0, 4
la $a0, mesaj
syscall
#Girilen değeri al
li $v0, 5
syscall
move $a0, $v0
li $v1,1
jal fakt
#Sonuc yazdır
li $v0, 1
move $a0, $v1
syscall
bitir:
#--------------------------------------------------------------
#terminate the main program
li $v0,10 # For exit, load 10 decimal into v0
syscall # Execute the last operation
fakt:
addi $sp,$sp,-8
sw $ra,4($sp)
sw $a0,0($sp)
slti $t0,$a0,2
bne $t0,$zero,stackKapat
addi $a0,$a0,-1
jal fakt
stackKapat:
lw $ra,4($sp)
lw $a0,0($sp)
addi $sp,$sp,8
mul $v1,$a0,$v1
jr $ra
|
AhmetEkmell/Ders-Notlari
| 2,997
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/UsAlma.s
|
#Firat University the dept. of Computer Engineering
#Lesson ..: Example of exponentiation (FOR POSITIVE INTEGERS (and for the 32 bits-results ))
#-----------------------------------------------------------
.data #the global variable field
#For text printing
SystemMessage1: .asciiz "Enter the base integer : "
SystemMessage2: .asciiz "Enter the exponent : "
SystemMessageF: .asciiz "The answer : "
NextLine: .ascii "\n"
#------------------------------------------------------------
.text #the user codes
main:
# In the program, $t0=the base number, $t1= the exponent, $t3= the result
# we use a sub procedure for the exponentiation operation
# So we will send t0 and t1 as parameters. For the return value, $v1 register will be used
# The text message that wants the base number to be entered
li $v0,4 # A text message will be written
la $a0,SystemMessage1 # ask for the base number
syscall
# get the base number
li $v0,5 # An integer will be read
syscall
move $t0, $v0 # The number entered is stored in v0, so this value is copied into another register
# The text message that wants the exponent number to be entered
li $v0,4 # A text message will be written
la $a0,SystemMessage1 # ask for the exponent number
syscall
# get the exponent number
li $v0,5 # An integer will be read
syscall
move $t1, $v0 # The number entered is stored in v0, so this value is copied into another register
#Now, let's send the parameters (Remember! a0, a1, a2 and a3 are the parameter registers)
move $a0, $t0
move $a1, $t1
jal Exponentiation # Brunch the sub procedure
move $t3, $v1 # copy the result into t3
# Now, we can print the result
# First a an explanation message
li $v0, 4
la $a0, SystemMessageF
syscall
# the result
li $v0, 1 # for integer printing
move $a0, $t3 # print the result
syscall
# Let's put a new line
li $v0,4
la $a0,NextLine
syscall
#--------------------------------------------------------------
#terminate the main program
li $v0,10 # For exit, load 10 decimal into v0
syscall # Execute the last operation
#--------------------------------------------------------------
#Sub-procedure
Exponentiation:
# for the exponentiation operation, we will use a loop. This loop will continue "exponent" times.
# Remember! a0=base, a1=exponent v1=return value
beq $a1,0,AA # if the exponent is zero, the result will be v1=1
move $v1, $a0 # for the result
beq $a1,1,BB # if the exponent is 1, the result will be v1
li $t4, 1 #for the loop counting
Loop:
mul $v1, $v1, $a0 # multiply the result by itself
addi $t4, 1 # increase the loop count
slt $t5, $t4, $a1 # if the loop number is greater than the exponent,
bne $t5, 0, Loop # then exit
jr $ra #return
AA: li $v1, 1 # if the exponent is zero, the result is 1
BB: jr $ra # return
|
AhmetEkmell/Ders-Notlari
| 1,345
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/prizmalan.s
|
# Bir diktortgenler prizmasinin hacmi ve yüzey alani.
#hacim akenari(en) * bkenari(boy) *ckenari(yukseklik)
#yuzey alani = her bir yuzey alanlarinin toplami yani 2*(a*b + a*c + b*c)
#Her bir kenara ait uzunluklar hafizada (user data segment) da saklansin
.data
aSide: .word 73 #hex 0x49
bSide: .word 14 #hex 0xe
cSide: .word 16 #hex 0x10
volume: .word 0 #baslangic deger 0
surfaceArea: .word 0 #baslangic deger 0
.text
main:
#Tum islemler registerlar uzerinde olacak hatirlayiniz. Bu nedenle hafizadaki degerleri register 'lara getirelim
lw $t0, aSide
#veya
#user data segment'de bu koddan once herhangi bir veri yuklenmediginden 0x10010000 (ilk adres) aSide 'ı tutuyor olacaktir.
#Boylece soyle de yukleme yapabiliriz
#li $t8, 0x10010000 #gecici bir register 'a user data sagment 'in ilk adresini yukle
#lw $t0,0($t8)
lw $t1, bSide
lw $t2, cSide
# Simdi bu uc degeri carp ve hacmi bul
mul $t3, $t0, $t1 #once a*b yi bul ve bunun sonucu ile c yi carp
mul $t4, $t3, $t2
sw $t4, volume
# Simdi de yuzey alanini bul
mul $t3, $t0, $t1 # a*b
mul $t4, $t0, $t2 # a*c
mul $t5, $t1, $t2 # b*c
add $t6, $t3, $t4 # simdi ara toplamlari
add $t7, $t6, $t5 # hesapla ve
sll $t7,$t7,1 # 2 ile carp
sw $t7, surfaceArea
#Programi sonlandir
li $v0, 10 # call code for terminate
syscall # system call
|
AhmetEkmell/Ders-Notlari
| 2,037
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/Sirali_miEB.s
|
#Lesson ..: Bu örnekte hafızada bulunan 10 adet integer sayının büyükten kucuge sirali olup
# olmadıgi kontrol edilecektir. Bu sayılar simdilik kolaylık olsun diye data kısmına
# teker teker yazılacaktır. Siz bu sayıları değiştirerek kodu kontrol edebilirsiniz
#-----------------------------------------------------------
.data #the global variable field
n1: .word 100
n2: .word 90
n3: .word 80
n4: .word 70
n5: .word 60
n6: .word 50
n7: .word 40
n8: .word 30
n9: .word 20
n10: .word 10
SystemMessageF: .asciiz "Dizi buyukten kucuge sirali mi : "
#------------------------------------------------------------
.text #the user codes
main:
li $t3,1 # t2 true false sonuç bildirecek. Başlangıçta bu değer true =1
li $t2,1 # döngü sayısı için
#Değişkenler word tipi bu nedenle adresler 4 byte arayla artacaktır
la $t0, n1 # dizinin ilk adresini al
addi $t1,$t0,4 # bir sonraki elemanın adresi
Loop:
lw $s0,0($t0) # t0 adresindeki değeri s0 'a getir
lw $s1,0($t1) # t1 adresindeki değeri s1 'e getir
slt $s2,$s0,$s1 # s0 s1 'den küçükse s2=1
beq $s2,1,FLS # eğer kucukse False yap ve çık
addi $t0,$t0,4 # adresleri 4 arttır
addi $t1,$t1,4 # adresleri 4 arttır
addi $t2,$t2,1 # değilse döngü sayıcısını bir arttır
bne $t2, 10,Loop # döngü 1 den başladığı ve ikişer ikişer kontrol edildiği için en son 9 'a kadar
j EXT # döngü başarı ile bitmiş ise o zaman t3 değişmeden çık
FLS:
li $t3,0
EXT:
#Printing the system message
li $v0, 4 # for text printing
la $a0, SystemMessageF # the system message address is sent to a0 paramter register (la = load address)
syscall
#Printing the user input
li $v0, 1 # for int printing
move $a0, $t3 # the temporary register with the user input is sent to the paramter register (move, not la!)
syscall
#--------------------------------------------------------------
#terminate the main program
li $v0,10 # For exit, load 10 decimal into v0
syscall # Execute the last operation
|
AhmetEkmell/Ders-Notlari
| 1,757
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/dizikay.s
|
# Not:
# Bu kodalar optimize (min satir ile yapilmis) degildir.
# Amac temel operasyonlari teker teker gormek oldugundan uzun kodlama yapilmistir
.data
f: .word 10 # (ki başlangıçta 0x10010000 dir) data segment adresine 0xa yükle
g: .word 55 # (artık 0x10010004, yani başlangıçtan 4 byte sonra) hafıza adresine 0x37 yükle
y: .word 22 # (artık 0x10010008) hafıza adresine 0x16 yükle
z: .word 7 # (artık 0x1001000c) hafıza adresine 0x7 yükle
# böylece kalinan en son adresin (yani 0x100100c) nin 4 byte fazlası olacaktir yani 0x10010010
.text
main:
addi $s0,$zero,0 #baslangic deger
addi $s1,$zero,0 #baslangic deger ata
li $s1,0x10010000 #user data segment baslangic adresi, artik s1 hep bu baslangic adresini gosterecek
#veya
#lui $s1,4097 # cunku 4097 hex olarak 1001 e denk gelir
# lui bu sayiyi s1 in en değerlikli 32 bitine atar
# böylece s1= 10010000 olur yani kullanici data segment başlangici
lw $t0,0($s1) #hafızada gosterilen ilk elemani en sona eklemek icin t0 'da sakla
etiket:
addi $s0,$s0,1 #hafizada baslangic adresinden 0, 4, 8 ve 12 byte uzaga gidebilmek icin birer birer artan bir register lazim
sll $s2,$s0,2 #simdi bu degiskeni 4 ile carp ve s1 referans adresine ekleyerek bir sonraki elemanı t2 ye getir
add $t1,$s2,$s1
lw $t2,0($t1)
sw $t2,-4($t1) #simdi getirilen bu elemani bir önceki adrese yukle (ilk eleman zaten t0 a önceden alinmisti)
slti $t3,$s0,3 #en son eleman 12 byte sonra oldugu icin son elemana geldigini anlamak icin artma register 'i 3 olmusmu kontrol et
beq $t3,$zero,exit #dongu tamam' cik
j etiket
exit:
sw $t0,0($t1) #Simdi saklanan dizinin ilk elmani (t0) en son adrese yukle
li $v0,10
syscall
|
AhmetEkmell/Ders-Notlari
| 1,220
|
Bilgisayar Organizasyonu ve Tasarımı/mips kodlarım/Güngör Hocamızın mips kodları/DiziToplam1_Klasik.s
|
######### $v0'a atanacak değerler ########
# #
# Konsola Yazma Konsoldan Deger Alma
# Integer 1 5
# Float 2 6
# Double 3 7
# Text 4 8
#-----------------------------------------------------------
.data #the global variable field
SystemMessage1: .asciiz "Bir integer deger giriniz : "
SystemMessageF: .asciiz "Dizi elemanlarinin toplami: "
#------------------------------------------------------------
.text #the user codes
main:
li $t0,0x10010050
li $t8,0
#deger al
Loop:
li $v0, 4
la $a0, SystemMessage1
syscall
li $v0, 5
syscall
move $t1, $v0
sw $t1,0($t0)
addi $t8,1
addi $t0,$t0,4
bne $t8,10, Loop
#topla
li $t0,0x10010050
li $t8,0
add $s0,$zero,$zero
Loop2:
lw $t2,0($t0)
add $s0,$s0,$t2
addi $t8,1
addi $t0,$t0,4
bne $t8,10, Loop2
#Sonucu yazdır
li $v0, 4
la $a0, SystemMessageF
syscall
li $v0, 1
move $a0, $s0
syscall
bitir:
#--------------------------------------------------------------
#terminate the main program
li $v0,10 # For exit, load 10 decimal into v0
syscall # Execute the last operation
|
Aiakos13/ece385_final_project
| 3,594
|
final/_1final/software/final_jodi_bsp/HAL/src/alt_exception_trap.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the trap exception handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_trap
alt_exception_trap:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
.Ltrap_handler:
/*
* Did a trap instruction cause the exception?
*
* The instruction which the exception occurred on has been loaded
* into r2 by code in alt_exception_entry.S
*
*/
movhi r3,0x003b /* upper half of trap opcode */
ori r3,r3,0x683a /* lower half of trap opcode */
bne r2,r3,.Lnot_trap
/*
* There is no trap handler defined here, and so executing a trap
* instruction causes a software break. If you provide a trap handler,
* then you must replace the break instruction below with your handler.
* Your handler must preserve ea and the usual callee saved registers.
*/
break
br .Lexception_exit
.Lnot_trap:
.section .exceptions.exit.label
.Lexception_exit:
|
Aiakos13/ece385_final_project
| 4,685
|
final/_1final/software/final_jodi_bsp/HAL/src/alt_irq_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the interrupt exception entry point code, which saves all the
* registers and calls the interrupt handler. It should be pulled in using
* a .globl from alt_irq_register.c. This scheme is used so that if an
* interrupt is never registered, then this code will not appear in the
* generated executable, thereby improving code footprint.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the compiler.
*/
.set noat
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.globl alt_irq_entry
.section .exceptions.entry.label, "xa"
alt_irq_entry:
/*
* Section .exceptions.entry is in alt_exception_entry.S
* This saves all the caller saved registers and reads estatus into r5
*/
.section .exceptions.irqtest, "xa"
#ifdef ALT_CI_INTERRUPT_VECTOR_N
/*
* Use the interrupt vector custom instruction if present to accelerate
* this code.
* If the interrupt vector custom instruction returns a negative
* value, there are no interrupts active (estatus.pie is 0
* or ipending is 0) so assume it is a software exception.
*/
custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0
blt r4, r0, .Lnot_irq
#else
/*
* Test to see if the exception was a software exception or caused
* by an external interrupt, and vector accordingly.
*/
rdctl r4, ipending
andi r2, r5, 1
beq r2, zero, .Lnot_irq
beq r4, zero, .Lnot_irq
#endif /* ALT_CI_INTERRUPT_VECTOR_N */
.section .exceptions.irqhandler, "xa"
/*
* Now that all necessary registers have been preserved, call
* alt_irq_handler() to process the interrupts.
*/
call alt_irq_handler
.section .exceptions.irqreturn, "xa"
br .Lexception_exit
.section .exceptions.notirq.label, "xa"
.Lnot_irq:
/*
* Section .exceptions.exit is in alt_exception_entry.S
* This restores all the caller saved registers
*/
.section .exceptions.exit.label
.Lexception_exit:
|
Aiakos13/ece385_final_project
| 1,919
|
final/_1final/software/final_jodi_bsp/HAL/src/alt_log_macro.S
|
/* alt_log_macro.S
*
* Implements the function tx_log_str, called by the assembly macro
* ALT_LOG_PUTS(). The macro will be empty when logging is turned off,
* and this function will not be compiled. When logging is on,
* this function is used to print out the strings defined in the beginning
* of alt_log_printf.c, using port information taken from system.h and
* alt_log_printf.h.
*
* This routine only handles strings, and sends a character into the defined
* output device's output buffer when the device is ready. It's intended for
* debugging purposes, where messages can be set to print out at certain
* points in the boot code to indicate the progress of the program.
*
*/
#ifndef __ALT_LOG_MACROS__
#define __ALT_LOG_MACROS__
/* define this flag to skip assembly-incompatible parts
* of various include files. */
#define ALT_ASM_SRC
#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined.
#include "system.h"
#include "sys/alt_log_printf.h"
.global tx_log_str
tx_log_str:
/* load base uart / jtag uart address into r6 */
movhi r6, %hiadj(ALT_LOG_PORT_BASE)
addi r6, r6, %lo(ALT_LOG_PORT_BASE)
tx_next_char:
/* if pointer points to null, return
* r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */
ldb r7, (r4)
beq r0, r7, end_tx
/* check device transmit ready */
wait_tx_ready_loop:
ldwio r8, ALT_LOG_PRINT_REG_OFFSET(r6)
/*UART, ALT_LOG_PRINT_MSK == 0x40
JTAG UART, ALT_LOG_PRINT_MSK == 0xFFFF0000 */
andhi r5, r8, %hi(ALT_LOG_PRINT_MSK)
andi r8, r8, %lo(ALT_LOG_PRINT_MSK)
or r5, r5, r8
beq r5, r0, wait_tx_ready_loop
/* write char */
stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6)
/* advance string pointer */
addi r4, r4, 1
br tx_next_char
end_tx:
ret
#endif
#endif /* __ALT_LOG_MACROS__ */
|
Aiakos13/ece385_final_project
| 15,129
|
final/_1final/software/final_jodi_bsp/HAL/src/alt_exception_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the exception entry point code, which saves all the caller saved
* registers and then handles the appropriate exception. It should be pulled
* in using a .globl from all the exception handler routines. This scheme is
* used so that if an interrupt is never registered, then this code will not
* appear in the generated executable, thereby improving code footprint.
*
* If an external interrpt controller (EIC) is present, it will supply an
* interrupt vector address to the processor when an interrupt occurs. For
* The Altera Vectored Interrupt Controller (VIC) driver will establish a
* vector table and the processor will jump directly to the appropriate
* table entry, funnel routine, and then user ISR. This will bypass this code
* in entirety. This code might still be linked into a system with an EIC,
* but would then be used only for non-interrupt exceptions.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* The top and bottom of the exception stack.
*/
#ifdef ALT_EXCEPTION_STACK
.globl __alt_exception_stack_pointer
#ifdef ALT_STACK_CHECK
.globl __alt_exception_stack_limit
/*
* Store the value of the stack limit after interrupt somewhere.
*/
.globl alt_exception_old_stack_limit
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* The code at alt_exception is located at the Nios II exception
* handler address.
*/
.section .exceptions.entry.label, "xa"
.globl alt_exception
.type alt_exception, @function
alt_exception:
/*
* The code for detecting a likely fatal ECC exception is
* linked here before the normal exception handler code if required.
* This is handled by the linker script and putting that code
* in the .exceptions.entry.ecc_fatal section.
*/
/*
* Now start the normal exception handler code.
*/
.section .exceptions.entry, "xa"
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
/*
* When runtime stack checking is enabled, the et register
* contains the stack limit. Save this in memory before
* overwriting the et register.
*/
stw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
/*
* Switch to the exception stack and save the current stack pointer
* in memory. Uses the et register as a scratch register.
*/
movhi et, %hi(__alt_exception_stack_pointer - 80)
ori et, et, %lo(__alt_exception_stack_pointer - 80)
stw sp, 76(et)
mov sp, et
#ifdef ALT_STACK_CHECK
/*
* Restore the stack limit from memory to the et register.
*/
movhi et, %hi(__alt_exception_stack_limit)
ori et, et, %lo(__alt_exception_stack_limit)
stw et, %gprel(alt_stack_limit_value)(gp)
#endif /* ALT_STACK_CHECK */
#else /* ALT_EXCEPTION_STACK disabled */
/*
* Reserve space on normal stack for registers about to be pushed.
*/
addi sp, sp, -76
#ifdef ALT_STACK_CHECK
/* Ensure stack didn't just overflow. */
bltu sp, et, .Lstack_overflow
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* Process an exception. For all exceptions we must preserve all
* caller saved registers on the stack (See the Nios II ABI
* documentation for details).
*
* Leave a gap in the stack frame at 4(sp) for the muldiv handler to
* store zero into.
*/
stw ra, 0(sp)
stw r1, 8(sp)
stw r2, 12(sp)
stw r3, 16(sp)
stw r4, 20(sp)
stw r5, 24(sp)
stw r6, 28(sp)
stw r7, 32(sp)
rdctl r5, estatus /* Read early to avoid usage stall */
stw r8, 36(sp)
stw r9, 40(sp)
stw r10, 44(sp)
stw r11, 48(sp)
stw r12, 52(sp)
stw r13, 56(sp)
stw r14, 60(sp)
stw r15, 64(sp)
/*
* ea-4 contains the address of the instruction being executed
* when the exception occured. For interrupt exceptions, we will
* will be re-issue the isntruction. Store it in 72(sp)
*/
stw r5, 68(sp) /* estatus */
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
/*
* The interrupt testing code (.exceptions.irqtest) will be
* linked here. If the Internal Interrupt Controller (IIC) is
* present (an EIC is not present), the presense of an interrupt
* is determined by examining CPU control registers or an interrupt
* custom instruction, if present.
*
* If the IIC is used and an interrupt is active, the code linked
* here will call the HAL IRQ handler (alt_irq_handler()) which
* successively calls registered interrupt handler(s) until no
* interrupts remain pending. It then jumps to .exceptions.exit. If
* there is no interrupt then it continues to .exception.notirq, below.
*/
.section .exceptions.notirq, "xa"
/*
* Prepare to service unimplemtned instructions or traps,
* each of which is optionally inked into section .exceptions.soft,
* which will preceed .exceptions.unknown below.
*
* Unlike interrupts, we want to skip the exception-causing instructon
* upon completion, so we write ea (address of instruction *after*
* the one where the exception occured) into 72(sp). The actual
* instruction that caused the exception is written in r2, which these
* handlers will utilize.
*/
stw ea, 72(sp) /* Don't re-issue */
#ifdef NIOS2_CDX_PRESENT
mov.n r4, ea
subi.n r4, r4, 4
ldhu.n r2, 0(r4)
ldhu.n r3, 2(r4)
slli.n r3, r3, 16
or.n r2, r2, r3 /* Instruction that caused exception */
#else
ldw r2, -4(ea) /* Instruction that caused exception */
#endif
/*
* Other exception handling code, if enabled, will be linked here.
* This includes unimplemted (multiply/divide) instruction support
* (a BSP generaton option), and a trap handler (that would typically
* be augmented with user-specific code). These are not linked in by
* default.
*/
/*
* In the context of linker sections, "unknown" are all exceptions
* not handled by the built-in handlers above (interupt, and trap or
* unimplemented instruction decoding, if enabled).
*
* Advanced exception types can be serviced by registering a handler.
* To do so, enable the "Enable Instruction-related Exception API" HAL
* BSP setting. If this setting is disabled, this handler code will
* either break (if the debug core is present) or enter an infinite
* loop because we don't how how to handle the exception.
*/
.section .exceptions.unknown
#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
/*
* The C-based HAL routine alt_instruction_exception_entry() will
* attempt to service the exception by calling a user-registered
* exception handler using alt_instruction_exception_register().
* If no handler was registered it will either break (if the
* debugger is present) or go into an infinite loop since the
* handling behavior is undefined; in that case we will not return here.
*/
/* Load exception-causing address as first argument (r4) */
addi r4, ea, -4
/* Call the instruction-exception entry */
call alt_instruction_exception_entry
/*
* If alt_instruction_exception_entry() returned, the exception was
* serviced by a user-registered routine. Its return code (now in r2)
* indicates whether to re-issue or skip the exception-causing
* instruction
*
* Return code was 0: Skip. The instruction after the exception is
* already stored in 72(sp).
*/
bne r2, r0, .Lexception_exit
/*
* Otherwise, modify 72(sp) to re-issue the instruction that caused the
* exception.
*/
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */
/*
* We got here because an instruction-related exception occured, but the
* handler API was not compiled in. We do not presume to know how to
* handle it. If the debugger is present, break, otherwise hang.
*
* If you get here then one of the following could have happened:
*
* - An instruction-generated exception occured, and the processor
* does not have the extra exceptions feature enabled, or you
* have not registered a handler using
* alt_instruction_exception_register()
*
* Some examples of instruction-generated exceptions and why they
* might occur:
*
* - Your program could have been compiled for a full-featured
* Nios II core, but it is running on a smaller core, and
* instruction emulation has been disabled by defining
* ALT_NO_INSTRUCTION_EMULATION.
*
* You can work around the problem by re-enabling instruction
* emulation, or you can figure out why your program is being
* compiled for a system other than the one that it is running on.
*
* - Your program has executed a trap instruction, but has not
* implemented a handler for this instruction.
*
* - Your program has executed an illegal instruction (one which is
* not defined in the instruction set).
*
* - Your processor includes an MMU or MPU, and you have enabled it
* before registering an exception handler to service exceptions it
* generates.
*
* The problem could also be hardware related:
* - If your hardware is broken and is generating spurious interrupts
* (a peripheral which negates its interrupt output before its
* interrupt handler has been executed will cause spurious
* interrupts)
*/
alt_exception_unknown:
#ifdef NIOS2_HAS_DEBUG_STUB
/*
* Either tell the user now (if there is a debugger attached) or go into
* the debug monitor which will loop until a debugger is attached.
*/
break
#else /* NIOS2_HAS_DEBUG_STUB disabled */
/*
* If there is no debug stub, an infinite loop is more useful.
*/
br alt_exception_unknown
#endif /* NIOS2_HAS_DEBUG_STUB */
#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
.section .exceptions.exit.label
.Lexception_exit:
.section .exceptions.exit, "xa"
/*
* Restore the saved registers, so that all general purpose registers
* have been restored to their state at the time the interrupt occured.
*/
ldw r5, 68(sp)
ldw ea, 72(sp) /* This becomes the PC once eret is executed */
ldw ra, 0(sp)
wrctl estatus, r5
ldw r1, 8(sp)
ldw r2, 12(sp)
ldw r3, 16(sp)
ldw r4, 20(sp)
ldw r5, 24(sp)
ldw r6, 28(sp)
ldw r7, 32(sp)
#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
ldw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif
ldw r8, 36(sp)
ldw r9, 40(sp)
ldw r10, 44(sp)
ldw r11, 48(sp)
ldw r12, 52(sp)
ldw r13, 56(sp)
ldw r14, 60(sp)
ldw r15, 64(sp)
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
stw et, %gprel(alt_stack_limit_value)(gp)
stw zero, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
ldw sp, 76(sp)
#else /* ALT_EXCEPTION_STACK disabled */
addi sp, sp, 76
#endif /* ALT_EXCEPTION_STACK */
/*
* Return to the interrupted instruction.
*/
eret
#ifdef ALT_STACK_CHECK
.Lstack_overflow:
break 3
#endif /* ALT_STACK_CHECK */
|
Aiakos13/ece385_final_project
| 21,315
|
final/_1final/software/final_jodi_bsp/HAL/src/alt_exception_muldiv.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the software multiply/divide handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_muldiv
alt_exception_muldiv:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
/* INSTRUCTION EMULATION
* ---------------------
*
* Nios II processors generate exceptions for unimplemented instructions.
* The routines below emulate these instructions. Depending on the
* processor core, the only instructions that might need to be emulated
* are div, divu, mul, muli, mulxss, mulxsu, and mulxuu.
*
* The emulations match the instructions, except for the following
* limitations:
*
* 1) The emulation routines do not emulate the use of the exception
* temporary register (et) as a source operand because the exception
* handler already has modified it.
*
* 2) The routines do not emulate the use of the stack pointer (sp) or the
* exception return address register (ea) as a destination because
* modifying these registers crashes the exception handler or the
* interrupted routine.
*
* 3) To save code size, the routines do not emulate the use of the
* breakpoint registers (ba and bt) as operands.
*
* Detailed Design
* ---------------
*
* The emulation routines expect the contents of integer registers r0-r31
* to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The
* routines retrieve source operands from the stack and modify the
* destination register's value on the stack prior to the end of the
* exception handler. Then all registers except the destination register
* are restored to their previous values.
*
* The instruction that causes the exception is found at address -4(ea).
* The instruction's OP and OPX fields identify the operation to be
* performed.
*
* One instruction, muli, is an I-type instruction that is identified by
* an OP field of 0x24.
*
* muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24-
* 27 22 6 0 <-- LSB of field
*
* The remaining emulated instructions are R-type and have an OP field
* of 0x3a. Their OPX fields identify them.
*
* R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a-
* 27 22 17 11 6 0 <-- LSB of field
*
*
*/
/*
* Split the instruction into its fields. We need 4*A, 4*B, and 4*C as
* offsets to the stack pointer for access to the stored register values.
*/
/* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */
roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */
roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */
roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */
srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */
xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */
roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */
andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */
xori r3, r3, 0x40
andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */
andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */
andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */
/* Now either
* r5 = OP
* r3 = 4*(A^16)
* r4 = IMM16 (sign extended)
* r6 = 4*(B^16)
* r7 = 4*(C^16)
* or
* r5 = OP
*/
/*
* Save everything on the stack to make it easy for the emulation routines
* to retrieve the source register operands. The exception entry code has
* already saved some of this so we don't need to do it all again.
*/
addi sp, sp, -60
stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */
/* Register at and r2-r15 have already been saved. */
stw r16, 0(sp)
stw r17, 4(sp)
stw r18, 8(sp)
stw r19, 12(sp)
stw r20, 16(sp)
stw r21, 20(sp)
stw r22, 24(sp)
stw r23, 28(sp)
/* et @ 32 - Has already been changed.*/
/* bt @ 36 - Usually isn't an operand. */
stw gp, 40(sp)
stw sp, 44(sp)
stw fp, 48(sp)
/* ea @ 52 - Don't bother to save - it's already been changed */
/* ba @ 56 - Breakpoint register usually isn't an operand */
/* ra @ 60 - Has already been saved */
/*
* Prepare for either multiplication or division loop.
* They both loop 32 times.
*/
movi r14, 32
/*
* Get the operands.
*
* It is necessary to check for muli because it uses an I-type instruction
* format, while the other instructions are have an R-type format.
*/
add r3, r3, sp /* r3 = address of A-operand. */
ldw r3, 0(r3) /* r3 = A-operand. */
movi r15, 0x24 /* muli opcode (I-type instruction format) */
beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */
add r6, r6, sp /* r6 = address of B-operand. */
ldw r6, 0(r6) /* r6 = B-operand. */
/* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */
/* IMM16 not needed, align OPX portion */
/* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */
/* Now
* r5 = OP
* r3 = src1
* r6 = src2
* r4 = OPX (no longer can be muli)
* r7 = 4*(C^16)
* r14 = loop counter
*/
/* ILLEGAL-INSTRUCTION EXCEPTION
* -----------------------------
*
* This code is for Nios II cores that generate exceptions when attempting
* to execute illegal instructions. Nios II cores that support an
* illegal-instruction exception are identified by the presence of the
* macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h .
*
* Remember that illegal instructions are different than unimplemented
* instructions. Illegal instructions are instruction encodings that
* have not been defined by the Nios II ISA. Unimplemented instructions
* are legal instructions that must be emulated by some Nios II cores.
*
* If we get here, all instructions except multiplies and divides
* are illegal.
*
* This code assumes that OP is not muli (because muli was tested above).
* All other multiplies and divides are legal. Anything else is illegal.
*/
movi r8, 0x3a /* OP for R-type mul* and div* */
bne r5, r8, .Lnot_muldiv
/* r15 already is 0x24 */ /* OPX of divu */
beq r4, r15, .Ldivide
movi r15,0x27 /* OPX of mul */
beq r4, r15, .Lmultiply
movi r15,0x07 /* OPX of mulxuu */
beq r4, r15, .Lmultiply
movi r15,0x17 /* OPX of mulxsu */
beq r4, r15, .Lmultiply
movi r15,0x1f /* OPX of mulxss */
beq r4, r15, .Lmultiply
movi r15,0x25 /* OPX of div */
bne r4, r15, .Lnot_muldiv
/* DIVISION
*
* Divide an unsigned dividend by an unsigned divisor using
* a shift-and-subtract algorithm. The example below shows
* 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a
* single register to store both the dividend and the quotient,
* allowing both values to be shifted with a single instruction.
*
* remainder dividend:quotient
* --------- -----------------
* initialize 00000000 00101011:
* shift 00000000 0101011:_
* remainder >= divisor? no 00000000 0101011:0
* shift 00000000 101011:0_
* remainder >= divisor? no 00000000 101011:00
* shift 00000001 01011:00_
* remainder >= divisor? no 00000001 01011:000
* shift 00000010 1011:000_
* remainder >= divisor? no 00000010 1011:0000
* shift 00000101 011:0000_
* remainder >= divisor? no 00000101 011:00000
* shift 00001010 11:00000_
* remainder >= divisor? yes 00001010 11:000001
* remainder -= divisor - 00000111
* ----------
* 00000011 11:000001
* shift 00000111 1:000001_
* remainder >= divisor? yes 00000111 1:0000011
* remainder -= divisor - 00000111
* ----------
* 00000000 1:0000011
* shift 00000001 :0000011_
* remainder >= divisor? no 00000001 :00000110
*
* The quotient is 00000110.
*/
.Ldivide:
/*
* Prepare for division by assuming the result
* is unsigned, and storing its "sign" as 0.
*/
movi r17, 0
/* Which division opcode? */
xori r15, r4, 0x25 /* OPX of div */
bne r15, zero, .Lunsigned_division
/*
* OPX is div. Determine and store the sign of the quotient.
* Then take the absolute value of both operands.
*/
xor r17, r3, r6 /* MSB contains sign of quotient */
bge r3, zero, 0f
sub r3, zero, r3 /* -r3 */
0:
bge r6, zero, 0f
sub r6, zero, r6 /* -r6 */
0:
.Lunsigned_division:
/* Initialize the unsigned-division loop. */
movi r13, 0 /* remainder = 0 */
/* Now
* r3 = dividend : quotient
* r4 = 0x25 for div, 0x24 for divu
* r6 = divisor
* r13 = remainder
* r14 = loop counter (already initialized to 32)
* r17 = MSB contains sign of quotient
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Ldivide_loop:
/*
* Division:
*
* (remainder:dividend:quotient) <<= 1;
*/
slli r13, r13, 1
cmplt r15, r3, zero /* r15 = MSB of r3 */
or r13, r13, r15
slli r3, r3, 1
/*
* if (remainder >= divisor)
* {
* set LSB of quotient
* remainder -= divisor;
* }
*/
bltu r13, r6, .Ldiv_skip
ori r3, r3, 1
sub r13, r13, r6
.Ldiv_skip:
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Ldivide_loop
mov r9, r3
/* Now
* r9 = quotient
* r4 = 0x25 for div, 0x24 for divu
* r7 = 4*(C^16)
* r17 = MSB contains sign of quotient
*/
/*
* Conditionally negate signed quotient. If quotient is unsigned,
* the sign already is initialized to 0.
*/
bge r17, zero, .Lstore_result
sub r9, zero, r9 /* -r9 */
br .Lstore_result
/* MULTIPLICATION
*
* A "product" is the number that one gets by summing a "multiplicand"
* several times. The "multiplier" specifies the number of copies of the
* multiplicand that are summed.
*
* Actual multiplication algorithms don't use repeated addition, however.
* Shift-and-add algorithms get the same answer as repeated addition, and
* they are faster. To compute the lower half of a product (pppp below)
* one shifts the product left before adding in each of the partial products
* (a * mmmm) through (d * mmmm).
*
* To compute the upper half of a product (PPPP below), one adds in the
* partial products (d * mmmm) through (a * mmmm), each time following the
* add by a right shift of the product.
*
* mmmm
* * abcd
* ------
* #### = d * mmmm
* #### = c * mmmm
* #### = b * mmmm
* #### = a * mmmm
* --------
* PPPPpppp
*
* The example above shows 4 partial products. Computing actual Nios II
* products requires 32 partials.
*
* It is possible to compute the result of mulxsu from the result of mulxuu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rA.
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*
* It is possible to compute the result of mulxss from the result of mulxsu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rB.
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*
*/
.Lmul_immed:
/* Opcode is muli. Change it into mul for remainder of algorithm. */
mov r7, r6 /* Field B is dest register, not field C. */
mov r6, r4 /* Field IMM16 is src2, not field B. */
movi r4, 0x27 /* OPX of mul is 0x27 */
.Lmultiply:
/* Initialize the multiplication loop. */
movi r9, 0 /* mul_product = 0 */
movi r10, 0 /* mulxuu_product = 0 */
mov r11, r6 /* save original multiplier for mulxsu and mulxss */
mov r12, r6 /* mulxuu_multiplier (will be shifted) */
movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */
/* Now
* r3 = multiplicand
* r6 = mul_multiplier
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r12 = mulxuu_multiplier
* r14 = loop counter (already initialized)
* r15 = temp
* r16 = 1
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Lmultiply_loop:
/*
* mul_product <<= 1;
* lsb = multiplier & 1;
*/
slli r9, r9, 1
andi r15, r12, 1
/*
* if (lsb == 1)
* {
* mulxuu_product += multiplicand;
* }
*/
beq r15, zero, .Lmulx_skip
add r10, r10, r3
cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */
ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */
.Lmulx_skip:
/*
* if (MSB of mul_multiplier == 1)
* {
* mul_product += multiplicand;
* }
*/
bge r6, zero, .Lmul_skip
add r9, r9, r3
.Lmul_skip:
/*
* mulxuu_product >>= 1; logical shift
* mul_multiplier <<= 1; done with MSB
* mulx_multiplier >>= 1; done with LSB
*/
srli r10, r10, 1
or r10, r10, r15 /* OR in the saved carry bit. */
slli r6, r6, 1
srli r12, r12, 1
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Lmultiply_loop
/*
* Multiply emulation loop done.
*/
/* Now
* r3 = multiplicand
* r4 = OPX
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r15 = temp
*/
/*
* Select/compute the result based on OPX.
*/
/* OPX == mul? Then store. */
xori r15, r4, 0x27
beq r15, zero, .Lstore_result
/* It's one of the mulx.. opcodes. Move over the result. */
mov r9, r10
/* OPX == mulxuu? Then store. */
xori r15, r4, 0x07
beq r15, zero, .Lstore_result
/* Compute mulxsu
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*/
bge r3, zero, .Lmulxsu_skip
sub r9, r9, r11
.Lmulxsu_skip:
/* OPX == mulxsu? Then store. */
xori r15, r4, 0x17
beq r15, zero, .Lstore_result
/* Compute mulxss
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*/
bge r11, zero, .Lmulxss_skip
sub r9, r9, r3
.Lmulxss_skip:
/* At this point, assume that OPX is mulxss, so store */
.Lstore_result:
add r7, r7, sp
stw r9, 0(r7)
ldw r16, 0(sp)
ldw r17, 4(sp)
ldw r18, 8(sp)
ldw r19, 12(sp)
ldw r20, 16(sp)
ldw r21, 20(sp)
ldw r22, 24(sp)
ldw r23, 28(sp)
/* bt @ 32 - Breakpoint register usually isn't an operand. */
/* et @ 36 - Don't corrupt et. */
/* gp @ 40 - Don't corrupt gp. */
/* sp @ 44 - Don't corrupt sp. */
ldw fp, 48(sp)
/* ea @ 52 - Don't corrupt ea. */
/* ba @ 56 - Breakpoint register usually isn't an operand. */
addi sp, sp, 60
br .Lexception_exit
.Lnot_muldiv:
addi sp, sp, 60
.section .exceptions.exit.label
.Lexception_exit:
|
Aiakos13/ece385_final_project
| 2,989
|
final/_1final/software/final_jodi_bsp/HAL/src/alt_software_exception.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This file provides the global symbol: software_exception. It is provided to
* support legacy code, and should not be used by new software.
*
* It is used by legacy code to invoke the software exception handler as
* defined by version 1.0 of the Nios II kit. It should only be used when you
* are providing your own interrupt entry point, i.e. you are not using
* alt_irq_entry.
*/
#include "system.h"
/*
* Pull in the exception handler.
*/
.globl alt_exception
.section .exceptions.entry.label, "xa"
.globl software_exception
.type software_exception, @function
software_exception:
|
Aiakos13/ece385_final_project
| 16,585
|
final/_1final/software/final_jodi_bsp/HAL/src/crt0.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
#include "nios2.h"
/* Setup header files to work with assembler code. */
#define ALT_ASM_SRC
/* Debug logging facility */
#include "sys/alt_log_printf.h"
/*************************************************************************\
| MACROS |
\*************************************************************************/
/*
* The new build tools explicitly define macros when alt_load()
* must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that
* those macros are controlling if alt_load() needs to be called.
*/
#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED
/* Need to call alt_load() if any of these sections are being copied. */
#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS)
#define CALL_ALT_LOAD
#endif
#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* The legacy build tools use the following macros to detect when alt_load()
* needs to be called.
*/
#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \
((res##_BASE != rodata##_BASE) || \
(res##_BASE != rwdata##_BASE) || \
(res##_BASE != exc##_BASE))
#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \
__ALT_LOAD_SECTIONS(res, text, rodata, exc)
#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \
ALT_RODATA_DEVICE, \
ALT_RWDATA_DEVICE, \
ALT_EXCEPTIONS_DEVICE)
/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */
#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS
#define CALL_ALT_LOAD
#endif
#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* When the legacy build tools define a macro called ALT_NO_BOOTLOADER,
* it indicates that initialization code is allowed at the reset address.
* The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for
* the same purpose.
*/
#ifdef ALT_NO_BOOTLOADER
#define ALT_ALLOW_CODE_AT_RESET
#endif
/*************************************************************************\
| EXTERNAL REFERENCES |
\*************************************************************************/
/*
* The entry point for user code is either "main" in hosted mode, or
* "alt_main" in standalone mode. These are explicitly referenced here,
* to ensure they are built into the executable. This allows the user
* to build them into libraries, rather than supplying them in object
* files at link time.
*/
.globl main
.globl alt_main
/*
* Create a reference to the software multiply/divide and trap handers,
* so that if they are provided, they will appear in the executable.
*/
#ifndef ALT_NO_INSTRUCTION_EMULATION
.globl alt_exception_muldiv
#endif
#ifdef ALT_TRAP_HANDLER
.globl alt_exception_trap
#endif
/*
* Linker defined symbols used to initialize bss.
*/
.globl __bss_start
.globl __bss_end
/*************************************************************************\
| RESET SECTION (.entry) |
\*************************************************************************/
/*
* This is the reset entry point for Nios II.
*
* At reset, only the cache line which contain the reset vector is
* initialized by the hardware. The code within the first cache line
* initializes the remainder of the instruction cache.
*/
.section .entry, "xa"
.align 5
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* Some tools want to know where the reset vector is.
* Code isn't always provided at the reset vector but at least the
* __reset label always contains the reset vector address because
* it is defined at the start of the .entry section.
*/
.globl __reset
.type __reset, @function
__reset:
/*
* Initialize the instruction cache if present (i.e. size > 0) and
* reset code is allowed unless optimizing for RTL simulation.
* RTL simulations can ensure the instruction cache is already initialized
* so skipping this loop speeds up RTL simulation.
*
* When ECC is present, need to execute initi for each word address
* to ensure ECC parity bits in cache RAM get initialized.
*/
#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
/* Assume the instruction cache size is always a power of two. */
#if NIOS2_ICACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_ICACHE_SIZE)
#else
movui r2, NIOS2_ICACHE_SIZE
#endif
0:
initi r2
addi r2, r2, -NIOS2_ICACHE_LINE_SIZE
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 1, 1, 0b, 1b
.popsection
#endif /* Initialize Instruction Cache */
/*
* Jump to the _start entry point in the .text section if reset code
* is allowed or if optimizing for RTL simulation.
*/
#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
/* Jump to the _start entry point in the .text section. */
movhi r1, %hi(_start)
ori r1, r1, %lo(_start)
jmp r1
.size __reset, . - __reset
#endif /* Jump to _start */
/*
* When not using exit, provide an _exit symbol to prevent unresolved
* references to _exit from the linker script.
*/
#ifdef ALT_NO_EXIT
.globl _exit
_exit:
#endif
/*************************************************************************\
| TEXT SECTION (.text) |
\*************************************************************************/
/*
* Start of the .text section, and also the code entry point when
* the code is executed by a bootloader rather than directly from reset.
*/
.section .text
.align 2
.globl _start
.type _start, @function
_start:
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Ensure that the current register set is 0 upon
* entry to this code. Switch register set to 0 by
* writing zero to SSTATUS register and executing an ERET instruction
* to set STATUS.CRS to 0.
*/
/* Get the current register set number (STATUS.CRS). */
rdctl r2, status
andi r2, r2, NIOS2_STATUS_CRS_MSK
/* Skip switching register set if STATUS.CRS is 0. */
beq r2, zero, 0f
/* Set SSTATUS to 0 to get to set SSTATUS.PRS to 0. */
.set nobreak
movui sstatus, 0
.set break
/* Switch to register set 0 and jump to label. */
movhi ea, %hi(0f)
ori ea, ea, %lo(0f)
eret
0:
#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */
/*
* Initialize the data cache if present (i.e. size > 0).
* Skip initialization if optimizing for RTL simulation and ECC isn't present.
* RTL simulations can ensure the data cache tag RAM is already initialized
* (but not the data RAM for ECC) so skipping this speeds up RTL simulation.
*
* When ECC is present, need to execute initd for each word address
* to ensure ECC parity bits in data RAM get initialized.
* Otherwise, only need to execute initd for each line address.
*/
#if NIOS2_DCACHE_SIZE > 0 && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
/* Assume the data cache size is always a power of two. */
#if NIOS2_DCACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_DCACHE_SIZE)
#else
movui r2, NIOS2_DCACHE_SIZE
#endif
0:
initd 0(r2)
#ifdef NIOS2_ECC_PRESENT
addi r2, r2, -4
#else
addi r2, r2, -NIOS2_DCACHE_LINE_SIZE
#endif
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 2, 1, 0b, 1b
.popsection
#endif /* Initialize Data Cache */
/* Log that caches have been initialized. */
ALT_LOG_PUTS(alt_log_msg_cache)
/* Log that the stack pointer is about to be setup. */
ALT_LOG_PUTS(alt_log_msg_stackpointer)
/*
* Now that the caches are initialized, set up the stack pointer and global pointer.
* The values provided by the linker are assumed to be correctly aligned.
*/
movhi sp, %hi(__alt_stack_pointer)
ori sp, sp, %lo(__alt_stack_pointer)
movhi gp, %hi(_gp)
ori gp, gp, %lo(_gp)
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
movui r1, 0
movui r2, 0
movui r3, 0
movui r4, 0
movui r5, 0
movui r6, 0
movui r7, 0
movui r8, 0
movui r9, 0
movui r10, 0
movui r11, 0
movui r12, 0
movui r13, 0
movui r14, 0
movui r15, 0
movui r16, 0
movui r17, 0
movui r18, 0
movui r19, 0
movui r20, 0
movui r21, 0
movui r22, 0
movui r23, 0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it is already been initialized. */
movui r28, 0 /* fp */
movui r29, 0 /* ea */
.set nobreak
movui r30, 0 /* sstatus */
.set break
movui r31, 0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Setup registers in shadow register sets
* from 1 to NIOS2_NUM_OF_SHADOW_REG_SETS.
*/
movui r2, 0 /* Contains value written into STATUS */
movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS /* counter */
movhi r4, 1 /* Constant to increment STATUS.PRS */
.Linitialize_shadow_registers:
/* Increment STATUS.PRS */
add r2, r2, r4
wrctl status, r2
/* Clear r0 in the shadow register set (not done by hardware) */
wrprs r0, r0
/* Write the GP in previous register set */
wrprs gp, gp
/*
* Only write the SP in previous register set
* if using the separate exception stack. For normal case (single stack),
* funnel code would read the SP from previous register set with a RDPRS.
*/
#ifdef ALT_INTERRUPT_STACK
movhi et, %hiadj(__alt_interrupt_stack_pointer)
addi et, et, %lo(__alt_interrupt_stack_pointer)
wrprs sp, et
#endif /* ALT_INTERRUPT_STACK */
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
wrprs r1, r0
wrprs r2, r0
wrprs r3, r0
wrprs r4, r0
wrprs r5, r0
wrprs r6, r0
wrprs r7, r0
wrprs r8, r0
wrprs r9, r0
wrprs r10, r0
wrprs r11, r0
wrprs r12, r0
wrprs r13, r0
wrprs r14, r0
wrprs r15, r0
wrprs r16, r0
wrprs r17, r0
wrprs r18, r0
wrprs r19, r0
wrprs r20, r0
wrprs r21, r0
wrprs r22, r0
wrprs r23, r0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it was initialized above or will be by a rdprs if not above */
wrprs r28, r0 /* fp */
wrprs r29, r0 /* ea */
wrprs r30, r0 /* ba */
wrprs r31, r0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
/* Decrement shadow register set counter */
addi r3, r3, -1
/* Done if index is 0. */
bne r3, zero, .Linitialize_shadow_registers
#endif /* (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) */
/*
* Clear the BSS if not optimizing for RTL simulation.
*
* This uses the symbols: __bss_start and __bss_end, which are defined
* by the linker script. They mark the begining and the end of the bss
* region. The linker script guarantees that these values are word aligned.
*/
#ifndef ALT_SIM_OPTIMIZE
/* Log that the BSS is about to be cleared. */
ALT_LOG_PUTS(alt_log_msg_bss)
movhi r2, %hi(__bss_start)
ori r2, r2, %lo(__bss_start)
movhi r3, %hi(__bss_end)
ori r3, r3, %lo(__bss_end)
beq r2, r3, 1f
0:
stw zero, (r2)
addi r2, r2, 4
bltu r2, r3, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 3, 1, 0b, 1b
.popsection
#endif /* ALT_SIM_OPTIMIZE */
/*
* Turn off the use of r1 (the assembler temporary register)
* so that call instructions can be safely relaxed across a
* 256MB boundary if needed
*/
.set at
/*
* The alt_load() facility is normally used when there is no bootloader.
* It copies some sections into RAM so it acts like a mini-bootloader.
*/
#ifdef CALL_ALT_LOAD
#ifdef ALT_STACK_CHECK
/*
* If the user has selected stack checking then we need to set up a safe
* value in the stack limit register so that the relocation functions
* don't think the stack has overflowed (the contents of the rwdata
* section aren't defined until alt_load() has been called).
*/
mov et, zero
#endif
call alt_load
#endif /* CALL_ALT_LOAD */
#ifdef ALT_STACK_CHECK
/*
* Set up the stack limit (if required). The linker has set up the
* copy of the variable which is in memory.
*/
ldw et, %gprel(alt_stack_limit_value)(gp)
#endif
/* Log that alt_main is about to be called. */
ALT_LOG_PUTS(alt_log_msg_alt_main)
/* Call the C entry point. It should never return. */
call alt_main
/* Wait in infinite loop in case alt_main does return. */
alt_after_alt_main:
br alt_after_alt_main
.size _start, . - _start
/*
* Add information about the stack base if stack overflow checking is enabled.
*/
#ifdef ALT_STACK_CHECK
.globl alt_stack_limit_value
.section .sdata,"aws",@progbits
.align 2
.type alt_stack_limit_value, @object
.size alt_stack_limit_value, 4
alt_stack_limit_value:
.long __alt_stack_limit
#endif
|
Aiakos13/ece385_final_project
| 8,293
|
final/_1final/software/final_jodi_bsp/HAL/src/alt_mcount.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/* mcount or _mcount is inserted by GCC before the function prologue of every
* function when a program is compiled for profiling. At the start of mcount,
* we guarantee that:
* ra = self_pc (an address in the function which called mcount)
* r8 = from_pc (an address in the function which called mcount's caller)
*
* Because this is always called at the start of a function we can corrupt
* r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain
* function arguments for the instrumented function) or r8 (which holds ra
* for the instrumented function).
*/
.global __mcount_fn_head
.global mcount
/* _mcount is used by gcc4 */
.global _mcount
_mcount:
mcount:
/* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose
* the bucket because bits 1:0 will always be 0, and because the distribution
* of values for bits 4:2 won't be even (aligning on cache line boundaries
* will skew it). Higher bits should be fairly random.
*/
/* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */
srli r2, ra, 3
movhi r3, %hiadj(__mcount_fn_head)
addi r3, r3, %lo(__mcount_fn_head)
andi r2, r2, 0xFC
add r11, r2, r3
/* The fast case is where we have already allocated a function arc, and so
* also a function pointer.
*/
/* First find the function being called (using self_pc) */
mov r10, r11
0:
ldw r10, 0(r10)
beq r10, zero, .Lnew_arc
ldw r2, 4(r10)
bne r2, ra, 0b
/* Found a function entry for this PC. Now look for an arc with a matching
* from_pc value. There will always be at least one arc. */
ldw r3, 8(r10)
0:
ldw r2, 4(r3)
beq r2, r8, .Lfound_arc
ldw r3, 0(r3)
bne r3, zero, 0b
.Lnew_arc:
addi sp, sp, -24
.LCFI0:
stw ra, 0(sp)
stw r4, 4(sp)
stw r5, 8(sp)
stw r6, 12(sp)
stw r7, 16(sp)
stw r8, 20(sp)
.LCFI1:
/* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */
mov r4, ra
mov r5, r8
mov r6, r10
mov r7, r11
call __mcount_record
/* restore registers from the stack */
ldw ra, 0(sp)
ldw r4, 4(sp)
ldw r5, 8(sp)
ldw r6, 12(sp)
ldw r7, 16(sp)
ldw r8, 20(sp)
addi sp, sp, 24
.LCFI2:
ret
.Lfound_arc:
/* We've found the correct arc record. Increment the count and return */
ldw r2, 8(r3)
addi r2, r2, 1
stw r2, 8(r3)
ret
.Lmcount_end:
/*
* Dwarf2 debug information for the function. This provides GDB with the
* information it needs to backtrace out of this function.
*/
.section .debug_frame,"",@progbits
.LCIE:
.4byte 2f - 1f /* Length */
1:
.4byte 0xffffffff /* CIE id */
.byte 0x1 /* Version */
.string "" /* Augmentation */
.uleb128 0x1 /* Code alignment factor */
.sleb128 -4 /* Data alignment factor */
.byte 0x1f /* Return address register */
.byte 0xc /* Define CFA */
.uleb128 0x1b /* Register 27 (sp) */
.uleb128 0x0 /* Offset 0 */
.align 2 /* Padding */
2:
.LFDE_mcount:
.4byte 2f - 1f /* Length */
1:
.4byte .LCIE /* Pointer to CIE */
.4byte mcount /* Start of table entry */
.4byte .Lmcount_end - mcount /* Size of table entry */
.byte 0x4 /* Advance location */
.4byte .LCFI0 - mcount /* to .LCFI0 */
.byte 0xe /* Define CFA offset */
.uleb128 24 /* to 24 */
.byte 0x4 /* Advance location */
.4byte .LCFI1 - .LCFI0 /* to .LCFI1 */
.byte 0x9f /* Store ra */
.uleb128 0x6 /* at CFA-24 */
.byte 0x84 /* Store r4 */
.uleb128 0x5 /* at CFA-20 */
.byte 0x85 /* Store r5 */
.uleb128 0x4 /* at CFA-16 */
.byte 0x86 /* Store r6 */
.uleb128 0x3 /* at CFA-12 */
.byte 0x87 /* Store r7 */
.uleb128 0x2 /* at CFA-8 */
.byte 0x88 /* Store r8 */
.uleb128 0x1 /* at CFA-4 */
.byte 0x4 /* Advance location */
.4byte .LCFI2 - .LCFI1 /* to .LCFI2 */
.byte 0xe /* Define CFA offset */
.uleb128 0 /* to 0 */
.byte 0x8 /* Same value */
.uleb128 31 /* for ra */
.byte 0x8 /* Same value */
.uleb128 4 /* for r4 */
.byte 0x8 /* Same value */
.uleb128 5 /* for r5 */
.byte 0x8 /* Same value */
.uleb128 6 /* for r6 */
.byte 0x8 /* Same value */
.uleb128 7 /* for r7 */
.byte 0x8 /* Same value */
.uleb128 8 /* for r8 */
.align 2
2:
|
Aiakos13/ece385_final_project
| 5,245
|
final/_1final/software/final_jodi_bsp/HAL/src/alt_ecc_fatal_entry.S
|
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the code called at the beginning of the exception handler
* to detect a likely fatal ECC error exception and then jump to
* user-provided code to handle it.
*
* This code is pulled in from a .globl in alt_ecc_fatal_exception.c.
* This scheme is used so that if a handler is never registered, then this
* code will not appear in the generated executable, thereby improving
* code footprint.
*
* This code is located in its own section that the linker script
* explicitly mentions and ensures it gets linked at the beginning
* of the exception handler.
*/
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.section .exceptions.entry.ecc_fatal, "xa"
/*
* This might be handling an unrecoverable ECC error exception
* in the register file and/or data cache.
* Must avoid reading registers or performing load/store instructions
* before this is determined because they could trigger another
* unrecoverable ECC error exception and create an infinite loop.
*
* The EXCEPTION register is always present when ECC is present.
* Bit 31 of this register indicates that there was an unrecoverable
* ECC error exception in the register file and/or data cache.
* Test this (using blt to check sign bit) to determine if this is
* what we are dealing with. Otherwise, just do normal processing.
*
* Jump to an application-provided routine to handle this condition.
* Pass in the return address in the et register in case this code
* can clean up the ECC error and then return here (unlikely).
*
* Runtime stack checking can't be enabled when ECC is present
* because they both want to use the et register.
*/
rdctl et, exception
bge et, r0, alt_exception_not_ecc_fatal /* Not ECCFTL if bit 31 is 0 */
/*
* Load ECC fatal handler pointer into et register.
* Using a ldwio is safe because it completely bypasses the data cache.
*/
movhi et, %hi(alt_exception_ecc_fatal_handler)
ori et, et, %lo(alt_exception_ecc_fatal_handler)
ldwio et, 0(et)
/*
* If ECC fatal handler pointer is not 0, assume a handler
* has been provided by the application.
*/
beq et, r0, alt_exception_not_ecc_fatal
/*
* The et register contains the address of the ECC fatal handler.
* Jump to this address to invoke the handler.
*/
jmp et
/*
* An ECC fatal handler can jump to this label if it able
* to recover from the fatal error (rare) and wants to continue
* with normal exception processing.
*/
.globl alt_exception_not_ecc_fatal
alt_exception_not_ecc_fatal:
|
Aiano/LocateMagnet
| 12,040
|
Firmware/MMC5603test/MDK-ARM/startup_stm32f103xb.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Aiano/LocateMagnet
| 12,040
|
Firmware/MMC5603test_GD32_Compatible/MDK-ARM/startup_stm32f103xb.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Aiano/FOC
| 9,896
|
Software/FOC_Driver_backup/startup/startup_stm32f103xb.s
|
/**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f103xb.s
* @author MCD Application Team
* @brief STM32F103xB Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F10x Medium Density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
Aidam7/PHavirP
| 2,783
|
Zend/asm/make_arm_aapcs_macho_gas.S
|
/*
Copyright Oliver Kowalke 2009.
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
/*******************************************************
* *
* ------------------------------------------------- *
* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | *
* ------------------------------------------------- *
* | 0x0 | 0x4 | 0x8 | 0xc | 0x10| 0x14| 0x18| 0x1c| *
* ------------------------------------------------- *
* | s16 | s17 | s18 | s19 | s20 | s21 | s22 | s23 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | *
* ------------------------------------------------- *
* | 0x20| 0x24| 0x28| 0x2c| 0x30| 0x34| 0x38| 0x3c| *
* ------------------------------------------------- *
* | s24 | s25 | s26 | s27 | s28 | s29 | s30 | s31 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | *
* ------------------------------------------------- *
* | 0x0 | 0x4 | 0x8 | 0xc | 0x10| 0x14| 0x18| 0x1c| *
* ------------------------------------------------- *
* | sjlj|hiddn| v1 | v2 | v3 | v4 | v5 | v6 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | *
* ------------------------------------------------- *
* | 0x20| 0x24| 0x28| 0x2c| 0x30| 0x34| 0x38| 0x3c| *
* ------------------------------------------------- *
* | v7 | v8 | lr | pc | FCTX| DATA| | *
* ------------------------------------------------- *
* *
*******************************************************/
.text
.globl _make_fcontext
.align 2
_make_fcontext:
@ shift address in A1 to lower 16 byte boundary
bic a1, a1, #15
@ reserve space for context-data on context-stack
sub a1, a1, #124
@ third arg of make_fcontext() == address of context-function
str a3, [a1, #108]
@ compute address of returned transfer_t
add a2, a1, #112
mov a3, a2
str a3, [a1, #68]
@ compute abs address of label finish
adr a2, finish
@ save address of finish as return-address for context-function
@ will be entered after context-function returns
str a2, [a1, #104]
bx lr @ return pointer to context-data
finish:
@ exit code is zero
mov a1, #0
@ exit application
bl __exit
|
Aidam7/PHavirP
| 6,724
|
Zend/asm/make_x86_64_sysv_elf_gas.S
|
/*
Copyright Oliver Kowalke 2009.
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
/****************************************************************************************
* *
* ---------------------------------------------------------------------------------- *
* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | *
* ---------------------------------------------------------------------------------- *
* | 0x0 | 0x4 | 0x8 | 0xc | 0x10 | 0x14 | 0x18 | 0x1c | *
* ---------------------------------------------------------------------------------- *
* | fc_mxcsr|fc_x87_cw| guard | R12 | R13 | *
* ---------------------------------------------------------------------------------- *
* ---------------------------------------------------------------------------------- *
* | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | *
* ---------------------------------------------------------------------------------- *
* | 0x20 | 0x24 | 0x28 | 0x2c | 0x30 | 0x34 | 0x38 | 0x3c | *
* ---------------------------------------------------------------------------------- *
* | R14 | R15 | RBX | RBP | *
* ---------------------------------------------------------------------------------- *
* ---------------------------------------------------------------------------------- *
* | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | *
* ---------------------------------------------------------------------------------- *
* | 0x40 | 0x44 | | *
* ---------------------------------------------------------------------------------- *
* | RIP | | *
* ---------------------------------------------------------------------------------- *
* *
****************************************************************************************/
# if defined __CET__
# include <cet.h>
# define SHSTK_ENABLED (__CET__ & 0x2)
# define BOOST_CONTEXT_SHADOW_STACK (SHSTK_ENABLED && SHADOW_STACK_SYSCALL)
# else
# define _CET_ENDBR
# endif
.file "make_x86_64_sysv_elf_gas.S"
.text
.globl make_fcontext
.type make_fcontext,@function
.align 16
make_fcontext:
_CET_ENDBR
#if BOOST_CONTEXT_SHADOW_STACK
/* the new shadow stack pointer (SSP) */
movq -0x8(%rdi), %r9
#endif
/* first arg of make_fcontext() == top of context-stack */
movq %rdi, %rax
/* shift address in RAX to lower 16 byte boundary */
andq $-16, %rax
/* reserve space for context-data on context-stack */
/* on context-function entry: (RSP -0x8) % 16 == 0 */
leaq -0x48(%rax), %rax
/* third arg of make_fcontext() == address of context-function */
/* stored in RBX */
movq %rdx, 0x30(%rax)
/* save MMX control- and status-word */
stmxcsr (%rax)
/* save x87 control-word */
fnstcw 0x4(%rax)
#if defined(BOOST_CONTEXT_TLS_STACK_PROTECTOR)
/* save stack guard */
movq %fs:0x28, %rcx /* read stack guard from TLS record */
movq %rcx, 0x8(%rsp) /* save stack guard */
#endif
/* compute abs address of label trampoline */
leaq trampoline(%rip), %rcx
/* save address of trampoline as return-address for context-function */
/* will be entered after calling jump_fcontext() first time */
movq %rcx, 0x40(%rax)
/* compute abs address of label finish */
leaq finish(%rip), %rcx
/* save address of finish as return-address for context-function */
/* will be entered after context-function returns */
movq %rcx, 0x38(%rax)
#if BOOST_CONTEXT_SHADOW_STACK
/* Populate the shadow stack and normal stack */
/* get original SSP */
rdsspq %r8
/* restore new shadow stack */
rstorssp -0x8(%r9)
/* save the restore token on the original shadow stack */
saveprevssp
/* push the address of "jmp trampoline" to the new shadow stack */
/* as well as the stack */
call 1f
jmp trampoline
1:
/* save address of "jmp trampoline" as return-address */
/* for context-function */
pop 0x38(%rax)
/* Get the new SSP. */
rdsspq %r9
/* restore original shadow stack */
rstorssp -0x8(%r8)
/* save the restore token on the new shadow stack. */
saveprevssp
/* reserve space for the new SSP */
leaq -0x8(%rax), %rax
/* save the new SSP to this fcontext */
movq %r9, (%rax)
#endif
#if BOOST_CONTEXT_SHADOW_STACK
/* Populate the shadow stack */
/* get original SSP */
rdsspq %r8
/* restore new shadow stack */
rstorssp -0x8(%r9)
/* save the restore token on the original shadow stack */
saveprevssp
/* push the address of "jmp trampoline" to the new shadow stack */
/* as well as the stack */
call 1f
jmp trampoline
1:
/* save address of "jmp trampoline" as return-address */
/* for context-function */
pop 0x38(%rax)
/* Get the new SSP. */
rdsspq %r9
/* restore original shadow stack */
rstorssp -0x8(%r8)
/* save the restore token on the new shadow stack. */
saveprevssp
/* now the new shadow stack looks like:
base-> +------------------------------+
| address of "jmp trampoline" |
SSP-> +------------------------------+
| restore token |
+------------------------------+
*/
/* reserve space for the new SSP */
leaq -0x8(%rax), %rax
/* save the new SSP to this fcontext */
movq %r9, (%rax)
#endif
ret /* return pointer to context-data */
trampoline:
/* store return address on stack */
/* fix stack alignment */
_CET_ENDBR
#if BOOST_CONTEXT_SHADOW_STACK
/* save address of "jmp *%rbp" as return-address */
/* on stack and shadow stack */
call 2f
jmp *%rbp
2:
#else
push %rbp
#endif
/* jump to context-function */
jmp *%rbx
finish:
_CET_ENDBR
/* exit code is zero */
xorq %rdi, %rdi
/* exit application */
call _exit@PLT
hlt
.size make_fcontext,.-make_fcontext
/* Mark that we don't need executable stack. */
.section .note.GNU-stack,"",%progbits
|
Aidam7/PHavirP
| 7,558
|
Zend/asm/jump_ppc32_sysv_macho_gas.S
|
/*
Copyright Oliver Kowalke 2009.
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
/******************************************************
* *
* ------------------------------------------------- *
* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | *
* ------------------------------------------------- *
* | 0 | 4 | 8 | 12 | 16 | 20 | 24 | 28 | *
* ------------------------------------------------- *
* | F14 | F15 | F16 | F17 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | *
* ------------------------------------------------- *
* | 32 | 36 | 40 | 44 | 48 | 52 | 56 | 60 | *
* ------------------------------------------------- *
* | F18 | F19 | F20 | F21 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | *
* ------------------------------------------------- *
* | 64 | 68 | 72 | 76 | 80 | 84 | 88 | 92 | *
* ------------------------------------------------- *
* | F22 | F23 | F24 | F25 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | *
* ------------------------------------------------- *
* | 96 | 100 | 104 | 108 | 112 | 116 | 120 | 124 | *
* ------------------------------------------------- *
* | F26 | F27 | F28 | F29 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | *
* ------------------------------------------------- *
* | 128 | 132 | 136 | 140 | 144 | 148 | 152 | 156 | *
* ------------------------------------------------- *
* | F30 | F31 | fpscr | R13 | R14 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | *
* ------------------------------------------------- *
* | 160 | 164 | 168 | 172 | 176 | 180 | 184 | 188 | *
* ------------------------------------------------- *
* | R15 | R16 | R17 | R18 | R19 | R20 | R21 | R22 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | *
* ------------------------------------------------- *
* | 192 | 196 | 200 | 204 | 208 | 212 | 216 | 220 | *
* ------------------------------------------------- *
* | R23 | R24 | R25 | R26 | R27 | R28 | R29 | R30 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | *
* ------------------------------------------------- *
* | 224 | 228 | 232 | 236 | 240 | 244 | 248 | 252 | *
* ------------------------------------------------- *
* | R31 |hiddn| CR | LR | PC |bchai|linkr| FCTX| *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 64 | | *
* ------------------------------------------------- *
* | 256 | | *
* ------------------------------------------------- *
* | DATA| | *
* ------------------------------------------------- *
* *
*******************************************************/
.text
.globl _jump_fcontext
.align 2
_jump_fcontext:
; reserve space on stack
subi r1, r1, 244
stfd f14, 0(r1) ; save F14
stfd f15, 8(r1) ; save F15
stfd f16, 16(r1) ; save F16
stfd f17, 24(r1) ; save F17
stfd f18, 32(r1) ; save F18
stfd f19, 40(r1) ; save F19
stfd f20, 48(r1) ; save F20
stfd f21, 56(r1) ; save F21
stfd f22, 64(r1) ; save F22
stfd f23, 72(r1) ; save F23
stfd f24, 80(r1) ; save F24
stfd f25, 88(r1) ; save F25
stfd f26, 96(r1) ; save F26
stfd f27, 104(r1) ; save F27
stfd f28, 112(r1) ; save F28
stfd f29, 120(r1) ; save F29
stfd f30, 128(r1) ; save F30
stfd f31, 136(r1) ; save F31
mffs f0 ; load FPSCR
stfd f0, 144(r1) ; save FPSCR
stw r13, 152(r1) ; save R13
stw r14, 156(r1) ; save R14
stw r15, 160(r1) ; save R15
stw r16, 164(r1) ; save R16
stw r17, 168(r1) ; save R17
stw r18, 172(r1) ; save R18
stw r19, 176(r1) ; save R19
stw r20, 180(r1) ; save R20
stw r21, 184(r1) ; save R21
stw r22, 188(r1) ; save R22
stw r23, 192(r1) ; save R23
stw r24, 196(r1) ; save R24
stw r25, 200(r1) ; save R25
stw r26, 204(r1) ; save R26
stw r27, 208(r1) ; save R27
stw r28, 212(r1) ; save R28
stw r29, 216(r1) ; save R29
stw r30, 220(r1) ; save R30
stw r31, 224(r1) ; save R31
stw r3, 228(r1) ; save hidden
; save CR
mfcr r0
stw r0, 232(r1)
; save LR
mflr r0
stw r0, 236(r1)
; save LR as PC
stw r0, 240(r1)
; store RSP (pointing to context-data) in R6
mr r6, r1
; restore RSP (pointing to context-data) from R4
mr r1, r4
lfd f14, 0(r1) ; restore F14
lfd f15, 8(r1) ; restore F15
lfd f16, 16(r1) ; restore F16
lfd f17, 24(r1) ; restore F17
lfd f18, 32(r1) ; restore F18
lfd f19, 40(r1) ; restore F19
lfd f20, 48(r1) ; restore F20
lfd f21, 56(r1) ; restore F21
lfd f22, 64(r1) ; restore F22
lfd f23, 72(r1) ; restore F23
lfd f24, 80(r1) ; restore F24
lfd f25, 88(r1) ; restore F25
lfd f26, 96(r1) ; restore F26
lfd f27, 104(r1) ; restore F27
lfd f28, 112(r1) ; restore F28
lfd f29, 120(r1) ; restore F29
lfd f30, 128(r1) ; restore F30
lfd f31, 136(r1) ; restore F31
lfd f0, 144(r1) ; load FPSCR
mtfsf 0xff, f0 ; restore FPSCR
lwz r13, 152(r1) ; restore R13
lwz r14, 156(r1) ; restore R14
lwz r15, 160(r1) ; restore R15
lwz r16, 164(r1) ; restore R16
lwz r17, 168(r1) ; restore R17
lwz r18, 172(r1) ; restore R18
lwz r19, 176(r1) ; restore R19
lwz r20, 180(r1) ; restore R20
lwz r21, 184(r1) ; restore R21
lwz r22, 188(r1) ; restore R22
lwz r23, 192(r1) ; restore R23
lwz r24, 196(r1) ; restore R24
lwz r25, 200(r1) ; restore R25
lwz r26, 204(r1) ; restore R26
lwz r27, 208(r1) ; restore R27
lwz r28, 212(r1) ; restore R28
lwz r29, 216(r1) ; restore R29
lwz r30, 220(r1) ; restore R30
lwz r31, 224(r1) ; restore R31
lwz r3, 228(r1) ; restore hidden
; restore CR
lwz r0, 232(r1)
mtcr r0
; restore LR
lwz r0, 236(r1)
mtlr r0
; load PC
lwz r0, 240(r1)
; restore CTR
mtctr r0
; adjust stack
addi r1, r1, 244
; return transfer_t
stw r6, 0(r3)
stw r5, 4(r3)
; jump to context
bctr
|
Aidam7/PHavirP
| 4,051
|
Zend/asm/make_riscv64_sysv_elf_gas.S
|
/*
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
/*******************************************************
* *
* ------------------------------------------------- *
* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | *
* ------------------------------------------------- *
* | 0x0 | 0x4 | 0x8 | 0xc | 0x10| 0x14| 0x18| 0x1c| *
* ------------------------------------------------- *
* | fs0 | fs1 | fs2 | fs3 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | *
* ------------------------------------------------- *
* | 0x20| 0x24| 0x28| 0x2c| 0x30| 0x34| 0x38| 0x3c| *
* ------------------------------------------------- *
* | fs4 | fs5 | fs6 | fs7 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | *
* ------------------------------------------------- *
* | 0x40| 0x44| 0x48| 0x4c| 0x50| 0x54| 0x58| 0x5c| *
* ------------------------------------------------- *
* | fs8 | fs9 | fs10 | fs11 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | *
* ------------------------------------------------- *
* | 0x60| 0x64| 0x68| 0x6c| 0x70| 0x74| 0x78| 0x7c| *
* ------------------------------------------------- *
* | s0 | s1 | s2 | s3 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | *
* ------------------------------------------------- *
* | 0x80| 0x84| 0x88| 0x8c| 0x90| 0x94| 0x98| 0x9c| *
* ------------------------------------------------- *
* | s4 | s5 | s6 | s7 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | *
* ------------------------------------------------- *
* | 0xa0| 0xa4| 0xa8| 0xac| 0xb0| 0xb4| 0xb8| 0xbc| *
* ------------------------------------------------- *
* | s8 | s9 | s10 | s11 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 48 | 49 | 50 | 51 | | | | | *
* ------------------------------------------------- *
* | 0xc0| 0xc4| 0xc8| 0xcc| | | | | *
* ------------------------------------------------- *
* | ra | pc | | | *
* ------------------------------------------------- *
* *
*******************************************************/
.file "make_riscv64_sysv_elf_gas.S"
.text
.align 1
.global make_fcontext
.type make_fcontext, %function
make_fcontext:
# shift address in a0 (allocated stack) to lower 16 byte boundary
andi a0, a0, ~0xF
# reserve space for context-data on context-stack
addi a0, a0, -0xd0
# third arg of make_fcontext() == address of context-function
# store address as a PC to jump in
sd a2, 0xc8(a0)
# save address of finish as return-address for context-function
# will be entered after context-function returns (RA register)
lla a4, finish
sd a4, 0xc0(a0)
ret // return pointer to context-data (a0)
finish:
# exit code is zero
li a0, 0
# exit application
tail _exit@plt
.size make_fcontext,.-make_fcontext
# Mark that we don't need executable stack.
.section .note.GNU-stack,"",%progbits
|
Aidam7/PHavirP
| 6,297
|
Zend/asm/jump_ppc32_sysv_elf_gas.S
|
/*
Copyright Oliver Kowalke 2009.
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
/*******************************************************
* *
* ------------------------------------------------- *
* | 0 | 4 | 8 | 12 | 16 | 20 | 24 | 28 | *
* ------------------------------------------------- *
* |bchai|hiddn| fpscr | PC | CR | R14 | R15 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 32 | 36 | 40 | 44 | 48 | 52 | 56 | 60 | *
* ------------------------------------------------- *
* | R16 | R17 | R18 | R19 | R20 | R21 | R22 | R23 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 64 | 68 | 72 | 76 | 80 | 84 | 88 | 92 | *
* ------------------------------------------------- *
* | R24 | R25 | R26 | R27 | R28 | R29 | R30 | R31 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 96 | 100 | 104 | 108 | 112 | 116 | 120 | 124 | *
* ------------------------------------------------- *
* | F14 | F15 | F16 | F17 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 128 | 132 | 136 | 140 | 144 | 148 | 152 | 156 | *
* ------------------------------------------------- *
* | F18 | F19 | F20 | F21 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 160 | 164 | 168 | 172 | 176 | 180 | 184 | 188 | *
* ------------------------------------------------- *
* | F22 | F23 | F24 | F25 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 192 | 196 | 200 | 204 | 208 | 212 | 216 | 220 | *
* ------------------------------------------------- *
* | F26 | F27 | F28 | F29 | *
* ------------------------------------------------- *
* ------------------------|------------ *
* | 224 | 228 | 232 | 236 | 240 | 244 | *
* ------------------------|------------ *
* | F30 | F31 |bchai| LR | *
* ------------------------|------------ *
* *
*******************************************************/
.file "jump_ppc32_sysv_elf_gas.S"
.text
.globl jump_fcontext
.align 2
.type jump_fcontext,@function
jump_fcontext:
# Linux: jump_fcontext( hidden transfer_t * R3, R4, R5)
# Other: transfer_t R3:R4 = jump_fcontext( R3, R4)
mflr %r0 # return address from LR
mffs %f0 # FPSCR
mfcr %r8 # condition register
stwu %r1, -240(%r1) # allocate stack space, R1 % 16 == 0
stw %r0, 244(%r1) # save LR in caller's frame
#ifdef __linux__
stw %r3, 4(%r1) # hidden pointer
#endif
stfd %f0, 8(%r1) # FPSCR
stw %r0, 16(%r1) # LR as PC
stw %r8, 20(%r1) # CR
# Save registers R14 to R31.
# Don't change R2, the thread-local storage pointer.
# Don't change R13, the small data pointer.
stw %r14, 24(%r1)
stw %r15, 28(%r1)
stw %r16, 32(%r1)
stw %r17, 36(%r1)
stw %r18, 40(%r1)
stw %r19, 44(%r1)
stw %r20, 48(%r1)
stw %r21, 52(%r1)
stw %r22, 56(%r1)
stw %r23, 60(%r1)
stw %r24, 64(%r1)
stw %r25, 68(%r1)
stw %r26, 72(%r1)
stw %r27, 76(%r1)
stw %r28, 80(%r1)
stw %r29, 84(%r1)
stw %r30, 88(%r1)
stw %r31, 92(%r1)
# Save registers F14 to F31 in slots with 8-byte alignment.
# 4-byte alignment may stall the pipeline of some processors.
# Less than 4 may cause alignment traps.
stfd %f14, 96(%r1)
stfd %f15, 104(%r1)
stfd %f16, 112(%r1)
stfd %f17, 120(%r1)
stfd %f18, 128(%r1)
stfd %f19, 136(%r1)
stfd %f20, 144(%r1)
stfd %f21, 152(%r1)
stfd %f22, 160(%r1)
stfd %f23, 168(%r1)
stfd %f24, 176(%r1)
stfd %f25, 184(%r1)
stfd %f26, 192(%r1)
stfd %f27, 200(%r1)
stfd %f28, 208(%r1)
stfd %f29, 216(%r1)
stfd %f30, 224(%r1)
stfd %f31, 232(%r1)
# store RSP (pointing to context-data) in R7/R6
# restore RSP (pointing to context-data) from R4/R3
#ifdef __linux__
mr %r7, %r1
mr %r1, %r4
lwz %r3, 4(%r1) # hidden pointer
#else
mr %r6, %r1
mr %r1, %r3
#endif
lfd %f0, 8(%r1) # FPSCR
lwz %r0, 16(%r1) # PC
lwz %r8, 20(%r1) # CR
mtfsf 0xff, %f0 # restore FPSCR
mtctr %r0 # load CTR with PC
mtcr %r8 # restore CR
# restore R14 to R31
lwz %r14, 24(%r1)
lwz %r15, 28(%r1)
lwz %r16, 32(%r1)
lwz %r17, 36(%r1)
lwz %r18, 40(%r1)
lwz %r19, 44(%r1)
lwz %r20, 48(%r1)
lwz %r21, 52(%r1)
lwz %r22, 56(%r1)
lwz %r23, 60(%r1)
lwz %r24, 64(%r1)
lwz %r25, 68(%r1)
lwz %r26, 72(%r1)
lwz %r27, 76(%r1)
lwz %r28, 80(%r1)
lwz %r29, 84(%r1)
lwz %r30, 88(%r1)
lwz %r31, 92(%r1)
# restore F14 to F31
lfd %f14, 96(%r1)
lfd %f15, 104(%r1)
lfd %f16, 112(%r1)
lfd %f17, 120(%r1)
lfd %f18, 128(%r1)
lfd %f19, 136(%r1)
lfd %f20, 144(%r1)
lfd %f21, 152(%r1)
lfd %f22, 160(%r1)
lfd %f23, 168(%r1)
lfd %f24, 176(%r1)
lfd %f25, 184(%r1)
lfd %f26, 192(%r1)
lfd %f27, 200(%r1)
lfd %f28, 208(%r1)
lfd %f29, 216(%r1)
lfd %f30, 224(%r1)
lfd %f31, 232(%r1)
# restore LR from caller's frame
lwz %r0, 244(%r1)
mtlr %r0
# adjust stack
addi %r1, %r1, 240
# return transfer_t
#ifdef __linux__
stw %r7, 0(%r3)
stw %r5, 4(%r3)
#else
mr %r3, %r6
# %r4, %r4
#endif
# jump to context
bctr
.size jump_fcontext, .-jump_fcontext
/* Mark that we don't need executable stack. */
.section .note.GNU-stack,"",%progbits
|
Aidam7/PHavirP
| 3,714
|
Zend/asm/make_mips64_n64_elf_gas.S
|
/*
Copyright Jiaxun Yang 2018.
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
/*******************************************************
* *
* ------------------------------------------------- *
* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | *
* ------------------------------------------------- *
* | 0 | 8 | 16 | 24 | *
* ------------------------------------------------- *
* | F24 | F25 | F26 | F27 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | *
* ------------------------------------------------- *
* | 32 | 40 | 48 | 56 | *
* ------------------------------------------------- *
* | F28 | F29 | F30 | F31 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | *
* ------------------------------------------------- *
* | 64 | 72 | 80 | 88 | *
* ------------------------------------------------- *
* | S0 | S1 | S2 | S3 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | *
* ------------------------------------------------- *
* | 96 | 100 | 104 | 108 | 112 | 116 | 120 | 124 | *
* ------------------------------------------------- *
* | S4 | S5 | S6 | S7 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | *
* ------------------------------------------------- *
* | 128 | 132 | 136 | 140 | 144 | 148 | 152 | 156 | *
* ------------------------------------------------- *
* | FP | GP | RA | PC | *
* ------------------------------------------------- *
* *
* *****************************************************/
.file "make_mips64_n64_elf_gas.S"
.text
.globl make_fcontext
.align 3
.type make_fcontext,@function
.ent make_fcontext
make_fcontext:
#ifdef __PIC__
.set noreorder
.cpload $t9
.set reorder
#endif
# shift address in A0 to lower 16 byte boundary
li $v1, 0xfffffffffffffff0
and $v0, $v1, $a0
# reserve space for context-data on context-stack
daddiu $v0, $v0, -160
# third arg of make_fcontext() == address of context-function
sd $a2, 152($v0)
# save global pointer in context-data
sd $gp, 136($v0)
# psudo instruction compute abs address of label finish based on GP
dla $t9, finish
# save address of finish as return-address for context-function
# will be entered after context-function returns
sd $t9, 144($v0)
jr $ra # return pointer to context-data
finish:
# reload our gp register (needed for la)
daddiu $t0, $sp, -160
ld $gp, 136($t0)
# call _exit(0)
# the previous function should have left the 16 bytes incoming argument
# area on the stack which we reuse for calling _exit
dla $t9, _exit
move $a0, $zero
jr $t9
.end make_fcontext
.size make_fcontext, .-make_fcontext
/* Mark that we don't need executable stack. */
.section .note.GNU-stack,"",%progbits
|
Aidam7/PHavirP
| 4,211
|
Zend/asm/jump_mips32_o32_elf_gas.S
|
/*
Copyright Oliver Kowalke 2009.
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
/*******************************************************
* *
* ------------------------------------------------- *
* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | *
* ------------------------------------------------- *
* | 0 | 4 | 8 | 12 | 16 | 20 | 24 | 28 | *
* ------------------------------------------------- *
* | F20 | F22 | F24 | F26 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | *
* ------------------------------------------------- *
* | 32 | 36 | 40 | 44 | 48 | 52 | 56 | 60 | *
* ------------------------------------------------- *
* | F28 | F30 | S0 | S1 | S2 | S3 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | *
* ------------------------------------------------- *
* | 64 | 68 | 72 | 76 | 80 | 84 | 88 | 92 | *
* ------------------------------------------------- *
* | S4 | S5 | S6 | S7 | FP |hiddn| RA | PC | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | *
* ------------------------------------------------- *
* | 96 | 100 | 104 | 108 | 112 | 116 | 120 | 124 | *
* ------------------------------------------------- *
* | ABI ARGS | GP | FCTX| DATA| | *
* ------------------------------------------------- *
* *
* *****************************************************/
.file "jump_mips32_o32_elf_gas.S"
.text
.globl jump_fcontext
.align 2
.type jump_fcontext,@function
.ent jump_fcontext
jump_fcontext:
# reserve space on stack
addiu $sp, $sp, -96
sw $s0, 48($sp) # save S0
sw $s1, 52($sp) # save S1
sw $s2, 56($sp) # save S2
sw $s3, 60($sp) # save S3
sw $s4, 64($sp) # save S4
sw $s5, 68($sp) # save S5
sw $s6, 72($sp) # save S6
sw $s7, 76($sp) # save S7
sw $fp, 80($sp) # save FP
sw $a0, 84($sp) # save hidden, address of returned transfer_t
sw $ra, 88($sp) # save RA
sw $ra, 92($sp) # save RA as PC
#if defined(__mips_hard_float)
s.d $f20, ($sp) # save F20
s.d $f22, 8($sp) # save F22
s.d $f24, 16($sp) # save F24
s.d $f26, 24($sp) # save F26
s.d $f28, 32($sp) # save F28
s.d $f30, 40($sp) # save F30
#endif
# store SP (pointing to context-data) in A0
move $a0, $sp
# restore SP (pointing to context-data) from A1
move $sp, $a1
#if defined(__mips_hard_float)
l.d $f20, ($sp) # restore F20
l.d $f22, 8($sp) # restore F22
l.d $f24, 16($sp) # restore F24
l.d $f26, 24($sp) # restore F26
l.d $f28, 32($sp) # restore F28
l.d $f30, 40($sp) # restore F30
#endif
lw $s0, 48($sp) # restore S0
lw $s1, 52($sp) # restore S1
lw $s2, 56($sp) # restore S2
lw $s3, 60($sp) # restore S3
lw $s4, 64($sp) # restore S4
lw $s5, 68($sp) # restore S5
lw $s6, 72($sp) # restore S6
lw $s7, 76($sp) # restore S7
lw $fp, 80($sp) # restore FP
lw $v0, 84($sp) # restore hidden, address of returned transfer_t
lw $ra, 88($sp) # restore RA
# load PC
lw $t9, 92($sp)
# adjust stack
addiu $sp, $sp, 96
# return transfer_t from jump
sw $a0, ($v0) # fctx of transfer_t
sw $a2, 4($v0) # data of transfer_t
# pass transfer_t as first arg in context function
# A0 == fctx, A1 == data
move $a1, $a2
# jump to context
jr $t9
.end jump_fcontext
.size jump_fcontext, .-jump_fcontext
/* Mark that we don't need executable stack. */
.section .note.GNU-stack,"",%progbits
|
Aidam7/PHavirP
| 3,040
|
Zend/asm/make_arm_aapcs_elf_gas.S
|
/*
Copyright Oliver Kowalke 2009.
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
/*******************************************************
* *
* ------------------------------------------------- *
* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | *
* ------------------------------------------------- *
* | 0x0 | 0x4 | 0x8 | 0xc | 0x10| 0x14| 0x18| 0x1c| *
* ------------------------------------------------- *
* | s16 | s17 | s18 | s19 | s20 | s21 | s22 | s23 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | *
* ------------------------------------------------- *
* | 0x20| 0x24| 0x28| 0x2c| 0x30| 0x34| 0x38| 0x3c| *
* ------------------------------------------------- *
* | s24 | s25 | s26 | s27 | s28 | s29 | s30 | s31 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | *
* ------------------------------------------------- *
* | 0x40| 0x44| 0x48| 0x4c| 0x50| 0x54| 0x58| 0x5c| *
* ------------------------------------------------- *
* |hiddn| v1 | v2 | v3 | v4 | v5 | v6 | v7 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | *
* ------------------------------------------------- *
* | 0x60| 0x64| 0x68| 0x6c| 0x70| 0x74| 0x78| 0x7c| *
* ------------------------------------------------- *
* | v8 | lr | pc | FCTX| DATA| | *
* ------------------------------------------------- *
* *
*******************************************************/
.file "make_arm_aapcs_elf_gas.S"
.text
.globl make_fcontext
.align 2
.type make_fcontext,%function
.syntax unified
make_fcontext:
@ shift address in A1 to lower 16 byte boundary
bic a1, a1, #15
@ reserve space for context-data on context-stack
sub a1, a1, #124
@ third arg of make_fcontext() == address of context-function
str a3, [a1, #104]
@ compute address of returned transfer_t
add a2, a1, #108
mov a3, a2
str a3, [a1, #64]
@ compute abs address of label finish
adr a2, finish
@ save address of finish as return-address for context-function
@ will be entered after context-function returns
str a2, [a1, #100]
#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
#endif
bx lr @ return pointer to context-data
finish:
@ exit code is zero
mov a1, #0
@ exit application
bl _exit@PLT
.size make_fcontext,.-make_fcontext
@ Mark that we don't need executable stack.
.section .note.GNU-stack,"",%progbits
|
Aidam7/PHavirP
| 3,532
|
Zend/asm/make_arm64_aapcs_macho_gas.S
|
/*
Copyright Edward Nevill + Oliver Kowalke 2015
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
/*******************************************************
* *
* ------------------------------------------------- *
* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | *
* ------------------------------------------------- *
* | 0x0 | 0x4 | 0x8 | 0xc | 0x10| 0x14| 0x18| 0x1c| *
* ------------------------------------------------- *
* | d8 | d9 | d10 | d11 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | *
* ------------------------------------------------- *
* | 0x20| 0x24| 0x28| 0x2c| 0x30| 0x34| 0x38| 0x3c| *
* ------------------------------------------------- *
* | d12 | d13 | d14 | d15 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | *
* ------------------------------------------------- *
* | 0x40| 0x44| 0x48| 0x4c| 0x50| 0x54| 0x58| 0x5c| *
* ------------------------------------------------- *
* | x19 | x20 | x21 | x22 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | *
* ------------------------------------------------- *
* | 0x60| 0x64| 0x68| 0x6c| 0x70| 0x74| 0x78| 0x7c| *
* ------------------------------------------------- *
* | x23 | x24 | x25 | x26 | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | *
* ------------------------------------------------- *
* | 0x80| 0x84| 0x88| 0x8c| 0x90| 0x94| 0x98| 0x9c| *
* ------------------------------------------------- *
* | x27 | x28 | FP | LR | *
* ------------------------------------------------- *
* ------------------------------------------------- *
* | 40 | 41 | 42 | 43 | | | *
* ------------------------------------------------- *
* | 0xa0| 0xa4| 0xa8| 0xac| | | *
* ------------------------------------------------- *
* | PC | align | | | *
* ------------------------------------------------- *
* *
*******************************************************/
.text
.globl _make_fcontext
.balign 16
_make_fcontext:
; shift address in x0 (allocated stack) to lower 16 byte boundary
and x0, x0, ~0xF
; reserve space for context-data on context-stack
sub x0, x0, #0xb0
; third arg of make_fcontext() == address of context-function
; store address as a PC to jump in
str x2, [x0, #0xa0]
adr x1, finish
; save address of finish as return-address for context-function
; will be entered after context-function returns (LR register)
str x1, [x0, #0x98]
ret lr ; return pointer to context-data (x0)
finish:
; exit code is zero
mov x0, #0
; exit application
bl __exit
|
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