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AirFortressIlikara/LS2K0300-linux-4.19
| 19,627
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arch/powerpc/mm/hash_low_32.S
|
/*
* PowerPC version
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
* Adapted for Power Macintosh by Paul Mackerras.
* Low-level exception handlers and MMU support
* rewritten by Paul Mackerras.
* Copyright (C) 1996 Paul Mackerras.
*
* This file contains low-level assembler routines for managing
* the PowerPC MMU hash table. (PPC 8xx processors don't use a
* hash table, so this file is not used on them.)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
*/
#include <asm/reg.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
#include <asm/export.h>
#include <asm/feature-fixups.h>
#ifdef CONFIG_SMP
.section .bss
.align 2
mmu_hash_lock:
.space 4
#endif /* CONFIG_SMP */
/*
* Load a PTE into the hash table, if possible.
* The address is in r4, and r3 contains an access flag:
* _PAGE_RW (0x400) if a write.
* r9 contains the SRR1 value, from which we use the MSR_PR bit.
* SPRG_THREAD contains the physical address of the current task's thread.
*
* Returns to the caller if the access is illegal or there is no
* mapping for the address. Otherwise it places an appropriate PTE
* in the hash table and returns from the exception.
* Uses r0, r3 - r8, r10, ctr, lr.
*/
.text
_GLOBAL(hash_page)
tophys(r7,0) /* gets -KERNELBASE into r7 */
#ifdef CONFIG_SMP
addis r8,r7,mmu_hash_lock@h
ori r8,r8,mmu_hash_lock@l
lis r0,0x0fff
b 10f
11: lwz r6,0(r8)
cmpwi 0,r6,0
bne 11b
10: lwarx r6,0,r8
cmpwi 0,r6,0
bne- 11b
stwcx. r0,0,r8
bne- 10b
isync
#endif
/* Get PTE (linux-style) and check access */
lis r0,KERNELBASE@h /* check if kernel address */
cmplw 0,r4,r0
mfspr r8,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
lwz r5,PGDIR(r8) /* virt page-table root */
blt+ 112f /* assume user more likely */
lis r5,swapper_pg_dir@ha /* if kernel address, use */
addi r5,r5,swapper_pg_dir@l /* kernel page table */
rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
112: add r5,r5,r7 /* convert to phys addr */
#ifndef CONFIG_PTE_64BIT
rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
lwz r8,0(r5) /* get pmd entry */
rlwinm. r8,r8,0,0,19 /* extract address of pte page */
#else
rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */
lwzx r8,r8,r5 /* Get L1 entry */
rlwinm. r8,r8,0,0,20 /* extract pt base address */
#endif
#ifdef CONFIG_SMP
beq- hash_page_out /* return if no mapping */
#else
/* XXX it seems like the 601 will give a machine fault on the
rfi if its alignment is wrong (bottom 4 bits of address are
8 or 0xc) and we have had a not-taken conditional branch
to the address following the rfi. */
beqlr-
#endif
#ifndef CONFIG_PTE_64BIT
rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
#else
rlwimi r8,r4,23,20,28 /* compute pte address */
#endif
rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
/*
* Update the linux PTE atomically. We do the lwarx up-front
* because almost always, there won't be a permission violation
* and there won't already be an HPTE, and thus we will have
* to update the PTE to set _PAGE_HASHPTE. -- paulus.
*
* If PTE_64BIT is set, the low word is the flags word; use that
* word for locking since it contains all the interesting bits.
*/
#if (PTE_FLAGS_OFFSET != 0)
addi r8,r8,PTE_FLAGS_OFFSET
#endif
retry:
lwarx r6,0,r8 /* get linux-style pte, flag word */
andc. r5,r3,r6 /* check access & ~permission */
#ifdef CONFIG_SMP
bne- hash_page_out /* return if access not permitted */
#else
bnelr-
#endif
or r5,r0,r6 /* set accessed/dirty bits */
#ifdef CONFIG_PTE_64BIT
#ifdef CONFIG_SMP
subf r10,r6,r8 /* create false data dependency */
subi r10,r10,PTE_FLAGS_OFFSET
lwzx r10,r6,r10 /* Get upper PTE word */
#else
lwz r10,-PTE_FLAGS_OFFSET(r8)
#endif /* CONFIG_SMP */
#endif /* CONFIG_PTE_64BIT */
stwcx. r5,0,r8 /* attempt to update PTE */
bne- retry /* retry if someone got there first */
mfsrin r3,r4 /* get segment reg for segment */
mfctr r0
stw r0,_CTR(r11)
bl create_hpte /* add the hash table entry */
#ifdef CONFIG_SMP
eieio
addis r8,r7,mmu_hash_lock@ha
li r0,0
stw r0,mmu_hash_lock@l(r8)
#endif
/* Return from the exception */
lwz r5,_CTR(r11)
mtctr r5
lwz r0,GPR0(r11)
lwz r7,GPR7(r11)
lwz r8,GPR8(r11)
b fast_exception_return
#ifdef CONFIG_SMP
hash_page_out:
eieio
addis r8,r7,mmu_hash_lock@ha
li r0,0
stw r0,mmu_hash_lock@l(r8)
blr
#endif /* CONFIG_SMP */
/*
* Add an entry for a particular page to the hash table.
*
* add_hash_page(unsigned context, unsigned long va, unsigned long pmdval)
*
* We assume any necessary modifications to the pte (e.g. setting
* the accessed bit) have already been done and that there is actually
* a hash table in use (i.e. we're not on a 603).
*/
_GLOBAL(add_hash_page)
mflr r0
stw r0,4(r1)
/* Convert context and va to VSID */
mulli r3,r3,897*16 /* multiply context by context skew */
rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
mulli r0,r0,0x111 /* multiply by ESID skew */
add r3,r3,r0 /* note create_hpte trims to 24 bits */
#ifdef CONFIG_SMP
CURRENT_THREAD_INFO(r8, r1) /* use cpu number to make tag */
lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */
oris r8,r8,12
#endif /* CONFIG_SMP */
/*
* We disable interrupts here, even on UP, because we don't
* want to race with hash_page, and because we want the
* _PAGE_HASHPTE bit to be a reliable indication of whether
* the HPTE exists (or at least whether one did once).
* We also turn off the MMU for data accesses so that we
* we can't take a hash table miss (assuming the code is
* covered by a BAT). -- paulus
*/
mfmsr r9
SYNC
rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */
rlwinm r0,r0,0,28,26 /* clear MSR_DR */
mtmsr r0
SYNC_601
isync
tophys(r7,0)
#ifdef CONFIG_SMP
addis r6,r7,mmu_hash_lock@ha
addi r6,r6,mmu_hash_lock@l
10: lwarx r0,0,r6 /* take the mmu_hash_lock */
cmpi 0,r0,0
bne- 11f
stwcx. r8,0,r6
beq+ 12f
11: lwz r0,0(r6)
cmpi 0,r0,0
beq 10b
b 11b
12: isync
#endif
/*
* Fetch the linux pte and test and set _PAGE_HASHPTE atomically.
* If _PAGE_HASHPTE was already set, we don't replace the existing
* HPTE, so we just unlock and return.
*/
mr r8,r5
#ifndef CONFIG_PTE_64BIT
rlwimi r8,r4,22,20,29
#else
rlwimi r8,r4,23,20,28
addi r8,r8,PTE_FLAGS_OFFSET
#endif
1: lwarx r6,0,r8
andi. r0,r6,_PAGE_HASHPTE
bne 9f /* if HASHPTE already set, done */
#ifdef CONFIG_PTE_64BIT
#ifdef CONFIG_SMP
subf r10,r6,r8 /* create false data dependency */
subi r10,r10,PTE_FLAGS_OFFSET
lwzx r10,r6,r10 /* Get upper PTE word */
#else
lwz r10,-PTE_FLAGS_OFFSET(r8)
#endif /* CONFIG_SMP */
#endif /* CONFIG_PTE_64BIT */
ori r5,r6,_PAGE_HASHPTE
stwcx. r5,0,r8
bne- 1b
bl create_hpte
9:
#ifdef CONFIG_SMP
addis r6,r7,mmu_hash_lock@ha
addi r6,r6,mmu_hash_lock@l
eieio
li r0,0
stw r0,0(r6) /* clear mmu_hash_lock */
#endif
/* reenable interrupts and DR */
mtmsr r9
SYNC_601
isync
lwz r0,4(r1)
mtlr r0
blr
/*
* This routine adds a hardware PTE to the hash table.
* It is designed to be called with the MMU either on or off.
* r3 contains the VSID, r4 contains the virtual address,
* r5 contains the linux PTE, r6 contains the old value of the
* linux PTE (before setting _PAGE_HASHPTE) and r7 contains the
* offset to be added to addresses (0 if the MMU is on,
* -KERNELBASE if it is off). r10 contains the upper half of
* the PTE if CONFIG_PTE_64BIT.
* On SMP, the caller should have the mmu_hash_lock held.
* We assume that the caller has (or will) set the _PAGE_HASHPTE
* bit in the linux PTE in memory. The value passed in r6 should
* be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set
* this routine will skip the search for an existing HPTE.
* This procedure modifies r0, r3 - r6, r8, cr0.
* -- paulus.
*
* For speed, 4 of the instructions get patched once the size and
* physical address of the hash table are known. These definitions
* of Hash_base and Hash_bits below are just an example.
*/
Hash_base = 0xc0180000
Hash_bits = 12 /* e.g. 256kB hash table */
Hash_msk = (((1 << Hash_bits) - 1) * 64)
/* defines for the PTE format for 32-bit PPCs */
#define HPTE_SIZE 8
#define PTEG_SIZE 64
#define LG_PTEG_SIZE 6
#define LDPTEu lwzu
#define LDPTE lwz
#define STPTE stw
#define CMPPTE cmpw
#define PTE_H 0x40
#define PTE_V 0x80000000
#define TST_V(r) rlwinm. r,r,0,0,0
#define SET_V(r) oris r,r,PTE_V@h
#define CLR_V(r,t) rlwinm r,r,0,1,31
#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1)
#define HASH_RIGHT 31-LG_PTEG_SIZE
_GLOBAL(create_hpte)
/* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */
rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
and r8,r8,r0 /* writable if _RW & _DIRTY */
rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */
rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
ori r8,r8,0xe04 /* clear out reserved bits */
andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */
BEGIN_FTR_SECTION
rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */
END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
#ifdef CONFIG_PTE_64BIT
/* Put the XPN bits into the PTE */
rlwimi r8,r10,8,20,22
rlwimi r8,r10,2,29,29
#endif
/* Construct the high word of the PPC-style PTE (r5) */
rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */
SET_V(r5) /* set V (valid) bit */
/* Get the address of the primary PTE group in the hash table (r3) */
_GLOBAL(hash_page_patch_A)
addis r0,r7,Hash_base@h /* base address of hash table */
rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
xor r3,r3,r0 /* make primary hash */
li r0,8 /* PTEs/group */
/*
* Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
* if it is clear, meaning that the HPTE isn't there already...
*/
andi. r6,r6,_PAGE_HASHPTE
beq+ 10f /* no PTE: go look for an empty slot */
tlbie r4
addis r4,r7,htab_hash_searches@ha
lwz r6,htab_hash_searches@l(r4)
addi r6,r6,1 /* count how many searches we do */
stw r6,htab_hash_searches@l(r4)
/* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
mtctr r0
addi r4,r3,-HPTE_SIZE
1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */
CMPPTE 0,r6,r5
bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
beq+ found_slot
/* Search the secondary PTEG for a matching PTE */
ori r5,r5,PTE_H /* set H (secondary hash) bit */
_GLOBAL(hash_page_patch_B)
xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
xori r4,r4,(-PTEG_SIZE & 0xffff)
addi r4,r4,-HPTE_SIZE
mtctr r0
2: LDPTEu r6,HPTE_SIZE(r4)
CMPPTE 0,r6,r5
bdnzf 2,2b
beq+ found_slot
xori r5,r5,PTE_H /* clear H bit again */
/* Search the primary PTEG for an empty slot */
10: mtctr r0
addi r4,r3,-HPTE_SIZE /* search primary PTEG */
1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */
TST_V(r6) /* test valid bit */
bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
beq+ found_empty
/* update counter of times that the primary PTEG is full */
addis r4,r7,primary_pteg_full@ha
lwz r6,primary_pteg_full@l(r4)
addi r6,r6,1
stw r6,primary_pteg_full@l(r4)
/* Search the secondary PTEG for an empty slot */
ori r5,r5,PTE_H /* set H (secondary hash) bit */
_GLOBAL(hash_page_patch_C)
xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
xori r4,r4,(-PTEG_SIZE & 0xffff)
addi r4,r4,-HPTE_SIZE
mtctr r0
2: LDPTEu r6,HPTE_SIZE(r4)
TST_V(r6)
bdnzf 2,2b
beq+ found_empty
xori r5,r5,PTE_H /* clear H bit again */
/*
* Choose an arbitrary slot in the primary PTEG to overwrite.
* Since both the primary and secondary PTEGs are full, and we
* have no information that the PTEs in the primary PTEG are
* more important or useful than those in the secondary PTEG,
* and we know there is a definite (although small) speed
* advantage to putting the PTE in the primary PTEG, we always
* put the PTE in the primary PTEG.
*
* In addition, we skip any slot that is mapping kernel text in
* order to avoid a deadlock when not using BAT mappings if
* trying to hash in the kernel hash code itself after it has
* already taken the hash table lock. This works in conjunction
* with pre-faulting of the kernel text.
*
* If the hash table bucket is full of kernel text entries, we'll
* lockup here but that shouldn't happen
*/
1: addis r4,r7,next_slot@ha /* get next evict slot */
lwz r6,next_slot@l(r4)
addi r6,r6,HPTE_SIZE /* search for candidate */
andi. r6,r6,7*HPTE_SIZE
stw r6,next_slot@l(r4)
add r4,r3,r6
LDPTE r0,HPTE_SIZE/2(r4) /* get PTE second word */
clrrwi r0,r0,12
lis r6,etext@h
ori r6,r6,etext@l /* get etext */
tophys(r6,r6)
cmpl cr0,r0,r6 /* compare and try again */
blt 1b
#ifndef CONFIG_SMP
/* Store PTE in PTEG */
found_empty:
STPTE r5,0(r4)
found_slot:
STPTE r8,HPTE_SIZE/2(r4)
#else /* CONFIG_SMP */
/*
* Between the tlbie above and updating the hash table entry below,
* another CPU could read the hash table entry and put it in its TLB.
* There are 3 cases:
* 1. using an empty slot
* 2. updating an earlier entry to change permissions (i.e. enable write)
* 3. taking over the PTE for an unrelated address
*
* In each case it doesn't really matter if the other CPUs have the old
* PTE in their TLB. So we don't need to bother with another tlbie here,
* which is convenient as we've overwritten the register that had the
* address. :-) The tlbie above is mainly to make sure that this CPU comes
* and gets the new PTE from the hash table.
*
* We do however have to make sure that the PTE is never in an invalid
* state with the V bit set.
*/
found_empty:
found_slot:
CLR_V(r5,r0) /* clear V (valid) bit in PTE */
STPTE r5,0(r4)
sync
TLBSYNC
STPTE r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
sync
SET_V(r5)
STPTE r5,0(r4) /* finally set V bit in PTE */
#endif /* CONFIG_SMP */
sync /* make sure pte updates get to memory */
blr
.section .bss
.align 2
next_slot:
.space 4
primary_pteg_full:
.space 4
htab_hash_searches:
.space 4
.previous
/*
* Flush the entry for a particular page from the hash table.
*
* flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval,
* int count)
*
* We assume that there is a hash table in use (Hash != 0).
*/
_GLOBAL(flush_hash_pages)
tophys(r7,0)
/*
* We disable interrupts here, even on UP, because we want
* the _PAGE_HASHPTE bit to be a reliable indication of
* whether the HPTE exists (or at least whether one did once).
* We also turn off the MMU for data accesses so that we
* we can't take a hash table miss (assuming the code is
* covered by a BAT). -- paulus
*/
mfmsr r10
SYNC
rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
rlwinm r0,r0,0,28,26 /* clear MSR_DR */
mtmsr r0
SYNC_601
isync
/* First find a PTE in the range that has _PAGE_HASHPTE set */
#ifndef CONFIG_PTE_64BIT
rlwimi r5,r4,22,20,29
#else
rlwimi r5,r4,23,20,28
#endif
1: lwz r0,PTE_FLAGS_OFFSET(r5)
cmpwi cr1,r6,1
andi. r0,r0,_PAGE_HASHPTE
bne 2f
ble cr1,19f
addi r4,r4,0x1000
addi r5,r5,PTE_SIZE
addi r6,r6,-1
b 1b
/* Convert context and va to VSID */
2: mulli r3,r3,897*16 /* multiply context by context skew */
rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
mulli r0,r0,0x111 /* multiply by ESID skew */
add r3,r3,r0 /* note code below trims to 24 bits */
/* Construct the high word of the PPC-style PTE (r11) */
rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */
SET_V(r11) /* set V (valid) bit */
#ifdef CONFIG_SMP
addis r9,r7,mmu_hash_lock@ha
addi r9,r9,mmu_hash_lock@l
CURRENT_THREAD_INFO(r8, r1)
add r8,r8,r7
lwz r8,TI_CPU(r8)
oris r8,r8,9
10: lwarx r0,0,r9
cmpi 0,r0,0
bne- 11f
stwcx. r8,0,r9
beq+ 12f
11: lwz r0,0(r9)
cmpi 0,r0,0
beq 10b
b 11b
12: isync
#endif
/*
* Check the _PAGE_HASHPTE bit in the linux PTE. If it is
* already clear, we're done (for this pte). If not,
* clear it (atomically) and proceed. -- paulus.
*/
#if (PTE_FLAGS_OFFSET != 0)
addi r5,r5,PTE_FLAGS_OFFSET
#endif
33: lwarx r8,0,r5 /* fetch the pte flags word */
andi. r0,r8,_PAGE_HASHPTE
beq 8f /* done if HASHPTE is already clear */
rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
stwcx. r8,0,r5 /* update the pte */
bne- 33b
/* Get the address of the primary PTE group in the hash table (r3) */
_GLOBAL(flush_hash_patch_A)
addis r8,r7,Hash_base@h /* base address of hash table */
rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
xor r8,r0,r8 /* make primary hash */
/* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
li r0,8 /* PTEs/group */
mtctr r0
addi r12,r8,-HPTE_SIZE
1: LDPTEu r0,HPTE_SIZE(r12) /* get next PTE */
CMPPTE 0,r0,r11
bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
beq+ 3f
/* Search the secondary PTEG for a matching PTE */
ori r11,r11,PTE_H /* set H (secondary hash) bit */
li r0,8 /* PTEs/group */
_GLOBAL(flush_hash_patch_B)
xoris r12,r8,Hash_msk>>16 /* compute secondary hash */
xori r12,r12,(-PTEG_SIZE & 0xffff)
addi r12,r12,-HPTE_SIZE
mtctr r0
2: LDPTEu r0,HPTE_SIZE(r12)
CMPPTE 0,r0,r11
bdnzf 2,2b
xori r11,r11,PTE_H /* clear H again */
bne- 4f /* should rarely fail to find it */
3: li r0,0
STPTE r0,0(r12) /* invalidate entry */
4: sync
tlbie r4 /* in hw tlb too */
sync
8: ble cr1,9f /* if all ptes checked */
81: addi r6,r6,-1
addi r5,r5,PTE_SIZE
addi r4,r4,0x1000
lwz r0,0(r5) /* check next pte */
cmpwi cr1,r6,1
andi. r0,r0,_PAGE_HASHPTE
bne 33b
bgt cr1,81b
9:
#ifdef CONFIG_SMP
TLBSYNC
li r0,0
stw r0,0(r9) /* clear mmu_hash_lock */
#endif
19: mtmsr r10
SYNC_601
isync
blr
EXPORT_SYMBOL(flush_hash_pages)
/*
* Flush an entry from the TLB
*/
_GLOBAL(_tlbie)
#ifdef CONFIG_SMP
CURRENT_THREAD_INFO(r8, r1)
lwz r8,TI_CPU(r8)
oris r8,r8,11
mfmsr r10
SYNC
rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
rlwinm r0,r0,0,28,26 /* clear DR */
mtmsr r0
SYNC_601
isync
lis r9,mmu_hash_lock@h
ori r9,r9,mmu_hash_lock@l
tophys(r9,r9)
10: lwarx r7,0,r9
cmpwi 0,r7,0
bne- 10b
stwcx. r8,0,r9
bne- 10b
eieio
tlbie r3
sync
TLBSYNC
li r0,0
stw r0,0(r9) /* clear mmu_hash_lock */
mtmsr r10
SYNC_601
isync
#else /* CONFIG_SMP */
tlbie r3
sync
#endif /* CONFIG_SMP */
blr
/*
* Flush the entire TLB. 603/603e only
*/
_GLOBAL(_tlbia)
#if defined(CONFIG_SMP)
CURRENT_THREAD_INFO(r8, r1)
lwz r8,TI_CPU(r8)
oris r8,r8,10
mfmsr r10
SYNC
rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
rlwinm r0,r0,0,28,26 /* clear DR */
mtmsr r0
SYNC_601
isync
lis r9,mmu_hash_lock@h
ori r9,r9,mmu_hash_lock@l
tophys(r9,r9)
10: lwarx r7,0,r9
cmpwi 0,r7,0
bne- 10b
stwcx. r8,0,r9
bne- 10b
sync
tlbia
sync
TLBSYNC
li r0,0
stw r0,0(r9) /* clear mmu_hash_lock */
mtmsr r10
SYNC_601
isync
#else /* CONFIG_SMP */
sync
tlbia
sync
#endif /* CONFIG_SMP */
blr
|
AirFortressIlikara/LS2K0300-linux-4.19
| 10,585
|
arch/powerpc/mm/tlb_nohash_low.S
|
/*
* This file contains low-level functions for performing various
* types of TLB invalidations on various processors with no hash
* table.
*
* This file implements the following functions for all no-hash
* processors. Some aren't implemented for some variants. Some
* are inline in tlbflush.h
*
* - tlbil_va
* - tlbil_pid
* - tlbil_all
* - tlbivax_bcast
*
* Code mostly moved over from misc_32.S
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Partially rewritten by Cort Dougan (cort@cs.nmt.edu)
* Paul Mackerras, Kumar Gala and Benjamin Herrenschmidt.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
*/
#include <asm/reg.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/mmu.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/processor.h>
#include <asm/bug.h>
#include <asm/asm-compat.h>
#include <asm/feature-fixups.h>
#if defined(CONFIG_40x)
/*
* 40x implementation needs only tlbil_va
*/
_GLOBAL(__tlbil_va)
/* We run the search with interrupts disabled because we have to change
* the PID and I don't want to preempt when that happens.
*/
mfmsr r5
mfspr r6,SPRN_PID
wrteei 0
mtspr SPRN_PID,r4
tlbsx. r3, 0, r3
mtspr SPRN_PID,r6
wrtee r5
bne 1f
sync
/* There are only 64 TLB entries, so r3 < 64, which means bit 25 is
* clear. Since 25 is the V bit in the TLB_TAG, loading this value
* will invalidate the TLB entry. */
tlbwe r3, r3, TLB_TAG
isync
1: blr
#elif defined(CONFIG_PPC_8xx)
/*
* Nothing to do for 8xx, everything is inline
*/
#elif defined(CONFIG_44x) /* Includes 47x */
/*
* 440 implementation uses tlbsx/we for tlbil_va and a full sweep
* of the TLB for everything else.
*/
_GLOBAL(__tlbil_va)
mfspr r5,SPRN_MMUCR
mfmsr r10
/*
* We write 16 bits of STID since 47x supports that much, we
* will never be passed out of bounds values on 440 (hopefully)
*/
rlwimi r5,r4,0,16,31
/* We have to run the search with interrupts disabled, otherwise
* an interrupt which causes a TLB miss can clobber the MMUCR
* between the mtspr and the tlbsx.
*
* Critical and Machine Check interrupts take care of saving
* and restoring MMUCR, so only normal interrupts have to be
* taken care of.
*/
wrteei 0
mtspr SPRN_MMUCR,r5
tlbsx. r6,0,r3
bne 10f
sync
BEGIN_MMU_FTR_SECTION
b 2f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
/* On 440 There are only 64 TLB entries, so r3 < 64, which means bit
* 22, is clear. Since 22 is the V bit in the TLB_PAGEID, loading this
* value will invalidate the TLB entry.
*/
tlbwe r6,r6,PPC44x_TLB_PAGEID
isync
10: wrtee r10
blr
2:
#ifdef CONFIG_PPC_47x
oris r7,r6,0x8000 /* specify way explicitly */
clrrwi r4,r3,12 /* get an EPN for the hashing with V = 0 */
ori r4,r4,PPC47x_TLBE_SIZE
tlbwe r4,r7,0 /* write it */
isync
wrtee r10
blr
#else /* CONFIG_PPC_47x */
1: trap
EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
#endif /* !CONFIG_PPC_47x */
_GLOBAL(_tlbil_all)
_GLOBAL(_tlbil_pid)
BEGIN_MMU_FTR_SECTION
b 2f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
li r3,0
sync
/* Load high watermark */
lis r4,tlb_44x_hwater@ha
lwz r5,tlb_44x_hwater@l(r4)
1: tlbwe r3,r3,PPC44x_TLB_PAGEID
addi r3,r3,1
cmpw 0,r3,r5
ble 1b
isync
blr
2:
#ifdef CONFIG_PPC_47x
/* 476 variant. There's not simple way to do this, hopefully we'll
* try to limit the amount of such full invalidates
*/
mfmsr r11 /* Interrupts off */
wrteei 0
li r3,-1 /* Current set */
lis r10,tlb_47x_boltmap@h
ori r10,r10,tlb_47x_boltmap@l
lis r7,0x8000 /* Specify way explicitly */
b 9f /* For each set */
1: li r9,4 /* Number of ways */
li r4,0 /* Current way */
li r6,0 /* Default entry value 0 */
andi. r0,r8,1 /* Check if way 0 is bolted */
mtctr r9 /* Load way counter */
bne- 3f /* Bolted, skip loading it */
2: /* For each way */
or r5,r3,r4 /* Make way|index for tlbre */
rlwimi r5,r5,16,8,15 /* Copy index into position */
tlbre r6,r5,0 /* Read entry */
3: addis r4,r4,0x2000 /* Next way */
andi. r0,r6,PPC47x_TLB0_VALID /* Valid entry ? */
beq 4f /* Nope, skip it */
rlwimi r7,r5,0,1,2 /* Insert way number */
rlwinm r6,r6,0,21,19 /* Clear V */
tlbwe r6,r7,0 /* Write it */
4: bdnz 2b /* Loop for each way */
srwi r8,r8,1 /* Next boltmap bit */
9: cmpwi cr1,r3,255 /* Last set done ? */
addi r3,r3,1 /* Next set */
beq cr1,1f /* End of loop */
andi. r0,r3,0x1f /* Need to load a new boltmap word ? */
bne 1b /* No, loop */
lwz r8,0(r10) /* Load boltmap entry */
addi r10,r10,4 /* Next word */
b 1b /* Then loop */
1: isync /* Sync shadows */
wrtee r11
#else /* CONFIG_PPC_47x */
1: trap
EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
#endif /* !CONFIG_PPC_47x */
blr
#ifdef CONFIG_PPC_47x
/*
* _tlbivax_bcast is only on 47x. We don't bother doing a runtime
* check though, it will blow up soon enough if we mistakenly try
* to use it on a 440.
*/
_GLOBAL(_tlbivax_bcast)
mfspr r5,SPRN_MMUCR
mfmsr r10
rlwimi r5,r4,0,16,31
wrteei 0
mtspr SPRN_MMUCR,r5
isync
PPC_TLBIVAX(0, R3)
isync
eieio
tlbsync
BEGIN_FTR_SECTION
b 1f
END_FTR_SECTION_IFSET(CPU_FTR_476_DD2)
sync
wrtee r10
blr
/*
* DD2 HW could hang if in instruction fetch happens before msync completes.
* Touch enough instruction cache lines to ensure cache hits
*/
1: mflr r9
bl 2f
2: mflr r6
li r7,32
PPC_ICBT(0,R6,R7) /* touch next cache line */
add r6,r6,r7
PPC_ICBT(0,R6,R7) /* touch next cache line */
add r6,r6,r7
PPC_ICBT(0,R6,R7) /* touch next cache line */
sync
nop
nop
nop
nop
nop
nop
nop
nop
mtlr r9
wrtee r10
blr
#endif /* CONFIG_PPC_47x */
#elif defined(CONFIG_FSL_BOOKE)
/*
* FSL BookE implementations.
*
* Since feature sections are using _SECTION_ELSE we need
* to have the larger code path before the _SECTION_ELSE
*/
/*
* Flush MMU TLB on the local processor
*/
_GLOBAL(_tlbil_all)
BEGIN_MMU_FTR_SECTION
li r3,(MMUCSR0_TLBFI)@l
mtspr SPRN_MMUCSR0, r3
1:
mfspr r3,SPRN_MMUCSR0
andi. r3,r3,MMUCSR0_TLBFI@l
bne 1b
MMU_FTR_SECTION_ELSE
PPC_TLBILX_ALL(0,R0)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
msync
isync
blr
_GLOBAL(_tlbil_pid)
BEGIN_MMU_FTR_SECTION
slwi r3,r3,16
mfmsr r10
wrteei 0
mfspr r4,SPRN_MAS6 /* save MAS6 */
mtspr SPRN_MAS6,r3
PPC_TLBILX_PID(0,R0)
mtspr SPRN_MAS6,r4 /* restore MAS6 */
wrtee r10
MMU_FTR_SECTION_ELSE
li r3,(MMUCSR0_TLBFI)@l
mtspr SPRN_MMUCSR0, r3
1:
mfspr r3,SPRN_MMUCSR0
andi. r3,r3,MMUCSR0_TLBFI@l
bne 1b
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBILX)
msync
isync
blr
/*
* Flush MMU TLB for a particular address, but only on the local processor
* (no broadcast)
*/
_GLOBAL(__tlbil_va)
mfmsr r10
wrteei 0
slwi r4,r4,16
ori r4,r4,(MAS6_ISIZE(BOOK3E_PAGESZ_4K))@l
mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
BEGIN_MMU_FTR_SECTION
tlbsx 0,r3
mfspr r4,SPRN_MAS1 /* check valid */
andis. r3,r4,MAS1_VALID@h
beq 1f
rlwinm r4,r4,0,1,31
mtspr SPRN_MAS1,r4
tlbwe
MMU_FTR_SECTION_ELSE
PPC_TLBILX_VA(0,R3)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
msync
isync
1: wrtee r10
blr
#elif defined(CONFIG_PPC_BOOK3E)
/*
* New Book3E (>= 2.06) implementation
*
* Note: We may be able to get away without the interrupt masking stuff
* if we save/restore MAS6 on exceptions that might modify it
*/
_GLOBAL(_tlbil_pid)
slwi r4,r3,MAS6_SPID_SHIFT
mfmsr r10
wrteei 0
mtspr SPRN_MAS6,r4
PPC_TLBILX_PID(0,R0)
wrtee r10
msync
isync
blr
_GLOBAL(_tlbil_pid_noind)
slwi r4,r3,MAS6_SPID_SHIFT
mfmsr r10
ori r4,r4,MAS6_SIND
wrteei 0
mtspr SPRN_MAS6,r4
PPC_TLBILX_PID(0,R0)
wrtee r10
msync
isync
blr
_GLOBAL(_tlbil_all)
PPC_TLBILX_ALL(0,R0)
msync
isync
blr
_GLOBAL(_tlbil_va)
mfmsr r10
wrteei 0
cmpwi cr0,r6,0
slwi r4,r4,MAS6_SPID_SHIFT
rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
beq 1f
rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
PPC_TLBILX_VA(0,R3)
msync
isync
wrtee r10
blr
_GLOBAL(_tlbivax_bcast)
mfmsr r10
wrteei 0
cmpwi cr0,r6,0
slwi r4,r4,MAS6_SPID_SHIFT
rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
beq 1f
rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
PPC_TLBIVAX(0,R3)
eieio
tlbsync
sync
wrtee r10
blr
_GLOBAL(set_context)
#ifdef CONFIG_BDI_SWITCH
/* Context switch the PTE pointer for the Abatron BDI2000.
* The PGDIR is the second parameter.
*/
lis r5, abatron_pteptrs@h
ori r5, r5, abatron_pteptrs@l
stw r4, 0x4(r5)
#endif
mtspr SPRN_PID,r3
isync /* Force context change */
blr
#else
#error Unsupported processor type !
#endif
#if defined(CONFIG_PPC_FSL_BOOK3E)
/*
* extern void loadcam_entry(unsigned int index)
*
* Load TLBCAM[index] entry in to the L2 CAM MMU
* Must preserve r7, r8, r9, r10 and r11
*/
_GLOBAL(loadcam_entry)
mflr r5
LOAD_REG_ADDR_PIC(r4, TLBCAM)
mtlr r5
mulli r5,r3,TLBCAM_SIZE
add r3,r5,r4
lwz r4,TLBCAM_MAS0(r3)
mtspr SPRN_MAS0,r4
lwz r4,TLBCAM_MAS1(r3)
mtspr SPRN_MAS1,r4
PPC_LL r4,TLBCAM_MAS2(r3)
mtspr SPRN_MAS2,r4
lwz r4,TLBCAM_MAS3(r3)
mtspr SPRN_MAS3,r4
BEGIN_MMU_FTR_SECTION
lwz r4,TLBCAM_MAS7(r3)
mtspr SPRN_MAS7,r4
END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
isync
tlbwe
isync
blr
/*
* Load multiple TLB entries at once, using an alternate-space
* trampoline so that we don't have to care about whether the same
* TLB entry maps us before and after.
*
* r3 = first entry to write
* r4 = number of entries to write
* r5 = temporary tlb entry
*/
_GLOBAL(loadcam_multi)
mflr r8
/* Don't switch to AS=1 if already there */
mfmsr r11
andi. r11,r11,MSR_IS
bne 10f
/*
* Set up temporary TLB entry that is the same as what we're
* running from, but in AS=1.
*/
bl 1f
1: mflr r6
tlbsx 0,r8
mfspr r6,SPRN_MAS1
ori r6,r6,MAS1_TS
mtspr SPRN_MAS1,r6
mfspr r6,SPRN_MAS0
rlwimi r6,r5,MAS0_ESEL_SHIFT,MAS0_ESEL_MASK
mr r7,r5
mtspr SPRN_MAS0,r6
isync
tlbwe
isync
/* Switch to AS=1 */
mfmsr r6
ori r6,r6,MSR_IS|MSR_DS
mtmsr r6
isync
10:
mr r9,r3
add r10,r3,r4
2: bl loadcam_entry
addi r9,r9,1
cmpw r9,r10
mr r3,r9
blt 2b
/* Don't return to AS=0 if we were in AS=1 at function start */
andi. r11,r11,MSR_IS
bne 3f
/* Return to AS=0 and clear the temporary entry */
mfmsr r6
rlwinm. r6,r6,0,~(MSR_IS|MSR_DS)
mtmsr r6
isync
li r6,0
mtspr SPRN_MAS1,r6
rlwinm r6,r7,MAS0_ESEL_SHIFT,MAS0_ESEL_MASK
oris r6,r6,MAS0_TLBSEL(1)@h
mtspr SPRN_MAS0,r6
isync
tlbwe
isync
3:
mtlr r8
blr
#endif
|
AirFortressIlikara/LS2K0300-linux-4.19
| 9,703
|
arch/powerpc/kernel/vdso32/sigtramp.S
|
/*
* Signal trampolines for 32 bits processes in a ppc64 kernel for
* use in the vDSO
*
* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
* Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/unistd.h>
#include <asm/vdso.h>
.text
/* The nop here is a hack. The dwarf2 unwind routines subtract 1 from
the return address to get an address in the middle of the presumed
call instruction. Since we don't have a call here, we artificially
extend the range covered by the unwind info by adding a nop before
the real start. */
nop
V_FUNCTION_BEGIN(__kernel_sigtramp32)
.Lsig_start = . - 4
li r0,__NR_sigreturn
sc
.Lsig_end:
V_FUNCTION_END(__kernel_sigtramp32)
.Lsigrt_start:
nop
V_FUNCTION_BEGIN(__kernel_sigtramp_rt32)
li r0,__NR_rt_sigreturn
sc
.Lsigrt_end:
V_FUNCTION_END(__kernel_sigtramp_rt32)
.section .eh_frame,"a",@progbits
/* Register r1 can be found at offset 4 of a pt_regs structure.
A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
#define cfa_save \
.byte 0x0f; /* DW_CFA_def_cfa_expression */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
.byte 0x06; /* DW_OP_deref */ \
.byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \
.byte 0x06; /* DW_OP_deref */ \
9:
/* Register REGNO can be found at offset OFS of a pt_regs structure.
A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
#define rsave(regno, ofs) \
.byte 0x10; /* DW_CFA_expression */ \
.uleb128 regno; /* regno */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
.byte 0x06; /* DW_OP_deref */ \
.ifne ofs; \
.byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
.endif; \
9:
/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
of the VMX reg struct. The VMX reg struct is at offset VREGS of
the pt_regs struct. This macro is for REGNO == 0, and contains
'subroutines' that the other macros jump to. */
#define vsave_msr0(regno) \
.byte 0x10; /* DW_CFA_expression */ \
.uleb128 regno + 77; /* regno */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x30 + regno; /* DW_OP_lit0 */ \
2: \
.byte 0x40; /* DW_OP_lit16 */ \
.byte 0x1e; /* DW_OP_mul */ \
3: \
.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
.byte 0x06; /* DW_OP_deref */ \
.byte 0x12; /* DW_OP_dup */ \
.byte 0x23; /* DW_OP_plus_uconst */ \
.uleb128 33*RSIZE; /* msr offset */ \
.byte 0x06; /* DW_OP_deref */ \
.byte 0x0c; .long 1 << 25; /* DW_OP_const4u */ \
.byte 0x1a; /* DW_OP_and */ \
.byte 0x12; /* DW_OP_dup, ret 0 if bra taken */ \
.byte 0x30; /* DW_OP_lit0 */ \
.byte 0x29; /* DW_OP_eq */ \
.byte 0x28; .short 0x7fff; /* DW_OP_bra to end */ \
.byte 0x13; /* DW_OP_drop, pop the 0 */ \
.byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
.byte 0x22; /* DW_OP_plus */ \
.byte 0x2f; .short 0x7fff; /* DW_OP_skip to end */ \
9:
/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
of the VMX reg struct. REGNO is 1 thru 31. */
#define vsave_msr1(regno) \
.byte 0x10; /* DW_CFA_expression */ \
.uleb128 regno + 77; /* regno */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x30 + regno; /* DW_OP_lit n */ \
.byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
9:
/* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
the VMX save block. */
#define vsave_msr2(regno, ofs) \
.byte 0x10; /* DW_CFA_expression */ \
.uleb128 regno + 77; /* regno */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x0a; .short ofs; /* DW_OP_const2u */ \
.byte 0x2f; .short 3b - 9f; /* DW_OP_skip */ \
9:
/* VMX register REGNO is at offset OFS of the VMX save area. */
#define vsave(regno, ofs) \
.byte 0x10; /* DW_CFA_expression */ \
.uleb128 regno + 77; /* regno */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
.byte 0x06; /* DW_OP_deref */ \
.byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
.byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
9:
/* This is where the pt_regs pointer can be found on the stack. */
#define PTREGS 64+28
/* Size of regs. */
#define RSIZE 4
/* This is the offset of the VMX regs. */
#define VREGS 48*RSIZE+34*8
/* Describe where general purpose regs are saved. */
#define EH_FRAME_GEN \
cfa_save; \
rsave ( 0, 0*RSIZE); \
rsave ( 2, 2*RSIZE); \
rsave ( 3, 3*RSIZE); \
rsave ( 4, 4*RSIZE); \
rsave ( 5, 5*RSIZE); \
rsave ( 6, 6*RSIZE); \
rsave ( 7, 7*RSIZE); \
rsave ( 8, 8*RSIZE); \
rsave ( 9, 9*RSIZE); \
rsave (10, 10*RSIZE); \
rsave (11, 11*RSIZE); \
rsave (12, 12*RSIZE); \
rsave (13, 13*RSIZE); \
rsave (14, 14*RSIZE); \
rsave (15, 15*RSIZE); \
rsave (16, 16*RSIZE); \
rsave (17, 17*RSIZE); \
rsave (18, 18*RSIZE); \
rsave (19, 19*RSIZE); \
rsave (20, 20*RSIZE); \
rsave (21, 21*RSIZE); \
rsave (22, 22*RSIZE); \
rsave (23, 23*RSIZE); \
rsave (24, 24*RSIZE); \
rsave (25, 25*RSIZE); \
rsave (26, 26*RSIZE); \
rsave (27, 27*RSIZE); \
rsave (28, 28*RSIZE); \
rsave (29, 29*RSIZE); \
rsave (30, 30*RSIZE); \
rsave (31, 31*RSIZE); \
rsave (67, 32*RSIZE); /* ap, used as temp for nip */ \
rsave (65, 36*RSIZE); /* lr */ \
rsave (70, 38*RSIZE) /* cr */
/* Describe where the FP regs are saved. */
#define EH_FRAME_FP \
rsave (32, 48*RSIZE + 0*8); \
rsave (33, 48*RSIZE + 1*8); \
rsave (34, 48*RSIZE + 2*8); \
rsave (35, 48*RSIZE + 3*8); \
rsave (36, 48*RSIZE + 4*8); \
rsave (37, 48*RSIZE + 5*8); \
rsave (38, 48*RSIZE + 6*8); \
rsave (39, 48*RSIZE + 7*8); \
rsave (40, 48*RSIZE + 8*8); \
rsave (41, 48*RSIZE + 9*8); \
rsave (42, 48*RSIZE + 10*8); \
rsave (43, 48*RSIZE + 11*8); \
rsave (44, 48*RSIZE + 12*8); \
rsave (45, 48*RSIZE + 13*8); \
rsave (46, 48*RSIZE + 14*8); \
rsave (47, 48*RSIZE + 15*8); \
rsave (48, 48*RSIZE + 16*8); \
rsave (49, 48*RSIZE + 17*8); \
rsave (50, 48*RSIZE + 18*8); \
rsave (51, 48*RSIZE + 19*8); \
rsave (52, 48*RSIZE + 20*8); \
rsave (53, 48*RSIZE + 21*8); \
rsave (54, 48*RSIZE + 22*8); \
rsave (55, 48*RSIZE + 23*8); \
rsave (56, 48*RSIZE + 24*8); \
rsave (57, 48*RSIZE + 25*8); \
rsave (58, 48*RSIZE + 26*8); \
rsave (59, 48*RSIZE + 27*8); \
rsave (60, 48*RSIZE + 28*8); \
rsave (61, 48*RSIZE + 29*8); \
rsave (62, 48*RSIZE + 30*8); \
rsave (63, 48*RSIZE + 31*8)
/* Describe where the VMX regs are saved. */
#ifdef CONFIG_ALTIVEC
#define EH_FRAME_VMX \
vsave_msr0 ( 0); \
vsave_msr1 ( 1); \
vsave_msr1 ( 2); \
vsave_msr1 ( 3); \
vsave_msr1 ( 4); \
vsave_msr1 ( 5); \
vsave_msr1 ( 6); \
vsave_msr1 ( 7); \
vsave_msr1 ( 8); \
vsave_msr1 ( 9); \
vsave_msr1 (10); \
vsave_msr1 (11); \
vsave_msr1 (12); \
vsave_msr1 (13); \
vsave_msr1 (14); \
vsave_msr1 (15); \
vsave_msr1 (16); \
vsave_msr1 (17); \
vsave_msr1 (18); \
vsave_msr1 (19); \
vsave_msr1 (20); \
vsave_msr1 (21); \
vsave_msr1 (22); \
vsave_msr1 (23); \
vsave_msr1 (24); \
vsave_msr1 (25); \
vsave_msr1 (26); \
vsave_msr1 (27); \
vsave_msr1 (28); \
vsave_msr1 (29); \
vsave_msr1 (30); \
vsave_msr1 (31); \
vsave_msr2 (33, 32*16+12); \
vsave (32, 32*16)
#else
#define EH_FRAME_VMX
#endif
.Lcie:
.long .Lcie_end - .Lcie_start
.Lcie_start:
.long 0 /* CIE ID */
.byte 1 /* Version number */
.string "zRS" /* NUL-terminated augmentation string */
.uleb128 4 /* Code alignment factor */
.sleb128 -4 /* Data alignment factor */
.byte 67 /* Return address register column, ap */
.uleb128 1 /* Augmentation value length */
.byte 0x1b /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */
.byte 0x0c,1,0 /* DW_CFA_def_cfa: r1 ofs 0 */
.balign 4
.Lcie_end:
.long .Lfde0_end - .Lfde0_start
.Lfde0_start:
.long .Lfde0_start - .Lcie /* CIE pointer. */
.long .Lsig_start - . /* PC start, length */
.long .Lsig_end - .Lsig_start
.uleb128 0 /* Augmentation */
EH_FRAME_GEN
EH_FRAME_FP
EH_FRAME_VMX
.balign 4
.Lfde0_end:
/* We have a different stack layout for rt_sigreturn. */
#undef PTREGS
#define PTREGS 64+16+128+20+28
.long .Lfde1_end - .Lfde1_start
.Lfde1_start:
.long .Lfde1_start - .Lcie /* CIE pointer. */
.long .Lsigrt_start - . /* PC start, length */
.long .Lsigrt_end - .Lsigrt_start
.uleb128 0 /* Augmentation */
EH_FRAME_GEN
EH_FRAME_FP
EH_FRAME_VMX
.balign 4
.Lfde1_end:
|
AirFortressIlikara/LS2K0300-linux-4.19
| 3,950
|
arch/powerpc/kernel/vdso32/vdso32.lds.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This is the infamous ld script for the 32 bits vdso
* library
*/
#include <asm/vdso.h>
#ifdef __LITTLE_ENDIAN__
OUTPUT_FORMAT("elf32-powerpcle", "elf32-powerpcle", "elf32-powerpcle")
#else
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", "elf32-powerpc")
#endif
OUTPUT_ARCH(powerpc:common)
ENTRY(_start)
SECTIONS
{
. = VDSO32_LBASE + SIZEOF_HEADERS;
.hash : { *(.hash) } :text
.gnu.hash : { *(.gnu.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.note : { *(.note.*) } :text :note
. = ALIGN(16);
.text : {
*(.text .stub .text.* .gnu.linkonce.t.* __ftr_alt_*)
} :text
PROVIDE(__etext = .);
PROVIDE(_etext = .);
PROVIDE(etext = .);
. = ALIGN(8);
__ftr_fixup : { *(__ftr_fixup) }
. = ALIGN(8);
__mmu_ftr_fixup : { *(__mmu_ftr_fixup) }
. = ALIGN(8);
__lwsync_fixup : { *(__lwsync_fixup) }
#ifdef CONFIG_PPC64
. = ALIGN(8);
__fw_ftr_fixup : { *(__fw_ftr_fixup) }
#endif
/*
* Other stuff is appended to the text segment:
*/
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
.eh_frame_hdr : { *(.eh_frame_hdr) } :text :eh_frame_hdr
.eh_frame : { KEEP (*(.eh_frame)) } :text
.gcc_except_table : { *(.gcc_except_table) }
.fixup : { *(.fixup) }
.dynamic : { *(.dynamic) } :text :dynamic
.got : { *(.got) } :text
.plt : { *(.plt) }
_end = .;
__end = .;
PROVIDE(end = .);
/*
* Stabs debugging sections are here too.
*/
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/*
* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0.
*/
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/DISCARD/ : {
*(.note.GNU-stack)
*(.data .data.* .gnu.linkonce.d.* .sdata*)
*(.bss .sbss .dynbss .dynsbss)
}
}
/*
* Very old versions of ld do not recognize this name token; use the constant.
*/
#define PT_GNU_EH_FRAME 0x6474e550
/*
* We must supply the ELF program headers explicitly to get just one
* PT_LOAD segment, and set the flags explicitly to make segments read-only.
*/
PHDRS
{
text PT_LOAD FILEHDR PHDRS FLAGS(5); /* PF_R|PF_X */
dynamic PT_DYNAMIC FLAGS(4); /* PF_R */
note PT_NOTE FLAGS(4); /* PF_R */
eh_frame_hdr PT_GNU_EH_FRAME;
}
/*
* This controls what symbols we export from the DSO.
*/
VERSION
{
VDSO_VERSION_STRING {
global:
/*
* Has to be there for the kernel to find
*/
__kernel_datapage_offset;
__kernel_get_syscall_map;
__kernel_gettimeofday;
__kernel_clock_gettime;
__kernel_clock_getres;
__kernel_get_tbfreq;
__kernel_sync_dicache;
__kernel_sync_dicache_p5;
__kernel_sigtramp32;
__kernel_sigtramp_rt32;
#ifdef CONFIG_PPC64
__kernel_getcpu;
#endif
__kernel_time;
local: *;
};
}
|
AirFortressIlikara/LS2K0300-linux-4.19
| 2,120
|
arch/powerpc/kernel/vdso32/datapage.S
|
/*
* Access to the shared data page by the vDSO & syscall map
*
* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/unistd.h>
#include <asm/vdso.h>
.text
.global __kernel_datapage_offset;
__kernel_datapage_offset:
.long 0
V_FUNCTION_BEGIN(__get_datapage)
.cfi_startproc
/* We don't want that exposed or overridable as we want other objects
* to be able to bl directly to here
*/
.protected __get_datapage
.hidden __get_datapage
mflr r0
.cfi_register lr,r0
bcl 20,31,data_page_branch
data_page_branch:
mflr r3
mtlr r0
addi r3, r3, __kernel_datapage_offset-data_page_branch
lwz r0,0(r3)
.cfi_restore lr
add r3,r0,r3
blr
.cfi_endproc
V_FUNCTION_END(__get_datapage)
/*
* void *__kernel_get_syscall_map(unsigned int *syscall_count) ;
*
* returns a pointer to the syscall map. the map is agnostic to the
* size of "long", unlike kernel bitops, it stores bits from top to
* bottom so that memory actually contains a linear bitmap
* check for syscall N by testing bit (0x80000000 >> (N & 0x1f)) of
* 32 bits int at N >> 5.
*/
V_FUNCTION_BEGIN(__kernel_get_syscall_map)
.cfi_startproc
mflr r12
.cfi_register lr,r12
mr r4,r3
bl __get_datapage@local
mtlr r12
addi r3,r3,CFG_SYSCALL_MAP32
cmpli cr0,r4,0
beqlr
li r0,NR_syscalls
stw r0,0(r4)
crclr cr0*4+so
blr
.cfi_endproc
V_FUNCTION_END(__kernel_get_syscall_map)
/*
* void unsigned long long __kernel_get_tbfreq(void);
*
* returns the timebase frequency in HZ
*/
V_FUNCTION_BEGIN(__kernel_get_tbfreq)
.cfi_startproc
mflr r12
.cfi_register lr,r12
bl __get_datapage@local
lwz r4,(CFG_TB_TICKS_PER_SEC + 4)(r3)
lwz r3,CFG_TB_TICKS_PER_SEC(r3)
mtlr r12
crclr cr0*4+so
blr
.cfi_endproc
V_FUNCTION_END(__kernel_get_tbfreq)
|
AirFortressIlikara/LS2K0300-linux-4.19
| 1,897
|
arch/powerpc/kernel/vdso32/cacheflush.S
|
/*
* vDSO provided cache flush routines
*
* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
* IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/vdso.h>
#include <asm/asm-offsets.h>
.text
/*
* Default "generic" version of __kernel_sync_dicache.
*
* void __kernel_sync_dicache(unsigned long start, unsigned long end)
*
* Flushes the data cache & invalidate the instruction cache for the
* provided range [start, end[
*/
V_FUNCTION_BEGIN(__kernel_sync_dicache)
.cfi_startproc
mflr r12
.cfi_register lr,r12
mr r11,r3
bl __get_datapage@local
mtlr r12
mr r10,r3
lwz r7,CFG_DCACHE_BLOCKSZ(r10)
addi r5,r7,-1
andc r6,r11,r5 /* round low to line bdy */
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10)
srw. r8,r8,r9 /* compute line count */
crclr cr0*4+so
beqlr /* nothing to do? */
mtctr r8
1: dcbst 0,r6
add r6,r6,r7
bdnz 1b
sync
/* Now invalidate the instruction cache */
lwz r7,CFG_ICACHE_BLOCKSZ(r10)
addi r5,r7,-1
andc r6,r11,r5 /* round low to line bdy */
subf r8,r6,r4 /* compute length */
add r8,r8,r5
lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10)
srw. r8,r8,r9 /* compute line count */
crclr cr0*4+so
beqlr /* nothing to do? */
mtctr r8
2: icbi 0,r6
add r6,r6,r7
bdnz 2b
isync
li r3,0
blr
.cfi_endproc
V_FUNCTION_END(__kernel_sync_dicache)
/*
* POWER5 version of __kernel_sync_dicache
*/
V_FUNCTION_BEGIN(__kernel_sync_dicache_p5)
.cfi_startproc
crclr cr0*4+so
sync
isync
li r3,0
blr
.cfi_endproc
V_FUNCTION_END(__kernel_sync_dicache_p5)
|
AirFortressIlikara/LS2K0300-linux-4.19
| 7,061
|
arch/powerpc/kernel/vdso32/gettimeofday.S
|
/*
* Userland implementation of gettimeofday() for 32 bits processes in a
* ppc64 kernel for use in the vDSO
*
* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org,
* IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/vdso.h>
#include <asm/asm-offsets.h>
#include <asm/unistd.h>
/* Offset for the low 32-bit part of a field of long type */
#ifdef CONFIG_PPC64
#define LOPART 4
#define TSPEC_TV_SEC TSPC64_TV_SEC+LOPART
#else
#define LOPART 0
#define TSPEC_TV_SEC TSPC32_TV_SEC
#endif
.text
/*
* Exact prototype of gettimeofday
*
* int __kernel_gettimeofday(struct timeval *tv, struct timezone *tz);
*
*/
V_FUNCTION_BEGIN(__kernel_gettimeofday)
.cfi_startproc
mflr r12
.cfi_register lr,r12
mr r10,r3 /* r10 saves tv */
mr r11,r4 /* r11 saves tz */
bl __get_datapage@local /* get data page */
mr r9, r3 /* datapage ptr in r9 */
cmplwi r10,0 /* check if tv is NULL */
beq 3f
lis r7,1000000@ha /* load up USEC_PER_SEC */
addi r7,r7,1000000@l /* so we get microseconds in r4 */
bl __do_get_tspec@local /* get sec/usec from tb & kernel */
stw r3,TVAL32_TV_SEC(r10)
stw r4,TVAL32_TV_USEC(r10)
3: cmplwi r11,0 /* check if tz is NULL */
beq 1f
lwz r4,CFG_TZ_MINUTEWEST(r9)/* fill tz */
lwz r5,CFG_TZ_DSTTIME(r9)
stw r4,TZONE_TZ_MINWEST(r11)
stw r5,TZONE_TZ_DSTTIME(r11)
1: mtlr r12
crclr cr0*4+so
li r3,0
blr
.cfi_endproc
V_FUNCTION_END(__kernel_gettimeofday)
/*
* Exact prototype of clock_gettime()
*
* int __kernel_clock_gettime(clockid_t clock_id, struct timespec *tp);
*
*/
V_FUNCTION_BEGIN(__kernel_clock_gettime)
.cfi_startproc
/* Check for supported clock IDs */
cmpli cr0,r3,CLOCK_REALTIME
cmpli cr1,r3,CLOCK_MONOTONIC
cror cr0*4+eq,cr0*4+eq,cr1*4+eq
bne cr0,99f
mflr r12 /* r12 saves lr */
.cfi_register lr,r12
mr r11,r4 /* r11 saves tp */
bl __get_datapage@local /* get data page */
mr r9,r3 /* datapage ptr in r9 */
lis r7,NSEC_PER_SEC@h /* want nanoseconds */
ori r7,r7,NSEC_PER_SEC@l
50: bl __do_get_tspec@local /* get sec/nsec from tb & kernel */
bne cr1,80f /* not monotonic -> all done */
/*
* CLOCK_MONOTONIC
*/
/* now we must fixup using wall to monotonic. We need to snapshot
* that value and do the counter trick again. Fortunately, we still
* have the counter value in r8 that was returned by __do_get_xsec.
* At this point, r3,r4 contain our sec/nsec values, r5 and r6
* can be used, r7 contains NSEC_PER_SEC.
*/
lwz r5,(WTOM_CLOCK_SEC+LOPART)(r9)
lwz r6,WTOM_CLOCK_NSEC(r9)
/* We now have our offset in r5,r6. We create a fake dependency
* on that value and re-check the counter
*/
or r0,r6,r5
xor r0,r0,r0
add r9,r9,r0
lwz r0,(CFG_TB_UPDATE_COUNT+LOPART)(r9)
cmpl cr0,r8,r0 /* check if updated */
bne- 50b
/* Calculate and store result. Note that this mimics the C code,
* which may cause funny results if nsec goes negative... is that
* possible at all ?
*/
add r3,r3,r5
add r4,r4,r6
cmpw cr0,r4,r7
cmpwi cr1,r4,0
blt 1f
subf r4,r7,r4
addi r3,r3,1
1: bge cr1,80f
addi r3,r3,-1
add r4,r4,r7
80: stw r3,TSPC32_TV_SEC(r11)
stw r4,TSPC32_TV_NSEC(r11)
mtlr r12
crclr cr0*4+so
li r3,0
blr
/*
* syscall fallback
*/
99:
li r0,__NR_clock_gettime
.cfi_restore lr
sc
blr
.cfi_endproc
V_FUNCTION_END(__kernel_clock_gettime)
/*
* Exact prototype of clock_getres()
*
* int __kernel_clock_getres(clockid_t clock_id, struct timespec *res);
*
*/
V_FUNCTION_BEGIN(__kernel_clock_getres)
.cfi_startproc
/* Check for supported clock IDs */
cmpwi cr0,r3,CLOCK_REALTIME
cmpwi cr1,r3,CLOCK_MONOTONIC
cror cr0*4+eq,cr0*4+eq,cr1*4+eq
bne cr0,99f
mflr r12
.cfi_register lr,r12
bl __get_datapage@local /* get data page */
lwz r5, CLOCK_HRTIMER_RES(r3)
mtlr r12
li r3,0
cmpli cr0,r4,0
crclr cr0*4+so
beqlr
stw r3,TSPC32_TV_SEC(r4)
stw r5,TSPC32_TV_NSEC(r4)
blr
/*
* syscall fallback
*/
99:
li r0,__NR_clock_getres
sc
blr
.cfi_endproc
V_FUNCTION_END(__kernel_clock_getres)
/*
* Exact prototype of time()
*
* time_t time(time *t);
*
*/
V_FUNCTION_BEGIN(__kernel_time)
.cfi_startproc
mflr r12
.cfi_register lr,r12
mr r11,r3 /* r11 holds t */
bl __get_datapage@local
mr r9, r3 /* datapage ptr in r9 */
lwz r3,STAMP_XTIME+TSPEC_TV_SEC(r9)
cmplwi r11,0 /* check if t is NULL */
beq 2f
stw r3,0(r11) /* store result at *t */
2: mtlr r12
crclr cr0*4+so
blr
.cfi_endproc
V_FUNCTION_END(__kernel_time)
/*
* This is the core of clock_gettime() and gettimeofday(),
* it returns the current time in r3 (seconds) and r4.
* On entry, r7 gives the resolution of r4, either USEC_PER_SEC
* or NSEC_PER_SEC, giving r4 in microseconds or nanoseconds.
* It expects the datapage ptr in r9 and doesn't clobber it.
* It clobbers r0, r5 and r6.
* On return, r8 contains the counter value that can be reused.
* This clobbers cr0 but not any other cr field.
*/
__do_get_tspec:
.cfi_startproc
/* Check for update count & load values. We use the low
* order 32 bits of the update count
*/
1: lwz r8,(CFG_TB_UPDATE_COUNT+LOPART)(r9)
andi. r0,r8,1 /* pending update ? loop */
bne- 1b
xor r0,r8,r8 /* create dependency */
add r9,r9,r0
/* Load orig stamp (offset to TB) */
lwz r5,CFG_TB_ORIG_STAMP(r9)
lwz r6,(CFG_TB_ORIG_STAMP+4)(r9)
/* Get a stable TB value */
2: MFTBU(r3)
MFTBL(r4)
MFTBU(r0)
cmplw cr0,r3,r0
bne- 2b
/* Subtract tb orig stamp and shift left 12 bits.
*/
subfc r4,r6,r4
subfe r0,r5,r3
slwi r0,r0,12
rlwimi. r0,r4,12,20,31
slwi r4,r4,12
/*
* Load scale factor & do multiplication.
* We only use the high 32 bits of the tb_to_xs value.
* Even with a 1GHz timebase clock, the high 32 bits of
* tb_to_xs will be at least 4 million, so the error from
* ignoring the low 32 bits will be no more than 0.25ppm.
* The error will just make the clock run very very slightly
* slow until the next time the kernel updates the VDSO data,
* at which point the clock will catch up to the kernel's value,
* so there is no long-term error accumulation.
*/
lwz r5,CFG_TB_TO_XS(r9) /* load values */
mulhwu r4,r4,r5
li r3,0
beq+ 4f /* skip high part computation if 0 */
mulhwu r3,r0,r5
mullw r5,r0,r5
addc r4,r4,r5
addze r3,r3
4:
/* At this point, we have seconds since the xtime stamp
* as a 32.32 fixed-point number in r3 and r4.
* Load & add the xtime stamp.
*/
lwz r5,STAMP_XTIME+TSPEC_TV_SEC(r9)
lwz r6,STAMP_SEC_FRAC(r9)
addc r4,r4,r6
adde r3,r3,r5
/* We create a fake dependency on the result in r3/r4
* and re-check the counter
*/
or r6,r4,r3
xor r0,r6,r6
add r9,r9,r0
lwz r0,(CFG_TB_UPDATE_COUNT+LOPART)(r9)
cmplw cr0,r8,r0 /* check if updated */
bne- 1b
mulhwu r4,r4,r7 /* convert to micro or nanoseconds */
blr
.cfi_endproc
|
AirFortressIlikara/LS2K0300-linux-4.19
| 1,280
|
arch/powerpc/kernel/vdso32/getcpu.S
|
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) IBM Corporation, 2012
*
* Author: Anton Blanchard <anton@au.ibm.com>
*/
#include <asm/ppc_asm.h>
#include <asm/vdso.h>
.text
/*
* Exact prototype of getcpu
*
* int __kernel_getcpu(unsigned *cpu, unsigned *node);
*
*/
V_FUNCTION_BEGIN(__kernel_getcpu)
.cfi_startproc
mfspr r5,SPRN_SPRG_VDSO_READ
cmpwi cr0,r3,0
cmpwi cr1,r4,0
clrlwi r6,r5,16
rlwinm r7,r5,16,31-15,31-0
beq cr0,1f
stw r6,0(r3)
1: beq cr1,2f
stw r7,0(r4)
2: crclr cr0*4+so
li r3,0 /* always success */
blr
.cfi_endproc
V_FUNCTION_END(__kernel_getcpu)
|
AirFortressIlikara/LS2K0300-linux-4.19
| 10,459
|
arch/powerpc/kernel/vdso64/sigtramp.S
|
/*
* Signal trampoline for 64 bits processes in a ppc64 kernel for
* use in the vDSO
*
* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
* Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/unistd.h>
#include <asm/vdso.h>
#include <asm/ptrace.h> /* XXX for __SIGNAL_FRAMESIZE */
.text
/* The nop here is a hack. The dwarf2 unwind routines subtract 1 from
the return address to get an address in the middle of the presumed
call instruction. Since we don't have a call here, we artificially
extend the range covered by the unwind info by padding before the
real start. */
nop
.balign 8
V_FUNCTION_BEGIN(__kernel_sigtramp_rt64)
.Lsigrt_start = . - 4
addi r1, r1, __SIGNAL_FRAMESIZE
li r0,__NR_rt_sigreturn
sc
.Lsigrt_end:
V_FUNCTION_END(__kernel_sigtramp_rt64)
/* The ".balign 8" above and the following zeros mimic the old stack
trampoline layout. The last magic value is the ucontext pointer,
chosen in such a way that older libgcc unwind code returns a zero
for a sigcontext pointer. */
.long 0,0,0
.quad 0,-21*8
/* Register r1 can be found at offset 8 of a pt_regs structure.
A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
#define cfa_save \
.byte 0x0f; /* DW_CFA_def_cfa_expression */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
.byte 0x06; /* DW_OP_deref */ \
.byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \
.byte 0x06; /* DW_OP_deref */ \
9:
/* Register REGNO can be found at offset OFS of a pt_regs structure.
A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
#define rsave(regno, ofs) \
.byte 0x10; /* DW_CFA_expression */ \
.uleb128 regno; /* regno */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
.byte 0x06; /* DW_OP_deref */ \
.ifne ofs; \
.byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
.endif; \
9:
/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
of the VMX reg struct. A pointer to the VMX reg struct is at VREGS in
the pt_regs struct. This macro is for REGNO == 0, and contains
'subroutines' that the other macros jump to. */
#define vsave_msr0(regno) \
.byte 0x10; /* DW_CFA_expression */ \
.uleb128 regno + 77; /* regno */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x30 + regno; /* DW_OP_lit0 */ \
2: \
.byte 0x40; /* DW_OP_lit16 */ \
.byte 0x1e; /* DW_OP_mul */ \
3: \
.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
.byte 0x06; /* DW_OP_deref */ \
.byte 0x12; /* DW_OP_dup */ \
.byte 0x23; /* DW_OP_plus_uconst */ \
.uleb128 33*RSIZE; /* msr offset */ \
.byte 0x06; /* DW_OP_deref */ \
.byte 0x0c; .long 1 << 25; /* DW_OP_const4u */ \
.byte 0x1a; /* DW_OP_and */ \
.byte 0x12; /* DW_OP_dup, ret 0 if bra taken */ \
.byte 0x30; /* DW_OP_lit0 */ \
.byte 0x29; /* DW_OP_eq */ \
.byte 0x28; .short 0x7fff; /* DW_OP_bra to end */ \
.byte 0x13; /* DW_OP_drop, pop the 0 */ \
.byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
.byte 0x06; /* DW_OP_deref */ \
.byte 0x22; /* DW_OP_plus */ \
.byte 0x2f; .short 0x7fff; /* DW_OP_skip to end */ \
9:
/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
of the VMX reg struct. REGNO is 1 thru 31. */
#define vsave_msr1(regno) \
.byte 0x10; /* DW_CFA_expression */ \
.uleb128 regno + 77; /* regno */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x30 + regno; /* DW_OP_lit n */ \
.byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
9:
/* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
the VMX save block. */
#define vsave_msr2(regno, ofs) \
.byte 0x10; /* DW_CFA_expression */ \
.uleb128 regno + 77; /* regno */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x0a; .short ofs; /* DW_OP_const2u */ \
.byte 0x2f; .short 3b - 9f; /* DW_OP_skip */ \
9:
/* VMX register REGNO is at offset OFS of the VMX save area. */
#define vsave(regno, ofs) \
.byte 0x10; /* DW_CFA_expression */ \
.uleb128 regno + 77; /* regno */ \
.uleb128 9f - 1f; /* length */ \
1: \
.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
.byte 0x06; /* DW_OP_deref */ \
.byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
.byte 0x06; /* DW_OP_deref */ \
.byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
9:
/* This is where the pt_regs pointer can be found on the stack. */
#define PTREGS 128+168+56
/* Size of regs. */
#define RSIZE 8
/* Size of CR reg in DWARF unwind info. */
#define CRSIZE 4
/* Offset of CR reg within a full word. */
#ifdef __LITTLE_ENDIAN__
#define CROFF 0
#else
#define CROFF (RSIZE - CRSIZE)
#endif
/* This is the offset of the VMX reg pointer. */
#define VREGS 48*RSIZE+33*8
/* Describe where general purpose regs are saved. */
#define EH_FRAME_GEN \
cfa_save; \
rsave ( 0, 0*RSIZE); \
rsave ( 2, 2*RSIZE); \
rsave ( 3, 3*RSIZE); \
rsave ( 4, 4*RSIZE); \
rsave ( 5, 5*RSIZE); \
rsave ( 6, 6*RSIZE); \
rsave ( 7, 7*RSIZE); \
rsave ( 8, 8*RSIZE); \
rsave ( 9, 9*RSIZE); \
rsave (10, 10*RSIZE); \
rsave (11, 11*RSIZE); \
rsave (12, 12*RSIZE); \
rsave (13, 13*RSIZE); \
rsave (14, 14*RSIZE); \
rsave (15, 15*RSIZE); \
rsave (16, 16*RSIZE); \
rsave (17, 17*RSIZE); \
rsave (18, 18*RSIZE); \
rsave (19, 19*RSIZE); \
rsave (20, 20*RSIZE); \
rsave (21, 21*RSIZE); \
rsave (22, 22*RSIZE); \
rsave (23, 23*RSIZE); \
rsave (24, 24*RSIZE); \
rsave (25, 25*RSIZE); \
rsave (26, 26*RSIZE); \
rsave (27, 27*RSIZE); \
rsave (28, 28*RSIZE); \
rsave (29, 29*RSIZE); \
rsave (30, 30*RSIZE); \
rsave (31, 31*RSIZE); \
rsave (67, 32*RSIZE); /* ap, used as temp for nip */ \
rsave (65, 36*RSIZE); /* lr */ \
rsave (68, 38*RSIZE + CROFF); /* cr fields */ \
rsave (69, 38*RSIZE + CROFF); \
rsave (70, 38*RSIZE + CROFF); \
rsave (71, 38*RSIZE + CROFF); \
rsave (72, 38*RSIZE + CROFF); \
rsave (73, 38*RSIZE + CROFF); \
rsave (74, 38*RSIZE + CROFF); \
rsave (75, 38*RSIZE + CROFF)
/* Describe where the FP regs are saved. */
#define EH_FRAME_FP \
rsave (32, 48*RSIZE + 0*8); \
rsave (33, 48*RSIZE + 1*8); \
rsave (34, 48*RSIZE + 2*8); \
rsave (35, 48*RSIZE + 3*8); \
rsave (36, 48*RSIZE + 4*8); \
rsave (37, 48*RSIZE + 5*8); \
rsave (38, 48*RSIZE + 6*8); \
rsave (39, 48*RSIZE + 7*8); \
rsave (40, 48*RSIZE + 8*8); \
rsave (41, 48*RSIZE + 9*8); \
rsave (42, 48*RSIZE + 10*8); \
rsave (43, 48*RSIZE + 11*8); \
rsave (44, 48*RSIZE + 12*8); \
rsave (45, 48*RSIZE + 13*8); \
rsave (46, 48*RSIZE + 14*8); \
rsave (47, 48*RSIZE + 15*8); \
rsave (48, 48*RSIZE + 16*8); \
rsave (49, 48*RSIZE + 17*8); \
rsave (50, 48*RSIZE + 18*8); \
rsave (51, 48*RSIZE + 19*8); \
rsave (52, 48*RSIZE + 20*8); \
rsave (53, 48*RSIZE + 21*8); \
rsave (54, 48*RSIZE + 22*8); \
rsave (55, 48*RSIZE + 23*8); \
rsave (56, 48*RSIZE + 24*8); \
rsave (57, 48*RSIZE + 25*8); \
rsave (58, 48*RSIZE + 26*8); \
rsave (59, 48*RSIZE + 27*8); \
rsave (60, 48*RSIZE + 28*8); \
rsave (61, 48*RSIZE + 29*8); \
rsave (62, 48*RSIZE + 30*8); \
rsave (63, 48*RSIZE + 31*8)
/* Describe where the VMX regs are saved. */
#ifdef CONFIG_ALTIVEC
#define EH_FRAME_VMX \
vsave_msr0 ( 0); \
vsave_msr1 ( 1); \
vsave_msr1 ( 2); \
vsave_msr1 ( 3); \
vsave_msr1 ( 4); \
vsave_msr1 ( 5); \
vsave_msr1 ( 6); \
vsave_msr1 ( 7); \
vsave_msr1 ( 8); \
vsave_msr1 ( 9); \
vsave_msr1 (10); \
vsave_msr1 (11); \
vsave_msr1 (12); \
vsave_msr1 (13); \
vsave_msr1 (14); \
vsave_msr1 (15); \
vsave_msr1 (16); \
vsave_msr1 (17); \
vsave_msr1 (18); \
vsave_msr1 (19); \
vsave_msr1 (20); \
vsave_msr1 (21); \
vsave_msr1 (22); \
vsave_msr1 (23); \
vsave_msr1 (24); \
vsave_msr1 (25); \
vsave_msr1 (26); \
vsave_msr1 (27); \
vsave_msr1 (28); \
vsave_msr1 (29); \
vsave_msr1 (30); \
vsave_msr1 (31); \
vsave_msr2 (33, 32*16+12); \
vsave (32, 33*16)
#else
#define EH_FRAME_VMX
#endif
.section .eh_frame,"a",@progbits
.Lcie:
.long .Lcie_end - .Lcie_start
.Lcie_start:
.long 0 /* CIE ID */
.byte 1 /* Version number */
.string "zRS" /* NUL-terminated augmentation string */
.uleb128 4 /* Code alignment factor */
.sleb128 -8 /* Data alignment factor */
.byte 67 /* Return address register column, ap */
.uleb128 1 /* Augmentation value length */
.byte 0x14 /* DW_EH_PE_pcrel | DW_EH_PE_udata8. */
.byte 0x0c,1,0 /* DW_CFA_def_cfa: r1 ofs 0 */
.balign 8
.Lcie_end:
.long .Lfde0_end - .Lfde0_start
.Lfde0_start:
.long .Lfde0_start - .Lcie /* CIE pointer. */
.quad .Lsigrt_start - . /* PC start, length */
.quad .Lsigrt_end - .Lsigrt_start
.uleb128 0 /* Augmentation */
EH_FRAME_GEN
EH_FRAME_FP
EH_FRAME_VMX
# Do we really need to describe the frame at this point? ie. will
# we ever have some call chain that returns somewhere past the addi?
# I don't think so, since gcc doesn't support async signals.
# .byte 0x41 /* DW_CFA_advance_loc 1*4 */
#undef PTREGS
#define PTREGS 168+56
# EH_FRAME_GEN
# EH_FRAME_FP
# EH_FRAME_VMX
.balign 8
.Lfde0_end:
|
AirFortressIlikara/LS2K0300-linux-4.19
| 3,909
|
arch/powerpc/kernel/vdso64/vdso64.lds.S
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This is the infamous ld script for the 64 bits vdso
* library
*/
#include <asm/vdso.h>
#ifdef __LITTLE_ENDIAN__
OUTPUT_FORMAT("elf64-powerpcle", "elf64-powerpcle", "elf64-powerpcle")
#else
OUTPUT_FORMAT("elf64-powerpc", "elf64-powerpc", "elf64-powerpc")
#endif
OUTPUT_ARCH(powerpc:common64)
ENTRY(_start)
SECTIONS
{
. = VDSO64_LBASE + SIZEOF_HEADERS;
.hash : { *(.hash) } :text
.gnu.hash : { *(.gnu.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.note : { *(.note.*) } :text :note
. = ALIGN(16);
.text : {
*(.text .stub .text.* .gnu.linkonce.t.* __ftr_alt_*)
*(.sfpr .glink)
} :text
PROVIDE(__etext = .);
PROVIDE(_etext = .);
PROVIDE(etext = .);
. = ALIGN(8);
__ftr_fixup : { *(__ftr_fixup) }
. = ALIGN(8);
__mmu_ftr_fixup : { *(__mmu_ftr_fixup) }
. = ALIGN(8);
__lwsync_fixup : { *(__lwsync_fixup) }
. = ALIGN(8);
__fw_ftr_fixup : { *(__fw_ftr_fixup) }
/*
* Other stuff is appended to the text segment:
*/
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
.dynamic : { *(.dynamic) } :text :dynamic
.eh_frame_hdr : { *(.eh_frame_hdr) } :text :eh_frame_hdr
.eh_frame : { KEEP (*(.eh_frame)) } :text
.gcc_except_table : { *(.gcc_except_table) }
.rela.dyn ALIGN(8) : { *(.rela.dyn) }
.opd ALIGN(8) : { KEEP (*(.opd)) }
.got ALIGN(8) : { *(.got .toc) }
_end = .;
PROVIDE(end = .);
/*
* Stabs debugging sections are here too.
*/
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/*
* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0.
*/
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/DISCARD/ : {
*(.note.GNU-stack)
*(.branch_lt)
*(.data .data.* .gnu.linkonce.d.* .sdata*)
*(.bss .sbss .dynbss .dynsbss)
}
}
/*
* Very old versions of ld do not recognize this name token; use the constant.
*/
#define PT_GNU_EH_FRAME 0x6474e550
/*
* We must supply the ELF program headers explicitly to get just one
* PT_LOAD segment, and set the flags explicitly to make segments read-only.
*/
PHDRS
{
text PT_LOAD FILEHDR PHDRS FLAGS(5); /* PF_R|PF_X */
dynamic PT_DYNAMIC FLAGS(4); /* PF_R */
note PT_NOTE FLAGS(4); /* PF_R */
eh_frame_hdr PT_GNU_EH_FRAME;
}
/*
* This controls what symbols we export from the DSO.
*/
VERSION
{
VDSO_VERSION_STRING {
global:
/*
* Has to be there for the kernel to find
*/
__kernel_datapage_offset;
__kernel_get_syscall_map;
__kernel_gettimeofday;
__kernel_clock_gettime;
__kernel_clock_getres;
__kernel_get_tbfreq;
__kernel_sync_dicache;
__kernel_sync_dicache_p5;
__kernel_sigtramp_rt64;
__kernel_getcpu;
__kernel_time;
local: *;
};
}
|
AirFortressIlikara/LS2K0300-linux-4.19
| 2,092
|
arch/powerpc/kernel/vdso64/datapage.S
|
/*
* Access to the shared data page by the vDSO & syscall map
*
* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/unistd.h>
#include <asm/vdso.h>
.text
.global __kernel_datapage_offset;
__kernel_datapage_offset:
.long 0
V_FUNCTION_BEGIN(__get_datapage)
.cfi_startproc
/* We don't want that exposed or overridable as we want other objects
* to be able to bl directly to here
*/
.protected __get_datapage
.hidden __get_datapage
mflr r0
.cfi_register lr,r0
bcl 20,31,data_page_branch
data_page_branch:
mflr r3
mtlr r0
addi r3, r3, __kernel_datapage_offset-data_page_branch
lwz r0,0(r3)
.cfi_restore lr
add r3,r0,r3
blr
.cfi_endproc
V_FUNCTION_END(__get_datapage)
/*
* void *__kernel_get_syscall_map(unsigned int *syscall_count) ;
*
* returns a pointer to the syscall map. the map is agnostic to the
* size of "long", unlike kernel bitops, it stores bits from top to
* bottom so that memory actually contains a linear bitmap
* check for syscall N by testing bit (0x80000000 >> (N & 0x1f)) of
* 32 bits int at N >> 5.
*/
V_FUNCTION_BEGIN(__kernel_get_syscall_map)
.cfi_startproc
mflr r12
.cfi_register lr,r12
mr r4,r3
bl V_LOCAL_FUNC(__get_datapage)
mtlr r12
addi r3,r3,CFG_SYSCALL_MAP64
cmpldi cr0,r4,0
crclr cr0*4+so
beqlr
li r0,NR_syscalls
stw r0,0(r4)
blr
.cfi_endproc
V_FUNCTION_END(__kernel_get_syscall_map)
/*
* void unsigned long __kernel_get_tbfreq(void);
*
* returns the timebase frequency in HZ
*/
V_FUNCTION_BEGIN(__kernel_get_tbfreq)
.cfi_startproc
mflr r12
.cfi_register lr,r12
bl V_LOCAL_FUNC(__get_datapage)
ld r3,CFG_TB_TICKS_PER_SEC(r3)
mtlr r12
crclr cr0*4+so
blr
.cfi_endproc
V_FUNCTION_END(__kernel_get_tbfreq)
|
AirFortressIlikara/LS2K0300-linux-4.19
| 1,904
|
arch/powerpc/kernel/vdso64/cacheflush.S
|
/*
* vDSO provided cache flush routines
*
* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
* IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/vdso.h>
#include <asm/asm-offsets.h>
.text
/*
* Default "generic" version of __kernel_sync_dicache.
*
* void __kernel_sync_dicache(unsigned long start, unsigned long end)
*
* Flushes the data cache & invalidate the instruction cache for the
* provided range [start, end[
*/
V_FUNCTION_BEGIN(__kernel_sync_dicache)
.cfi_startproc
mflr r12
.cfi_register lr,r12
mr r11,r3
bl V_LOCAL_FUNC(__get_datapage)
mtlr r12
mr r10,r3
lwz r7,CFG_DCACHE_BLOCKSZ(r10)
addi r5,r7,-1
andc r6,r11,r5 /* round low to line bdy */
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10)
srd. r8,r8,r9 /* compute line count */
crclr cr0*4+so
beqlr /* nothing to do? */
mtctr r8
1: dcbst 0,r6
add r6,r6,r7
bdnz 1b
sync
/* Now invalidate the instruction cache */
lwz r7,CFG_ICACHE_BLOCKSZ(r10)
addi r5,r7,-1
andc r6,r11,r5 /* round low to line bdy */
subf r8,r6,r4 /* compute length */
add r8,r8,r5
lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10)
srd. r8,r8,r9 /* compute line count */
crclr cr0*4+so
beqlr /* nothing to do? */
mtctr r8
2: icbi 0,r6
add r6,r6,r7
bdnz 2b
isync
li r3,0
blr
.cfi_endproc
V_FUNCTION_END(__kernel_sync_dicache)
/*
* POWER5 version of __kernel_sync_dicache
*/
V_FUNCTION_BEGIN(__kernel_sync_dicache_p5)
.cfi_startproc
crclr cr0*4+so
sync
isync
li r3,0
blr
.cfi_endproc
V_FUNCTION_END(__kernel_sync_dicache_p5)
|
AirFortressIlikara/LS2K0300-linux-4.19
| 7,083
|
arch/powerpc/kernel/vdso64/gettimeofday.S
|
/*
* Userland implementation of gettimeofday() for 64 bits processes in a
* ppc64 kernel for use in the vDSO
*
* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
* IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/vdso.h>
#include <asm/asm-offsets.h>
#include <asm/unistd.h>
.text
/*
* Exact prototype of gettimeofday
*
* int __kernel_gettimeofday(struct timeval *tv, struct timezone *tz);
*
*/
V_FUNCTION_BEGIN(__kernel_gettimeofday)
.cfi_startproc
mflr r12
.cfi_register lr,r12
mr r11,r3 /* r11 holds tv */
mr r10,r4 /* r10 holds tz */
bl V_LOCAL_FUNC(__get_datapage) /* get data page */
cmpldi r11,0 /* check if tv is NULL */
beq 2f
lis r7,1000000@ha /* load up USEC_PER_SEC */
addi r7,r7,1000000@l
bl V_LOCAL_FUNC(__do_get_tspec) /* get sec/us from tb & kernel */
std r4,TVAL64_TV_SEC(r11) /* store sec in tv */
std r5,TVAL64_TV_USEC(r11) /* store usec in tv */
2: cmpldi r10,0 /* check if tz is NULL */
beq 1f
lwz r4,CFG_TZ_MINUTEWEST(r3)/* fill tz */
lwz r5,CFG_TZ_DSTTIME(r3)
stw r4,TZONE_TZ_MINWEST(r10)
stw r5,TZONE_TZ_DSTTIME(r10)
1: mtlr r12
crclr cr0*4+so
li r3,0 /* always success */
blr
.cfi_endproc
V_FUNCTION_END(__kernel_gettimeofday)
/*
* Exact prototype of clock_gettime()
*
* int __kernel_clock_gettime(clockid_t clock_id, struct timespec *tp);
*
*/
V_FUNCTION_BEGIN(__kernel_clock_gettime)
.cfi_startproc
/* Check for supported clock IDs */
cmpwi cr0,r3,CLOCK_REALTIME
cmpwi cr1,r3,CLOCK_MONOTONIC
cror cr0*4+eq,cr0*4+eq,cr1*4+eq
cmpwi cr5,r3,CLOCK_REALTIME_COARSE
cmpwi cr6,r3,CLOCK_MONOTONIC_COARSE
cror cr5*4+eq,cr5*4+eq,cr6*4+eq
cror cr0*4+eq,cr0*4+eq,cr5*4+eq
bne cr0,99f
mflr r12 /* r12 saves lr */
.cfi_register lr,r12
mr r11,r4 /* r11 saves tp */
bl V_LOCAL_FUNC(__get_datapage) /* get data page */
lis r7,NSEC_PER_SEC@h /* want nanoseconds */
ori r7,r7,NSEC_PER_SEC@l
beq cr5,70f
50: bl V_LOCAL_FUNC(__do_get_tspec) /* get time from tb & kernel */
bne cr1,80f /* if not monotonic, all done */
/*
* CLOCK_MONOTONIC
*/
/* now we must fixup using wall to monotonic. We need to snapshot
* that value and do the counter trick again. Fortunately, we still
* have the counter value in r8 that was returned by __do_get_tspec.
* At this point, r4,r5 contain our sec/nsec values.
*/
ld r6,WTOM_CLOCK_SEC(r3)
lwa r9,WTOM_CLOCK_NSEC(r3)
/* We now have our result in r6,r9. We create a fake dependency
* on that result and re-check the counter
*/
or r0,r6,r9
xor r0,r0,r0
add r3,r3,r0
ld r0,CFG_TB_UPDATE_COUNT(r3)
cmpld cr0,r0,r8 /* check if updated */
bne- 50b
b 78f
/*
* For coarse clocks we get data directly from the vdso data page, so
* we don't need to call __do_get_tspec, but we still need to do the
* counter trick.
*/
70: ld r8,CFG_TB_UPDATE_COUNT(r3)
andi. r0,r8,1 /* pending update ? loop */
bne- 70b
add r3,r3,r0 /* r0 is already 0 */
/*
* CLOCK_REALTIME_COARSE, below values are needed for MONOTONIC_COARSE
* too
*/
ld r4,STAMP_XTIME+TSPC64_TV_SEC(r3)
ld r5,STAMP_XTIME+TSPC64_TV_NSEC(r3)
bne cr6,75f
/* CLOCK_MONOTONIC_COARSE */
ld r6,WTOM_CLOCK_SEC(r3)
lwa r9,WTOM_CLOCK_NSEC(r3)
/* check if counter has updated */
or r0,r6,r9
75: or r0,r0,r4
or r0,r0,r5
xor r0,r0,r0
add r3,r3,r0
ld r0,CFG_TB_UPDATE_COUNT(r3)
cmpld cr0,r0,r8 /* check if updated */
bne- 70b
/* Counter has not updated, so continue calculating proper values for
* sec and nsec if monotonic coarse, or just return with the proper
* values for realtime.
*/
bne cr6,80f
/* Add wall->monotonic offset and check for overflow or underflow */
78: add r4,r4,r6
add r5,r5,r9
cmpd cr0,r5,r7
cmpdi cr1,r5,0
blt 79f
subf r5,r7,r5
addi r4,r4,1
79: bge cr1,80f
addi r4,r4,-1
add r5,r5,r7
80: std r4,TSPC64_TV_SEC(r11)
std r5,TSPC64_TV_NSEC(r11)
mtlr r12
crclr cr0*4+so
li r3,0
blr
/*
* syscall fallback
*/
99:
li r0,__NR_clock_gettime
.cfi_restore lr
sc
blr
.cfi_endproc
V_FUNCTION_END(__kernel_clock_gettime)
/*
* Exact prototype of clock_getres()
*
* int __kernel_clock_getres(clockid_t clock_id, struct timespec *res);
*
*/
V_FUNCTION_BEGIN(__kernel_clock_getres)
.cfi_startproc
/* Check for supported clock IDs */
cmpwi cr0,r3,CLOCK_REALTIME
cmpwi cr1,r3,CLOCK_MONOTONIC
cror cr0*4+eq,cr0*4+eq,cr1*4+eq
bne cr0,99f
mflr r12
.cfi_register lr,r12
bl V_LOCAL_FUNC(__get_datapage)
lwz r5, CLOCK_HRTIMER_RES(r3)
mtlr r12
li r3,0
cmpldi cr0,r4,0
crclr cr0*4+so
beqlr
std r3,TSPC64_TV_SEC(r4)
std r5,TSPC64_TV_NSEC(r4)
blr
/*
* syscall fallback
*/
99:
li r0,__NR_clock_getres
sc
blr
.cfi_endproc
V_FUNCTION_END(__kernel_clock_getres)
/*
* Exact prototype of time()
*
* time_t time(time *t);
*
*/
V_FUNCTION_BEGIN(__kernel_time)
.cfi_startproc
mflr r12
.cfi_register lr,r12
mr r11,r3 /* r11 holds t */
bl V_LOCAL_FUNC(__get_datapage)
ld r4,STAMP_XTIME+TSPC64_TV_SEC(r3)
cmpldi r11,0 /* check if t is NULL */
beq 2f
std r4,0(r11) /* store result at *t */
2: mtlr r12
crclr cr0*4+so
mr r3,r4
blr
.cfi_endproc
V_FUNCTION_END(__kernel_time)
/*
* This is the core of clock_gettime() and gettimeofday(),
* it returns the current time in r4 (seconds) and r5.
* On entry, r7 gives the resolution of r5, either USEC_PER_SEC
* or NSEC_PER_SEC, giving r5 in microseconds or nanoseconds.
* It expects the datapage ptr in r3 and doesn't clobber it.
* It clobbers r0, r6 and r9.
* On return, r8 contains the counter value that can be reused.
* This clobbers cr0 but not any other cr field.
*/
V_FUNCTION_BEGIN(__do_get_tspec)
.cfi_startproc
/* check for update count & load values */
1: ld r8,CFG_TB_UPDATE_COUNT(r3)
andi. r0,r8,1 /* pending update ? loop */
bne- 1b
xor r0,r8,r8 /* create dependency */
add r3,r3,r0
/* Get TB & offset it. We use the MFTB macro which will generate
* workaround code for Cell.
*/
MFTB(r6)
ld r9,CFG_TB_ORIG_STAMP(r3)
subf r6,r9,r6
/* Scale result */
ld r5,CFG_TB_TO_XS(r3)
sldi r6,r6,12 /* compute time since stamp_xtime */
mulhdu r6,r6,r5 /* in units of 2^-32 seconds */
/* Add stamp since epoch */
ld r4,STAMP_XTIME+TSPC64_TV_SEC(r3)
lwz r5,STAMP_SEC_FRAC(r3)
or r0,r4,r5
or r0,r0,r6
xor r0,r0,r0
add r3,r3,r0
ld r0,CFG_TB_UPDATE_COUNT(r3)
cmpld r0,r8 /* check if updated */
bne- 1b /* reload if so */
/* convert to seconds & nanoseconds and add to stamp */
add r6,r6,r5 /* add on fractional seconds of xtime */
mulhwu r5,r6,r7 /* compute micro or nanoseconds and */
srdi r6,r6,32 /* seconds since stamp_xtime */
clrldi r5,r5,32
add r4,r4,r6
blr
.cfi_endproc
V_FUNCTION_END(__do_get_tspec)
|
AirFortressIlikara/LS2K0300-linux-4.19
| 1,280
|
arch/powerpc/kernel/vdso64/getcpu.S
|
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) IBM Corporation, 2012
*
* Author: Anton Blanchard <anton@au.ibm.com>
*/
#include <asm/ppc_asm.h>
#include <asm/vdso.h>
.text
/*
* Exact prototype of getcpu
*
* int __kernel_getcpu(unsigned *cpu, unsigned *node);
*
*/
V_FUNCTION_BEGIN(__kernel_getcpu)
.cfi_startproc
mfspr r5,SPRN_SPRG_VDSO_READ
cmpdi cr0,r3,0
cmpdi cr1,r4,0
clrlwi r6,r5,16
rlwinm r7,r5,16,31-15,31-0
beq cr0,1f
stw r6,0(r3)
1: beq cr1,2f
stw r7,0(r4)
2: crclr cr0*4+so
li r3,0 /* always success */
blr
.cfi_endproc
V_FUNCTION_END(__kernel_getcpu)
|
AirFortressIlikara/LS2K0300-linux-4.19
| 2,094
|
arch/powerpc/kernel/trace/ftrace_32.S
|
/*
* Split from entry_32.S
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/magic.h>
#include <asm/reg.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/ftrace.h>
#include <asm/export.h>
_GLOBAL(mcount)
_GLOBAL(_mcount)
/*
* It is required that _mcount on PPC32 must preserve the
* link register. But we have r0 to play with. We use r0
* to push the return address back to the caller of mcount
* into the ctr register, restore the link register and
* then jump back using the ctr register.
*/
mflr r0
mtctr r0
lwz r0, 4(r1)
mtlr r0
bctr
_GLOBAL(ftrace_caller)
MCOUNT_SAVE_FRAME
/* r3 ends up with link register */
subi r3, r3, MCOUNT_INSN_SIZE
.globl ftrace_call
ftrace_call:
bl ftrace_stub
nop
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
.globl ftrace_graph_call
ftrace_graph_call:
b ftrace_graph_stub
_GLOBAL(ftrace_graph_stub)
#endif
MCOUNT_RESTORE_FRAME
/* old link register ends up in ctr reg */
bctr
EXPORT_SYMBOL(_mcount)
_GLOBAL(ftrace_stub)
blr
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
_GLOBAL(ftrace_graph_caller)
/* load r4 with local address */
lwz r4, 44(r1)
subi r4, r4, MCOUNT_INSN_SIZE
/* Grab the LR out of the caller stack frame */
lwz r3,52(r1)
bl prepare_ftrace_return
nop
/*
* prepare_ftrace_return gives us the address we divert to.
* Change the LR in the callers stack frame to this.
*/
stw r3,52(r1)
MCOUNT_RESTORE_FRAME
/* old link register ends up in ctr reg */
bctr
_GLOBAL(return_to_handler)
/* need to save return values */
stwu r1, -32(r1)
stw r3, 20(r1)
stw r4, 16(r1)
stw r31, 12(r1)
mr r31, r1
bl ftrace_return_to_handler
nop
/* return value has real return address */
mtlr r3
lwz r3, 20(r1)
lwz r4, 16(r1)
lwz r31,12(r1)
lwz r1, 0(r1)
/* Jump back to real return address */
blr
#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
|
AirFortressIlikara/LS2K0300-linux-4.19
| 1,133
|
arch/powerpc/kernel/trace/ftrace_64.S
|
/*
* Split from entry_64.S
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/magic.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/ftrace.h>
#include <asm/ppc-opcode.h>
#include <asm/export.h>
_GLOBAL(mcount)
_GLOBAL(_mcount)
EXPORT_SYMBOL(_mcount)
mflr r12
mtctr r12
mtlr r0
bctr
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
_GLOBAL(return_to_handler)
/* need to save return values */
std r4, -32(r1)
std r3, -24(r1)
/* save TOC */
std r2, -16(r1)
std r31, -8(r1)
mr r31, r1
stdu r1, -112(r1)
/*
* We might be called from a module.
* Switch to our TOC to run inside the core kernel.
*/
ld r2, PACATOC(r13)
bl ftrace_return_to_handler
nop
/* return value has real return address */
mtlr r3
ld r1, 0(r1)
ld r4, -32(r1)
ld r3, -24(r1)
ld r2, -16(r1)
ld r31, -8(r1)
/* Jump back to real return address */
blr
#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
|
AirFortressIlikara/LS2K0300-linux-4.19
| 1,457
|
arch/powerpc/kernel/trace/ftrace_64_pg.S
|
/*
* Split from ftrace_64.S
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/magic.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/ftrace.h>
#include <asm/ppc-opcode.h>
#include <asm/export.h>
_GLOBAL_TOC(ftrace_caller)
lbz r3, PACA_FTRACE_ENABLED(r13)
cmpdi r3, 0
beqlr
/* Taken from output of objdump from lib64/glibc */
mflr r3
ld r11, 0(r1)
stdu r1, -112(r1)
std r3, 128(r1)
ld r4, 16(r11)
subi r3, r3, MCOUNT_INSN_SIZE
.globl ftrace_call
ftrace_call:
bl ftrace_stub
nop
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
.globl ftrace_graph_call
ftrace_graph_call:
b ftrace_graph_stub
_GLOBAL(ftrace_graph_stub)
#endif
ld r0, 128(r1)
mtlr r0
addi r1, r1, 112
_GLOBAL(ftrace_stub)
blr
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
_GLOBAL(ftrace_graph_caller)
/* load r4 with local address */
ld r4, 128(r1)
subi r4, r4, MCOUNT_INSN_SIZE
/* Grab the LR out of the caller stack frame */
ld r11, 112(r1)
ld r3, 16(r11)
bl prepare_ftrace_return
nop
/*
* prepare_ftrace_return gives us the address we divert to.
* Change the LR in the callers stack frame to this.
*/
ld r11, 112(r1)
std r3, 16(r11)
ld r0, 128(r1)
mtlr r0
addi r1, r1, 112
blr
#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
|
AirFortressIlikara/LS2K0300-linux-4.19
| 7,441
|
arch/powerpc/kernel/trace/ftrace_64_mprofile.S
|
/*
* Split from ftrace_64.S
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/magic.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/ftrace.h>
#include <asm/ppc-opcode.h>
#include <asm/export.h>
#include <asm/thread_info.h>
#include <asm/bug.h>
#include <asm/ptrace.h>
/*
*
* ftrace_caller()/ftrace_regs_caller() is the function that replaces _mcount()
* when ftrace is active.
*
* We arrive here after a function A calls function B, and we are the trace
* function for B. When we enter r1 points to A's stack frame, B has not yet
* had a chance to allocate one yet.
*
* Additionally r2 may point either to the TOC for A, or B, depending on
* whether B did a TOC setup sequence before calling us.
*
* On entry the LR points back to the _mcount() call site, and r0 holds the
* saved LR as it was on entry to B, ie. the original return address at the
* call site in A.
*
* Our job is to save the register state into a struct pt_regs (on the stack)
* and then arrange for the ftrace function to be called.
*/
_GLOBAL(ftrace_regs_caller)
/* Save the original return address in A's stack frame */
std r0,LRSAVE(r1)
/* Create our stack frame + pt_regs */
stdu r1,-SWITCH_FRAME_SIZE(r1)
/* Save all gprs to pt_regs */
SAVE_GPR(0, r1)
SAVE_10GPRS(2, r1)
/* Ok to continue? */
lbz r3, PACA_FTRACE_ENABLED(r13)
cmpdi r3, 0
beq ftrace_no_trace
SAVE_10GPRS(12, r1)
SAVE_10GPRS(22, r1)
/* Save previous stack pointer (r1) */
addi r8, r1, SWITCH_FRAME_SIZE
std r8, GPR1(r1)
/* Load special regs for save below */
mfmsr r8
mfctr r9
mfxer r10
mfcr r11
/* Get the _mcount() call site out of LR */
mflr r7
/* Save it as pt_regs->nip */
std r7, _NIP(r1)
/* Save the read LR in pt_regs->link */
std r0, _LINK(r1)
/* Save callee's TOC in the ABI compliant location */
std r2, 24(r1)
ld r2,PACATOC(r13) /* get kernel TOC in r2 */
addis r3,r2,function_trace_op@toc@ha
addi r3,r3,function_trace_op@toc@l
ld r5,0(r3)
#ifdef CONFIG_LIVEPATCH
mr r14,r7 /* remember old NIP */
#endif
/* Calculate ip from nip-4 into r3 for call below */
subi r3, r7, MCOUNT_INSN_SIZE
/* Put the original return address in r4 as parent_ip */
mr r4, r0
/* Save special regs */
std r8, _MSR(r1)
std r9, _CTR(r1)
std r10, _XER(r1)
std r11, _CCR(r1)
/* Load &pt_regs in r6 for call below */
addi r6, r1 ,STACK_FRAME_OVERHEAD
/* ftrace_call(r3, r4, r5, r6) */
.globl ftrace_regs_call
ftrace_regs_call:
bl ftrace_stub
nop
/* Load ctr with the possibly modified NIP */
ld r3, _NIP(r1)
mtctr r3
#ifdef CONFIG_LIVEPATCH
cmpd r14, r3 /* has NIP been altered? */
#endif
/* Restore gprs */
REST_GPR(0,r1)
REST_10GPRS(2,r1)
REST_10GPRS(12,r1)
REST_10GPRS(22,r1)
/* Restore possibly modified LR */
ld r0, _LINK(r1)
mtlr r0
/* Restore callee's TOC */
ld r2, 24(r1)
/* Pop our stack frame */
addi r1, r1, SWITCH_FRAME_SIZE
#ifdef CONFIG_LIVEPATCH
/* Based on the cmpd above, if the NIP was altered handle livepatch */
bne- livepatch_handler
#endif
ftrace_caller_common:
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
.globl ftrace_graph_call
ftrace_graph_call:
b ftrace_graph_stub
_GLOBAL(ftrace_graph_stub)
#endif
bctr /* jump after _mcount site */
_GLOBAL(ftrace_stub)
blr
ftrace_no_trace:
mflr r3
mtctr r3
REST_GPR(3, r1)
addi r1, r1, SWITCH_FRAME_SIZE
mtlr r0
bctr
_GLOBAL(ftrace_caller)
/* Save the original return address in A's stack frame */
std r0, LRSAVE(r1)
/* Create our stack frame + pt_regs */
stdu r1, -SWITCH_FRAME_SIZE(r1)
/* Save all gprs to pt_regs */
SAVE_8GPRS(3, r1)
lbz r3, PACA_FTRACE_ENABLED(r13)
cmpdi r3, 0
beq ftrace_no_trace
/* Get the _mcount() call site out of LR */
mflr r7
std r7, _NIP(r1)
/* Save callee's TOC in the ABI compliant location */
std r2, 24(r1)
ld r2, PACATOC(r13) /* get kernel TOC in r2 */
addis r3, r2, function_trace_op@toc@ha
addi r3, r3, function_trace_op@toc@l
ld r5, 0(r3)
/* Calculate ip from nip-4 into r3 for call below */
subi r3, r7, MCOUNT_INSN_SIZE
/* Put the original return address in r4 as parent_ip */
mr r4, r0
/* Set pt_regs to NULL */
li r6, 0
/* ftrace_call(r3, r4, r5, r6) */
.globl ftrace_call
ftrace_call:
bl ftrace_stub
nop
ld r3, _NIP(r1)
mtctr r3
/* Restore gprs */
REST_8GPRS(3,r1)
/* Restore callee's TOC */
ld r2, 24(r1)
/* Pop our stack frame */
addi r1, r1, SWITCH_FRAME_SIZE
/* Reload original LR */
ld r0, LRSAVE(r1)
mtlr r0
/* Handle function_graph or go back */
b ftrace_caller_common
#ifdef CONFIG_LIVEPATCH
/*
* This function runs in the mcount context, between two functions. As
* such it can only clobber registers which are volatile and used in
* function linkage.
*
* We get here when a function A, calls another function B, but B has
* been live patched with a new function C.
*
* On entry:
* - we have no stack frame and can not allocate one
* - LR points back to the original caller (in A)
* - CTR holds the new NIP in C
* - r0, r11 & r12 are free
*/
livepatch_handler:
CURRENT_THREAD_INFO(r12, r1)
/* Allocate 3 x 8 bytes */
ld r11, TI_livepatch_sp(r12)
addi r11, r11, 24
std r11, TI_livepatch_sp(r12)
/* Save toc & real LR on livepatch stack */
std r2, -24(r11)
mflr r12
std r12, -16(r11)
/* Store stack end marker */
lis r12, STACK_END_MAGIC@h
ori r12, r12, STACK_END_MAGIC@l
std r12, -8(r11)
/* Put ctr in r12 for global entry and branch there */
mfctr r12
bctrl
/*
* Now we are returning from the patched function to the original
* caller A. We are free to use r11, r12 and we can use r2 until we
* restore it.
*/
CURRENT_THREAD_INFO(r12, r1)
ld r11, TI_livepatch_sp(r12)
/* Check stack marker hasn't been trashed */
lis r2, STACK_END_MAGIC@h
ori r2, r2, STACK_END_MAGIC@l
ld r12, -8(r11)
1: tdne r12, r2
EMIT_BUG_ENTRY 1b, __FILE__, __LINE__ - 1, 0
/* Restore LR & toc from livepatch stack */
ld r12, -16(r11)
mtlr r12
ld r2, -24(r11)
/* Pop livepatch stack frame */
CURRENT_THREAD_INFO(r12, r1)
subi r11, r11, 24
std r11, TI_livepatch_sp(r12)
/* Return to original caller of live patched function */
blr
#endif /* CONFIG_LIVEPATCH */
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
_GLOBAL(ftrace_graph_caller)
stdu r1, -112(r1)
/* with -mprofile-kernel, parameter regs are still alive at _mcount */
std r10, 104(r1)
std r9, 96(r1)
std r8, 88(r1)
std r7, 80(r1)
std r6, 72(r1)
std r5, 64(r1)
std r4, 56(r1)
std r3, 48(r1)
/* Save callee's TOC in the ABI compliant location */
std r2, 24(r1)
ld r2, PACATOC(r13) /* get kernel TOC in r2 */
mfctr r4 /* ftrace_caller has moved local addr here */
std r4, 40(r1)
mflr r3 /* ftrace_caller has restored LR from stack */
subi r4, r4, MCOUNT_INSN_SIZE
bl prepare_ftrace_return
nop
/*
* prepare_ftrace_return gives us the address we divert to.
* Change the LR to this.
*/
mtlr r3
ld r0, 40(r1)
mtctr r0
ld r10, 104(r1)
ld r9, 96(r1)
ld r8, 88(r1)
ld r7, 80(r1)
ld r6, 72(r1)
ld r5, 64(r1)
ld r4, 56(r1)
ld r3, 48(r1)
/* Restore callee's TOC */
ld r2, 24(r1)
addi r1, r1, 112
mflr r0
std r0, LRSAVE(r1)
bctr
#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
|
AirFortressIlikara/LS2K0300-linux-4.19
| 12,311
|
arch/powerpc/platforms/powernv/opal-wrappers.S
|
/*
* PowerNV OPAL API wrappers
*
* Copyright 2011 IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/jump_label.h>
#include <asm/ppc_asm.h>
#include <asm/hvcall.h>
#include <asm/asm-offsets.h>
#include <asm/opal.h>
#include <asm/asm-compat.h>
#include <asm/feature-fixups.h>
.section ".text"
#ifdef CONFIG_TRACEPOINTS
#ifdef CONFIG_JUMP_LABEL
#define OPAL_BRANCH(LABEL) \
ARCH_STATIC_BRANCH(LABEL, opal_tracepoint_key)
#else
.section ".toc","aw"
.globl opal_tracepoint_refcount
opal_tracepoint_refcount:
.8byte 0
.section ".text"
/*
* We branch around this in early init by using an unconditional cpu
* feature.
*/
#define OPAL_BRANCH(LABEL) \
BEGIN_FTR_SECTION; \
b 1f; \
END_FTR_SECTION(0, 1); \
ld r11,opal_tracepoint_refcount@toc(r2); \
cmpdi r11,0; \
bne- LABEL; \
1:
#endif
#else
#define OPAL_BRANCH(LABEL)
#endif
/*
* DO_OPAL_CALL assumes:
* r0 = opal call token
* r12 = msr
* LR has been saved
*/
#define DO_OPAL_CALL() \
mfcr r11; \
stw r11,8(r1); \
li r11,0; \
ori r11,r11,MSR_EE; \
std r12,PACASAVEDMSR(r13); \
andc r12,r12,r11; \
mtmsrd r12,1; \
LOAD_REG_ADDR(r11,opal_return); \
mtlr r11; \
li r11,MSR_DR|MSR_IR|MSR_LE;\
andc r12,r12,r11; \
mtspr SPRN_HSRR1,r12; \
LOAD_REG_ADDR(r11,opal); \
ld r12,8(r11); \
ld r2,0(r11); \
mtspr SPRN_HSRR0,r12; \
hrfid
#define OPAL_CALL(name, token) \
_GLOBAL_TOC(name); \
mfmsr r12; \
mflr r0; \
andi. r11,r12,MSR_IR|MSR_DR; \
std r0,PPC_LR_STKOFF(r1); \
li r0,token; \
beq opal_real_call; \
OPAL_BRANCH(opal_tracepoint_entry) \
DO_OPAL_CALL()
opal_return:
/*
* Fixup endian on OPAL return... we should be able to simplify
* this by instead converting the below trampoline to a set of
* bytes (always BE) since MSR:LE will end up fixed up as a side
* effect of the rfid.
*/
FIXUP_ENDIAN_HV
ld r2,PACATOC(r13);
lwz r4,8(r1);
ld r5,PPC_LR_STKOFF(r1);
ld r6,PACASAVEDMSR(r13);
mtcr r4;
mtspr SPRN_HSRR0,r5;
mtspr SPRN_HSRR1,r6;
hrfid
opal_real_call:
mfcr r11
stw r11,8(r1)
/* Set opal return address */
LOAD_REG_ADDR(r11, opal_return_realmode)
mtlr r11
li r11,MSR_LE
andc r12,r12,r11
mtspr SPRN_HSRR1,r12
LOAD_REG_ADDR(r11,opal)
ld r12,8(r11)
ld r2,0(r11)
mtspr SPRN_HSRR0,r12
hrfid
opal_return_realmode:
FIXUP_ENDIAN_HV
ld r2,PACATOC(r13);
lwz r11,8(r1);
ld r12,PPC_LR_STKOFF(r1)
mtcr r11;
mtlr r12
blr
#ifdef CONFIG_TRACEPOINTS
opal_tracepoint_entry:
stdu r1,-STACKFRAMESIZE(r1)
std r0,STK_REG(R23)(r1)
std r3,STK_REG(R24)(r1)
std r4,STK_REG(R25)(r1)
std r5,STK_REG(R26)(r1)
std r6,STK_REG(R27)(r1)
std r7,STK_REG(R28)(r1)
std r8,STK_REG(R29)(r1)
std r9,STK_REG(R30)(r1)
std r10,STK_REG(R31)(r1)
mr r3,r0
addi r4,r1,STK_REG(R24)
bl __trace_opal_entry
ld r0,STK_REG(R23)(r1)
ld r3,STK_REG(R24)(r1)
ld r4,STK_REG(R25)(r1)
ld r5,STK_REG(R26)(r1)
ld r6,STK_REG(R27)(r1)
ld r7,STK_REG(R28)(r1)
ld r8,STK_REG(R29)(r1)
ld r9,STK_REG(R30)(r1)
ld r10,STK_REG(R31)(r1)
/* setup LR so we return via tracepoint_return */
LOAD_REG_ADDR(r11,opal_tracepoint_return)
std r11,16(r1)
mfmsr r12
DO_OPAL_CALL()
opal_tracepoint_return:
std r3,STK_REG(R31)(r1)
mr r4,r3
ld r3,STK_REG(R23)(r1)
bl __trace_opal_exit
ld r3,STK_REG(R31)(r1)
addi r1,r1,STACKFRAMESIZE
ld r0,16(r1)
mtlr r0
blr
#endif
OPAL_CALL(opal_invalid_call, OPAL_INVALID_CALL);
OPAL_CALL(opal_console_write, OPAL_CONSOLE_WRITE);
OPAL_CALL(opal_console_read, OPAL_CONSOLE_READ);
OPAL_CALL(opal_console_write_buffer_space, OPAL_CONSOLE_WRITE_BUFFER_SPACE);
OPAL_CALL(opal_rtc_read, OPAL_RTC_READ);
OPAL_CALL(opal_rtc_write, OPAL_RTC_WRITE);
OPAL_CALL(opal_cec_power_down, OPAL_CEC_POWER_DOWN);
OPAL_CALL(opal_cec_reboot, OPAL_CEC_REBOOT);
OPAL_CALL(opal_cec_reboot2, OPAL_CEC_REBOOT2);
OPAL_CALL(opal_read_nvram, OPAL_READ_NVRAM);
OPAL_CALL(opal_write_nvram, OPAL_WRITE_NVRAM);
OPAL_CALL(opal_handle_interrupt, OPAL_HANDLE_INTERRUPT);
OPAL_CALL(opal_poll_events, OPAL_POLL_EVENTS);
OPAL_CALL(opal_pci_set_hub_tce_memory, OPAL_PCI_SET_HUB_TCE_MEMORY);
OPAL_CALL(opal_pci_set_phb_tce_memory, OPAL_PCI_SET_PHB_TCE_MEMORY);
OPAL_CALL(opal_pci_config_read_byte, OPAL_PCI_CONFIG_READ_BYTE);
OPAL_CALL(opal_pci_config_read_half_word, OPAL_PCI_CONFIG_READ_HALF_WORD);
OPAL_CALL(opal_pci_config_read_word, OPAL_PCI_CONFIG_READ_WORD);
OPAL_CALL(opal_pci_config_write_byte, OPAL_PCI_CONFIG_WRITE_BYTE);
OPAL_CALL(opal_pci_config_write_half_word, OPAL_PCI_CONFIG_WRITE_HALF_WORD);
OPAL_CALL(opal_pci_config_write_word, OPAL_PCI_CONFIG_WRITE_WORD);
OPAL_CALL(opal_set_xive, OPAL_SET_XIVE);
OPAL_CALL(opal_get_xive, OPAL_GET_XIVE);
OPAL_CALL(opal_register_exception_handler, OPAL_REGISTER_OPAL_EXCEPTION_HANDLER);
OPAL_CALL(opal_pci_eeh_freeze_status, OPAL_PCI_EEH_FREEZE_STATUS);
OPAL_CALL(opal_pci_eeh_freeze_clear, OPAL_PCI_EEH_FREEZE_CLEAR);
OPAL_CALL(opal_pci_eeh_freeze_set, OPAL_PCI_EEH_FREEZE_SET);
OPAL_CALL(opal_pci_err_inject, OPAL_PCI_ERR_INJECT);
OPAL_CALL(opal_pci_shpc, OPAL_PCI_SHPC);
OPAL_CALL(opal_pci_phb_mmio_enable, OPAL_PCI_PHB_MMIO_ENABLE);
OPAL_CALL(opal_pci_set_phb_mem_window, OPAL_PCI_SET_PHB_MEM_WINDOW);
OPAL_CALL(opal_pci_map_pe_mmio_window, OPAL_PCI_MAP_PE_MMIO_WINDOW);
OPAL_CALL(opal_pci_set_phb_table_memory, OPAL_PCI_SET_PHB_TABLE_MEMORY);
OPAL_CALL(opal_pci_set_pe, OPAL_PCI_SET_PE);
OPAL_CALL(opal_pci_set_peltv, OPAL_PCI_SET_PELTV);
OPAL_CALL(opal_pci_set_mve, OPAL_PCI_SET_MVE);
OPAL_CALL(opal_pci_set_mve_enable, OPAL_PCI_SET_MVE_ENABLE);
OPAL_CALL(opal_pci_get_xive_reissue, OPAL_PCI_GET_XIVE_REISSUE);
OPAL_CALL(opal_pci_set_xive_reissue, OPAL_PCI_SET_XIVE_REISSUE);
OPAL_CALL(opal_pci_set_xive_pe, OPAL_PCI_SET_XIVE_PE);
OPAL_CALL(opal_get_xive_source, OPAL_GET_XIVE_SOURCE);
OPAL_CALL(opal_get_msi_32, OPAL_GET_MSI_32);
OPAL_CALL(opal_get_msi_64, OPAL_GET_MSI_64);
OPAL_CALL(opal_start_cpu, OPAL_START_CPU);
OPAL_CALL(opal_query_cpu_status, OPAL_QUERY_CPU_STATUS);
OPAL_CALL(opal_write_oppanel, OPAL_WRITE_OPPANEL);
OPAL_CALL(opal_pci_map_pe_dma_window, OPAL_PCI_MAP_PE_DMA_WINDOW);
OPAL_CALL(opal_pci_map_pe_dma_window_real, OPAL_PCI_MAP_PE_DMA_WINDOW_REAL);
OPAL_CALL(opal_pci_reset, OPAL_PCI_RESET);
OPAL_CALL(opal_pci_get_hub_diag_data, OPAL_PCI_GET_HUB_DIAG_DATA);
OPAL_CALL(opal_pci_get_phb_diag_data, OPAL_PCI_GET_PHB_DIAG_DATA);
OPAL_CALL(opal_pci_fence_phb, OPAL_PCI_FENCE_PHB);
OPAL_CALL(opal_pci_reinit, OPAL_PCI_REINIT);
OPAL_CALL(opal_pci_mask_pe_error, OPAL_PCI_MASK_PE_ERROR);
OPAL_CALL(opal_set_slot_led_status, OPAL_SET_SLOT_LED_STATUS);
OPAL_CALL(opal_get_epow_status, OPAL_GET_EPOW_STATUS);
OPAL_CALL(opal_get_dpo_status, OPAL_GET_DPO_STATUS);
OPAL_CALL(opal_set_system_attention_led, OPAL_SET_SYSTEM_ATTENTION_LED);
OPAL_CALL(opal_pci_next_error, OPAL_PCI_NEXT_ERROR);
OPAL_CALL(opal_pci_poll, OPAL_PCI_POLL);
OPAL_CALL(opal_pci_msi_eoi, OPAL_PCI_MSI_EOI);
OPAL_CALL(opal_pci_get_phb_diag_data2, OPAL_PCI_GET_PHB_DIAG_DATA2);
OPAL_CALL(opal_xscom_read, OPAL_XSCOM_READ);
OPAL_CALL(opal_xscom_write, OPAL_XSCOM_WRITE);
OPAL_CALL(opal_lpc_read, OPAL_LPC_READ);
OPAL_CALL(opal_lpc_write, OPAL_LPC_WRITE);
OPAL_CALL(opal_return_cpu, OPAL_RETURN_CPU);
OPAL_CALL(opal_reinit_cpus, OPAL_REINIT_CPUS);
OPAL_CALL(opal_read_elog, OPAL_ELOG_READ);
OPAL_CALL(opal_send_ack_elog, OPAL_ELOG_ACK);
OPAL_CALL(opal_get_elog_size, OPAL_ELOG_SIZE);
OPAL_CALL(opal_resend_pending_logs, OPAL_ELOG_RESEND);
OPAL_CALL(opal_write_elog, OPAL_ELOG_WRITE);
OPAL_CALL(opal_validate_flash, OPAL_FLASH_VALIDATE);
OPAL_CALL(opal_manage_flash, OPAL_FLASH_MANAGE);
OPAL_CALL(opal_update_flash, OPAL_FLASH_UPDATE);
OPAL_CALL(opal_resync_timebase, OPAL_RESYNC_TIMEBASE);
OPAL_CALL(opal_check_token, OPAL_CHECK_TOKEN);
OPAL_CALL(opal_dump_init, OPAL_DUMP_INIT);
OPAL_CALL(opal_dump_info, OPAL_DUMP_INFO);
OPAL_CALL(opal_dump_info2, OPAL_DUMP_INFO2);
OPAL_CALL(opal_dump_read, OPAL_DUMP_READ);
OPAL_CALL(opal_dump_ack, OPAL_DUMP_ACK);
OPAL_CALL(opal_get_msg, OPAL_GET_MSG);
OPAL_CALL(opal_write_oppanel_async, OPAL_WRITE_OPPANEL_ASYNC);
OPAL_CALL(opal_check_completion, OPAL_CHECK_ASYNC_COMPLETION);
OPAL_CALL(opal_dump_resend_notification, OPAL_DUMP_RESEND);
OPAL_CALL(opal_sync_host_reboot, OPAL_SYNC_HOST_REBOOT);
OPAL_CALL(opal_sensor_read, OPAL_SENSOR_READ);
OPAL_CALL(opal_get_param, OPAL_GET_PARAM);
OPAL_CALL(opal_set_param, OPAL_SET_PARAM);
OPAL_CALL(opal_handle_hmi, OPAL_HANDLE_HMI);
OPAL_CALL(opal_config_cpu_idle_state, OPAL_CONFIG_CPU_IDLE_STATE);
OPAL_CALL(opal_slw_set_reg, OPAL_SLW_SET_REG);
OPAL_CALL(opal_register_dump_region, OPAL_REGISTER_DUMP_REGION);
OPAL_CALL(opal_unregister_dump_region, OPAL_UNREGISTER_DUMP_REGION);
OPAL_CALL(opal_pci_set_phb_cxl_mode, OPAL_PCI_SET_PHB_CAPI_MODE);
OPAL_CALL(opal_tpo_write, OPAL_WRITE_TPO);
OPAL_CALL(opal_tpo_read, OPAL_READ_TPO);
OPAL_CALL(opal_ipmi_send, OPAL_IPMI_SEND);
OPAL_CALL(opal_ipmi_recv, OPAL_IPMI_RECV);
OPAL_CALL(opal_i2c_request, OPAL_I2C_REQUEST);
OPAL_CALL(opal_flash_read, OPAL_FLASH_READ);
OPAL_CALL(opal_flash_write, OPAL_FLASH_WRITE);
OPAL_CALL(opal_flash_erase, OPAL_FLASH_ERASE);
OPAL_CALL(opal_prd_msg, OPAL_PRD_MSG);
OPAL_CALL(opal_leds_get_ind, OPAL_LEDS_GET_INDICATOR);
OPAL_CALL(opal_leds_set_ind, OPAL_LEDS_SET_INDICATOR);
OPAL_CALL(opal_console_flush, OPAL_CONSOLE_FLUSH);
OPAL_CALL(opal_get_device_tree, OPAL_GET_DEVICE_TREE);
OPAL_CALL(opal_pci_get_presence_state, OPAL_PCI_GET_PRESENCE_STATE);
OPAL_CALL(opal_pci_get_power_state, OPAL_PCI_GET_POWER_STATE);
OPAL_CALL(opal_pci_set_power_state, OPAL_PCI_SET_POWER_STATE);
OPAL_CALL(opal_int_get_xirr, OPAL_INT_GET_XIRR);
OPAL_CALL(opal_int_set_cppr, OPAL_INT_SET_CPPR);
OPAL_CALL(opal_int_eoi, OPAL_INT_EOI);
OPAL_CALL(opal_int_set_mfrr, OPAL_INT_SET_MFRR);
OPAL_CALL(opal_pci_tce_kill, OPAL_PCI_TCE_KILL);
OPAL_CALL(opal_nmmu_set_ptcr, OPAL_NMMU_SET_PTCR);
OPAL_CALL(opal_xive_reset, OPAL_XIVE_RESET);
OPAL_CALL(opal_xive_get_irq_info, OPAL_XIVE_GET_IRQ_INFO);
OPAL_CALL(opal_xive_get_irq_config, OPAL_XIVE_GET_IRQ_CONFIG);
OPAL_CALL(opal_xive_set_irq_config, OPAL_XIVE_SET_IRQ_CONFIG);
OPAL_CALL(opal_xive_get_queue_info, OPAL_XIVE_GET_QUEUE_INFO);
OPAL_CALL(opal_xive_set_queue_info, OPAL_XIVE_SET_QUEUE_INFO);
OPAL_CALL(opal_xive_donate_page, OPAL_XIVE_DONATE_PAGE);
OPAL_CALL(opal_xive_alloc_vp_block, OPAL_XIVE_ALLOCATE_VP_BLOCK);
OPAL_CALL(opal_xive_free_vp_block, OPAL_XIVE_FREE_VP_BLOCK);
OPAL_CALL(opal_xive_allocate_irq_raw, OPAL_XIVE_ALLOCATE_IRQ);
OPAL_CALL(opal_xive_free_irq, OPAL_XIVE_FREE_IRQ);
OPAL_CALL(opal_xive_get_vp_info, OPAL_XIVE_GET_VP_INFO);
OPAL_CALL(opal_xive_set_vp_info, OPAL_XIVE_SET_VP_INFO);
OPAL_CALL(opal_xive_sync, OPAL_XIVE_SYNC);
OPAL_CALL(opal_xive_dump, OPAL_XIVE_DUMP);
OPAL_CALL(opal_signal_system_reset, OPAL_SIGNAL_SYSTEM_RESET);
OPAL_CALL(opal_npu_init_context, OPAL_NPU_INIT_CONTEXT);
OPAL_CALL(opal_npu_destroy_context, OPAL_NPU_DESTROY_CONTEXT);
OPAL_CALL(opal_npu_map_lpar, OPAL_NPU_MAP_LPAR);
OPAL_CALL(opal_imc_counters_init, OPAL_IMC_COUNTERS_INIT);
OPAL_CALL(opal_imc_counters_start, OPAL_IMC_COUNTERS_START);
OPAL_CALL(opal_imc_counters_stop, OPAL_IMC_COUNTERS_STOP);
OPAL_CALL(opal_pci_set_p2p, OPAL_PCI_SET_P2P);
OPAL_CALL(opal_get_powercap, OPAL_GET_POWERCAP);
OPAL_CALL(opal_set_powercap, OPAL_SET_POWERCAP);
OPAL_CALL(opal_get_power_shift_ratio, OPAL_GET_POWER_SHIFT_RATIO);
OPAL_CALL(opal_set_power_shift_ratio, OPAL_SET_POWER_SHIFT_RATIO);
OPAL_CALL(opal_sensor_group_clear, OPAL_SENSOR_GROUP_CLEAR);
OPAL_CALL(opal_quiesce, OPAL_QUIESCE);
OPAL_CALL(opal_npu_spa_setup, OPAL_NPU_SPA_SETUP);
OPAL_CALL(opal_npu_spa_clear_cache, OPAL_NPU_SPA_CLEAR_CACHE);
OPAL_CALL(opal_npu_tl_set, OPAL_NPU_TL_SET);
OPAL_CALL(opal_pci_get_pbcq_tunnel_bar, OPAL_PCI_GET_PBCQ_TUNNEL_BAR);
OPAL_CALL(opal_pci_set_pbcq_tunnel_bar, OPAL_PCI_SET_PBCQ_TUNNEL_BAR);
OPAL_CALL(opal_sensor_read_u64, OPAL_SENSOR_READ_U64);
OPAL_CALL(opal_sensor_group_enable, OPAL_SENSOR_GROUP_ENABLE);
OPAL_CALL(opal_nx_coproc_init, OPAL_NX_COPROC_INIT);
|
AirFortressIlikara/LS2K0300-linux-4.19
| 2,013
|
arch/powerpc/platforms/powernv/subcore-asm.S
|
/*
* Copyright 2013, Michael (Ellerman|Neuling), IBM Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/asm-offsets.h>
#include <asm/ppc_asm.h>
#include <asm/reg.h>
#include "subcore.h"
_GLOBAL(split_core_secondary_loop)
/*
* r3 = u8 *state, used throughout the routine
* r4 = temp
* r5 = temp
* ..
* r12 = MSR
*/
mfmsr r12
/* Disable interrupts so SRR0/1 don't get trashed */
li r4,0
ori r4,r4,MSR_EE|MSR_SE|MSR_BE|MSR_RI
andc r4,r12,r4
sync
mtmsrd r4
/* Switch to real mode and leave interrupts off */
li r5, MSR_IR|MSR_DR
andc r5, r4, r5
LOAD_REG_ADDR(r4, real_mode)
mtspr SPRN_SRR0,r4
mtspr SPRN_SRR1,r5
rfid
b . /* prevent speculative execution */
real_mode:
/* Grab values from unsplit SPRs */
mfspr r6, SPRN_LDBAR
mfspr r7, SPRN_PMMAR
mfspr r8, SPRN_PMCR
mfspr r9, SPRN_RPR
mfspr r10, SPRN_SDR1
/* Order reading the SPRs vs telling the primary we are ready to split */
sync
/* Tell thread 0 we are in real mode */
li r4, SYNC_STEP_REAL_MODE
stb r4, 0(r3)
li r5, (HID0_POWER8_4LPARMODE | HID0_POWER8_2LPARMODE)@highest
sldi r5, r5, 48
/* Loop until we see the split happen in HID0 */
1: mfspr r4, SPRN_HID0
and. r4, r4, r5
beq 1b
/*
* We only need to initialise the below regs once for each subcore,
* but it's simpler and harmless to do it on each thread.
*/
/* Make sure various SPRS have sane values */
li r4, 0
mtspr SPRN_LPID, r4
mtspr SPRN_PCR, r4
mtspr SPRN_HDEC, r4
/* Restore SPR values now we are split */
mtspr SPRN_LDBAR, r6
mtspr SPRN_PMMAR, r7
mtspr SPRN_PMCR, r8
mtspr SPRN_RPR, r9
mtspr SPRN_SDR1, r10
LOAD_REG_ADDR(r5, virtual_mode)
/* Get out of real mode */
mtspr SPRN_SRR0,r5
mtspr SPRN_SRR1,r12
rfid
b . /* prevent speculative execution */
virtual_mode:
blr
|
AirFortressIlikara/LS2K0300-linux-4.19
| 7,818
|
arch/powerpc/platforms/52xx/lite5200_sleep.S
|
/* SPDX-License-Identifier: GPL-2.0 */
#include <asm/reg.h>
#include <asm/ppc_asm.h>
#include <asm/processor.h>
#include <asm/cache.h>
#define SDRAM_CTRL 0x104
#define SC_MODE_EN (1<<31)
#define SC_CKE (1<<30)
#define SC_REF_EN (1<<28)
#define SC_SOFT_PRE (1<<1)
#define GPIOW_GPIOE 0xc00
#define GPIOW_DDR 0xc08
#define GPIOW_DVO 0xc0c
#define CDM_CE 0x214
#define CDM_SDRAM (1<<3)
/* helpers... beware: r10 and r4 are overwritten */
#define SAVE_SPRN(reg, addr) \
mfspr r10, SPRN_##reg; \
stw r10, ((addr)*4)(r4);
#define LOAD_SPRN(reg, addr) \
lwz r10, ((addr)*4)(r4); \
mtspr SPRN_##reg, r10; \
sync; \
isync;
.data
registers:
.space 0x5c*4
.text
/* ---------------------------------------------------------------------- */
/* low-power mode with help of M68HLC908QT1 */
.globl lite5200_low_power
lite5200_low_power:
mr r7, r3 /* save SRAM va */
mr r8, r4 /* save MBAR va */
/* setup wakeup address for u-boot at physical location 0x0 */
lis r3, CONFIG_KERNEL_START@h
lis r4, lite5200_wakeup@h
ori r4, r4, lite5200_wakeup@l
sub r4, r4, r3
stw r4, 0(r3)
/*
* save stuff BDI overwrites
* 0xf0 (0xe0->0x100 gets overwritten when BDI connected;
* even when CONFIG_BDI* is disabled and MMU XLAT commented; heisenbug?))
* WARNING: self-refresh doesn't seem to work when BDI2000 is connected,
* possibly because BDI sets SDRAM registers before wakeup code does
*/
lis r4, registers@h
ori r4, r4, registers@l
lwz r10, 0xf0(r3)
stw r10, (0x1d*4)(r4)
/* save registers to r4 [destroys r10] */
SAVE_SPRN(LR, 0x1c)
bl save_regs
/* flush caches [destroys r3, r4] */
bl flush_data_cache
/* copy code to sram */
mr r4, r7
li r3, (sram_code_end - sram_code)/4
mtctr r3
lis r3, sram_code@h
ori r3, r3, sram_code@l
1:
lwz r5, 0(r3)
stw r5, 0(r4)
addi r3, r3, 4
addi r4, r4, 4
bdnz 1b
/* get tb_ticks_per_usec */
lis r3, tb_ticks_per_usec@h
lwz r11, tb_ticks_per_usec@l(r3)
/* disable I and D caches */
mfspr r3, SPRN_HID0
ori r3, r3, HID0_ICE | HID0_DCE
xori r3, r3, HID0_ICE | HID0_DCE
sync; isync;
mtspr SPRN_HID0, r3
sync; isync;
/* jump to sram */
mtlr r7
blrl
/* doesn't return */
sram_code:
/* self refresh */
lwz r4, SDRAM_CTRL(r8)
/* send NOP (precharge) */
oris r4, r4, SC_MODE_EN@h /* mode_en */
stw r4, SDRAM_CTRL(r8)
sync
ori r4, r4, SC_SOFT_PRE /* soft_pre */
stw r4, SDRAM_CTRL(r8)
sync
xori r4, r4, SC_SOFT_PRE
xoris r4, r4, SC_MODE_EN@h /* !mode_en */
stw r4, SDRAM_CTRL(r8)
sync
/* delay (for NOP to finish) */
li r12, 1
bl udelay
/*
* mode_en must not be set when enabling self-refresh
* send AR with CKE low (self-refresh)
*/
oris r4, r4, (SC_REF_EN | SC_CKE)@h
xoris r4, r4, (SC_CKE)@h /* ref_en !cke */
stw r4, SDRAM_CTRL(r8)
sync
/* delay (after !CKE there should be two cycles) */
li r12, 1
bl udelay
/* disable clock */
lwz r4, CDM_CE(r8)
ori r4, r4, CDM_SDRAM
xori r4, r4, CDM_SDRAM
stw r4, CDM_CE(r8)
sync
/* delay a bit */
li r12, 1
bl udelay
/* turn off with QT chip */
li r4, 0x02
stb r4, GPIOW_GPIOE(r8) /* enable gpio_wkup1 */
sync
stb r4, GPIOW_DVO(r8) /* "output" high */
sync
stb r4, GPIOW_DDR(r8) /* output */
sync
stb r4, GPIOW_DVO(r8) /* output high */
sync
/* 10uS delay */
li r12, 10
bl udelay
/* turn off */
li r4, 0
stb r4, GPIOW_DVO(r8) /* output low */
sync
/* wait until we're offline */
1:
b 1b
/* local udelay in sram is needed */
udelay: /* r11 - tb_ticks_per_usec, r12 - usecs, overwrites r13 */
mullw r12, r12, r11
mftb r13 /* start */
addi r12, r13, r12 /* end */
1:
mftb r13 /* current */
cmp cr0, r13, r12
blt 1b
blr
sram_code_end:
/* uboot jumps here on resume */
lite5200_wakeup:
bl restore_regs
/* HIDs, MSR */
LOAD_SPRN(HID1, 0x19)
LOAD_SPRN(HID2, 0x1a)
/* address translation is tricky (see turn_on_mmu) */
mfmsr r10
ori r10, r10, MSR_DR | MSR_IR
mtspr SPRN_SRR1, r10
lis r10, mmu_on@h
ori r10, r10, mmu_on@l
mtspr SPRN_SRR0, r10
sync
rfi
mmu_on:
/* kernel offset (r4 is still set from restore_registers) */
addis r4, r4, CONFIG_KERNEL_START@h
/* restore MSR */
lwz r10, (4*0x1b)(r4)
mtmsr r10
sync; isync;
/* invalidate caches */
mfspr r10, SPRN_HID0
ori r5, r10, HID0_ICFI | HID0_DCI
mtspr SPRN_HID0, r5 /* invalidate caches */
sync; isync;
mtspr SPRN_HID0, r10
sync; isync;
/* enable caches */
lwz r10, (4*0x18)(r4)
mtspr SPRN_HID0, r10 /* restore (enable caches, DPM) */
/* ^ this has to be after address translation set in MSR */
sync
isync
/* restore 0xf0 (BDI2000) */
lis r3, CONFIG_KERNEL_START@h
lwz r10, (0x1d*4)(r4)
stw r10, 0xf0(r3)
LOAD_SPRN(LR, 0x1c)
blr
/* ---------------------------------------------------------------------- */
/* boring code: helpers */
/* save registers */
#define SAVE_BAT(n, addr) \
SAVE_SPRN(DBAT##n##L, addr); \
SAVE_SPRN(DBAT##n##U, addr+1); \
SAVE_SPRN(IBAT##n##L, addr+2); \
SAVE_SPRN(IBAT##n##U, addr+3);
#define SAVE_SR(n, addr) \
mfsr r10, n; \
stw r10, ((addr)*4)(r4);
#define SAVE_4SR(n, addr) \
SAVE_SR(n, addr); \
SAVE_SR(n+1, addr+1); \
SAVE_SR(n+2, addr+2); \
SAVE_SR(n+3, addr+3);
save_regs:
stw r0, 0(r4)
stw r1, 0x4(r4)
stw r2, 0x8(r4)
stmw r11, 0xc(r4) /* 0xc -> 0x5f, (0x18*4-1) */
SAVE_SPRN(HID0, 0x18)
SAVE_SPRN(HID1, 0x19)
SAVE_SPRN(HID2, 0x1a)
mfmsr r10
stw r10, (4*0x1b)(r4)
/*SAVE_SPRN(LR, 0x1c) have to save it before the call */
/* 0x1d reserved by 0xf0 */
SAVE_SPRN(RPA, 0x1e)
SAVE_SPRN(SDR1, 0x1f)
/* save MMU regs */
SAVE_BAT(0, 0x20)
SAVE_BAT(1, 0x24)
SAVE_BAT(2, 0x28)
SAVE_BAT(3, 0x2c)
SAVE_BAT(4, 0x30)
SAVE_BAT(5, 0x34)
SAVE_BAT(6, 0x38)
SAVE_BAT(7, 0x3c)
SAVE_4SR(0, 0x40)
SAVE_4SR(4, 0x44)
SAVE_4SR(8, 0x48)
SAVE_4SR(12, 0x4c)
SAVE_SPRN(SPRG0, 0x50)
SAVE_SPRN(SPRG1, 0x51)
SAVE_SPRN(SPRG2, 0x52)
SAVE_SPRN(SPRG3, 0x53)
SAVE_SPRN(SPRG4, 0x54)
SAVE_SPRN(SPRG5, 0x55)
SAVE_SPRN(SPRG6, 0x56)
SAVE_SPRN(SPRG7, 0x57)
SAVE_SPRN(IABR, 0x58)
SAVE_SPRN(DABR, 0x59)
SAVE_SPRN(TBRL, 0x5a)
SAVE_SPRN(TBRU, 0x5b)
blr
/* restore registers */
#define LOAD_BAT(n, addr) \
LOAD_SPRN(DBAT##n##L, addr); \
LOAD_SPRN(DBAT##n##U, addr+1); \
LOAD_SPRN(IBAT##n##L, addr+2); \
LOAD_SPRN(IBAT##n##U, addr+3);
#define LOAD_SR(n, addr) \
lwz r10, ((addr)*4)(r4); \
mtsr n, r10;
#define LOAD_4SR(n, addr) \
LOAD_SR(n, addr); \
LOAD_SR(n+1, addr+1); \
LOAD_SR(n+2, addr+2); \
LOAD_SR(n+3, addr+3);
restore_regs:
lis r4, registers@h
ori r4, r4, registers@l
/* MMU is not up yet */
subis r4, r4, CONFIG_KERNEL_START@h
lwz r0, 0(r4)
lwz r1, 0x4(r4)
lwz r2, 0x8(r4)
lmw r11, 0xc(r4)
/*
* these are a bit tricky
*
* 0x18 - HID0
* 0x19 - HID1
* 0x1a - HID2
* 0x1b - MSR
* 0x1c - LR
* 0x1d - reserved by 0xf0 (BDI2000)
*/
LOAD_SPRN(RPA, 0x1e);
LOAD_SPRN(SDR1, 0x1f);
/* restore MMU regs */
LOAD_BAT(0, 0x20)
LOAD_BAT(1, 0x24)
LOAD_BAT(2, 0x28)
LOAD_BAT(3, 0x2c)
LOAD_BAT(4, 0x30)
LOAD_BAT(5, 0x34)
LOAD_BAT(6, 0x38)
LOAD_BAT(7, 0x3c)
LOAD_4SR(0, 0x40)
LOAD_4SR(4, 0x44)
LOAD_4SR(8, 0x48)
LOAD_4SR(12, 0x4c)
/* rest of regs */
LOAD_SPRN(SPRG0, 0x50);
LOAD_SPRN(SPRG1, 0x51);
LOAD_SPRN(SPRG2, 0x52);
LOAD_SPRN(SPRG3, 0x53);
LOAD_SPRN(SPRG4, 0x54);
LOAD_SPRN(SPRG5, 0x55);
LOAD_SPRN(SPRG6, 0x56);
LOAD_SPRN(SPRG7, 0x57);
LOAD_SPRN(IABR, 0x58);
LOAD_SPRN(DABR, 0x59);
LOAD_SPRN(TBWL, 0x5a); /* these two have separate R/W regs */
LOAD_SPRN(TBWU, 0x5b);
blr
/* cache flushing code. copied from arch/ppc/boot/util.S */
#define NUM_CACHE_LINES (128*8)
/*
* Flush data cache
* Do this by just reading lots of stuff into the cache.
*/
flush_data_cache:
lis r3,CONFIG_KERNEL_START@h
ori r3,r3,CONFIG_KERNEL_START@l
li r4,NUM_CACHE_LINES
mtctr r4
1:
lwz r4,0(r3)
addi r3,r3,L1_CACHE_BYTES /* Next line, please */
bdnz 1b
blr
|
AirFortressIlikara/LS2K0300-linux-4.19
| 2,634
|
arch/powerpc/platforms/52xx/mpc52xx_sleep.S
|
/* SPDX-License-Identifier: GPL-2.0 */
#include <asm/reg.h>
#include <asm/ppc_asm.h>
#include <asm/processor.h>
.text
_GLOBAL(mpc52xx_deep_sleep)
mpc52xx_deep_sleep: /* args r3-r6: SRAM, SDRAM regs, CDM regs, INTR regs */
/* enable interrupts */
mfmsr r7
ori r7, r7, 0x8000 /* EE */
mtmsr r7
sync; isync;
li r10, 0 /* flag that irq handler sets */
/* enable tmr7 (or any other) interrupt */
lwz r8, 0x14(r6) /* intr->main_mask */
ori r8, r8, 0x1
xori r8, r8, 0x1
stw r8, 0x14(r6)
sync
/* emulate tmr7 interrupt */
li r8, 0x1
stw r8, 0x40(r6) /* intr->main_emulate */
sync
/* wait for it to happen */
1:
cmpi cr0, r10, 1
bne cr0, 1b
/* lock icache */
mfspr r10, SPRN_HID0
ori r10, r10, 0x2000
sync; isync;
mtspr SPRN_HID0, r10
sync; isync;
mflr r9 /* save LR */
/* jump to sram */
mtlr r3
blrl
mtlr r9 /* restore LR */
/* unlock icache */
mfspr r10, SPRN_HID0
ori r10, r10, 0x2000
xori r10, r10, 0x2000
sync; isync;
mtspr SPRN_HID0, r10
sync; isync;
/* return to C code */
blr
_GLOBAL(mpc52xx_ds_sram)
mpc52xx_ds_sram:
/* put SDRAM into self-refresh */
lwz r8, 0x4(r4) /* sdram->ctrl */
oris r8, r8, 0x8000 /* mode_en */
stw r8, 0x4(r4)
sync
ori r8, r8, 0x0002 /* soft_pre */
stw r8, 0x4(r4)
sync
xori r8, r8, 0x0002
xoris r8, r8, 0x8000 /* !mode_en */
stw r8, 0x4(r4)
sync
oris r8, r8, 0x5000
xoris r8, r8, 0x4000 /* ref_en !cke */
stw r8, 0x4(r4)
sync
/* disable SDRAM clock */
lwz r8, 0x14(r5) /* cdm->clkenable */
ori r8, r8, 0x0008
xori r8, r8, 0x0008
stw r8, 0x14(r5)
sync
/* put mpc5200 to sleep */
mfmsr r10
oris r10, r10, 0x0004 /* POW = 1 */
sync; isync;
mtmsr r10
sync; isync;
/* enable clock */
lwz r8, 0x14(r5)
ori r8, r8, 0x0008
stw r8, 0x14(r5)
sync
/* get ram out of self-refresh */
lwz r8, 0x4(r4)
oris r8, r8, 0x5000 /* cke ref_en */
stw r8, 0x4(r4)
sync
blr
_GLOBAL(mpc52xx_ds_sram_size)
mpc52xx_ds_sram_size:
.long $-mpc52xx_ds_sram
/* ### interrupt handler for wakeup from deep-sleep ### */
_GLOBAL(mpc52xx_ds_cached)
mpc52xx_ds_cached:
mtspr SPRN_SPRG0, r7
mtspr SPRN_SPRG1, r8
/* disable emulated interrupt */
mfspr r7, 311 /* MBAR */
addi r7, r7, 0x540 /* intr->main_emul */
li r8, 0
stw r8, 0(r7)
sync
dcbf 0, r7
/* acknowledge wakeup, so CCS releases power pown */
mfspr r7, 311 /* MBAR */
addi r7, r7, 0x524 /* intr->enc_status */
lwz r8, 0(r7)
ori r8, r8, 0x0400
stw r8, 0(r7)
sync
dcbf 0, r7
/* flag - we handled the interrupt */
li r10, 1
mfspr r8, SPRN_SPRG1
mfspr r7, SPRN_SPRG0
rfi
_GLOBAL(mpc52xx_ds_cached_size)
mpc52xx_ds_cached_size:
.long $-mpc52xx_ds_cached
|
AirFortressIlikara/LS2K0300-linux-4.19
| 15,193
|
arch/powerpc/platforms/ps3/hvcall.S
|
/*
* PS3 hvcall interface.
*
* Copyright (C) 2006 Sony Computer Entertainment Inc.
* Copyright 2006 Sony Corp.
* Copyright 2003, 2004 (c) MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#define lv1call .long 0x44000022; extsw r3, r3
#define LV1_N_IN_0_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_0_IN_0_OUT LV1_N_IN_0_OUT
#define LV1_1_IN_0_OUT LV1_N_IN_0_OUT
#define LV1_2_IN_0_OUT LV1_N_IN_0_OUT
#define LV1_3_IN_0_OUT LV1_N_IN_0_OUT
#define LV1_4_IN_0_OUT LV1_N_IN_0_OUT
#define LV1_5_IN_0_OUT LV1_N_IN_0_OUT
#define LV1_6_IN_0_OUT LV1_N_IN_0_OUT
#define LV1_7_IN_0_OUT LV1_N_IN_0_OUT
#define LV1_0_IN_1_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
stdu r3, -8(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 8; \
ld r11, -8(r1); \
std r4, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_0_IN_2_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r3, -8(r1); \
stdu r4, -16(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 16; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_0_IN_3_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r3, -8(r1); \
std r4, -16(r1); \
stdu r5, -24(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 24; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_0_IN_7_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r3, -8(r1); \
std r4, -16(r1); \
std r5, -24(r1); \
std r6, -32(r1); \
std r7, -40(r1); \
std r8, -48(r1); \
stdu r9, -56(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 56; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
ld r11, -32(r1); \
std r7, 0(r11); \
ld r11, -40(r1); \
std r8, 0(r11); \
ld r11, -48(r1); \
std r9, 0(r11); \
ld r11, -56(r1); \
std r10, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_1_IN_1_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
stdu r4, -8(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 8; \
ld r11, -8(r1); \
std r4, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_1_IN_2_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r4, -8(r1); \
stdu r5, -16(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 16; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_1_IN_3_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r4, -8(r1); \
std r5, -16(r1); \
stdu r6, -24(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 24; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_1_IN_4_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r4, -8(r1); \
std r5, -16(r1); \
std r6, -24(r1); \
stdu r7, -32(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 32; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
ld r11, -32(r1); \
std r7, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_1_IN_5_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r4, -8(r1); \
std r5, -16(r1); \
std r6, -24(r1); \
std r7, -32(r1); \
stdu r8, -40(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 40; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
ld r11, -32(r1); \
std r7, 0(r11); \
ld r11, -40(r1); \
std r8, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_1_IN_6_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r4, -8(r1); \
std r5, -16(r1); \
std r6, -24(r1); \
std r7, -32(r1); \
std r8, -40(r1); \
stdu r9, -48(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 48; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
ld r11, -32(r1); \
std r7, 0(r11); \
ld r11, -40(r1); \
std r8, 0(r11); \
ld r11, -48(r1); \
std r9, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_1_IN_7_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r4, -8(r1); \
std r5, -16(r1); \
std r6, -24(r1); \
std r7, -32(r1); \
std r8, -40(r1); \
std r9, -48(r1); \
stdu r10, -56(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 56; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
ld r11, -32(r1); \
std r7, 0(r11); \
ld r11, -40(r1); \
std r8, 0(r11); \
ld r11, -48(r1); \
std r9, 0(r11); \
ld r11, -56(r1); \
std r10, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_2_IN_1_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
stdu r5, -8(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 8; \
ld r11, -8(r1); \
std r4, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_2_IN_2_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r5, -8(r1); \
stdu r6, -16(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 16; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_2_IN_3_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r5, -8(r1); \
std r6, -16(r1); \
stdu r7, -24(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 24; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_2_IN_4_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r5, -8(r1); \
std r6, -16(r1); \
std r7, -24(r1); \
stdu r8, -32(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 32; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
ld r11, -32(r1); \
std r7, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_2_IN_5_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r5, -8(r1); \
std r6, -16(r1); \
std r7, -24(r1); \
std r8, -32(r1); \
stdu r9, -40(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 40; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
ld r11, -32(r1); \
std r7, 0(r11); \
ld r11, -40(r1); \
std r8, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_3_IN_1_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
stdu r6, -8(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 8; \
ld r11, -8(r1); \
std r4, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_3_IN_2_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r6, -8(r1); \
stdu r7, -16(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 16; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_3_IN_3_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r6, -8(r1); \
std r7, -16(r1); \
stdu r8, -24(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 24; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_4_IN_1_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
stdu r7, -8(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 8; \
ld r11, -8(r1); \
std r4, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_4_IN_2_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r7, -8(r1); \
stdu r8, -16(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 16; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_4_IN_3_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r7, -8(r1); \
std r8, -16(r1); \
stdu r9, -24(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 24; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_5_IN_1_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
stdu r8, -8(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 8; \
ld r11, -8(r1); \
std r4, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_5_IN_2_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r8, -8(r1); \
stdu r9, -16(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 16; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_5_IN_3_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r8, -8(r1); \
std r9, -16(r1); \
stdu r10, -24(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 24; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, -24(r1); \
std r6, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_6_IN_1_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
stdu r9, -8(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 8; \
ld r11, -8(r1); \
std r4, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_6_IN_2_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r9, -8(r1); \
stdu r10, -16(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 16; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_6_IN_3_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r9, -8(r1); \
stdu r10, -16(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 16; \
ld r11, -8(r1); \
std r4, 0(r11); \
ld r11, -16(r1); \
std r5, 0(r11); \
ld r11, 48+8*8(r1); \
std r6, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_7_IN_1_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
stdu r10, -8(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
addi r1, r1, 8; \
ld r11, -8(r1); \
std r4, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_7_IN_6_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
std r10, 48+8*7(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
ld r11, 48+8*7(r1); \
std r4, 0(r11); \
ld r11, 48+8*8(r1); \
std r5, 0(r11); \
ld r11, 48+8*9(r1); \
std r6, 0(r11); \
ld r11, 48+8*10(r1); \
std r7, 0(r11); \
ld r11, 48+8*11(r1); \
std r8, 0(r11); \
ld r11, 48+8*12(r1); \
std r9, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
#define LV1_8_IN_1_OUT(API_NAME, API_NUMBER) \
_GLOBAL(_##API_NAME) \
\
mflr r0; \
std r0, 16(r1); \
\
li r11, API_NUMBER; \
lv1call; \
\
ld r11, 48+8*8(r1); \
std r4, 0(r11); \
\
ld r0, 16(r1); \
mtlr r0; \
blr
.text
/* the lv1 underscored call definitions expand here */
#define LV1_CALL(name, in, out, num) LV1_##in##_IN_##out##_OUT(lv1_##name, num)
#include <asm/lv1call.h>
|
AirFortressIlikara/LS2K0300-linux-4.19
| 6,608
|
arch/powerpc/platforms/pseries/hvCall.S
|
/*
* This file contains the generic code to perform a call to the
* pSeries LPAR hypervisor.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/jump_label.h>
#include <asm/hvcall.h>
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/ptrace.h>
#include <asm/feature-fixups.h>
.section ".text"
#ifdef CONFIG_TRACEPOINTS
#ifndef CONFIG_JUMP_LABEL
.section ".toc","aw"
.globl hcall_tracepoint_refcount
hcall_tracepoint_refcount:
.8byte 0
.section ".text"
#endif
/*
* precall must preserve all registers. use unused STK_PARAM()
* areas to save snapshots and opcode.
*/
#define HCALL_INST_PRECALL(FIRST_REG) \
mflr r0; \
std r3,STK_PARAM(R3)(r1); \
std r4,STK_PARAM(R4)(r1); \
std r5,STK_PARAM(R5)(r1); \
std r6,STK_PARAM(R6)(r1); \
std r7,STK_PARAM(R7)(r1); \
std r8,STK_PARAM(R8)(r1); \
std r9,STK_PARAM(R9)(r1); \
std r10,STK_PARAM(R10)(r1); \
std r0,16(r1); \
addi r4,r1,STK_PARAM(FIRST_REG); \
stdu r1,-STACK_FRAME_OVERHEAD(r1); \
bl __trace_hcall_entry; \
ld r3,STACK_FRAME_OVERHEAD+STK_PARAM(R3)(r1); \
ld r4,STACK_FRAME_OVERHEAD+STK_PARAM(R4)(r1); \
ld r5,STACK_FRAME_OVERHEAD+STK_PARAM(R5)(r1); \
ld r6,STACK_FRAME_OVERHEAD+STK_PARAM(R6)(r1); \
ld r7,STACK_FRAME_OVERHEAD+STK_PARAM(R7)(r1); \
ld r8,STACK_FRAME_OVERHEAD+STK_PARAM(R8)(r1); \
ld r9,STACK_FRAME_OVERHEAD+STK_PARAM(R9)(r1); \
ld r10,STACK_FRAME_OVERHEAD+STK_PARAM(R10)(r1)
/*
* postcall is performed immediately before function return which
* allows liberal use of volatile registers.
*/
#define __HCALL_INST_POSTCALL \
ld r0,STACK_FRAME_OVERHEAD+STK_PARAM(R3)(r1); \
std r3,STACK_FRAME_OVERHEAD+STK_PARAM(R3)(r1); \
mr r4,r3; \
mr r3,r0; \
bl __trace_hcall_exit; \
ld r0,STACK_FRAME_OVERHEAD+16(r1); \
addi r1,r1,STACK_FRAME_OVERHEAD; \
ld r3,STK_PARAM(R3)(r1); \
mtlr r0
#define HCALL_INST_POSTCALL_NORETS \
li r5,0; \
__HCALL_INST_POSTCALL
#define HCALL_INST_POSTCALL(BUFREG) \
mr r5,BUFREG; \
__HCALL_INST_POSTCALL
#ifdef CONFIG_JUMP_LABEL
#define HCALL_BRANCH(LABEL) \
ARCH_STATIC_BRANCH(LABEL, hcall_tracepoint_key)
#else
/*
* We branch around this in early init (eg when populating the MMU
* hashtable) by using an unconditional cpu feature.
*/
#define HCALL_BRANCH(LABEL) \
BEGIN_FTR_SECTION; \
b 1f; \
END_FTR_SECTION(0, 1); \
ld r12,hcall_tracepoint_refcount@toc(r2); \
std r12,32(r1); \
cmpdi r12,0; \
bne- LABEL; \
1:
#endif
#else
#define HCALL_INST_PRECALL(FIRST_ARG)
#define HCALL_INST_POSTCALL_NORETS
#define HCALL_INST_POSTCALL(BUFREG)
#define HCALL_BRANCH(LABEL)
#endif
_GLOBAL_TOC(plpar_hcall_norets)
HMT_MEDIUM
mfcr r0
stw r0,8(r1)
HCALL_BRANCH(plpar_hcall_norets_trace)
HVSC /* invoke the hypervisor */
lwz r0,8(r1)
mtcrf 0xff,r0
blr /* return r3 = status */
#ifdef CONFIG_TRACEPOINTS
plpar_hcall_norets_trace:
HCALL_INST_PRECALL(R4)
HVSC
HCALL_INST_POSTCALL_NORETS
lwz r0,8(r1)
mtcrf 0xff,r0
blr
#endif
_GLOBAL_TOC(plpar_hcall)
HMT_MEDIUM
mfcr r0
stw r0,8(r1)
HCALL_BRANCH(plpar_hcall_trace)
std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
mr r4,r5
mr r5,r6
mr r6,r7
mr r7,r8
mr r8,r9
mr r9,r10
HVSC /* invoke the hypervisor */
ld r12,STK_PARAM(R4)(r1)
std r4, 0(r12)
std r5, 8(r12)
std r6, 16(r12)
std r7, 24(r12)
lwz r0,8(r1)
mtcrf 0xff,r0
blr /* return r3 = status */
#ifdef CONFIG_TRACEPOINTS
plpar_hcall_trace:
HCALL_INST_PRECALL(R5)
std r4,STK_PARAM(R4)(r1)
mr r0,r4
mr r4,r5
mr r5,r6
mr r6,r7
mr r7,r8
mr r8,r9
mr r9,r10
HVSC
ld r12,STK_PARAM(R4)(r1)
std r4,0(r12)
std r5,8(r12)
std r6,16(r12)
std r7,24(r12)
HCALL_INST_POSTCALL(r12)
lwz r0,8(r1)
mtcrf 0xff,r0
blr
#endif
/*
* plpar_hcall_raw can be called in real mode. kexec/kdump need some
* hypervisor calls to be executed in real mode. So plpar_hcall_raw
* does not access the per cpu hypervisor call statistics variables,
* since these variables may not be present in the RMO region.
*/
_GLOBAL(plpar_hcall_raw)
HMT_MEDIUM
mfcr r0
stw r0,8(r1)
std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
mr r4,r5
mr r5,r6
mr r6,r7
mr r7,r8
mr r8,r9
mr r9,r10
HVSC /* invoke the hypervisor */
ld r12,STK_PARAM(R4)(r1)
std r4, 0(r12)
std r5, 8(r12)
std r6, 16(r12)
std r7, 24(r12)
lwz r0,8(r1)
mtcrf 0xff,r0
blr /* return r3 = status */
_GLOBAL_TOC(plpar_hcall9)
HMT_MEDIUM
mfcr r0
stw r0,8(r1)
HCALL_BRANCH(plpar_hcall9_trace)
std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
mr r4,r5
mr r5,r6
mr r6,r7
mr r7,r8
mr r8,r9
mr r9,r10
ld r10,STK_PARAM(R11)(r1) /* put arg7 in R10 */
ld r11,STK_PARAM(R12)(r1) /* put arg8 in R11 */
ld r12,STK_PARAM(R13)(r1) /* put arg9 in R12 */
HVSC /* invoke the hypervisor */
mr r0,r12
ld r12,STK_PARAM(R4)(r1)
std r4, 0(r12)
std r5, 8(r12)
std r6, 16(r12)
std r7, 24(r12)
std r8, 32(r12)
std r9, 40(r12)
std r10,48(r12)
std r11,56(r12)
std r0, 64(r12)
lwz r0,8(r1)
mtcrf 0xff,r0
blr /* return r3 = status */
#ifdef CONFIG_TRACEPOINTS
plpar_hcall9_trace:
HCALL_INST_PRECALL(R5)
std r4,STK_PARAM(R4)(r1)
mr r0,r4
mr r4,r5
mr r5,r6
mr r6,r7
mr r7,r8
mr r8,r9
mr r9,r10
ld r10,STACK_FRAME_OVERHEAD+STK_PARAM(R11)(r1)
ld r11,STACK_FRAME_OVERHEAD+STK_PARAM(R12)(r1)
ld r12,STACK_FRAME_OVERHEAD+STK_PARAM(R13)(r1)
HVSC
mr r0,r12
ld r12,STACK_FRAME_OVERHEAD+STK_PARAM(R4)(r1)
std r4,0(r12)
std r5,8(r12)
std r6,16(r12)
std r7,24(r12)
std r8,32(r12)
std r9,40(r12)
std r10,48(r12)
std r11,56(r12)
std r0,64(r12)
HCALL_INST_POSTCALL(r12)
lwz r0,8(r1)
mtcrf 0xff,r0
blr
#endif
/* See plpar_hcall_raw to see why this is needed */
_GLOBAL(plpar_hcall9_raw)
HMT_MEDIUM
mfcr r0
stw r0,8(r1)
std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
mr r4,r5
mr r5,r6
mr r6,r7
mr r7,r8
mr r8,r9
mr r9,r10
ld r10,STK_PARAM(R11)(r1) /* put arg7 in R10 */
ld r11,STK_PARAM(R12)(r1) /* put arg8 in R11 */
ld r12,STK_PARAM(R13)(r1) /* put arg9 in R12 */
HVSC /* invoke the hypervisor */
mr r0,r12
ld r12,STK_PARAM(R4)(r1)
std r4, 0(r12)
std r5, 8(r12)
std r6, 16(r12)
std r7, 24(r12)
std r8, 32(r12)
std r9, 40(r12)
std r10,48(r12)
std r11,56(r12)
std r0, 64(r12)
lwz r0,8(r1)
mtcrf 0xff,r0
blr /* return r3 = status */
|
AirFortressIlikara/LS2K0300-linux-4.19
| 7,470
|
arch/powerpc/platforms/powermac/cache.S
|
/*
* This file contains low-level cache management functions
* used for sleep and CPU speed changes on Apple machines.
* (In fact the only thing that is Apple-specific is that we assume
* that we can read from ROM at physical address 0xfff00000.)
*
* Copyright (C) 2004 Paul Mackerras (paulus@samba.org) and
* Benjamin Herrenschmidt (benh@kernel.crashing.org)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
*/
#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/cputable.h>
#include <asm/feature-fixups.h>
/*
* Flush and disable all data caches (dL1, L2, L3). This is used
* when going to sleep, when doing a PMU based cpufreq transition,
* or when "offlining" a CPU on SMP machines. This code is over
* paranoid, but I've had enough issues with various CPU revs and
* bugs that I decided it was worth being over cautious
*/
_GLOBAL(flush_disable_caches)
#ifndef CONFIG_6xx
blr
#else
BEGIN_FTR_SECTION
b flush_disable_745x
END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
BEGIN_FTR_SECTION
b flush_disable_75x
END_FTR_SECTION_IFSET(CPU_FTR_L2CR)
b __flush_disable_L1
/* This is the code for G3 and 74[01]0 */
flush_disable_75x:
mflr r10
/* Turn off EE and DR in MSR */
mfmsr r11
rlwinm r0,r11,0,~MSR_EE
rlwinm r0,r0,0,~MSR_DR
sync
mtmsr r0
isync
/* Stop DST streams */
BEGIN_FTR_SECTION
DSSALL
sync
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
/* Stop DPM */
mfspr r8,SPRN_HID0 /* Save SPRN_HID0 in r8 */
rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
sync
mtspr SPRN_HID0,r4 /* Disable DPM */
sync
/* Disp-flush L1. We have a weird problem here that I never
* totally figured out. On 750FX, using the ROM for the flush
* results in a non-working flush. We use that workaround for
* now until I finally understand what's going on. --BenH
*/
/* ROM base by default */
lis r4,0xfff0
mfpvr r3
srwi r3,r3,16
cmplwi cr0,r3,0x7000
bne+ 1f
/* RAM base on 750FX */
li r4,0
1: li r4,0x4000
mtctr r4
1: lwz r0,0(r4)
addi r4,r4,32
bdnz 1b
sync
isync
/* Disable / invalidate / enable L1 data */
mfspr r3,SPRN_HID0
rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE)
mtspr SPRN_HID0,r3
sync
isync
ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI)
sync
isync
mtspr SPRN_HID0,r3
xori r3,r3,(HID0_DCI|HID0_ICFI)
mtspr SPRN_HID0,r3
sync
/* Get the current enable bit of the L2CR into r4 */
mfspr r5,SPRN_L2CR
/* Set to data-only (pre-745x bit) */
oris r3,r5,L2CR_L2DO@h
b 2f
/* When disabling L2, code must be in L1 */
.balign 32
1: mtspr SPRN_L2CR,r3
3: sync
isync
b 1f
2: b 3f
3: sync
isync
b 1b
1: /* disp-flush L2. The interesting thing here is that the L2 can be
* up to 2Mb ... so using the ROM, we'll end up wrapping back to memory
* but that is probbaly fine. We disp-flush over 4Mb to be safe
*/
lis r4,2
mtctr r4
lis r4,0xfff0
1: lwz r0,0(r4)
addi r4,r4,32
bdnz 1b
sync
isync
lis r4,2
mtctr r4
lis r4,0xfff0
1: dcbf 0,r4
addi r4,r4,32
bdnz 1b
sync
isync
/* now disable L2 */
rlwinm r5,r5,0,~L2CR_L2E
b 2f
/* When disabling L2, code must be in L1 */
.balign 32
1: mtspr SPRN_L2CR,r5
3: sync
isync
b 1f
2: b 3f
3: sync
isync
b 1b
1: sync
isync
/* Invalidate L2. This is pre-745x, we clear the L2I bit ourselves */
oris r4,r5,L2CR_L2I@h
mtspr SPRN_L2CR,r4
sync
isync
/* Wait for the invalidation to complete */
1: mfspr r3,SPRN_L2CR
rlwinm. r0,r3,0,31,31
bne 1b
/* Clear L2I */
xoris r4,r4,L2CR_L2I@h
sync
mtspr SPRN_L2CR,r4
sync
/* now disable the L1 data cache */
mfspr r0,SPRN_HID0
rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
mtspr SPRN_HID0,r0
sync
isync
/* Restore HID0[DPM] to whatever it was before */
sync
mfspr r0,SPRN_HID0
rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */
mtspr SPRN_HID0,r0
sync
/* restore DR and EE */
sync
mtmsr r11
isync
mtlr r10
blr
/* This code is for 745x processors */
flush_disable_745x:
/* Turn off EE and DR in MSR */
mfmsr r11
rlwinm r0,r11,0,~MSR_EE
rlwinm r0,r0,0,~MSR_DR
sync
mtmsr r0
isync
/* Stop prefetch streams */
DSSALL
sync
/* Disable L2 prefetching */
mfspr r0,SPRN_MSSCR0
rlwinm r0,r0,0,0,29
mtspr SPRN_MSSCR0,r0
sync
isync
lis r4,0
dcbf 0,r4
dcbf 0,r4
dcbf 0,r4
dcbf 0,r4
dcbf 0,r4
dcbf 0,r4
dcbf 0,r4
dcbf 0,r4
/* Due to a bug with the HW flush on some CPU revs, we occasionally
* experience data corruption. I'm adding a displacement flush along
* with a dcbf loop over a few Mb to "help". The problem isn't totally
* fixed by this in theory, but at least, in practice, I couldn't reproduce
* it even with a big hammer...
*/
lis r4,0x0002
mtctr r4
li r4,0
1:
lwz r0,0(r4)
addi r4,r4,32 /* Go to start of next cache line */
bdnz 1b
isync
/* Now, flush the first 4MB of memory */
lis r4,0x0002
mtctr r4
li r4,0
sync
1:
dcbf 0,r4
addi r4,r4,32 /* Go to start of next cache line */
bdnz 1b
/* Flush and disable the L1 data cache */
mfspr r6,SPRN_LDSTCR
lis r3,0xfff0 /* read from ROM for displacement flush */
li r4,0xfe /* start with only way 0 unlocked */
li r5,128 /* 128 lines in each way */
1: mtctr r5
rlwimi r6,r4,0,24,31
mtspr SPRN_LDSTCR,r6
sync
isync
2: lwz r0,0(r3) /* touch each cache line */
addi r3,r3,32
bdnz 2b
rlwinm r4,r4,1,24,30 /* move on to the next way */
ori r4,r4,1
cmpwi r4,0xff /* all done? */
bne 1b
/* now unlock the L1 data cache */
li r4,0
rlwimi r6,r4,0,24,31
sync
mtspr SPRN_LDSTCR,r6
sync
isync
/* Flush the L2 cache using the hardware assist */
mfspr r3,SPRN_L2CR
cmpwi r3,0 /* check if it is enabled first */
bge 4f
oris r0,r3,(L2CR_L2IO_745x|L2CR_L2DO_745x)@h
b 2f
/* When disabling/locking L2, code must be in L1 */
.balign 32
1: mtspr SPRN_L2CR,r0 /* lock the L2 cache */
3: sync
isync
b 1f
2: b 3f
3: sync
isync
b 1b
1: sync
isync
ori r0,r3,L2CR_L2HWF_745x
sync
mtspr SPRN_L2CR,r0 /* set the hardware flush bit */
3: mfspr r0,SPRN_L2CR /* wait for it to go to 0 */
andi. r0,r0,L2CR_L2HWF_745x
bne 3b
sync
rlwinm r3,r3,0,~L2CR_L2E
b 2f
/* When disabling L2, code must be in L1 */
.balign 32
1: mtspr SPRN_L2CR,r3 /* disable the L2 cache */
3: sync
isync
b 1f
2: b 3f
3: sync
isync
b 1b
1: sync
isync
oris r4,r3,L2CR_L2I@h
mtspr SPRN_L2CR,r4
sync
isync
1: mfspr r4,SPRN_L2CR
andis. r0,r4,L2CR_L2I@h
bne 1b
sync
BEGIN_FTR_SECTION
/* Flush the L3 cache using the hardware assist */
4: mfspr r3,SPRN_L3CR
cmpwi r3,0 /* check if it is enabled */
bge 6f
oris r0,r3,L3CR_L3IO@h
ori r0,r0,L3CR_L3DO
sync
mtspr SPRN_L3CR,r0 /* lock the L3 cache */
sync
isync
ori r0,r0,L3CR_L3HWF
sync
mtspr SPRN_L3CR,r0 /* set the hardware flush bit */
5: mfspr r0,SPRN_L3CR /* wait for it to go to zero */
andi. r0,r0,L3CR_L3HWF
bne 5b
rlwinm r3,r3,0,~L3CR_L3E
sync
mtspr SPRN_L3CR,r3 /* disable the L3 cache */
sync
ori r4,r3,L3CR_L3I
mtspr SPRN_L3CR,r4
1: mfspr r4,SPRN_L3CR
andi. r0,r4,L3CR_L3I
bne 1b
sync
END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
6: mfspr r0,SPRN_HID0 /* now disable the L1 data cache */
rlwinm r0,r0,0,~HID0_DCE
mtspr SPRN_HID0,r0
sync
isync
mtmsr r11 /* restore DR and EE */
isync
blr
#endif /* CONFIG_6xx */
|
AirFortressIlikara/LS2K0300-linux-4.19
| 9,559
|
arch/powerpc/platforms/powermac/sleep.S
|
/*
* This file contains sleep low-level functions for PowerBook G3.
* Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
* and Paul Mackerras (paulus@samba.org).
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
*/
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/ppc_asm.h>
#include <asm/cputable.h>
#include <asm/cache.h>
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
#include <asm/mmu.h>
#include <asm/feature-fixups.h>
#define MAGIC 0x4c617273 /* 'Lars' */
/*
* Structure for storing CPU registers on the stack.
*/
#define SL_SP 0
#define SL_PC 4
#define SL_MSR 8
#define SL_SDR1 0xc
#define SL_SPRG0 0x10 /* 4 sprg's */
#define SL_DBAT0 0x20
#define SL_IBAT0 0x28
#define SL_DBAT1 0x30
#define SL_IBAT1 0x38
#define SL_DBAT2 0x40
#define SL_IBAT2 0x48
#define SL_DBAT3 0x50
#define SL_IBAT3 0x58
#define SL_DBAT4 0x60
#define SL_IBAT4 0x68
#define SL_DBAT5 0x70
#define SL_IBAT5 0x78
#define SL_DBAT6 0x80
#define SL_IBAT6 0x88
#define SL_DBAT7 0x90
#define SL_IBAT7 0x98
#define SL_TB 0xa0
#define SL_R2 0xa8
#define SL_CR 0xac
#define SL_R12 0xb0 /* r12 to r31 */
#define SL_SIZE (SL_R12 + 80)
.section .text
.align 5
#if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || \
(defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32))
/* This gets called by via-pmu.c late during the sleep process.
* The PMU was already send the sleep command and will shut us down
* soon. We need to save all that is needed and setup the wakeup
* vector that will be called by the ROM on wakeup
*/
_GLOBAL(low_sleep_handler)
#ifndef CONFIG_6xx
blr
#else
mflr r0
stw r0,4(r1)
stwu r1,-SL_SIZE(r1)
mfcr r0
stw r0,SL_CR(r1)
stw r2,SL_R2(r1)
stmw r12,SL_R12(r1)
/* Save MSR & SDR1 */
mfmsr r4
stw r4,SL_MSR(r1)
mfsdr1 r4
stw r4,SL_SDR1(r1)
/* Get a stable timebase and save it */
1: mftbu r4
stw r4,SL_TB(r1)
mftb r5
stw r5,SL_TB+4(r1)
mftbu r3
cmpw r3,r4
bne 1b
/* Save SPRGs */
mfsprg r4,0
stw r4,SL_SPRG0(r1)
mfsprg r4,1
stw r4,SL_SPRG0+4(r1)
mfsprg r4,2
stw r4,SL_SPRG0+8(r1)
mfsprg r4,3
stw r4,SL_SPRG0+12(r1)
/* Save BATs */
mfdbatu r4,0
stw r4,SL_DBAT0(r1)
mfdbatl r4,0
stw r4,SL_DBAT0+4(r1)
mfdbatu r4,1
stw r4,SL_DBAT1(r1)
mfdbatl r4,1
stw r4,SL_DBAT1+4(r1)
mfdbatu r4,2
stw r4,SL_DBAT2(r1)
mfdbatl r4,2
stw r4,SL_DBAT2+4(r1)
mfdbatu r4,3
stw r4,SL_DBAT3(r1)
mfdbatl r4,3
stw r4,SL_DBAT3+4(r1)
mfibatu r4,0
stw r4,SL_IBAT0(r1)
mfibatl r4,0
stw r4,SL_IBAT0+4(r1)
mfibatu r4,1
stw r4,SL_IBAT1(r1)
mfibatl r4,1
stw r4,SL_IBAT1+4(r1)
mfibatu r4,2
stw r4,SL_IBAT2(r1)
mfibatl r4,2
stw r4,SL_IBAT2+4(r1)
mfibatu r4,3
stw r4,SL_IBAT3(r1)
mfibatl r4,3
stw r4,SL_IBAT3+4(r1)
BEGIN_MMU_FTR_SECTION
mfspr r4,SPRN_DBAT4U
stw r4,SL_DBAT4(r1)
mfspr r4,SPRN_DBAT4L
stw r4,SL_DBAT4+4(r1)
mfspr r4,SPRN_DBAT5U
stw r4,SL_DBAT5(r1)
mfspr r4,SPRN_DBAT5L
stw r4,SL_DBAT5+4(r1)
mfspr r4,SPRN_DBAT6U
stw r4,SL_DBAT6(r1)
mfspr r4,SPRN_DBAT6L
stw r4,SL_DBAT6+4(r1)
mfspr r4,SPRN_DBAT7U
stw r4,SL_DBAT7(r1)
mfspr r4,SPRN_DBAT7L
stw r4,SL_DBAT7+4(r1)
mfspr r4,SPRN_IBAT4U
stw r4,SL_IBAT4(r1)
mfspr r4,SPRN_IBAT4L
stw r4,SL_IBAT4+4(r1)
mfspr r4,SPRN_IBAT5U
stw r4,SL_IBAT5(r1)
mfspr r4,SPRN_IBAT5L
stw r4,SL_IBAT5+4(r1)
mfspr r4,SPRN_IBAT6U
stw r4,SL_IBAT6(r1)
mfspr r4,SPRN_IBAT6L
stw r4,SL_IBAT6+4(r1)
mfspr r4,SPRN_IBAT7U
stw r4,SL_IBAT7(r1)
mfspr r4,SPRN_IBAT7L
stw r4,SL_IBAT7+4(r1)
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
/* Backup various CPU config stuffs */
bl __save_cpu_setup
/* The ROM can wake us up via 2 different vectors:
* - On wallstreet & lombard, we must write a magic
* value 'Lars' at address 4 and a pointer to a
* memory location containing the PC to resume from
* at address 0.
* - On Core99, we must store the wakeup vector at
* address 0x80 and eventually it's parameters
* at address 0x84. I've have some trouble with those
* parameters however and I no longer use them.
*/
lis r5,grackle_wake_up@ha
addi r5,r5,grackle_wake_up@l
tophys(r5,r5)
stw r5,SL_PC(r1)
lis r4,KERNELBASE@h
tophys(r5,r1)
addi r5,r5,SL_PC
lis r6,MAGIC@ha
addi r6,r6,MAGIC@l
stw r5,0(r4)
stw r6,4(r4)
/* Setup stuffs at 0x80-0x84 for Core99 */
lis r3,core99_wake_up@ha
addi r3,r3,core99_wake_up@l
tophys(r3,r3)
stw r3,0x80(r4)
stw r5,0x84(r4)
/* Store a pointer to our backup storage into
* a kernel global
*/
lis r3,sleep_storage@ha
addi r3,r3,sleep_storage@l
stw r5,0(r3)
.globl low_cpu_die
low_cpu_die:
/* Flush & disable all caches */
bl flush_disable_caches
/* Turn off data relocation. */
mfmsr r3 /* Save MSR in r7 */
rlwinm r3,r3,0,28,26 /* Turn off DR bit */
sync
mtmsr r3
isync
BEGIN_FTR_SECTION
/* Flush any pending L2 data prefetches to work around HW bug */
sync
lis r3,0xfff0
lwz r0,0(r3) /* perform cache-inhibited load to ROM */
sync /* (caches are disabled at this point) */
END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
/*
* Set the HID0 and MSR for sleep.
*/
mfspr r2,SPRN_HID0
rlwinm r2,r2,0,10,7 /* clear doze, nap */
oris r2,r2,HID0_SLEEP@h
sync
isync
mtspr SPRN_HID0,r2
sync
/* This loop puts us back to sleep in case we have a spurrious
* wakeup so that the host bridge properly stays asleep. The
* CPU will be turned off, either after a known time (about 1
* second) on wallstreet & lombard, or as soon as the CPU enters
* SLEEP mode on core99
*/
mfmsr r2
oris r2,r2,MSR_POW@h
1: sync
mtmsr r2
isync
b 1b
/*
* Here is the resume code.
*/
/*
* Core99 machines resume here
* r4 has the physical address of SL_PC(sp) (unused)
*/
_GLOBAL(core99_wake_up)
/* Make sure HID0 no longer contains any sleep bit and that data cache
* is disabled
*/
mfspr r3,SPRN_HID0
rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
mtspr SPRN_HID0,r3
sync
isync
/* sanitize MSR */
mfmsr r3
ori r3,r3,MSR_EE|MSR_IP
xori r3,r3,MSR_EE|MSR_IP
sync
isync
mtmsr r3
sync
isync
/* Recover sleep storage */
lis r3,sleep_storage@ha
addi r3,r3,sleep_storage@l
tophys(r3,r3)
lwz r1,0(r3)
/* Pass thru to older resume code ... */
/*
* Here is the resume code for older machines.
* r1 has the physical address of SL_PC(sp).
*/
grackle_wake_up:
/* Restore the kernel's segment registers before
* we do any r1 memory access as we are not sure they
* are in a sane state above the first 256Mb region
*/
li r0,16 /* load up segment register values */
mtctr r0 /* for context 0 */
lis r3,0x2000 /* Ku = 1, VSID = 0 */
li r4,0
3: mtsrin r3,r4
addi r3,r3,0x111 /* increment VSID */
addis r4,r4,0x1000 /* address of next segment */
bdnz 3b
sync
isync
subi r1,r1,SL_PC
/* Restore various CPU config stuffs */
bl __restore_cpu_setup
/* Make sure all FPRs have been initialized */
bl reloc_offset
bl __init_fpu_registers
/* Invalidate & enable L1 cache, we don't care about
* whatever the ROM may have tried to write to memory
*/
bl __inval_enable_L1
/* Restore the BATs, and SDR1. Then we can turn on the MMU. */
lwz r4,SL_SDR1(r1)
mtsdr1 r4
lwz r4,SL_SPRG0(r1)
mtsprg 0,r4
lwz r4,SL_SPRG0+4(r1)
mtsprg 1,r4
lwz r4,SL_SPRG0+8(r1)
mtsprg 2,r4
lwz r4,SL_SPRG0+12(r1)
mtsprg 3,r4
lwz r4,SL_DBAT0(r1)
mtdbatu 0,r4
lwz r4,SL_DBAT0+4(r1)
mtdbatl 0,r4
lwz r4,SL_DBAT1(r1)
mtdbatu 1,r4
lwz r4,SL_DBAT1+4(r1)
mtdbatl 1,r4
lwz r4,SL_DBAT2(r1)
mtdbatu 2,r4
lwz r4,SL_DBAT2+4(r1)
mtdbatl 2,r4
lwz r4,SL_DBAT3(r1)
mtdbatu 3,r4
lwz r4,SL_DBAT3+4(r1)
mtdbatl 3,r4
lwz r4,SL_IBAT0(r1)
mtibatu 0,r4
lwz r4,SL_IBAT0+4(r1)
mtibatl 0,r4
lwz r4,SL_IBAT1(r1)
mtibatu 1,r4
lwz r4,SL_IBAT1+4(r1)
mtibatl 1,r4
lwz r4,SL_IBAT2(r1)
mtibatu 2,r4
lwz r4,SL_IBAT2+4(r1)
mtibatl 2,r4
lwz r4,SL_IBAT3(r1)
mtibatu 3,r4
lwz r4,SL_IBAT3+4(r1)
mtibatl 3,r4
BEGIN_MMU_FTR_SECTION
lwz r4,SL_DBAT4(r1)
mtspr SPRN_DBAT4U,r4
lwz r4,SL_DBAT4+4(r1)
mtspr SPRN_DBAT4L,r4
lwz r4,SL_DBAT5(r1)
mtspr SPRN_DBAT5U,r4
lwz r4,SL_DBAT5+4(r1)
mtspr SPRN_DBAT5L,r4
lwz r4,SL_DBAT6(r1)
mtspr SPRN_DBAT6U,r4
lwz r4,SL_DBAT6+4(r1)
mtspr SPRN_DBAT6L,r4
lwz r4,SL_DBAT7(r1)
mtspr SPRN_DBAT7U,r4
lwz r4,SL_DBAT7+4(r1)
mtspr SPRN_DBAT7L,r4
lwz r4,SL_IBAT4(r1)
mtspr SPRN_IBAT4U,r4
lwz r4,SL_IBAT4+4(r1)
mtspr SPRN_IBAT4L,r4
lwz r4,SL_IBAT5(r1)
mtspr SPRN_IBAT5U,r4
lwz r4,SL_IBAT5+4(r1)
mtspr SPRN_IBAT5L,r4
lwz r4,SL_IBAT6(r1)
mtspr SPRN_IBAT6U,r4
lwz r4,SL_IBAT6+4(r1)
mtspr SPRN_IBAT6L,r4
lwz r4,SL_IBAT7(r1)
mtspr SPRN_IBAT7U,r4
lwz r4,SL_IBAT7+4(r1)
mtspr SPRN_IBAT7L,r4
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
/* Flush all TLBs */
lis r4,0x1000
1: addic. r4,r4,-0x1000
tlbie r4
blt 1b
sync
/* restore the MSR and turn on the MMU */
lwz r3,SL_MSR(r1)
bl turn_on_mmu
/* get back the stack pointer */
tovirt(r1,r1)
/* Restore TB */
li r3,0
mttbl r3
lwz r3,SL_TB(r1)
lwz r4,SL_TB+4(r1)
mttbu r3
mttbl r4
/* Restore the callee-saved registers and return */
lwz r0,SL_CR(r1)
mtcr r0
lwz r2,SL_R2(r1)
lmw r12,SL_R12(r1)
addi r1,r1,SL_SIZE
lwz r0,4(r1)
mtlr r0
blr
turn_on_mmu:
mflr r4
tovirt(r4,r4)
mtsrr0 r4
mtsrr1 r3
sync
isync
rfi
#endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
.section .data
.balign L1_CACHE_BYTES
sleep_storage:
.long 0
.balign L1_CACHE_BYTES, 0
#endif /* CONFIG_6xx */
.section .text
|
AirFortressIlikara/LS2K0300-linux-4.19
| 10,919
|
arch/powerpc/platforms/83xx/suspend-asm.S
|
/*
* Enter and leave deep sleep state on MPC83xx
*
* Copyright (c) 2006-2008 Freescale Semiconductor, Inc.
* Author: Scott Wood <scottwood@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <asm/page.h>
#include <asm/ppc_asm.h>
#include <asm/reg.h>
#include <asm/asm-offsets.h>
#define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */
#define SS_HID 0x08 /* 3 HIDs */
#define SS_IABR 0x14 /* 2 IABRs */
#define SS_IBCR 0x1c
#define SS_DABR 0x20 /* 2 DABRs */
#define SS_DBCR 0x28
#define SS_SP 0x2c
#define SS_SR 0x30 /* 16 segment registers */
#define SS_R2 0x70
#define SS_MSR 0x74
#define SS_SDR1 0x78
#define SS_LR 0x7c
#define SS_SPRG 0x80 /* 8 SPRGs */
#define SS_DBAT 0xa0 /* 8 DBATs */
#define SS_IBAT 0xe0 /* 8 IBATs */
#define SS_TB 0x120
#define SS_CR 0x128
#define SS_GPREG 0x12c /* r12-r31 */
#define STATE_SAVE_SIZE 0x17c
.section .data
.align 5
mpc83xx_sleep_save_area:
.space STATE_SAVE_SIZE
immrbase:
.long 0
.section .text
.align 5
/* r3 = physical address of IMMR */
_GLOBAL(mpc83xx_enter_deep_sleep)
lis r4, immrbase@ha
stw r3, immrbase@l(r4)
/* The first 2 words of memory are used to communicate with the
* bootloader, to tell it how to resume.
*
* The first word is the magic number 0xf5153ae5, and the second
* is the pointer to mpc83xx_deep_resume.
*
* The original content of these two words is saved in SS_MEMSAVE.
*/
lis r3, mpc83xx_sleep_save_area@h
ori r3, r3, mpc83xx_sleep_save_area@l
lis r4, KERNELBASE@h
lwz r5, 0(r4)
lwz r6, 4(r4)
stw r5, SS_MEMSAVE+0(r3)
stw r6, SS_MEMSAVE+4(r3)
mfspr r5, SPRN_HID0
mfspr r6, SPRN_HID1
mfspr r7, SPRN_HID2
stw r5, SS_HID+0(r3)
stw r6, SS_HID+4(r3)
stw r7, SS_HID+8(r3)
mfspr r4, SPRN_IABR
mfspr r5, SPRN_IABR2
mfspr r6, SPRN_IBCR
mfspr r7, SPRN_DABR
mfspr r8, SPRN_DABR2
mfspr r9, SPRN_DBCR
stw r4, SS_IABR+0(r3)
stw r5, SS_IABR+4(r3)
stw r6, SS_IBCR(r3)
stw r7, SS_DABR+0(r3)
stw r8, SS_DABR+4(r3)
stw r9, SS_DBCR(r3)
mfspr r4, SPRN_SPRG0
mfspr r5, SPRN_SPRG1
mfspr r6, SPRN_SPRG2
mfspr r7, SPRN_SPRG3
mfsdr1 r8
stw r4, SS_SPRG+0(r3)
stw r5, SS_SPRG+4(r3)
stw r6, SS_SPRG+8(r3)
stw r7, SS_SPRG+12(r3)
stw r8, SS_SDR1(r3)
mfspr r4, SPRN_SPRG4
mfspr r5, SPRN_SPRG5
mfspr r6, SPRN_SPRG6
mfspr r7, SPRN_SPRG7
stw r4, SS_SPRG+16(r3)
stw r5, SS_SPRG+20(r3)
stw r6, SS_SPRG+24(r3)
stw r7, SS_SPRG+28(r3)
mfspr r4, SPRN_DBAT0U
mfspr r5, SPRN_DBAT0L
mfspr r6, SPRN_DBAT1U
mfspr r7, SPRN_DBAT1L
stw r4, SS_DBAT+0x00(r3)
stw r5, SS_DBAT+0x04(r3)
stw r6, SS_DBAT+0x08(r3)
stw r7, SS_DBAT+0x0c(r3)
mfspr r4, SPRN_DBAT2U
mfspr r5, SPRN_DBAT2L
mfspr r6, SPRN_DBAT3U
mfspr r7, SPRN_DBAT3L
stw r4, SS_DBAT+0x10(r3)
stw r5, SS_DBAT+0x14(r3)
stw r6, SS_DBAT+0x18(r3)
stw r7, SS_DBAT+0x1c(r3)
mfspr r4, SPRN_DBAT4U
mfspr r5, SPRN_DBAT4L
mfspr r6, SPRN_DBAT5U
mfspr r7, SPRN_DBAT5L
stw r4, SS_DBAT+0x20(r3)
stw r5, SS_DBAT+0x24(r3)
stw r6, SS_DBAT+0x28(r3)
stw r7, SS_DBAT+0x2c(r3)
mfspr r4, SPRN_DBAT6U
mfspr r5, SPRN_DBAT6L
mfspr r6, SPRN_DBAT7U
mfspr r7, SPRN_DBAT7L
stw r4, SS_DBAT+0x30(r3)
stw r5, SS_DBAT+0x34(r3)
stw r6, SS_DBAT+0x38(r3)
stw r7, SS_DBAT+0x3c(r3)
mfspr r4, SPRN_IBAT0U
mfspr r5, SPRN_IBAT0L
mfspr r6, SPRN_IBAT1U
mfspr r7, SPRN_IBAT1L
stw r4, SS_IBAT+0x00(r3)
stw r5, SS_IBAT+0x04(r3)
stw r6, SS_IBAT+0x08(r3)
stw r7, SS_IBAT+0x0c(r3)
mfspr r4, SPRN_IBAT2U
mfspr r5, SPRN_IBAT2L
mfspr r6, SPRN_IBAT3U
mfspr r7, SPRN_IBAT3L
stw r4, SS_IBAT+0x10(r3)
stw r5, SS_IBAT+0x14(r3)
stw r6, SS_IBAT+0x18(r3)
stw r7, SS_IBAT+0x1c(r3)
mfspr r4, SPRN_IBAT4U
mfspr r5, SPRN_IBAT4L
mfspr r6, SPRN_IBAT5U
mfspr r7, SPRN_IBAT5L
stw r4, SS_IBAT+0x20(r3)
stw r5, SS_IBAT+0x24(r3)
stw r6, SS_IBAT+0x28(r3)
stw r7, SS_IBAT+0x2c(r3)
mfspr r4, SPRN_IBAT6U
mfspr r5, SPRN_IBAT6L
mfspr r6, SPRN_IBAT7U
mfspr r7, SPRN_IBAT7L
stw r4, SS_IBAT+0x30(r3)
stw r5, SS_IBAT+0x34(r3)
stw r6, SS_IBAT+0x38(r3)
stw r7, SS_IBAT+0x3c(r3)
mfmsr r4
mflr r5
mfcr r6
stw r4, SS_MSR(r3)
stw r5, SS_LR(r3)
stw r6, SS_CR(r3)
stw r1, SS_SP(r3)
stw r2, SS_R2(r3)
1: mftbu r4
mftb r5
mftbu r6
cmpw r4, r6
bne 1b
stw r4, SS_TB+0(r3)
stw r5, SS_TB+4(r3)
stmw r12, SS_GPREG(r3)
li r4, 0
addi r6, r3, SS_SR-4
1: mfsrin r5, r4
stwu r5, 4(r6)
addis r4, r4, 0x1000
cmpwi r4, 0
bne 1b
/* Disable machine checks and critical exceptions */
mfmsr r4
rlwinm r4, r4, 0, ~MSR_CE
rlwinm r4, r4, 0, ~MSR_ME
mtmsr r4
isync
#define TMP_VIRT_IMMR 0xf0000000
#define DEFAULT_IMMR_VALUE 0xff400000
#define IMMRBAR_BASE 0x0000
lis r4, immrbase@ha
lwz r4, immrbase@l(r4)
/* Use DBAT0 to address the current IMMR space */
ori r4, r4, 0x002a
mtspr SPRN_DBAT0L, r4
lis r8, TMP_VIRT_IMMR@h
ori r4, r8, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT0U, r4
isync
/* Use DBAT1 to address the original IMMR space */
lis r4, DEFAULT_IMMR_VALUE@h
ori r4, r4, 0x002a
mtspr SPRN_DBAT1L, r4
lis r9, (TMP_VIRT_IMMR + 0x01000000)@h
ori r4, r9, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT1U, r4
isync
/* Use DBAT2 to address the beginning of RAM. This isn't done
* using the normal virtual mapping, because with page debugging
* enabled it will be read-only.
*/
li r4, 0x0002
mtspr SPRN_DBAT2L, r4
lis r4, KERNELBASE@h
ori r4, r4, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT2U, r4
isync
/* Flush the cache with our BAT, as there will be TLB misses
* otherwise if page debugging is enabled, and these misses
* will disturb the PLRU algorithm.
*/
bl __flush_disable_L1
/* Keep the i-cache enabled, so the hack below for low-boot
* flash will work.
*/
mfspr r3, SPRN_HID0
ori r3, r3, HID0_ICE
mtspr SPRN_HID0, r3
isync
lis r6, 0xf515
ori r6, r6, 0x3ae5
lis r7, mpc83xx_deep_resume@h
ori r7, r7, mpc83xx_deep_resume@l
tophys(r7, r7)
lis r5, KERNELBASE@h
stw r6, 0(r5)
stw r7, 4(r5)
/* Reset BARs */
li r4, 0
stw r4, 0x0024(r8)
stw r4, 0x002c(r8)
stw r4, 0x0034(r8)
stw r4, 0x003c(r8)
stw r4, 0x0064(r8)
stw r4, 0x006c(r8)
/* Rev 1 of the 8313 has problems with wakeup events that are
* pending during the transition to deep sleep state (such as if
* the PCI host sets the state to D3 and then D0 in rapid
* succession). This check shrinks the race window somewhat.
*
* See erratum PCI23, though the problem is not limited
* to PCI.
*/
lwz r3, 0x0b04(r8)
andi. r3, r3, 1
bne- mpc83xx_deep_resume
/* Move IMMR back to the default location, following the
* procedure specified in the MPC8313 manual.
*/
lwz r4, IMMRBAR_BASE(r8)
isync
lis r4, DEFAULT_IMMR_VALUE@h
stw r4, IMMRBAR_BASE(r8)
lis r4, KERNELBASE@h
lwz r4, 0(r4)
isync
lwz r4, IMMRBAR_BASE(r9)
mr r8, r9
isync
/* Check the Reset Configuration Word to see whether flash needs
* to be mapped at a low address or a high address.
*/
lwz r4, 0x0904(r8)
andis. r4, r4, 0x0400
li r4, 0
beq boot_low
lis r4, 0xff80
boot_low:
stw r4, 0x0020(r8)
lis r7, 0x8000
ori r7, r7, 0x0016
mfspr r5, SPRN_HID0
rlwinm r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
oris r5, r5, HID0_SLEEP@h
mtspr SPRN_HID0, r5
isync
mfmsr r5
oris r5, r5, MSR_POW@h
/* Enable the flash mapping at the appropriate address. This
* mapping will override the RAM mapping if booting low, so there's
* no need to disable the latter. This must be done inside the same
* cache line as setting MSR_POW, so that no instruction fetches
* from RAM happen after the flash mapping is turned on.
*/
.align 5
stw r7, 0x0024(r8)
sync
isync
mtmsr r5
isync
1: b 1b
mpc83xx_deep_resume:
lis r4, 1f@h
ori r4, r4, 1f@l
tophys(r4, r4)
mtsrr0 r4
mfmsr r4
rlwinm r4, r4, 0, ~(MSR_IR | MSR_DR)
mtsrr1 r4
rfi
1: tlbia
bl __inval_enable_L1
lis r3, mpc83xx_sleep_save_area@h
ori r3, r3, mpc83xx_sleep_save_area@l
tophys(r3, r3)
lwz r5, SS_MEMSAVE+0(r3)
lwz r6, SS_MEMSAVE+4(r3)
stw r5, 0(0)
stw r6, 4(0)
lwz r5, SS_HID+0(r3)
lwz r6, SS_HID+4(r3)
lwz r7, SS_HID+8(r3)
mtspr SPRN_HID0, r5
mtspr SPRN_HID1, r6
mtspr SPRN_HID2, r7
lwz r4, SS_IABR+0(r3)
lwz r5, SS_IABR+4(r3)
lwz r6, SS_IBCR(r3)
lwz r7, SS_DABR+0(r3)
lwz r8, SS_DABR+4(r3)
lwz r9, SS_DBCR(r3)
mtspr SPRN_IABR, r4
mtspr SPRN_IABR2, r5
mtspr SPRN_IBCR, r6
mtspr SPRN_DABR, r7
mtspr SPRN_DABR2, r8
mtspr SPRN_DBCR, r9
li r4, 0
addi r6, r3, SS_SR-4
1: lwzu r5, 4(r6)
mtsrin r5, r4
addis r4, r4, 0x1000
cmpwi r4, 0
bne 1b
lwz r4, SS_DBAT+0x00(r3)
lwz r5, SS_DBAT+0x04(r3)
lwz r6, SS_DBAT+0x08(r3)
lwz r7, SS_DBAT+0x0c(r3)
mtspr SPRN_DBAT0U, r4
mtspr SPRN_DBAT0L, r5
mtspr SPRN_DBAT1U, r6
mtspr SPRN_DBAT1L, r7
lwz r4, SS_DBAT+0x10(r3)
lwz r5, SS_DBAT+0x14(r3)
lwz r6, SS_DBAT+0x18(r3)
lwz r7, SS_DBAT+0x1c(r3)
mtspr SPRN_DBAT2U, r4
mtspr SPRN_DBAT2L, r5
mtspr SPRN_DBAT3U, r6
mtspr SPRN_DBAT3L, r7
lwz r4, SS_DBAT+0x20(r3)
lwz r5, SS_DBAT+0x24(r3)
lwz r6, SS_DBAT+0x28(r3)
lwz r7, SS_DBAT+0x2c(r3)
mtspr SPRN_DBAT4U, r4
mtspr SPRN_DBAT4L, r5
mtspr SPRN_DBAT5U, r6
mtspr SPRN_DBAT5L, r7
lwz r4, SS_DBAT+0x30(r3)
lwz r5, SS_DBAT+0x34(r3)
lwz r6, SS_DBAT+0x38(r3)
lwz r7, SS_DBAT+0x3c(r3)
mtspr SPRN_DBAT6U, r4
mtspr SPRN_DBAT6L, r5
mtspr SPRN_DBAT7U, r6
mtspr SPRN_DBAT7L, r7
lwz r4, SS_IBAT+0x00(r3)
lwz r5, SS_IBAT+0x04(r3)
lwz r6, SS_IBAT+0x08(r3)
lwz r7, SS_IBAT+0x0c(r3)
mtspr SPRN_IBAT0U, r4
mtspr SPRN_IBAT0L, r5
mtspr SPRN_IBAT1U, r6
mtspr SPRN_IBAT1L, r7
lwz r4, SS_IBAT+0x10(r3)
lwz r5, SS_IBAT+0x14(r3)
lwz r6, SS_IBAT+0x18(r3)
lwz r7, SS_IBAT+0x1c(r3)
mtspr SPRN_IBAT2U, r4
mtspr SPRN_IBAT2L, r5
mtspr SPRN_IBAT3U, r6
mtspr SPRN_IBAT3L, r7
lwz r4, SS_IBAT+0x20(r3)
lwz r5, SS_IBAT+0x24(r3)
lwz r6, SS_IBAT+0x28(r3)
lwz r7, SS_IBAT+0x2c(r3)
mtspr SPRN_IBAT4U, r4
mtspr SPRN_IBAT4L, r5
mtspr SPRN_IBAT5U, r6
mtspr SPRN_IBAT5L, r7
lwz r4, SS_IBAT+0x30(r3)
lwz r5, SS_IBAT+0x34(r3)
lwz r6, SS_IBAT+0x38(r3)
lwz r7, SS_IBAT+0x3c(r3)
mtspr SPRN_IBAT6U, r4
mtspr SPRN_IBAT6L, r5
mtspr SPRN_IBAT7U, r6
mtspr SPRN_IBAT7L, r7
lwz r4, SS_SPRG+16(r3)
lwz r5, SS_SPRG+20(r3)
lwz r6, SS_SPRG+24(r3)
lwz r7, SS_SPRG+28(r3)
mtspr SPRN_SPRG4, r4
mtspr SPRN_SPRG5, r5
mtspr SPRN_SPRG6, r6
mtspr SPRN_SPRG7, r7
lwz r4, SS_SPRG+0(r3)
lwz r5, SS_SPRG+4(r3)
lwz r6, SS_SPRG+8(r3)
lwz r7, SS_SPRG+12(r3)
lwz r8, SS_SDR1(r3)
mtspr SPRN_SPRG0, r4
mtspr SPRN_SPRG1, r5
mtspr SPRN_SPRG2, r6
mtspr SPRN_SPRG3, r7
mtsdr1 r8
lwz r4, SS_MSR(r3)
lwz r5, SS_LR(r3)
lwz r6, SS_CR(r3)
lwz r1, SS_SP(r3)
lwz r2, SS_R2(r3)
mtsrr1 r4
mtsrr0 r5
mtcr r6
li r4, 0
mtspr SPRN_TBWL, r4
lwz r4, SS_TB+0(r3)
lwz r5, SS_TB+4(r3)
mtspr SPRN_TBWU, r4
mtspr SPRN_TBWL, r5
lmw r12, SS_GPREG(r3)
/* Kick decrementer */
li r0, 1
mtdec r0
rfi
|
AirFortressIlikara/LS2K0300-linux-4.19
| 1,855
|
arch/powerpc/platforms/pasemi/powersave.S
|
/*
* Copyright (C) 2006-2007 PA Semi, Inc
*
* Maintained by: Olof Johansson <olof@lixom.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/ppc_asm.h>
#include <asm/cputable.h>
#include <asm/cache.h>
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
/* Power savings opcodes since not all binutils have them at this time */
#define DOZE .long 0x4c000324
#define NAP .long 0x4c000364
#define SLEEP .long 0x4c0003a4
#define RVW .long 0x4c0003e4
/* Common sequence to do before going to any of the
* powersavings modes.
*/
#define PRE_SLEEP_SEQUENCE \
std r3,8(r1); \
ptesync ; \
ld r3,8(r1); \
1: cmpd r3,r3; \
bne 1b
_doze:
PRE_SLEEP_SEQUENCE
DOZE
b .
_GLOBAL(idle_spin)
blr
_GLOBAL(idle_doze)
LOAD_REG_ADDR(r3, _doze)
b sleep_common
/* Add more modes here later */
sleep_common:
mflr r0
std r0, 16(r1)
stdu r1,-64(r1)
#ifdef CONFIG_PPC_PASEMI_CPUFREQ
std r3, 48(r1)
/* Only do power savings when in astate 0 */
bl check_astate
cmpwi r3,0
bne 1f
ld r3, 48(r1)
#endif
LOAD_REG_IMMEDIATE(r6,MSR_DR|MSR_IR|MSR_ME|MSR_EE)
mfmsr r4
andc r5,r4,r6
mtmsrd r5,0
mtctr r3
bctrl
mtmsrd r4,0
1: addi r1,r1,64
ld r0,16(r1)
mtlr r0
blr
|
AirFortressIlikara/LS2K0300-linux-4.19
| 3,153
|
arch/powerpc/platforms/cell/spufs/spu_restore_crt0.S
|
/*
* crt0_r.S: Entry function for SPU-side context restore.
*
* Copyright (C) 2005 IBM
*
* Entry and exit function for SPU-side of the context restore
* sequence. Sets up an initial stack frame, then branches to
* 'main'. On return, restores all 128 registers from the LSCSA
* and exits.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <asm/spu_csa.h>
.data
.align 7
.globl regs_spill
regs_spill:
.space SIZEOF_SPU_SPILL_REGS, 0x0
.text
.global _start
_start:
/* Initialize the stack pointer to point to 16368
* (16kb-16). The back chain pointer is initialized
* to NULL.
*/
il $0, 0
il $SP, 16368
stqd $0, 0($SP)
/* Allocate a minimum stack frame for the called main.
* This is needed so that main has a place to save the
* link register when it calls another function.
*/
stqd $SP, -160($SP)
ai $SP, $SP, -160
/* Call the program's main function. */
brsl $0, main
.global exit
.global _exit
exit:
_exit:
/* SPU Context Restore, Step 5: Restore the remaining 112 GPRs. */
ila $3, regs_spill + 256
restore_regs:
lqr $4, restore_reg_insts
restore_reg_loop:
ai $4, $4, 4
.balignl 16, 0x40200000
restore_reg_insts: /* must be quad-word aligned. */
lqd $16, 0($3)
lqd $17, 16($3)
lqd $18, 32($3)
lqd $19, 48($3)
andi $5, $4, 0x7F
stqr $4, restore_reg_insts
ai $3, $3, 64
brnz $5, restore_reg_loop
/* SPU Context Restore Step 17: Restore the first 16 GPRs. */
lqa $0, regs_spill + 0
lqa $1, regs_spill + 16
lqa $2, regs_spill + 32
lqa $3, regs_spill + 48
lqa $4, regs_spill + 64
lqa $5, regs_spill + 80
lqa $6, regs_spill + 96
lqa $7, regs_spill + 112
lqa $8, regs_spill + 128
lqa $9, regs_spill + 144
lqa $10, regs_spill + 160
lqa $11, regs_spill + 176
lqa $12, regs_spill + 192
lqa $13, regs_spill + 208
lqa $14, regs_spill + 224
lqa $15, regs_spill + 240
/* Under normal circumstances, the 'exit' function
* terminates with 'stop SPU_RESTORE_COMPLETE',
* indicating that the SPU-side restore code has
* completed.
*
* However it is possible that instructions immediately
* following the 'stop 0x3ffc' have been modified at run
* time so as to recreate the exact SPU_Status settings
* from the application, e.g. illegal instruciton, halt,
* etc.
*/
.global exit_fini
.global _exit_fini
exit_fini:
_exit_fini:
stop SPU_RESTORE_COMPLETE
stop 0
stop 0
stop 0
/* Pad the size of this crt0.o to be multiple of 16 bytes. */
.balignl 16, 0x0
|
AirFortressIlikara/LS2K0300-linux-4.19
| 2,680
|
arch/powerpc/platforms/cell/spufs/spu_save_crt0.S
|
/*
* crt0_s.S: Entry function for SPU-side context save.
*
* Copyright (C) 2005 IBM
*
* Entry function for SPU-side of the context save sequence.
* Saves all 128 GPRs, sets up an initial stack frame, then
* branches to 'main'.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <asm/spu_csa.h>
.data
.align 7
.globl regs_spill
regs_spill:
.space SIZEOF_SPU_SPILL_REGS, 0x0
.text
.global _start
_start:
/* SPU Context Save Step 1: Save the first 16 GPRs. */
stqa $0, regs_spill + 0
stqa $1, regs_spill + 16
stqa $2, regs_spill + 32
stqa $3, regs_spill + 48
stqa $4, regs_spill + 64
stqa $5, regs_spill + 80
stqa $6, regs_spill + 96
stqa $7, regs_spill + 112
stqa $8, regs_spill + 128
stqa $9, regs_spill + 144
stqa $10, regs_spill + 160
stqa $11, regs_spill + 176
stqa $12, regs_spill + 192
stqa $13, regs_spill + 208
stqa $14, regs_spill + 224
stqa $15, regs_spill + 240
/* SPU Context Save, Step 8: Save the remaining 112 GPRs. */
ila $3, regs_spill + 256
save_regs:
lqr $4, save_reg_insts
save_reg_loop:
ai $4, $4, 4
.balignl 16, 0x40200000
save_reg_insts: /* must be quad-word aligned. */
stqd $16, 0($3)
stqd $17, 16($3)
stqd $18, 32($3)
stqd $19, 48($3)
andi $5, $4, 0x7F
stqr $4, save_reg_insts
ai $3, $3, 64
brnz $5, save_reg_loop
/* Initialize the stack pointer to point to 16368
* (16kb-16). The back chain pointer is initialized
* to NULL.
*/
il $0, 0
il $SP, 16368
stqd $0, 0($SP)
/* Allocate a minimum stack frame for the called main.
* This is needed so that main has a place to save the
* link register when it calls another function.
*/
stqd $SP, -160($SP)
ai $SP, $SP, -160
/* Call the program's main function. */
brsl $0, main
/* In this case main should not return; if it does
* there has been an error in the sequence. Execute
* stop-and-signal with code=0.
*/
.global exit
.global _exit
exit:
_exit:
stop 0x0
/* Pad the size of this crt0.o to be multiple of 16 bytes. */
.balignl 16, 0x0
|
Ai-Thinker-Open/Telink_825X_SDK
| 10,912
|
components/boot/div_mod.S
|
/********************************************************************************************************
* @file div_mod.S
*
* @brief This is the assembly file for TLSR8258
*
* @author author@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#define UDIV #0
#define SDIV #1
#define UMOD #2
#define SMOD #3
#define MUL2_STEP 8
.code 16
.text
.section .ram_code,"ax" //in ram code
.align 2
.global __modsi3
.code 16
.thumb_func
.type __modsi3, %function
__modsi3:
tmov r2, SMOD
tj div
.size __modsi3, .-__modsi3
.section .ram_code,"ax" //in ram code
.align 2
.global __divsi3
.code 16
.thumb_func
.type __divsi3, %function
__divsi3:
tmov r2, SDIV
tj div
.size __divsi3, .-__divsi3
.section .ram_code,"ax" //in ram code
.align 2
.global __umodsi3
.code 16
.thumb_func
.type __umodsi3, %function
__umodsi3:
tmov r2, UMOD
tj div
.size __umodsi3, .-__umodsi3
.section .ram_code,"ax" //in ram code
.align 2
.global __udivsi3
.code 16
.thumb_func
.type __udivsi3, %function
__udivsi3:
tmov r2, UDIV
tj div
.size __udivsi3, .-__udivsi3
.section .ram_code,"ax" //in ram code
.align 2
.global div
.code 16
.thumb_func
.type div, %function
div:
tmrcs r3
tpush {r3, r4}
tmov r4, #0x80
tor r3, r4
tmcsr r3
tloadr r3, .L11
tstorer r0, [r3]
tadd r3, r3, #4
tstorer r1, [r3]
tsub r3, r3, #8
tstorerb r2, [r3]
.L2:
tloadrb r0, [r3]
tcmp r0, #0
tjne .L2
tcmp r2, #1
tjls .L4
tadd r3, r3, #8
tloadr r0, [r3]
tj .L6
.L4:
tadd r3, r3, #4
tloadr r0, [r3]
.L6:
tpop {r3, r4}
tmcsr r3
tjex lr
.align 4
.L11:
.word(0x800664)
.word(0x800660)
.word(0x800668)
.size div, .-div
//removed
#if 0
//.section .ram_code,"ax" //in ram code
.align 4
.global mul32x32_64
.thumb_func
.type mul32x32_64, %function
mul32x32_64:
tmul r0, r1
tloadr r1, [pc, #4]
tloadr r1, [r1, #0]
tjex lr
.word(0x008006fc)
#endif
#if 0
//.section .ram_code,"ax" //in ram code
.align 4
.global mz_mul1
.thumb_func
.type mz_mul1, %function
mz_mul1:
tpush {r4, r5, r6, r7}
tmov r4, r8
tpush {r4}
tmov r4, #1
tmov r8, r4 //r8 = 1
tloadr r6, [pc, #4] //r6 REG_ADDR32(0x6fc)
tmovs r5, #0 //clear carry
tj MZ_MUL1_END
.word(0x008006fc)
MZ_MUL1_START:
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r5 // l0 + c => c0
tsubc r5, r5 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r5, r8 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0
taddc r5, r7 // cn = c0 + h1 + c1
MZ_MUL1_END:
tloadm r1!, {r4} // load *a
tsub r2, #1 // r2--
tcmp r2, #0
tjge MZ_MUL1_START // carry set
tstorem r0!, {r5}
tpop {r4}
tmov r8, r4
tpop {r4, r5, r6, r7}
tjex lr
#endif
//.section .ram_code,"ax" //in ram code
.align 4
.global mz_mul2
.thumb_func
.type mz_mul2, %function
mz_mul2:
tpush {r4, r5, r6, r7}
tmov r4, r8
tmov r5, r9
tmov r6, r10
tmov r7, r11
tpush {r4, r5, r6, r7}
tmov r8, r2 //r8 = n, loop number
tmov r2, #1
tmov r10, r2 // r10 = 1
tsub r2, #(MUL2_STEP + 1)
tmov r9, r2 //r9 = -MUL2_STEP
tmov r2, #0
tmov r2, #0
tloadr r6, [pc, #4] //r6 REG_ADDR32(0x6fc)
tmov r11,r2 //r11 = 0
tj MZ_MUL2_LOOP
//tj MZ_MUL2_LOOP2
.word(0x008006fc)
MZ_MUL2_START:
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
///// next 2
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
taddc r2, r7 // cn2 = c2 + h1 + c3
MZ_MUL2_LOOP:
tloadm r1!, {r4, r5} // load *a
tadd r8, r9 // r8 -= MUL2_STEP
tcmp r8, r11 // const 0
tjge MZ_MUL2_START // carry set
tmov r5, r8
tadd r5, #MUL2_STEP
tsub r1, #8
tj MZ_MUL2_LOOP2
MZ_MUL2_START2:
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0
taddc r2, r7 // cn = c0 + h1 + c1
MZ_MUL2_LOOP2:
tloadm r1!, {r4} // load *a
tsub r5, #1 // r7--
tcmp r5, #0
tjge MZ_MUL2_START2 // carry set
MZ_MUL2_END:
//tmov r2, #13
tstorem r0!, {r2}
tpop {r4, r5, r6, r7}
tmov r8, r4
tmov r9, r5
tmov r10, r6
tmov r11, r7
tpop {r4, r5, r6, r7}
tjex lr
tnop
///////// asm crc24 function 2
.section .ram_code,"ax" //in ram code
.align 2
.global blt_packet_crc24_opt
.code 16
.thumb_func
.type blt_packet_crc24_opt, %function
blt_packet_crc24_opt:
tpush {r3, r4, r5, r6, r7, lr}
tmov r5, r8
tpush {r5}
tmov r5, r1
tneg r1, r0
tmov r4, #3
tand r1, r4 //number of byte CRC of pre_process to align CRC to word boundary
tsub r5, r1
tjge CRC24_SAVE_WORD_NUM
tadd r1, r5
tmov r5, #0
CRC24_SAVE_WORD_NUM:
tmov r8, r5 //save to r8
//tloadr r3, CRC24_DAT
tadd r4, r0, #0
tmov r0, #0
tmov r7, #60 //r7 = 15 * 4
CRC24_BYTE_LOOP: //r4: src; r6: dat; r2: crc; r5: tmp
tcmp r0, r1
tjeq CRC24_BYTE_END
tloadrb r6, [r4, r0] //r6 = dat[r0]
txor r6, r2 //r6 = crc ^ dat
tshftl r5, r6, #2 //r5 = r6 << 2
tand r5, r7 //r2 = r2 & 60
tloadr r5, [r5, r3] //load table
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r6, #2 // r6 = r6 >> 2
txor r2, r5 //r2 = r5 ^ r2
tand r6, r7 //r6 = r6 & 60
tloadr r6, [r6, r3]
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tadd r0, #1
txor r2, r6 //r2 = r6 ^ r2
tjne CRC24_BYTE_LOOP
CRC24_BYTE_END:
tmov r1, r8
tcmp r1, #0
tjeq CRC24_END
tmov r5, #0
tmov r8, r5
tadd r4, r0
tmov r0, #0
CRC24_WORD_LOOP:
tsub r1, #4
tjlt CRC24_WORD_END
tloadr r0, [r4, #0] //r0 = dat[r0]
tadd r4, #4
tshftr r6, r0, #0 // r6 = r0 >> 0
CRC24_WORD_nib0:
txor r6, r2 //r6 = crc ^ dat
tshftl r5, r6, #2 //r5 = r6 << 2
tand r5, r7 //r2 = r2 & 60
tloadr r5, [r5, r3] //load table
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r6, #2 // r6 = r6 >> 2
tand r6, r7 //r6 = r6 & 60
tloadr r6, [r6, r3]
txor r2, r5 //r2 = r5 ^ r2
CRC24_WORD_nib1:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r0, #8 //dat >> 8
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib2:
txor r5, r2 //r6 = crc ^ dat
tshftl r6, r5, #2 //r5 << 2
tand r6, r7
tloadr r6, [r6, r3]
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r5, #2
tand r5, r7 //r6 = r6 & 60
tloadr r5, [r5, r3]
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib3:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r0, #16 //dat >> 8
txor r2, r5 //r2 = r6 ^ r2
CRC24_WORD_nib4:
txor r6, r2 //r6 = crc ^ dat
tshftl r5, r6, #2 //r5 = r6 << 2
tand r5, r7 //r2 = r2 & 60
tloadr r5, [r5, r3] //load table
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r6, #2 // r6 = r6 >> 2
tand r6, r7 //r6 = r6 & 60
tloadr r6, [r6, r3]
txor r2, r5 //r2 = r5 ^ r2
CRC24_WORD_nib5:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r0, #24 //dat >> 8
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib6:
txor r5, r2 //r6 = crc ^ dat
tshftl r6, r5, #2 //r5 << 2
tand r6, r7
tloadr r6, [r6, r3]
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r5, #2
tand r5, r7 //r5 = r5 & 60
tloadr r5, [r5, r3]
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib7:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tmov r0, #0
txor r2, r5 //r2 = r6 ^ r2
tj CRC24_WORD_LOOP
CRC24_WORD_END:
tadd r1, #4
tj CRC24_BYTE_LOOP
CRC24_END:
tadd r0, r2, #0
tpop {r5}
tmov r8, r5
tpop {r3, r4, r5, r6, r7, pc}
tnop
// static int Crc24Lookup[16] = {
// 0x0000000,0x01b4c00,0x0369800,0x02dd400,
// 0x06d3000,0x0767c00,0x05ba800,0x040e400,
// 0x0da6000,0x0c12c00,0x0ecf800,0x0f7b400,
// 0x0b75000,0x0ac1c00,0x081c800,0x09a8400,
// };
// //usage
// //crc = blt_packet_crc24_opt (dat, length, crc_init, Crc24Lookup);
|
Ai-Thinker-Open/Telink_825X_SDK
| 9,176
|
components/boot/8251/cstartup_8251_RET_32K.S
|
/********************************************************************************************************
* @file cstartup_8251_RET_32K.S
*
* @brief This is the boot file for TLSR8258
*
* @author public@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#ifdef MCU_STARTUP_8251_RET_32K
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ramcode_size_align_256_
.extern _ictag_start_
.extern _ictag_end_
.extern _ram_use_size_align_256__
.org 0x0
tj __reset
@ .word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + 13) @208 byte: load vector part before START_SECTIONS
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
@ enable debug GPIO toggle
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
RANA_REG_BEGIN:
@ 1.system on for read anag_reg module
tloadr r0,ADATA_I+8 @0x00800060
tloadr r1,ADATA_I+12 @0xff000000
tstorer r1,[r0,#0] @*(unsigned int*)0x800060=0xff000000
tshftr r1,r1,#24 @0x000000ff
tstorerb r1,[r0,#4]
tstorerb r1,[r0,#5]
@ 2.read ana_reg_0x7f
tloadr r0,ADATA_I+0 @0x7f
@ read anag_reg(0x7f):
tloadr r1,ADATA_I+4 @0x008000b8
tmov r2,r0 @ana_reg_adr:0x7f
tstorerb r2,[r1,#0] @*(unsigned int*)0x8000b8=0x7f;
tmov r2,#64 @ana_reg_dat:0x40=64
tstorerb r2,[r1,#2] @*(unsigned int*)0x8000ba=0x40;
RWAIT_REG_FINISH:
tloadrb r2,[r1,#2]
tshftl r2,r2,#31
tshftr r2,r2,#31
tcmp r2,#1
tjeq RWAIT_REG_FINISH
tloadrb r2,[r1,#1]
@ read anag_reg end
@ 3.check: if(!(analog_read(0x7f) & 0x01)){ //deepretention mode }
@ copy flash ram code part to SRAM
CPY_FLASH_RAM_PART_TO_SRAM:
tmov r3, #1
tand r3, r2
tcmp r3, #1
tjne START_SECTIONS // 0->deepreten
tloadr r0, IC_IA @r0 = 0x800608
tloadr r1, CODE_CPY @r1 = 0x000060 -> 0x000070
tloadr r2, CODE_CPY+4 @r2 = virtual_ram_code_size=vector_size+ram_code_size
tmov r4, #1 @r4 = 1
tshftl r4, r4, #24 @r4 = r4<<24
PWR_ON_CPY:
tcmp r1, r2 @
tjge START_SECTIONS @r1>=r2 jump to START_SECTIONS
tmov r5, r4 @r5=r4
tadd r5, r1 @r5=r5+r1
tstorer r5, [r0, #0] @*(unsigned int*)0x800608 = r5;
LOOP_WHILE:
tloadr r3, [r0, #0] @r3 = *(unsigned int*)0x800608;
tasr r3, r3, #24 @r3 = r3>>24
tcmp r3, #0
tjne LOOP_WHILE @r3!=0 jump to loop_wait
tadd r1, #16 @r1=r1+16
tj PWR_ON_CPY @jump to PWR_ON_CPY
PWR_ON_CPY_END:
.balign 4
IC_IA:
.word 0x00800608
CODE_CPY:
.word (0x000000d0) @0 208 byte:
.word (_ram_use_size_align_256__) @4
ADATA_I:
.word (0x0000007f) @0
.word (0x008000b8) @4
.word (0x00800060) @8
.word (0xff000000) @12
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
.org 0xd0
START_SECTIONS:
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE) @8
.word (0x848000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word _ictag_start_ @28 @ IC tag start
.word _ictag_end_ @32 @ IC tag end
.word _retention_data_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff @0
.word (_start_data_) @4
.word (_start_data_ + 32) @8 @.word (0x848000)
.word (_retention_data_start_) @12
.word (_retention_data_end_) @16
.word (_rstored_) @20
.word (_ram_use_size_div_16_) @24
@.word (0x544c4e4b) @28
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_825X_SDK
| 6,964
|
components/boot/8251/cstartup_8251_RET_16K.S
|
/********************************************************************************************************
* @file cstartup_8251_RET_16K.S
*
* @brief This is the boot file for TLSR8258
*
* @author public@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#ifdef MCU_STARTUP_8251_RET_16K
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ramcode_size_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
@ .word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ram_use_size_div_16_)
@ .word (0x00880000 + 0x400)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x848000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word (0x844000) @28
.word (0x844100) @32
.word (0x40) @36
@ .word _ictag_start_ @28 @ IC tag start
@ .word _ictag_end_ @32 @ IC tag end
@ .word _ramcode_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff
.word (_start_data_)
@.word (0x848000)
.word (_start_data_ + 32)
.word (_retention_data_start_) @16
.word (_retention_data_end_) @20
.word (_rstored_) @24
.word (_ram_use_size_div_16_)
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_825X_SDK
| 6,612
|
components/boot/8251/cstartup_8251.S
|
/********************************************************************************************************
* @file cstartup_8258.S
*
* @brief This is the boot file for TLSR8258
*
* @author public@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#ifdef MCU_STARTUP_8251
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
@ .word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ramcode_size_div_16_align_256_)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x848000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word _ictag_start_ @28 @ IC tag start
.word _ictag_end_ @32 @ IC tag end
.word _ramcode_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff
.word (_start_data_)
@.word (0x848000)
.word (_start_data_ + 32)
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_825X_SDK
| 6,964
|
components/boot/8253/cstartup_8253_RET_32K.S
|
/********************************************************************************************************
* @file cstartup_8253_RET_32K.S
*
* @brief This is the boot file for TLSR8258
*
* @author public@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#ifdef MCU_STARTUP_8253_RET_32K
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ramcode_size_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
@ .word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ram_use_size_div_16_)
@ .word (0x00880000 + 0x800)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x84c000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word (0x848000) @28
.word (0x848100) @32
.word (0x80) @36
@ .word _ictag_start_ @28 @ IC tag start
@ .word _ictag_end_ @32 @ IC tag end
@ .word _ramcode_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff
.word (_start_data_)
@.word (0x84c000)
.word (_start_data_ + 32)
.word (_retention_data_start_) @16
.word (_retention_data_end_) @20
.word (_rstored_) @24
.word (_ram_use_size_div_16_)
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_825X_SDK
| 6,964
|
components/boot/8253/cstartup_8253_RET_16K.S
|
/********************************************************************************************************
* @file 8253_cstartup_RET_16K.S
*
* @brief This is the boot file for TLSR8258
*
* @author public@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#ifdef MCU_STARTUP_8253_RET_16K
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ramcode_size_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
@ .word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ram_use_size_div_16_)
@ .word (0x00880000 + 0x400)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x84c000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word (0x844000) @28
.word (0x844100) @32
.word (0x40) @36
@ .word _ictag_start_ @28 @ IC tag start
@ .word _ictag_end_ @32 @ IC tag end
@ .word _ramcode_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff
.word (_start_data_)
@.word (0x84c000)
.word (_start_data_ + 32)
.word (_retention_data_start_) @16
.word (_retention_data_end_) @20
.word (_rstored_) @24
.word (_ram_use_size_div_16_)
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_825X_SDK
| 6,612
|
components/boot/8253/cstartup_8253.S
|
/********************************************************************************************************
* @file cstartup_8253.S
*
* @brief This is the boot file for TLSR8258
*
* @author public@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#ifdef MCU_STARTUP_8253
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
@ .word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ramcode_size_div_16_align_256_)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x84c000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word _ictag_start_ @28 @ IC tag start
.word _ictag_end_ @32 @ IC tag end
.word _ramcode_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff
.word (_start_data_)
@.word (0x84c000)
.word (_start_data_ + 32)
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_825X_SDK
| 6,612
|
components/boot/8258/cstartup_8258.S
|
/********************************************************************************************************
* @file cstartup_8258.S
*
* @brief This is the boot file for TLSR8258
*
* @author public@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#ifdef MCU_STARTUP_8258
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
@ .word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ramcode_size_div_16_align_256_)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x850000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word _ictag_start_ @28 @ IC tag start
.word _ictag_end_ @32 @ IC tag end
.word _ramcode_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff
.word (_start_data_)
@.word (0x850000)
.word (_start_data_ + 32)
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_825X_SDK
| 6,964
|
components/boot/8258/cstartup_8258_RET_32K.S
|
/********************************************************************************************************
* @file cstartup_8258_RET_32K.S
*
* @brief This is the boot file for TLSR8258
*
* @author public@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#ifdef MCU_STARTUP_8258_RET_32K
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ramcode_size_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
@ .word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ram_use_size_div_16_)
@ .word (0x00880000 + 0x800)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x850000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word (0x848000) @28
.word (0x848100) @32
.word (0x80) @36
@ .word _ictag_start_ @28 @ IC tag start
@ .word _ictag_end_ @32 @ IC tag end
@ .word _ramcode_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff
.word (_start_data_)
@.word (0x850000)
.word (_start_data_ + 32)
.word (_retention_data_start_) @16
.word (_retention_data_end_) @20
.word (_rstored_) @24
.word (_ram_use_size_div_16_)
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_825X_SDK
| 7,098
|
components/boot/8258/cstartup_8258_RET_16K.S
|
/********************************************************************************************************
* @file 8258_cstartup_RET_16K.S
*
* @brief This is the boot file for TLSR8258
*
* @author public@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#ifdef MCU_STARTUP_8258_RET_16K
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ramcode_size_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
@ .word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ram_use_size_div_16_)
@ .word (0x00880000 + 0x400)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x850000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word (0x844000) @28
.word (0x844100) @32
.word (0x40) @36
@ .word _ictag_start_ @28 @ IC tag start
@ .word _ictag_end_ @32 @ IC tag end
@ .word _ramcode_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff
.word (_start_data_)
@.word (0x850000)
.word (_start_data_ + 32)
.word (_retention_data_start_) @16
.word (_retention_data_end_) @20
.word (_rstored_) @24
.word (_ram_use_size_div_16_)
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
//---------------------
#ifdef USE_FREE_RTOS
tmov r1, r13
tloadr r2, =StackSave
tstorer r1, [r2]
#endif
//---------------------
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_825X_SDK
| 10,912
|
example/bootloader/div_mod.S
|
/********************************************************************************************************
* @file div_mod.S
*
* @brief This is the assembly file for TLSR8258
*
* @author author@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#define UDIV #0
#define SDIV #1
#define UMOD #2
#define SMOD #3
#define MUL2_STEP 8
.code 16
.text
.section .ram_code,"ax" //in ram code
.align 2
.global __modsi3
.code 16
.thumb_func
.type __modsi3, %function
__modsi3:
tmov r2, SMOD
tj div
.size __modsi3, .-__modsi3
.section .ram_code,"ax" //in ram code
.align 2
.global __divsi3
.code 16
.thumb_func
.type __divsi3, %function
__divsi3:
tmov r2, SDIV
tj div
.size __divsi3, .-__divsi3
.section .ram_code,"ax" //in ram code
.align 2
.global __umodsi3
.code 16
.thumb_func
.type __umodsi3, %function
__umodsi3:
tmov r2, UMOD
tj div
.size __umodsi3, .-__umodsi3
.section .ram_code,"ax" //in ram code
.align 2
.global __udivsi3
.code 16
.thumb_func
.type __udivsi3, %function
__udivsi3:
tmov r2, UDIV
tj div
.size __udivsi3, .-__udivsi3
.section .ram_code,"ax" //in ram code
.align 2
.global div
.code 16
.thumb_func
.type div, %function
div:
tmrcs r3
tpush {r3, r4}
tmov r4, #0x80
tor r3, r4
tmcsr r3
tloadr r3, .L11
tstorer r0, [r3]
tadd r3, r3, #4
tstorer r1, [r3]
tsub r3, r3, #8
tstorerb r2, [r3]
.L2:
tloadrb r0, [r3]
tcmp r0, #0
tjne .L2
tcmp r2, #1
tjls .L4
tadd r3, r3, #8
tloadr r0, [r3]
tj .L6
.L4:
tadd r3, r3, #4
tloadr r0, [r3]
.L6:
tpop {r3, r4}
tmcsr r3
tjex lr
.align 4
.L11:
.word(0x800664)
.word(0x800660)
.word(0x800668)
.size div, .-div
//removed
#if 0
//.section .ram_code,"ax" //in ram code
.align 4
.global mul32x32_64
.thumb_func
.type mul32x32_64, %function
mul32x32_64:
tmul r0, r1
tloadr r1, [pc, #4]
tloadr r1, [r1, #0]
tjex lr
.word(0x008006fc)
#endif
#if 0
//.section .ram_code,"ax" //in ram code
.align 4
.global mz_mul1
.thumb_func
.type mz_mul1, %function
mz_mul1:
tpush {r4, r5, r6, r7}
tmov r4, r8
tpush {r4}
tmov r4, #1
tmov r8, r4 //r8 = 1
tloadr r6, [pc, #4] //r6 REG_ADDR32(0x6fc)
tmovs r5, #0 //clear carry
tj MZ_MUL1_END
.word(0x008006fc)
MZ_MUL1_START:
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r5 // l0 + c => c0
tsubc r5, r5 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r5, r8 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0
taddc r5, r7 // cn = c0 + h1 + c1
MZ_MUL1_END:
tloadm r1!, {r4} // load *a
tsub r2, #1 // r2--
tcmp r2, #0
tjge MZ_MUL1_START // carry set
tstorem r0!, {r5}
tpop {r4}
tmov r8, r4
tpop {r4, r5, r6, r7}
tjex lr
#endif
//.section .ram_code,"ax" //in ram code
.align 4
.global mz_mul2
.thumb_func
.type mz_mul2, %function
mz_mul2:
tpush {r4, r5, r6, r7}
tmov r4, r8
tmov r5, r9
tmov r6, r10
tmov r7, r11
tpush {r4, r5, r6, r7}
tmov r8, r2 //r8 = n, loop number
tmov r2, #1
tmov r10, r2 // r10 = 1
tsub r2, #(MUL2_STEP + 1)
tmov r9, r2 //r9 = -MUL2_STEP
tmov r2, #0
tmov r2, #0
tloadr r6, [pc, #4] //r6 REG_ADDR32(0x6fc)
tmov r11,r2 //r11 = 0
tj MZ_MUL2_LOOP
//tj MZ_MUL2_LOOP2
.word(0x008006fc)
MZ_MUL2_START:
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
///// next 2
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
taddc r2, r7 // cn2 = c2 + h1 + c3
MZ_MUL2_LOOP:
tloadm r1!, {r4, r5} // load *a
tadd r8, r9 // r8 -= MUL2_STEP
tcmp r8, r11 // const 0
tjge MZ_MUL2_START // carry set
tmov r5, r8
tadd r5, #MUL2_STEP
tsub r1, #8
tj MZ_MUL2_LOOP2
MZ_MUL2_START2:
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0
taddc r2, r7 // cn = c0 + h1 + c1
MZ_MUL2_LOOP2:
tloadm r1!, {r4} // load *a
tsub r5, #1 // r7--
tcmp r5, #0
tjge MZ_MUL2_START2 // carry set
MZ_MUL2_END:
//tmov r2, #13
tstorem r0!, {r2}
tpop {r4, r5, r6, r7}
tmov r8, r4
tmov r9, r5
tmov r10, r6
tmov r11, r7
tpop {r4, r5, r6, r7}
tjex lr
tnop
///////// asm crc24 function 2
.section .ram_code,"ax" //in ram code
.align 2
.global blt_packet_crc24_opt
.code 16
.thumb_func
.type blt_packet_crc24_opt, %function
blt_packet_crc24_opt:
tpush {r3, r4, r5, r6, r7, lr}
tmov r5, r8
tpush {r5}
tmov r5, r1
tneg r1, r0
tmov r4, #3
tand r1, r4 //number of byte CRC of pre_process to align CRC to word boundary
tsub r5, r1
tjge CRC24_SAVE_WORD_NUM
tadd r1, r5
tmov r5, #0
CRC24_SAVE_WORD_NUM:
tmov r8, r5 //save to r8
//tloadr r3, CRC24_DAT
tadd r4, r0, #0
tmov r0, #0
tmov r7, #60 //r7 = 15 * 4
CRC24_BYTE_LOOP: //r4: src; r6: dat; r2: crc; r5: tmp
tcmp r0, r1
tjeq CRC24_BYTE_END
tloadrb r6, [r4, r0] //r6 = dat[r0]
txor r6, r2 //r6 = crc ^ dat
tshftl r5, r6, #2 //r5 = r6 << 2
tand r5, r7 //r2 = r2 & 60
tloadr r5, [r5, r3] //load table
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r6, #2 // r6 = r6 >> 2
txor r2, r5 //r2 = r5 ^ r2
tand r6, r7 //r6 = r6 & 60
tloadr r6, [r6, r3]
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tadd r0, #1
txor r2, r6 //r2 = r6 ^ r2
tjne CRC24_BYTE_LOOP
CRC24_BYTE_END:
tmov r1, r8
tcmp r1, #0
tjeq CRC24_END
tmov r5, #0
tmov r8, r5
tadd r4, r0
tmov r0, #0
CRC24_WORD_LOOP:
tsub r1, #4
tjlt CRC24_WORD_END
tloadr r0, [r4, #0] //r0 = dat[r0]
tadd r4, #4
tshftr r6, r0, #0 // r6 = r0 >> 0
CRC24_WORD_nib0:
txor r6, r2 //r6 = crc ^ dat
tshftl r5, r6, #2 //r5 = r6 << 2
tand r5, r7 //r2 = r2 & 60
tloadr r5, [r5, r3] //load table
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r6, #2 // r6 = r6 >> 2
tand r6, r7 //r6 = r6 & 60
tloadr r6, [r6, r3]
txor r2, r5 //r2 = r5 ^ r2
CRC24_WORD_nib1:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r0, #8 //dat >> 8
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib2:
txor r5, r2 //r6 = crc ^ dat
tshftl r6, r5, #2 //r5 << 2
tand r6, r7
tloadr r6, [r6, r3]
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r5, #2
tand r5, r7 //r6 = r6 & 60
tloadr r5, [r5, r3]
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib3:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r0, #16 //dat >> 8
txor r2, r5 //r2 = r6 ^ r2
CRC24_WORD_nib4:
txor r6, r2 //r6 = crc ^ dat
tshftl r5, r6, #2 //r5 = r6 << 2
tand r5, r7 //r2 = r2 & 60
tloadr r5, [r5, r3] //load table
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r6, #2 // r6 = r6 >> 2
tand r6, r7 //r6 = r6 & 60
tloadr r6, [r6, r3]
txor r2, r5 //r2 = r5 ^ r2
CRC24_WORD_nib5:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r0, #24 //dat >> 8
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib6:
txor r5, r2 //r6 = crc ^ dat
tshftl r6, r5, #2 //r5 << 2
tand r6, r7
tloadr r6, [r6, r3]
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r5, #2
tand r5, r7 //r5 = r5 & 60
tloadr r5, [r5, r3]
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib7:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tmov r0, #0
txor r2, r5 //r2 = r6 ^ r2
tj CRC24_WORD_LOOP
CRC24_WORD_END:
tadd r1, #4
tj CRC24_BYTE_LOOP
CRC24_END:
tadd r0, r2, #0
tpop {r5}
tmov r8, r5
tpop {r3, r4, r5, r6, r7, pc}
tnop
// static int Crc24Lookup[16] = {
// 0x0000000,0x01b4c00,0x0369800,0x02dd400,
// 0x06d3000,0x0767c00,0x05ba800,0x040e400,
// 0x0da6000,0x0c12c00,0x0ecf800,0x0f7b400,
// 0x0b75000,0x0ac1c00,0x081c800,0x09a8400,
// };
// //usage
// //crc = blt_packet_crc24_opt (dat, length, crc_init, Crc24Lookup);
|
Ai-Thinker-Open/Telink_825X_SDK
| 10,402
|
example/bootloader/bootloader.S
|
/********************************************************************************************************
* @file 8258_cstartup_RET_16K.S
*
* @brief This is the boot file for TLSR8258
*
* @author public@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#ifdef MCU_BOOT_8258_RET_16K
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ramcode_size_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
@ .word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
@ .word (0x00880000 + _ram_use_size_div_16_)
.word (0x00880000 + 0x800)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
@********************************************************************************************************
@ UART BOOTLOADER IF PC5 IS LOW , ENTER UART BOOT
@********************************************************************************************************
tj UART_BOOT_END
.org 0x60
UART_BOOT_START:
tloadr r1, UART_BOOT_DATA @ Source addr
tloadr r2, UART_BOOT_DATA + 4 @ Direct addr
tloadr r3, UART_BOOT_DATA + 8 @ Direct addr + Len
BOOT_COPY:
tcmp r2, r3
tjge BOOT_COPY_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj BOOT_COPY
BOOT_COPY_END:
tloadr r1, UART_BOOT_DATA + 12 @ Source addr
tloadr r2, UART_BOOT_DATA + 16 @ Direct addr
tloadr r3, UART_BOOT_DATA + 20 @ Direct addr + Len
tloadr r4, UART_BOOT_DATA + 24 @ reboot addr
tjl _boot_copy_start_
.org 0x80
USER_COPY:
tcmp r2, r3
tjge USER_COPY_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj USER_COPY
USER_COPY_END:
tmov r1,#0x88
tstorerb r1,[r4,#0] @reboot from RAM
.align 4
UART_BOOT_DATA:
.word 0x80
.word 0x849FE0
.word 0x84A000
.word 0x02C000
.word 0x840000
.word 0x844000
.word 0x800602
UART_BOOT_END:
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
@********************************************************************************************************
@ FILL .DATA AND .BSS WITH 0xFF
@********************************************************************************************************
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
@********************************************************************************************************
@ UPDATE SP UNDER IRQ/SVC MODE
@********************************************************************************************************
tloadr r0, DAT0 @r0 = 0x12 IRQ
tmcsr r0 @CPSR=r0
tloadr r0, DAT0 + 8 @r0 = irq_stk + IRQ_STK_SIZE
tmov r13, r0 @r13/SP= r0 update SP under IRQ mode
tloadr r0, DAT0 + 4 @r0 = 0x13 SVC
tmcsr r0 @CPSR=r0
tloadr r0, DAT0 + 12 @r0 = 0x84c000
tmov r13, r0 @r13= r0 update SP under SVC mode
@********************************************************************************************************
@ .BSS INITIALIZATION FOR 0
@********************************************************************************************************
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
@********************************************************************************************************
@ IC TAG INITIALIZATION
@********************************************************************************************************
ZERO_TAG:
tmov r0, #0
tloadr r1, DAT0 + 28 @r1 = _ictag_start_
tloadr r2, DAT0 + 32 @r2 = _ictag_end_
ZERO_TAG_BEGIN:
tcmp r1, r2
tjge ZERO_TAG_END @r1>=r2 jump to ZERO_TAG_END
tstorer r0, [r1, #0] @*(unsigned int*)(_ictag_start_)=r0=0
tadd r1, #4 @r1 = r1 + 4
tj ZERO_TAG_BEGIN @jump to ZERO_TAG_BEGIN
ZERO_TAG_END:
@********************************************************************************************************
@ IC CACHE INITIALIZATION
@********************************************************************************************************
SETIC:
tloadr r1, DAT0 + 24 @ r1 = 0x80060c
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0] @*(unsigned int*)(0x80060c) = r0
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1] @ *(unsigned int*)(0x80060d) = r0
@tmov r0, #0;
@tstorerb r0, [r1, #2]
@********************************************************************************************************
@ DATA SECTION LOAD
@********************************************************************************************************
tloadr r1, DATA_I @ r1 = _dstored_
tloadr r2, DATA_I+4 @ r2 = _start_data_
tloadr r3, DATA_I+8 @ r3 = _end_data_
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END @ r2>=r3 jump to COPY_DATA_END
tloadr r0, [r1, #0] @ r0 = *(unsigned int*)(_dstored_)
tstorer r0, [r2, #0] @ *(unsigned int*)(_start_data_) = r0
tadd r1, #4 @ r1 = r1 + 4
tadd r2, #4 @ r2 = r2 + 4
tj COPY_DATA @ jump to COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @ 0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @ 3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x850000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word (0x84A000) @28
.word (0x84A100) @32
.word (0xA0) @36
@ .word _ictag_start_ @28 @ IC tag start
@ .word _ictag_end_ @32 @ IC tag end
@ .word _ramcode_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff
.word (_start_data_)
@.word (0x850000)
.word (_start_data_ + 32)
.word (_retention_data_start_) @16
.word (_retention_data_end_) @20
.word (_rstored_) @24
.word (_ram_use_size_div_16_)
DEBUG_GPIO:
.word (0x00800580) @ PAx oen
.word (0x008000b8) @ ANA REG
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
@tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-08
| 7,983
|
platform/system/startup_cm4.S
|
.syntax unified
.cpu cortex-m4
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl system_init
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word SEC_IRQHandler
.word RTC_IRQHandler
.word WDG_IRQHandler
.word EFC_IRQHandler
.word UART3_IRQHandler
.word I2C2_IRQHandler
.word UART0_IRQHandler
.word UART1_IRQHandler
.word UART2_IRQHandler
.word LPUART_IRQHandler
.word SSP0_IRQHandler
.word SSP1_IRQHandler
.word QSPI_IRQHandler
.word I2C0_IRQHandler
.word I2C1_IRQHandler
.word SCC_IRQHandler
.word ADC_IRQHandler
.word AFEC_IRQHandler
.word SSP2_IRQHandler
.word DMA1_IRQHandler
.word DAC_IRQHandler
.word LORA_IRQHandler
.word GPIO_IRQHandler
.word TIMER0_IRQHandler
.word TIMER1_IRQHandler
.word TIMER2_IRQHandler
.word TIMER3_IRQHandler
.word BSTIMER0_IRQHandler
.word BSTIMER1_IRQHandler
.word LPTIMER0_IRQHandler
.word SAC_IRQHandler
.word DMA0_IRQHandler
.word I2S_IRQHandler
.word LCD_IRQHandler
.word PWR_IRQHandler
.word LPTIMER1_IRQHandler
.word IWDG_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak SEC_IRQHandler
.thumb_set SEC_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak WDG_IRQHandler
.thumb_set WDG_IRQHandler,Default_Handler
.weak EFC_IRQHandler
.thumb_set EFC_IRQHandler,Default_Handler
.weak UART3_IRQHandler
.thumb_set UART3_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak UART0_IRQHandler
.thumb_set UART0_IRQHandler,Default_Handler
.weak UART1_IRQHandler
.thumb_set UART1_IRQHandler,Default_Handler
.weak UART2_IRQHandler
.thumb_set UART2_IRQHandler,Default_Handler
.weak LPUART_IRQHandler
.thumb_set LPUART_IRQHandler,Default_Handler
.weak SSP0_IRQHandler
.thumb_set SSP0_IRQHandler,Default_Handler
.weak SSP1_IRQHandler
.thumb_set SSP1_IRQHandler,Default_Handler
.weak QSPI_IRQHandler
.thumb_set QSPI_IRQHandler,Default_Handler
.weak I2C0_IRQHandler
.thumb_set I2C0_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak SCC_IRQHandler
.thumb_set SCC_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak AFEC_IRQHandler
.thumb_set AFEC_IRQHandler,Default_Handler
.weak SSP2_IRQHandler
.thumb_set SSP2_IRQHandler,Default_Handler
.weak DMA1_IRQHandler
.thumb_set DMA1_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak LORA_IRQHandler
.thumb_set LORA_IRQHandler,Default_Handler
.weak GPIO_IRQHandler
.thumb_set GPIO_IRQHandler,Default_Handler
.weak TIMER0_IRQHandler
.thumb_set TIMER0_IRQHandler,Default_Handler
.weak TIMER1_IRQHandler
.thumb_set TIMER1_IRQHandler,Default_Handler
.weak TIMER2_IRQHandler
.thumb_set TIMER2_IRQHandler,Default_Handler
.weak TIMER3_IRQHandler
.thumb_set TIMER3_IRQHandler,Default_Handler
.weak BSTIMER0_IRQHandler
.thumb_set BSTIMER0_IRQHandler,Default_Handler
.weak BSTIMER1_IRQHandler
.thumb_set BSTIMER1_IRQHandler,Default_Handler
.weak LPTIMER0_IRQHandler
.thumb_set LPTIMER0_IRQHandler,Default_Handler
.weak SAC_IRQHandler
.thumb_set SAC_IRQHandler,Default_Handler
.weak DMA0_IRQHandler
.thumb_set DMA0_IRQHandler,Default_Handler
.weak I2S_IRQHandler
.thumb_set I2S_IRQHandler,Default_Handler
.weak LCD_IRQHandler
.thumb_set LCD_IRQHandler,Default_Handler
.weak PWR_IRQHandler
.thumb_set PWR_IRQHandler,Default_Handler
.weak LPTIMER1_IRQHandler
.thumb_set LPTIMER1_IRQHandler,Default_Handler
.weak IWDG_IRQHandler
.thumb_set IWDG_IRQHandler,Default_Handler
/*****************END OF FILE*********************/
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-08
| 8,442
|
projects/ASR6601CB-EVAL/examples/flash/wordline_program/src/startup_cm4.S
|
.syntax unified
.cpu cortex-m4
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the initialization values of the .func section.
defined in linker script */
.word _sifunc
/* start address for the .func section. defined in linker script */
.word _sfunc
/* end address for the .func section. defined in linker script */
.word _efunc
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
movs r1, #0
b LoopCopyFuncInit
CopyFuncInit:
ldr r3, =_sifunc
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyFuncInit:
ldr r0, =_sfunc
ldr r3, =_efunc
adds r2, r0, r1
cmp r2, r3
bcc CopyFuncInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl system_init
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word SEC_IRQHandler
.word RTC_IRQHandler
.word WDG_IRQHandler
.word EFC_IRQHandler
.word UART3_IRQHandler
.word I2C2_IRQHandler
.word UART0_IRQHandler
.word UART1_IRQHandler
.word UART2_IRQHandler
.word LPUART_IRQHandler
.word SSP0_IRQHandler
.word SSP1_IRQHandler
.word QSPI_IRQHandler
.word I2C0_IRQHandler
.word I2C1_IRQHandler
.word SCC_IRQHandler
.word ADC_IRQHandler
.word AFEC_IRQHandler
.word SSP2_IRQHandler
.word DMA1_IRQHandler
.word DAC_IRQHandler
.word LORA_IRQHandler
.word GPIO_IRQHandler
.word TIMER0_IRQHandler
.word TIMER1_IRQHandler
.word TIMER2_IRQHandler
.word TIMER3_IRQHandler
.word BSTIMER0_IRQHandler
.word BSTIMER1_IRQHandler
.word LPTIMER0_IRQHandler
.word SAC_IRQHandler
.word DMA0_IRQHandler
.word I2S_IRQHandler
.word LCD_IRQHandler
.word PWR_IRQHandler
.word LPTIMER1_IRQHandler
.word IWDG_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak SEC_IRQHandler
.thumb_set SEC_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak WDG_IRQHandler
.thumb_set WDG_IRQHandler,Default_Handler
.weak EFC_IRQHandler
.thumb_set EFC_IRQHandler,Default_Handler
.weak UART3_IRQHandler
.thumb_set UART3_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak UART0_IRQHandler
.thumb_set UART0_IRQHandler,Default_Handler
.weak UART1_IRQHandler
.thumb_set UART1_IRQHandler,Default_Handler
.weak UART2_IRQHandler
.thumb_set UART2_IRQHandler,Default_Handler
.weak LPUART_IRQHandler
.thumb_set LPUART_IRQHandler,Default_Handler
.weak SSP0_IRQHandler
.thumb_set SSP0_IRQHandler,Default_Handler
.weak SSP1_IRQHandler
.thumb_set SSP1_IRQHandler,Default_Handler
.weak QSPI_IRQHandler
.thumb_set QSPI_IRQHandler,Default_Handler
.weak I2C0_IRQHandler
.thumb_set I2C0_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak SCC_IRQHandler
.thumb_set SCC_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak AFEC_IRQHandler
.thumb_set AFEC_IRQHandler,Default_Handler
.weak SSP2_IRQHandler
.thumb_set SSP2_IRQHandler,Default_Handler
.weak DMA1_IRQHandler
.thumb_set DMA1_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak LORA_IRQHandler
.thumb_set LORA_IRQHandler,Default_Handler
.weak GPIO_IRQHandler
.thumb_set GPIO_IRQHandler,Default_Handler
.weak TIMER0_IRQHandler
.thumb_set TIMER0_IRQHandler,Default_Handler
.weak TIMER1_IRQHandler
.thumb_set TIMER1_IRQHandler,Default_Handler
.weak TIMER2_IRQHandler
.thumb_set TIMER2_IRQHandler,Default_Handler
.weak TIMER3_IRQHandler
.thumb_set TIMER3_IRQHandler,Default_Handler
.weak BSTIMER0_IRQHandler
.thumb_set BSTIMER0_IRQHandler,Default_Handler
.weak BSTIMER1_IRQHandler
.thumb_set BSTIMER1_IRQHandler,Default_Handler
.weak LPTIMER0_IRQHandler
.thumb_set LPTIMER0_IRQHandler,Default_Handler
.weak SAC_IRQHandler
.thumb_set SAC_IRQHandler,Default_Handler
.weak DMA0_IRQHandler
.thumb_set DMA0_IRQHandler,Default_Handler
.weak I2S_IRQHandler
.thumb_set I2S_IRQHandler,Default_Handler
.weak LCD_IRQHandler
.thumb_set LCD_IRQHandler,Default_Handler
.weak PWR_IRQHandler
.thumb_set PWR_IRQHandler,Default_Handler
.weak LPTIMER1_IRQHandler
.thumb_set LPTIMER1_IRQHandler,Default_Handler
.weak IWDG_IRQHandler
.thumb_set IWDG_IRQHandler,Default_Handler
/*****************END OF FILE*********************/
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 10,584
|
SDK_3.1.5/div_mod.S
|
/********************************************************************************************************
* @file div_mod.S
*
* @brief This is the assembly file for TLSR8258
*
* @author author@telink-semi.com;
* @date May 8, 2018
*
* @par Copyright (c) 2018, Telink Semiconductor (Shanghai) Co., Ltd.
* All rights reserved.
*
* The information contained herein is confidential property of Telink
* Semiconductor (Shanghai) Co., Ltd. and is available under the terms
* of Commercial License Agreement between Telink Semiconductor (Shanghai)
* Co., Ltd. and the licensee or the terms described here-in. This heading
* MUST NOT be removed from this file.
*
* Licensees are granted free, non-transferable use of the information in this
* file under Mutual Non-Disclosure Agreement. NO WARRENTY of ANY KIND is provided.
*
*******************************************************************************************************/
#define UDIV #0
#define SDIV #1
#define UMOD #2
#define SMOD #3
#define MUL2_STEP 8
.code 16
.text
.align 2
.global __modsi3
.code 16
.thumb_func
.type __modsi3, %function
__modsi3:
tmov r2, SMOD
tj div
.size __modsi3, .-__modsi3
.align 2
.global __divsi3
.code 16
.thumb_func
.type __divsi3, %function
__divsi3:
tmov r2, SDIV
tj div
.size __divsi3, .-__divsi3
.align 2
.global __umodsi3
.code 16
.thumb_func
.type __umodsi3, %function
__umodsi3:
tmov r2, UMOD
tj div
.size __umodsi3, .-__umodsi3
.align 2
.global __udivsi3
.code 16
.thumb_func
.type __udivsi3, %function
__udivsi3:
tmov r2, UDIV
tj div
.size __udivsi3, .-__udivsi3
.align 2
.global div
.code 16
.thumb_func
.type div, %function
div:
tmrcs r3
tpush {r3, r4}
tmov r4, #0x80
tor r3, r4
tmcsr r3
tloadr r3, .L11
tstorer r0, [r3]
tadd r3, r3, #4
tstorer r1, [r3]
tsub r3, r3, #8
tstorerb r2, [r3]
.L2:
tloadrb r0, [r3]
tcmp r0, #0
tjne .L2
tcmp r2, #1
tjls .L4
tadd r3, r3, #8
tloadr r0, [r3]
tj .L6
.L4:
tadd r3, r3, #4
tloadr r0, [r3]
.L6:
tpop {r3, r4}
tmcsr r3
tjex lr
.align 4
.L11:
.word(0x800664)
.word(0x800660)
.word(0x800668)
.size div, .-div
#if 1
.align 4
.global mul32x32_64
.thumb_func
.type mul32x32_64, %function
mul32x32_64:
tmul r0, r1
tloadr r1, [pc, #4]
tloadr r1, [r1, #0]
tjex lr
.word(0x008006fc)
#endif
#if 1
.align 4
.global mz_mul1
.thumb_func
.type mz_mul1, %function
mz_mul1:
tpush {r4, r5, r6, r7}
tmov r4, r8
tpush {r4}
tmov r4, #1
tmov r8, r4 //r8 = 1
tloadr r6, [pc, #4] //r6 REG_ADDR32(0x6fc)
tmovs r5, #0 //clear carry
tj MZ_MUL1_END
.word(0x008006fc)
MZ_MUL1_START:
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r5 // l0 + c => c0
tsubc r5, r5 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r5, r8 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0
taddc r5, r7 // cn = c0 + h1 + c1
MZ_MUL1_END:
tloadm r1!, {r4} // load *a
tsub r2, #1 // r2--
tcmp r2, #0
tjge MZ_MUL1_START // carry set
tstorem r0!, {r5}
tpop {r4}
tmov r8, r4
tpop {r4, r5, r6, r7}
tjex lr
#endif
.align 4
.global mz_mul2
.thumb_func
.type mz_mul2, %function
mz_mul2:
tpush {r4, r5, r6, r7}
tmov r4, r8
tmov r5, r9
tmov r6, r10
tmov r7, r11
tpush {r4, r5, r6, r7}
tmov r8, r2 //r8 = n, loop number
tmov r2, #1
tmov r10, r2 // r10 = 1
tsub r2, #(MUL2_STEP + 1)
tmov r9, r2 //r9 = -MUL2_STEP
tmov r2, #0
tmov r2, #0
tloadr r6, [pc, #4] //r6 REG_ADDR32(0x6fc)
tmov r11,r2 //r11 = 0
tj MZ_MUL2_LOOP
//tj MZ_MUL2_LOOP2
.word(0x008006fc)
MZ_MUL2_START:
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
///// next 2
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
taddc r2, r7 // cn2 = c2 + h1 + c3
MZ_MUL2_LOOP:
tloadm r1!, {r4, r5} // load *a
tadd r8, r9 // r8 -= MUL2_STEP
tcmp r8, r11 // const 0
tjge MZ_MUL2_START // carry set
tmov r5, r8
tadd r5, #MUL2_STEP
tsub r1, #8
tj MZ_MUL2_LOOP2
MZ_MUL2_START2:
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0
taddc r2, r7 // cn = c0 + h1 + c1
MZ_MUL2_LOOP2:
tloadm r1!, {r4} // load *a
tsub r5, #1 // r7--
tcmp r5, #0
tjge MZ_MUL2_START2 // carry set
MZ_MUL2_END:
//tmov r2, #13
tstorem r0!, {r2}
tpop {r4, r5, r6, r7}
tmov r8, r4
tmov r9, r5
tmov r10, r6
tmov r11, r7
tpop {r4, r5, r6, r7}
tjex lr
tnop
///////// asm crc24 function 2
.section .ram_code,"ax" //in ram code
.align 2
.global blt_packet_crc24_opt
.code 16
.thumb_func
.type blt_packet_crc24_opt, %function
blt_packet_crc24_opt:
tpush {r3, r4, r5, r6, r7, lr}
tmov r5, r8
tpush {r5}
tmov r5, r1
tneg r1, r0
tmov r4, #3
tand r1, r4 //number of byte CRC of pre_process to align CRC to word boundary
tsub r5, r1
tjge CRC24_SAVE_WORD_NUM
tadd r1, r5
tmov r5, #0
CRC24_SAVE_WORD_NUM:
tmov r8, r5 //save to r8
//tloadr r3, CRC24_DAT
tadd r4, r0, #0
tmov r0, #0
tmov r7, #60 //r7 = 15 * 4
CRC24_BYTE_LOOP: //r4: src; r6: dat; r2: crc; r5: tmp
tcmp r0, r1
tjeq CRC24_BYTE_END
tloadrb r6, [r4, r0] //r6 = dat[r0]
txor r6, r2 //r6 = crc ^ dat
tshftl r5, r6, #2 //r5 = r6 << 2
tand r5, r7 //r2 = r2 & 60
tloadr r5, [r5, r3] //load table
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r6, #2 // r6 = r6 >> 2
txor r2, r5 //r2 = r5 ^ r2
tand r6, r7 //r6 = r6 & 60
tloadr r6, [r6, r3]
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tadd r0, #1
txor r2, r6 //r2 = r6 ^ r2
tjne CRC24_BYTE_LOOP
CRC24_BYTE_END:
tmov r1, r8
tcmp r1, #0
tjeq CRC24_END
tmov r5, #0
tmov r8, r5
tadd r4, r0
tmov r0, #0
CRC24_WORD_LOOP:
tsub r1, #4
tjlt CRC24_WORD_END
tloadr r0, [r4, #0] //r0 = dat[r0]
tadd r4, #4
tshftr r6, r0, #0 // r6 = r0 >> 0
CRC24_WORD_nib0:
txor r6, r2 //r6 = crc ^ dat
tshftl r5, r6, #2 //r5 = r6 << 2
tand r5, r7 //r2 = r2 & 60
tloadr r5, [r5, r3] //load table
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r6, #2 // r6 = r6 >> 2
tand r6, r7 //r6 = r6 & 60
tloadr r6, [r6, r3]
txor r2, r5 //r2 = r5 ^ r2
CRC24_WORD_nib1:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r0, #8 //dat >> 8
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib2:
txor r5, r2 //r6 = crc ^ dat
tshftl r6, r5, #2 //r5 << 2
tand r6, r7
tloadr r6, [r6, r3]
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r5, #2
tand r5, r7 //r6 = r6 & 60
tloadr r5, [r5, r3]
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib3:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r0, #16 //dat >> 8
txor r2, r5 //r2 = r6 ^ r2
CRC24_WORD_nib4:
txor r6, r2 //r6 = crc ^ dat
tshftl r5, r6, #2 //r5 = r6 << 2
tand r5, r7 //r2 = r2 & 60
tloadr r5, [r5, r3] //load table
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r6, r6, #2 // r6 = r6 >> 2
tand r6, r7 //r6 = r6 & 60
tloadr r6, [r6, r3]
txor r2, r5 //r2 = r5 ^ r2
CRC24_WORD_nib5:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r0, #24 //dat >> 8
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib6:
txor r5, r2 //r6 = crc ^ dat
tshftl r6, r5, #2 //r5 << 2
tand r6, r7
tloadr r6, [r6, r3]
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tshftr r5, r5, #2
tand r5, r7 //r5 = r5 & 60
tloadr r5, [r5, r3]
txor r2, r6 //r2 = r6 ^ r2
CRC24_WORD_nib7:
tasr r2, r2, #4 //r2 >> 4 (crc >> 4)
tmov r0, #0
txor r2, r5 //r2 = r6 ^ r2
tj CRC24_WORD_LOOP
CRC24_WORD_END:
tadd r1, #4
tj CRC24_BYTE_LOOP
CRC24_END:
tadd r0, r2, #0
tpop {r5}
tmov r8, r5
tpop {r3, r4, r5, r6, r7, pc}
tnop
// static int Crc24Lookup[16] = {
// 0x0000000,0x01b4c00,0x0369800,0x02dd400,
// 0x06d3000,0x0767c00,0x05ba800,0x040e400,
// 0x0da6000,0x0c12c00,0x0ecf800,0x0f7b400,
// 0x0b75000,0x0ac1c00,0x081c800,0x09a8400,
// };
// //usage
// //crc = blt_packet_crc24_opt (dat, length, crc_init, Crc24Lookup);
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 5,669
|
SDK_3.1.5/boot/8258/cstartup_8258.S
|
#ifdef MCU_STARTUP_8258
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
#ifndef __IRQ_STK_SIZE__
#define __IRQ_STK_SIZE__ 0x180
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ramcode_size_div_16_align_256_)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x850000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word _ictag_start_ @28 @ IC tag start
.word _ictag_end_ @32 @ IC tag end
.word _ramcode_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff
.word (_start_data_)
@.word (0x850000)
.word (_start_data_ + 32)
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 5,939
|
SDK_3.1.5/boot/8258/cstartup_8258_RET_32K.S
|
#ifdef MCU_STARTUP_8258_RET_32K
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ramcode_size_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ram_use_size_div_16_)
@ .word (0x00880000 + 0x800)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
SET_BOOT:
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
SET_BOOT_END:
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x850000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word (0x848000) @28
.word (0x848100) @32
.word (0x80) @36
@ .word _ictag_start_ @28 @ IC tag start
@ .word _ictag_end_ @32 @ IC tag end
@ .word _ramcode_size_div_256_ @36
DATA_I:
.word _dstored_ @0
.word _start_data_ @4
.word _end_data_ @8
FLL_D:
.word 0xffffffff
.word (_start_data_)
@.word (0x850000)
.word (_start_data_ + 32)
.word (_retention_data_start_) @16
.word (_retention_data_end_) @20
.word (_rstored_) @24
.word (_ram_use_size_div_16_)
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 9,166
|
SDK_3.1.5/boot/8258/cstartup_8258_RET_16K.S
|
#ifdef MCU_STARTUP_8258_RET_16K
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
#ifdef __PROJECT_MESH_GW_NODE_HK__
.equ IRQ_STK_SIZE, 0x400
#else
.equ IRQ_STK_SIZE, 0x180
#endif
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
.equ __RAM_START_ADDR, (0x840000)
.equ __RAM_SIZE_MAX, (64*1024)
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
.global __RAM_START_ADDR
.global __RAM_SIZE_MAX
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ramcode_size_align_256_
.extern _ictag_start_
.extern _ictag_end_
.extern _code_size_div_256_
.extern _ramcode_size_div_256_compile_
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
#if (MCU_RUN_SRAM_EN || MCU_RUN_SRAM_WITH_CACHE_EN)
.word (0x00880000 + _bin_size_div_16_)
#else
.word (0x00880000 + _ramcode_size_div_16_align_256_) @must align 256, because of ic tag is 256 aligned
@ .word (0x00880000 + 0x400)
#endif
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
.align 4
.global start_suspend
.thumb_func
.type start_suspend, %function
start_suspend:
tpush {r2-r3}
tmovs r2, #129 @0x81
tloadr r3, __suspend_data @0x80006f
tstorerb r2, [r3, #0] @*(volatile unsigned char *)0x80006f = 0x81
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tmov r8, r8
tpop {r2-r3}
tjex lr
__suspend_data:
.word (0x80006f)
__reset:
#if 0
@ add debug, PB4 output 1
tloadr r1, DEBUG_GPIO @0x80058a PB oen
tmov r0, #139 @0b 11101111
tstorerb r0, [r1, #0]
tmov r0, #16 @0b 00010000
tstorerb r0, [r1, #1] @0x800583 PB output
#endif
@send flash cmd 0xab to wakeup flash;
FLASH_WAKEUP_BEGIN:
tloadr r0,FLASH_RECOVER + 0
tmov r1,#0
tstorerb r1,[r0,#1]
tmov r1,#171 @Flash deep cmd: 0xAB
tstorerb r1,[r0,#0]
tmov r2,#0
tmov r3,#6
TNOP:
tadd r2,#1
tcmp r2,r3
tjle TNOP
tmov r1,#1
tstorerb r1,[r0,#1]
FLASH_WAKEUP_END:
#if __PROJECT_BOOTLOADER__
@ bootloader copy code mode
tloadr r1, COPY_CODE_I
tloadr r2, COPY_CODE_I+4
tloadr r3, COPY_CODE_I+8
COPY_CODE:
tcmp r2, r3
tjge COPY_CODE_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_CODE
COPY_CODE_END:
#endif
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
SETIC:
tloadr r1, DAT0 + 24
#if (MCU_RUN_SRAM_EN)
tmov r0, #255;
tstorerb r0, [r1, #0]
tstorerb r0, [r1, #1]
#else
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tmov r0, #0
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG: @no need init tag when wake up from deep retention, because tag is in retention too
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
#endif
SET_BOOT: @because no load ramcode when boot from retention, so must set boot area manually.
tmov r2, #4
tloadrb r1, [r2] @read form core_840004
tmov r0, #165 @A5
tcmp r0, r1
tjne SET_BOOT_END @power up
tmov r2, #5
tloadrb r1, [r2] @read form core_840005
tloadr r0, BOOT_SEL_D
tstorerb r1, [r0, #0]
tj COPY_DATA_END @wake up from retention deep
SET_BOOT_END:
#if RUN_254K_IN_20000_EN // run 254K in 0x20000, default disable to save RAM.
tloadr r0, BOOT_SEL_D
tloadrb r1, [r0, #0]
tcmp r1, #125
tjne SET_OFFSET_END
tmovs r1, #253
tstorerb r1, [r0, #0]
SET_OFFSET_END:
#endif
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
@always load data or zero here
tmov r0, #0
tloadr r1, NO_RET_BSS_I + 0
tloadr r2, NO_RET_BSS_I + 4
ZERO_NO_RET_BSS:
tcmp r1, r2
tjge ZERO_NO_RET_BSS_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_NO_RET_BSS
ZERO_NO_RET_BSS_END:
#if 1 // (_dstored_ + (_end_data_ - _start_data_))
tloadr r1, DATA_I+0
tloadr r2, DATA_I+8
tadd r1, r1, r2
tloadr r2, DATA_I+4
tsub r1, r1, r2
#endif
tloadr r2, NO_RET_DATA_I+0
tloadr r3, NO_RET_DATA_I+4
COPY_NO_RET_DATA:
tcmp r2, r3
tjge COPY_NO_RET_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_NO_RET_DATA
COPY_NO_RET_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (__RAM_START_ADDR + __RAM_SIZE_MAX) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
#if 0
.word (0x840000 + __RETENTION_SIZE_DIV_256*0x100) @28. if tag is not in retention ram, must zero tag always.
.word (0x840100 + __RETENTION_SIZE_DIV_256*0x100) @32
.word (__RETENTION_SIZE_DIV_256) @36
#else
.word _ictag_start_ @28
.word _ictag_end_ @32
.word _ramcode_size_div_256_ @36 @ IC tag u8 value
#endif
BOOT_LINK_NEED:
.word _code_size_div_256_ @ exclude data
.word _ramcode_size_div_256_compile_
DATA_I:
#if __PROJECT_BOOTLOADER__
.word _dstored_bin_ @0
#else
.word _dstored_ @0
#endif
.word _start_data_ @4
.word _end_data_ @8
NO_RET_DATA_I:
.word (_no_retention_data_start_) @0
.word (_no_retention_data_end_) @4
NO_RET_BSS_I:
.word (_no_retention_bss_start_) @0
.word (_no_retention_bss_end_) @4
#if __PROJECT_BOOTLOADER__
COPY_CODE_I:
.word (__RAM_START_ADDR + _vector_end_)
.word (__RAM_START_ADDR + _ram_code_start_)
.word (__RAM_START_ADDR + _bootloader_ram_code_end_)
#endif
FLL_D:
.word 0xffffffff
#if 0 // org
.word (_start_data_)
@.word (__RAM_START_ADDR + __RAM_SIZE_MAX)
.word (_start_data_ + 32)
#else
.word (__RAM_START_ADDR + __RAM_SIZE_MAX - 3*1024) @just clear 3k to decrease time. @(_end_bss_)
.word (__RAM_START_ADDR + __RAM_SIZE_MAX)
#endif
.word (_rstored_) @24 // not use with FLL_D, just extern.
@.word (_ram_use_size_div_16_) // not use with FLL_D, just extern.
DEBUG_GPIO:
.word (0x80058a) @ PBx oen
BOOT_SEL_D:
.word (0x80063e)
FLASH_RECOVER:
.word (0x80000c) @0
.word _ram_code_start_ @ without this, compile would be error:"nonconstant expression for load base" when there is not text section.
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 3,726
|
SDK_3.1.5/proj/mcu_spec/cstartup_8266_ram.S
|
#ifdef MCU_CORE_8266_RAM
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x100
.equ __LOAD_RAM, 0x2f
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880300)
.org 0x10
tj __irq
.org 0x18
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
__reset:
@ tloadr r0, DAT0 + 36
@ tmov r1, #1024 @ set sws to GPIO
@ tstorer r1, [r0, #0]
@ tloadr r0, DAT0 + 40 @**** enable watchdog at the very first time
@ tloadr r1, DAT0 + 44
@ tstorer r1, [r0, #0]
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
SETIC:
tloadr r1, DAT0 + 24
tmov r0, #64; @ IC tag start
tstorerb r0, [r1, #0]
tmov r0, #64; @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x80c000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word (0x808000 + __LOAD_RAM * 0x100) @28 @ IC tag start
.word (0x808000 + (__LOAD_RAM + 1) * 0x100) @32 @ IC tag end
@ .word (0x80058c) @36 gpio
@ .word (0x800620) @40 watchdog
@ .word (0x802c01) @44 watchdog
DATA_I:
.word _dstored_
.word _start_data_
.word _end_data_
FLL_D:
.word 0x0
.word (_start_data_)
.word (0x80c000)
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 3,726
|
SDK_3.1.5/proj/mcu_spec/cstartup_8263_ram.S
|
#ifdef MCU_CORE_8263_RAM
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x100
.equ __LOAD_RAM, 0x09
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880100)
.org 0x10
tj __irq
.org 0x18
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
__reset:
@ tloadr r0, DAT0 + 36
@ tmov r1, #1024 @ set sws to GPIO
@ tstorer r1, [r0, #0]
@ tloadr r0, DAT0 + 40 @**** enable watchdog at the very first time
@ tloadr r1, DAT0 + 44
@ tstorer r1, [r0, #0]
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
SETIC:
tloadr r1, DAT0 + 24
tmov r0, #64; @ IC tag start
tstorerb r0, [r1, #0]
tmov r0, #64; @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x809800) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word (0x808000 + __LOAD_RAM * 0x100) @28 @ IC tag start
.word (0x808000 + (__LOAD_RAM + 1) * 0x100) @32 @ IC tag end
@ .word (0x80058c) @36 gpio
@ .word (0x800620) @40 watchdog
@ .word (0x802c01) @44 watchdog
DATA_I:
.word _dstored_
.word _start_data_
.word _end_data_
FLL_D:
.word 0x0
.word (_start_data_)
.word (0x809800)
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 5,015
|
SDK_3.1.5/proj/mcu_spec/cstartup_8269.S
|
#ifdef MCU_STARTUP_8269 // it's define in eclipse configuration.
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
#ifndef __IRQ_STK_SIZE__
#define __IRQ_STK_SIZE__ 0x180
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
.equ __RAM_START_ADDR, (0x808000)
.equ __RAM_SIZE_MAX, (32*1024)
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
.global __RAM_START_ADDR
.global __RAM_SIZE_MAX
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ictag_start_
.extern _ictag_end_
.extern _code_size_div_256_
.extern _ramcode_size_div_256_compile_
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ramcode_size_div_16_align_256_)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
__reset:
@ tloadr r0, DAT0 + 36
@ tmov r1, #1024 @ set sws to GPIO
@ tstorer r1, [r0, #0]
@ tloadr r0, DAT0 + 40 @**** enable watchdog at the very first time
@ tloadr r1, DAT0 + 44
@ tstorer r1, [r0, #0]
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (__RAM_START_ADDR + __RAM_SIZE_MAX) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word _ictag_start_ @28 @ IC tag start
.word _ictag_end_ @32 @ IC tag end
.word _ramcode_size_div_256_ @36
@ .word (0x808000 + __LOAD_RAM * 0x100) @28 @ IC tag start
@ .word (0x808000 + (__LOAD_RAM + 1) * 0x100) @32 @ IC tag end
@ .word (0x80000e) @36
@ .word (0x80058c) @36 gpio
@ .word (0x800620) @40 watchdog
@ .word (0x802c01) @44 watchdog
BOOT_LINK_NEED:
.word _code_size_div_256_ @ exclude data
.word _ramcode_size_div_256_compile_
DATA_I:
.word _dstored_
.word _start_data_
.word _end_data_
FLL_D:
.word 0xffffffff
.word (_start_data_)
.word (__RAM_START_ADDR + __RAM_SIZE_MAX)
.word (_rstored_)
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 4,897
|
SDK_3.1.5/proj/mcu_spec/cstartup_8267.S
|
#ifdef MCU_STARTUP_8267
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
.equ __RAM_START_ADDR, (0x808000)
.equ __RAM_SIZE_MAX, (16*1024)
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
.global __RAM_START_ADDR
.global __RAM_SIZE_MAX
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ictag_start_
.extern _ictag_end_
.extern _code_size_div_256_
.extern _ramcode_size_div_256_compile_
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ramcode_size_div_16_align_256_)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
__reset:
@ tloadr r0, DAT0 + 36
@ tmov r1, #1024 @ set sws to GPIO
@ tstorer r1, [r0, #0]
@ tloadr r0, DAT0 + 40 @**** enable watchdog at the very first time
@ tloadr r1, DAT0 + 44
@ tstorer r1, [r0, #0]
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (__RAM_START_ADDR + __RAM_SIZE_MAX) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word _ictag_start_ @28 @ IC tag start
.word _ictag_end_ @32 @ IC tag end
.word _ramcode_size_div_256_ @36
@ .word (0x808000 + __LOAD_RAM * 0x100) @28 @ IC tag start
@ .word (0x808000 + (__LOAD_RAM + 1) * 0x100) @32 @ IC tag end
@ .word (0x80000e) @36
@ .word (0x80058c) @36 gpio
@ .word (0x800620) @40 watchdog
@ .word (0x802c01) @44 watchdog
BOOT_LINK_NEED:
.word _code_size_div_256_ @ exclude data
.word _ramcode_size_div_256_compile_
DATA_I:
.word _dstored_
.word _start_data_
.word _end_data_
FLL_D:
.word 0xffffffff
.word (_start_data_)
.word (__RAM_START_ADDR + __RAM_SIZE_MAX)
.word (_rstored_)
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 5,445
|
SDK_3.1.5/proj/mcu_spec/cstartup_8266.S
|
#ifdef MCU_CORE_8266
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x180
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ramcode_size_div_16_align_256_)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
__reset:
@ tloadr r0, DAT0 + 36
@ tmov r1, #1024 @ set sws to GPIO
@ tstorer r1, [r0, #0]
@ tloadr r0, DAT0 + 40 @**** enable watchdog at the very first time
@ tloadr r1, DAT0 + 44
@ tstorer r1, [r0, #0]
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
#ifdef MCU_CORE_8266_OTA_BOOT
tloadr r0, DAT0 + 36
tloadr r0, DAT0 + 36
tloadr r0, DAT0 + 36
#else
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
#endif
@tmov r0, #0;
@tstorerb r0, [r1, #2]
COPY_CODE_INIT:
tmov r3, #115 @ OTA FW ready flag at 0x73000; (0x73000 = #115 << 12)
tshftl r3, r3, #12 @ 0x73<<12
tloadr r3, [r3, #0]
#ifdef MCU_CORE_8266_OTA_BOOT
tcmp r3, #0 @ 0x0
#else
tcmp r3, #165 @ *(u32 *)0x73000 == 0xa5
#endif
tjne COPY_DATA_INIT
tmov r2, #114 @ OTA boot code at: 0x72000 (OTA128K: 0x72000 = 114 << 12)
tloadr r3, COPY_CODE_DAT
tloadr r0, COPY_CODE_DAT + 4
tshftl r2, r2, #12 @ 0x72<<12
COPY_CODE_START:
tloadm r2!, {r1}
tstorem r3!, {r1}
tcmp r3, r0
tjne COPY_CODE_START
tloadr r3, COPY_CODE_DAT + 8
tmov r2, #136 @0x88
tstorerb r2, [r3, #0]
COPY_CODE_END:
tj COPY_CODE_END
.balign 4
COPY_CODE_DAT:
.word (0x808000)
.word (0x808600)
.word (0x800602)
COPY_DATA_INIT:
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x80c000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word _ictag_start_ @28 @ IC tag start
.word _ictag_end_ @32 @ IC tag end
.word _ramcode_size_div_256_ @36
@ .word (0x808000 + __LOAD_RAM * 0x100) @28 @ IC tag start
@ .word (0x808000 + (__LOAD_RAM + 1) * 0x100) @32 @ IC tag end
@ .word (0x80000e) @36
@ .word (0x80058c) @36 gpio
@ .word (0x800620) @40 watchdog
@ .word (0x802c01) @44 watchdog
DATA_I:
.word _dstored_
.word _start_data_
.word _end_data_
FLL_D:
.word 0xffffffff
.word (_start_data_)
.word (0x80c000)
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 3,726
|
SDK_3.1.5/proj/mcu_spec/cstartup_8267_ram.S
|
#ifdef MCU_CORE_8267_RAM
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x100
.equ __LOAD_RAM, 0x2f
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880300)
.org 0x10
tj __irq
.org 0x18
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
__reset:
@ tloadr r0, DAT0 + 36
@ tmov r1, #1024 @ set sws to GPIO
@ tstorer r1, [r0, #0]
@ tloadr r0, DAT0 + 40 @**** enable watchdog at the very first time
@ tloadr r1, DAT0 + 44
@ tstorer r1, [r0, #0]
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
SETIC:
tloadr r1, DAT0 + 24
tmov r0, #64; @ IC tag start
tstorerb r0, [r1, #0]
tmov r0, #64; @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x80c000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word (0x808000 + __LOAD_RAM * 0x100) @28 @ IC tag start
.word (0x808000 + (__LOAD_RAM + 1) * 0x100) @32 @ IC tag end
@ .word (0x80058c) @36 gpio
@ .word (0x800620) @40 watchdog
@ .word (0x802c01) @44 watchdog
DATA_I:
.word _dstored_
.word _start_data_
.word _end_data_
FLL_D:
.word 0x0
.word (_start_data_)
.word (0x80c000)
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 5,470
|
SDK_3.1.5/proj/mcu_spec/cstartup_8261.S
|
#ifdef MCU_CORE_8261
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0xc
#endif
#ifndef __IRQ_STK_SIZE__
#define __IRQ_STK_SIZE__ 0x180
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ramcode_size_div_16_align_256_)
.org 0x10
tj __irq
.org 0x18
.word (_bin_size_)
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
__reset:
@ tloadr r0, DAT0 + 36
@ tmov r1, #1024 @ set sws to GPIO
@ tstorer r1, [r0, #0]
@ tloadr r0, DAT0 + 40 @**** enable watchdog at the very first time
@ tloadr r1, DAT0 + 44
@ tstorer r1, [r0, #0]
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
#ifdef MCU_CORE_8261_OTA_BOOT
tloadr r0, DAT0 + 36
tloadr r0, DAT0 + 36
tloadr r0, DAT0 + 36
#else
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
#endif
COPY_CODE_INIT:
tmov r3, #27 @ OTA FW ready flag at 0x1B000; (0x1B000 = #27 << 12)
tshftl r3, r3, #12 @ 0x1B<<12
tloadr r3, [r3, #0]
#ifdef MCU_CORE_8261_OTA_BOOT
tcmp r3, #0 @ 0x0
#else
tcmp r3, #165 @ *(u32 *)0x1B000 == 0xa5
#endif
tjne COPY_DATA_INIT
tmov r2, #26 @ OTA boot code at: 0x1A000 (OTA128K: 0x1A000 = 26 << 12)
tloadr r3, COPY_CODE_DAT
tloadr r0, COPY_CODE_DAT + 4
tshftl r2, r2, #12 @ 0x1A<<12
COPY_CODE_START:
tloadm r2!, {r1}
tstorem r3!, {r1}
tcmp r3, r0
tjne COPY_CODE_START
tloadr r3, COPY_CODE_DAT + 8
tmov r2, #136 @0x88
tstorerb r2, [r3, #0]
COPY_CODE_END:
tj COPY_CODE_END
.balign 4
COPY_CODE_DAT:
.word (0x808000)
.word (0x808600)
.word (0x800602)
COPY_DATA_INIT:
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
#if 0
SETSPISPEED:
tloadr r1, DAT0 + 36
tmov r0, #0xbb @0x0b for fast read; 0xbb for dual dat/adr
tstorerb r0, [r1, #0]
tmov r0, #3 @3 for dual dat/adr
tstorerb r0, [r1, #1]
#endif
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x80c000) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word _ictag_start_ @28 @ IC tag start
.word _ictag_end_ @32 @ IC tag end
.word _ramcode_size_div_256_ @36
@ .word (0x808000 + __LOAD_RAM * 0x100) @28 @ IC tag start
@ .word (0x808000 + (__LOAD_RAM + 1) * 0x100) @32 @ IC tag end
@ .word (0x80000e) @36
@ .word (0x80058c) @36 gpio
@ .word (0x800620) @40 watchdog
@ .word (0x802c01) @44 watchdog
DATA_I:
.word _dstored_
.word _start_data_
.word _end_data_
FLL_D:
.word 0xffffffff
.word (_start_data_)
.word (0x80c000)
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 3,728
|
SDK_3.1.5/proj/mcu_spec/cstartup_8269_ram.S
|
#ifdef MCU_CORE_8267_RAM
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, 0x100
.equ __LOAD_RAM, 0x2f
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880600)
.org 0x10
tj __irq
.org 0x18
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
__reset:
@ tloadr r0, DAT0 + 36
@ tmov r1, #1024 @ set sws to GPIO
@ tstorer r1, [r0, #0]
@ tloadr r0, DAT0 + 40 @**** enable watchdog at the very first time
@ tloadr r1, DAT0 + 44
@ tstorer r1, [r0, #0]
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
SETIC:
tloadr r1, DAT0 + 24
tmov r0, #126; @ IC tag start
tstorerb r0, [r1, #0]
tmov r0, #126; @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x80ff80) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word (0x808000 + __LOAD_RAM * 0x100) @28 @ IC tag start
.word (0x808000 + (__LOAD_RAM + 1) * 0x100) @32 @ IC tag end
@ .word (0x80058c) @36 gpio
@ .word (0x800620) @40 watchdog
@ .word (0x802c01) @44 watchdog
DATA_I:
.word _dstored_
.word _start_data_
.word _end_data_
FLL_D:
.word 0x0
.word (_start_data_)
.word (0x810000)
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Telink_SIG_Mesh
| 4,487
|
SDK_3.1.5/proj/mcu_spec/cstartup_8263.S
|
#ifdef MCU_CORE_8263
#ifndef __LOAD_RAM_SIZE__
#define __LOAD_RAM_SIZE__ 0x7
#endif
#ifndef __IRQ_STK_SIZE__
#define __IRQ_STK_SIZE__ 0x40
#endif
.code 16
@********************************************************************************************************
@ MACROS AND DEFINIITIONS
@********************************************************************************************************
@.include "version.in"
#include "mesh/version.h"
@ Mode, correspords to bits 0-5 in CPSR
.equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
.equ IRQ_MODE, 0x12 @ Interrupt Request mode
.equ SVC_MODE, 0x13 @ Supervisor mode
.equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
.equ __LOAD_RAM, __LOAD_RAM_SIZE__
@********************************************************************************************************
@ TC32 EXCEPTION VECTORS
@********************************************************************************************************
.section .vectors,"ax"
.global __reset
.global __irq
.global __start
.global __LOAD_RAM
__start: @ MUST, referenced by boot.link
.extern irq_handler
.extern _ramcode_size_div_16_
.extern _ramcode_size_div_256_
.extern _ramcode_size_div_16_align_256_
.extern _ictag_start_
.extern _ictag_end_
.org 0x0
tj __reset
.word (BUILD_VERSION)
.org 0x8
.word (0x544c4e4b)
.word (0x00880000 + _ramcode_size_div_16_align_256_)
.org 0x10
tj __irq
.org 0x18
@********************************************************************************************************
@ LOW-LEVEL INITIALIZATION
@********************************************************************************************************
.extern main
.org 0x20
__reset:
@ tloadr r0, DAT0 + 36
@ tmov r1, #1024 @ set sws to GPIO
@ tstorer r1, [r0, #0]
@ tloadr r0, DAT0 + 40 @**** enable watchdog at the very first time
@ tloadr r1, DAT0 + 44
@ tstorer r1, [r0, #0]
tloadr r0, FLL_D
tloadr r1, FLL_D+4
tloadr r2, FLL_D+8
FLL_STK:
tcmp r1, r2
tjge FLL_STK_END
tstorer r0, [r1, #0]
tadd r1, #4
tj FLL_STK
FLL_STK_END:
tloadr r0, DAT0
tmcsr r0
tloadr r0, DAT0 + 8
tmov r13, r0
tloadr r0, DAT0 + 4
tmcsr r0
tloadr r0, DAT0 + 12
tmov r13, r0
tmov r0, #0
tloadr r1, DAT0 + 16
tloadr r2, DAT0 + 20
ZERO:
tcmp r1, r2
tjge ZERO_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO
ZERO_END:
tloadr r1, DAT0 + 28
tloadr r2, DAT0 + 32
ZERO_TAG:
tcmp r1, r2
tjge ZERO_TAG_END
tstorer r0, [r1, #0]
tadd r1, #4
tj ZERO_TAG
ZERO_TAG_END:
SETIC:
tloadr r1, DAT0 + 24
tloadr r0, DAT0 + 36 @ IC tag start
tstorerb r0, [r1, #0]
tadd r0, #1 @ IC tag end
tstorerb r0, [r1, #1]
@tmov r0, #0;
@tstorerb r0, [r1, #2]
SETSPISPEED:
tloadr r1, DAT0 + 40
tmov r0, #0x3b
tstorerb r0, [r1, #0]
tmov r0, #1
tstorerb r0, [r1, #1]
tloadr r1, DATA_I
tloadr r2, DATA_I+4
tloadr r3, DATA_I+8
COPY_DATA:
tcmp r2, r3
tjge COPY_DATA_END
tloadr r0, [r1, #0]
tstorer r0, [r2, #0]
tadd r1, #4
tadd r2, #4
tj COPY_DATA
COPY_DATA_END:
tjl main
END: tj END
.balign 4
DAT0:
.word 0x12 @IRQ @0
.word 0x13 @SVC @4
.word (irq_stk + IRQ_STK_SIZE)
.word (0x809800) @12 stack end
.word (_start_bss_) @16
.word (_end_bss_) @20
.word (0x80060c) @24
.word _ictag_start_ @28 @ IC tag start
.word _ictag_end_ @32 @ IC tag end
.word _ramcode_size_div_256_ @36
@ .word (0x808000 + __LOAD_RAM * 0x100) @28 @ IC tag start
@ .word (0x808000 + (__LOAD_RAM + 1) * 0x100) @32 @ IC tag end
.word (0x80000e) @40
@ .word (0x80058c) @36 gpio
@ .word (0x800620) @40 watchdog
@ .word (0x802c01) @44 watchdog
DATA_I:
.word _dstored_
.word _start_data_
.word _end_data_
FLL_D:
.word 0xffffffff
.word (_start_data_)
.word (0x809800)
.align 4
__irq:
tpush {r14}
tpush {r0-r7}
tmrss r0
tmov r1, r8
tmov r2, r9
tmov r3, r10
tmov r4, r11
tmov r5, r12
tpush {r0-r5}
tjl irq_handler
tpop {r0-r5}
tmov r8, r1
tmov r9, r2
tmov r10,r3
tmov r11,r4
tmov r12,r5
tmssr r0
tpop {r0-r7}
treti {r15}
ASMEND:
.section .bss
.align 4
.lcomm irq_stk, IRQ_STK_SIZE
.end
#endif
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,086
|
Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,086
|
Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,086
|
Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,086
|
Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,086
|
Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,086
|
Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,086
|
Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,086
|
Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,086
|
Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,086
|
Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,086
|
Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
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