repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
212
| content
stringlengths 590
5.01M
|
|---|---|---|---|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 6,348
|
Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 2,545
|
Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S
|
#if defined (__CC_ARM)
#if (defined (ARMCM0))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARMCM0P) || defined (ARMCM0P_MPU))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARMCM3))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARMCM4) || defined (ARMCM4_FP))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARMv8MBL))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \
defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \
defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) )
#include "ARMCC\startup_armv7-m.s"
#else
#error "No appropriate startup file found!"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if (defined (ARMCM0))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARMCM0P) || defined (ARMCM0P_MPU))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARMCM3))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARMCM4) || defined (ARMCM4_FP))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARMv8MBL))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \
defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \
defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) )
#include "ARMCLANG\startup_armv7-m.S"
#else
#error "No appropriate startup file found!"
#endif
#elif defined (__GNUC__)
#if (defined (ARMCM0))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARMCM0P) || defined (ARMCM0P_MPU))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARMCM3))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARMCM4) || defined (ARMCM4_FP))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARMv8MBL))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \
defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \
defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) )
#include "GCC\startup_armv7-m.S"
#else
#error "No appropriate startup file found!"
#endif
#else
#error "Compiler not supported!"
#endif
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 5,111
|
Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s
|
;/* File: startup_armv7-m.s
; * Purpose: startup file for armv7-m architecture devices.
; * Should be used with ARMCC
; * Version: V2.00
; * Date: 16 November 2015
; *
; */
;/* Copyright (c) 2011 - 2014 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit||
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
BKPT #0
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
BKPT #0
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
BKPT #0
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
BKPT #0
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
BKPT #0
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
ALIGN
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 4,422
|
Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s
|
;/* File: startup_armv6-m.s
; * Purpose: startup file for armv7-m architecture devices.
; * Should be used with ARMCC
; * Version: V2.00
; * Date: 16 November 2015
; *
; */
;/* Copyright (c) 2011 - 2014 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit||
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
BKPT #0
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
BKPT #0
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
ALIGN
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 4,858
|
Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S
|
/* File: startup_armv7-m.S
* Purpose: startup file for armv7-m architecture devices.
* Should be used with ARMCLANG
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
.syntax unified
.arch armv7-m
/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
.global Image$$ARM_LIB_STACK$$ZI$$Limit
.section RESET, "x"
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.text
.thumb
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
.thumb_func
Reset_Handler:
bl SystemInit
bl __main
.globl NMI_Handler
.weak NMI_Handler
.type NMI_Handler, %function
.thumb_func
NMI_Handler:
bkpt #0
b .
.globl HardFault_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
.thumb_func
HardFault_Handler:
bkpt #0
b .
.globl MemManage_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
.thumb_func
MemManage_Handler:
bkpt #0
b .
.globl BusFault_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
.thumb_func
BusFault_Handler:
bkpt #0
b .
.globl UsageFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
.thumb_func
UsageFault_Handler:
bkpt #0
b .
.globl SVC_Handler
.weak SVC_Handler
.type SVC_Handler, %function
.thumb_func
SVC_Handler:
bkpt #0
b .
.globl DebugMon_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
.thumb_func
DebugMon_Handler:
bkpt #0
b .
.globl PendSV_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
.thumb_func
PendSV_Handler:
bkpt #0
b .
.globl SysTick_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
.thumb_func
SysTick_Handler:
bkpt #0
b .
.end
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 4,156
|
Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S
|
/* File: startup_armv6-m.S
* Purpose: startup file for armv6-m architecture devices.
* Should be used with ARMCLANG
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
.syntax unified
.arch armv6-m
/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
.global Image$$ARM_LIB_STACK$$ZI$$Limit
.section RESET, "x"
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.text
.thumb
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
.thumb_func
Reset_Handler:
bl SystemInit
bl __main
.globl NMI_Handler
.weak NMI_Handler
.type NMI_Handler, %function
.thumb_func
NMI_Handler:
bkpt #0
b .
.globl HardFault_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
.thumb_func
HardFault_Handler:
bkpt #0
b .
.globl SVC_Handler
.weak SVC_Handler
.type SVC_Handler, %function
.thumb_func
SVC_Handler:
bkpt #0
b .
.globl PendSV_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
.thumb_func
PendSV_Handler:
bkpt #0
b .
.globl SysTick_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
.thumb_func
SysTick_Handler:
bkpt #0
b .
.end
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 7,347
|
Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S
|
/* File: startup_armv7-m.S
* Purpose: startup file for armv7-m architecture devices.
* Should be used with GCC for ARM Embedded Processors
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
bkpt #0
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
.end
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 7,290
|
Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S
|
/* File: startup_armv6-m.S
* Purpose: startup file for armv6-m architecture devices.
* Should be used with GCC for ARM Embedded Processors
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
blt .L_loop0_0_done
ldr r0, [r1, r3]
str r0, [r2, r3]
b .L_loop0_0
.L_loop0_0_done:
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .L_loop1_done
.L_loop1:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
blt .L_loop2_0_done
str r0, [r1, r2]
b .L_loop2_0
.L_loop2_0_done:
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
subs r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
bkpt #0
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
.end
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 5,313
|
Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S
|
;/* ----------------------------------------------------------------------
; * Project: CMSIS DSP Library
; * Title: arm_bitreversal2.S
; * Description: arm_bitreversal_32 function done in assembly for maximum speed.
; * Called after doing an fft to reorder the output.
; * The function is loop unrolled by 2. arm_bitreversal_16 as well.
; *
; * $Date: 18. March 2019
; * $Revision: V1.5.2
; *
; * Target Processor: Cortex-M cores
; * -------------------------------------------------------------------- */
;/*
; * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
#if defined ( __CC_ARM ) /* Keil */
#define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2
#define LABEL
#elif defined ( __IASMARM__ ) /* IAR */
#define CODESECT SECTION `.text`:CODE
#define PROC
#define LABEL
#define ENDP
#define EXPORT PUBLIC
#elif defined ( __CSMC__ ) /* Cosmic */
#define CODESECT switch .text
#define THUMB
#define EXPORT xdef
#define PROC :
#define LABEL :
#define ENDP
#define arm_bitreversal_32 _arm_bitreversal_32
#elif defined ( __TI_ARM__ ) /* TI ARM */
#define THUMB .thumb
#define CODESECT .text
#define EXPORT .global
#define PROC : .asmfunc
#define LABEL :
#define ENDP .endasmfunc
#define END
#elif defined ( __GNUC__ ) /* GCC */
#define THUMB .thumb
#define CODESECT .section .text
#define EXPORT .global
#define PROC :
#define LABEL :
#define ENDP
#define END
.syntax unified
#endif
CODESECT
THUMB
;/**
; @brief In-place bit reversal function.
; @param[in,out] pSrc points to the in-place buffer of unknown 32-bit data type
; @param[in] bitRevLen bit reversal table length
; @param[in] pBitRevTab points to bit reversal table
; @return none
; */
EXPORT arm_bitreversal_32
EXPORT arm_bitreversal_16
#if defined ( __CC_ARM ) /* Keil */
#elif defined ( __IASMARM__ ) /* IAR */
#elif defined ( __CSMC__ ) /* Cosmic */
#elif defined ( __TI_ARM__ ) /* TI ARM */
#elif defined ( __GNUC__ ) /* GCC */
.type arm_bitreversal_16, %function
.type arm_bitreversal_32, %function
#endif
#if defined (ARM_MATH_CM0_FAMILY)
arm_bitreversal_32 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_32_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
LDR r5,[r2,#4]
LDR r4,[r6,#4]
STR r5,[r6,#4]
STR r4,[r2,#4]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r6}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_16_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
LSRS r2,r2,#1
LSRS r6,r6,#1
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r6}
BX lr
ENDP
#else
arm_bitreversal_32 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8
ADD r9,r0,r9
ADD r2,r0,r2
ADD r12,r0,r12
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
LDR r7,[r9,#4]
LDR r6,[r8,#4]
LDR r5,[r2,#4]
LDR r4,[r12,#4]
STR r6,[r9,#4]
STR r7,[r8,#4]
STR r5,[r12,#4]
STR r4,[r2,#4]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r9}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_16_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8,LSR #1
ADD r9,r0,r9,LSR #1
ADD r2,r0,r2,LSR #1
ADD r12,r0,r12,LSR #1
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r9}
BX lr
ENDP
#endif
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 9,269
|
Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 9,269
|
Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 8,652
|
Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 9,269
|
Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 9,269
|
Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 9,269
|
Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 8,652
|
Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 9,269
|
Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 9,269
|
Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00100000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 26,124
|
Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f411xe.s
;* Author : MCD Application Team
;* Version : V2.6.0
;* Date : 04-November-2016
;* Description : STM32F411xExx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD 0 ; Reserved
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
DMA1_Stream7_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
FPU_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 9,269
|
Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.s
|
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 9,269
|
Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
|
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00080000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 8,652
|
Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.s
|
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 9,269
|
Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.s
|
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00080000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 11,086
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wl5mxx_cm0plus.s
|
;********************************************************************************
;* File Name : startup_stm32wl5mxx_cm0plus.s
;* Author : MCD Application Team
;* Description : MO+ core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TZIC_ILA_IRQHandler ; TZIC ILA Interrupt
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup, Tamper, TimeStamp, RTC Alarms (A & B) and RTC SSRU Interrupts and LSECSS Interrupts
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupt
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD TIM1_IRQHandler ; TIM1 Global Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupt
DCD HSEM_IRQHandler ; Semaphore Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD AES_PKA_IRQHandler ; AES and PKA Interrupt
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK TZIC_ILA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TZIC_ILA_IRQHandler
B TZIC_ILA_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_LSECSS_IRQHandler
B RTC_LSECSS_IRQHandler
PUBWEAK RCC_FLASH_C1SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_FLASH_C1SEV_IRQHandler
B RCC_FLASH_C1SEV_IRQHandler
PUBWEAK EXTI1_0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_0_IRQHandler
B EXTI1_0_IRQHandler
PUBWEAK EXTI3_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_2_IRQHandler
B EXTI3_2_IRQHandler
PUBWEAK EXTI15_4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_4_IRQHandler
B EXTI15_4_IRQHandler
PUBWEAK ADC_COMP_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_COMP_DAC_IRQHandler
B ADC_COMP_DAC_IRQHandler
PUBWEAK DMA1_Channel1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_2_3_IRQHandler
B DMA1_Channel1_2_3_IRQHandler
PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_5_6_7_IRQHandler
B DMA1_Channel4_5_6_7_IRQHandler
PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_DMAMUX1_OVR_IRQHandler
B DMA2_DMAMUX1_OVR_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK TIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_IRQHandler
B TIM1_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK IPCC_C2_RX_C2_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C2_RX_C2_TX_IRQHandler
B IPCC_C2_RX_C2_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK AES_PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_PKA_IRQHandler
B AES_PKA_IRQHandler
PUBWEAK LCD_802_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LCD_802_1_IRQHandler
B LCD_802_1_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK I2C2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_IRQHandler
B I2C2_IRQHandler
PUBWEAK I2C3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_IRQHandler
B I2C3_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 11,086
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wl55xx_cm0plus.s
|
;********************************************************************************
;* File Name : startup_stm32wl55xx_cm0plus.s
;* Author : MCD Application Team
;* Description : MO+ core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TZIC_ILA_IRQHandler ; TZIC ILA Interrupt
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup, Tamper, TimeStamp, RTC Alarms (A & B) and RTC SSRU Interrupts and LSECSS Interrupts
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupt
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD TIM1_IRQHandler ; TIM1 Global Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupt
DCD HSEM_IRQHandler ; Semaphore Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD AES_PKA_IRQHandler ; AES and PKA Interrupt
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK TZIC_ILA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TZIC_ILA_IRQHandler
B TZIC_ILA_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_LSECSS_IRQHandler
B RTC_LSECSS_IRQHandler
PUBWEAK RCC_FLASH_C1SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_FLASH_C1SEV_IRQHandler
B RCC_FLASH_C1SEV_IRQHandler
PUBWEAK EXTI1_0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_0_IRQHandler
B EXTI1_0_IRQHandler
PUBWEAK EXTI3_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_2_IRQHandler
B EXTI3_2_IRQHandler
PUBWEAK EXTI15_4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_4_IRQHandler
B EXTI15_4_IRQHandler
PUBWEAK ADC_COMP_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_COMP_DAC_IRQHandler
B ADC_COMP_DAC_IRQHandler
PUBWEAK DMA1_Channel1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_2_3_IRQHandler
B DMA1_Channel1_2_3_IRQHandler
PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_5_6_7_IRQHandler
B DMA1_Channel4_5_6_7_IRQHandler
PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_DMAMUX1_OVR_IRQHandler
B DMA2_DMAMUX1_OVR_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK TIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_IRQHandler
B TIM1_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK IPCC_C2_RX_C2_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C2_RX_C2_TX_IRQHandler
B IPCC_C2_RX_C2_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK AES_PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_PKA_IRQHandler
B AES_PKA_IRQHandler
PUBWEAK LCD_802_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LCD_802_1_IRQHandler
B LCD_802_1_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK I2C2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_IRQHandler
B I2C2_IRQHandler
PUBWEAK I2C3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_IRQHandler
B I2C3_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 11,086
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wl54xx_cm0plus.s
|
;********************************************************************************
;* File Name : startup_stm32wl54xx_cm0plus.s
;* Author : MCD Application Team
;* Description : MO+ core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TZIC_ILA_IRQHandler ; TZIC ILA Interrupt
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup, Tamper, TimeStamp, RTC Alarms (A & B) and RTC SSRU Interrupts and LSECSS Interrupts
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupt
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD TIM1_IRQHandler ; TIM1 Global Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupt
DCD HSEM_IRQHandler ; Semaphore Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD AES_PKA_IRQHandler ; AES and PKA Interrupt
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK TZIC_ILA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TZIC_ILA_IRQHandler
B TZIC_ILA_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_LSECSS_IRQHandler
B RTC_LSECSS_IRQHandler
PUBWEAK RCC_FLASH_C1SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_FLASH_C1SEV_IRQHandler
B RCC_FLASH_C1SEV_IRQHandler
PUBWEAK EXTI1_0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_0_IRQHandler
B EXTI1_0_IRQHandler
PUBWEAK EXTI3_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_2_IRQHandler
B EXTI3_2_IRQHandler
PUBWEAK EXTI15_4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_4_IRQHandler
B EXTI15_4_IRQHandler
PUBWEAK ADC_COMP_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_COMP_DAC_IRQHandler
B ADC_COMP_DAC_IRQHandler
PUBWEAK DMA1_Channel1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_2_3_IRQHandler
B DMA1_Channel1_2_3_IRQHandler
PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_5_6_7_IRQHandler
B DMA1_Channel4_5_6_7_IRQHandler
PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_DMAMUX1_OVR_IRQHandler
B DMA2_DMAMUX1_OVR_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK TIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_IRQHandler
B TIM1_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK IPCC_C2_RX_C2_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C2_RX_C2_TX_IRQHandler
B IPCC_C2_RX_C2_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK AES_PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_PKA_IRQHandler
B AES_PKA_IRQHandler
PUBWEAK LCD_802_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LCD_802_1_IRQHandler
B LCD_802_1_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK I2C2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_IRQHandler
B I2C2_IRQHandler
PUBWEAK I2C3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_IRQHandler
B I2C3_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,546
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wl5mxx_cm4.s
|
;********************************************************************************
;* File Name : startup_stm32wl5mxx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,546
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wl55xx_cm4.s
|
;********************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,546
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wl54xx_cm4.s
|
;********************************************************************************
;* File Name : startup_stm32wl54xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,064
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wle5xx.s
|
;********************************************************************************
;* File Name : startup_stm32wle5xx.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD 0 ; Reserved
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,064
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wle4xx.s
|
;********************************************************************************
;* File Name : startup_stm32wle4xx.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD 0 ; Reserved
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 10,476
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl5mxx_cm0plus.s
|
/**
******************************************************************************
* @file startup_stm32wl5mxx_cm0plus.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M0+ vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0+ processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0plus
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M0+ vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word TZIC_ILA_IRQHandler /* TZIC ILA Interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word RTC_LSECSS_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RCC_FLASH_C1SEV_IRQHandler /* RCC and FLASH and CPU1 M4 SEV Interrupt */
.word EXTI1_0_IRQHandler /* EXTI Line 1:0 Interrupt */
.word EXTI3_2_IRQHandler /* EXTI Line 3:2 Interrupt */
.word EXTI15_4_IRQHandler /* EXTI Line 15:4 interrupt */
.word ADC_COMP_DAC_IRQHandler /* ADC, COMP1, COMP2, DAC Interrupt */
.word DMA1_Channel1_2_3_IRQHandler /* DMA1 Channel 1 to 3 Interrupt */
.word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channels 4,5,6,7 Interrupt */
.word DMA2_DMAMUX1_OVR_IRQHandler /* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts */
.word LPTIM1_IRQHandler /* LPTIM1 Global Interrupt */
.word LPTIM2_IRQHandler /* LPTIM2 Global Interrupt */
.word LPTIM3_IRQHandler /* LPTIM3 Global Interrupt */
.word TIM1_IRQHandler /* TIM1 Global Interrupt */
.word TIM2_IRQHandler /* TIM2 Global Interrupt */
.word TIM16_IRQHandler /* TIM16 Global Interrupt */
.word TIM17_IRQHandler /* TIM17 Global Interrupt */
.word IPCC_C2_RX_C2_TX_IRQHandler /* IPCC RX Occupied and TX Free Interrupt Interrupt */
.word HSEM_IRQHandler /* Semaphore Interrupt */
.word RNG_IRQHandler /* RNG Interrupt */
.word AES_PKA_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word I2C1_IRQHandler /* I2C1 Event and Error Interrupt */
.word I2C2_IRQHandler /* I2C2 Event and Error Interrupt */
.word I2C3_IRQHandler /* I2C3 Event and Error Interrupt */
.word SPI1_IRQHandler /* SPI1 Interrupt */
.word SPI2_IRQHandler /* SPI2 Interrupt */
.word USART1_IRQHandler /* USART1 Interrupt */
.word USART2_IRQHandler /* USART2 Interrupt */
.word LPUART1_IRQHandler /* LPUART1 Interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI Interrupt */
.word SUBGHZ_Radio_IRQHandler /* SUBGHZ Radio Interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak TZIC_ILA_IRQHandler
.thumb_set TZIC_ILA_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_LSECSS_IRQHandler
.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
.weak RCC_FLASH_C1SEV_IRQHandler
.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
.weak EXTI1_0_IRQHandler
.thumb_set EXTI1_0_IRQHandler,Default_Handler
.weak EXTI3_2_IRQHandler
.thumb_set EXTI3_2_IRQHandler,Default_Handler
.weak EXTI15_4_IRQHandler
.thumb_set EXTI15_4_IRQHandler,Default_Handler
.weak ADC_COMP_DAC_IRQHandler
.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
.weak DMA1_Channel1_2_3_IRQHandler
.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_6_7_IRQHandler
.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
.weak DMA2_DMAMUX1_OVR_IRQHandler
.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak TIM1_IRQHandler
.thumb_set TIM1_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak IPCC_C2_RX_C2_TX_IRQHandler
.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak AES_PKA_IRQHandler
.thumb_set AES_PKA_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak I2C3_IRQHandler
.thumb_set I2C3_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 10,476
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl55xx_cm0plus.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm0plus.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M0+ vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0+ processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0plus
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M0+ vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word TZIC_ILA_IRQHandler /* TZIC ILA Interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word RTC_LSECSS_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RCC_FLASH_C1SEV_IRQHandler /* RCC and FLASH and CPU1 M4 SEV Interrupt */
.word EXTI1_0_IRQHandler /* EXTI Line 1:0 Interrupt */
.word EXTI3_2_IRQHandler /* EXTI Line 3:2 Interrupt */
.word EXTI15_4_IRQHandler /* EXTI Line 15:4 interrupt */
.word ADC_COMP_DAC_IRQHandler /* ADC, COMP1, COMP2, DAC Interrupt */
.word DMA1_Channel1_2_3_IRQHandler /* DMA1 Channel 1 to 3 Interrupt */
.word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channels 4,5,6,7 Interrupt */
.word DMA2_DMAMUX1_OVR_IRQHandler /* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts */
.word LPTIM1_IRQHandler /* LPTIM1 Global Interrupt */
.word LPTIM2_IRQHandler /* LPTIM2 Global Interrupt */
.word LPTIM3_IRQHandler /* LPTIM3 Global Interrupt */
.word TIM1_IRQHandler /* TIM1 Global Interrupt */
.word TIM2_IRQHandler /* TIM2 Global Interrupt */
.word TIM16_IRQHandler /* TIM16 Global Interrupt */
.word TIM17_IRQHandler /* TIM17 Global Interrupt */
.word IPCC_C2_RX_C2_TX_IRQHandler /* IPCC RX Occupied and TX Free Interrupt Interrupt */
.word HSEM_IRQHandler /* Semaphore Interrupt */
.word RNG_IRQHandler /* RNG Interrupt */
.word AES_PKA_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word I2C1_IRQHandler /* I2C1 Event and Error Interrupt */
.word I2C2_IRQHandler /* I2C2 Event and Error Interrupt */
.word I2C3_IRQHandler /* I2C3 Event and Error Interrupt */
.word SPI1_IRQHandler /* SPI1 Interrupt */
.word SPI2_IRQHandler /* SPI2 Interrupt */
.word USART1_IRQHandler /* USART1 Interrupt */
.word USART2_IRQHandler /* USART2 Interrupt */
.word LPUART1_IRQHandler /* LPUART1 Interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI Interrupt */
.word SUBGHZ_Radio_IRQHandler /* SUBGHZ Radio Interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak TZIC_ILA_IRQHandler
.thumb_set TZIC_ILA_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_LSECSS_IRQHandler
.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
.weak RCC_FLASH_C1SEV_IRQHandler
.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
.weak EXTI1_0_IRQHandler
.thumb_set EXTI1_0_IRQHandler,Default_Handler
.weak EXTI3_2_IRQHandler
.thumb_set EXTI3_2_IRQHandler,Default_Handler
.weak EXTI15_4_IRQHandler
.thumb_set EXTI15_4_IRQHandler,Default_Handler
.weak ADC_COMP_DAC_IRQHandler
.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
.weak DMA1_Channel1_2_3_IRQHandler
.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_6_7_IRQHandler
.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
.weak DMA2_DMAMUX1_OVR_IRQHandler
.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak TIM1_IRQHandler
.thumb_set TIM1_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak IPCC_C2_RX_C2_TX_IRQHandler
.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak AES_PKA_IRQHandler
.thumb_set AES_PKA_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak I2C3_IRQHandler
.thumb_set I2C3_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 10,476
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl54xx_cm0plus.s
|
/**
******************************************************************************
* @file startup_stm32wl54xx_cm0plus.s
* @author MCD Application Team
* @brief STM32WL54xx devices Cortex-M0+ vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0+ processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0plus
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL54xx Cortex-M0+ vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word TZIC_ILA_IRQHandler /* TZIC ILA Interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word RTC_LSECSS_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RCC_FLASH_C1SEV_IRQHandler /* RCC and FLASH and CPU1 M4 SEV Interrupt */
.word EXTI1_0_IRQHandler /* EXTI Line 1:0 Interrupt */
.word EXTI3_2_IRQHandler /* EXTI Line 3:2 Interrupt */
.word EXTI15_4_IRQHandler /* EXTI Line 15:4 interrupt */
.word ADC_COMP_DAC_IRQHandler /* ADC, COMP1, COMP2, DAC Interrupt */
.word DMA1_Channel1_2_3_IRQHandler /* DMA1 Channel 1 to 3 Interrupt */
.word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channels 4,5,6,7 Interrupt */
.word DMA2_DMAMUX1_OVR_IRQHandler /* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts */
.word LPTIM1_IRQHandler /* LPTIM1 Global Interrupt */
.word LPTIM2_IRQHandler /* LPTIM2 Global Interrupt */
.word LPTIM3_IRQHandler /* LPTIM3 Global Interrupt */
.word TIM1_IRQHandler /* TIM1 Global Interrupt */
.word TIM2_IRQHandler /* TIM2 Global Interrupt */
.word TIM16_IRQHandler /* TIM16 Global Interrupt */
.word TIM17_IRQHandler /* TIM17 Global Interrupt */
.word IPCC_C2_RX_C2_TX_IRQHandler /* IPCC RX Occupied and TX Free Interrupt Interrupt */
.word HSEM_IRQHandler /* Semaphore Interrupt */
.word RNG_IRQHandler /* RNG Interrupt */
.word AES_PKA_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word I2C1_IRQHandler /* I2C1 Event and Error Interrupt */
.word I2C2_IRQHandler /* I2C2 Event and Error Interrupt */
.word I2C3_IRQHandler /* I2C3 Event and Error Interrupt */
.word SPI1_IRQHandler /* SPI1 Interrupt */
.word SPI2_IRQHandler /* SPI2 Interrupt */
.word USART1_IRQHandler /* USART1 Interrupt */
.word USART2_IRQHandler /* USART2 Interrupt */
.word LPUART1_IRQHandler /* LPUART1 Interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI Interrupt */
.word SUBGHZ_Radio_IRQHandler /* SUBGHZ Radio Interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak TZIC_ILA_IRQHandler
.thumb_set TZIC_ILA_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_LSECSS_IRQHandler
.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
.weak RCC_FLASH_C1SEV_IRQHandler
.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
.weak EXTI1_0_IRQHandler
.thumb_set EXTI1_0_IRQHandler,Default_Handler
.weak EXTI3_2_IRQHandler
.thumb_set EXTI3_2_IRQHandler,Default_Handler
.weak EXTI15_4_IRQHandler
.thumb_set EXTI15_4_IRQHandler,Default_Handler
.weak ADC_COMP_DAC_IRQHandler
.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
.weak DMA1_Channel1_2_3_IRQHandler
.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_6_7_IRQHandler
.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
.weak DMA2_DMAMUX1_OVR_IRQHandler
.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak TIM1_IRQHandler
.thumb_set TIM1_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak IPCC_C2_RX_C2_TX_IRQHandler
.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak AES_PKA_IRQHandler
.thumb_set AES_PKA_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak I2C3_IRQHandler
.thumb_set I2C3_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,268
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl5mxx_cm4.s
|
/**
******************************************************************************
* @file startup_stm32wl5mxx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,268
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl55xx_cm4.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,268
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl54xx_cm4.s
|
/**
******************************************************************************
* @file startup_stm32wl54xx_cm4.s
* @author MCD Application Team
* @brief STM32WL54xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL54xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 15,998
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wle5xx.s
|
/**
******************************************************************************
* @file startup_stm32wle5xx.s
* @author MCD Application Team
* @brief STM32WLE5xx devices vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WLE5xx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word 0 /* Reserved */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 15,998
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wle4xx.s
|
/**
******************************************************************************
* @file startup_stm32wle4xx.s
* @author MCD Application Team
* @brief STM32WLE4xx devices vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WLE4xx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word 0 /* Reserved */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 10,765
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl5mxx_cm0plus.s
|
;********************************************************************************
;* File Name : startup_stm32wl5mxx_cm0plus.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TZIC_ILA_IRQHandler ; Security Interrupt controller illegal access Interrupts
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupts
DCD EXTI3_2_IRQHandler ; XTI Line 3:2 Interrupts
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupts
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupts
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupts
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4, 5, 6, 7 Interrupts
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
DCD LPTIM1_IRQHandler ; LPTIM1 global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 global Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 global Interrupt
DCD TIM1_IRQHandler ; TIM1 Interrupt
DCD TIM2_IRQHandler ; TIM2 Interrupt
DCD TIM16_IRQHandler ; TIM16 Interrupt
DCD TIM17_IRQHandler ; TIM17 Interrupt
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupts
DCD HSEM_IRQHandler ; Semaphore Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD AES_PKA_IRQHandler ; AES and PKA Interrupts
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupts
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT TZIC_ILA_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_LSECSS_IRQHandler [WEAK]
EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
EXPORT EXTI1_0_IRQHandler [WEAK]
EXPORT EXTI3_2_IRQHandler [WEAK]
EXPORT EXTI15_4_IRQHandler [WEAK]
EXPORT ADC_COMP_DAC_IRQHandler [WEAK]
EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT TIM1_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT IPCC_C2_RX_C2_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT AES_PKA_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT I2C3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
TZIC_ILA_IRQHandler
PVD_PVM_IRQHandler
RTC_LSECSS_IRQHandler
RCC_FLASH_C1SEV_IRQHandler
EXTI1_0_IRQHandler
EXTI3_2_IRQHandler
EXTI15_4_IRQHandler
ADC_COMP_DAC_IRQHandler
DMA1_Channel1_2_3_IRQHandler
DMA1_Channel4_5_6_7_IRQHandler
DMA2_DMAMUX1_OVR_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
TIM1_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
IPCC_C2_RX_C2_TX_IRQHandler
HSEM_IRQHandler
RNG_IRQHandler
AES_PKA_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
SUBGHZSPI_IRQHandler
SUBGHZ_Radio_IRQHandler
B .
ENDP
ALIGN
;********************************************************************************
; User Stack and Heap initialization
;********************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 10,765
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl55xx_cm0plus.s
|
;********************************************************************************
;* File Name : startup_stm32wl55xx_cm0plus.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TZIC_ILA_IRQHandler ; Security Interrupt controller illegal access Interrupts
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupts
DCD EXTI3_2_IRQHandler ; XTI Line 3:2 Interrupts
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupts
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupts
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupts
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4, 5, 6, 7 Interrupts
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
DCD LPTIM1_IRQHandler ; LPTIM1 global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 global Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 global Interrupt
DCD TIM1_IRQHandler ; TIM1 Interrupt
DCD TIM2_IRQHandler ; TIM2 Interrupt
DCD TIM16_IRQHandler ; TIM16 Interrupt
DCD TIM17_IRQHandler ; TIM17 Interrupt
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupts
DCD HSEM_IRQHandler ; Semaphore Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD AES_PKA_IRQHandler ; AES and PKA Interrupts
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupts
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT TZIC_ILA_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_LSECSS_IRQHandler [WEAK]
EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
EXPORT EXTI1_0_IRQHandler [WEAK]
EXPORT EXTI3_2_IRQHandler [WEAK]
EXPORT EXTI15_4_IRQHandler [WEAK]
EXPORT ADC_COMP_DAC_IRQHandler [WEAK]
EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT TIM1_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT IPCC_C2_RX_C2_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT AES_PKA_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT I2C3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
TZIC_ILA_IRQHandler
PVD_PVM_IRQHandler
RTC_LSECSS_IRQHandler
RCC_FLASH_C1SEV_IRQHandler
EXTI1_0_IRQHandler
EXTI3_2_IRQHandler
EXTI15_4_IRQHandler
ADC_COMP_DAC_IRQHandler
DMA1_Channel1_2_3_IRQHandler
DMA1_Channel4_5_6_7_IRQHandler
DMA2_DMAMUX1_OVR_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
TIM1_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
IPCC_C2_RX_C2_TX_IRQHandler
HSEM_IRQHandler
RNG_IRQHandler
AES_PKA_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
SUBGHZSPI_IRQHandler
SUBGHZ_Radio_IRQHandler
B .
ENDP
ALIGN
;********************************************************************************
; User Stack and Heap initialization
;********************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 10,765
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl54xx_cm0plus.s
|
;********************************************************************************
;* File Name : startup_stm32wl54xx_cm0plus.s
;* Author : MCD Application Team
;* Description : STM32WL54xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TZIC_ILA_IRQHandler ; Security Interrupt controller illegal access Interrupts
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupts
DCD EXTI3_2_IRQHandler ; XTI Line 3:2 Interrupts
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupts
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupts
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupts
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4, 5, 6, 7 Interrupts
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
DCD LPTIM1_IRQHandler ; LPTIM1 global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 global Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 global Interrupt
DCD TIM1_IRQHandler ; TIM1 Interrupt
DCD TIM2_IRQHandler ; TIM2 Interrupt
DCD TIM16_IRQHandler ; TIM16 Interrupt
DCD TIM17_IRQHandler ; TIM17 Interrupt
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupts
DCD HSEM_IRQHandler ; Semaphore Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD AES_PKA_IRQHandler ; AES and PKA Interrupts
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupts
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT TZIC_ILA_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_LSECSS_IRQHandler [WEAK]
EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
EXPORT EXTI1_0_IRQHandler [WEAK]
EXPORT EXTI3_2_IRQHandler [WEAK]
EXPORT EXTI15_4_IRQHandler [WEAK]
EXPORT ADC_COMP_DAC_IRQHandler [WEAK]
EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT TIM1_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT IPCC_C2_RX_C2_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT AES_PKA_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT I2C3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
TZIC_ILA_IRQHandler
PVD_PVM_IRQHandler
RTC_LSECSS_IRQHandler
RCC_FLASH_C1SEV_IRQHandler
EXTI1_0_IRQHandler
EXTI3_2_IRQHandler
EXTI15_4_IRQHandler
ADC_COMP_DAC_IRQHandler
DMA1_Channel1_2_3_IRQHandler
DMA1_Channel4_5_6_7_IRQHandler
DMA2_DMAMUX1_OVR_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
TIM1_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
IPCC_C2_RX_C2_TX_IRQHandler
HSEM_IRQHandler
RNG_IRQHandler
AES_PKA_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
SUBGHZSPI_IRQHandler
SUBGHZ_Radio_IRQHandler
B .
ENDP
ALIGN
;********************************************************************************
; User Stack and Heap initialization
;********************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,431
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl5mxx_cm4.s
|
;********************************************************************************
;* File Name : startup_stm32wl5mxx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;********************************************************************************
; User Stack and Heap initialization
;********************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,431
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl55xx_cm4.s
|
;********************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;********************************************************************************
; User Stack and Heap initialization
;********************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,431
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl54xx_cm4.s
|
;********************************************************************************
;* File Name : startup_stm32wl54xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL54xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;********************************************************************************
; User Stack and Heap initialization
;********************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,080
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wle5xx.s
|
;********************************************************************************
;* File Name : startup_stm32wle5xx.s
;* Author : MCD Application Team
;* Description : STM32WLE5xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD 0 ; Reserved
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;********************************************************************************
; User Stack and Heap initialization
;********************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,080
|
Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wle4xx.s
|
;********************************************************************************
;* File Name : startup_stm32wle4xx.s
;* Author : MCD Application Team
;* Description : STM32WLE4xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD 0 ; Reserved
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;********************************************************************************
; User Stack and Heap initialization
;********************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 10,745
|
Projects/NUCLEO-WL55JC/Templates/DualCore/MDK-ARM/startup_stm32wl55xx_cm0plus.s
|
;********************************************************************************
;* File Name : startup_stm32wl55xx_cm0plus.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TZIC_ILA_IRQHandler ; Security Interrupt controller illegal access Interrupts
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupts
DCD EXTI3_2_IRQHandler ; XTI Line 3:2 Interrupts
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupts
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupts
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupts
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4, 5, 6, 7 Interrupts
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
DCD LPTIM1_IRQHandler ; LPTIM1 global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 global Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 global Interrupt
DCD TIM1_IRQHandler ; TIM1 Interrupt
DCD TIM2_IRQHandler ; TIM2 Interrupt
DCD TIM16_IRQHandler ; TIM16 Interrupt
DCD TIM17_IRQHandler ; TIM17 Interrupt
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupts
DCD HSEM_IRQHandler ; Semaphore Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD AES_PKA_IRQHandler ; AES and PKA Interrupts
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupts
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT TZIC_ILA_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_LSECSS_IRQHandler [WEAK]
EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
EXPORT EXTI1_0_IRQHandler [WEAK]
EXPORT EXTI3_2_IRQHandler [WEAK]
EXPORT EXTI15_4_IRQHandler [WEAK]
EXPORT ADC_COMP_DAC_IRQHandler [WEAK]
EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT TIM1_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT IPCC_C2_RX_C2_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT AES_PKA_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT I2C3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
TZIC_ILA_IRQHandler
PVD_PVM_IRQHandler
RTC_LSECSS_IRQHandler
RCC_FLASH_C1SEV_IRQHandler
EXTI1_0_IRQHandler
EXTI3_2_IRQHandler
EXTI15_4_IRQHandler
ADC_COMP_DAC_IRQHandler
DMA1_Channel1_2_3_IRQHandler
DMA1_Channel4_5_6_7_IRQHandler
DMA2_DMAMUX1_OVR_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
TIM1_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
IPCC_C2_RX_C2_TX_IRQHandler
HSEM_IRQHandler
RNG_IRQHandler
AES_PKA_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
SUBGHZSPI_IRQHandler
SUBGHZ_Radio_IRQHandler
B .
ENDP
ALIGN
;********************************************************************************
; User Stack and Heap initialization
;********************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,411
|
Projects/NUCLEO-WL55JC/Templates/DualCore/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;********************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;********************************************************************************
; User Stack and Heap initialization
;********************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 11,082
|
Projects/NUCLEO-WL55JC/Templates/DualCore/EWARM/startup_stm32wl55xx_cm0plus.s
|
;********************************************************************************
;* File Name : startup_stm32wl55xx_cm0plus.s
;* Author : MCD Application Team
;* Description : MO+ core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TZIC_ILA_IRQHandler ; TZIC ILA Interrupt
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup, Tamper, TimeStamp, RTC Alarms (A & B) and RTC SSRU Interrupts and LSECSS Interrupts
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupt
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD TIM1_IRQHandler ; TIM1 Global Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupt
DCD HSEM_IRQHandler ; Semaphore Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD AES_PKA_IRQHandler ; AES and PKA Interrupt
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK TZIC_ILA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TZIC_ILA_IRQHandler
B TZIC_ILA_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_LSECSS_IRQHandler
B RTC_LSECSS_IRQHandler
PUBWEAK RCC_FLASH_C1SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_FLASH_C1SEV_IRQHandler
B RCC_FLASH_C1SEV_IRQHandler
PUBWEAK EXTI1_0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_0_IRQHandler
B EXTI1_0_IRQHandler
PUBWEAK EXTI3_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_2_IRQHandler
B EXTI3_2_IRQHandler
PUBWEAK EXTI15_4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_4_IRQHandler
B EXTI15_4_IRQHandler
PUBWEAK ADC_COMP_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_COMP_DAC_IRQHandler
B ADC_COMP_DAC_IRQHandler
PUBWEAK DMA1_Channel1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_2_3_IRQHandler
B DMA1_Channel1_2_3_IRQHandler
PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_5_6_7_IRQHandler
B DMA1_Channel4_5_6_7_IRQHandler
PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_DMAMUX1_OVR_IRQHandler
B DMA2_DMAMUX1_OVR_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK TIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_IRQHandler
B TIM1_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK IPCC_C2_RX_C2_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C2_RX_C2_TX_IRQHandler
B IPCC_C2_RX_C2_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK AES_PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_PKA_IRQHandler
B AES_PKA_IRQHandler
PUBWEAK LCD_802_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LCD_802_1_IRQHandler
B LCD_802_1_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK I2C2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_IRQHandler
B I2C2_IRQHandler
PUBWEAK I2C3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_IRQHandler
B I2C3_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,542
|
Projects/NUCLEO-WL55JC/Templates/DualCore/EWARM/startup_stm32wl55xx_cm4.s
|
;********************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Templates/DualCore/STM32CubeIDE/CM4/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 10,487
|
Projects/NUCLEO-WL55JC/Templates/DualCore/STM32CubeIDE/CM0PLUS/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm0plus.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M0+ vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0+ processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0plus
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M0+ vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word TZIC_ILA_IRQHandler /* TZIC ILA Interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word RTC_LSECSS_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RCC_FLASH_C1SEV_IRQHandler /* RCC and FLASH and CPU1 M4 SEV Interrupt */
.word EXTI1_0_IRQHandler /* EXTI Line 1:0 Interrupt */
.word EXTI3_2_IRQHandler /* EXTI Line 3:2 Interrupt */
.word EXTI15_4_IRQHandler /* EXTI Line 15:4 interrupt */
.word ADC_COMP_DAC_IRQHandler /* ADC, COMP1, COMP2, DAC Interrupt */
.word DMA1_Channel1_2_3_IRQHandler /* DMA1 Channel 1 to 3 Interrupt */
.word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channels 4,5,6,7 Interrupt */
.word DMA2_DMAMUX1_OVR_IRQHandler /* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts */
.word LPTIM1_IRQHandler /* LPTIM1 Global Interrupt */
.word LPTIM2_IRQHandler /* LPTIM2 Global Interrupt */
.word LPTIM3_IRQHandler /* LPTIM3 Global Interrupt */
.word TIM1_IRQHandler /* TIM1 Global Interrupt */
.word TIM2_IRQHandler /* TIM2 Global Interrupt */
.word TIM16_IRQHandler /* TIM16 Global Interrupt */
.word TIM17_IRQHandler /* TIM17 Global Interrupt */
.word IPCC_C2_RX_C2_TX_IRQHandler /* IPCC RX Occupied and TX Free Interrupt Interrupt */
.word HSEM_IRQHandler /* Semaphore Interrupt */
.word RNG_IRQHandler /* RNG Interrupt */
.word AES_PKA_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word I2C1_IRQHandler /* I2C1 Event and Error Interrupt */
.word I2C2_IRQHandler /* I2C2 Event and Error Interrupt */
.word I2C3_IRQHandler /* I2C3 Event and Error Interrupt */
.word SPI1_IRQHandler /* SPI1 Interrupt */
.word SPI2_IRQHandler /* SPI2 Interrupt */
.word USART1_IRQHandler /* USART1 Interrupt */
.word USART2_IRQHandler /* USART2 Interrupt */
.word LPUART1_IRQHandler /* LPUART1 Interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI Interrupt */
.word SUBGHZ_Radio_IRQHandler /* SUBGHZ Radio Interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak TZIC_ILA_IRQHandler
.thumb_set TZIC_ILA_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_LSECSS_IRQHandler
.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
.weak RCC_FLASH_C1SEV_IRQHandler
.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
.weak EXTI1_0_IRQHandler
.thumb_set EXTI1_0_IRQHandler,Default_Handler
.weak EXTI3_2_IRQHandler
.thumb_set EXTI3_2_IRQHandler,Default_Handler
.weak EXTI15_4_IRQHandler
.thumb_set EXTI15_4_IRQHandler,Default_Handler
.weak ADC_COMP_DAC_IRQHandler
.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
.weak DMA1_Channel1_2_3_IRQHandler
.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_6_7_IRQHandler
.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
.weak DMA2_DMAMUX1_OVR_IRQHandler
.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak TIM1_IRQHandler
.thumb_set TIM1_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak IPCC_C2_RX_C2_TX_IRQHandler
.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak AES_PKA_IRQHandler
.thumb_set AES_PKA_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak I2C3_IRQHandler
.thumb_set I2C3_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,426
|
Projects/NUCLEO-WL55JC/Templates/SingleCore/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;********************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;********************************************************************************
; User Stack and Heap initialization
;********************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,542
|
Projects/NUCLEO-WL55JC/Templates/SingleCore/EWARM/startup_stm32wl55xx_cm4.s
|
;********************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2020 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Templates/SingleCore/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_DMABurst/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_DMABurst/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_DMABurst/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_InputCapture/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_InputCapture/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_InputCapture/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_PWMOutput/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_PWMOutput/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_PWMInput/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_PWMInput/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_DMA/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_DMA/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_DMA/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OCInactive/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OCInactive/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OCInactive/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_TimeBase/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_TimeBase/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_TimeBase/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OCActive/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OCActive/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OnePulse/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OnePulse/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OnePulse/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OCToggle/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OCToggle/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/TIM/TIM_OCToggle/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/WWDG/WWDG_Example/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/WWDG/WWDG_Example/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/PWR/PWR_STOP2_RTC/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 10,746
|
Projects/NUCLEO-WL55JC/Examples/PWR/PWR_Standby_DualCore/MDK-ARM/startup_stm32wl55xx_cm0plus.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm0plus.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TZIC_ILA_IRQHandler ; Security Interrupt controller illegal access Interrupts
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupts
DCD EXTI3_2_IRQHandler ; XTI Line 3:2 Interrupts
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupts
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupts
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupts
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4, 5, 6, 7 Interrupts
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
DCD LPTIM1_IRQHandler ; LPTIM1 global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 global Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 global Interrupt
DCD TIM1_IRQHandler ; TIM1 Interrupt
DCD TIM2_IRQHandler ; TIM2 Interrupt
DCD TIM16_IRQHandler ; TIM16 Interrupt
DCD TIM17_IRQHandler ; TIM17 Interrupt
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupts
DCD HSEM_IRQHandler ; Semaphore Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD AES_PKA_IRQHandler ; AES and PKA Interrupts
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupts
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT TZIC_ILA_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_LSECSS_IRQHandler [WEAK]
EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
EXPORT EXTI1_0_IRQHandler [WEAK]
EXPORT EXTI3_2_IRQHandler [WEAK]
EXPORT EXTI15_4_IRQHandler [WEAK]
EXPORT ADC_COMP_DAC_IRQHandler [WEAK]
EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT TIM1_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT IPCC_C2_RX_C2_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT AES_PKA_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT I2C3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
TZIC_ILA_IRQHandler
PVD_PVM_IRQHandler
RTC_LSECSS_IRQHandler
RCC_FLASH_C1SEV_IRQHandler
EXTI1_0_IRQHandler
EXTI3_2_IRQHandler
EXTI15_4_IRQHandler
ADC_COMP_DAC_IRQHandler
DMA1_Channel1_2_3_IRQHandler
DMA1_Channel4_5_6_7_IRQHandler
DMA2_DMAMUX1_OVR_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
TIM1_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
IPCC_C2_RX_C2_TX_IRQHandler
HSEM_IRQHandler
RNG_IRQHandler
AES_PKA_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
SUBGHZSPI_IRQHandler
SUBGHZ_Radio_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/PWR/PWR_Standby_DualCore/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 11,085
|
Projects/NUCLEO-WL55JC/Examples/PWR/PWR_Standby_DualCore/EWARM/startup_stm32wl55xx_cm0plus.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm0plus.s
;* Author : MCD Application Team
;* Description : MO+ core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TZIC_ILA_IRQHandler ; TZIC ILA Interrupt
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup, Tamper, TimeStamp, RTC Alarms (A & B) and RTC SSRU Interrupts and LSECSS Interrupts
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupt
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD TIM1_IRQHandler ; TIM1 Global Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupt
DCD HSEM_IRQHandler ; Semaphore Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD AES_PKA_IRQHandler ; AES and PKA Interrupt
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK TZIC_ILA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TZIC_ILA_IRQHandler
B TZIC_ILA_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_LSECSS_IRQHandler
B RTC_LSECSS_IRQHandler
PUBWEAK RCC_FLASH_C1SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_FLASH_C1SEV_IRQHandler
B RCC_FLASH_C1SEV_IRQHandler
PUBWEAK EXTI1_0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_0_IRQHandler
B EXTI1_0_IRQHandler
PUBWEAK EXTI3_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_2_IRQHandler
B EXTI3_2_IRQHandler
PUBWEAK EXTI15_4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_4_IRQHandler
B EXTI15_4_IRQHandler
PUBWEAK ADC_COMP_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_COMP_DAC_IRQHandler
B ADC_COMP_DAC_IRQHandler
PUBWEAK DMA1_Channel1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_2_3_IRQHandler
B DMA1_Channel1_2_3_IRQHandler
PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_5_6_7_IRQHandler
B DMA1_Channel4_5_6_7_IRQHandler
PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_DMAMUX1_OVR_IRQHandler
B DMA2_DMAMUX1_OVR_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK TIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_IRQHandler
B TIM1_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK IPCC_C2_RX_C2_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C2_RX_C2_TX_IRQHandler
B IPCC_C2_RX_C2_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK AES_PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_PKA_IRQHandler
B AES_PKA_IRQHandler
PUBWEAK LCD_802_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LCD_802_1_IRQHandler
B LCD_802_1_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK I2C2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_IRQHandler
B I2C2_IRQHandler
PUBWEAK I2C3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_IRQHandler
B I2C3_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 17,545
|
Projects/NUCLEO-WL55JC/Examples/PWR/PWR_Standby_DualCore/EWARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WLxxxx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_SSRU_IRQHandler
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK SUBGHZSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZSPI_IRQHandler
B SUBGHZSPI_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SUBGHZ_Radio_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SUBGHZ_Radio_IRQHandler
B SUBGHZ_Radio_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,279
|
Projects/NUCLEO-WL55JC/Examples/PWR/PWR_Standby_DualCore/STM32CubeIDE/CM4/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm4.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
.word ADC_IRQHandler /* ADC interrupt */
.word DAC_IRQHandler /* DAC interrupt */
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
.word TIM1_UP_IRQHandler /* Timer 1 Update */
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM16_IRQHandler /* Timer 16 global interrupt */
.word TIM17_IRQHandler /* Timer 17 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
.word AES_IRQHandler /* AES global interrupt */
.word RNG_IRQHandler /* RNG interrupt */
.word PKA_IRQHandler /* PKA interrupt */
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 10,487
|
Projects/NUCLEO-WL55JC/Examples/PWR/PWR_Standby_DualCore/STM32CubeIDE/CM0PLUS/Application/Startup/startup_stm32wl55jcix.s
|
/**
******************************************************************************
* @file startup_stm32wl55xx_cm0plus.s
* @author MCD Application Team
* @brief STM32WL55xx devices Cortex-M0+ vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0+ processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2020 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0plus
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32WL55xx Cortex-M0+ vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word TZIC_ILA_IRQHandler /* TZIC ILA Interrupt */
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
.word RTC_LSECSS_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
.word RCC_FLASH_C1SEV_IRQHandler /* RCC and FLASH and CPU1 M4 SEV Interrupt */
.word EXTI1_0_IRQHandler /* EXTI Line 1:0 Interrupt */
.word EXTI3_2_IRQHandler /* EXTI Line 3:2 Interrupt */
.word EXTI15_4_IRQHandler /* EXTI Line 15:4 interrupt */
.word ADC_COMP_DAC_IRQHandler /* ADC, COMP1, COMP2, DAC Interrupt */
.word DMA1_Channel1_2_3_IRQHandler /* DMA1 Channel 1 to 3 Interrupt */
.word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channels 4,5,6,7 Interrupt */
.word DMA2_DMAMUX1_OVR_IRQHandler /* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts */
.word LPTIM1_IRQHandler /* LPTIM1 Global Interrupt */
.word LPTIM2_IRQHandler /* LPTIM2 Global Interrupt */
.word LPTIM3_IRQHandler /* LPTIM3 Global Interrupt */
.word TIM1_IRQHandler /* TIM1 Global Interrupt */
.word TIM2_IRQHandler /* TIM2 Global Interrupt */
.word TIM16_IRQHandler /* TIM16 Global Interrupt */
.word TIM17_IRQHandler /* TIM17 Global Interrupt */
.word IPCC_C2_RX_C2_TX_IRQHandler /* IPCC RX Occupied and TX Free Interrupt Interrupt */
.word HSEM_IRQHandler /* Semaphore Interrupt */
.word RNG_IRQHandler /* RNG Interrupt */
.word AES_PKA_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
.word I2C1_IRQHandler /* I2C1 Event and Error Interrupt */
.word I2C2_IRQHandler /* I2C2 Event and Error Interrupt */
.word I2C3_IRQHandler /* I2C3 Event and Error Interrupt */
.word SPI1_IRQHandler /* SPI1 Interrupt */
.word SPI2_IRQHandler /* SPI2 Interrupt */
.word USART1_IRQHandler /* USART1 Interrupt */
.word USART2_IRQHandler /* USART2 Interrupt */
.word LPUART1_IRQHandler /* LPUART1 Interrupt */
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI Interrupt */
.word SUBGHZ_Radio_IRQHandler /* SUBGHZ Radio Interrupt */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak TZIC_ILA_IRQHandler
.thumb_set TZIC_ILA_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_LSECSS_IRQHandler
.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
.weak RCC_FLASH_C1SEV_IRQHandler
.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
.weak EXTI1_0_IRQHandler
.thumb_set EXTI1_0_IRQHandler,Default_Handler
.weak EXTI3_2_IRQHandler
.thumb_set EXTI3_2_IRQHandler,Default_Handler
.weak EXTI15_4_IRQHandler
.thumb_set EXTI15_4_IRQHandler,Default_Handler
.weak ADC_COMP_DAC_IRQHandler
.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
.weak DMA1_Channel1_2_3_IRQHandler
.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_6_7_IRQHandler
.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
.weak DMA2_DMAMUX1_OVR_IRQHandler
.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak TIM1_IRQHandler
.thumb_set TIM1_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak IPCC_C2_RX_C2_TX_IRQHandler
.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak AES_PKA_IRQHandler
.thumb_set AES_PKA_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak I2C3_IRQHandler
.thumb_set I2C3_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak SUBGHZSPI_IRQHandler
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
.weak SUBGHZ_Radio_IRQHandler
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
.weak SystemInit
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 10,746
|
Projects/NUCLEO-WL55JC/Examples/PWR/PWR_Stop2_DualCore/MDK-ARM/startup_stm32wl55xx_cm0plus.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm0plus.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TZIC_ILA_IRQHandler ; Security Interrupt controller illegal access Interrupts
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupts
DCD EXTI3_2_IRQHandler ; XTI Line 3:2 Interrupts
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupts
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupts
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupts
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4, 5, 6, 7 Interrupts
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
DCD LPTIM1_IRQHandler ; LPTIM1 global Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 global Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 global Interrupt
DCD TIM1_IRQHandler ; TIM1 Interrupt
DCD TIM2_IRQHandler ; TIM2 Interrupt
DCD TIM16_IRQHandler ; TIM16 Interrupt
DCD TIM17_IRQHandler ; TIM17 Interrupt
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupts
DCD HSEM_IRQHandler ; Semaphore Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD AES_PKA_IRQHandler ; AES and PKA Interrupts
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupts
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT TZIC_ILA_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_LSECSS_IRQHandler [WEAK]
EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
EXPORT EXTI1_0_IRQHandler [WEAK]
EXPORT EXTI3_2_IRQHandler [WEAK]
EXPORT EXTI15_4_IRQHandler [WEAK]
EXPORT ADC_COMP_DAC_IRQHandler [WEAK]
EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT TIM1_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT IPCC_C2_RX_C2_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT AES_PKA_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT I2C3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
TZIC_ILA_IRQHandler
PVD_PVM_IRQHandler
RTC_LSECSS_IRQHandler
RCC_FLASH_C1SEV_IRQHandler
EXTI1_0_IRQHandler
EXTI3_2_IRQHandler
EXTI15_4_IRQHandler
ADC_COMP_DAC_IRQHandler
DMA1_Channel1_2_3_IRQHandler
DMA1_Channel4_5_6_7_IRQHandler
DMA2_DMAMUX1_OVR_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
TIM1_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
IPCC_C2_RX_C2_TX_IRQHandler
HSEM_IRQHandler
RNG_IRQHandler
AES_PKA_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
SUBGHZSPI_IRQHandler
SUBGHZ_Radio_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Ai-Thinker-Open/Ai-Thinker-LoRaWAN-Ra-09
| 16,412
|
Projects/NUCLEO-WL55JC/Examples/PWR/PWR_Stop2_DualCore/MDK-ARM/startup_stm32wl55xx_cm4.s
|
;*******************************************************************************
;* File Name : startup_stm32wl55xx_cm4.s
;* Author : MCD Application Team
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;* @attention
;*
;* Copyright (c) 2020-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;********************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD DAC_IRQHandler ; DAC Interrupt
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD USART1_IRQHandler ; USART1 Interrupt
DCD USART2_IRQHandler ; USART2 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
DCD AES_IRQHandler ; AES Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT SUBGHZSPI_IRQHandler [WEAK]
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
EXPORT HSEM_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT PKA_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_LSECSS_SSRU_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC_IRQHandler
DAC_IRQHandler
C2SEV_PWR_C2H_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LPUART1_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
LPTIM3_IRQHandler
SUBGHZSPI_IRQHandler
IPCC_C1_RX_IRQHandler
IPCC_C1_TX_IRQHandler
HSEM_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SUBGHZ_Radio_IRQHandler
AES_IRQHandler
RNG_IRQHandler
PKA_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMAMUX1_OVR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
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