module_name stringlengths 1 2.17k | module_content stringlengths 6 11.3k |
|---|---|
cu_driver |
#if MIXED_SIM
sc_out<sc_logic> rst;
sc_out<sc_logic> RD; // DRAM read command
sc_out<sc_logic> WR; // DRAM write command
sc_out<sc_logic> ACT; // DRAM activate command
// sc_out<sc_logic> RSTB; //
sc_out<sc_logic> AB_mode; // Signals if the All-Banks mode is enabled
sc_out<sc_lo... |
rocket_wrapper |
//== Ports
sc_in<bool> clock;
sc_in<bool> reset;
sc_out<sc_lv<44>> periph_aw_msg;
sc_out<bool> periph_aw_valid;
sc_in<bool> periph_aw_ready;
sc_out<sc_lv<37>> periph_w_msg;
sc_out<bool> periph_w_valid;
sc_in<bool... |
sc_shifter_TB |
sc_clock clk;
sc_signal<bool> rst,
sc_signal<sc_bv<7> > rst, din, qout;
Vshifter* u_Vshifter;
sc_trace_file* fp; // SystemC VCD file
SC_CTOR(sc_shifter_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate... |
communicationInterfaceTB |
sc_signal<sc_uint<12> > inData;
sc_signal<bool> clock , reset , clear;
sc_signal<sc_uint<4> > payloadOut;
sc_signal<sc_uint<8> > countOut , errorOut;
void clockSignal();
void clearSignal();
void resetSignal();
void inDataSignal();
communicationInterface* cI;
SC_CTOR(communicationInterfaceTB) {
cI = ne... |
fir_top |
sc_in<bool> CLK;
sc_in<bool> RESET;
sc_in<bool> IN_VALID;
sc_in<int> SAMPLE;
sc_out<bool> OUTPUT_DATA_READY;
sc_out<int> RESULT;
sc_signal<unsigned> state_out;
fir_fsm *fir_fsm1;
fir_data *fir_data1;
SC_CTOR(fir_top) {
fir_fsm1 = new fir_fsm("FirFSM");... |
top |
HMAC hmc;
SHA512_masked sha384_1;
SHA512_masked sha384_2;
hmac_sha hmacsha;
blocking_in<block> top_hmac;
blocking_out<sc_biguint<KEY_WIDTH>> top_tag;
Blocking<block> hmac_msg;
Blocking<sc_biguint<KEY_WIDTH>> tag;
Blocking<sha_splitter> sha_msg_split_1, sha_msg_split_2;
Blocking<sc_big... |
transmitter)
//class transmitter : public sc_module
{
/// Input port for datas from the switch
sc_in<Packet> datain;
/// reset port
sc_in<bool> rst_n;
/// clk port
sc_in<bool> clk;
/// full port. If it's set it indicates that the fifo of the transmitter is to small to contain all datas
sc_out<sc_bit> full;
//... |
SC_METHOD(evaluate);
sensitive<<clk.pos()<<rst_n.neg();
FIFO= new Packet[m_fifo_tx_dim];
for (i=0;i<m_fifo_tx_dim;i++)
FIFO[i]=empty_NL_PDU;
last_pos=0;
if(m_N_R > m_N_T)
c=m_N_R;
tx_file.open ("tx_file.txt",ios::trunc);
tx_file << "SIMULATION STARTS NOW: "<<endl<<endl;
tx_file.close();
}... |
sc_fir8 |
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<8> > X[FILTER_TAP_NUM]; // Shift Register X
void fir8_thread(void)
{
uint8_t x;
uint8_t yL, yH... |
fir |
sc_in<bool> clk;
sc_in<bool> rst;
sc_in<sc_int<16>> inp;
sc_out<sc_int<16>> out;
// Handshake signals
sc_in<bool> inp_vld;
sc_out<bool> inp_rdy;
sc_out<bool> out_vld;
sc_in<bool> out_rdy;
void fir_main();
SC_CTOR( fir ) {
SC_... |
CounterModule |
// Inputs
sc_in<bool> clk;
sc_in<bool> reset;
sc_in<bool> up_down_ctrl;
sc_in<bool> count_enable;
//Outputs
sc_out<sc_uint<N> > count_out;
sc_out<bool> overflow_intr;
sc_out<bool> underflow_intr;
// Variables
sc_uint<N> count;
// Main function of the module
void do_count();
SC_CTOR(Coun... |
i2c_controller_tb |
sc_clock *clk;
sc_signal<bool> rst;
sc_signal<sc_uint<7>> addr;
sc_signal<sc_uint<8>> data_in;
sc_signal<bool> enable;
sc_signal<bool> rw;
sc_signal<sc_lv<8>> data_out;
sc_signal<bool> ready;
sc_signal<sc_logic, SC_MANY_WRITERS> i2c_sda;
sc_signal<sc_logic> i2c_scl;
i2c_controller *master;
i2c_slave_co... |
sc_DUT_TB |
sc_clock CLK;
sc_signal<bool> nCLR;
sc_signal<bool> nLOAD;
sc_signal<bool> ENP;
sc_signal<bool> ENT;
sc_signal<bool> RCO;
// Verilator treats all Verilog's vector as <uint32_t>
sc_signal<uint32_t> Digit;
sc_signal<uint32_t>... |
dut_cycsim |
// Port declarations.
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_dat... |
dut |
sc_in_clk clk;
sc_in< bool > rst;
cynw_p2p< input_data, ioConfig >::in in;
cynw_p2p< output_data, ioConfig >::out out;
stream_16X8::in<ioConfig> streamin;
stream_16X8::out<ioConfig> streamout;
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, in( "in" )
, ou... |
tb |
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_CTOR( tb ){
SC_... |
s3 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s3_box();
SC_CTOR(s3)
{
SC_METHOD(s3_box);
sensitive << stage1_input;
}
|
display |
// Port for input by channel
sc_port< sc_csp_channel_in_if< sc_uint<8> > > result_channel_port;
SC_CTOR(display)
{
SC_THREAD(output);
}
// Main method
void output();
|
dut_cycsim |
// Port declarations.
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_1_busy;
sc_in< bool > din_1_vld;
sc_in< sc_uint< 8 > > din_1_data;
sc_out< bool > din_2_busy;
sc_in< bool > din_2_vld;
sc_in< sc_uint< 8 > > din_2_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 9 > > d... |
sc_top |
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> d... |
V_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<ui... |
Neuron |
sc_in<float> input1, input2;
sc_out<float> output;
float w1, w2, b, y;
float output_temp;
void neuron();
SC_CTOR(Neuron) {
SC_METHOD(neuron);
sensitive << input1 << input2;
}
|
ACCNAME |
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> ... |
s6 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s6_box();
SC_CTOR(s6)
{
SC_METHOD(s6_box);
sensitive << stage1_input;
}
|
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<8> > Xin;
sc_signal<sc_uint<8> > Xout;
sc_signal<sc_uint<16> > Yin;
sc_signal<sc_uint<16> > Yout;
#ifdef EMULATED
sc_signal<sc_uint<8> > E_Xout;
sc_signal<sc_uint<16> > E_Yout;
#endif
sc_fir8* u_sc_fir8;
// Test util... |
Neural_Network |
sc_in<float> input1, input2;
sc_out<float> output;
sc_signal<float> c1, c2;
Neuron* N1;
Neuron* N2;
Neuron* N3;
SC_CTOR(Neural_Network) {
// vvvvv put your code here vvvvv
N1 = new Neuron("N1");
N2 = new Neuron("N2");
N3 = new Neuron("N3");
N1->in... |
tb |
sc_out < sc_uint<4> > OPa,OPb;
sc_out < sc_uint<4> > OP;
sc_in<bool> Clk;
void tbGen() {
OPa.write(0111);
OPb.write(0001);
OP.write(0);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(1);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(2);
wait(... |
dut_cycsim |
// Port declarations.
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_dat... |
sc_top |
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> d... |
V_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<ui... |
cnn |
// typedef
typedef hwcore::cnn::top_cnn<P_data_W, P_data_P, P_input_BW_N, P_output_BW_N, P_pe_n, P_pe_bw_n, P_wbuf_size,
P_data_buf_clb_size, P_data_buf_clb_n, P_data_buf_shift_size, P_data_out_n,
P_pool_size, P_PE_pipeline_II, P_pe_pre_fifo_deep>
top... |
mux_pcnt |
sc_port<sc_signal_in_if<bool>,0> mout_i {"mout_i" |
IP_RIVER |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface bus
sc_in<bool> ACK;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> GRANT;
sc_in<sc_uint<32>> ADR_I;
sc_out<sc_uint<32>> ADR;
sc_out<sc_uint<32>> DAT_O;
sc_out<sc_uint<2>> SEL;
sc_out<bool> STB;... |
icache |
// interface global
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface RiVer
sc_in<sc_uint<32> > ADR_SI;
sc_in<bool> ADR_VALID_SI;
sc_out<sc_bv<32> > INST_SIC;
sc_out<bool> STALL_SIC;
//interface wrapper
sc_in<sc_uint<32>> DT_SW;
sc_out<sc_uint<32>> A_SIC;
sc_out<boo... |
tb |
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_HAS_PROCESS( tb );
tb(... |
x1_multiplier |
// input :
sc_in<sc_bv<320>> IN_RX0;
sc_in<bool> SELECT_HIGHER_BITS_RX0;
sc_in<bool> SIGNED_RES_RX0;
sc_in<bool> X02X1_EMPTY_SX0;
sc_in<bool> X12X2_POP_SX2;
// output :
sc_out<sc_bv<128>> RES_RX1;
sc_out<bool> SELECT_HIGHER_BITS_RX1;
... |
ACCNAME |
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
... |
E_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
#define N_TX 3
#define N_RX 2
void pe_thr... |
sc_dffrs_TB |
sc_clock clk;
sc_signal<bool> r, s, d, q;
Vdffrs* u_Vdffrs;
sc_trace_file* fp; // VCD file
SC_CTOR(sc_dffrs_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
u_Vdffrs = new Vdffrs("u_Vdffrs");
// Binding
... |
fila |
sc_in<bool > clock;
sc_in<bool > reset_n;
sc_in<regflit > data_in;
sc_in<bool > rx;
sc_out<bool > credit_o;
//sc_out<bool > ack_rx;
sc_out<bool > h;
sc_in<bool > ack_h;
sc_out<bool > data_av;
sc_out<regflit > data;
sc_in<bool > data_ack;
sc_out<bool > sender;
enum fila_out{S_INIT, S_PAYLOAD... |
s8 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s8_box();
SC_CTOR(s8)
{
SC_METHOD(s8_box);
sensitive << stage1_input;
}
|
fpu_driver |
#if MIXED_SIM
sc_out<sc_logic> rst;
sc_out<sc_logic> mult_en; // Signals that a multiply computation step should be performed
sc_out<sc_logic> add_en; // Signals that an add computation step should be performed
sc_out<sc_lv<16> > srf_in; // Scalar operand from SRF
sc_out<... |
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_i... |
scClk |
sc_out<bool> clk{"clk_o" |
E_fir_pe |
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
#define N_TX 4
#define N_RX 3
void pe_thread(void)
{
uint8_t x, y, txPacket[N_TX], rxPacket... |
ACCNAME |
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
// int rows=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
... |
subbytes |
sc_in<bool> clk;
sc_in<bool> reset;
sc_in<bool> start_i;
sc_in<bool> decrypt_i;
sc_in<sc_biguint <128> > data_i;
sc_out<bool> ready_o;
sc_out<sc_biguint<128> > data_o;
//To sbox
sc_out<sc_uint<8> > sbox_data_o;
sc_in<sc_uint<8> > sbox_data_i;
sc_out<bool>sbox_decrypt_o;
void sub();
void registers();
... |
full_adder |
public: sc_in<bool> a, b, cin;
public: sc_out<bool> sum, cout;
//---------------------------------------
public: SC_CTOR(full_adder)
{
SC_METHOD(process);
sensitive << a << b << cin;
}
//---------------------------------------
private: void process()
{
bool aANDb, aXORb, cinANDaXORb;
aANDb = a.read... |
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<4> > Xin;
sc_signal<sc_uint<4> > Xout;
sc_signal<sc_uint<4> > Yin;
sc_signal<sc_uint<4> > Yout;
sc_signal<bool> Vld;
sc_signal<bool> Rdy;
#ifdef EMULATED
sc_signal<sc_uint<4> > E_Xout;
sc_signal<sc_uint<4> > ... |
ACCNAME |
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
... |
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_i... |
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_i... |
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_i... |
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_i... |
riscv_soc |
public:
sc_in<bool> i_sys_nrst; // Power-on system reset active LOW
sc_in<bool> i_sys_clk; // System/Bus clock
sc_in<bool> i_dbg_nrst; // Reset from Debug interface (DMI). Reset everything except DMI
sc_in... |
btclient |
sc_in<unsigned int> rx {"rx" |
ALEXNET |
CONV_RELU_1 m_CONV_RELU_1;
MAX_POOLING_1 m_MAX_POOLING_1;
CONV_RELU_2 m_CONV_RELU_2;
MAX_POOLING_2 m_MAX_POOLING_2;
CONV_RELU_3 m_CONV_RELU_3;
CONV_RELU_4 m_CONV_RELU_4;
CONV_RELU_5 m_CONV_RELU_5;
MAX_POOLING_3 m_MAX_POOLING_3;
LINEAR_RELU_1 m_LINEAR_RELU_1;
LINEAR_RELU_2 m_LINE... |
tb |
// inputs
sc_in<bool> clk;
sc_in<sc_uint<64> > rt_des_data_i;
sc_in<bool> rt_des_ready_i;
// outputs
sc_out<bool> rt_load_o;
sc_out<sc_uint<64> >rt_des_data_o;
sc_out<sc_uint<64> >rt_des_key_o;
sc_out<bool> rt_decrypt_o;
sc_out<bool> rt_reset;
void send();
void recv();... |
param_in |
sc_in<bool> clk;
sc_fifo_out<T> o;
void main(void) {
while ( 1 ) {
o.write(val);
if ( trace ) cout << modname << " put " << val << " at " << sc_time_stamp() << endl;
wait(clk.posedge_event());
}
}
SC_HAS_PROCESS(param_in);
param_in(sc_module_name name_, T val_, bool trace_... |
Showcase0 |
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contO... |
tb_gpio |
public:
sc_signal_resolved pin1 {"pin1" |
tb |
public:
// Declaration of clock and reset parameters
sc_in < bool > clk;
sc_in < bool > rst;
// End of simulation signal.
sc_in < bool > program_end;
// Fetch enable signal.
sc_out < bool > fetch_en;
// CPU Reset
sc_out < bool > cpu_rst;
// Entry point
sc_out < unsigned > entry_point;
// TODO: removeme
/... |
plic |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_out<dev_config_type> o_cfg; // ... |
keyExpansion |
sc_in<sc_logic> key[128];
sc_out<sc_logic> w[1408];
sc_signal<sc_lv<1408>> w_lv;
sc_signal<sc_lv<128>> key_lv;
sc_lv<32> temp;
sc_lv<32> r;
sc_lv<32> rot;
sc_lv<32> x;
sc_lv<32> rconv;
sc_lv<32> new_k;
sc_lv<1408> w_temp;
SC_CTOR( keyExpansion ) {
SC_METHOD(eval);... |
st7735 |
sc_inout<gn_mixed> sda {"sda" |
cd4067 |
sc_in<bool> inh {"inh" |
apb_pnp |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_vector<sc_in<dev_config_type>> i_cfg; // ... |
RegIntBank |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<6>> i_radr1; // Port 1 read address
sc_out<sc_uint<RISCV_ARCH>> o_rdata1; // Port 1 rea... |
_sc_stream_buffer |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 |
_sc_stream_buffer_not_stream_while_write |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 |
add_one_wrapper |
public:
sc_in< bool > clk;
sc_in< bool > rst;
cynw::cynw_p2p_base_in <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > add_one_x;
cynw::cynw_p2p_base_out <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > add_one_return;
// These signals are used to connect structured ports or ports that need
/... |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Metho... |
gndemux |
sc_port< sc_signal_out_if<gn_mixed>,0 > pin {"pin" |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exe... |
simple_bus_master_blocking |
// ports
sc_in_clk clock;
sc_port<simple_bus_blocking_if> bus_port;
// constructor
simple_bus_master_blocking(sc_module_name name_
, unsigned int unique_priority
, unsigned int address
, bool lock
, int timeout)
: sc_module(name_... |
fetch |
sc_port <mem_if> p_mem;
sc_port <breg_if> p_breg;
sc_fifo_in < contexto*> execute_fetch;
sc_fifo_out < contexto* > fetch_decode;
void fetch_method(){
while(true){
recebimento = execute_fetch.read();
escrita = recebimento;
PC = (p_breg->read(31));
#ifdef RASTREIA_PC
cout << "PC = " << PC << e... |
GemmDriver |
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> dout1;
sc_fifo_in<DATA> dout2;
sc_fifo_in<DATA> dout3;
sc_fifo_in<DATA> dout4;
sc_fifo_out<DATA> din1;
sc_fifo_out<DATA> din2;
sc_fifo_out<DATA> din3;
sc_fifo_out<DATA> din4;
bool sent;
bool retval;
//States
int states[9];
sc_s... |
ACCNAME |
sc_in<bool> clock;
sc_in<bool> reset;
sc_in<unsigned int> start_acc;
sc_out<unsigned int> done_acc;
sc_in<bool> reset_acc;
sc_in<unsigned int> insn_count;
sc_in<unsigned int> insn_addr;
sc_in<unsigned int> input_addr;
sc_in<unsigned int> weight_addr;
sc_in<unsigned int> bias_addr;
sc_in<unsigne... |
InstrFetch |
sc_in<bool> i_clk;
sc_in<bool> i_nrst;
sc_in<bool> i_pipeline_hold;
sc_in<bool> i_mem_req_ready;
sc_out<bool> o_mem_addr_valid;
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_mem_addr;
sc_in<bool> i_mem_data_valid;
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_mem_data_addr;
sc_in<sc_uint<32>> i_mem_data;
... |
tb |
public:
sc_vector<sc_out<bool>> inp_a, inp_b;
sc_out<bool> inp_cin;
sc_vector<sc_in<bool>> sum;
sc_in<bool> co;
SC_HAS_PROCESS( tb );
bool a[6][4];
bool b[6][4];
tb( sc_module_name nm );
private:
void source();
void sink();
|
tb_top_imagedata_fix |
sc_clock clk;
sc_in<bool> iclk;
sc_signal<bool> reset;
typedef hwcore::pipes::sc_stream_imagedatafix<W, I, BW> stream_image_t;
typedef typename stream_image_t::din_T fifo_t;
stream_image_t imagefix_u0;
sc_fifo<fifo_t> din;
sc_fifo<fifo_t> dout;
sc_fifo<sc_uint<1> > enable;
SC_CTOR(tb_top_imagedata_fix) :... |
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <unsigned int> address;
sc_core::sc_in <uint8_t*> data_in;
sc_core::sc_in <unsigned int> req_size;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <uint8_t*> da... |
top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top |
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| |
InputSetup |
public:
sc_in_clk clk;
sc_in<bool> rst;
typedef SysPE::InputType InputType;
static const int N = SysArray::N; // # banks = N
static const int Entries = N*4; // # of entries per bank
static const int Capacity = N*Entries;
typedef ArbitratedScratchpad<InputType, Capacity, N, N, 0> MemT... |
xtea_RTL_testbench |
private:
void run();
public:
sc_in_clk clk;
sc_out< bool > rst;
sc_in<sc_uint<1> > dout_rdy; // output from xtea module
sc_in<sc_uint<32> > result0_in;
sc_in<sc_uint<32> > result1_in;
sc_out<sc_uint<1> > din_rdy; ... |
spimod |
public:
sc_out<bool> d_oen_o {"d_oen_o" |
EdgeDetector |
enum ed_icm_mode {
Any,
Pos,
Neg
|
Edge_Detector |
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<64> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
... |
MemAccess |
sc_in<bool> i_clk;
sc_in<bool> i_nrst;
sc_in<bool> i_e_valid; // Execution stage outputs are valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_e_pc; // Execution stage instruction pointer
sc_in<sc_uint<32>> i_e_instr; // Execution stage instruction value
... |
GemmDriver |
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> dout1;
sc_fifo_in<DATA> dout2;
sc_fifo_in<DATA> dout3;
sc_fifo_in<DATA> dout4;
sc_fifo_out<DATA> din1;
sc_fifo_out<DATA> din2;
sc_fifo_out<DATA> din3;
sc_fifo_out<DATA> din4;
bool sent;
bool retval;
//States
int states[9];
sc_s... |
top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top |
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| |
CacheTop |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Control path:
sc_in<bool> i_req_ctrl_valid; // Control request from CPU Core is valid
sc_in<sc_uint<RISCV_ARCH>> i_... |
RAM |
sc_in_clk CLK;
sc_in<bool> RESET_N;
sc_in<sc_uint<32>> ADR_I;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> VALID_I;
sc_in<bool> WE_I;
sc_in<sc_uint<2>> MEM_SIZE;
sc_out<sc_uint<32>> DAT_O;
//signals
sc_signal<sc_uint<4>> current_state;
sc_si... |
vip_spi_transmitter |
public:
sc_in<bool> i_nrst;
sc_in<bool> i_clk;
sc_in<bool> i_csn;
sc_in<bool> i_sclk;
sc_in<bool> i_mosi;
sc_out<bool> o_miso;
sc_out<bool> o_req_valid;
sc_out<bool> o_req_write;
sc_out<sc_uint<32>> o_req_addr;
sc_out<sc_uint<32>> o_req_wdata;
sc_in<bool> i_req_ready;
s... |
_sc_stream_stitching |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T din_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T dout_T;
sc_in<bool> clk, reset;
sc_fifo_in<din_T> din_buf;
sc_fifo_in<din_T> din;
sc_fifo_out<dout_T> dout;
sc_fifo_in<sc_uint<16> > ctrl_depth;
sc_fi... |
i2c |
public:
sc_out<bool> scl_en_o {"scl_en_o" |
Workgroup |
public:
sc_in<bool> i_cores_nrst; // System reset without DMI inteface
sc_in<bool> i_dmi_nrst; // Debug interface reset
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_trst;
sc_in<bool> i_tck;
sc_i... |
zeroenc |
public:
sc_in<sc_biguint<iwidth>> i_value; // Input value to encode
sc_out<sc_uint<shiftwidth>> o_shift; // First non-zero bit
void gen0();
SC_HAS_PROCESS(zeroenc);
zeroenc(sc_module_name name);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o... |
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
processing_engine_module |
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_scheduler_weight;
sc_fifo_in<float> from_scheduler_input;
sc_fifo_in< sc_uint<34> > from_scheduler_instructions;
sc_fifo_out<float> to_scheduler;
// STATES
sc_uint<30> state_length;
sc_uint<4> state_activation_... |
IP_RAM |
sc_in_clk CLK;
sc_in<bool> RESET_N;
sc_in<sc_uint<32>> DAT_I;
sc_in<sc_uint<32>> ADR_I;
sc_in<bool> CYC_I; // when asserted indicates that a valid bus cycle in progress
sc_in<sc_uint<2>> SEL_I; // select which words on DAT_O are valid
sc_in<bool> STB_I;
sc_in<bo... |
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