module_name stringlengths 1 2.17k | module_content stringlengths 6 11.3k |
|---|---|
ACCNAME |
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
// int rows=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
... |
tb |
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_HAS_PROCESS( tb );
tb(... |
x1_multiplier |
// input :
sc_in<sc_bv<320>> IN_RX0;
sc_in<bool> SELECT_HIGHER_BITS_RX0;
sc_in<bool> SIGNED_RES_RX0;
sc_in<bool> X02X1_EMPTY_SX0;
sc_in<bool> X12X2_POP_SX2;
// output :
sc_out<sc_bv<128>> RES_RX1;
sc_out<bool> SELECT_HIGHER_BITS_RX1;
... |
IP_RIVER |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface bus
sc_in<bool> ACK;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> GRANT;
sc_in<sc_uint<32>> ADR_I;
sc_out<sc_uint<32>> ADR;
sc_out<sc_uint<32>> DAT_O;
sc_out<sc_uint<2>> SEL;
sc_out<bool> STB;... |
s8 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s8_box();
SC_CTOR(s8)
{
SC_METHOD(s8_box);
sensitive << stage1_input;
}
|
icache |
// interface global
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface RiVer
sc_in<sc_uint<32> > ADR_SI;
sc_in<bool> ADR_VALID_SI;
sc_out<sc_bv<32> > INST_SIC;
sc_out<bool> STALL_SIC;
//interface wrapper
sc_in<sc_uint<32>> DT_SW;
sc_out<sc_uint<32>> A_SIC;
sc_out<boo... |
sc_dffrs_TB |
sc_clock clk;
sc_signal<bool> r, s, d, q;
Vdffrs* u_Vdffrs;
sc_trace_file* fp; // VCD file
SC_CTOR(sc_dffrs_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
u_Vdffrs = new Vdffrs("u_Vdffrs");
// Binding
... |
scClk |
sc_out<bool> clk{"clk_o" |
sc_beh_shifter_TB |
sc_clock clk;
sc_signal<bool> rst;
sc_signal<uint32_t> din, qout;
Vbeh_shifter* u_Vbeh_shifter;
sc_trace_file* fp; // SystemC VCD file
SC_CTOR(sc_beh_shifter_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
... |
cnn |
// typedef
typedef hwcore::cnn::top_cnn<P_data_W, P_data_P, P_input_BW_N, P_output_BW_N, P_pe_n, P_pe_bw_n, P_wbuf_size,
P_data_buf_clb_size, P_data_buf_clb_n, P_data_buf_shift_size, P_data_out_n,
P_pool_size, P_PE_pipeline_II, P_pe_pre_fifo_deep>
top... |
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<4> > Xin;
sc_signal<sc_uint<4> > Xout;
sc_signal<sc_uint<4> > Yin;
sc_signal<sc_uint<4> > Yout;
sc_signal<bool> Vld;
sc_signal<bool> Rdy;
#ifdef EMULATED
sc_signal<sc_uint<4> > E_Xout;
sc_signal<sc_uint<4> > ... |
mux_pcnt |
sc_port<sc_signal_in_if<bool>,0> mout_i {"mout_i" |
E_fir_pe |
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
#define N_TX 4
#define N_RX 3
void pe_thread(void)
{
uint8_t x, y, txPacket[N_TX], rxPacket... |
<DIRNAME>test |
/* Signals */
sc_signal<bool> led {"led" |
full_adder |
public: sc_in<bool> a, b, cin;
public: sc_out<bool> sum, cout;
//---------------------------------------
public: SC_CTOR(full_adder)
{
SC_METHOD(process);
sensitive << a << b << cin;
}
//---------------------------------------
private: void process()
{
bool aANDb, aXORb, cinANDaXORb;
aANDb = a.read... |
AXIS_ENGINE |
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> dout1;
sc_fifo_out<DATA> din1;
bool send;
bool recv;
int id;
void DMA_MMS2() {
while (1) {
while (!send) wait();
for (int i = 0; i < input_len; i++) {
int d = DMA_input_buffer[i + input_offset];
din1.write({d, 1});
... |
ACCNAME |
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
... |
readMifaretest |
/* Signals */
gn_signal_mix i2c_sda {"i2c_sda" |
SerialToSerialBTtest |
/* Signals */
sc_signal<bool> led {"led" |
ACCNAME |
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
... |
dcache |
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface processeur
sc_in<sc_uint<32>> DATA_ADR_SM;
sc_in<sc_uint<32>> DATA_SM;
sc_in<bool> LOAD_SM;
sc_in<bool> STORE_SM;
sc_in<bool> VALID_ADR_SM;
sc_in<sc_uint<2>> MEM_SIZE_SM;
sc_out<sc_uint<32>> DATA_SDC;
sc_out<bool> STALL_SDC; // if sta... |
pcnttest |
/* Signals */
sc_signal<bool> led {"led" |
ACCNAME |
sc_uint<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> dout3;
sc_fifo_out<DATA> dout4;
sc_signal<bool> read_inputs;
sc_signal<bool> rtake;
... |
HamReg |
HCGen *hgen; //this circuit generate a code word
SynGen *sgen; //this circuit calculate the syndrome
Corrector *corr; //this circuit correct and decode a word
//Ports
sc_in < bool > clk;
sc_in < sc_uint<15> > coded_din;
sc_out < sc_uint<15> > coded_dout;
sc_in < sc_uint<11> > din;
sc_out < sc_uint<11>... |
tb |
sc_in_clk clk;
sc_out< bool > rst;
cynw_p2p< input_data, ioConfig >::base_out out; /* from tb to dut. */
cynw_p2p< output_data, ioConfig >::base_in in; /* from dut to tb. */
stream_16X8::in <ioConfig> streamin;
stream_16X8::out <ioConfig> streamout;
FILE * ofile;
SC_CTOR( tb )
... |
sc_fir_pe |
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<16> > mul;
sc_signal<sc_uint<16> > rYin;
void pe_thread(void)
{
while (... |
x0_multiplier |
// input :
sc_in<sc_uint<32>> OP1_SE, OP2_SE;
sc_in<sc_uint<2>> EXE_CMD_RD;
sc_in<bool> X02X1_POP_SX1;
sc_in<bool> DEC2X0_EMPTY_SD;
// output :
sc_out<sc_bv<320>> RES_RX0;
sc_out<bool> SELECT_HIGHER_BITS_RX0;
sc_out<bool> SIGNED_RES_RX0;
sc_out<bo... |
s7 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s7_box();
SC_CTOR(s7)
{
SC_METHOD(s7_box);
sensitive << stage1_input;
}
|
buffercache |
sc_in<bool> RESET_N;
sc_in_clk CLK;
//INPUT from DCACHE
sc_in<bool> WRITE_OBUFF;
sc_in<bool> ACK;
sc_in<sc_uint<32>> DATA_C;
sc_in<sc_uint<32>> ADR_C;
sc_in<bool> STORE_C;
sc_in<bool> LOAD_C;
sc_in<sc_uint<2>> SIZE_C;
//Snoopy
sc_in<sc_uint<32>> ADR_I;
//OUTPUT
... |
desround |
sc_in<bool > clk;
sc_in<bool > reset;
sc_in<sc_uint<4> > iteration_i;
sc_in<bool > decrypt_i;
sc_in<sc_uint<32> > R_i;
sc_in<sc_uint<32> > L_i;
sc_in<sc_uint<56> > Key_i;
sc_out<sc_uint<32> > R_o;
sc_out<sc_uint<32> > L_o;
sc_out<sc_uint<56> > Key_o;
sc_out<sc_uint<6> > s... |
cchan |
sc_in<unsigned int> rx;
sc_out<unsigned int> tx;
sc_fifo<unsigned char> from;
sc_fifo<unsigned char> to;
void intake();
void outtake();
sc_time baudperiod;
void set_baud(unsigned int baudrate);
cchan(sc_module_name name, int tx_buffer_size, int rx_buffer_size):
rx("rx"), tx("tx"... |
NoximNoC |
// I/O Ports
sc_in_clk clock; // The input clock for the NoC
sc_in<bool> reset; // The reset signal for the NoC
// Signals
sc_signal <bool> req_to_east [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal... |
counters |
sc_in<sc_uint<8> > in1 , in2 , in3;
sc_in<bool> dec1 , dec2 , clock , load1 , load2;
sc_out<sc_uint<8> > count1 , count2;
sc_out<bool> ended;
sc_signal<bool> isOverflow1 , isOverflow2;
void handleCount1();
void handleCount2();
void updateEnded();
SC_CTOR(counters) {
isOverflow1.write(false);
isOverflow... |
alu |
sc_in<sc_uint<32>> OP1_SE, OP2_SE;
sc_in<bool> CIN_SE;
sc_in<sc_uint<2>> CMD_SE;
sc_out<sc_uint<32>> RES_SE;
void operation();
void trace(sc_trace_file * tf);
SC_CTOR(alu) {
SC_METHOD(operation);
sensitive << OP1_SE << OP2_SE << CIN_SE << CMD_SE;
}
|
i2c_slave_controller |
sc_inout<sc_logic> sda;
sc_inout<sc_logic> scl;
enum states {READ_ADDR, SEND_ACK, READ_DATA, WRITE_DATA, SEND_ACK2 |
dual_memory | |
sc_fir8 |
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
#ifdef EMULATED
sc_out<sc_uint<8> > E_Xout;
sc_out<sc_uint<16> > E_Yout;
#endif
// void fir8_thread(void)
// {
// }
#ifdef VER... |
dut |
// Declare the clock and reset ports
sc_in< bool > clk;
sc_in< bool > rst;
// Declare the input port and the output port.
// The template specializations <DT_*> configure the
// modular interfaces to carry the desired datatypes.
// LAB EXERCISE: Add a second parameter to select TLM I/O
... |
sc_fir_pe |
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<16> > y;
void pe_thread(void)
{
//sc_uint<16> y=0; // Beware! Do NOT u... |
s2 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s2_box();
SC_CTOR(s2)
{
SC_METHOD(s2_box);
sensitive << stage1_input;
}
|
s1 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s1_box();
SC_CTOR(s1)
{
SC_METHOD(s1_box);
sensitive << stage1_input;
}
|
System |
// clock and reset signals
sc_clock clk_sig;
sc_signal< bool > rst_sig;
// cynw_p2p channels
cynw_p2p< input_t > chan1;
cynw_p2p< output_t > chan2;
// Declare pointers for the testbench and dut modules
dut_wrapper *m_dut; // use the generated wrapper for all HLS modules
tb *m_tb;
// LAB EXERCISE: Declar... |
serial_tft |
sc_in<gn_mixed> sck {"sck" |
clkgen |
sc_out<bool> apb_clk {"apb_clk" |
Diviseur |
// input :
sc_in<sc_uint<32>> OP1_SE;
sc_in<sc_uint<32>> OP2_SE;
sc_in<sc_uint<2>> CMD_RD;
sc_in<bool> START_SE;
// output :
sc_out<sc_uint<32>> DIVIDER_RES_OUTPUT;
sc_out<bool> BUSY_SE;
sc_out<bool> DONE_SE;
// General interface:
sc_in_clk ... |
display |
sc_port < sc_csp_channel_in_if < system_display_payload > > system_display_port_in;
SC_CTOR(display)
{
SC_THREAD(main);
}
void main();
|
CounterTestbench |
// Inputs
sc_in<bool> clk;
sc_in<sc_uint<N> > count_out;
sc_in<bool> overflow_intr;
sc_in<bool> underflow_intr;
//Outputs
sc_out<bool> reset;
sc_out<bool> up_down_ctrl;
sc_out<bool> count_enable;
// Main function of the module
void do_testbench();
SC_CTOR(CounterTestbench){
SC_THREAD(do_... |
wb_ram_sc |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface with BUS
sc_in<sc_uint<32>> DAT_I;
sc_in<sc_uint<32>> ADR_I;
sc_in<bool> CYC_I; // when asserted indicates that a valid bus cycle in progress
sc_in<sc_uint<2>> SEL_I; // select which words on DAT_O are valid
sc_in<bool> ... |
e4067test |
/* Signals */
sc_signal<bool> led {"led" |
receiver)
//class receiver : public sc_module
{
/// Input port for datac from the transmitter
sc_in<Packet> datac;
/// Input port for the strobe from the transmitter
sc_in<sc_bit> strobe;
/// reset port
sc_in<bool> rst_n;
/// clock port
sc_in<bool> clk;
/// output port for the data to the receiver switch
sc_... |
sample_container = new bool*[2];
sample_container[0] = new bool[(m_N_T*2)+1];
sample_container[1] = new bool[(m_N_T*2)+1];
must_i_sample = new bool[(m_N_T*2)+1];
SC_METHOD(receiver_register);
//sensitive<<clk.pos()<<rst_n.neg();
sensitive<<output_update<<rst_n.neg();
SC_THREAD(strobe_analysis);
se... |
fir |
sc_in<bool> clk;
sc_in<bool> rst;
sc_in< sc_int<16> > inp;
sc_out< sc_int<16> > outp;
sc_in<bool> inp_sig_vld;
sc_in<bool> outp_sig_rdy;
sc_out<bool> inp_sig_rdy;
sc_out<bool> outp_sig_vld;
//Just prototype this here as you have a ... |
System |
// testbench and DUT modules
dut_wrapper *m_dut; // use the generated wrapper for all hls_modules
tb *m_tb;
// clock and reset signals
sc_clock clk_sig;
sc_signal< bool > rst_sig;
// cynw_p2p channels
cynw_p2p< input_t > in_chan1; // For data going into the design
cynw_p2p... |
stim_gen |
sc_port < sc_csp_channel_out_if < stimulus_system_payload > > stimulus_system_port_out;
SC_CTOR(stim_gen)
{
SC_THREAD(main);
}
void main();
|
ledctest |
/* Signals */
sc_signal<bool> led {"led" |
System |
// clock and reset signals
sc_clock clk_sig;
sc_signal< bool > rst_sig;
// cynw_p2p channels
cynw_p2p< input_t > in_chan_1; // For data going into the design
cynw_p2p< input_t > in_chan_2; // For data going into the design
cynw_p2p< output_t > out_chan; // For data coming out of the design
// The testbench a... |
sc_fir8 |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
V_fir_pe* u_fir_pe[N_PE_ARRAY];
sc_signal<sc_uint<4> > X[N_PE_ARR... |
fifo)
//class fifo : public sc_module
{
/// It is used to get input values from a file which represents the resource.
sc_in<Packet> FIFO_in;
/// reset signal
sc_in<sc_bit> rst_n;
/// Input of the resource ready signal. If the resource is ready (true) i can output values from the fifo every clock period.
sc_in<sc_... |
SC_METHOD(prc_fifo);
sensitive<<rst_n<<clkfifo; //is the same of having sensitive<<d<<empty
//dont_initialize();
FIFO_LastPosition=0;
for (i=0;i<10;i++)
FIFO_vector[i]=empty_NL_PDU;
FIFO_reg=empty_NL_PDU;
fifofile.open ("fifo.txt",ios::trunc);
fifofile << "SIMULATION STARTS NOW: "<<endl<<endl;
fif... |
s5 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s5_box();
SC_CTOR(s5)
{
SC_METHOD(s5_box);
sensitive << stage1_input;
}
|
DFTModule |
sc_in_clk clock;
sc_in<bool> f_Enable;
sc_in<bool> f_RxSamples;
sc_in<bool> f_Calculate;
sc_in<bool> Reset;
sc_in<int> N;
sc_in<double> Sample;
sc_out<double> OutReal;
sc_out<double> OutImg;
double* _Samples;
int _N;
int _Counter;
void DFT(void);
SC_CTOR(DFTMo... |
fpu_monitor |
#if MIXED_SIM
sc_in<sc_logic> clk;
sc_in<sc_logic> rst;
sc_in<sc_logic> mult_en; // Signals that a multiply computation step should be performed
sc_in<sc_logic> add_en; // Signals that an add computation step should be performed
sc_in<sc_lv<16> > srf_in; // Scalar... |
Producer |
sc_out<int> data;
int generatedNumber;
int i;
SC_CTOR(Producer){
data.initialize(42); //initialisiert den Ausgangsport mit dem angegebenen Wert (ansonsten 0)
SC_THREAD(produce);
}
void produce()
{
i = 0;
while(i < 10) {
generatedNumber = rand();
cout << "[" << sc_time_stamp() << "](" << name()... |
cpu |
sc_in<bool> clk;
sc_in<bool> reset;
axi_tc_in s_ctl;
axi_tc_out m_ctl;
int exitval;
void th_main()
{
if (reset.read() == RLEVEL) for (int i = 0; i < 2; i++) wait();
#if 0
printf("&s_ctl: %p\n", &s_ctl);
printf("s_gctl: %p\n", s_gctl);
// printf("sbrk(0): %p\n", sbrk(0));
{int var; printf("var: %p\... |
dcache |
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface processeur
sc_in<sc_uint<32>> DATA_ADR_SM;
sc_in<sc_uint<32>> DATA_SM;
sc_in<bool> LOAD_SM;
sc_in<bool> STORE_SM;
sc_in<bool> VALID_ADR_SM;
sc_in<sc_uint<2>> MEM_SIZE_SM;
sc_out<sc_uint<32>> DATA_SC;
sc_out<bool> STALL_SC; // if stall... |
des |
sc_in<bool > clk;
sc_in<bool > reset;
sc_in<bool > load_i;
sc_in<bool > decrypt_i;
sc_in<sc_uint<64> > data_i;
sc_in<sc_uint<64> > key_i;
sc_out<sc_uint<64> > data_o;
sc_out<bool > ready_o;
//Registers for iteration counters
sc_signal<sc_uint<4> > stage1_iter, next_stage1_ite... |
wrapper_mod)
//class wrapper_mod : public sc_module
{
private:
int m_N_left,m_N_right;
public:
///data input port of the left side of the wrapper
sc_in<Packet> L_datain;
///data output port of the left side of the wrapper
sc_out<Packet> L_dataout;
///data input port of the right side of the wrapper
sc_in<... |
tx_LtoR.datain(L_datain);
tx_LtoR.rst_n(rst_n);
tx_LtoR.clk(clkL);
tx_LtoR.full(L_full_s);
tx_LtoR.datac(L_datac_s);
tx_LtoR.strobe(L_strobe_s);
rx_LtoR.datac(L_datac_s);
rx_LtoR.strobe(L_strobe_s);
rx_LtoR.clk(clkR);
rx_LtoR.rst_n(rst_n);
rx_LtoR.dataout(R_dataout);
tx_RtoL.datain(R_datain);
... |
Blinktest |
/* Signals */
sc_signal<bool> led {"led" |
__TBUF_ |
sc_in< sc_logic> A;
sc_in< sc_logic> E;
sc_out< sc_logic> Y;
SC_CTOR(__TBUF_){
SC_METHOD(eval);
sensitive << A << E;
}
void eval(void){
if (E->read() == SC_LOGIC_1){
Y->write(A->read());
} else {
Y->write(SC_LOGIC_Z);
}
|
wb_river_mc |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface with BUS
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> ACK_I; // when asserted indicates the normal termination of a bus cycle
sc_out<sc_uint<32>> DAT_O;
sc_out<sc_uint<32>> ADR_O;
sc_out<sc_uint<2>> SEL_O; // select which words on D... |
id_driver |
sc_out<bool> rst;
sc_out<bool> rf_access; // Enables rd/wr to the RFs while not in PIM mode
// sc_out<bool> rf_wr_nrd; // Signals if reading (low) or writing (high)
sc_out<bool> decode_en; // Enables decoding of the next CRF instruction
sc_out<uint8_t>... |
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