module_name stringlengths 1 2.17k | module_content stringlengths 6 11.3k |
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SC_FIFO_OUT_TRANS |
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_out<hwcore::pipes::sc_data_stream_t<W> > data_source;
sc_signal<sc_logic> data_source_full_n;
sc_signal<sc_logic> data_source_write;
sc_signal<sc_lv<W> > data_source_0_din;
sc_signal<sc_lv<1> > data_source_1_din;
sc_signal<sc_lv<W / 8> > data_source_2_din;
sc_signal<sc_lo... |
dut_type_wrapper |
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_data_f;
sc_in< sc... |
jpg_output |
//-----------Internal variables-------------------
// const int Block_rows = 8;
// const int Block_cols = 8;
double *image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
int quantificator[8][8] = {// quantization table
{16, 11, 10, 16,... |
sc_TOP_SPW |
sc_clock CLOCK;
sc_signal<bool> RESET;
sc_signal<bool> LINK_START;
sc_signal<bool> LINK_DISABLE;
sc_signal<bool> AUTO_START;
sc_signal<sc_uint<4> > FSM_SPW_OUT;
sc_signal<sc_uint<4> > FSM_TX;
sc_signal<sc_uint<10> > CLOCK_GEN;
sc_signal<bool> E_SEND_DATA;
sc_signal<bool> BUFFER_READY;
sc_signal<sc_uint... |
BitsToBytes |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<1> > e;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(BitsToBytes)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
#if 1
while ( true )
{
... |
DummyCpu |
public:
sc_out<axi4_l1_out_type> o_msto;
sc_out<dport_out_type> o_dport;
sc_out<bool> o_flush_l2; // Flush L2 after D$ has been finished
sc_out<bool> o_halted; // CPU halted via debug interface
sc_out<bool> o_available; ... |
mon_CNN |
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > data_in;
SC_CTOR_DEFAULT(mon_CNN) {
SC_CTHREAD(mon_thread, clk.pos());
// sensitive << clk;
}
void mon_thread() {
reset.write(true);
wait();
wait();
wait();
wait();
wait();
wait();
wait();
res... |
wave_CNN |
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_out<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > data_out;
sc_out<sc_uint<16 + 1> > weight_ctrl; //, data_ctrl;
sc_out<sc_uint<16 + 1> > weight_ctrl_replay;
sc_out<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_out<sc_uint<16 + 1> > ctrl_window_size;
sc_out<sc_uint<16 + 1> > ctrl... |
tb_CNN |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_CNN wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > wave_2_u1;
sc_signal<sc_uint<31 + 1> > weight_ctrl; //, data_ctrl;
sc_signal<sc_uint<16 + 1> ... |
cu_monitor |
#if MIXED_SIM
sc_in<sc_logic> clk;
sc_in<sc_logic> rst;
sc_in<sc_logic> RD; // DRAM read command
sc_in<sc_logic> WR; // DRAM write command
sc_in<sc_logic> ACT; // DRAM activate command
// sc_in<sc_logic> RSTB; //
sc_in<sc_logic> AB_mode; // Signals if the All-Banks mode is e... |
dut_type_wrapper |
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_data_f;
sc_in< sc... |
cpu_sim |
sc_fifo_out<pipes::sc_data_stream_t<16*32> > dma_out;
sc_fifo_in<pipes::sc_data_stream_t<16*32> > dma_in;
//sc_out<uint32_t>
|
tb_cnn_top |
hf::sc_fifo_template<pipes::sc_data_stream_t<16*32> > cpu_sim_2_u1_dma;
cnn::top_cnn<> cnn_u1;
hf::sc_fifo_template<pipes::sc_data_stream_t<16*32> > u1_2_cpu_sim_dma;
|
mon_CNN |
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > data_in;
SC_CTOR_DEFAULT(mon_CNN) {
SC_CTHREAD(mon_thread, clk.pos());
// sensitive << clk;
}
void mon_thread() {
reset.write(true);
wait();
wait();
wait();
wait();
wait();
wait();
wait();
res... |
wave_CNN |
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_out<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > data_out;
sc_out<sc_uint<16 + 1> > weight_ctrl; //, data_ctrl;
sc_out<sc_uint<16 + 1> > weight_ctrl_replay;
sc_out<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_out<sc_uint<16 + 1> > ctrl_window_size;
sc_out<sc_uint<16 + 1> > ctrl... |
tb_CNN |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_CNN wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > wave_2_u1;
sc_signal<sc_uint<31 + 1> > weight_ctrl; //, data_ctrl;
sc_signal<sc_uint<16 + 1> ... |
TOP |
public:
// Clock and reset
sc_in<bool> clk;
sc_in<bool> rst;
// End of simulation signal.
sc_signal < bool > program_end;
// Fetch enable signal.
sc_signal < bool > fetch_en;
// CPU Reset
sc_signal < bool > cpu_rst;
// Entry point
sc_signal < unsigned > entry_point;
// TODO: removeme
// sc_signal < bool... |
execute |
// FlexChannel initiators
get_initiator< de_out_t > din;
put_initiator< exe_out_t > dout;
// Forward
sc_out< reg_forward_t > fwd_exe;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Thread prototype
void execute_th(void);
void perf_th(void);
// Support functions
sc_bv<XLEN> sign_extend_i... |
tb |
public:
// Declaration of clock and reset parameters
sc_in < bool > clk;
sc_in < bool > rst;
// End of simulation signal.
sc_in < bool > program_end;
// Fetch enable signal.
sc_out < bool > fetch_en;
// CPU Reset
sc_out < bool > cpu_rst;
// Entry point
sc_out < unsigned > entry_point;
// TODO: removeme
/... |
tb_pe |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W + 1 * W>::interface_T interface_W_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_out_T;
sc_clock clk;
sc_in<bool> iclk;
sc_... |
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <unsigned int> address;
sc_core::sc_in <uint8_t*> data_in;
sc_core::sc_in <unsigned int> req_size;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <uint8_t*> da... |
processing_engine_module |
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_scheduler_weight;
sc_fifo_in<float> from_scheduler_input;
sc_fifo_in< sc_uint<34> > from_scheduler_instructions;
sc_fifo_out<float> to_scheduler;
// STATES
sc_uint<30> state_length;
sc_uint<4> state_activation_... |
Edge_Detector |
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<64> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
... |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exe... |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Metho... |
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <int> address;
sc_core::sc_in <int> data_in;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <int> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core:... |
img_transmiter |
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_OUTPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data... |
jpg_output |
//-----------Internal variables-------------------
// const int Block_rows = 8;
// const int Block_cols = 8;
double *image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
int quantificator[8][8] = {// quantization table
{16, 11, 10, 16,... |
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Metho... |
SwitchStmHwModule |
// ports
sc_in<sc_uint<1>> a;
sc_in<sc_uint<1>> b;
sc_in<sc_uint<1>> c;
sc_out<sc_uint<1>> out;
sc_in<sc_uint<3>> sel;
// component instances
// internal signals
void assig_process_out() {
switch(sel.read()) {
case sc_uint<3>("0b000"): {
out.write(a.r... |
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
Rgb2Gray |
unsigned char r;
unsigned char g;
unsigned char b;
unsigned char gray_value;
SC_CTOR(Rgb2Gray)
{
}
void set_rgb_pixel(unsigned char r_val, unsigned char g_val, unsigned char b_val);
void compute_gray_value();
unsigned char obtain_gray_value();
|
memwb |
// FlexChannel initiators
get_initiator< exe_out_t > din;
put_initiator< mem_out_t > dout;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Enable fetch
sc_in<bool> fetch_en; // Used to synchronize writeback with fetch at reset.
// Instruction cache pointer to external memory
sc_uint<XLEN> ... |
communicationInterface |
sc_in<sc_uint<12> > inData;
sc_in<bool> clock , reset , clear;
sc_out<sc_uint<4> > payloadOut;
sc_out<sc_uint<8> > countOut , errorOut;
void validateData();
SC_CTOR(communicationInterface) {
SC_METHOD(validateData);
sensitive<<clock.pos();
}
|
Functional_bus |
//Input Port
sc_core::sc_in <unsigned int> request_address;
sc_core::sc_in <uint8_t*> request_data;
sc_core::sc_in <bool> flag_from_core;
sc_core::sc_in <bool> request_ready;
sc_core::sc_in <unsigned int> request_size;
sc_core::sc_in <uint8_t*> data_input_sensor[NUM_SENSORS];
sc_cor... |
Functional_bus |
//Input Port
sc_core::sc_in <int> request_address;
sc_core::sc_in <int> request_data;
sc_core::sc_in <bool> flag_from_core;
sc_core::sc_in <bool> request_ready;
sc_core::sc_in <int> data_input_sensor[NUM_SENSORS];
sc_core::sc_in <bool> go_sensors[NUM_SENSORS];
//Output Port
sc_c... |
seq_item_ams |
protected:
cv::Mat tx_img;
public:
// Input clock
sc_core::sc_in<bool> clk;
// Counters
sc_core::sc_in<unsigned int> hcount;
sc_core::sc_in<unsigned int> vcount;
// Output pixel
sc_core::sc_out<sc_uint<N> > o_red;
sc_core::sc_out<sc_uint<N> > o_green;
sc_core::sc_out<sc_uint<N> > o_blue;
SC_CTO... |
MIPS |
sc_in<bool> clk;
sc_port<readwrite_if> ioController;
uint32_t breg[32];
Bitmap bg;
SC_CTOR(MIPS) {
SC_METHOD(exec);
sensitive << clk.pos();
const char fn[] = "mandrill2.bmp";
const char mode[] = "rb";
breg[4] = (uint32_t)fn; breg[5] = (uint32_t)mode;
fileOpen();
... |
waveform |
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_out<DATA1024_t > source;
SC_CTOR(waveform)
{
SC_CTHREAD(waveform_thread,clk.pos());
}
void waveform_thread()
{
DATA1024_t tmp;
tmp.data = 0;
tmp.tlast = 0;
reset.write(true);
float numberGen = 0;
while(true)
{
wait();
reset.write(false);
... |
monitor |
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<DATA32_t > sink;
std::ofstream ofs;
SC_CTOR(monitor)
:ofs("test.txt", std::ofstream::out)
{
SC_CTHREAD(monitor_thread,clk.pos());
reset_signal_is(reset,true);
}
~monitor()
{
ofs.close();
}
void monitor_thread()
{
DATA32_t tmp;
unsigned countdo... |
Edge_Detector |
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<24> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
... |
Counter |
//------------------------------Module Inputs------------------------------
// Input clock
sc_in_clk clk;
// Reset bar (reset when 1'b0)
sc_in<bool> rstb;
// Starts the counter
sc_in<bool> enable;
// N-bit output of the counter
sc_out<sc_uint<N > > count_out;
//----------------... |
tb_cnn_2d |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
typedef sc_fixed<P_data_W, P_data_P> sc_data;
sc_data func(int a, int b, int c, int d) {
int tmp = ((d & 0xFF) << 24) | ((c & 0xFF) << 16) | ((b & 0xFF) << 8) | ((a & 0xFF) << 0);
return (sc_data)tmp;
... |
mon_bufferstreamer |
sc_fifo_out<sc_uint<31> > ctrl_out;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<16> > data_in;
SC_CTOR(mon_bufferstreamer) { SC_THREAD(mon_thread); }
void mon_thread() {
uint16_t data_gen = 0;
std::cout << "(mon) req. newset (start) " << std::endl;
ctrl_out.write(hwcore::pipes::sc_stream_buffer<>::ctrls::new... |
wave_bufferstreamer |
sc_fifo_out<hwcore::pipes::sc_data_stream_t<16> > data_out;
SC_CTOR(wave_bufferstreamer) { SC_THREAD(wave_thread); }
void wave_thread() {
hwcore::pipes::sc_data_stream_t<16> tmp;
for (int i = 0; i < test_size; i++) {
tmp.data = i;
std::cout << "(wave) write new data: " << i << std::endl;
tmp.tkeep =... |
tb_bufferstreamer |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
hwcore::pipes::sc_stream_buffer_not_stream_while_write<16> bs_u1;
wave_bufferstreamer wave;
mon_bufferstreamer mon;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > b... |
vga |
protected:
// Horizontal count
int h_count;
// Vertical count
int v_count;
public:
#ifndef USING_TLM_TB_EN
// Input clock
sc_core::sc_in<bool> clk;
#else
// Compute the clock time in seconds
const double CLK_TIME = 1.0 / static_cast<double>(CLK_FREQ);
// Internal clock
sc_core::sc_clock clk;
#endif... |
mon_split_and_merge |
sc_fifo_in<hwcore::pipes::sc_data_stream_t<16> > data_in;
SC_CTOR(mon_split_and_merge)
{
SC_THREAD(mon_thread);
}
void mon_thread()
{
for(int a=0;a<2;a++)
{
uint16_t data_gen = 0;
hwcore::pipes::sc_data_stream_t<16> tmp_in;
do
{
tmp_in = data_in.read();
std::cout << "(mon) got sig... |
wave_split_and_merge |
sc_fifo_out<hwcore::pipes::sc_data_stream_t<16> > data_out;
SC_CTOR(wave_split_and_merge)
{
SC_THREAD(wave_thread);
}
void wave_thread()
{
hwcore::pipes::sc_data_stream_t<16> tmp;
for (int i = 0; i < test_size; i++)
{
tmp.data = i;
std::cout << "(wave) write new data: " << i << std::endl;
... |
tb_split_and_merge |
#if __RTL_SIMULATION__
//DMA_performance_tester_rtl_wrapper u1;
#else
//DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_split_and_merge wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > wave_2_u1;
hwcore::pipes::sc_stream_splitter<16,split_N,false> u1_ss;
hwcore::hf::sc_st... |
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
hl5 |
public:
// Declaration of clock and reset signals
sc_in_clk clk;
sc_in < bool > rst;
//End of simulation signal.
sc_out < bool > program_end;
// Fetch enable signal.
sc_in < bool > fetch_en;
// Entry point
sc_in < unsigned > entry_point;
// TODO: removeme
// sc_out < bool > main_start;
// sc_out <... |
Filter |
//-----------------------------Local Variables-----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
/**
* @brief Default constructor for Filter
*/
SC_CTOR(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name... |
memory |
protected:
int *mem;
public:
sc_core::sc_in<bool> clk;
sc_core::sc_in<bool> we;
sc_core::sc_in<unsigned long long int> address;
sc_core::sc_in<sc_uint<24>> wdata;
sc_core::sc_out<sc_uint<24>> rdata;
// Constructor for memory
SC_CTOR(memory)
{
this->mem = new int[SIZE];
SC_METHOD(run);
... |
fedec |
public:
// FlexChannel initiators
put_initiator< de_out_t > dout;
get_initiator< mem_out_t > feed_from_wb;
// Forward
sc_in< reg_forward_t > fwd_exe;
// End of simulation signal.
sc_out < bool > program_end;
// Fetch enable signal.
sc_in < bool > fetch_en;
// Entry point
sc_in < unsigned > entry_point;
... |
scheduler_module |
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_dma_weight;
sc_fifo_in<float> from_dma_input;
sc_fifo_in< sc_uint<64> > from_dma_instructions;
sc_fifo_out<float> to_dma;
// PROCESSING ENGINES
sc_fifo_out< sc_uint<34> > npu_instructions[CORE];
sc_fifo_out<flo... |
sequenceDetectorTB |
sc_signal<bool> clock , reset , clear , input , output , state;
void clockSignal();
void resetSignal();
void clearSignal();
void inputSignal();
sequenceDetector* sd;
SC_CTOR(sequenceDetectorTB) {
sd = new sequenceDetector ("SD");
sd->clock(clock);
sd->reset(reset);
sd->clear(cl... |
img_receiver |
//Array for input image
unsigned char* input_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_receiver)
{
input_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_INPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, uns... |
img_receiver |
//Array for input image
unsigned char* input_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_receiver)
{
input_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_INPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, uns... |
FrameProcessing |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint< 8> > e;
sc_fifo_out< sc_uint<32> > addr;
sc_fifo_out< sc_uint<24> > rgbv;
SC_CTOR(FrameProcessing)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
cout << "(II) ... |
my_module1 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int <8> > e;
sc_fifo_out< sc_uint<32> > addr;
sc_fifo_out< sc_uint<24> > rgbv;
// sc_fifo_out< bool > detect1;
SC_CTOR(my_module1) :
mod("mod"),
// dbl("dbl"),
det("det"),
dow("dow"),
bit("bi... |
BMPWriter_fixed |
public:
sc_fifo_in< sc_uint<32> > addr;
sc_fifo_in< sc_uint<24> > rgbv;
SC_CTOR(BMPWriter_fixed)
{
SC_THREAD(do_gen);
}
~BMPWriter_fixed( )
{
string fn;
fn = "received_image_fixed";
string filename = fn + ".bmp";
if (fopen(filename.c_str(), "rb")== NU... |
vga |
protected:
// Horizontal count
int h_count;
// Vertical count
int v_count;
public:
#ifndef USING_TLM_TB_EN
// Input clock
sc_core::sc_in<bool> clk;
#else
// Compute the clock time in seconds
const double CLK_TIME = 1.0 / static_cast<double>(CLK_FREQ);
// Internal clock
sc_core::sc_clock clk;
#endif... |
execute |
// FlexChannel initiators
get_initiator< de_out_t > din;
put_initiator< exe_out_t > dout;
// Forward
sc_out< reg_forward_t > fwd_exe;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Thread prototype
void execute_th(void);
void perf_th(void);
// Support functions
sc_bv<XLEN> sign_extend_i... |
my_module |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int <8> > e;
sc_fifo_out< sc_uint<32> > addr;
sc_fifo_out< sc_uint<24> > rgbv;
SC_CTOR(my_module) :
mod("mod"),
// dbl("dbl"),
det("det"),
dow("dow"),
bit("bit"),
byt("byt"),
crc("... |
hello_world |
private int meaning_of_life; // easter egg
//SC_CTOR -- systemC constructor
SC_CTOR(hello_world) {
meaning_of_life=42;
}
void say_hello() {
cout << "Hello Systemc-2.3.1!\n";
}
void open_magic_box() {
cout << meaning_of_life << endl;
}
|
trames_separ1 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_in <bool> detect;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(trames_separ1)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
// #ifdef _DEBUG_SYNCHRO_
... |
DOUBLEUR_U |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out< sc_uint<8> > s1;
sc_fifo_out< sc_uint<8> > s2;
SC_CTOR(DOUBLEUR_U)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
whil... |
processing_engine_module |
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_scheduler_weight;
sc_fifo_in<float> from_scheduler_input;
sc_fifo_in< sc_uint<34> > from_scheduler_instructions;
sc_fifo_out<float> to_scheduler;
// STATES
sc_uint<30> state_length;
sc_uint<4> state_activation_... |
tb_pe |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W + 1 * W>::interface_T interface_W_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_out_T;
sc_clock clk;
sc_in<bool> iclk;
sc_... |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exe... |
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <int> address;
sc_core::sc_in <int> data_in;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <int> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core:... |
my_module2 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int <8> > e;
sc_fifo_out< sc_uint<32> > addr;
sc_fifo_out< sc_uint<24> > rgbv;
// sc_fifo_out< bool > detect1;
SC_CTOR(my_module2) :
mod("mod"),
// dbl("dbl"),
det("det"),
dow("dow"),
bit("bi... |
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <unsigned int> address;
sc_core::sc_in <uint8_t*> data_in;
sc_core::sc_in <unsigned int> req_size;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <uint8_t*> da... |
img_transmiter |
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_OUTPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data... |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Metho... |
Edge_Detector |
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<64> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
... |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Metho... |
tb |
public:
// Declaration of clock and reset parameters
sc_in < bool > clk;
sc_in < bool > rst;
// End of simulation signal.
sc_in < bool > program_end;
// Fetch enable signal.
sc_out < bool > fetch_en;
// CPU Reset
sc_out < bool > cpu_rst;
// Entry point
sc_out < unsigned > entry_point;
// TODO: removeme
/... |
Tripleur |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int<8> > e;
sc_fifo_out< sc_int<8> > s1;
sc_fifo_out< sc_int<8> > s2;
sc_fifo_out< sc_int<8> > s3;
SC_CTOR(Tripleur)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void... |
TOP |
public:
// Clock and reset
sc_in<bool> clk;
sc_in<bool> rst;
// End of simulation signal.
sc_signal < bool > program_end;
// Fetch enable signal.
sc_signal < bool > fetch_en;
// CPU Reset
sc_signal < bool > cpu_rst;
// Entry point
sc_signal < unsigned > entry_point;
// TODO: removeme
// sc_signal < bool... |
ModuleCompute |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int <8> > e;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(ModuleCompute)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
/*
template< int XW, int OW, bool OS >
void ac_sqrt(
ac_int<XW,false> x... |
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
mon_CNN |
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > data_in;
SC_CTOR_DEFAULT(mon_CNN) {
SC_CTHREAD(mon_thread, clk.pos());
// sensitive << clk;
}
void mon_thread() {
reset.write(true);
wait();
wait();
wait();
wait();
wait();
wait();
wait();
res... |
wave_CNN |
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_out<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > data_out;
sc_out<sc_uint<16 + 1> > weight_ctrl; //, data_ctrl;
sc_out<sc_uint<16 + 1> > weight_ctrl_replay;
sc_out<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_out<sc_uint<16 + 1> > ctrl_window_size;
sc_out<sc_uint<16 + 1> > ctrl... |
tb_CNN |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_CNN wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > wave_2_u1;
sc_signal<sc_uint<31 + 1> > weight_ctrl; //, data_ctrl;
sc_signal<sc_uint<16 + 1> ... |
jpg_output |
//-----------Internal variables-------------------
// const int Block_rows = 8;
// const int Block_cols = 8;
double *image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
int quantificator[8][8] = {// quantization table
{16, 11, 10, 16,... |
Detecteur |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
// sc_fifo_in < sc_uint<8> > e2;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(Detecteur):
s_calc("s_calc"),
t_sep("t_sep"),
dbl("dbl"),
dbl2scalc("dbl2scalc",1024),
dbl2tsep("dbl2tsep",1024),
detect("... |
Rgb2Gray |
unsigned char r;
unsigned char g;
unsigned char b;
unsigned char gray_value;
SC_CTOR(Rgb2Gray)
{
}
void set_rgb_pixel(unsigned char r_val, unsigned char g_val, unsigned char b_val);
void compute_gray_value();
unsigned char obtain_gray_value();
|
DownSampling |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(DownSampling)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
const uint8_t scale = 2;
#if 1
... |
BitsToBytes |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<1> > e;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(BitsToBytes)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
#if 1
while ( true )
{
... |
Seuil_calc |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out <bool> detect;
SC_CTOR(Seuil_calc)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
// #ifdef _DEBUG_SYNCHRO_
// uint64_t counter = 0;
// ... |
Functional_bus |
//Input Port
sc_core::sc_in <int> request_address;
sc_core::sc_in <int> request_data;
sc_core::sc_in <bool> flag_from_core;
sc_core::sc_in <bool> request_ready;
sc_core::sc_in <int> data_input_sensor[NUM_SENSORS];
sc_core::sc_in <bool> go_sensors[NUM_SENSORS];
//Output Port
sc_c... |
BitDecider |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out< sc_uint<1> > s;
SC_CTOR(BitDecider)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
while ( true )
{
con... |
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
memwb |
// FlexChannel initiators
get_initiator< exe_out_t > din;
put_initiator< mem_out_t > dout;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Enable fetch
sc_in<bool> fetch_en; // Used to synchronize writeback with fetch at reset.
// Instruction cache pointer to external memory
sc_uint<XLEN> ... |
rbm |
sc_in<bool> clk; // clock
sc_in<bool> rst; // reset
// DMA requests interface from memory to device
sc_out<u32> rd_index; // array index (offset from base address)
sc_out<u32> rd_length; // burst size
sc_out<bool> rd_request; // transaction request
sc_in... |
CRCCheck |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(CRCCheck)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
cout << "(II) CRCCheck :: START" << endl;
sc_uint<8> ib... |
Functional_bus |
//Input Port
sc_core::sc_in <unsigned int> request_address;
sc_core::sc_in <uint8_t*> request_data;
sc_core::sc_in <bool> flag_from_core;
sc_core::sc_in <bool> request_ready;
sc_core::sc_in <unsigned int> request_size;
sc_core::sc_in <uint8_t*> data_input_sensor[NUM_SENSORS];
sc_cor... |
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