module_name stringlengths 1 2.17k | module_content stringlengths 6 11.3k |
|---|---|
System |
public:
/* Instantiated sub-modules. We instantiate the dut_wrapper module,
rather than the dut module directly. This is because the dut
module can exist in multiple versions (such as behavioral and
synthesized RTL), and the wrapper module automatically selects
between the versions bas... |
Sram |
sc_in<uint32_t> i_sram_addr;
sc_in<uint32_t> i_sram_dq;
sc_out<uint32_t> o_sram_dq;
sc_in<bool> i_sram_ce_n;
sc_in<bool> i_sram_we_n;
sc_in<bool> i_sram_oe_n;
sc_in<bool> i_sram_ub_n;
sc_in<bool> i_sram_lb_n;
SC_CTOR(Sram) {
SC_METHOD(process);
sensitive << i_sram_a... |
dut_type_wrapper |
public:
#if defined ( ioConfig_TLM )
sc_in< bool > clk;
sc_in< bool > rst;
#else
sc_in< bool > clk;
sc_in< bool > rst;
#endif
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
#if defined ( ioConfig_TLM )
#el... |
vip_uart_receiver |
public:
sc_in<bool> i_nrst;
sc_in<bool> i_clk;
sc_in<bool> i_rx;
sc_out<bool> o_rdy;
sc_in<bool> i_rdy_clr;
sc_out<sc_uint<8>> o_data;
void comb();
void registers();
SC_HAS_PROCESS(vip_uart_receiver);
vip_uart_receiver(sc_module_name name,
bool async_re... |
TOP |
public:
// Clock and reset
sc_in<bool> clk;
sc_in<bool> rst;
// End of simulation signal.
sc_signal < bool > program_end;
// Fetch enable signal.
sc_signal < bool > fetch_en;
// CPU Reset
sc_signal < bool > cpu_rst;
// Entry point
sc_signal < unsigned > entry_point;
// TODO: removeme
// sc_signal < bool... |
cdc_axi_sync_tech |
public:
sc_in<bool> i_xslv_clk; // system clock
sc_in<bool> i_xslv_nrst; // system reset
sc_in<axi4_slave_in_type> i_xslvi; // system clock
sc_out<axi4_slave_out_type> o_xslvo; // system clock
sc... |
sdctrl_cache |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Data path:
sc_in<bool> i_req_valid;
sc_in<bool> i_req_write;
sc_in<sc_uint<CFG_SDCACHE_ADDR_BITS>> i_req_addr;
sc_in<sc_uint<64>> i_r... |
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <int> address;
sc_core::sc_in <int> data_in;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <int> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core:... |
testbench)
// {
// public:
// // Clock
// sc_clock clk;
//
// // Interconnect
// sc_in_clk clk;
// sc_signal<bool> rst;
// sc_signal<int> datain;
// sc_signal<int> dataout;
//
// // Design Under Test (DUT)
// CCS_DESIGN(adder) adder_INST;
//
// ... |
// SC_THREAD(reset_driver);
// }
//
// // Active-high Asynchronous reset driver
// void reset_driver() {
// rst.write(1);
// wait(clk.period() * 1.5); // wait 1.5 clock cycles
// std::ostringstream msg;
// msg << "De-asserting reset signal '" << rst.name() << "' @ " << sc_time_stamp();
// ... |
img_transmiter |
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_OUTPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data... |
InstrExecute |
sc_in<bool> i_clk;
sc_in<bool> i_nrst; // Reset active LOW
sc_in<bool> i_pipeline_hold; // Hold execution by any reason
sc_in<bool> i_d_valid; // Decoded instruction is valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_d_pc; // Instruction point... |
pn532_base |
/* Signals */
sc_out<gn_mixed> irq {"irq" |
decod |
/*****************************************************
Interface with REG
******************************************************/
// adresses of Rs and Rd
sc_out<sc_uint<6>> RADR1_SD;
sc_out<sc_uint<6>> RADR2_SD;
// Data read in registers
sc_in<sc_uint<32>> RDATA1_SR;
... |
jpg_output |
//-----------Internal variables-------------------
// const int Block_rows = 8;
// const int Block_cols = 8;
double *image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
int quantificator[8][8] = {// quantization table
{16, 11, 10, 16,... |
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
simple_bus_master_direct |
// ports
sc_in_clk clock;
sc_port<simple_bus_direct_if> bus_port;
SC_HAS_PROCESS(simple_bus_master_direct);
// constructor
simple_bus_master_direct(sc_module_name name_
, unsigned int address
, int timeout
, bool verbose = t... |
decod |
/*****************************************************
Interface with REG
******************************************************/
// adresses of Rs and Rd
sc_out<sc_uint<6>> RADR1_SD;
sc_out<sc_uint<6>> RADR2_SD;
// Data read in registers
sc_in<sc_uint<32>> RDATA1_SR;
... |
axi_sram |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_out<dev_config_type> o_cfg; // ... |
Timer |
sc_in<bool> at, reset;
sc_in<bool> clk;
sc_out<bool> IL, IC;
SC_CTOR(Timer){
counter = 0;
SC_METHOD(proc);
sensitive << reset << at << clk.pos();
SC_METHOD(printcounter);
sensitive << clk.pos();
}
private:
void proc();
void printcounter();
int counter;
|
subBytes |
sc_in<sc_logic> in[128];
sc_out<sc_logic> out[128];
sbox* sub_Bytes_0;
sbox* sub_Bytes_1;
sbox* sub_Bytes_2;
sbox* sub_Bytes_3;
sbox* sub_Bytes_4;
sbox* sub_Bytes_5;
sbox* sub_Bytes_6;
sbox* sub_Bytes_7;
sbox* sub_Bytes_8;
sbox* sub_Bytes_9;
sbox* sub_Bytes_10;
... |
shifter |
sc_in<sc_uint<32>> DIN_SE; // input
sc_in<sc_uint<5>> SHIFT_VAL_SE; // shift value
sc_in<sc_uint<2>> CMD_SE; // command
/*
Command value :
- 0 : Shift Left Logical (sll)
- 1 : Shift Right Logical (srl)
- 2 : Shift Right Arithmetic (sra)
*/
sc_out<sc... |
Rgb2Gray |
unsigned char r;
unsigned char g;
unsigned char b;
unsigned char gray_value;
SC_CTOR(Rgb2Gray)
{
}
void set_rgb_pixel(unsigned char r_val, unsigned char g_val, unsigned char b_val);
void compute_gray_value();
unsigned char obtain_gray_value();
|
ic_axi4_to_l1 |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// AXI4 port
sc_in<axi4_master_out_type> i_xmsto;
sc_out<axi4_master_in_type> o_xmsti;
// L1 port
sc_in<axi4_l1_in_type> i_l1i;
sc_o... |
apb_uart |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_out<dev_config_type> o_cfg; // ... |
execute |
// FlexChannel initiators
get_initiator< de_out_t > din;
put_initiator< exe_out_t > dout;
// Forward
sc_out< reg_forward_t > fwd_exe;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Thread prototype
void execute_th(void);
void perf_th(void);
// Support functions
sc_bv<XLEN> sign_extend_i... |
execute |
sc_port <mem_if> p_mem;
sc_port <breg_if> p_breg;
sc_fifo_in < contexto* > decode_execute;
sc_fifo_out < contexto*> execute_fetch;
void execute_method(){
while(true){
recebimento = decode_execute.read();
escrita = recebimento;
e_rs2 = recebimento->rs2;
e_rs1 = recebimento-> rs1;
e_rd = recebim... |
simple_bus_master_direct |
// ports
sc_in_clk clock;
sc_port<simple_bus_direct_if> bus_port;
// constructor
simple_bus_master_direct(sc_module_name name_
, unsigned int address
, int timeout
, bool verbose = true)
: sc_module(name_)
, m_address(... |
ic_csr_m2_s1 |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// master[0]:
sc_in<bool> i_m0_req_valid;
sc_out<bool> o_m0_req_ready;
sc_in<sc_uint<CsrReq_TotalBits>> i_m0_req_type;
sc_in<sc_uint<12>... |
sdctrl_cmd_transmitter |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<bool> i_sclk_posedge;
sc_in<bool> i_sclk_negedge;
sc_in<bool> i_cmd;
sc_out<bool> o_cmd;
sc_out<bool> o_cmd_dir;
sc_out<bool> ... |
Shifter |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<4>> i_mode; // operation type: [0]0=rv64;1=rv32;[1]=sll;[2]=srl;[3]=sra
sc_in<sc_uint<RISCV_ARCH>> i_a1;... |
tb |
public:
sc_out<bool> inp_a[4], inp_b[4], inp_cin;
sc_in<bool> sum[4], co;
SC_HAS_PROCESS( tb );
bool a[6][4];
bool b[6][4];
tb( sc_module_name nm );
private:
void source();
void sink();
|
dut_wrapper |
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > finish;
cynw::cynw_p2p_base_out <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > find_max_x_out;
cynw::cynw_p2p_base_in <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > find_max_return_in;
// These signals are used to connect structur... |
axictrl_bus0 |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_out<dev_config_type> o_cfg; // Slave config descriptor
sc_vector<sc_in<axi4_master_out_type>> i_xmsto; // AXI4 m... |
tta_mem_arbiter |
/*MODULE INPUT INTERFACE */
sc_in<bool> clk;
sc_in<bool> rst_n;
sc_in<sc_bv<dataw_g/8> > bit_wr_x[ports_g];
sc_in<bool> en_x[ports_g];
sc_in<bool> wr_x[ports_g];
sc_in<sc_bv<dataw_g> > d[ports_g];
sc_in<sc_bv<addrw_g> > addr[ports_g];
/*MODULE OUTPUT INTERFACE */
sc_out<sc_bv... |
TagMem |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<abus>> i_addr;
sc_in<sc_uint<(1 << lnbits)>> i_wstrb;
sc_in<sc_biguint<(8 * (1 << lnbits))>> i_wdata;
sc_in<sc_uint<flbits>> i... |
filter_load |
SC_MODULE_CLK_RESET_SIGNAL;
sc_out<sc_fixed<W_WIDTH,P_DATA> > Wout[3*3];
SC_CTOR_DEFAULT(filter_load)
{
SC_CTHREAD(thread_filter_load, clk.pos());
reset_signal_is(reset,true);
}
void thread_filter_load()
{
sc_fixed<W_WIDTH,P_DATA> coeffs[N_ROWS * N_ROWS] = {1.0f, 0.0f, -1.0f,... |
TB_imfilter_top |
sc_clock clk;
sc_signal<bool> reset;
template<int W>
using imread = hwcore::tb::imread_func_fx<W,W/2>;
template<int W>
using imwrite = hwcore::tb::imwrite_func_fx<W,W/2>;
template<int W=TB_IMFILTER_W, int depth=16>
using fifo=hwcore::hf::sc_fifo_template< hwcore::pipes::sc_data_stream_... |
ALEXNET |
CONV_RELU_1 m_CONV_RELU_1;
MAX_POOLING_1 m_MAX_POOLING_1;
CONV_RELU_2 m_CONV_RELU_2;
MAX_POOLING_2 m_MAX_POOLING_2;
CONV_RELU_3 m_CONV_RELU_3;
CONV_RELU_4 m_CONV_RELU_4;
CONV_RELU_5 m_CONV_RELU_5;
MAX_POOLING_3 m_MAX_POOLING_3;
LINEAR_RELU_1 m_LINEAR_RELU_1;
LINEAR_RELU_2 m_LINE... |
HW_Quant |
public:
//constructor
SC_CTOR(HW_Quant) {
//instantiate the Quantize thread
SC_THREAD(Quant_thread);
}
//define the Quantize thread method
void Quant_thread();
//TODO: define the FIFO buffer interfaces
//TODO: name them InBuffer and OutBuffer
sc_fifo_in<Block> InBuffer;
sc_fifo_out<Block> OutBuffer;
... |
lenet |
sc_in_clk clock;
sc_in<bool> reset;
sc_out<bool> rom_rd;
sc_out<bool> ram_wr;
sc_out<sc_uint<16> > rom_addr;
sc_out<sc_uint<16> > ram_addr;
sc_in<TYPE > rom_data_in; // TYPE
sc_in<TYPE > ram_data_in; // TYPE
sc_out<TYPE > ram_data_out; // TYPE
sc_out<TYPE > result; // TYPE
sc_out<bool> valid;
void ... |
Sram |
sc_in<uint32_t> i_sram_addr;
sc_in<uint32_t> i_sram_dq;
sc_out<uint32_t> o_sram_dq;
sc_in<bool> i_sram_ce_n;
sc_in<bool> i_sram_we_n;
sc_in<bool> i_sram_oe_n;
sc_in<bool> i_sram_ub_n;
sc_in<bool> i_sram_lb_n;
SC_CTOR(Sram) {
SC_METHOD(process);
sensitive << i_sram_a... |
xtea_RTL_testbench |
private:
void run();
public:
sc_in_clk clk;
sc_out< bool > rst;
sc_in<sc_uint<1> > dout_rdy; // output from xtea module
sc_in<sc_uint<32> > result0_in;
sc_in<sc_uint<32> > result1_in;
sc_out<sc_uint<1> > din_rdy; ... |
fetch |
sc_port <mem_if> p_mem;
sc_port <breg_if> p_breg;
sc_fifo_in < contexto*> execute_fetch;
sc_fifo_out < contexto* > fetch_decode;
void fetch_method(){
while(true){
recebimento = execute_fetch.read();
escrita = recebimento;
PC = (p_breg->read(31));
#ifdef RASTREIA_PC
cout << "PC = " << PC << e... |
gndemux |
sc_port< sc_signal_out_if<gn_mixed>,0 > pin {"pin" |
sdctrl_crc16 |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<bool> i_clear; // Clear CRC register;
sc_in<bool> i_next; // Shift enab... |
RegIntBank |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<6>> i_radr1; // Port 1 read address
sc_out<sc_uint<RISCV_ARCH>> o_rdata1; // Port 1 rea... |
_sc_stream_buffer |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 |
_sc_stream_buffer_not_stream_while_write |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 |
dut |
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 11 > > dout_data;
sc_out< bool > mem_WE0;
sc_out< sc_uint< 8 > > mem_DIN0;
sc_in< sc_uint< 8 > > mem_DOUT0;
sc_out... |
dut |
public:
sc_in< bool > clk;
sc_in< bool > rst;
cynw::cynw_p2p_base_in <sc_dt::sc_uint <(int)8 >, CYN::cyn_enum <(int)1 > > din;
cynw::cynw_p2p_base_out <sc_dt::sc_uint <(int)11 >, CYN::cyn_enum <(int)1 > > dout;
RAM_64x8::port <CYN::cyn_enum <(int)1 >, sc_dt::sc_uint <(int)8 >, (HLS::HLS_INDEX_MAPPING_OPTIONS)256 ... |
dut_wrapper |
public:
sc_in< bool > clk;
sc_in< bool > rst;
cynw::cynw_p2p_base_in <sc_dt::sc_uint <(int)8 >, CYN::cyn_enum <(int)1 > > din;
cynw::cynw_p2p_base_out <sc_dt::sc_uint <(int)11 >, CYN::cyn_enum <(int)1 > > dout;
RAM_64x8::port <CYN::cyn_enum <(int)1 >, sc_dt::sc_uint <(int)8 >, (HLS::HLS_INDEX_MAPPING_OPTIONS)256... |
dut_wrapper_r |
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 11 > > dout_data;
sc_out< bool > mem_WE0;
sc_out< sc_uint< 8 > > mem_DIN0;
sc_in< sc_uint< 8 > > mem_DOUT0;
sc_ou... |
top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top |
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| |
or_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
|
or_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
|
top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top |
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| |
ic_dport |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// DMI connection
sc_in<sc_uint<CFG_LOG2_CPU_MAX>> i_hartsel; // Selected hart index
sc_in<bool> i_haltreq;
sc_in<bool> i_resume... |
RAM |
sc_in_clk CLK;
sc_in<bool> RESET_N;
sc_in<sc_uint<32>> ADR_I;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> VALID_I;
sc_in<bool> WE_I;
sc_in<sc_uint<2>> MEM_SIZE;
sc_out<sc_uint<32>> DAT_O;
//signals
sc_signal<sc_uint<4>> current_state;
sc_si... |
dut_type_wrapper |
public:
#if defined ( ioConfig_TLM )
sc_in< bool > clk;
sc_in< bool > rst;
#else
sc_in< bool > clk;
sc_in< bool > rst;
#endif
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
#if defined ( ioConfig_TLM )
#el... |
img_transmiter |
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_OUTPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data... |
i2c |
public:
sc_out<bool> scl_en_o {"scl_en_o" |
FIFO |
enum ic_addresses {
ICCONF = 0x18,
ICBUF = 0x1C
|
AESLCFUComp |
public:
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR( AESLCFUComp );
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> *super;
virtual void sanity_check() {}
virtual sc_lv<DOUT_WIDTH>
compu... |
AESLFUComp |
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> core;
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
/// Dont use stage_regvec[0].
sc_signal< sc... |
AESLCFUComp_seq |
public:
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR( AESLCFUComp_seq );
AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> *super;
virtual void sanity_check() {}
virtual sc_lv<DOUT_WIDTH>
... |
AESLFUComp_seq |
AESLCFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> core;
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_logic > start;
sc_in< sc_logic > done;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH>... |
AESLCFUMOComp |
public:
sc_in< sc_lv<OPC_WIDTH> > opcode;
sc_in< sc_lv<DIN_WIDTH> > din;
sc_out< sc_lv<DOUT_WIDTH> > dout;
public:
SC_CTOR( AESLCFUMOComp ) {
assert(OPC_WIDTH > 0 && DIN_WIDTH > 0 && DOUT_WIDTH > 0
&& NUM_STAGE == 1);
SC_METHOD( thread_compute );
... |
AESLFUMultiCycle |
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<OPC_WIDTH> > opcode;
sc_in< sc_lv<DIN_WIDTH> > din;
sc_out< sc_lv<DOUT_WIDTH> > dout;
public:
SC_CTOR( AESLFUMultiCycle ) {
assert(OPC_WIDTH > 0 && DIN_WIDTH > 0 && DOUT_WIDTH > 0
... |
CFUUnaryOp |
public:
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR(CFUUnaryOp) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, 1, DIN0_WIDTH, DOUT_WIDTH>("u_U");
mMCModule->opcode(sigone);
mMCModule->din(din0);
mMCModule->dout(d... |
FUUnaryOp |
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR(FUUnaryOp) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, 1, DIN0_WIDTH, DOUT_WIDTH>("u_U");
mMCMo... |
FUMOUnaryOp |
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<OPC_WIDTH> > opcode;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR(FUMOUnaryOp) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, OPC_WIDTH... |
Monitor |
sc_in_clk clk;
sc_in < bool > rst;
sc_in < DATA_TYPE > data_in;
sc_in < bool > data_valid;
void monitor();
int x, cycle;
SC_CTOR( Monitor )
{
x = 0;
cycle = 0;
SC_METHOD( monitor );
sensitive << clk.pos();
}
|
Showcase0 |
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contO... |
CONV_RELU_1 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 150528 |
MAX_POOLING_1 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 193600 |
CONV_RELU_2 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 46656 |
MAX_POOLING_2 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 139968 |
CONV_RELU_3 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 32448 |
CONV_RELU_4 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 64896 |
CONV_RELU_5 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 43264 |
MAX_POOLING_3 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 43264 |
LINEAR_RELU_1 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 9216 |
LINEAR_RELU_2 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 4096 |
LINEAR_3 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 4096 |
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
sdctrl_cache |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Data path:
sc_in<bool> i_req_valid;
sc_in<bool> i_req_write;
sc_in<sc_uint<CFG_SDCACHE_ADDR_BITS>> i_req_addr;
sc_in<sc_uint<64>> i_r... |
pch_monitor |
#if MIXED_SIM
sc_in<sc_logic> clk;
sc_in<sc_logic> rst;
sc_in<sc_logic> RD; // DRAM read command
sc_in<sc_logic> WR; // DRAM write command
sc_in<sc_logic> ACT; // DRAM activate command
// sc_in<sc_logic> RSTB; ... |
_sc_stream_stitching |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T din_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T dout_T;
sc_in<bool> clk, reset;
sc_fifo_in<din_T> din_buf;
sc_fifo_in<din_T> din;
sc_fifo_out<dout_T> dout;
sc_fifo_in<sc_uint<16> > ctrl_depth;
sc_fi... |
PowerButton |
//port(s) connected to outside
sc_in<bool> pt_pressed;
//port(s) inside the phone
sc_out<bool> shortPress;
sc_out<bool> longPress;
//internal variables
sc_time lastTimeStamp;
sc_time interval_3S;
//constructor
SC_HAS_PROCESS(PowerButton);
PowerButton(sc_module_name name){
shortPress.initialize(false... |
{project} | {\n"
// " extern int instr_cntr;\n"
" std::ofstream instr_log;\n"
" std::ofstream instr_update_log;\n" // add instruction state update logging
" int GetInstrCntr();\n"
" void IncrementInstrCntr();\n"
" void LogIn... |
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
CacheTop |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Control path:
sc_in<bool> i_req_ctrl_valid; // Control request from CPU Core is valid
sc_in<sc_uint<RISCV_ARCH>> i_... |
InstrExecute |
sc_in<bool> i_clk;
sc_in<bool> i_nrst; // Reset active LOW
sc_in<bool> i_pipeline_hold; // Hold execution by any reason
sc_in<bool> i_d_valid; // Decoded instruction is valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_d_pc; // Instruction point... |
TagMem |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<abus>> i_addr;
sc_in<sc_uint<(1 << lnbits)>> i_wstrb;
sc_in<sc_biguint<(8 * (1 << lnbits))>> i_wdata;
sc_in<sc_uint<flbits>> i... |
ex20_parameter_owner |
public:
/**
* @fn ex20_parameter_owner()
* @brief The class constructor
* @return void
*/
SC_CTOR(ex20_parameter_owner) {
XREPORT("Prior to " << sc_time_stamp());
XREPORT("[OWNER C_TOR] : Creating new integer type cci-parameter with"
" default value 10");
int_param = n... |
SC_FIFO_IN_TRANS |
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<W> > data_sink;
sc_signal<sc_logic> data_sink_empty_n;
sc_signal<sc_logic> data_sink_read;
sc_signal<sc_lv<W> > data_sink_0_dout;
sc_signal<sc_lv<1> > data_sink_1_dout;
sc_signal<sc_lv<W / 8> > data_sink_2_dout;
sc_signal<sc_logic> data_s... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.