module_name stringlengths 1 2.17k | module_content stringlengths 6 11.3k |
|---|---|
gate |
// inputs
sc_in<bool> inA, inB;
// outputs
sc_out<bool> out;
// C function
void do_something()
{
out.write(inA.read() || inB.read());
}
// constructor
SC_CTOR(gate)
{
// register method
SC_METHOD(do_something);
}
|
counters |
sc_in<sc_uint<8> > in1 , in2 , in3;
sc_in<bool> dec1 , dec2 , clock , load1 , load2;
sc_out<sc_uint<8> > count1 , count2;
sc_out<bool> ended;
sc_signal<bool> isOverflow1 , isOverflow2;
void handleCount1();
void handleCount2();
void updateEnded();
SC_CTOR(counters) {
isOverflow1.write(false);
isOverflow... |
communicationInterfaceTB |
sc_signal<sc_uint<12> > inData;
sc_signal<bool> clock , reset , clear;
sc_signal<sc_uint<4> > payloadOut;
sc_signal<sc_uint<8> > countOut , errorOut;
void clockSignal();
void clearSignal();
void resetSignal();
void inDataSignal();
communicationInterface* cI;
SC_CTOR(communicationInterfaceTB) {
cI = ne... |
TLM |
Initiator *initiator;
Memory *memory;
sc_core::sc_in<bool> IO_request;
SC_HAS_PROCESS(TLM);
TLM(sc_module_name tlm) // Construct and name socket
{
// Instantiate components
initiator = new Initiator("initiator");
initiator->IO_request(IO_request);
memory = new ... |
or_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
|
or_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
|
communicationInterface |
sc_in<sc_uint<12> > inData;
sc_in<bool> clock , reset , clear;
sc_out<sc_uint<4> > payloadOut;
sc_out<sc_uint<8> > countOut , errorOut;
void validateData();
SC_CTOR(communicationInterface) {
SC_METHOD(validateData);
sensitive<<clock.pos();
}
|
sequenceDetectorTB |
sc_signal<bool> clock , reset , clear , input , output , state;
void clockSignal();
void resetSignal();
void clearSignal();
void inputSignal();
sequenceDetector* sd;
SC_CTOR(sequenceDetectorTB) {
sd = new sequenceDetector ("SD");
sd->clock(clock);
sd->reset(reset);
sd->clear(cl... |
SYSTEM |
//Module Declarations
tb *tb0;
full_adder *full_adder0;
//Local signal declarations
sc_signal<bool> sig_inp_a, sig_inp_b,
sig_inp_cin, sig_sum, sig_co;
SC_HAS_PROCESS(SYSTEM);
SYSTEM( sc_module_name nm) : sc_module (nm) {
//Module instance signal connections
tb0 = new tb("tb0");
tb0->inp_a( sig... |
Showcase0 |
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contO... |
Showcase0 |
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contO... |
nand_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void nand_process(void)
{
and_process(); // c = a and b
c = !c.read(); // c = not c
}
void and_process ( void )
{
c = a.read() && b.read();
}
void test_process(void)
{
assert( c.read() == ( a.read() && b.read() ) );
}
SC_CTOR(nand_gate)
{... |
nand_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void nand_process(void)
{
and_process(); // c = a and b
c = !c.read(); // c = not c
}
void and_process ( void )
{
c = a.read() && b.read();
}
void test_process(void)
{
assert( c.read() == ( a.read() && b.read() ) );
}
SC_CTOR(nand_gate)
{... |
sequenceDetectorTB |
sc_signal<bool> clock , reset , clear , input , output , state;
void clockSignal();
void resetSignal();
void clearSignal();
void inputSignal();
sequenceDetector* sd;
SC_CTOR(sequenceDetectorTB) {
sd = new sequenceDetector ("SD");
sd->clock(clock);
sd->reset(reset);
sd->clear(cl... |
hello_world |
private int meaning_of_life; // easter egg
//SC_CTOR -- systemC constructor
SC_CTOR(hello_world) {
meaning_of_life=42;
}
void say_hello() {
cout << "Hello Systemc-2.3.1!\n";
}
void open_magic_box() {
cout << meaning_of_life << endl;
}
|
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_... |
SYSTEM |
//module declarations
//Done by doing module_name Pointer_to_instance i.e. name *iname;
tb *tb0;
fir *fir0;
//signal declarations
sc_signal<bool> rst_sig;
sc_signal< sc_int<16> > inp_sig;
sc_signal< sc_int<16> > outp_sig;
sc_clock clk_sig;
... |
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_... |
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_... |
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_... |
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_... |
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for... |
counters |
sc_in<sc_uint<8> > in1 , in2 , in3;
sc_in<bool> dec1 , dec2 , clock , load1 , load2;
sc_out<sc_uint<8> > count1 , count2;
sc_out<bool> ended;
sc_signal<bool> isOverflow1 , isOverflow2;
void handleCount1();
void handleCount2();
void updateEnded();
SC_CTOR(counters) {
isOverflow1.write(false);
isOverflow... |
DUT |
SC_CTOR(DUT)
{
SC_THREAD(exec)
sensitive << m_clk.pos();
// CONNECT PORTS TO THEIR BACKING SIGNALS:
m_in_bigint4(m_back_in_bigint4);
m_inout_bigint4(m_back_inout_bigint4);
m_in_biguint4(m_back_in_biguint4);
m_inout_biguint4(m_back_inout_biguint4);
m_in_int4(m_back_in_int4);
m_inout_i... |
SYSTEM |
//module declarations
//Done by doing module_name Pointer_to_instance i.e. name *iname;
tb *tb0;
fir *fir0;
//signal declarations
sc_signal<bool> rst_sig;
sc_signal< sc_int<16> > inp_sig;
sc_signal< sc_int<16> > outp_sig;
sc_clock clk_sig;
... |
communicationInterfaceTB |
sc_signal<sc_uint<12> > inData;
sc_signal<bool> clock , reset , clear;
sc_signal<sc_uint<4> > payloadOut;
sc_signal<sc_uint<8> > countOut , errorOut;
void clockSignal();
void clearSignal();
void resetSignal();
void inDataSignal();
communicationInterface* cI;
SC_CTOR(communicationInterfaceTB) {
cI = ne... |
tensor_subtractor |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
SC_CTOR(tensor_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
for (int i = 0... |
watchDog |
async_event when;
bool barked;
public:
SC_CTOR(watchDog) : barked(false)
{
SC_METHOD(call_stop);
sensitive << when;
dont_initialize();
}
#if SC_CPLUSPLUS >= 201103L // C++11 threading support
~watchDog()
{
m_thread.join();
}
private:
std::thread m_thread;
void start_of_simulation... |
activity |
SC_CTOR(activity)
{
SC_THREAD(busy);
}
void busy()
{
cout << "I'm busy!"<<endl;
}
|
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for... |
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for... |
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for... |
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for... |
tensor_subtractor |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
SC_CTOR(tensor_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
for (int i = 0... |
tensor_subtractor |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
SC_CTOR(tensor_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
for (int i = 0... |
tensor_subtractor |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
SC_CTOR(tensor_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
for (int i = 0... |
tensor_subtractor |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
SC_CTOR(tensor_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
for (int i = 0... |
watchDog |
async_event when;
bool barked;
public:
SC_CTOR(watchDog) : barked(false)
{
SC_METHOD(call_stop);
sensitive << when;
dont_initialize();
}
#if SC_CPLUSPLUS >= 201103L // C++11 threading support
~watchDog()
{
m_thread.join();
}
private:
std::thread m_thread;
void start_of_simulation... |
activity |
SC_CTOR(activity)
{
SC_THREAD(busy);
}
void busy()
{
cout << "I'm busy!"<<endl;
}
|
watchDog |
async_event when;
bool barked;
public:
SC_CTOR(watchDog) : barked(false)
{
SC_METHOD(call_stop);
sensitive << when;
dont_initialize();
}
#if SC_CPLUSPLUS >= 201103L // C++11 threading support
~watchDog()
{
m_thread.join();
}
private:
std::thread m_thread;
void start_of_simulation... |
activity |
SC_CTOR(activity)
{
SC_THREAD(busy);
}
void busy()
{
cout << "I'm busy!"<<endl;
}
|
watchDog |
async_event when;
bool barked;
public:
SC_CTOR(watchDog) : barked(false)
{
SC_METHOD(call_stop);
sensitive << when;
dont_initialize();
}
#if SC_CPLUSPLUS >= 201103L // C++11 threading support
~watchDog()
{
m_thread.join();
}
private:
std::thread m_thread;
void start_of_simulation... |
activity |
SC_CTOR(activity)
{
SC_THREAD(busy);
}
void busy()
{
cout << "I'm busy!"<<endl;
}
|
watchDog |
async_event when;
bool barked;
public:
SC_CTOR(watchDog) : barked(false)
{
SC_METHOD(call_stop);
sensitive << when;
dont_initialize();
}
#if SC_CPLUSPLUS >= 201103L // C++11 threading support
~watchDog()
{
m_thread.join();
}
private:
std::thread m_thread;
void start_of_simulation... |
activity |
SC_CTOR(activity)
{
SC_THREAD(busy);
}
void busy()
{
cout << "I'm busy!"<<endl;
}
|
SwitchStmHwModule |
// ports
sc_in<sc_uint<1>> a;
sc_in<sc_uint<1>> b;
sc_in<sc_uint<1>> c;
sc_out<sc_uint<1>> out;
sc_in<sc_uint<3>> sel;
// component instances
// internal signals
void assig_process_out() {
switch(sel.read()) {
case sc_uint<3>("0b000"): {
out.write(a.r... |
Showcase0 |
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contO... |
communicationInterface |
sc_in<sc_uint<12> > inData;
sc_in<bool> clock , reset , clear;
sc_out<sc_uint<4> > payloadOut;
sc_out<sc_uint<8> > countOut , errorOut;
void validateData();
SC_CTOR(communicationInterface) {
SC_METHOD(validateData);
sensitive<<clock.pos();
}
|
E_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
#define N_TX 3
#define N_RX 2
void pe_thr... |
Consumer |
sc_in<int> data;
int readNumber;
SC_CTOR(Consumer){
SC_METHOD(consume);
sensitive << data;
}
void consume()
{
readNumber = data.read();
//readNumber = data; //geht bei SC_SIGNAL auch
cout << "[" << sc_time_stamp() << " / " << sc_delta_count() << "](" << name() << "): read " << readNumber << endl;
... |
gpio_matrix |
sc_inout<gn_mixed> d0_a11 {"d0_a11" |
HelloServertest |
/* Signals */
sc_signal<bool> led {"led" |
pcntmod |
sc_signal<uint32_t> conf0[8];
sc_signal<uint32_t> conf1[8];
sc_signal<uint32_t> conf2[8];
sc_signal<uint16_t> cnt_unit[8];
sc_signal<uint32_t> int_raw[8];
sc_signal<uint32_t> int_st {"int_st" |
SmallScreentest |
/* Signals */
sc_signal<bool> led {"led" |
System |
// clock and reset signals
sc_clock clk_sig;
sc_signal< bool > rst_sig;
// cynw_p2p channels
// LAB EXERCISE: Add a second parameter to select TLM I/O
// OLD
cynw_p2p < input_t, CYN::TLM > chan1; // For data going into the design
cynw_p2p < output_t, CYN::TLM > chan2; // For data co... |
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_i... |
System |
sc_clock clk_sig;
sc_signal<bool> rst_sig;
sc_signal<bool> finish;
sc_int<32> A[10];
sc_int<32> B[10];
sc_int<32> D[10];
dut_wrapper *m_dut;
tb *m_tb;
SC_CTOR(System)
: clk_sig("clk_sig", CLOCK_PERIOD, SC_NS)
, rst_sig("rst_sig")
, finish("finish")
{
m_dut = new dut_wrapper("dut_wrapp... |
s3 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s3_box();
SC_CTOR(s3)
{
SC_METHOD(s3_box);
sensitive << stage1_input;
}
|
s4 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s4_box();
SC_CTOR(s4)
{
SC_METHOD(s4_box);
sensitive << stage1_input;
}
|
des |
sc_in<bool > clk;
sc_in<bool > reset;
sc_in<bool > load_i;
sc_in<bool > decrypt_i;
sc_in<sc_uint<64> > data_i;
sc_in<sc_uint<64> > key_i;
sc_out<sc_uint<64> > data_o;
sc_out<bool > ready_o;
//Registers for iteration counters
sc_signal<sc_uint<4> > stage1_iter, next_stage1_ite... |
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_i... |
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_i... |
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_i... |
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_i... |
reg |
// Reading Port :
sc_in<sc_uint<6>> RADR1_SD;
sc_in<sc_uint<6>> RADR2_SD;
sc_out<sc_uint<32>> RDATA1_SR;
sc_out<sc_uint<32>> RDATA2_SR;
// Writing Port :
sc_in<sc_uint<6>> WADR_SW;
sc_in<bool> WENABLE_SW;
sc_in<sc_uint<32>> WDATA_SW;
sc_in<sc_uint<32>> WRITE_PC_SD;
... |
wb_arbiter |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface bus
sc_in<sc_uint<32>> ADR_I;
//interface master0
sc_in<bool> CYC_0_I;
sc_out<bool> GRANT_0_O;
//interface master1
sc_in<bool> CYC_1_I;
sc_out<bool> GRANT_1_O;
//interface slave0
sc_out<bool> CYC... |
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<8> > Xin;
sc_signal<sc_uint<8> > Xout;
sc_signal<sc_uint<16> > Yin;
sc_signal<sc_uint<16> > Yout;
sc_fir8* u_sc_fir8;
#ifdef VERILATED_CO_SIM
sc_signal<uint32_t> V_Xin;
sc_signal<uint32_t> V_Xout;
sc_signal<ui... |
rocket_wrapper |
//== Ports
sc_in<bool> clock;
sc_in<bool> reset;
sc_out<sc_lv<44>> periph_aw_msg;
sc_out<bool> periph_aw_valid;
sc_in<bool> periph_aw_ready;
sc_out<sc_lv<37>> periph_w_msg;
sc_out<bool> periph_w_valid;
sc_in<bool... |
Blinktest |
/* Signals */
sc_signal<bool> led {"led" |
s5 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s5_box();
SC_CTOR(s5)
{
SC_METHOD(s5_box);
sensitive << stage1_input;
}
|
wb_river_mc |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface with BUS
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> ACK_I; // when asserted indicates the normal termination of a bus cycle
sc_out<sc_uint<32>> DAT_O;
sc_out<sc_uint<32>> ADR_O;
sc_out<sc_uint<2>> SEL_O; // select which words on D... |
sc_fir8_tb |
sc_in<bool> clk;
sc_in<sc_uint<4> > eXout;
sc_in<sc_uint<4> > eYout;
sc_in<bool> eVld;
sc_out<sc_uint<4> > eXin;
sc_out<sc_uint<4> > eYin;
sc_out<bool> eRdy;
sc_signal<sc_uint<4> > Xin;
sc_signal<sc_uint<4> > Yin;
sc_signal... |
sc_shifter_TB |
sc_clock clk;
sc_signal<bool> rst,
sc_signal<sc_bv<7> > rst, din, qout;
Vshifter* u_Vshifter;
sc_trace_file* fp; // SystemC VCD file
SC_CTOR(sc_shifter_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate... |
dcache |
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface processeur
sc_in<sc_uint<32>> DATA_ADR_SM;
sc_in<sc_uint<32>> DATA_SM;
sc_in<bool> LOAD_SM;
sc_in<bool> STORE_SM;
sc_in<bool> VALID_ADR_SM;
sc_in<sc_uint<2>> MEM_SIZE_SM;
sc_out<sc_uint<32>> DATA_SC;
sc_out<bool> STALL_SC; // if stall... |
reg |
// Reading Port :
sc_in<sc_uint<6>> RADR1_SD;
sc_in<sc_uint<6>> RADR2_SD;
sc_out<sc_uint<32>> RDATA1_SR;
sc_out<sc_uint<32>> RDATA2_SR;
// Writing Port :
sc_in<sc_uint<6>> WADR_SW;
sc_in<bool> WENABLE_SW;
sc_in<sc_uint<32>> WDATA_SW;
sc_in<sc_uint<32>> WRITE_PC_SD;
... |
fir_top |
sc_in<bool> CLK;
sc_in<bool> RESET;
sc_in<bool> IN_VALID;
sc_in<int> SAMPLE;
sc_out<bool> OUTPUT_DATA_READY;
sc_out<int> RESULT;
sc_signal<unsigned> state_out;
fir_fsm *fir_fsm1;
fir_data *fir_data1;
SC_CTOR(fir_top) {
fir_fsm1 = new fir_fsm("FirFSM");... |
dut |
sc_in_clk clk;
sc_in< bool > rst;
cynw_p2p< input_data, ioConfig >::in in;
cynw_p2p< output_data, ioConfig >::out out;
stream_16X8::in<ioConfig> streamin;
stream_16X8::out<ioConfig> streamout;
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, in( "in" )
, ou... |
V_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<ui... |
ACCNAME |
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> ... |
TLM |
Initiator *initiator;
Memory *memory;
sc_core::sc_in<bool> IO_request;
SC_HAS_PROCESS(TLM);
TLM(sc_module_name tlm) // Construct and name socket
{
// Instantiate components
initiator = new Initiator("initiator");
initiator->IO_request(IO_request);
memory = new ... |
tb |
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_CTOR( tb ){
SC_... |
s6 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s6_box();
SC_CTOR(s6)
{
SC_METHOD(s6_box);
sensitive << stage1_input;
}
|
display |
// Port for input by channel
sc_port< sc_csp_channel_in_if< sc_uint<8> > > result_channel_port;
SC_CTOR(display)
{
SC_THREAD(output);
}
// Main method
void output();
|
sc_top |
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> d... |
i2c_controller_tb |
sc_clock *clk;
sc_signal<bool> rst;
sc_signal<sc_uint<7>> addr;
sc_signal<sc_uint<8>> data_in;
sc_signal<bool> enable;
sc_signal<bool> rw;
sc_signal<sc_lv<8>> data_out;
sc_signal<bool> ready;
sc_signal<sc_logic, SC_MANY_WRITERS> i2c_sda;
sc_signal<sc_logic> i2c_scl;
i2c_controller *master;
i2c_slave_co... |
fir |
sc_in<bool> clk;
sc_in<bool> rst;
sc_in<sc_int<16>> inp;
sc_out<sc_int<16>> out;
// Handshake signals
sc_in<bool> inp_vld;
sc_out<bool> inp_rdy;
sc_out<bool> out_vld;
sc_in<bool> out_rdy;
void fir_main();
SC_CTOR( fir ) {
SC_... |
CounterModule |
// Inputs
sc_in<bool> clk;
sc_in<bool> reset;
sc_in<bool> up_down_ctrl;
sc_in<bool> count_enable;
//Outputs
sc_out<sc_uint<N> > count_out;
sc_out<bool> overflow_intr;
sc_out<bool> underflow_intr;
// Variables
sc_uint<N> count;
// Main function of the module
void do_count();
SC_CTOR(Coun... |
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<8> > Xin;
sc_signal<sc_uint<8> > Xout;
sc_signal<sc_uint<16> > Yin;
sc_signal<sc_uint<16> > Yout;
#ifdef EMULATED
sc_signal<sc_uint<8> > E_Xout;
sc_signal<sc_uint<16> > E_Yout;
#endif
sc_fir8* u_sc_fir8;
// Test util... |
sc_fir8 |
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<8> > X[FILTER_TAP_NUM]; // Shift Register X
void fir8_thread(void)
{
uint8_t x;
uint8_t yL, yH... |
sc_fir8 |
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_fir_pe* u_fir_pe[N_PE_ARRAY];
sc_signal<sc_uint<8> > X[N_PE_ARRAY-1]; // X-input
sc_signal<sc_uint<16> > Y[N_PE_ARRAY-1]; /... |
sc_DUT_TB |
sc_clock CLK;
sc_signal<bool> nCLR;
sc_signal<bool> nLOAD;
sc_signal<bool> ENP;
sc_signal<bool> ENT;
sc_signal<bool> RCO;
// Verilator treats all Verilog's vector as <uint32_t>
sc_signal<uint32_t> Digit;
sc_signal<uint32_t>... |
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<4> > Xin;
sc_signal<sc_uint<4> > Xout;
sc_signal<sc_uint<4> > Yin;
sc_signal<sc_uint<4> > Yout;
sc_signal<bool> Vld;
sc_signal<bool> Rdy;
#ifdef EMULATED
sc_signal<sc_uint<4> > E_Xout;
sc_signal<sc_uint<4> > ... |
simple_bus_test |
// channels
sc_clock C1;
// module instances
simple_bus_master_blocking *master_b;
simple_bus_master_non_blocking *master_nb;
simple_bus_master_direct *master_d;
simple_bus_slow_mem *mem_slow;
simple_bus *bus;
simple_bus_fast_mem *mem_fast;
simpl... |
V_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<ui... |
sc_top |
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> d... |
quant |
sc_in_clk clk;
sc_in<Coeff8x8> data_in;
sc_in<bool> start;
sc_in<bool> data_ok;
sc_out<Coeff8x8> data_out;
sc_out<bool> ready;
sc_out<bool> data_out_ready;
void do_quant();
SC_CTOR(quant) {
SC_CTHREAD(do_quant,clk.pos());
|
quant |
sc_in_clk clk;
sc_in<Coeff8x8> data_in;
sc_in<bool> start;
sc_in<bool> data_ok;
sc_out<Coeff8x8> data_out;
sc_out<bool> ready;
sc_out<bool> data_out_ready;
void do_quant();
SC_CTOR(quant) {
SC_CTHREAD(do_quant,clk.pos());
|
quant |
sc_in_clk clk;
sc_in<Coeff8x8> data_in;
sc_in<bool> start;
sc_in<bool> data_ok;
sc_out<Coeff8x8> data_out;
sc_out<bool> ready;
sc_out<bool> data_out_ready;
void do_quant();
SC_CTOR(quant) {
SC_CTHREAD(do_quant,clk.pos());
|
transmitter)
//class transmitter : public sc_module
{
/// Input port for datas from the switch
sc_in<Packet> datain;
/// reset port
sc_in<bool> rst_n;
/// clk port
sc_in<bool> clk;
/// full port. If it's set it indicates that the fifo of the transmitter is to small to contain all datas
sc_out<sc_bit> full;
//... |
SC_METHOD(evaluate);
sensitive<<clk.pos()<<rst_n.neg();
FIFO= new Packet[m_fifo_tx_dim];
for (i=0;i<m_fifo_tx_dim;i++)
FIFO[i]=empty_NL_PDU;
last_pos=0;
if(m_N_R > m_N_T)
c=m_N_R;
tx_file.open ("tx_file.txt",ios::trunc);
tx_file << "SIMULATION STARTS NOW: "<<endl<<endl;
tx_file.close();
}... |
fila |
sc_in<bool > clock;
sc_in<bool > reset_n;
sc_in<regflit > data_in;
sc_in<bool > rx;
sc_out<bool > credit_o;
//sc_out<bool > ack_rx;
sc_out<bool > h;
sc_in<bool > ack_h;
sc_out<bool > data_av;
sc_out<regflit > data;
sc_in<bool > data_ack;
sc_out<bool > sender;
enum fila_out{S_INIT, S_PAYLOAD... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.