module_name stringlengths 1 2.17k | module_content stringlengths 6 11.3k |
|---|---|
seq_item_ams |
protected:
cv::Mat tx_img;
public:
// Input clock
sc_core::sc_in<bool> clk;
// Counters
sc_core::sc_in<unsigned int> hcount;
sc_core::sc_in<unsigned int> vcount;
// Output pixel
sc_core::sc_out<sc_uint<N> > o_red;
sc_core::sc_out<sc_uint<N> > o_green;
sc_core::sc_out<sc_uint<N> > o_blue;
SC_CTO... |
waveform |
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_out<DATA1024_t > source;
SC_CTOR(waveform)
{
SC_CTHREAD(waveform_thread,clk.pos());
}
void waveform_thread()
{
DATA1024_t tmp;
tmp.data = 0;
tmp.tlast = 0;
reset.write(true);
float numberGen = 0;
while(true)
{
wait();
reset.write(false);
... |
monitor |
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<DATA32_t > sink;
std::ofstream ofs;
SC_CTOR(monitor)
:ofs("test.txt", std::ofstream::out)
{
SC_CTHREAD(monitor_thread,clk.pos());
reset_signal_is(reset,true);
}
~monitor()
{
ofs.close();
}
void monitor_thread()
{
DATA32_t tmp;
unsigned countdo... |
Seuil_calc1 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out <bool> detect;
// sc_fifo_out <bool> detect1;
SC_CTOR(Seuil_calc1)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
sc_uint<8> buffer... |
tb_cnn_2d |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
typedef sc_fixed<P_data_W, P_data_P> sc_data;
sc_data func(int a, int b, int c, int d) {
int tmp = ((d & 0xFF) << 24) | ((c & 0xFF) << 16) | ((b & 0xFF) << 8) | ((a & 0xFF) << 0);
return (sc_data)tmp;
... |
Counter |
//------------------------------Module Inputs------------------------------
// Input clock
sc_in_clk clk;
// Reset bar (reset when 1'b0)
sc_in<bool> rstb;
// Starts the counter
sc_in<bool> enable;
// N-bit output of the counter
sc_out<sc_uint<N > > count_out;
//----------------... |
Edge_Detector |
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<24> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
... |
mon_split_and_merge |
sc_fifo_in<hwcore::pipes::sc_data_stream_t<16> > data_in;
SC_CTOR(mon_split_and_merge)
{
SC_THREAD(mon_thread);
}
void mon_thread()
{
for(int a=0;a<2;a++)
{
uint16_t data_gen = 0;
hwcore::pipes::sc_data_stream_t<16> tmp_in;
do
{
tmp_in = data_in.read();
std::cout << "(mon) got sig... |
wave_split_and_merge |
sc_fifo_out<hwcore::pipes::sc_data_stream_t<16> > data_out;
SC_CTOR(wave_split_and_merge)
{
SC_THREAD(wave_thread);
}
void wave_thread()
{
hwcore::pipes::sc_data_stream_t<16> tmp;
for (int i = 0; i < test_size; i++)
{
tmp.data = i;
std::cout << "(wave) write new data: " << i << std::endl;
... |
tb_split_and_merge |
#if __RTL_SIMULATION__
//DMA_performance_tester_rtl_wrapper u1;
#else
//DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_split_and_merge wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > wave_2_u1;
hwcore::pipes::sc_stream_splitter<16,split_N,false> u1_ss;
hwcore::hf::sc_st... |
MIPS |
sc_in<bool> clk;
sc_port<readwrite_if> ioController;
uint32_t breg[32];
Bitmap bg;
SC_CTOR(MIPS) {
SC_METHOD(exec);
sensitive << clk.pos();
const char fn[] = "mandrill2.bmp";
const char mode[] = "rb";
breg[4] = (uint32_t)fn; breg[5] = (uint32_t)mode;
fileOpen();
... |
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
Seuil_calc2 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out <bool> detect;
// sc_fifo_out <bool> detect1;
SC_CTOR(Seuil_calc2)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
sc_uint<8> buffer... |
mon_bufferstreamer |
sc_fifo_out<sc_uint<31> > ctrl_out;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<16> > data_in;
SC_CTOR(mon_bufferstreamer) { SC_THREAD(mon_thread); }
void mon_thread() {
uint16_t data_gen = 0;
std::cout << "(mon) req. newset (start) " << std::endl;
ctrl_out.write(hwcore::pipes::sc_stream_buffer<>::ctrls::new... |
wave_bufferstreamer |
sc_fifo_out<hwcore::pipes::sc_data_stream_t<16> > data_out;
SC_CTOR(wave_bufferstreamer) { SC_THREAD(wave_thread); }
void wave_thread() {
hwcore::pipes::sc_data_stream_t<16> tmp;
for (int i = 0; i < test_size; i++) {
tmp.data = i;
std::cout << "(wave) write new data: " << i << std::endl;
tmp.tkeep =... |
tb_bufferstreamer |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
hwcore::pipes::sc_stream_buffer_not_stream_while_write<16> bs_u1;
wave_bufferstreamer wave;
mon_bufferstreamer mon;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > b... |
Detecteur2 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
// sc_fifo_in < sc_uint<8> > e2;
sc_fifo_out< sc_uint<8> > s;
// sc_fifo_out< bool > detect1;
SC_CTOR(Detecteur2):
s_calc("s_calc"),
t_sep("t_sep"),
dbl("dbl"),
dbl2scalc("dbl2scalc",1024),
d... |
memory |
protected:
int *mem;
public:
sc_core::sc_in<bool> clk;
sc_core::sc_in<bool> we;
sc_core::sc_in<unsigned long long int> address;
sc_core::sc_in<sc_uint<24>> wdata;
sc_core::sc_out<sc_uint<24>> rdata;
// Constructor for memory
SC_CTOR(memory)
{
this->mem = new int[SIZE];
SC_METHOD(run);
... |
hl5 |
public:
// Declaration of clock and reset signals
sc_in_clk clk;
sc_in < bool > rst;
//End of simulation signal.
sc_out < bool > program_end;
// Fetch enable signal.
sc_in < bool > fetch_en;
// Entry point
sc_in < unsigned > entry_point;
// TODO: removeme
// sc_out < bool > main_start;
// sc_out <... |
BMPWriter |
public:
sc_fifo_in< sc_uint<32> > addr;
sc_fifo_in< sc_uint<24> > rgbv;
SC_CTOR(BMPWriter)
{
SC_THREAD(do_gen);
}
~BMPWriter( )
{
string fn;
fn = "received_image";
string filename = fn + ".bmp";
if (fopen(filename.c_str(), "rb")== NULL )
bmp... |
Filter |
//-----------------------------Local Variables-----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
/**
* @brief Default constructor for Filter
*/
SC_CTOR(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name... |
img_receiver |
//Array for input image
unsigned char* input_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_receiver)
{
input_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_INPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, uns... |
trames_separ |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_in <bool> detect;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(trames_separ)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
// #ifdef _DEBUG_SYNCHRO_
... |
cpu_sim |
sc_fifo_out<pipes::sc_data_stream_t<16*32> > dma_out;
sc_fifo_in<pipes::sc_data_stream_t<16*32> > dma_in;
//sc_out<uint32_t>
|
tb_cnn_top |
hf::sc_fifo_template<pipes::sc_data_stream_t<16*32> > cpu_sim_2_u1_dma;
cnn::top_cnn<> cnn_u1;
hf::sc_fifo_template<pipes::sc_data_stream_t<16*32> > u1_2_cpu_sim_dma;
|
RAWReader |
public:
sc_fifo_out< sc_int<8> > s;
SC_CTOR(RAWReader)
{
SC_THREAD(do_gen);
}
private:
void do_gen( )
{
cout << "(II) RAWReader :: START" << endl;
FILE* f = fopen("/tmp/file.raw", "rb");
if( f == NULL )
{
cout << "(EE) Error opening the input file (/tmp/file.raw)" << endl;
... |
fedec |
public:
// FlexChannel initiators
put_initiator< de_out_t > dout;
get_initiator< mem_out_t > feed_from_wb;
// Forward
sc_in< reg_forward_t > fwd_exe;
// End of simulation signal.
sc_out < bool > program_end;
// Fetch enable signal.
sc_in < bool > fetch_en;
// Entry point
sc_in < unsigned > entry_point;
... |
img_receiver |
//Array for input image
unsigned char* input_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_receiver)
{
input_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_INPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, uns... |
Detecteur1 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
// sc_fifo_in < sc_uint<8> > e2;
sc_fifo_out< sc_uint<8> > s;
// sc_fifo_out< bool > detect1;
SC_CTOR(Detecteur1):
s_calc("s_calc"),
t_sep("t_sep"),
dbl("dbl"),
dbl2scalc("dbl2scalc",1024),
d... |
DOUBLEUR |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int<8> > e;
sc_fifo_out< sc_int<8> > s1;
sc_fifo_out< sc_int<8> > s2;
SC_CTOR(DOUBLEUR)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
while ( t... |
first_counter |
// Clock input of the design
sc_in_clk clock;
// Active high, synchronous Reset input
sc_in<bool> reset;
// Active high enable signal for counter
sc_in<bool> enable;
// 4 bit vector output of the counter
sc_out<sc_uint<4> > counter_out;
//------------Local Variables Here---------------------
sc_ui... |
scheduler_module |
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_dma_weight;
sc_fifo_in<float> from_dma_input;
sc_fifo_in< sc_uint<64> > from_dma_instructions;
sc_fifo_out<float> to_dma;
// PROCESSING ENGINES
sc_fifo_out< sc_uint<34> > npu_instructions[CORE];
sc_fifo_out<flo... |
trames_separ2 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_in <bool> detect;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(trames_separ2)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
// #ifdef _DEBUG_SYNCHRO_
... |
BMPWriter_fixed_acc |
public:
sc_fifo_in< sc_uint<32> > addr;
sc_fifo_in< sc_uint<24> > rgbv;
SC_CTOR(BMPWriter_fixed_acc)
{
SC_THREAD(do_gen);
}
~BMPWriter_fixed_acc( )
{
string fn;
fn = "received_image_fixed_acc";
string filename = fn + ".bmp";
if (fopen(filename.c_str()... |
LED |
sc_in<bool> in;
sc_in<bool> in2;
SC_CTOR(LED)
{
SC_METHOD(blink);
sensitive << in;
}
void blink()
{
if (in.read())
cout << log_time() << "LED "<< name() << ": ON\n";
else
cout << log_time() << "LED "<< name() << ": OFF\n";
}
|
Gate |
sc_in<Person> card;
// Turnstile interface:
sc_in<bool> passed;
sc_out<bool> unlock;
// Two lights for green and red:
sc_out<bool> green;
sc_out<bool> red;
public:
// Better: make it private, include values as constructor args.
Building org;
Building dest;
private:
Person dap= NO_PERSO... |
turnstile |
sc_in<bool> unlock;
sc_out<bool> passed;
SC_CTOR(turnstile)
{
SC_THREAD(operate);
// sensitive << unlock;
}
void operate()
{
int t;
bool b;
while (true)
{
wait (unlock.posedge_event());
cout << log_time() << "Turnstile " << name() << " unlocked.\n";
/* Wait random ... |
Door |
sc_out<Person> card;
private:
sc_signal<bool> green_sig;
sc_signal<bool> red_sig;
sc_signal<bool> unlock_sig;
sc_signal<bool> pass_sig;
sc_signal<Person> card_sig;
LED grn;
LED red;
turnstile ts;
Gate gc;
public:
SC_CTOR(Door) : grn("Green"), red("Red"), ts("TS"), gc("GC")
{
gc.red... |
testGen |
Door *doors[NUM_DOORS];
int num_steps;
SC_CTOR(testGen)
{
doors[0] = new Door("DoorA");
doors[1] = new Door("DoorB");
doors[2] = new Door("DoorC");
doors[3] = new Door("DoorD");
doors[4] = new Door("DoorE");
doors[5] = new Door("DoorF");
/* Connect doors */
doors[0]->se... |
SYSTEM |
//Module Declarations
tb *tb0;
full_adder *full_adder0;
//Local signal declarations
sc_signal<bool> sig_inp_a, sig_inp_b,
sig_inp_cin, sig_sum, sig_co;
SC_HAS_PROCESS(SYSTEM);
SYSTEM( sc_module_name nm) : sc_module (nm) {
//Module instance signal connections
tb0 = new tb("tb0");
tb0->inp_a( sig... |
nand_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void nand_process(void)
{
and_process(); // c = a and b
c = !c.read(); // c = not c
}
void and_process ( void )
{
c = a.read() && b.read();
}
void test_process(void)
{
assert( c.read() == ( a.read() && b.read() ) );
}
SC_CTOR(nand_gate)
{... |
nand_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void nand_process(void)
{
and_process(); // c = a and b
c = !c.read(); // c = not c
}
void and_process ( void )
{
c = a.read() && b.read();
}
void test_process(void)
{
assert( c.read() == ( a.read() && b.read() ) );
}
SC_CTOR(nand_gate)
{... |
M |
sc_in<bool> ckp;
sc_out<int> s1p;
sc_signal<int> s2;
sc_event e1, e2;
void P1_meth(void);
void P3_thrd(void);
void P2_thrd(void);
SC_CTOR(M):count(0),temp(9)
,prev_time(99),prev_ck(true),prev_s1(99),prev_s2(99),prev_temp(99)
{
cout << "T-5:---- Elaborating (CTOR Registering P3_thrd)" << std::... |
communicationInterface |
sc_in<sc_uint<12> > inData;
sc_in<bool> clock , reset , clear;
sc_out<sc_uint<4> > payloadOut;
sc_out<sc_uint<8> > countOut , errorOut;
void validateData();
SC_CTOR(communicationInterface) {
SC_METHOD(validateData);
sensitive<<clock.pos();
}
|
IDE |
// Declare inputs and outputs if needed
|
PCIx |
// Declare inputs and outputs if needed
|
ESATA |
public:
sc_in<bool> clk;
sc_out<std::string> path;
void write(const std::string& path) {
// Write logic goes here
}
void read_permissions() {
// Read permissions logic goes here
}
void thread_process() {
wait();
write(/* Your path */);
read_permis... |
ETH |
public:
sc_in<bool> clk;
sc_in<unsigned char*> ethData;
sc_out<std::string> encryptionKey;
void thread_process() {
wait();
// Replace this line with your actual Ethernet signal transmission logic
sendEthernetSignal(ethData, encryptionKey);
}
|
bootmsgs) : sc_module("bootmsgs" |
QUIETELSECLASS(bootmsgs, "bootmsgs");
SC_HAS_PROCESS(bootmsgs);
bootmsgs(sc_module_name name) : sc_module(name) {
IDE ide("ide");
PCIx pci("/PCI@0xC0000471e/PCIe_X2_1.0");
ESATA esata("esata");
ETH eth("eth");
sensitive << clk.pos();
idesign(ide, pci, esa... |
sequenceDetectorTB |
sc_signal<bool> clock , reset , clear , input , output , state;
void clockSignal();
void resetSignal();
void clearSignal();
void inputSignal();
sequenceDetector* sd;
SC_CTOR(sequenceDetectorTB) {
sd = new sequenceDetector ("SD");
sd->clock(clock);
sd->reset(reset);
sd->clear(cl... |
YourSimulator |
IceWrapper *thermalSimulation;
SC_CTOR(YourSimulator) {
thermalSimulation = new IceWrapper(ServerIp, ServerPort);
SC_THREAD(process);
}
void process()
{
std::vector<float> powerValues = {0, // 1: CPUs
0, // 2: GPU
... |
sequenceDetector |
sc_in<bool> clock , reset , clear;
sc_in<bool> input;
sc_out<bool> output;
sc_out<bool> state;
void detectorAlgo();
void updateValues();
enum states {S1,S2,S3,S4,S5 |
DReg |
// ports
sc_in_clk clk;
sc_in<sc_uint<1>> din;
sc_out<sc_uint<1>> dout;
sc_in<sc_uint<1>> rst;
// component instances
// internal signals
sc_uint<1> internReg = sc_uint<1>("0b0");
sc_signal<sc_uint<1>> internReg_next;
void assig_process_dout() {
dout.write(internReg);
... |
scalar_subtractor |
sc_in_clk clock;
sc_in<int> data_a_in;
sc_in<int> data_b_in;
sc_out<int> data_out;
SC_CTOR(scalar_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
sensitive << data_a_in;
sensitive << data_b_in;
}
void subtractor() {
data_out.write(data_a_in.read() - data_b_in.read())... |
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_... |
C%s | \n", baseName.c_str());
fprintf(pIncFile, "\n");
fprintf(pIncFile, "\t//sc_uint<64> zero;\n");
fprintf(pIncFile, "\t//sc_uint<64> one;\n");
fprintf(pIncFile, "\n");
fprintf(pIncFile, "\t///////////////////////\n");
fprintf(pIncFile, "\t// Port declarations\n");
fp... |
M |
sc_in<bool> ckp;
sc_out<int> s1p;
sc_signal<int> s2;
sc_event e1, e2;
void P1_meth(void);
void P3_thrd(void);
void P2_thrd(void);
SC_CTOR(M):count(0),temp(9)
{
cout << "T-5:---- Elaborating (CTOR Registering P3_thrd)" << std::endl;
SC_THREAD(P3_thrd);
cout << "T-4:---- Elaborating (CTOR R... |
scalar_subtractor |
sc_in_clk clock;
sc_in<int> data_a_in;
sc_in<int> data_b_in;
sc_out<int> data_out;
SC_CTOR(scalar_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
sensitive << data_a_in;
sensitive << data_b_in;
}
void subtractor() {
data_out.write(data_a_in.read() - data_b_in.read())... |
scalar_subtractor |
sc_in_clk clock;
sc_in<int> data_a_in;
sc_in<int> data_b_in;
sc_out<int> data_out;
SC_CTOR(scalar_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
sensitive << data_a_in;
sensitive << data_b_in;
}
void subtractor() {
data_out.write(data_a_in.read() - data_b_in.read())... |
scalar_subtractor |
sc_in_clk clock;
sc_in<int> data_a_in;
sc_in<int> data_b_in;
sc_out<int> data_out;
SC_CTOR(scalar_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
sensitive << data_a_in;
sensitive << data_b_in;
}
void subtractor() {
data_out.write(data_a_in.read() - data_b_in.read())... |
scalar_subtractor |
sc_in_clk clock;
sc_in<int> data_a_in;
sc_in<int> data_b_in;
sc_out<int> data_out;
SC_CTOR(scalar_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
sensitive << data_a_in;
sensitive << data_b_in;
}
void subtractor() {
data_out.write(data_a_in.read() - data_b_in.read())... |
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_... |
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_... |
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_... |
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_... |
matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
f... |
TLM |
Initiator *initiator;
Memory *memory;
sc_core::sc_in<bool> IO_request;
SC_HAS_PROCESS(TLM);
TLM(sc_module_name tlm) // Construct and name socket
{
// Instantiate components
initiator = new Initiator("initiator");
initiator->IO_request(IO_request);
memory = new ... |
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for... |
communicationInterfaceTB |
sc_signal<sc_uint<12> > inData;
sc_signal<bool> clock , reset , clear;
sc_signal<sc_uint<4> > payloadOut;
sc_signal<sc_uint<8> > countOut , errorOut;
void clockSignal();
void clearSignal();
void resetSignal();
void inDataSignal();
communicationInterface* cI;
SC_CTOR(communicationInterfaceTB) {
cI = ne... |
SYSTEM |
//module declarations
//Done by doing module_name Pointer_to_instance i.e. name *iname;
tb *tb0;
fir *fir0;
//signal declarations
sc_signal<bool> rst_sig;
sc_signal< sc_int<16> > inp_sig;
sc_signal< sc_int<16> > outp_sig;
sc_clock clk_sig;
... |
scalar_logistic_function |
sc_in_clk clock;
sc_in<int> data_in;
sc_out<int> data_out;
SC_CTOR(scalar_logistic_function) {
SC_METHOD(logistic_function);
sensitive << clock.pos();
sensitive << data_in;
}
void logistic_function() {
data_out.write(data_in.read());
}
|
counters |
sc_in<sc_uint<8> > in1 , in2 , in3;
sc_in<bool> dec1 , dec2 , clock , load1 , load2;
sc_out<sc_uint<8> > count1 , count2;
sc_out<bool> ended;
sc_signal<bool> isOverflow1 , isOverflow2;
void handleCount1();
void handleCount2();
void updateEnded();
SC_CTOR(counters) {
isOverflow1.write(false);
isOverflow... |
matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
f... |
matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
f... |
matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
f... |
matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
f... |
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for... |
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for... |
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for... |
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for... |
scalar_logistic_function |
sc_in_clk clock;
sc_in<int> data_in;
sc_out<int> data_out;
SC_CTOR(scalar_logistic_function) {
SC_METHOD(logistic_function);
sensitive << clock.pos();
sensitive << data_in;
}
void logistic_function() {
data_out.write(data_in.read());
}
|
scalar_logistic_function |
sc_in_clk clock;
sc_in<int> data_in;
sc_out<int> data_out;
SC_CTOR(scalar_logistic_function) {
SC_METHOD(logistic_function);
sensitive << clock.pos();
sensitive << data_in;
}
void logistic_function() {
data_out.write(data_in.read());
}
|
scalar_logistic_function |
sc_in_clk clock;
sc_in<int> data_in;
sc_out<int> data_out;
SC_CTOR(scalar_logistic_function) {
SC_METHOD(logistic_function);
sensitive << clock.pos();
sensitive << data_in;
}
void logistic_function() {
data_out.write(data_in.read());
}
|
scalar_logistic_function |
sc_in_clk clock;
sc_in<int> data_in;
sc_out<int> data_out;
SC_CTOR(scalar_logistic_function) {
SC_METHOD(logistic_function);
sensitive << clock.pos();
sensitive << data_in;
}
void logistic_function() {
data_out.write(data_in.read());
}
|
IDE |
// Declare inputs and outputs if needed
|
PCIx |
// Declare inputs and outputs if needed
|
ESATA |
public:
sc_in<bool> clk;
sc_out<std::string> path;
void write(const std::string& path) {
// Write logic goes here
}
void read_permissions() {
// Read permissions logic goes here
}
void thread_process() {
wait();
write(/* Your path */);
read_permis... |
ETH |
public:
sc_in<bool> clk;
sc_in<unsigned char*> ethData;
sc_out<std::string> encryptionKey;
void thread_process() {
wait();
// Replace this line with your actual Ethernet signal transmission logic
sendEthernetSignal(ethData, encryptionKey);
}
|
bootmsgs) : sc_module("bootmsgs" |
QUIETELSECLASS(bootmsgs, "bootmsgs");
SC_HAS_PROCESS(bootmsgs);
bootmsgs(sc_module_name name) : sc_module(name) {
IDE ide("ide");
PCIx pci("/PCI@0xC0000471e/PCIe_X2_1.0");
ESATA esata("esata");
ETH eth("eth");
sensitive << clk.pos();
idesign(ide, pci, esa... |
CONSUMER |
SC_CTOR(CONSUMER)
{
SC_CTHREAD(consumer,m_clk.pos());
reset_signal_is(m_reset,false);
}
void consumer()
{
cout << sc_time_stamp() << ": reset" << endl;
while (1)
{
m_ready = true;
do { wait(); } while ( !m_valid);
cout << sc_time_stamp() << ": " << m_value.read() << endl;
}
}
sc_in_clk ... |
PRODUCER |
SC_CTOR(PRODUCER)
{
SC_CTHREAD(producer,m_clk.pos());
reset_signal_is(m_reset,false);
}
void producer()
{
m_value = 0;
while (1)
{
m_valid = true;
do { wait(); } while (!m_ready);
m_value = m_value + 1;
}
}
sc_in_clk m_clk;
sc_in<bool> m_ready;
sc_in<bool> m_reset;
sc_inout... |
TESTBENCH |
SC_CTOR(TESTBENCH) : m_consumer("consumer"), m_producer("producer")
{
SC_CTHREAD(testbench,m_clk.pos());
m_consumer.m_clk(m_clk);
m_consumer.m_ready(m_ready);
m_consumer.m_reset(m_reset);
m_consumer.m_valid(m_valid);
m_consumer.m_value(m_value);
m_producer.m_clk(m_clk);
m_producer.m_ready(m_ready);
... |
SwitchStmHwModule |
// ports
sc_in<sc_uint<1>> a;
sc_in<sc_uint<1>> b;
sc_in<sc_uint<1>> c;
sc_out<sc_uint<1>> out;
sc_in<sc_uint<3>> sel;
// component instances
// internal signals
void assig_process_out() {
switch(sel.read()) {
case sc_uint<3>("0b000"): {
out.write(a.r... |
LED |
sc_in<bool> in;
sc_in<bool> in2;
SC_CTOR(LED)
{
SC_METHOD(blink);
sensitive << in;
}
void blink()
{
if (in.read())
cout << log_time() << "LED "<< name() << ": ON\n";
else
cout << log_time() << "LED "<< name() << ": OFF\n";
}
|
Gate |
sc_in<Person> card;
// Turnstile interface:
sc_in<bool> passed;
sc_out<bool> unlock;
// Two lights for green and red:
sc_out<bool> green;
sc_out<bool> red;
public:
// Better: make it private, include values as constructor args.
Building org;
Building dest;
private:
Person dap= NO_PERSO... |
turnstile |
sc_in<bool> unlock;
sc_out<bool> passed;
SC_CTOR(turnstile)
{
SC_THREAD(operate);
// sensitive << unlock;
}
void operate()
{
int t;
bool b;
while (true)
{
wait (unlock.posedge_event());
cout << log_time() << "Turnstile " << name() << " unlocked.\n";
/* Wait random ... |
Door |
sc_out<Person> card;
private:
sc_signal<bool> green_sig;
sc_signal<bool> red_sig;
sc_signal<bool> unlock_sig;
sc_signal<bool> pass_sig;
sc_signal<Person> card_sig;
LED grn;
LED red;
turnstile ts;
Gate gc;
public:
SC_CTOR(Door) : grn("Green"), red("Red"), ts("TS"), gc("GC")
{
gc.red... |
testGen |
Door *doors[NUM_DOORS];
int num_steps;
SC_CTOR(testGen)
{
doors[0] = new Door("DoorA");
doors[1] = new Door("DoorB");
doors[2] = new Door("DoorC");
doors[3] = new Door("DoorD");
doors[4] = new Door("DoorE");
doors[5] = new Door("DoorF");
/* Connect doors */
doors[0]->se... |
hello_world |
private int meaning_of_life; // easter egg
//SC_CTOR -- systemC constructor
SC_CTOR(hello_world) {
meaning_of_life=42;
}
void say_hello() {
cout << "Hello Systemc-2.3.1!\n";
}
void open_magic_box() {
cout << meaning_of_life << endl;
}
|
SYSTEM |
//module declarations
//Done by doing module_name Pointer_to_instance i.e. name *iname;
tb *tb0;
fir *fir0;
//signal declarations
sc_signal<bool> rst_sig;
sc_signal< sc_int<16> > inp_sig;
sc_signal< sc_int<16> > outp_sig;
sc_clock clk_sig;
... |
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