url stringclasses 147
values | commit stringclasses 147
values | file_path stringlengths 7 101 | full_name stringlengths 1 94 | start stringlengths 6 10 | end stringlengths 6 11 | tactic stringlengths 1 11.2k | state_before stringlengths 3 2.09M | state_after stringlengths 6 2.09M | input stringlengths 73 2.09M |
|---|---|---|---|---|---|---|---|---|---|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleAt_card_eq_orderOf_cycleOf | [170, 1] | [172, 102] | simp_rw [cycleAt_eq_cycleAtTo_orderOf_cycleOf, cycleAtTo_card_eq_of_le_orderOf_cycleOf (le_refl _)] | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
⊢ orderOf (π.cycleOf x) = (CycleAt π x).card | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
⊢ orderOf (π.cycleOf x) = (CycleAt π x).card
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleAt_eq_cycleAtTo_ge_orderOf_cycleOf | [174, 1] | [179, 33] | refine le_antisymm ?_ ?_ | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
a : ℕ
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleAt π x = CycleAtTo π a x | case refine_1
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
a : ℕ
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleAt π x ≤ CycleAtTo π a x
case refine_2
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
a : ℕ
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleAtTo π a x ≤ CycleAt π x | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
a : ℕ
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleAt π x = CycleAtTo π a x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleAt_eq_cycleAtTo_ge_orderOf_cycleOf | [174, 1] | [179, 33] | rw [cycleAt_eq_cycleAtTo_orderOf_cycleOf] | case refine_1
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
a : ℕ
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleAt π x ≤ CycleAtTo π a x | case refine_1
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
a : ℕ
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleAtTo π (orderOf (π.cycleOf x)) x ≤ CycleAtTo π a x | Please generate a tactic in lean4 to solve the state.
STATE:
case refine_1
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
a : ℕ
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleAt π x ≤ CycleAtTo π a x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleAt_eq_cycleAtTo_ge_orderOf_cycleOf | [174, 1] | [179, 33] | exact cycleAtTo_of_mono ha | case refine_1
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
a : ℕ
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleAtTo π (orderOf (π.cycleOf x)) x ≤ CycleAtTo π a x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case refine_1
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
a : ℕ
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleAtTo π (orderOf (π.cycleOf x)) x ≤ CycleAtTo π a x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleAt_eq_cycleAtTo_ge_orderOf_cycleOf | [174, 1] | [179, 33] | exact cycleAtTo_subset_cycleAt | case refine_2
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
a : ℕ
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleAtTo π a x ≤ CycleAt π x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case refine_2
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
x : α
a : ℕ
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleAtTo π a x ≤ CycleAt π x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | insert_cycleAtTo_eq_succ | [181, 1] | [185, 74] | ext y | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
⊢ insert ((π ^ a) x) (CycleAtTo π a x) = CycleAtTo π (a + 1) x | case a
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x y : α
⊢ y ∈ insert ((π ^ a) x) (CycleAtTo π a x) ↔ y ∈ CycleAtTo π (a + 1) x | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
⊢ insert ((π ^ a) x) (CycleAtTo π a x) = CycleAtTo π (a + 1) x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | insert_cycleAtTo_eq_succ | [181, 1] | [185, 74] | simp_rw [mem_insert, mem_cycleAtTo_iff, Nat.lt_succ_iff_lt_or_eq, or_and_right, exists_or,
exists_eq_left, or_comm (a := y = (π ^ a) x), eq_comm (b := (π^a) x)] | case a
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x y : α
⊢ y ∈ insert ((π ^ a) x) (CycleAtTo π a x) ↔ y ∈ CycleAtTo π (a + 1) x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case a
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x y : α
⊢ y ∈ insert ((π ^ a) x) (CycleAtTo π a x) ↔ y ∈ CycleAtTo π (a + 1) x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | insert_cycleAtTo | [187, 1] | [194, 59] | intros y hy | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
⊢ insert ((π ^ k) x) (CycleAtTo π a x) ⊆ CycleAtTo π b x | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
y : α
hy : y ∈ insert ((π ^ k) x) (CycleAtTo π a x)
⊢ y ∈ CycleAtTo π b x | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
⊢ insert ((π ^ k) x) (CycleAtTo π a x) ⊆ CycleAtTo π b x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | insert_cycleAtTo | [187, 1] | [194, 59] | rw [mem_insert] at hy | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
y : α
hy : y ∈ insert ((π ^ k) x) (CycleAtTo π a x)
⊢ y ∈ CycleAtTo π b x | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
y : α
hy : y = (π ^ k) x ∨ y ∈ CycleAtTo π a x
⊢ y ∈ CycleAtTo π b x | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
y : α
hy : y ∈ insert ((π ^ k) x) (CycleAtTo π a x)
⊢ y ∈ CycleAtTo π b x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | insert_cycleAtTo | [187, 1] | [194, 59] | rcases hy with (rfl | hy) | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
y : α
hy : y = (π ^ k) x ∨ y ∈ CycleAtTo π a x
⊢ y ∈ CycleAtTo π b x | case inl
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
⊢ (π ^ k) x ∈ CycleAtTo π b x
case inr
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
y : α
hy : y ∈ CycleAtTo π a x
⊢ y ∈ CycleAtTo π b x | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
y : α
hy : y = (π ^ k) x ∨ y ∈ CycleAtTo π a x
⊢ y ∈ CycleAtTo π b x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | insert_cycleAtTo | [187, 1] | [194, 59] | rw [mem_cycleAtTo_iff] | case inl
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
⊢ (π ^ k) x ∈ CycleAtTo π b x | case inl
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
⊢ ∃ b_1 < b, (π ^ b_1) x = (π ^ k) x | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
⊢ (π ^ k) x ∈ CycleAtTo π b x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | insert_cycleAtTo | [187, 1] | [194, 59] | exact ⟨k, hkb, rfl⟩ | case inl
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
⊢ ∃ b_1 < b, (π ^ b_1) x = (π ^ k) x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
⊢ ∃ b_1 < b, (π ^ b_1) x = (π ^ k) x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | insert_cycleAtTo | [187, 1] | [194, 59] | exact cycleAtTo_of_mono (lt_of_le_of_lt hak hkb).le hy | case inr
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
y : α
hy : y ∈ CycleAtTo π a x
⊢ y ∈ CycleAtTo π b x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
k b : ℕ
x : α
a : ℕ
hak : a ≤ k
hkb : k < b
y : α
hy : y ∈ CycleAtTo π a x
⊢ y ∈ CycleAtTo π b x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | pow_apply_not_mem_cycleAtTo_of_lt_orderOf_cycleOf | [196, 1] | [201, 73] | intro h | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h : a < orderOf (π.cycleOf x)
⊢ (π ^ a) x ∉ CycleAtTo π a x | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h✝ : a < orderOf (π.cycleOf x)
h : (π ^ a) x ∈ CycleAtTo π a x
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h : a < orderOf (π.cycleOf x)
⊢ (π ^ a) x ∉ CycleAtTo π a x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | pow_apply_not_mem_cycleAtTo_of_lt_orderOf_cycleOf | [196, 1] | [201, 73] | rw [mem_cycleAtTo_iff] at h | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h✝ : a < orderOf (π.cycleOf x)
h : (π ^ a) x ∈ CycleAtTo π a x
⊢ False | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h✝ : a < orderOf (π.cycleOf x)
h : ∃ b < a, (π ^ b) x = (π ^ a) x
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h✝ : a < orderOf (π.cycleOf x)
h : (π ^ a) x ∈ CycleAtTo π a x
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | pow_apply_not_mem_cycleAtTo_of_lt_orderOf_cycleOf | [196, 1] | [201, 73] | rcases h with ⟨b, hb, hbx⟩ | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h✝ : a < orderOf (π.cycleOf x)
h : ∃ b < a, (π ^ b) x = (π ^ a) x
⊢ False | case intro.intro
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h : a < orderOf (π.cycleOf x)
b : ℕ
hb : b < a
hbx : (π ^ b) x = (π ^ a) x
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h✝ : a < orderOf (π.cycleOf x)
h : ∃ b < a, (π ^ b) x = (π ^ a) x
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | pow_apply_not_mem_cycleAtTo_of_lt_orderOf_cycleOf | [196, 1] | [201, 73] | exact hb.ne (π.pow_apply_injOn_Iio_orderOf_cycleOf (hb.trans h) h hbx) | case intro.intro
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h : a < orderOf (π.cycleOf x)
b : ℕ
hb : b < a
hbx : (π ^ b) x = (π ^ a) x
⊢ False | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h : a < orderOf (π.cycleOf x)
b : ℕ
hb : b < a
hbx : (π ^ b) x = (π ^ a) x
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleAtTo_strict_mono_lt_of_lt_lt_orderOf | [203, 1] | [206, 98] | rw [Finset.ssubset_iff] | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
b : ℕ
ha : a < orderOf (π.cycleOf x)
hab : a < b
⊢ CycleAtTo π a x ⊂ CycleAtTo π b x | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
b : ℕ
ha : a < orderOf (π.cycleOf x)
hab : a < b
⊢ ∃ a_1 ∉ CycleAtTo π a x, insert a_1 (CycleAtTo π a x) ⊆ CycleAtTo π b x | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
b : ℕ
ha : a < orderOf (π.cycleOf x)
hab : a < b
⊢ CycleAtTo π a x ⊂ CycleAtTo π b x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleAtTo_strict_mono_lt_of_lt_lt_orderOf | [203, 1] | [206, 98] | exact ⟨_, pow_apply_not_mem_cycleAtTo_of_lt_orderOf_cycleOf ha, insert_cycleAtTo (le_refl _) hab⟩ | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
b : ℕ
ha : a < orderOf (π.cycleOf x)
hab : a < b
⊢ ∃ a_1 ∉ CycleAtTo π a x, insert a_1 (CycleAtTo π a x) ⊆ CycleAtTo π b x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
b : ℕ
ha : a < orderOf (π.cycleOf x)
hab : a < b
⊢ ∃ a_1 ∉ CycleAtTo π a x, insert a_1 (CycleAtTo π a x) ⊆ CycleAtTo π b x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleAt_gt_cycleAtTo_lt_orderOf_cycleOf | [208, 1] | [211, 54] | rw [cycleAt_eq_cycleAtTo_orderOf_cycleOf] | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h : a < orderOf (π.cycleOf x)
⊢ CycleAtTo π a x ⊂ CycleAt π x | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h : a < orderOf (π.cycleOf x)
⊢ CycleAtTo π a x ⊂ CycleAtTo π (orderOf (π.cycleOf x)) x | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h : a < orderOf (π.cycleOf x)
⊢ CycleAtTo π a x ⊂ CycleAt π x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleAt_gt_cycleAtTo_lt_orderOf_cycleOf | [208, 1] | [211, 54] | exact cycleAtTo_strict_mono_lt_of_lt_lt_orderOf h h | α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h : a < orderOf (π.cycleOf x)
⊢ CycleAtTo π a x ⊂ CycleAtTo π (orderOf (π.cycleOf x)) x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : DecidableEq α
π : Perm α
inst✝ : Fintype α
a : ℕ
x : α
h : a < orderOf (π.cycleOf x)
⊢ CycleAtTo π a x ⊂ CycleAtTo π (orderOf (π.cycleOf x)) x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleMin_eq_min_cycleAtTo | [222, 1] | [224, 63] | simp_rw [cycleMin_def, cycleAt_eq_cycleAtTo_orderOf_cycleOf] | α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
⊢ CycleMin π x = (CycleAtTo π (orderOf (π.cycleOf x)) x).min' ⋯ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
⊢ CycleMin π x = (CycleAtTo π (orderOf (π.cycleOf x)) x).min' ⋯
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleMin_of_fixed | [226, 1] | [229, 35] | simp_rw [cycleMin_eq_min_cycleAtTo, π.cycleOf_eq_one_iff.mpr h, orderOf_one,
cycleAtTo_one, min'_singleton] | α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
h : Function.IsFixedPt (⇑π) x
⊢ CycleMin π x = x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
h : Function.IsFixedPt (⇑π) x
⊢ CycleMin π x = x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleMin_eq_min_cycleAtTo_ge | [244, 1] | [246, 67] | simp_rw [cycleMin_def, cycleAt_eq_cycleAtTo_ge_orderOf_cycleOf ha] | α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
a : ℕ
cycleAtTo_nonempty : (CycleAtTo π a x).Nonempty
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleMin π x = (CycleAtTo π a x).min' cycleAtTo_nonempty | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
a : ℕ
cycleAtTo_nonempty : (CycleAtTo π a x).Nonempty
ha : orderOf (π.cycleOf x) ≤ a
⊢ CycleMin π x = (CycleAtTo π a x).min' cycleAtTo_nonempty
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleMin_le | [248, 1] | [250, 51] | rw [cycleMin_def] | α : Type u
inst✝² : DecidableEq α
π✝ : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
y : α
π : Perm α
x : α
h : π.SameCycle x y
⊢ CycleMin π x ≤ y | α : Type u
inst✝² : DecidableEq α
π✝ : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
y : α
π : Perm α
x : α
h : π.SameCycle x y
⊢ (CycleAt π x).min' ⋯ ≤ y | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π✝ : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
y : α
π : Perm α
x : α
h : π.SameCycle x y
⊢ CycleMin π x ≤ y
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleMin_le | [248, 1] | [250, 51] | exact Finset.min'_le _ y (mem_cycleAt_iff.mpr h) | α : Type u
inst✝² : DecidableEq α
π✝ : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
y : α
π : Perm α
x : α
h : π.SameCycle x y
⊢ (CycleAt π x).min' ⋯ ≤ y | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π✝ : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
y : α
π : Perm α
x : α
h : π.SameCycle x y
⊢ (CycleAt π x).min' ⋯ ≤ y
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | le_cycleMin | [267, 1] | [268, 70] | simp_rw [cycleMin_def, Finset.le_min'_iff, mem_cycleAt_iff] | α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x z : α
h : ∀ (y : α), π.SameCycle x y → z ≤ y
⊢ z ≤ CycleMin π x | α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x z : α
h : ∀ (y : α), π.SameCycle x y → z ≤ y
⊢ ∀ (y : α), π.SameCycle x y → z ≤ y | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x z : α
h : ∀ (y : α), π.SameCycle x y → z ≤ y
⊢ z ≤ CycleMin π x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | le_cycleMin | [267, 1] | [268, 70] | exact h | α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x z : α
h : ∀ (y : α), π.SameCycle x y → z ≤ y
⊢ ∀ (y : α), π.SameCycle x y → z ≤ y | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x z : α
h : ∀ (y : α), π.SameCycle x y → z ≤ y
⊢ ∀ (y : α), π.SameCycle x y → z ≤ y
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | le_cycleMin_iff | [270, 1] | [271, 60] | simp_rw [cycleMin_def, Finset.le_min'_iff, mem_cycleAt_iff] | α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
z x : α
⊢ z ≤ CycleMin π x ↔ ∀ (y : α), π.SameCycle x y → z ≤ y | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
z x : α
⊢ z ≤ CycleMin π x ↔ ∀ (y : α), π.SameCycle x y → z ≤ y
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | fastCycleMin_eq_min_cycleAtTo | [285, 1] | [297, 76] | induction' i with i hi generalizing x | α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
x : α
⊢ FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯ | case zero
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
⊢ FastCycleMin 0 π x = (CycleAtTo π (2 ^ 0) x).min' ⋯
case succ
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
⊢ FastCycleMin (i + 1) π x = (CycleAtTo π (2 ^ (i + 1)) x).min' ⋯ | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
x : α
⊢ FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | fastCycleMin_eq_min_cycleAtTo | [285, 1] | [297, 76] | simp_rw [fastCycleMin_zero_eq, pow_zero, cycleAtTo_one, min'_singleton] | case zero
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
⊢ FastCycleMin 0 π x = (CycleAtTo π (2 ^ 0) x).min' ⋯ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case zero
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
⊢ FastCycleMin 0 π x = (CycleAtTo π (2 ^ 0) x).min' ⋯
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | fastCycleMin_eq_min_cycleAtTo | [285, 1] | [297, 76] | simp_rw [fastCycleMin_succ_eq, hi, le_antisymm_iff, le_min_iff, Finset.le_min'_iff, min_le_iff,
mem_cycleAtTo_iff, Nat.pow_succ', Nat.two_mul, forall_exists_index, and_imp,
forall_apply_eq_imp_iff₂, ← forall_and, ← Equiv.Perm.mul_apply, ← pow_add, imp_and] | case succ
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
⊢ FastCycleMin (i + 1) π x = (CycleAtTo π (2 ^ (i + 1)) x).min' ⋯ | case succ
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
⊢ ∀ (x_1 : ℕ),
(x_1 < 2 ^ i + 2 ^ i →
(CycleAtTo π (2 ^ i) x).min' ⋯ ≤ (π ^ x_1) x ∨ (CycleAtTo π (2 ^ i) ((π ^ 2 ^ i) x)).min' ⋯ ≤ (π ^ x_1) x) ∧
(x_1 < 2 ^ i → (CycleAtTo π (2 ^ i + 2 ^ i) x).min' ⋯ ≤ (π ^ x_1) x) ∧
(x_1 < 2 ^ i → (CycleAtTo π (2 ^ i + 2 ^ i) x).min' ⋯ ≤ (π ^ (x_1 + 2 ^ i)) x) | Please generate a tactic in lean4 to solve the state.
STATE:
case succ
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
⊢ FastCycleMin (i + 1) π x = (CycleAtTo π (2 ^ (i + 1)) x).min' ⋯
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | fastCycleMin_eq_min_cycleAtTo | [285, 1] | [297, 76] | refine' fun b => And.intro (fun h => (lt_or_le b (2^i)).imp _ _) (And.intro _ _) <;>
refine' fun hb => min'_le _ _ _ | case succ
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
⊢ ∀ (x_1 : ℕ),
(x_1 < 2 ^ i + 2 ^ i →
(CycleAtTo π (2 ^ i) x).min' ⋯ ≤ (π ^ x_1) x ∨ (CycleAtTo π (2 ^ i) ((π ^ 2 ^ i) x)).min' ⋯ ≤ (π ^ x_1) x) ∧
(x_1 < 2 ^ i → (CycleAtTo π (2 ^ i + 2 ^ i) x).min' ⋯ ≤ (π ^ x_1) x) ∧
(x_1 < 2 ^ i → (CycleAtTo π (2 ^ i + 2 ^ i) x).min' ⋯ ≤ (π ^ (x_1 + 2 ^ i)) x) | case succ.refine'_1
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
h : b < 2 ^ i + 2 ^ i
hb : b < 2 ^ i
⊢ (π ^ b) x ∈ CycleAtTo π (2 ^ i) x
case succ.refine'_2
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
h : b < 2 ^ i + 2 ^ i
hb : 2 ^ i ≤ b
⊢ (π ^ b) x ∈ CycleAtTo π (2 ^ i) ((π ^ 2 ^ i) x)
case succ.refine'_3
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
hb : b < 2 ^ i
⊢ (π ^ b) x ∈ CycleAtTo π (2 ^ i + 2 ^ i) x
case succ.refine'_4
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
hb : b < 2 ^ i
⊢ (π ^ (b + 2 ^ i)) x ∈ CycleAtTo π (2 ^ i + 2 ^ i) x | Please generate a tactic in lean4 to solve the state.
STATE:
case succ
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
⊢ ∀ (x_1 : ℕ),
(x_1 < 2 ^ i + 2 ^ i →
(CycleAtTo π (2 ^ i) x).min' ⋯ ≤ (π ^ x_1) x ∨ (CycleAtTo π (2 ^ i) ((π ^ 2 ^ i) x)).min' ⋯ ≤ (π ^ x_1) x) ∧
(x_1 < 2 ^ i → (CycleAtTo π (2 ^ i + 2 ^ i) x).min' ⋯ ≤ (π ^ x_1) x) ∧
(x_1 < 2 ^ i → (CycleAtTo π (2 ^ i + 2 ^ i) x).min' ⋯ ≤ (π ^ (x_1 + 2 ^ i)) x)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | fastCycleMin_eq_min_cycleAtTo | [285, 1] | [297, 76] | exact apply_pow_mem_cycleAtTo_of_lt hb | case succ.refine'_1
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
h : b < 2 ^ i + 2 ^ i
hb : b < 2 ^ i
⊢ (π ^ b) x ∈ CycleAtTo π (2 ^ i) x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case succ.refine'_1
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
h : b < 2 ^ i + 2 ^ i
hb : b < 2 ^ i
⊢ (π ^ b) x ∈ CycleAtTo π (2 ^ i) x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | fastCycleMin_eq_min_cycleAtTo | [285, 1] | [297, 76] | exact apply_pow_mem_cycleAtTo_apply_pow_of_ge_of_lt h hb | case succ.refine'_2
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
h : b < 2 ^ i + 2 ^ i
hb : 2 ^ i ≤ b
⊢ (π ^ b) x ∈ CycleAtTo π (2 ^ i) ((π ^ 2 ^ i) x) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case succ.refine'_2
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
h : b < 2 ^ i + 2 ^ i
hb : 2 ^ i ≤ b
⊢ (π ^ b) x ∈ CycleAtTo π (2 ^ i) ((π ^ 2 ^ i) x)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | fastCycleMin_eq_min_cycleAtTo | [285, 1] | [297, 76] | exact apply_pow_mem_cycleAtTo_of_lt (lt_of_lt_of_le hb le_self_add) | case succ.refine'_3
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
hb : b < 2 ^ i
⊢ (π ^ b) x ∈ CycleAtTo π (2 ^ i + 2 ^ i) x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case succ.refine'_3
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
hb : b < 2 ^ i
⊢ (π ^ b) x ∈ CycleAtTo π (2 ^ i + 2 ^ i) x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | fastCycleMin_eq_min_cycleAtTo | [285, 1] | [297, 76] | exact apply_pow_mem_cycleAtTo_of_lt ((add_lt_add_iff_right _).mpr hb) | case succ.refine'_4
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
hb : b < 2 ^ i
⊢ (π ^ (b + 2 ^ i)) x ∈ CycleAtTo π (2 ^ i + 2 ^ i) x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case succ.refine'_4
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
i : ℕ
hi : ∀ {x : α}, FastCycleMin i π x = (CycleAtTo π (2 ^ i) x).min' ⋯
x : α
b : ℕ
hb : b < 2 ^ i
⊢ (π ^ (b + 2 ^ i)) x ∈ CycleAtTo π (2 ^ i + 2 ^ i) x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleMin_eq_fastCycleMin | [301, 1] | [303, 69] | rw [fastCycleMin_eq_min_cycleAtTo, cycleMin_eq_min_cycleAtTo_ge h] | α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
i : ℕ
h : orderOf (π.cycleOf x) ≤ 2 ^ i
⊢ FastCycleMin i π x = CycleMin π x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
i : ℕ
h : orderOf (π.cycleOf x) ≤ 2 ^ i
⊢ FastCycleMin i π x = CycleMin π x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleMin_eq_cycleMin_apply | [306, 1] | [307, 51] | simp_rw [cycleMin_def, cycleAt_apply_eq_cycleAt] | α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
⊢ CycleMin π x = CycleMin π (π x) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
⊢ CycleMin π x = CycleMin π (π x)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Cycles.lean | cycleMin_eq_cycleMin_apply_inv | [309, 1] | [310, 74] | rw [cycleMin_eq_cycleMin_apply (x := (π⁻¹ x)), Equiv.Perm.apply_inv_self] | α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
⊢ CycleMin π x = CycleMin π (π⁻¹ x) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : DecidableEq α
π : Perm α
inst✝¹ : Fintype α
inst✝ : LinearOrder α
x : α
⊢ CycleMin π x = CycleMin π (π⁻¹ x)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_apply_zero | [44, 1] | [47, 99] | ext <;> simp only [getBitRes_apply, finFunctionFinEquiv, Equiv.ofRightInverseOfCardLE_symm_apply,
Fin.val_zero', Nat.zero_div, Nat.zero_mod, Fin.zero_eta, finTwoEquiv_apply, zero_ne_one,
decide_False, Equiv.ofRightInverseOfCardLE_apply, Fin.val_zero, zero_mul, Finset.sum_const_zero] | a✝ : ℕ
i : Fin (a✝ + 1)
⊢ (getBitRes i) 0 = (false, 0) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
⊢ (getBitRes i) 0 = (false, 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_apply_zero | [49, 1] | [50, 40] | rw [getBit_apply, getBitRes_apply_zero] | a✝ : ℕ
i : Fin (a✝ + 1)
⊢ getBit i 0 = false | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
⊢ getBit i 0 = false
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_apply_zero | [52, 1] | [53, 40] | rw [getRes_apply, getBitRes_apply_zero] | a✝ : ℕ
i : Fin (a✝ + 1)
⊢ getRes i 0 = 0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
⊢ getRes i 0 = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply_false_zero | [55, 1] | [56, 80] | rw [mergeBitRes_apply, ← getBitRes_apply_zero (i := i), Equiv.symm_apply_apply] | a✝ : ℕ
i : Fin (a✝ + 1)
⊢ mergeBitRes i false 0 = 0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
⊢ mergeBitRes i false 0 = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_apply_two_pow | [58, 1] | [70, 74] | ext | m : ℕ
i : Fin (m + 1)
⊢ (getBitRes i) ⟨2 ^ ↑i, ⋯⟩ = (true, 0) | case a
m : ℕ
i : Fin (m + 1)
⊢ ((getBitRes i) ⟨2 ^ ↑i, ⋯⟩).1 = (true, 0).1
case a.h
m : ℕ
i : Fin (m + 1)
⊢ ↑((getBitRes i) ⟨2 ^ ↑i, ⋯⟩).2 = ↑(true, 0).2 | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ (getBitRes i) ⟨2 ^ ↑i, ⋯⟩ = (true, 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_apply_two_pow | [58, 1] | [70, 74] | simp only [getBitRes_apply, finFunctionFinEquiv, Equiv.ofRightInverseOfCardLE_symm_apply,
gt_iff_lt, zero_lt_two, pow_pos, Nat.div_self, Nat.one_mod, Fin.mk_one, finTwoEquiv_apply,
decide_True, Equiv.ofRightInverseOfCardLE_apply] | case a
m : ℕ
i : Fin (m + 1)
⊢ ((getBitRes i) ⟨2 ^ ↑i, ⋯⟩).1 = (true, 0).1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case a
m : ℕ
i : Fin (m + 1)
⊢ ((getBitRes i) ⟨2 ^ ↑i, ⋯⟩).1 = (true, 0).1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_apply_two_pow | [58, 1] | [70, 74] | simp only [getBitRes_apply, finFunctionFinEquiv_apply_val, finFunctionFinEquiv_symm_apply_val,
Fin.val_zero', Finset.sum_eq_zero_iff, Finset.mem_univ, mul_eq_zero, forall_true_left] | case a.h
m : ℕ
i : Fin (m + 1)
⊢ ↑((getBitRes i) ⟨2 ^ ↑i, ⋯⟩).2 = ↑(true, 0).2 | case a.h
m : ℕ
i : Fin (m + 1)
⊢ ∀ (x : Fin m), 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 ∨ 2 ^ ↑x = 0 | Please generate a tactic in lean4 to solve the state.
STATE:
case a.h
m : ℕ
i : Fin (m + 1)
⊢ ↑((getBitRes i) ⟨2 ^ ↑i, ⋯⟩).2 = ↑(true, 0).2
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_apply_two_pow | [58, 1] | [70, 74] | refine' fun x => Or.inl _ | case a.h
m : ℕ
i : Fin (m + 1)
⊢ ∀ (x : Fin m), 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 ∨ 2 ^ ↑x = 0 | case a.h
m : ℕ
i : Fin (m + 1)
x : Fin m
⊢ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 | Please generate a tactic in lean4 to solve the state.
STATE:
case a.h
m : ℕ
i : Fin (m + 1)
⊢ ∀ (x : Fin m), 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 ∨ 2 ^ ↑x = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_apply_two_pow | [58, 1] | [70, 74] | rcases (Fin.succAbove_ne i x).lt_or_lt with h | h <;> rw [Fin.lt_iff_val_lt_val] at h | case a.h
m : ℕ
i : Fin (m + 1)
x : Fin m
⊢ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 | case a.h.inl
m : ℕ
i : Fin (m + 1)
x : Fin m
h : ↑(i.succAbove x) < ↑i
⊢ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0
case a.h.inr
m : ℕ
i : Fin (m + 1)
x : Fin m
h : ↑i < ↑(i.succAbove x)
⊢ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 | Please generate a tactic in lean4 to solve the state.
STATE:
case a.h
m : ℕ
i : Fin (m + 1)
x : Fin m
⊢ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_apply_two_pow | [58, 1] | [70, 74] | rw [Nat.pow_div h.le zero_lt_two, Nat.pow_mod, Nat.mod_self,
Nat.zero_pow (Nat.sub_pos_of_lt h), Nat.zero_mod] | case a.h.inl
m : ℕ
i : Fin (m + 1)
x : Fin m
h : ↑(i.succAbove x) < ↑i
⊢ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case a.h.inl
m : ℕ
i : Fin (m + 1)
x : Fin m
h : ↑(i.succAbove x) < ↑i
⊢ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_apply_two_pow | [58, 1] | [70, 74] | rw [Nat.div_eq_of_lt (pow_lt_pow_right one_lt_two h), Nat.zero_mod] | case a.h.inr
m : ℕ
i : Fin (m + 1)
x : Fin m
h : ↑i < ↑(i.succAbove x)
⊢ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case a.h.inr
m : ℕ
i : Fin (m + 1)
x : Fin m
h : ↑i < ↑(i.succAbove x)
⊢ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_apply_two_pow | [72, 1] | [74, 45] | rw [getBit_apply, getBitRes_apply_two_pow] | m : ℕ
i : Fin (m + 1)
⊢ getBit i ⟨2 ^ ↑i, ⋯⟩ = true | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ getBit i ⟨2 ^ ↑i, ⋯⟩ = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_apply_zero_one | [76, 1] | [78, 85] | convert getBit_apply_two_pow | m : ℕ
⊢ getBit 0 1 = true | case h.e'_2.h.e'_3.h.h.e'_2
m : ℕ
⊢ ↑1 = 2 ^ ↑0 | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
⊢ getBit 0 1 = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_apply_zero_one | [76, 1] | [78, 85] | rw [Fin.val_one', Nat.mod_eq_of_lt (Nat.one_lt_pow' _ _ ), Fin.val_zero, pow_zero] | case h.e'_2.h.e'_3.h.h.e'_2
m : ℕ
⊢ ↑1 = 2 ^ ↑0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case h.e'_2.h.e'_3.h.h.e'_2
m : ℕ
⊢ ↑1 = 2 ^ ↑0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_apply_two_pow | [80, 1] | [82, 45] | rw [getRes_apply, getBitRes_apply_two_pow] | m : ℕ
i : Fin (m + 1)
⊢ getRes i ⟨2 ^ ↑i, ⋯⟩ = 0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ getRes i ⟨2 ^ ↑i, ⋯⟩ = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply_true_zero | [84, 1] | [86, 85] | rw [mergeBitRes_apply, ← getBitRes_apply_two_pow (i := i), Equiv.symm_apply_apply] | m : ℕ
i : Fin (m + 1)
⊢ mergeBitRes i true 0 = ⟨2 ^ ↑i, ⋯⟩ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ mergeBitRes i true 0 = ⟨2 ^ ↑i, ⋯⟩
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply' | [88, 1] | [97, 12] | unfold mergeBitRes getBitRes | m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ mergeBitRes i b p =
∑ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / 2 ^ ↑b % 2) i' * 2 ^ ↑i' | m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
b p =
∑ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / 2 ^ ↑b % 2) i' * 2 ^ ↑i' | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ mergeBitRes i b p =
∑ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / 2 ^ ↑b % 2) i' * 2 ^ ↑i'
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply' | [88, 1] | [97, 12] | simp [finFunctionFinEquiv] | m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
b p =
∑ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / 2 ^ ↑b % 2) i' * 2 ^ ↑i' | m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) i_1) * 2 ^ ↑i_1, ⋯⟩ =
∑ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / 2 ^ ↑b % 2) i' * 2 ^ ↑i' | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
b p =
∑ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / 2 ^ ↑b % 2) i' * 2 ^ ↑i'
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply' | [88, 1] | [97, 12] | norm_cast | m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) i_1) * 2 ^ ↑i_1, ⋯⟩ =
∑ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / 2 ^ ↑b % 2) i' * 2 ^ ↑i' | m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ⟨∑ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
∑ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x) | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) i_1) * 2 ^ ↑i_1, ⋯⟩ =
∑ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / 2 ^ ↑b % 2) i' * 2 ^ ↑i'
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply' | [88, 1] | [97, 12] | ext | m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ⟨∑ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
∑ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x) | case h
m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ↑⟨∑ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
↑(∑ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x)) | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ⟨∑ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
∑ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply' | [88, 1] | [97, 12] | simp | case h
m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ↑⟨∑ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
↑(∑ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x)) | case h
m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ∑ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x =
↑(∑ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / 2 ^ ↑b % 2) x * 2 ^ ↑x) | Please generate a tactic in lean4 to solve the state.
STATE:
case h
m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ↑⟨∑ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
↑(∑ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply' | [88, 1] | [97, 12] | norm_cast | case h
m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ∑ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x =
↑(∑ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / 2 ^ ↑b % 2) x * 2 ^ ↑x) | case h
m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ∑ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x =
↑(∑ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x)) | Please generate a tactic in lean4 to solve the state.
STATE:
case h
m : ℕ
i : Fin (m + 1)
b : Bool
p : BV m
⊢ ∑ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x =
↑(∑ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE ⋯ p / 2 ^ ↑b % 2) x * 2 ^ ↑x)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero | [99, 1] | [108, 70] | unfold mergeBitRes getBitRes | m : ℕ
p : BV m
i : Fin (m + 1)
⊢ mergeBitRes i true p = mergeBitRes i false p + mergeBitRes i true 0 | m : ℕ
p : BV m
i : Fin (m + 1)
⊢ Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
true p =
Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
false p +
Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
true 0 | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ mergeBitRes i true p = mergeBitRes i false p + mergeBitRes i true 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero | [99, 1] | [108, 70] | simp [finFunctionFinEquiv] | m : ℕ
p : BV m
i : Fin (m + 1)
⊢ Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
true p =
Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
false p +
Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
true 0 | m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) i_1) * 2 ^ ↑i_1, ⋯⟩ =
⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) i_1) * 2 ^ ↑i_1, ⋯⟩ +
⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) i_1) * 2 ^ ↑i_1, ⋯⟩ | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
true p =
Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
false p +
Function.curry
(⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i))
(finTwoEquiv.prodCongr finFunctionFinEquiv)).symm)
true 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero | [99, 1] | [108, 70] | norm_cast | m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) i_1) * 2 ^ ↑i_1, ⋯⟩ =
⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) i_1) * 2 ^ ↑i_1, ⋯⟩ +
⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) i_1) * 2 ^ ↑i_1, ⋯⟩ | m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
⟨∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ +
⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x, ⋯⟩ | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) i_1) * 2 ^ ↑i_1, ⋯⟩ =
⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) i_1) * 2 ^ ↑i_1, ⋯⟩ +
⟨∑ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) i_1) * 2 ^ ↑i_1, ⋯⟩
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero | [99, 1] | [108, 70] | simp_rw [Fin.add_def] | m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
⟨∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ +
⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x, ⋯⟩ | m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
⟨(∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x +
∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) %
2 ^ (m + 1),
⋯⟩ | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
⟨∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ +
⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x, ⋯⟩
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero | [99, 1] | [108, 70] | ext : 1 | m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
⟨(∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x +
∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) %
2 ^ (m + 1),
⋯⟩ | case h
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ↑⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
↑⟨(∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x +
∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) %
2 ^ (m + 1),
⋯⟩ | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
⟨(∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x +
∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) %
2 ^ (m + 1),
⋯⟩
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero | [99, 1] | [108, 70] | simp | case h
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ↑⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
↑⟨(∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x +
∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) %
2 ^ (m + 1),
⋯⟩ | case h
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x =
(∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x +
∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) %
2 ^ (m + 1) | Please generate a tactic in lean4 to solve the state.
STATE:
case h
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ↑⟨∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x, ⋯⟩ =
↑⟨(∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x +
∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) %
2 ^ (m + 1),
⋯⟩
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero | [99, 1] | [108, 70] | rw [← Finset.sum_add_distrib, Finset.sum_nat_mod, Finset.sum_congr] | case h
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x =
(∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x +
∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) %
2 ^ (m + 1) | case h
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ?m.88623.sum ?m.88625 =
(∑ i_1 : Fin (m + 1),
(↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) i_1) * 2 ^ ↑i_1 +
↑(i.insertNth 1 (fun b => 0) i_1) * 2 ^ ↑i_1) %
2 ^ (m + 1)) %
2 ^ (m + 1)
case h.h
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ Finset.univ = ?m.88623
case h.a
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ∀ x ∈ ?m.88623, ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x = ?m.88625 x
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ Finset (Fin (m + 1))
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ Fin (m + 1) → ℕ | Please generate a tactic in lean4 to solve the state.
STATE:
case h
m : ℕ
p : BV m
i : Fin (m + 1)
⊢ ∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x =
(∑ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => ⟨↑p / 2 ^ ↑b % 2, ⋯⟩) x) * 2 ^ ↑x +
∑ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) %
2 ^ (m + 1)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitResZero_symm_apply | [120, 1] | [121, 65] | cases b <;> rfl | b : Bool
a✝ : ℕ
p : BV a✝
⊢ getBitResZero.symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
b : Bool
a✝ : ℕ
p : BV a✝
⊢ getBitResZero.symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_zero | [123, 1] | [136, 61] | ext q : 1 | m : ℕ
⊢ getBitRes 0 = getBitResZero | case H
m : ℕ
q : BV (m + 1)
⊢ (getBitRes 0) q = getBitResZero q | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
⊢ getBitRes 0 = getBitResZero
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_zero | [123, 1] | [136, 61] | simp_rw [getBitRes_apply, getBitResZero_apply, Fin.zero_succAbove, finFunctionFinEquiv,
Equiv.ofRightInverseOfCardLE_symm_apply, Fin.val_zero, pow_zero, Nat.div_one,
finTwoEquiv_apply, Fin.val_succ, Equiv.ofRightInverseOfCardLE_apply,
Nat.pow_eq, Prod.mk.injEq, decide_eq_decide, Fin.ext_iff, Fin.val_one, Fin.coe_modNat,
Finset.sum_fin_eq_sum_range, dite_eq_ite, Fin.coe_divNat, true_and] | case H
m : ℕ
q : BV (m + 1)
⊢ (getBitRes 0) q = getBitResZero q | case H
m : ℕ
q : BV (m + 1)
⊢ (∑ x ∈ Finset.range m, if x < m then ↑q / 2 ^ (x + 1) % 2 * 2 ^ x else 0) = ↑q / 2 | Please generate a tactic in lean4 to solve the state.
STATE:
case H
m : ℕ
q : BV (m + 1)
⊢ (getBitRes 0) q = getBitResZero q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_zero | [123, 1] | [136, 61] | rw [Finset.sum_ite_of_true (h := fun _ H => (Finset.mem_range.mp H))] | case H
m : ℕ
q : BV (m + 1)
⊢ (∑ x ∈ Finset.range m, if x < m then ↑q / 2 ^ (x + 1) % 2 * 2 ^ x else 0) = ↑q / 2 | case H
m : ℕ
q : BV (m + 1)
⊢ ∑ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x = ↑q / 2 | Please generate a tactic in lean4 to solve the state.
STATE:
case H
m : ℕ
q : BV (m + 1)
⊢ (∑ x ∈ Finset.range m, if x < m then ↑q / 2 ^ (x + 1) % 2 * 2 ^ x else 0) = ↑q / 2
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_zero | [123, 1] | [136, 61] | refine' Nat.eq_of_mul_eq_mul_left (zero_lt_two)
(add_right_cancel (b := (q : ℕ) / 2 ^ 0 % 2 * 2 ^ 0) _) | case H
m : ℕ
q : BV (m + 1)
⊢ ∑ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x = ↑q / 2 | case H
m : ℕ
q : BV (m + 1)
⊢ 2 * ∑ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x + ↑q / 2 ^ 0 % 2 * 2 ^ 0 =
2 * (↑q / 2) + ↑q / 2 ^ 0 % 2 * 2 ^ 0 | Please generate a tactic in lean4 to solve the state.
STATE:
case H
m : ℕ
q : BV (m + 1)
⊢ ∑ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x = ↑q / 2
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_zero | [123, 1] | [136, 61] | simp_rw [Finset.mul_sum, mul_left_comm (2 : ℕ), ← Nat.pow_succ', Nat.succ_eq_add_one,
← Finset.sum_range_succ' (fun x => (q : ℕ) / 2 ^ x % 2 * 2 ^ x), pow_zero, Nat.div_one,
mul_one, Nat.div_add_mod, Finset.sum_range, ← finFunctionFinEquiv_symm_apply_val,
← finFunctionFinEquiv_apply_val, Equiv.apply_symm_apply] | case H
m : ℕ
q : BV (m + 1)
⊢ 2 * ∑ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x + ↑q / 2 ^ 0 % 2 * 2 ^ 0 =
2 * (↑q / 2) + ↑q / 2 ^ 0 % 2 * 2 ^ 0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H
m : ℕ
q : BV (m + 1)
⊢ 2 * ∑ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x + ↑q / 2 ^ 0 % 2 * 2 ^ 0 =
2 * (↑q / 2) + ↑q / 2 ^ 0 % 2 * 2 ^ 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_zero_apply | [138, 1] | [139, 48] | simp_rw [getBitRes_zero, getBitResZero_apply] | m : ℕ
q : BV (m + 1)
⊢ (getBitRes 0) q = (finTwoEquiv q.modNat, q.divNat) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1)
⊢ (getBitRes 0) q = (finTwoEquiv q.modNat, q.divNat)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_zero_symm_apply | [141, 1] | [142, 100] | simp_rw [getBitRes_zero, getBitResZero_symm_apply] | m : ℕ
b : Bool
p : BV m
⊢ (getBitRes 0).symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b : Bool
p : BV m
⊢ (getBitRes 0).symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_zero | [144, 1] | [145, 47] | simp_rw [getBit_apply, getBitRes_zero_apply] | a✝ : ℕ
q : BV (a✝ + 1)
⊢ getBit 0 q = finTwoEquiv q.modNat | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
q : BV (a✝ + 1)
⊢ getBit 0 q = finTwoEquiv q.modNat
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_zero | [147, 1] | [148, 47] | simp_rw [getRes_apply, getBitRes_zero_apply] | a✝ : ℕ
q : BV (a✝ + 1)
⊢ getRes 0 q = q.divNat | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
q : BV (a✝ + 1)
⊢ getRes 0 q = q.divNat
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_zero | [150, 1] | [151, 57] | simp_rw [mergeBitRes_apply, getBitRes_zero_symm_apply] | b : Bool
a✝ : ℕ
p : BV a✝
⊢ mergeBitRes 0 b p = finProdFinEquiv (p, bif b then 1 else 0) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
b : Bool
a✝ : ℕ
p : BV a✝
⊢ mergeBitRes 0 b p = finProdFinEquiv (p, bif b then 1 else 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_zero_divNat_modNat | [153, 1] | [156, 25] | simp_rw [← finProdFinEquiv_symm_apply, Equiv.symm_apply_eq] | b : Bool
a✝ : ℕ
p : BV a✝
⊢ ((mergeBitRes 0 b p).divNat, (mergeBitRes 0 b p).modNat) = (p, bif b then 1 else 0) | b : Bool
a✝ : ℕ
p : BV a✝
⊢ mergeBitRes 0 b p = finProdFinEquiv (p, bif b then 1 else 0) | Please generate a tactic in lean4 to solve the state.
STATE:
b : Bool
a✝ : ℕ
p : BV a✝
⊢ ((mergeBitRes 0 b p).divNat, (mergeBitRes 0 b p).modNat) = (p, bif b then 1 else 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_zero_divNat_modNat | [153, 1] | [156, 25] | exact mergeBitRes_zero | b : Bool
a✝ : ℕ
p : BV a✝
⊢ mergeBitRes 0 b p = finProdFinEquiv (p, bif b then 1 else 0) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
b : Bool
a✝ : ℕ
p : BV a✝
⊢ mergeBitRes 0 b p = finProdFinEquiv (p, bif b then 1 else 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_zero_apply_true_zero_eq_one | [164, 1] | [167, 43] | simp_rw [mergeBitRes_zero, Fin.ext_iff, finProdFinEquiv_apply_val, Fin.val_zero', mul_zero,
add_zero, Bool.cond_true, Fin.val_one, Fin.val_one', ← Nat.pow_succ,
Nat.mod_eq_of_lt (Nat.one_lt_pow' _ _ )] | m : ℕ
⊢ mergeBitRes 0 true 0 = 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
⊢ mergeBitRes 0 true 0 = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_base_true | [169, 1] | [170, 82] | rw [Fin.eq_zero p, Fin.eq_zero i] | i : Fin (0 + 1)
p : BV 0
⊢ mergeBitRes i true p = 1 | i : Fin (0 + 1)
p : BV 0
⊢ mergeBitRes 0 true 0 = 1 | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
p : BV 0
⊢ mergeBitRes i true p = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_base_true | [169, 1] | [170, 82] | exact mergeBitRes_zero_apply_true_zero_eq_one | i : Fin (0 + 1)
p : BV 0
⊢ mergeBitRes 0 true 0 = 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
p : BV 0
⊢ mergeBitRes 0 true 0 = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_base_false | [172, 1] | [173, 56] | rw [Fin.eq_zero p] | i : Fin (0 + 1)
p : BV 0
⊢ mergeBitRes i false p = 0 | i : Fin (0 + 1)
p : BV 0
⊢ mergeBitRes i false 0 = 0 | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
p : BV 0
⊢ mergeBitRes i false p = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_base_false | [172, 1] | [173, 56] | exact mergeBitRes_apply_false_zero | i : Fin (0 + 1)
p : BV 0
⊢ mergeBitRes i false 0 = 0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
p : BV 0
⊢ mergeBitRes i false 0 = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_base | [178, 1] | [180, 65] | rw [Fin.eq_zero i] | i : Fin (0 + 1)
q : BV (0 + 1)
⊢ getBit i q = decide (q = 1) | i : Fin (0 + 1)
q : BV (0 + 1)
⊢ getBit 0 q = decide (q = 1) | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
q : BV (0 + 1)
⊢ getBit i q = decide (q = 1)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_base | [178, 1] | [180, 65] | rcases Fin.exists_fin_two.mp ⟨q, rfl⟩ with (rfl | rfl) <;> rfl | i : Fin (0 + 1)
q : BV (0 + 1)
⊢ getBit 0 q = decide (q = 1) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
q : BV (0 + 1)
⊢ getBit 0 q = decide (q = 1)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_base | [182, 1] | [184, 65] | rw [Fin.eq_zero i] | i : Fin (0 + 1)
q : BV (0 + 1)
⊢ getRes i q = 0 | i : Fin (0 + 1)
q : BV (0 + 1)
⊢ getRes 0 q = 0 | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
q : BV (0 + 1)
⊢ getRes i q = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_base | [182, 1] | [184, 65] | rcases Fin.exists_fin_two.mp ⟨q, rfl⟩ with (rfl | rfl) <;> rfl | i : Fin (0 + 1)
q : BV (0 + 1)
⊢ getRes 0 q = 0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
q : BV (0 + 1)
⊢ getRes 0 q = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_succ | [202, 1] | [207, 53] | simp_rw [Equiv.ext_iff, getBitResSucc_apply,
getBitRes_apply, getBitRes_symm_apply, Equiv.symm_apply_apply,
Prod.mk.injEq, EmbeddingLike.apply_eq_iff_eq,
Fin.eq_insertNth_iff, Fin.succAbove_zero, Fin.succ_succAbove_zero,
Fin.succ_succAbove_succ, true_and, implies_true] | m : ℕ
i : Fin (m + 1)
⊢ getBitRes i.succ = getBitResSucc i | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ getBitRes i.succ = getBitResSucc i
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_succ_apply | [209, 1] | [212, 43] | rw [getBitRes_succ, getBitResSucc_apply] | m : ℕ
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ (getBitRes i.succ) q =
(((getBitRes i) ((getBitRes 0) q).2).1,
(getBitRes 0).symm (((getBitRes 0) q).1, ((getBitRes i) ((getBitRes 0) q).2).2)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ (getBitRes i.succ) q =
(((getBitRes i) ((getBitRes 0) q).2).1,
(getBitRes 0).symm (((getBitRes 0) q).1, ((getBitRes i) ((getBitRes 0) q).2).2))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_succ_symm_apply | [214, 1] | [216, 48] | rw [getBitRes_succ, getBitResSucc_symm_apply] | m : ℕ
b : Bool
p : BV (m + 1)
i : Fin (m + 1)
⊢ (getBitRes i.succ).symm (b, p) = (getBitRes 0).symm (((getBitRes 0) p).1, (getBitRes i).symm (b, ((getBitRes 0) p).2)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b : Bool
p : BV (m + 1)
i : Fin (m + 1)
⊢ (getBitRes i.succ).symm (b, p) = (getBitRes 0).symm (((getBitRes 0) p).1, (getBitRes i).symm (b, ((getBitRes 0) p).2))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_succ | [218, 1] | [220, 80] | simp_rw [getRes_apply, mergeBitRes_apply, getBit_apply, getBitRes_succ_apply] | m : ℕ
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ getRes i.succ q = mergeBitRes 0 (getBit 0 q) (getRes i (getRes 0 q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ getRes i.succ q = mergeBitRes 0 (getBit 0 q) (getRes i (getRes 0 q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_succ | [222, 1] | [224, 61] | simp_rw [getRes_apply, getBit_apply, getBitRes_succ_apply] | m : ℕ
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ getBit i.succ q = getBit i (getRes 0 q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ getBit i.succ q = getBit i (getRes 0 q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_succ | [226, 1] | [228, 85] | simp_rw [mergeBitRes_apply, getBit_apply, getRes_apply, getBitRes_succ_symm_apply] | m : ℕ
b : Bool
q : BV (m + 1)
i : Fin (m + 1)
⊢ mergeBitRes i.succ b q = mergeBitRes 0 (getBit 0 q) (mergeBitRes i b (getRes 0 q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b : Bool
q : BV (m + 1)
i : Fin (m + 1)
⊢ mergeBitRes i.succ b q = mergeBitRes 0 (getBit 0 q) (mergeBitRes i b (getRes 0 q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitResLast_symm_apply | [230, 1] | [231, 65] | cases b <;> rfl | b : Bool
a✝ : ℕ
p : BV a✝
⊢ getBitResZero.symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
b : Bool
a✝ : ℕ
p : BV a✝
⊢ getBitResZero.symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_castSucc | [251, 1] | [256, 61] | simp_rw [Equiv.ext_iff, getBitResCastSucc_apply,
getBitRes_apply, getBitRes_symm_apply, Equiv.symm_apply_apply,
Prod.mk.injEq, EmbeddingLike.apply_eq_iff_eq,
Fin.eq_insertNth_iff, Fin.succAbove_last, Fin.castSucc_succAbove_last,
Fin.castSucc_succAbove_castSucc, true_and, implies_true] | m : ℕ
i : Fin (m + 1)
⊢ getBitRes i.castSucc = getBitResCastSucc i | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ getBitRes i.castSucc = getBitResCastSucc i
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_castSucc_apply | [258, 1] | [262, 51] | rw [getBitRes_castSucc, getBitResCastSucc_apply] | m : ℕ
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ (getBitRes i.castSucc) q =
(((getBitRes i) ((getBitRes (Fin.last (m + 1))) q).2).1,
(getBitRes (Fin.last m)).symm
(((getBitRes (Fin.last (m + 1))) q).1, ((getBitRes i) ((getBitRes (Fin.last (m + 1))) q).2).2)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ (getBitRes i.castSucc) q =
(((getBitRes i) ((getBitRes (Fin.last (m + 1))) q).2).1,
(getBitRes (Fin.last m)).symm
(((getBitRes (Fin.last (m + 1))) q).1, ((getBitRes i) ((getBitRes (Fin.last (m + 1))) q).2).2))
TACTIC:
|
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