url stringclasses 147
values | commit stringclasses 147
values | file_path stringlengths 7 101 | full_name stringlengths 1 94 | start stringlengths 6 10 | end stringlengths 6 11 | tactic stringlengths 1 11.2k | state_before stringlengths 3 2.09M | state_after stringlengths 6 2.09M | input stringlengths 73 2.09M |
|---|---|---|---|---|---|---|---|---|---|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_ne_self | [856, 1] | [859, 46] | rw [getBit_flipBit, ne_eq, Bool.not_not_eq] | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ getBit i ((flipBit i) q) ≠ getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ getBit i ((flipBit i) q) ≠ getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt | [861, 1] | [869, 67] | rcases mergeBitRes_surj 0 q with ⟨bq, pq, rfl⟩ | a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
⊢ getBit 0 r = false ∧ getBit 0 q = true ∧ getRes 0 r = getRes 0 q | case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) r
⊢ getBit 0 r = false ∧ getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 r = getRes 0 (mergeBitRes 0 bq pq) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
⊢ getBit 0 r = false ∧ getBit 0 q = true ∧ getRes 0 r = getRes 0 q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt | [861, 1] | [869, 67] | rcases mergeBitRes_surj 0 r with ⟨br, pr, rfl⟩ | case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) r
⊢ getBit 0 r = false ∧ getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 r = getRes 0 (mergeBitRes 0 bq pq) | case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes 0 br pr < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) (mergeBitRes 0 br pr)
⊢ getBit 0 (mergeBitRes 0 br pr) = false ∧
getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 (mergeBitRes 0 br pr) = getRes 0 (mergeBitRes 0 bq pq) | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) r
⊢ getBit 0 r = false ∧ getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 r = getRes 0 (mergeBitRes 0 bq pq)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt | [861, 1] | [869, 67] | simp_rw [flipBit_mergeBitRes, getBit_mergeBitRes, getRes_mergeBitRes,
Fin.lt_iff_val_lt_val, mergeBitRes_zero, finProdFinEquiv_apply_val, Bool.cond_not, add_comm,
Bool.apply_cond (Fin.val), Fin.val_one, Fin.val_zero] at hf h ⊢ | case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes 0 br pr < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) (mergeBitRes 0 br pr)
⊢ getBit 0 (mergeBitRes 0 br pr) = false ∧
getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 (mergeBitRes 0 br pr) = getRes 0 (mergeBitRes 0 bq pq) | case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
⊢ br = false ∧ bq = true ∧ pr = pq | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes 0 br pr < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) (mergeBitRes 0 br pr)
⊢ getBit 0 (mergeBitRes 0 br pr) = false ∧
getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 (mergeBitRes 0 br pr) = getRes 0 (mergeBitRes 0 bq pq)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt | [861, 1] | [869, 67] | rcases Nat.eq_false_true_of_cond_succ_lt_of_cond_succ_lt h hf with ⟨hr, hq, he⟩ | case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
⊢ br = false ∧ bq = true ∧ pr = pq | case intro.intro.intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
hr : br = false
hq : bq = true
he : 2 * ↑pr = 2 * ↑pq
⊢ br = false ∧ bq = true ∧ pr = pq | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
⊢ br = false ∧ bq = true ∧ pr = pq
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt | [861, 1] | [869, 67] | exact ⟨hr, hq, Fin.ext (Nat.eq_of_mul_eq_mul_left zero_lt_two he)⟩ | case intro.intro.intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
hr : br = false
hq : bq = true
he : 2 * ↑pr = 2 * ↑pq
⊢ br = false ∧ bq = true ∧ pr = pq | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
hr : br = false
hq : bq = true
he : 2 * ↑pr = 2 * ↑pq
⊢ br = false ∧ bq = true ∧ pr = pq
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt | [871, 1] | [874, 65] | rcases getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt h hf with ⟨hr, hq, hrq⟩ | a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
⊢ r = (flipBit 0) q | case intro.intro
a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
hr : getBit 0 r = false
hq : getBit 0 q = true
hrq : getRes 0 r = getRes 0 q
⊢ r = (flipBit 0) q | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
⊢ r = (flipBit 0) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt | [871, 1] | [874, 65] | simp only [eq_flipBit_iff, hr, hq, hrq, Bool.not_true, and_self] | case intro.intro
a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
hr : getBit 0 r = false
hq : getBit 0 q = true
hrq : getRes 0 r = getRes 0 q
⊢ r = (flipBit 0) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
hr : getBit 0 r = false
hq : getBit 0 q = true
hrq : getRes 0 r = getRes 0 q
⊢ r = (flipBit 0) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | rcases mergeBitRes_surj i q with ⟨bq, pq, rfl⟩ | a✝ : ℕ
r q : BV (a✝ + 1)
i : Fin (a✝ + 1)
h : r < q
hf : (flipBit i) q < (flipBit i) r
⊢ ∀ k ≥ i, getBit k r = getBit k ((flipBit i) q) | case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) r
⊢ ∀ k ≥ i, getBit k r = getBit k ((flipBit i) (mergeBitRes i bq pq)) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
r q : BV (a✝ + 1)
i : Fin (a✝ + 1)
h : r < q
hf : (flipBit i) q < (flipBit i) r
⊢ ∀ k ≥ i, getBit k r = getBit k ((flipBit i) q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | rcases mergeBitRes_surj i r with ⟨br, pr, rfl⟩ | case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) r
⊢ ∀ k ≥ i, getBit k r = getBit k ((flipBit i) (mergeBitRes i bq pq)) | case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) (mergeBitRes i br pr)
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq)) | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) r
⊢ ∀ k ≥ i, getBit k r = getBit k ((flipBit i) (mergeBitRes i bq pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | simp_rw [flipBit_mergeBitRes] at hf | case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) (mergeBitRes i br pr)
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq)) | case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : mergeBitRes i (!bq) pq < mergeBitRes i (!br) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq)) | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) (mergeBitRes i br pr)
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | cases br <;> cases bq | case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : mergeBitRes i (!bq) pq < mergeBitRes i (!br) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq)) | case intro.intro.intro.intro.false.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i false pq))
case intro.intro.intro.intro.false.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i true pq))
case intro.intro.intro.intro.true.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i false pq))
case intro.intro.intro.intro.true.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i true pq)) | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : mergeBitRes i (!bq) pq < mergeBitRes i (!br) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | sorry | case intro.intro.intro.intro.false.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i false pq)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro.false.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i false pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | sorry | case intro.intro.intro.intro.false.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i true pq)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro.false.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i true pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | sorry | case intro.intro.intro.intro.true.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i false pq)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro.true.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i false pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | sorry | case intro.intro.intro.intro.true.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i true pq)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro.true.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i true pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBitCore_condFlipBitCore | [897, 1] | [899, 87] | rcases (c (getRes i q)).dichotomy with h | h <;>
simp only [condFlipBitCore, h, cond_true, cond_false, getRes_flipBit, flipBit_flipBit] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ condFlipBitCore i c (condFlipBitCore i c q) = q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ condFlipBitCore i c (condFlipBitCore i c q) = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_eq_mergeBitRes | [913, 1] | [917, 49] | rw [condFlipBit_apply] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) q = mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q) | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif c (getRes i q) then (flipBit i) q else q) = mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) q = mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_eq_mergeBitRes | [913, 1] | [917, 49] | cases (c (getRes i q)) | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif c (getRes i q) then (flipBit i) q else q) = mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q) | case false
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif false then (flipBit i) q else q) = mergeBitRes i (xor false (getBit i q)) (getRes i q)
case true
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif true then (flipBit i) q else q) = mergeBitRes i (xor true (getBit i q)) (getRes i q) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif c (getRes i q) then (flipBit i) q else q) = mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_eq_mergeBitRes | [913, 1] | [917, 49] | rw [cond_false, Bool.false_xor, mergeBitRes_getBit_getRes] | case false
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif false then (flipBit i) q else q) = mergeBitRes i (xor false (getBit i q)) (getRes i q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case false
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif false then (flipBit i) q else q) = mergeBitRes i (xor false (getBit i q)) (getRes i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_eq_mergeBitRes | [913, 1] | [917, 49] | rw [cond_true, Bool.true_xor, flipBit_apply] | case true
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif true then (flipBit i) q else q) = mergeBitRes i (xor true (getBit i q)) (getRes i q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case true
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif true then (flipBit i) q else q) = mergeBitRes i (xor true (getBit i q)) (getRes i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_eq_swap_apply | [919, 1] | [921, 80] | exact condFlipBit_apply_eq_mergeBitRes.trans (Equiv.swap_apply_left _ _).symm | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) q = (Equiv.swap q (mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q))) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) q = (Equiv.swap q (mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q))) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_base | [923, 1] | [926, 22] | ext q : 1 | i : Fin (0 + 1)
c : BV 0 → Bool
⊢ condFlipBit i c = bif c 0 then Equiv.swap 0 1 else 1 | case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (condFlipBit i c) q = (bif c 0 then Equiv.swap 0 1 else 1) q | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
c : BV 0 → Bool
⊢ condFlipBit i c = bif c 0 then Equiv.swap 0 1 else 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_base | [923, 1] | [926, 22] | rw [condFlipBit_apply, Fin.eq_zero (getRes i q), flipBit_base] | case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (condFlipBit i c) q = (bif c 0 then Equiv.swap 0 1 else 1) q | case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (bif c 0 then (Equiv.swap 0 1) q else q) = (bif c 0 then Equiv.swap 0 1 else 1) q | Please generate a tactic in lean4 to solve the state.
STATE:
case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (condFlipBit i c) q = (bif c 0 then Equiv.swap 0 1 else 1) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_base | [923, 1] | [926, 22] | cases (c 0) <;> rfl | case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (bif c 0 then (Equiv.swap 0 1) q else q) = (bif c 0 then Equiv.swap 0 1 else 1) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (bif c 0 then (Equiv.swap 0 1) q else q) = (bif c 0 then Equiv.swap 0 1 else 1) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_mergeBitRes | [928, 1] | [930, 78] | rw [condFlipBit_apply_eq_mergeBitRes, getRes_mergeBitRes, getBit_mergeBitRes] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
b : Bool
p : BV a✝
⊢ (condFlipBit i c) (mergeBitRes i b p) = mergeBitRes i (xor (c p) b) p | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
b : Bool
p : BV a✝
⊢ (condFlipBit i c) (mergeBitRes i b p) = mergeBitRes i (xor (c p) b) p
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_mul_self | [942, 1] | [945, 54] | ext | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ condFlipBit i c * condFlipBit i c = 1 | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i c) x✝) = ↑(1 x✝) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ condFlipBit i c * condFlipBit i c = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_mul_self | [942, 1] | [945, 54] | simp_rw [Equiv.Perm.coe_mul, Function.comp_apply,
condFlipBit_condFlipBit, Equiv.Perm.coe_one, id_eq] | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i c) x✝) = ↑(1 x✝) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i c) x✝) = ↑(1 x✝)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_mul_cancel_right | [947, 1] | [949, 48] | rw [mul_assoc, condFlipBit_mul_self, mul_one] | a✝ : ℕ
ρ : Equiv.Perm (BV (a✝ + 1))
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ ρ * condFlipBit i c * condFlipBit i c = ρ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
ρ : Equiv.Perm (BV (a✝ + 1))
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ ρ * condFlipBit i c * condFlipBit i c = ρ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_mul_cancel_left | [951, 1] | [953, 50] | rw [← mul_assoc, condFlipBit_mul_self, one_mul] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
ρ : Equiv.Perm (BV (a✝ + 1))
⊢ condFlipBit i c * (condFlipBit i c * ρ) = ρ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
ρ : Equiv.Perm (BV (a✝ + 1))
⊢ condFlipBit i c * (condFlipBit i c * ρ) = ρ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_flipBit_of_all_true | [955, 1] | [958, 6] | ext | a✝ : ℕ
i : Fin (a✝ + 1)
⊢ flipBit i = condFlipBit i (Function.const (BV a✝) true) | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑((condFlipBit i (Function.const (BV a✝) true)) x✝) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
⊢ flipBit i = condFlipBit i (Function.const (BV a✝) true)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_flipBit_of_all_true | [955, 1] | [958, 6] | rw [condFlipBit_apply] | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑((condFlipBit i (Function.const (BV a✝) true)) x✝) | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑(bif Function.const (BV a✝) true (getRes i x✝) then (flipBit i) x✝ else x✝) | Please generate a tactic in lean4 to solve the state.
STATE:
case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑((condFlipBit i (Function.const (BV a✝) true)) x✝)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_flipBit_of_all_true | [955, 1] | [958, 6] | rfl | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑(bif Function.const (BV a✝) true (getRes i x✝) then (flipBit i) x✝ else x✝) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑(bif Function.const (BV a✝) true (getRes i x✝) then (flipBit i) x✝ else x✝)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_comm | [962, 1] | [965, 42] | simp_rw [condFlipBit_apply_eq_mergeBitRes, getRes_mergeBitRes,
getBit_mergeBitRes, Bool.xor_left_comm] | a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((condFlipBit i d) q) = (condFlipBit i d) ((condFlipBit i c) q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((condFlipBit i d) q) = (condFlipBit i d) ((condFlipBit i c) q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_comm | [967, 1] | [969, 80] | ext | a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
⊢ condFlipBit i c * condFlipBit i d = condFlipBit i d * condFlipBit i c | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i d) x✝) = ↑((condFlipBit i d * condFlipBit i c) x✝) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
⊢ condFlipBit i c * condFlipBit i d = condFlipBit i d * condFlipBit i c
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_comm | [967, 1] | [969, 80] | simp_rw [Equiv.Perm.coe_mul, Function.comp_apply, condFlipBit_apply_comm] | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i d) x✝) = ↑((condFlipBit i d * condFlipBit i c) x✝) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i d) x✝) = ↑((condFlipBit i d * condFlipBit i c) x✝)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_comm_flipBit | [971, 1] | [973, 63] | rw [condFlipBit_flipBit_of_all_true, condFlipBit_apply_comm] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((flipBit i) q) = (flipBit i) ((condFlipBit i c) q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((flipBit i) q) = (flipBit i) ((condFlipBit i c) q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_comm_flipBit | [975, 1] | [977, 57] | rw [condFlipBit_flipBit_of_all_true, condFlipBit_comm] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ condFlipBit i c * flipBit i = flipBit i * condFlipBit i c | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ condFlipBit i c * flipBit i = flipBit i * condFlipBit i c
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_flipBit | [979, 1] | [984, 41] | rw [condFlipBit_apply_comm_flipBit] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((flipBit i) q) = bif c (getRes i q) then q else (flipBit i) q | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (flipBit i) ((condFlipBit i c) q) = bif c (getRes i q) then q else (flipBit i) q | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((flipBit i) q) = bif c (getRes i q) then q else (flipBit i) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_flipBit | [979, 1] | [984, 41] | rcases (c (getRes i q)).dichotomy with h | h <;> rw [condFlipBit_apply, h] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (flipBit i) ((condFlipBit i c) q) = bif c (getRes i q) then q else (flipBit i) q | case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ (flipBit i) (bif false then (flipBit i) q else q) = bif false then q else (flipBit i) q
case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ (flipBit i) (bif true then (flipBit i) q else q) = bif true then q else (flipBit i) q | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (flipBit i) ((condFlipBit i c) q) = bif c (getRes i q) then q else (flipBit i) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_flipBit | [979, 1] | [984, 41] | simp_rw [cond_false] | case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ (flipBit i) (bif false then (flipBit i) q else q) = bif false then q else (flipBit i) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ (flipBit i) (bif false then (flipBit i) q else q) = bif false then q else (flipBit i) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_flipBit | [979, 1] | [984, 41] | simp_rw [cond_true, flipBit_flipBit] | case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ (flipBit i) (bif true then (flipBit i) q else q) = bif true then q else (flipBit i) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ (flipBit i) (bif true then (flipBit i) q else q) = bif true then q else (flipBit i) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_condFlipBit | [986, 1] | [990, 33] | rcases (c (getRes i q)).dichotomy with h | h <;> rw [condFlipBit_apply, h] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getRes i ((condFlipBit i c) q) = getRes i q | case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ getRes i (bif false then (flipBit i) q else q) = getRes i q
case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ getRes i (bif true then (flipBit i) q else q) = getRes i q | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getRes i ((condFlipBit i c) q) = getRes i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_condFlipBit | [986, 1] | [990, 33] | rfl | case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ getRes i (bif false then (flipBit i) q else q) = getRes i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ getRes i (bif false then (flipBit i) q else q) = getRes i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_condFlipBit | [986, 1] | [990, 33] | rw [cond_true, getRes_flipBit] | case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ getRes i (bif true then (flipBit i) q else q) = getRes i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ getRes i (bif true then (flipBit i) q else q) = getRes i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit | [992, 1] | [995, 73] | rcases (c (getRes i q)).dichotomy with hc | hc <;>
simp only [condFlipBit_apply, cond_false, hc, cond_true, getBit_flipBit] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = bif c (getRes i q) then !getBit i q else getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = bif c (getRes i q) then !getBit i q else getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit' | [997, 1] | [1001, 49] | rcases (c (getRes i q)).dichotomy with hc | hc <;>
simp only [condFlipBit_apply, hc, cond_false, cond_true,
Bool.false_xor, Bool.true_xor, getBit_flipBit] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = xor (c (getRes i q)) (getBit i q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = xor (c (getRes i q)) (getBit i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit'' | [1003, 1] | [1006, 90] | rcases (getBit i q).dichotomy with hc | hc <;>
simp only [getBit_condFlipBit', hc, Bool.xor_false, Bool.xor_true, cond_true, cond_false] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = bif getBit i q then !c (getRes i q) else c (getRes i q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = bif getBit i q then !c (getRes i q) else c (getRes i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit_of_ne | [1008, 1] | [1013, 45] | rw [condFlipBit_apply] | m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
⊢ getBit i ((condFlipBit j c) q) = getBit i q | m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
⊢ getBit i (bif c (getRes j q) then (flipBit j) q else q) = getBit i q | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
⊢ getBit i ((condFlipBit j c) q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit_of_ne | [1008, 1] | [1013, 45] | rcases (c (getRes j q)).dichotomy with (h | h) <;> simp_rw [h] | m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
⊢ getBit i (bif c (getRes j q) then (flipBit j) q else q) = getBit i q | case inl
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = false
⊢ getBit i (bif false then (flipBit j) q else q) = getBit i q
case inr
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = true
⊢ getBit i (bif true then (flipBit j) q else q) = getBit i q | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
⊢ getBit i (bif c (getRes j q) then (flipBit j) q else q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit_of_ne | [1008, 1] | [1013, 45] | rw [cond_false] | case inl
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = false
⊢ getBit i (bif false then (flipBit j) q else q) = getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = false
⊢ getBit i (bif false then (flipBit j) q else q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit_of_ne | [1008, 1] | [1013, 45] | rw [cond_true, getBit_flipBit_of_ne hij] | case inr
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = true
⊢ getBit i (bif true then (flipBit j) q else q) = getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = true
⊢ getBit i (bif true then (flipBit j) q else q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_succ_apply | [1018, 1] | [1022, 44] | simp_rw [condFlipBit_apply_eq_mergeBitRes, mergeBitRes_succ, getRes_succ, getBit_succ,
getBit_mergeBitRes, getRes_mergeBitRes] | m : ℕ
c : BV (m + 1) → Bool
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ (condFlipBit i.succ c) q =
mergeBitRes 0 (getBit 0 q) ((condFlipBit i fun p => c (mergeBitRes 0 (getBit 0 q) p)) (getRes 0 q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
c : BV (m + 1) → Bool
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ (condFlipBit i.succ c) q =
mergeBitRes 0 (getBit 0 q) ((condFlipBit i fun p => c (mergeBitRes 0 (getBit 0 q) p)) (getRes 0 q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_succAbove_apply | [1024, 1] | [1030, 23] | simp_rw [condFlipBit_apply, getRes_succAbove,
Bool.apply_cond (fun x => mergeBitRes j (getBit j q) x), mergeBitRes_getBit_getRes,
flipBit_succAbove] | m : ℕ
c : BV (m + 1) → Bool
q : BV (m + 1 + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ (condFlipBit (j.succAbove i) c) q =
mergeBitRes j (getBit j q) ((condFlipBit i fun p => c (mergeBitRes (i.predAbove j) (getBit j q) p)) (getRes j q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
c : BV (m + 1) → Bool
q : BV (m + 1 + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ (condFlipBit (j.succAbove i) c) q =
mergeBitRes j (getBit j q) ((condFlipBit i fun p => c (mergeBitRes (i.predAbove j) (getBit j q) p)) (getRes j q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_zero_apply | [1032, 1] | [1036, 58] | rw [condFlipBit_apply, flipBit_zero_apply, getRes_zero] | a✝ : ℕ
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit 0 c) q = bif c q.divNat then finProdFinEquiv (q.divNat, q.modNat.rev) else q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit 0 c) q = bif c q.divNat then finProdFinEquiv (q.divNat, q.modNat.rev) else q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_zero_mergeBitRes | [1038, 1] | [1040, 54] | simp_rw [condFlipBit_mergeBitRes, mergeBitRes_zero] | a✝ : ℕ
c : BV a✝ → Bool
b : Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 b p) = finProdFinEquiv (p, bif xor (c p) b then 1 else 0) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
c : BV a✝ → Bool
b : Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 b p) = finProdFinEquiv (p, bif xor (c p) b then 1 else 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_zero_mergeBitRes_true | [1042, 1] | [1044, 71] | simp_rw [condFlipBit_zero_mergeBitRes, Bool.xor_true, Bool.cond_not] | a✝ : ℕ
c : BV a✝ → Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 true p) = finProdFinEquiv (p, bif c p then 0 else 1) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
c : BV a✝ → Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 true p) = finProdFinEquiv (p, bif c p then 0 else 1)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_zero_mergeBitRes_false | [1046, 1] | [1048, 57] | simp_rw [condFlipBit_zero_mergeBitRes, Bool.xor_false] | a✝ : ℕ
c : BV a✝ → Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 false p) = finProdFinEquiv (p, bif c p then 1 else 0) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
c : BV a✝ → Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 false p) = finProdFinEquiv (p, bif c p then 1 else 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | bitInvarMulEquiv_last_apply_condFlipBits | [1069, 1] | [1073, 100] | rw [← Fin.predAbove_right_last (i := i), bitInvarMulEquiv_apply_condFlipBits, Fin.succAbove_last] | m : ℕ
c : BV (m + 1) → Bool
i : Fin (m + 1)
⊢ ↑((bitInvarMulEquiv (Fin.last (m + 1))) fun b => condFlipBit i fun p => c (mergeBitRes (Fin.last m) b p)) =
condFlipBit i.castSucc c | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
c : BV (m + 1) → Bool
i : Fin (m + 1)
⊢ ↑((bitInvarMulEquiv (Fin.last (m + 1))) fun b => condFlipBit i fun p => c (mergeBitRes (Fin.last m) b p)) =
condFlipBit i.castSucc c
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/FoldFin.lean | coe_foldFinLE | [22, 1] | [23, 68] | simp_rw [foldFin, Nat.lt_succ_of_le h, dite_true, Fin.coe_castLT] | m : ℕ
i : Fin (2 * m + 1)
h : ↑i ≤ m
⊢ ↑(foldFin m i) = ↑i | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (2 * m + 1)
h : ↑i ≤ m
⊢ ↑(foldFin m i) = ↑i
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/FoldFin.lean | foldFinCastLE | [31, 1] | [32, 77] | rw [Fin.ext_iff, coe_foldFinLE (Nat.le_of_lt_succ i.isLt), Fin.coe_castLE] | m : ℕ
i : Fin (m + 1)
⊢ foldFin m (Fin.castLE ⋯ i) = i | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ foldFin m (Fin.castLE ⋯ i) = i
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/FoldFin.lean | foldFinCastLT | [36, 1] | [37, 75] | rw [Fin.ext_iff, coe_foldFinLT i.isLt, Fin.coe_castLT, Fin.coe_castSucc] | m : ℕ
i : Fin m
⊢ foldFin m (i.castLT ⋯) = i.castSucc | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin m
⊢ foldFin m (i.castLT ⋯) = i.castSucc
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/FoldFin.lean | foldFin_last | [41, 1] | [54, 9] | cases' m with m | m : ℕ
⊢ foldFin m (Fin.last (2 * m)) = 0 | case zero
⊢ foldFin 0 (Fin.last (2 * 0)) = 0
case succ
m : ℕ
⊢ foldFin (m + 1) (Fin.last (2 * (m + 1))) = 0 | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
⊢ foldFin m (Fin.last (2 * m)) = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/FoldFin.lean | foldFin_last | [41, 1] | [54, 9] | rfl | case zero
⊢ foldFin 0 (Fin.last (2 * 0)) = 0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case zero
⊢ foldFin 0 (Fin.last (2 * 0)) = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/FoldFin.lean | foldFin_last | [41, 1] | [54, 9] | rw [foldFin] | case succ
m : ℕ
⊢ foldFin (m + 1) (Fin.last (2 * (m + 1))) = 0 | case succ
m : ℕ
⊢ (if h : ↑(Fin.last (2 * (m + 1))) < m + 1 + 1 then (Fin.last (2 * (m + 1))).castLT h
else (Fin.subNat (m + 1) ((finCongr ⋯) (Fin.last (2 * (m + 1)))) ⋯).rev) =
0 | Please generate a tactic in lean4 to solve the state.
STATE:
case succ
m : ℕ
⊢ foldFin (m + 1) (Fin.last (2 * (m + 1))) = 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/FoldFin.lean | foldFin_last | [41, 1] | [54, 9] | rw [dif_neg] | case succ
m : ℕ
⊢ (if h : ↑(Fin.last (2 * (m + 1))) < m + 1 + 1 then (Fin.last (2 * (m + 1))).castLT h
else (Fin.subNat (m + 1) ((finCongr ⋯) (Fin.last (2 * (m + 1)))) ⋯).rev) =
0 | case succ
m : ℕ
⊢ (Fin.subNat (m + 1) ((finCongr ⋯) (Fin.last (2 * (m + 1)))) ⋯).rev = 0
case succ.hnc
m : ℕ
⊢ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1 | Please generate a tactic in lean4 to solve the state.
STATE:
case succ
m : ℕ
⊢ (if h : ↑(Fin.last (2 * (m + 1))) < m + 1 + 1 then (Fin.last (2 * (m + 1))).castLT h
else (Fin.subNat (m + 1) ((finCongr ⋯) (Fin.last (2 * (m + 1)))) ⋯).rev) =
0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/FoldFin.lean | foldFin_last | [41, 1] | [54, 9] | ext | case succ
m : ℕ
⊢ (Fin.subNat (m + 1) ((finCongr ⋯) (Fin.last (2 * (m + 1)))) ⋯).rev = 0
case succ.hnc
m : ℕ
⊢ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1 | case succ.h
m : ℕ
⊢ ↑(Fin.subNat (m + 1) ((finCongr ⋯) (Fin.last (2 * (m + 1)))) ⋯).rev = ↑0
case succ.hnc
m : ℕ
⊢ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1 | Please generate a tactic in lean4 to solve the state.
STATE:
case succ
m : ℕ
⊢ (Fin.subNat (m + 1) ((finCongr ⋯) (Fin.last (2 * (m + 1)))) ⋯).rev = 0
case succ.hnc
m : ℕ
⊢ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/FoldFin.lean | foldFin_last | [41, 1] | [54, 9] | simp | case succ.h
m : ℕ
⊢ ↑(Fin.subNat (m + 1) ((finCongr ⋯) (Fin.last (2 * (m + 1)))) ⋯).rev = ↑0
case succ.hnc
m : ℕ
⊢ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1 | case succ.h
m : ℕ
⊢ m + 1 - (m + 1 + 1 + m - (m + 1)) = 0
case succ.hnc
m : ℕ
⊢ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1 | Please generate a tactic in lean4 to solve the state.
STATE:
case succ.h
m : ℕ
⊢ ↑(Fin.subNat (m + 1) ((finCongr ⋯) (Fin.last (2 * (m + 1)))) ⋯).rev = ↑0
case succ.hnc
m : ℕ
⊢ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_apply_comm | [12, 1] | [16, 65] | simp_rw [cycleMin_eq_cycleMin_apply (x := y (x q)), ← Perm.mul_apply, ← mul_assoc,
cmtr_mul_eq_mul_inv_cmtr_inv, commutatorElement_inv, Perm.mul_apply,
cmtr_apply, inv_inv, Perm.inv_apply_self, Perm.apply_inv_self] | α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
⊢ CycleMin ⁅x, y⁆ (x (y q)) = CycleMin ⁅x, y⁆ (y (x q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
⊢ CycleMin ⁅x, y⁆ (x (y q)) = CycleMin ⁅x, y⁆ (y (x q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_disjoint_image | [18, 1] | [23, 55] | simp_rw [Finset.disjoint_iff_ne, Finset.mem_image, mem_cycleAt_iff] | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ Disjoint (CycleAt ⁅x, y⁆ q) (Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)) | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (a : α), ⁅x, y⁆.SameCycle q a → ∀ (b : α), (∃ a, ⁅x, y⁆.SameCycle q a ∧ y a = b) → a ≠ b | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ Disjoint (CycleAt ⁅x, y⁆ q) (Finset.image (⇑y) (CycleAt ⁅x, y⁆ q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_disjoint_image | [18, 1] | [23, 55] | rintro _ ⟨j, rfl⟩ _ ⟨_, ⟨⟨_, rfl⟩, rfl⟩⟩ | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (a : α), ⁅x, y⁆.SameCycle q a → ∀ (b : α), (∃ a, ⁅x, y⁆.SameCycle q a ∧ y a = b) → a ≠ b | case intro.intro.intro.intro
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
j w✝ : ℤ
⊢ (⁅x, y⁆ ^ j) q ≠ y ((⁅x, y⁆ ^ w✝) q) | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (a : α), ⁅x, y⁆.SameCycle q a → ∀ (b : α), (∃ a, ⁅x, y⁆.SameCycle q a ∧ y a = b) → a ≠ b
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_disjoint_image | [18, 1] | [23, 55] | exact cmtr_zpow_apply_ne_apply_cmtr_pow_apply hxy hy | case intro.intro.intro.intro
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
j w✝ : ℤ
⊢ (⁅x, y⁆ ^ j) q ≠ y ((⁅x, y⁆ ^ w✝) q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
j w✝ : ℤ
⊢ (⁅x, y⁆ ^ j) q ≠ y ((⁅x, y⁆ ^ w✝) q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_card_le_card_univ_div_two | [25, 1] | [31, 51] | rw [cycleAt_card_eq_orderOf_cycleOf, Nat.le_div_iff_mul_le (zero_lt_two), mul_comm, two_mul] | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ orderOf (⁅x, y⁆.cycleOf q) ≤ Finset.univ.card / 2 | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (CycleAt ⁅x, y⁆ q).card ≤ Finset.univ.card | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ orderOf (⁅x, y⁆.cycleOf q) ≤ Finset.univ.card / 2
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_card_le_card_univ_div_two | [25, 1] | [31, 51] | nth_rewrite 2 [← Finset.card_image_of_injective _ (y.injective)] | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (CycleAt ⁅x, y⁆ q).card ≤ Finset.univ.card | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (CycleAt ⁅x, y⁆ q).card ≤ Finset.univ.card
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_card_le_card_univ_div_two | [25, 1] | [31, 51] | rw [← Finset.card_union_of_disjoint (cycleAt_cmtr_disjoint_image hxy hy)] | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q ∪ Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_card_le_card_univ_div_two | [25, 1] | [31, 51] | exact Finset.card_le_card (Finset.subset_univ _) | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q ∪ Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q ∪ Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_right_apply_eq_apply_cycleMin_cmtr | [33, 1] | [48, 69] | rcases cycleMin_exists_pow_apply ⁅x, y⁆ q with ⟨j, hjq₂⟩ | α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
⊢ CycleMin ⁅x, y⁆ (y q) = y (CycleMin ⁅x, y⁆ q) | case intro
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
⊢ CycleMin ⁅x, y⁆ (y q) = y (CycleMin ⁅x, y⁆ q) | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
⊢ CycleMin ⁅x, y⁆ (y q) = y (CycleMin ⁅x, y⁆ q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_right_apply_eq_apply_cycleMin_cmtr | [33, 1] | [48, 69] | refine' eq_of_le_of_not_lt _ (fun h => _) | case intro
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
⊢ CycleMin ⁅x, y⁆ (y q) = y (CycleMin ⁅x, y⁆ q) | case intro.refine'_1
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
⊢ CycleMin ⁅x, y⁆ (y q) ≤ y (CycleMin ⁅x, y⁆ q)
case intro.refine'_2
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
h : CycleMin ⁅x, y⁆ (y q) < y (CycleMin ⁅x, y⁆ q)
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
case intro
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
⊢ CycleMin ⁅x, y⁆ (y q) = y (CycleMin ⁅x, y⁆ q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_right_apply_eq_apply_cycleMin_cmtr | [33, 1] | [48, 69] | refine' cycleMin_le ⁅x, y⁆ (y q) ⟨-j, _⟩ | case intro.refine'_1
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
⊢ CycleMin ⁅x, y⁆ (y q) ≤ y (CycleMin ⁅x, y⁆ q) | case intro.refine'_1
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
⊢ (⁅x, y⁆ ^ (-j)) (y q) = y (CycleMin ⁅x, y⁆ q) | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.refine'_1
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
⊢ CycleMin ⁅x, y⁆ (y q) ≤ y (CycleMin ⁅x, y⁆ q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_right_apply_eq_apply_cycleMin_cmtr | [33, 1] | [48, 69] | simp_rw [zpow_neg, ← Perm.mul_apply, cmtr_zpow_inv_mul_eq_mul_inv_cmtr_zpow, hxy,
Perm.mul_apply, hjq₂] | case intro.refine'_1
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
⊢ (⁅x, y⁆ ^ (-j)) (y q) = y (CycleMin ⁅x, y⁆ q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.refine'_1
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
⊢ (⁅x, y⁆ ^ (-j)) (y q) = y (CycleMin ⁅x, y⁆ q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_right_apply_eq_apply_cycleMin_cmtr | [33, 1] | [48, 69] | rcases cycleMin_exists_pow_apply ⁅x, y⁆ (y q) with ⟨k, hkq₂⟩ | case intro.refine'_2
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
h : CycleMin ⁅x, y⁆ (y q) < y (CycleMin ⁅x, y⁆ q)
⊢ False | case intro.refine'_2.intro
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
h : CycleMin ⁅x, y⁆ (y q) < y (CycleMin ⁅x, y⁆ q)
k : ℤ
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.refine'_2
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
h : CycleMin ⁅x, y⁆ (y q) < y (CycleMin ⁅x, y⁆ q)
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_right_apply_eq_apply_cycleMin_cmtr | [33, 1] | [48, 69] | rw [←hkq₂, ← hjq₂, ← Perm.mul_apply, cmtr_zpow_mul_eq_mul_inv_cmtr_zpow_inv, Perm.mul_apply,
hxy, ← zpow_neg] at h | case intro.refine'_2.intro
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
h : CycleMin ⁅x, y⁆ (y q) < y (CycleMin ⁅x, y⁆ q)
k : ℤ
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
⊢ False | case intro.refine'_2.intro
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.refine'_2.intro
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
h : CycleMin ⁅x, y⁆ (y q) < y (CycleMin ⁅x, y⁆ q)
k : ℤ
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_right_apply_eq_apply_cycleMin_cmtr | [33, 1] | [48, 69] | rcases lt_trichotomy ((⁅x, y⁆ ^ (-k)) q) ((⁅x, y⁆ ^ j) q) with H | H | H | case intro.refine'_2.intro
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
⊢ False | case intro.refine'_2.intro.inl
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
H : (⁅x, y⁆ ^ (-k)) q < (⁅x, y⁆ ^ j) q
⊢ False
case intro.refine'_2.intro.inr.inl
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
H : (⁅x, y⁆ ^ (-k)) q = (⁅x, y⁆ ^ j) q
⊢ False
case intro.refine'_2.intro.inr.inr
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
H : (⁅x, y⁆ ^ j) q < (⁅x, y⁆ ^ (-k)) q
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.refine'_2.intro
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_right_apply_eq_apply_cycleMin_cmtr | [33, 1] | [48, 69] | exact (cycleMin_le ⁅x, y⁆ q ⟨-k, rfl⟩).not_lt (hjq₂.symm ▸ H) | case intro.refine'_2.intro.inl
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
H : (⁅x, y⁆ ^ (-k)) q < (⁅x, y⁆ ^ j) q
⊢ False | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.refine'_2.intro.inl
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
H : (⁅x, y⁆ ^ (-k)) q < (⁅x, y⁆ ^ j) q
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_right_apply_eq_apply_cycleMin_cmtr | [33, 1] | [48, 69] | exact False.elim (lt_irrefl _ (H ▸ h)) | case intro.refine'_2.intro.inr.inl
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
H : (⁅x, y⁆ ^ (-k)) q = (⁅x, y⁆ ^ j) q
⊢ False | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.refine'_2.intro.inr.inl
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
H : (⁅x, y⁆ ^ (-k)) q = (⁅x, y⁆ ^ j) q
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_right_apply_eq_apply_cycleMin_cmtr | [33, 1] | [48, 69] | exact cmtr_zpow_apply_ne_apply_cmtr_pow_apply hxy hy (hy₂ H h) | case intro.refine'_2.intro.inr.inr
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
H : (⁅x, y⁆ ^ j) q < (⁅x, y⁆ ^ (-k)) q
⊢ False | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.refine'_2.intro.inr.inr
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
hy₂ : ∀ {r q : α}, r < q → y q < y r → r = y q
j : ℤ
hjq₂ : (⁅x, y⁆ ^ j) q = CycleMin ⁅x, y⁆ q
k : ℤ
h : y ((⁅x, y⁆ ^ (-k)) q) < y ((⁅x, y⁆ ^ j) q)
hkq₂ : (⁅x, y⁆ ^ k) (y q) = CycleMin ⁅x, y⁆ (y q)
H : (⁅x, y⁆ ^ j) q < (⁅x, y⁆ ^ (-k)) q
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Order.lean | Order.eq_false_true_of_cond_succ_lt_of_cond_succ_lt | [11, 1] | [22, 25] | cases bm <;> cases bn <;>
simp only [false_and, and_false, true_and, and_self, cond_true, cond_false, id_eq,
succ_le_iff, succ_lt_succ_iff, lt_succ_iff] at * | α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
bm bn : Bool
hmn : (bif bm then succ else id) m < (bif bn then succ else id) n
hnm : (bif bn then id else succ) n < (bif bm then id else succ) m
⊢ bm = false ∧ bn = true ∧ m = n | case false.false
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hmn : m < n
hnm : n < m
⊢ False
case false.true
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hmn : m ≤ n
hnm : n ≤ m
⊢ m = n
case true.false
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hmn : succ m < n
hnm : succ n < m
⊢ False
case true.true
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hnm : n < m
hmn : m < n
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
bm bn : Bool
hmn : (bif bm then succ else id) m < (bif bn then succ else id) n
hnm : (bif bn then id else succ) n < (bif bm then id else succ) m
⊢ bm = false ∧ bn = true ∧ m = n
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Order.lean | Order.eq_false_true_of_cond_succ_lt_of_cond_succ_lt | [11, 1] | [22, 25] | exact hmn.not_lt hnm | case false.false
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hmn : m < n
hnm : n < m
⊢ False | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case false.false
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hmn : m < n
hnm : n < m
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Order.lean | Order.eq_false_true_of_cond_succ_lt_of_cond_succ_lt | [11, 1] | [22, 25] | exact le_antisymm hmn hnm | case false.true
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hmn : m ≤ n
hnm : n ≤ m
⊢ m = n | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case false.true
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hmn : m ≤ n
hnm : n ≤ m
⊢ m = n
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Order.lean | Order.eq_false_true_of_cond_succ_lt_of_cond_succ_lt | [11, 1] | [22, 25] | exact lt_irrefl _ (((hnm.trans (lt_succ _)).trans hmn).trans (lt_succ _)) | case true.false
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hmn : succ m < n
hnm : succ n < m
⊢ False | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case true.false
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hmn : succ m < n
hnm : succ n < m
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Order.lean | Order.eq_false_true_of_cond_succ_lt_of_cond_succ_lt | [11, 1] | [22, 25] | exact hmn.not_lt hnm | case true.true
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hnm : n < m
hmn : m < n
⊢ False | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case true.true
α : Type u_1
inst✝² : PartialOrder α
inst✝¹ : SuccOrder α
inst✝ : NoMaxOrder α
m n : α
hnm : n < m
hmn : m < n
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isLeft_eq_of_liftRel_inl_right | [8, 1] | [10, 17] | cases h | α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
ab : α✝ ⊕ β✝
c : γ✝
h : LiftRel ra rb ab (inl c)
⊢ ab.isLeft = true | case inl
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
c : γ✝
a✝¹ : α✝
a✝ : ra a✝¹ c
⊢ (inl a✝¹).isLeft = true | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
ab : α✝ ⊕ β✝
c : γ✝
h : LiftRel ra rb ab (inl c)
⊢ ab.isLeft = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isLeft_eq_of_liftRel_inl_right | [8, 1] | [10, 17] | simp | case inl
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
c : γ✝
a✝¹ : α✝
a✝ : ra a✝¹ c
⊢ (inl a✝¹).isLeft = true | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
c : γ✝
a✝¹ : α✝
a✝ : ra a✝¹ c
⊢ (inl a✝¹).isLeft = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isLeft_eq_of_liftRel_inl_left | [12, 1] | [14, 17] | cases h | α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
a : α✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb (inl a) cd
⊢ cd.isLeft = true | case inl
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
a : α✝¹
c✝ : α✝
a✝ : ra a c✝
⊢ (inl c✝).isLeft = true | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
a : α✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb (inl a) cd
⊢ cd.isLeft = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isLeft_eq_of_liftRel_inl_left | [12, 1] | [14, 17] | simp | case inl
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
a : α✝¹
c✝ : α✝
a✝ : ra a c✝
⊢ (inl c✝).isLeft = true | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
a : α✝¹
c✝ : α✝
a✝ : ra a c✝
⊢ (inl c✝).isLeft = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isLeft_eq_of_liftRel | [16, 1] | [17, 19] | cases h <;> simp | α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
ab : α✝¹ ⊕ β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb ab cd
⊢ ab.isLeft = cd.isLeft | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
ab : α✝¹ ⊕ β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb ab cd
⊢ ab.isLeft = cd.isLeft
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isRight_eq_of_liftRel | [19, 1] | [20, 19] | cases h <;> simp | α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
ab : α✝¹ ⊕ β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb ab cd
⊢ ab.isRight = cd.isRight | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
ab : α✝¹ ⊕ β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb ab cd
⊢ ab.isRight = cd.isRight
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isRight_eq_of_liftRel_inr_left | [22, 1] | [24, 17] | cases h | α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
b : β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb (inr b) cd
⊢ cd.isRight = true | case inr
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
b : β✝¹
d✝ : β✝
a✝ : rb b d✝
⊢ (inr d✝).isRight = true | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
b : β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb (inr b) cd
⊢ cd.isRight = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isRight_eq_of_liftRel_inr_left | [22, 1] | [24, 17] | simp | case inr
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
b : β✝¹
d✝ : β✝
a✝ : rb b d✝
⊢ (inr d✝).isRight = true | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
b : β✝¹
d✝ : β✝
a✝ : rb b d✝
⊢ (inr d✝).isRight = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isRight_eq_of_liftRel_inr_right | [26, 1] | [28, 17] | cases h | α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
ab : α✝ ⊕ β✝
d : δ✝
h : LiftRel ra rb ab (inr d)
⊢ ab.isRight = true | case inr
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
d : δ✝
b✝ : β✝
a✝ : rb b✝ d
⊢ (inr b✝).isRight = true | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
ab : α✝ ⊕ β✝
d : δ✝
h : LiftRel ra rb ab (inr d)
⊢ ab.isRight = true
TACTIC:
|
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