content stringlengths 1 1.04M ⌀ |
|---|
--
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
end entity ent;
architecture a of ent is
signal clk : std_logic := '0';
signal check_stable_in_1 : std_logic_vector(1 to 5) := "00000";
alias check_stable_start_event_1 : std_logic is check_stable_in_1(1);
alias check_stable_end_event_1 : std_logic... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:50:54 11/19/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282_19.11.2013/My_SignExtend_tb_948282.vhd
-- Project Name: Mips32_948282_19.11.2013
-- Target Device:
-... |
PACKAGE test_pkg IS
TYPE string_array_t IS ARRAY (natural RANGE <>) OF string;
END test_pkg;
ENTITY test IS
END ENTITY test;
LIBRARY work;
USE work.test_pkg.string_array_t;
ARCHITECTURE rtl OF test IS
BEGIN
END ARCHITECTURE rtl;
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- ... |
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- ... |
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- ... |
---------------------------------------------------
-- Alan Daly 2009(c)
-- AtomIC project
-- minimal implementation of an 8255
-- just enough for the machine to function
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- multiple1902 <multple1902@gmail.com>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use std.textio.all;
entity bfp is
port (ins_in : in std_logic_vector(2 downto 0);
data_in : ... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
PORT (
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:58:26 05/17/2011
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/Projects/Personal/Senior Project/FPGA Stuff/OZ3_Mandelbrot/OZ3_Sys_Top_TB.vhd
-- Project Name: OZ3... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------
-- INFORMATION: http://www.GNSS-sensor.com
-- PROPERTY: GNSS Sensor Ltd
-- E-MAIL: sergey.khabarov@gnss-sensor.com
-- DESCRIPTION: This file contains copy of the firmware image
--------------------------------------------------... |
----------------------------------------------------------------------------
-- INFORMATION: http://www.GNSS-sensor.com
-- PROPERTY: GNSS Sensor Ltd
-- E-MAIL: sergey.khabarov@gnss-sensor.com
-- DESCRIPTION: This file contains copy of the firmware image
--------------------------------------------------... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- ... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
--!
--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06:28:55 11/20/2014
-- Design Name:
-- Module Name: calc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cronometro is
port (
clock_50: in std_logic;
dificuldade: in std_logic_vector(1 downto 0);
reset: in std_logic;
restante: out std_logic_vector(7 downto 0);
atual: out std_logic_vector(7 downto 0)
);
end cronometro;
archit... |
library ieee;
use ieee.std_logic_1164.all;
--XOR is an easy task and can take place everywhere easily. But since in DES it is a separate step, it is implemented separetely.
entity xor_48_bits is
port( data_in: in std_logic_vector(0 to 47);
key: in std_logic_vector(0 to 47);
data_out: out std_logic_vector(0 to 47)... |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a cha... |
------------------------------------------------------------------------------
-- @license MIT
-- @brief
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.global.all;
use work.reg;
entity tex... |
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
USE IEEE.std_logic_signed.all; --math operations for signed std_logic
ENTITY tb_counter_up_down_4bit IS END tb_count... |
-- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
------------------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in st... |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_algorithm_wrapper - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
--------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:47 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : UART-Model for Simulation
-- Last update : 28.11.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_1.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ---------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:32 02/12/2014
-- Design Name:
-- Module Name: full_adder_1_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
library ieee;
use ieee.std_logic_1164.all;
entity key_permutation_2 is
port( left_half: in std_logic_vector(0 to 27);
right_half: in std_logic_vector(0 to 27);
permuted_key: out std_logic_vector(0 to 47));
end key_permutation_2;
architecture behavior of key_permutation_2 is
signal merged_halfs: std_logic_vector... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v8_0 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietar... |
entity test is
end test;
architecture arch of test is
type natural_vec is array (natural range <>) of natural;
type natural_vec_ptr is access natural_vec;
procedure bad is
variable v : natural_vec_ptr;
begin
v := new natural_vec_ptr(0 to 9); -- Should give an error, gives assertion failed
v := new ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:10:06 12/28/2015
-- Design Name:
-- Module Name: livelli2impulsi - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependen... |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Perform majority voting on read.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 08-02-2016
-- Module Name: majority.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1165... |
library ieee;
use ieee.std_logic_1164.all;
entity driver is
generic (val : string);
port (o : out std_logic);
end driver;
architecture behav of driver is
begin
drv1: if val = "one" generate
o <= '1';
end generate;
drv0: if val = "zero" generate
o <= '0';
end generate;
end behav;
library ieee;
us... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
-- A testbench has no ports.
entity Adder_tb is
end Adder_tb;
architecture test of Adder_tb is
-- Declaration of the component that will be instantiated.
component adder
port (src1 : in addr_t; src2 : in ad... |
-- NEED RESULT: ARCH00287: 'Abs' does not require parentheses around argument passed
-- NEED RESULT: ARCH00287: 'Not' does not require parentheses around argument passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Dec2_4En is
port( enable : in std_logic;
inputs : in std_logic_vector(1 downto 0);
outputs : out std_logic_vector(3 downto 0));
end Dec2_4En;
architecture RTL of Dec2_4En is
begin
process(enable, inputs)
begin
if (enable = '0') then
outputs <= "0000";
... |
package pack1 is
procedure read ( x : out integer );
end package;
-------------------------------------------------------------------------------
use work.pack1.all;
package pack2 is
alias read is work.pack1.read [integer];
end package;
-----------------------------------------------------------------------... |
-- Altera Microperipheral Reference Design Version 0802
--------------------------------------------------------
--
-- FILE NAME : portaout.vhd
-- PROJECT : Altera A8255 Peripheral Interface Adapter
-- PURPOSE : This file contains the entity and architecture
-- for the Port A Output... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_execute_block is
-- define attributes
attribute ENUM_ENCODING : STRING;
-- define any necessary types
type aluOp is (NOP, SLLS, SRLS, SRAS, ADDS, ADDUS, SUBS, SUBUS, ANDS, ORS,
XORS, SEQS, SNES, SLTS, SGTS, SLES, SGES, MOVI2SS, MOVS2IS, MOVFS, MOVDS,... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 00:52:18 04/10/2009
-- Design Name:
-- Module Name: Gate_Xor - Behavioral
-- Project Name: XOR Gate
-- Target Devices:
-- Tool versions:
-- Description: An X... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: BusPLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ================================... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY pong IS
PORT(
clock : IN STD_LOGIC;
-- Puertos VGA
vga_red : OUT STD_LOGIC;
vga_green : OUT STD_LOGIC;
vga_blue : O... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
--
-- (C) Alvaro Lopes <alvieboy@alvie.com> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block8.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ------------------------------------... |
--============================================================================
--!
--! \file <FILE_NAME>
--!
--! \project <PROJECT_NAME>
--!
--! \langv VHDL-1993
--!
--! \brief <BRIEF_DESCRIPTION>.
--!
--! \details <DETAILED_DESCRIPTION>.
--!
--! \bug <BUGS_OR_KNOWN_ISSUES>.
--!
--! \see <R... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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