content stringlengths 1 1.04M ⌀ |
|---|
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: freqDividerV3.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:50:46 2017
-- Host : Juice-Laptop running 64-bit major re... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:50:46 2017
-- Host : Juice-Laptop running 64-bit major re... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_139 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_139;
architecture augh of cmp_139 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_139 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_139;
architecture augh of cmp_139 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y... |
entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y... |
entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y... |
entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y... |
entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_a_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.std_logic_1164.all;
library Examples;
use Examples.examples.all;
entity Top is
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Top;
architecture Structural of Top is
constant FREQ : positive := 50e6;
begin
dut: Blinking
generic map (FREQ => FREQ,... |
library IEEE;
use IEEE.std_logic_1164.all;
library Examples;
use Examples.examples.all;
entity Top is
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Top;
architecture Structural of Top is
constant FREQ : positive := 50e6;
begin
dut: Blinking
generic map (FREQ => FREQ,... |
library IEEE;
use IEEE.std_logic_1164.all;
library Examples;
use Examples.examples.all;
entity Top is
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Top;
architecture Structural of Top is
constant FREQ : positive := 50e6;
begin
dut: Blinking
generic map (FREQ => FREQ,... |
library IEEE;
use IEEE.std_logic_1164.all;
library Examples;
use Examples.examples.all;
entity Top is
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Top;
architecture Structural of Top is
constant FREQ : positive := 50e6;
begin
dut: Blinking
generic map (FREQ => FREQ,... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity dmod is
generic(
width:integer := 16
);
port(
clk: in std_logic;
I: in std_logic_vector(width-1 downto 0);
Q: in std_logic_vector(width-1 downto 0);
outpu... |
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Ta... |
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Ta... |
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Ta... |
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Ta... |
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Ta... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity bounds21 is
end entity;
architecture test of bounds21 is
type boolean_v is array (integer range <>) of boolean;
subtype boolean_4 is boolean_v (1 to 4);
subtype boolean_7 is boolean_v (1 to 7);
function return_array return boolean_4 is
constant l_operand : boolean_4 := (true,false,true,false);
... |
architecture RTL of FIFO is
begin
process
begin
LOOP_LABEL : loop
end loop;
-- Violations below
LOOP_LABEL : loop
end loop;
end process;
end;
|
------------------------------------------------------------------------------
-- matrixmultiplier - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: matrixmultiplier
-- Version: 2.00.a
-- Description: matrix multiplier(VHDL).
-- Date: Wed June 7... |
------------------------------------------------------------------------------
-- matrixmultiplier - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: matrixmultiplier
-- Version: 2.00.a
-- Description: matrix multiplier(VHDL).
-- Date: Wed June 7... |
library IEEE;
use ieee.std_logic_1164.all;
entity memory_data_register is
port(
input : in std_logic_vector(31 downto 0);
clk, rst, pre, ce : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end memory_data_register;
architecture behav of memory_data_register is
begin
Mem : entity work.thirty_tw... |
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-- A6500 - 6502 CPU and variants
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or ... |
entity tb_dpram2w is
end tb_dpram2w;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dpram2w is
signal waddr : natural range 0 to 3;
signal wnib : natural range 0 to 1;
signal wdat : std_logic_vector (3 downto 0);
signal raddr : natural range 0 to 3;
signal rdat : std_logic_vector(7 down... |
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_op... |
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_op... |
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_op... |
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_op... |
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_op... |
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_op... |
library verilog;
use verilog.vl_types.all;
entity BFM_AHBL is
generic(
VECTFILE : string := "test.vec";
MAX_INSTRUCTIONS: integer := 16384;
MAX_STACK : integer := 1024;
MAX_MEMTEST : integer := 65536;
TPD : integer := 1;
DEBUGLEVEL :... |
library verilog;
use verilog.vl_types.all;
entity BFM_AHBL is
generic(
VECTFILE : string := "test.vec";
MAX_INSTRUCTIONS: integer := 16384;
MAX_STACK : integer := 1024;
MAX_MEMTEST : integer := 65536;
TPD : integer := 1;
DEBUGLEVEL :... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
----------------------------------------------------------
-- ECE403 Lab3 Sorter Toplevel - 4 4-bit unsigned sorter
-- Jiawei Wu
-- Satyen Akolkar
-- Top level: sorter_top.vhd
-- Maps the multiplier core to the input and output pads
----------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_L... |
-- file: clk_182.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--
-- A simulation model of VIC20 hardware
-- Copyright (c) MikeJ - March 2003
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain ... |
--
-- TemporalMixer.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyri... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity time_keeper is
Port ( memRead : in STD_LOGIC_VECTOR (7 downto 0);
memWrite : out STD_LOGIC_VECTOR (7 downto 0);
memAddress : out STD_LOGIC_VECTOR (11 downto 0);
mem_valid : out STD_LOGIC;
... |
-- multiple1902 <multple1902@gmail.com>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
entity memory_tb is
end memory_tb;
architecture behav of memory_tb is
component memory
port (
cs : in std_logic; -- Chip select
re, we : in std_logic; -- R... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: System Monitor wrapper f... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: System Monitor wrapper f... |
-- $Id: ib_sres_or_3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_3 - syn
-- Description: ibus: ... |
entity grlib1 is
end entity;
architecture test of grlib1 is
constant NAHBMST : integer := 16; -- maximum AHB masters
constant NAHBSLV : integer := 16; -- maximum AHB slaves
constant NAPBSLV : integer := 16; -- maximum APB slaves
constant NAHBAMR : integer := 4; -- maximum address mapping reg... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modi... |
Library IEEE;
use IEEE.std_logic_1164.all;
entity DC7 is
port( A: in std_logic_vector (3 downto 0);
Q: out std_logic_vector (6 downto 0));
end entity DC7;
architecture Behave of DC7 is
begin
process (A)
begin
case A is
when "0000" => Q <= "0000001";
when "0001" => Q <= "1001111";
... |
--
-- Package File Template
--
-- Purpose: This package defines data types for AXI transfers
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package axi is
type axi_in_type is record
data_in : STD_LOGIC_VECTOR (7 downto 0);
data_in_valid : STD_LOGIC; -- indicates data_in valid on clock
data_in_last ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity global_memory is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
--compute group 0
ADDRESS_A_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG0 : IN STD_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity global_memory is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
--compute group 0
ADDRESS_A_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG0 : IN STD_... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: test bench for the FPU core
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity graphics is
Port ( CLK50 : in STD_LOGIC;
CLK12 : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC;
A : in STD_L... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Tue Mar 30 18:39:52 2004
-- cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
-- Module Name: colour_space_conversion - Behavioral
--
-- Description: Convert the input pixel data into YCbCr 422 values
--
-- Feel free to use this how you see fit, and fix any error... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- name can be any name chosen for this architecture
-- entity is the name of the entity previously defined
ARCHITECTURE name OF entity IS
-- Signal, component, type and constant declarations go here
...
BEGIN
-- Concurrent statements and processes go here
...
END name;
|
library verilog;
use verilog.vl_types.all;
entity Transmit is
port(
Transmit_CLK : in vl_logic;
Line_Num : in vl_logic_vector(7 downto 0);
Focus_Num : in vl_logic_vector(1 downto 0);
Pr_Gate : in vl_logic;
RX_Gate : in vl_lo... |
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