content stringlengths 1 1.04M ⌀ |
|---|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY busTriState IS
PORT(
clk : in std_logic;
rst : in std_logic;
rw : in std_logic;
d : in std_logic_vector(15 downto 0);
q : out std_logic_vector(15 downto 0);
dq : inout ... |
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and ... |
entity tb_issue is
end tb_issue;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_issue is
signal a : boolean;
begin
dut: entity work.issue
port map (a);
process
begin
wait for 1 ns;
assert a severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_64 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_64;
architecture BEHAVIO... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Implementation of the grethaxi device.
--! @details This is Ethernet MAC device with the A... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Implementation of the grethaxi device.
--! @details This is Ethernet MAC device with the A... |
entity repro2 is
end entity;
architecture tb of repro2 is
type tb_cfg_t is record
value : string;
end record tb_cfg_t;
function get_msg return string is
begin
return "goodbye";
end get_msg;
constant tb_cfg: tb_cfg_t := ( value => get_msg );
begin
assert tb_cfg.value > "a";
end tb;
|
-------------------------------------------------------------------------------
-- axi_vdma_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights res... |
-------------------------------------------------------------------------------
-- axi_vdma_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights res... |
-------------------------------------------------------------------------------
-- axi_vdma_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights res... |
-------------------------------------------------------------------------------
-- axi_vdma_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights res... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY freqDividerTb IS
END freqDividerTb;
ARCHITECTURE behavior OF freqDividerTb IS
COMPONENT freqDivider
Generic (
divisor : integer
);
PORT(
clk : IN std_logic;
rst : IN std_logic;... |
-- Descp. decodes the 3 bit color to the 4 bit needed for the segment_decoder
--
-- entity name: g05_color_decoder
--
-- Version 1.0
-- Author: Felix Dube; felix.dube@mail.mcgill.ca & Auguste Lalande; auguste.lalande@mail.mcgill.ca
-- Date: October 29, 2015
library ieee;
use ieee.std_logic_1164.all;
entity... |
--Package declaration for the above program
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package test_pkg is
function reverse_any_vector (a : in std_logic_vector) return std_logic_vector;
end test_pkg; --end of package.
package body test_pkg is --start of package body
--d... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
-- xemac.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- xemac.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- xemac.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- xemac.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end PACKAGE body fifo_pkg;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ios_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:55:26 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: io... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.al... |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later ver... |
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture ARCH00001_Test_Bench of ENT00001_Test_Bench is
type t_int1 is range 0 to 100 ;
subtype st_int1 is t_int1 range 8 to 60 ;
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr2_range1 is integer range 1 to 10 ;
s... |
--------------------------------------------------------------------------------
-- Entity: usb_tracer
-- Date:2018-07-15
-- Author: Gideon
--
-- Description: Encodes USB data into 1480A compatible data format
--------------------------------------------------------------------------------
library ieee;
use ieee... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_1_block4.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_b is
port (
q : in std_logic_vector(31 downto 0);
A : in std_logic_vector(31 downto 0);
k : in std_logic_vector(31 downto 0);
T : in std_logic_vector(31 downto 0);
clock : in ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.fixed_pkg.all;
entity phz_calc is
end entity phz_calc;
architecture behavioral of phz_calc is
function to_string (inp: sfixed) return string is
variable image_str: string (1 to inp'length + 1);
variable j: integer range 1 to image_str'length + 1... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-... |
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual prope... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 00:57:43 10/03/2009
-- Design Name:
-- Module Name: TestCPU1_RegFile - Behavioral
-- Project Name: Test CPU 1
-- Target Devices:
-- Tool versions:
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_rx is
end entity;
architecture tb of tb_ulpi_rx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_last ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_rx is
end entity;
architecture tb of tb_ulpi_rx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_last ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
--===========================================================================--
-- --
-- ps2_keyboard.vhd - Synthesizable PS/2 Keyboard Interface --
-- --
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_0_crossbar_wrap_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_0_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_0_crossbar_wrap_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_0_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
-- This should not fail... |
library vunit_lib;
context vunit_lib.vunit_context;
entity tb_minimal is
generic (runner_cfg : string);
end entity;
architecture tb of tb_minimal is
begin
main : process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("testcase_1") then
repor... |
library vunit_lib;
context vunit_lib.vunit_context;
entity tb_minimal is
generic (runner_cfg : string);
end entity;
architecture tb of tb_minimal is
begin
main : process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("testcase_1") then
repor... |
-- Automatically generated: write_netlist -wrapapp -vhdl -module reconflogic-wrapmax6682mean.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MyReconfigLogic is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : ou... |
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of t... |
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of t... |
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of t... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
---------------------------------... |
----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
---------------------------------... |
----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
---------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
entity logical2 is
end entity;
architecture test of logical2 is
signal x : bit;
signal one : bit := '1';
signal zero : bit := '0';
signal vec : bit_vector(0 to 1) := ('0', '1');
begin
process is
variable v : boolean := true;
begin
x <= '0';
wait for 1 ns;
a... |
architecture RTL of ENT is
BEGIN
end RTL;
architecture RTL of ENT is
BEGIN
end rtl;
architecture RTL of ENT is
BEGIN
end Rtl;
architecture RTL of ENT is
BEGIN
end;
architecture RTL of ENT is
BEGIN
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity issue3 is
end issue3;
architecture beh of issue3 is
type t_rec is
record
elem : std_logic_vector (3 downto 0);
end record;
begin
assert t_rec'(elem => 4b"0") = t_rec'(elem => 3b"0");
end architecture beh;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:13:41 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_16.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -----------------------------------------------... |
package order1 is
type t is (A, B, C);
type t_vec is array (natural range <>) of t;
end package;
package order1 is
type t is (C, B, A); -- Redefine t
type t_vec is array (1 to 2) of t;
constant x : boolean := t_vec'(A, A) < t_vec'(C, C); -- Should not fold!
end package;
|
------------------------------------------------------------------------------
-- Title : Top FMC250M design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
----... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
----------------------------------------------------------------------------------
-- Engineer: Cesar Avalos B
-- Create Date: 01/28/2018 07:53:02 PM
-- Module Name: MMU_stub - Behavioral
-- Description: Full flegded MMU to feed instructions and store data, supports SV39
--
-- Additional Comments: Mk. VIII
--
--------... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity inctwo is
port (DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end inctwo;
architecture Logic of inctwo is
begin
ADD_COMP : add16 port map(DIN,"0000000000000010",DOUT);
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity inctwo is
port (DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end inctwo;
architecture Logic of inctwo is
begin
ADD_COMP : add16 port map(DIN,"0000000000000010",DOUT);
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity inctwo is
port (DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end inctwo;
architecture Logic of inctwo is
begin
ADD_COMP : add16 port map(DIN,"0000000000000010",DOUT);
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity inctwo is
port (DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end inctwo;
architecture Logic of inctwo is
begin
ADD_COMP : add16 port map(DIN,"0000000000000010",DOUT);
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : out std_logic;
clock : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return boolean;
begin
process(A) is
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : out std_logic;
clock : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return boolean;
begin
process(A) is
... |
-- $Id: tst_fx2loop.vhd 510 2013-04-26 16:14:57Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.defs.all;
-- We run off a 50mhz clock, transferring 1 byte every 4 cycles. This gives
-- up to 12.5MB/s transfer rate, to achieve the maximum rate we need to use
-- 'turbo' mode that ignores the FT2232H async strobes.
-- xmit... |
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