content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Author: David Wolf, Leonhardt Schwarz
-- Project: FPGA Project
--
-- Copyright (C) 2014 David Wolf, Leonhardt Schwarz
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.... |
-------------------------------------------------------------------------------
-- axi_vdma_reset
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights r... |
-------------------------------------------------------------------------------
-- axi_vdma_reset
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights r... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Cadre : GEN1333 - Conception des circuits integrés --
-- : Projet de conception individuel 1 --
... |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_footer
---- Version: 1.0.0
---- Description:
---- TBD
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
---------------------... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- This system does nothing useful
-- It takes input X and this is registered internally
-- It computes x+1 and x+const independently
-- The output is computed as (x+const)-(x+1)=const-1
-- so the higher level modifies C and then C-1 is returned
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;... |
-- This system does nothing useful
-- It takes input X and this is registered internally
-- It computes x+1 and x+const independently
-- The output is computed as (x+const)-(x+1)=const-1
-- so the higher level modifies C and then C-1 is returned
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;... |
-- This system does nothing useful
-- It takes input X and this is registered internally
-- It computes x+1 and x+const independently
-- The output is computed as (x+const)-(x+1)=const-1
-- so the higher level modifies C and then C-1 is returned
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;... |
-- This system does nothing useful
-- It takes input X and this is registered internally
-- It computes x+1 and x+const independently
-- The output is computed as (x+const)-(x+1)=const-1
-- so the higher level modifies C and then C-1 is returned
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;... |
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of X... |
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of X... |
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of X... |
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of X... |
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of X... |
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of X... |
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of X... |
library ieee;
use ieee.std_logic_1164.all;
use work.rec05_pkg.all;
entity rec05 is
port (inp : std_logic;
o : out myrec);
end rec05;
architecture behav of rec05 is
begin
o.b <= not inp;
o.a <= "0101" when inp = '0' else "1010";
end behav;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY counter_tb IS
END counter_tb;
ARCHITECTURE behavior OF counter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT counter
PORT(
CLK : IN std_logic;
OUTPUT : OUT std_logic_vector(7 downto 0)
);
... |
entity foo is end;
architecture bar of foo is
signal S: STANDARD.BIT_VECTOR (1 to 10);
signal CLK1, CLK2: TIME;
signal CLK3: TIME register;
signal CLK4: TIME bus;
signal X: INTEGER := 42;
signal OUTPUT: WIRED_OR MULTI_VALUED_LOGIC;
begin end;
|
-------------------------------------------------------------------------------------------------
-- Company: CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version: V1
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
entity Arbiter_out_one_hot_pseudo is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_log... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
entity Arbiter_out_one_hot_pseudo is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_log... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
entity Arbiter_out_one_hot_pseudo is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_log... |
-------------------------------------------------------------------------------
-- system_microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_50_c;
use micr... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity nbit_encoder is
generic(
numInputs: integer:=4
);
port(
enable: in std_logic;
inputVector: in std_logic_vector(numInputs -1 downto 0);
outputVector: out std_logic_vector(integer(log2(Real(numInputs))) -1 down... |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_model.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File... |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_model.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File... |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_model.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File... |
---------------------------------------------------------------------------------------------------
--
-- Title : Shift Reg
-- Design : Common Module
-- Author : Zhao Ming
-- Company : a4a881d4
--
------------------------------------------------------------------------------------------------... |
---------------------------------------------------------------------------------------------------
--
-- Title : Shift Reg
-- Design : Common Module
-- Author : Zhao Ming
-- Company : a4a881d4
--
------------------------------------------------------------------------------------------------... |
library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of truth_table is
begin
O<= (not D and C) or (D and not C) or A or B ;
end behavior;
|
library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of truth_table is
begin
O<= (not D and C) or (D and not C) or A or B ;
end behavior;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of pads_westsouth
--
-- Generated
-- by: wig
-- on: Mon Mar 5 15:01:50 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../padio2.xls
--
-- !!! Do not edit this fi... |
--
-- File Name: OsvvmGlobalPkg.vhd
-- Design Unit Name: OsvvmGlobalPkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Global Settings ... |
--
-- File Name: OsvvmGlobalPkg.vhd
-- Design Unit Name: OsvvmGlobalPkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Global Settings ... |
--
-- File Name: OsvvmGlobalPkg.vhd
-- Design Unit Name: OsvvmGlobalPkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Global Settings ... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
termina... |
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for I2C WB Arbiter
---------------------------------------------------------------------------------------
-- File : i2c_arb_wb.vhd
-- Author : auto-generated by wbgen2 from ... |
-------------------------------------------------------------------------------
--! @file nf_pkg.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-11
--! @brief NanoFIP package.
--------------------------------------------------------------------... |
-- megafunction wizard: %ALTFP_EXP%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTFP_EXP
-- ============================================================
-- File Name: fp_exp.vhd
-- Megafunction Name(s):
-- ALTFP_EXP
--
-- Simulation Library Files(s):
--
-- ============================================... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
library ieee;
library ieee, lib2, lib3;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
clk : in std_logic;
enable : in std_logic;
i : in std_logic;
o : out std_logic
);
end;
architecture a of ent is
begin
process(clk)
begin
-- works:
--if rising_edge(clk) and enable = '1' then... |
architecture RTL of FIFO is
attribute max_delay : time;
-- Violations below
attribute max_delay : time;
attribute max_delay : time;
begin
end architecture RTL;
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is... |
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is... |
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is... |
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This ... |
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This ... |
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This ... |
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This ... |
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This ... |
------------------------------------------------------------------------------
-- Controller of context select register
--
-- Project :
-- File : $URL: svn+ssh://plessl@yosemite.ethz.ch/home/plessl/SVN/simzippy/trunk/vhdl/contextselctrl.vhd $
-- Authos : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- ... |
library verilog;
use verilog.vl_types.all;
entity Controller is
port(
Rb : in vl_logic;
Reset : in vl_logic;
Eq : in vl_logic;
D7 : in vl_logic;
D711 : in vl_logic;
D2312 : in ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
quada: in STD_LOGIC;
quadb: in STD_LOGIC;
index: in STD_LOGIC;
ccrloadcmd: in STD... |
--------------------------------------------------------------------------------
-- Title : Data Unit of VME-Bridge
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_du.vhd
-- Author : michael.miehling@men.de
-- Organizati... |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software th... |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software th... |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software th... |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software th... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:29:38 11/03/2016
-- Design Name:
-- Module Name: /home/student1/Documents/Omega/CPU/Hardware/Omega/MemoryController_TB.vhd
-- Project Name: Omega
-- Target Device:
-- Tool versions:... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
-- Title : tx_ctrl
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_ctrl.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.d... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
package Display_Management_pkg is --============================================================================
constant nbits_pixel : natural := 12;
type format_type is record
------------------------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--
-- True Dual-Port RAM
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.MEMS.all;
entity TrueDualPortRAM is
generic (
AWIDTH :... |
library accum;
use accum.OneHotAccum.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mrom_tb is
end mrom_tb;
architecture TB_ARCHITECTURE of mrom_tb is
-- Component declaration of the tested unit
component m... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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