content stringlengths 1 1.04M ⌀ |
|---|
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redist... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_962 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_962;
architecture augh of cmp_962 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_962 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_962;
architecture augh of cmp_962 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
architecture rtl of fifo is
signal sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0)
,
elementB(3 downto 0)),
element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),
element5(
elementE
(3 downto
0)
... |
entity issue101 is
end entity;
architecture SIGN of issue101 is
signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process (signal1, signal2, signal3)
begin
-- wait on TRIGGER;
signal1 <= signal2;
... |
----------------------------------------------------------------------
-- brdLexSwx (for SCS Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
l... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen
--
-- Create Date: 11:24:03 09/18/2017
-- Design Name:
-- Module Name: Mux4x1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is a generic 4x1 10 bit mux with... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
----------------------------------------------------------------------------------
-- Nicolas Primeau
--
-- Create Date: 13:24:12 03/15/2014
-- Design Name: Asynchronous Generic Memory
-- Module Name: Mem_Async - Behavioral
-- Description:
--
-- Asynchronous generic memory. CAREFUL, Do not write un... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNURIZNNI4 is
generic ( use_else_output : natural := 0;
bwr : natural :... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNURIZNNI4 is
generic ( use_else_output : natural := 0;
bwr : natural :... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNURIZNNI4 is
generic ( use_else_output : natural := 0;
bwr : natural :... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNURIZNNI4 is
generic ( use_else_output : natural := 0;
bwr : natural :... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inverse_quant is
generic(
in_sample_width : integer := 8;
out_sample_width : integer := 16;
qp_width : integer := 8;
wo_dc_width : integer := 8
);
port(
qua... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inverse_quant is
generic(
in_sample_width : integer := 8;
out_sample_width : integer := 16;
qp_width : integer := 8;
wo_dc_width : integer := 8
);
port(
qua... |
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:15:21 08/06/2014
-- Design Name:
-- Module Name: C:/Xilinx/14.7/workspace/prac1_beta/test_and2gate.vhd
-- Project Name: prac1_beta
-- Target Device:
-- Tool versions:
--... |
library verilog;
use verilog.vl_types.all;
entity lab50 is
port(
reset : in vl_logic;
rb : in vl_logic;
clk_50m : in vl_logic;
clk_28m : in vl_logic;
win : out vl_logic;
lose : out vl_... |
library verilog;
use verilog.vl_types.all;
entity lab50 is
port(
reset : in vl_logic;
rb : in vl_logic;
clk_50m : in vl_logic;
clk_28m : in vl_logic;
win : out vl_logic;
lose : out vl_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div00 is
port(
clkdiv: in std_logic ;
indiv: in std_logic_vector ( 3 downto 0 );
outdiv: inout std_logic );
end;
architecture div0 of div00 is
signal sdiv: std_logic_vector(11 downto ... |
----------------------------------------------------------------------
-- FsmPatGen
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Blink some LEDs to show results of initialisation attempts.
--
-- Result :
-- -assignments at declaration time will not work
-- -... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package phasedet_comp is
component phasedet
Port ( ref : in STD_LOGIC;
vco : in STD_LOGIC;
mclk : in STD_LOGIC;
rst : in std_logic;
phase : out signed (15 downto 0));
end component;
end package;... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
----------------------------------------------------------------------------------------------
--
-- Input file : mem.vhd
-- Design name : mem
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, De... |
----------------------------------------------------------------------------------------------
--
-- Input file : mem.vhd
-- Design name : mem
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, De... |
----------------------------------------------------------------------------------------------
--
-- Input file : mem.vhd
-- Design name : mem
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, De... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _ ... |
entity arith2 is
end entity;
architecture test of arith2 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 0;
wait for 1 ns;
x := x / y;
wait;
end process;
end architecture;
|
entity arith2 is
end entity;
architecture test of arith2 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 0;
wait for 1 ns;
x := x / y;
wait;
end process;
end architecture;
|
entity arith2 is
end entity;
architecture test of arith2 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 0;
wait for 1 ns;
x := x / y;
wait;
end process;
end architecture;
|
entity arith2 is
end entity;
architecture test of arith2 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 0;
wait for 1 ns;
x := x / y;
wait;
end process;
end architecture;
|
entity arith2 is
end entity;
architecture test of arith2 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 0;
wait for 1 ns;
x := x / y;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dfir_types.all;
package dfir_coeff_lib is
constant dfir_order : natural := 129;
type integer_vector is array(dfir_order downto 0) of integer;
constant dfir_coeff_content : integer_vector := (
30251, 25860, 4784, -21256, -36393, -2... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dfir_types.all;
package dfir_coeff_lib is
constant dfir_order : natural := 129;
type integer_vector is array(dfir_order downto 0) of integer;
constant dfir_coeff_content : integer_vector := (
30251, 25860, 4784, -21256, -36393, -2... |
-- PCIEXP interface
constant CFG_PCIEXP : integer := CFG_PCIE;
constant CFG_PCIE_TYPE : integer := CFG_PCIETYPE;
constant CFG_PCIE_SIM_MAS : integer := CFG_PCIEMASTER;
constant CFG_PCIEXPVID : integer := 16#CONFIG_PCIEXP_VENDORID#;
constant CFG_PCIEXPDID : integer := 16#CONFIG_PCIEXP_DEVICEID#;
co... |
-- PCIEXP interface
constant CFG_PCIEXP : integer := CFG_PCIE;
constant CFG_PCIE_TYPE : integer := CFG_PCIETYPE;
constant CFG_PCIE_SIM_MAS : integer := CFG_PCIEMASTER;
constant CFG_PCIEXPVID : integer := 16#CONFIG_PCIEXP_VENDORID#;
constant CFG_PCIEXPDID : integer := 16#CONFIG_PCIEXP_DEVICEID#;
co... |
-- PCIEXP interface
constant CFG_PCIEXP : integer := CFG_PCIE;
constant CFG_PCIE_TYPE : integer := CFG_PCIETYPE;
constant CFG_PCIE_SIM_MAS : integer := CFG_PCIEMASTER;
constant CFG_PCIEXPVID : integer := 16#CONFIG_PCIEXP_VENDORID#;
constant CFG_PCIEXPDID : integer := 16#CONFIG_PCIEXP_DEVICEID#;
co... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
---------------------------------------------------------------------------------------------
-- VIDEO DELAY - Slow Clock
--
-- Part of the Synkie Project: www.synkie.net
--
-- © 2013 Michael Egger, Licensed under GNU GPLv3
--
--------------------------------------------------------------------------------------------
... |
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
signal clock : bit;
begin -- only
process (clock)
variable x : integer := 0;
variable l : line;
begin -- process
write( l, string'( "x = " ) );
write( l, x );
writeline( output, l );
x := x + 1;
end process;
pr... |
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
signal clock : bit;
begin -- only
process (clock)
variable x : integer := 0;
variable l : line;
begin -- process
write( l, string'( "x = " ) );
write( l, x );
writeline( output, l );
x := x + 1;
end process;
pr... |
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
signal clock : bit;
begin -- only
process (clock)
variable x : integer := 0;
variable l : line;
begin -- process
write( l, string'( "x = " ) );
write( l, x );
writeline( output, l );
x := x + 1;
end process;
pr... |
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
entity c_not is
generic
(
width : integer := 1
);
port
(
input : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_not;
architecture behavior of c_not is
begin
P0 : process (input)
variable result : std_logic_... |
library ieee;
use ieee.std_logic_1164.all;
entity c_not is
generic
(
width : integer := 1
);
port
(
input : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_not;
architecture behavior of c_not is
begin
P0 : process (input)
variable result : std_logic_... |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_types
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume Rembert
-------------------------------
---- Licence:
---- MIT
-------------... |
-- Test extended identifiers
architecture foo of bar is
signal \foo bar\ : integer;
signal \a\\b\ : integer;
signal \Thing!!! \ : integer;
signal \name\ : integer;
signal name : integer;
begin
\foo.bar.baz\ <= \hello\;
end architecture;
|
-- Test extended identifiers
architecture foo of bar is
signal \foo bar\ : integer;
signal \a\\b\ : integer;
signal \Thing!!! \ : integer;
signal \name\ : integer;
signal name : integer;
begin
\foo.bar.baz\ <= \hello\;
end architecture;
|
-- Test extended identifiers
architecture foo of bar is
signal \foo bar\ : integer;
signal \a\\b\ : integer;
signal \Thing!!! \ : integer;
signal \name\ : integer;
signal name : integer;
begin
\foo.bar.baz\ <= \hello\;
end architecture;
|
-- Test extended identifiers
architecture foo of bar is
signal \foo bar\ : integer;
signal \a\\b\ : integer;
signal \Thing!!! \ : integer;
signal \name\ : integer;
signal name : integer;
begin
\foo.bar.baz\ <= \hello\;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use work.pp_types.all;
--! @brief Simple priority-based wishbone arb... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--
-- hwt_semaphore_post.vhd: measure time for semaphore_post() operation
--
-- This HW thread measures the time it takes to execute a semaphore_post()
-- operation from hardware.
-- To avoid side effects caused by activity of the delegate after returnung
-- from a sem_post() call, this thread waits a defined number of... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 15-02-2016
-- Module Name: decoder_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_116... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Yuan Mei
--
-- Create Date: 12/13/2013 07:56:40 PM
-- Design Name:
-- Module Name: global_clock_reset - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- This module en... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_7.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ------------------------------------------------... |
-- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab7_lib;
CONFIGURATION fetch_stage_struct_config OF fetch_stage IS
FOR struct
... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Procesador IS
END TB_Procesador;
ARCHITECTURE behavior OF TB_Procesador IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT unionModulos
PORT(
clk : IN std_logic;
rst : IN std_logic;
salida : OUT std_... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_AB_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this fil... |
-- $Id: rbd_tester.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versio... |
-- $Id: rbd_tester.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versio... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.cart_slot_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.command_if_pkg.all;
library std;
use std.textio.all;
entity harness_logic_32 is
end entity;
architecture tb of harn... |
/* Using vhdl 2008 comments. */
entity simple08 is
end;
architecture behav of simple08 is
begin
process
begin
assert false report "Test is running" severity note;
wait; -- Indefinite
end process;
end behav;
|
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