content stringlengths 1 1.04M ⌀ |
|---|
/* Using vhdl 2008 comments. */
entity simple08 is
end;
architecture behav of simple08 is
begin
process
begin
assert false report "Test is running" severity note;
wait; -- Indefinite
end process;
end behav;
|
--
-- File Name: CoveragePkg.vhd
-- Design Unit Name: CoveragePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis SynthWorks
-- Matthias Alles Creonic. Inspired GetMinBinVal, GetMinPoint, GetC... |
-- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
-- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
package pkg is
end package;
context ctx is
library lib;
use lib.pkg.all;
end context;
|
package pkg is
end package;
context ctx is
library lib;
use lib.pkg.all;
end context;
|
package pkg is
end package;
context ctx is
library lib;
use lib.pkg.all;
end context;
|
-- NEED RESULT: ARCH00409.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00409: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00409: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00409: One i... |
-- $Id: rbd_eyemon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: rbd_eyemon - syn
-- Description: rbus dev: ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
PORT (
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Author: Varun Nagpal
-- May 4th, 2019
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- This design implements an FIR Moving Average filter
-- which averages L points
--
-- y[n] = ( x[n] + x[n-1] + .. + x[n-L-1] ) / L
--
-- To design above FIR filer using minimum number of adders,
-- we modi... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ControlUnit is
port(reset : in std_logic;
clk : in std_logic;
statop : in std_logic;
laprst : in std_logic;
cntReset : out std_logic;
cntEnable : out std_logic;
regEnable : out std_logic);
end ControlUnit;
architecture Behavioral of C... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: endianness_pkg
-- Date:2015-01-15
-- Author: Gideon
-- Description:
--------------------------------------------------------------------------------
library ieee;
use ieee... |
entity reader is
end reader;
use std.textio.all;
architecture behav of reader is
begin
process
file f : text is in "input.txt";
variable l : line;
begin
for i in 1 to 5 loop
readline (f, l);
end loop;
wait;
end process;
end behav;
|
package pkg is
type prot_t is protected
procedure proc;
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc is
procedure nested_proc is
begin
end procedure;
function nested_fun return integer is
begin
return 0;
end fun... |
package pkg is
type prot_t is protected
procedure proc;
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc is
procedure nested_proc is
begin
end procedure;
function nested_fun return integer is
begin
return 0;
end fun... |
package pkg is
type prot_t is protected
procedure proc;
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc is
procedure nested_proc is
begin
end procedure;
function nested_fun return integer is
begin
return 0;
end fun... |
package pkg is
type prot_t is protected
procedure proc;
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc is
procedure nested_proc is
begin
end procedure;
function nested_fun return integer is
begin
return 0;
end fun... |
package pkg is
type prot_t is protected
procedure proc;
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc is
procedure nested_proc is
begin
end procedure;
function nested_fun return integer is
begin
return 0;
end fun... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
--use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v1_03_a;
use reconos_v1_03_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity game_rom is
Port ( address : in STD_LOGIC_VECTOR (15 downto 0);
clock : in STD_LOGIC;
we : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0));
e... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: lpm_add_sub_db0.vhd
-- Megafunction Name(s):
-- lpm_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ==============... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity threeph is
Port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
crload: in STD_LOGIC;
crread: in STD_LOGIC;
rateloa... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
------------------------------------------------------... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
--Part of Mano Basic Computer
--Behzad Mokhtari; MokhtariBehzad@Gmail.com
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--FlipFlopJK
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity flipflopJK is... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This... |
-------------------------------------------------------------------------------
-- Title : BMP Package
-- Project :
-------------------------------------------------------------------------------
-- File : sim_bmppack.vhd
-- Author : Kest
-- Company :
-- Created : 2006-12-05
-- Last update: 20... |
-- includes
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY bouton_diode IS
PORT (
-- le bouton
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
B : IN STD_LOGIC;
D : OUT STD_LOGIC
);
END bouton_diode ;
ARCHITECTURE arch OF bouton_diode IS
TYPE STATE_TYPE IS (debut, a0, a1, e0);
SIGN... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity testcase is
generic ( DATA_WIDTH : natural := 32 );
port (
ce : in std_logic;
clk : in std_logic
);
end entity testcase;
architecture behaviour of testcase is
signal reg_tmode : unsigned(1 downto 0) := "00";
begin
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity testcase is
generic ( DATA_WIDTH : natural := 32 );
port (
ce : in std_logic;
clk : in std_logic
);
end entity testcase;
architecture behaviour of testcase is
signal reg_tmode : unsigned(1 downto 0) := "00";
begin
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
library verilog;
use verilog.vl_types.all;
entity generic_m20k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string ... |
library verilog;
use verilog.vl_types.all;
entity generic_m20k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string ... |
library verilog;
use verilog.vl_types.all;
entity generic_m20k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string ... |
library verilog;
use verilog.vl_types.all;
entity generic_m20k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string ... |
library verilog;
use verilog.vl_types.all;
entity generic_m20k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 14:11:00 11/22/2009
-- Design Name: FIFO
-- Module Name: FIFODualPortRam - rtl
-- Description: Dual port RAM for FIFO
--
-- Revision:
-- Revision 0.01 - ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:35:44 08/06/2015
-- Design Name:
-- Module Name: E:/Programas_FPGA/SYNGLE_CYCLE_V3/TB_MAIN_PROCESSOR.vhd
-- Project Name: SYNGLE_CYCLE_V3
-- Target Device:
-- Tool versions... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:35:44 08/06/2015
-- Design Name:
-- Module Name: E:/Programas_FPGA/SYNGLE_CYCLE_V3/TB_MAIN_PROCESSOR.vhd
-- Project Name: SYNGLE_CYCLE_V3
-- Target Device:
-- Tool versions... |
entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",... |
entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",... |
entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",... |
entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",... |
entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:54:34 06/02/2011
-- Design Name:
-- Module Name: sha256_s0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:54:34 06/02/2011
-- Design Name:
-- Module Name: sha256_s0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:54:34 06/02/2011
-- Design Name:
-- Module Name: sha256_s0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:54:34 06/02/2011
-- Design Name:
-- Module Name: sha256_s0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
-------------------------------------------------------------------------------
-- Title : Wishbone Debugger package
-- Project : FMC DEL 1ns 4cha-stand-alone application (fmc-delay-1ns-4cha-sa)
-------------------------------------------------------------------------------
-- File : debugger_pkg.vhd
-- A... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- NEED RESULT: ARCH00639.P1: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P2: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P3: Multi inertial transactions occurred on signal asg with slice name... |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : ff3_rtl.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_i: in std_logic;
rst_i: in std_logic;
-- external SRAM / EEPROM SPI interface
spi_ssn_o: out std_logic;
spi_ssn2_o: ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_6_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author:... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_3_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-------------------------------------------------------------------------------
-- $Id: axi_quad_spi.vhd
-------------------------------------------------------------------------------
-- axi_quad_spi.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- ***... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
library verilog;
use verilog.vl_types.all;
entity clk_gen is
port(
clk_ref : in vl_logic;
reset_sw : in vl_logic;
clk : out vl_logic;
clk_n : out vl_logic;
chip_reset : out vl_logic
);
end clk_gen;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
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