content stringlengths 1 1.04M ⌀ |
|---|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Aut... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Aut... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Aut... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Aut... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Aut... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_misc.all;
entity flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_misc.all;
entity flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_misc.all;
entity flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:32:48 11/24/2011
-- Design Name:
-- Module Name: C:/Users/Digitales/Desktop/roadWarriorV2/roadWarrior/testRoadWarrior.vhd
-- Project Name: roadWarrior
-- Target Device:
-- ... |
--
-- File Name: SortListPkg_int.vhd
-- Design Unit Name: SortListPkg_int
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
-- Description:
-- Sorting utility for array of scalars
-... |
--
-- File Name: SortListPkg_int.vhd
-- Design Unit Name: SortListPkg_int
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
-- Description:
-- Sorting utility for array of scalars
-... |
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
---------------------------------------------------------------------------------
--Project Test Bench------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION-------------------------------------------------------... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity softcore is port (
clk, RX : in STD_LOGIC;
TX : out STD_LOGIC;
SW : in std_logic_vector(7 downto 0);
LED : out STD_LOGIC_VECTOR (7 downto 0));
end softcore;
architecture Behavioral of softcore is
component microblaze port(
Cl... |
component system is
port (
clk_50_clk : in std_logic := 'X'; -- clk
kernel_clk_clk : out std_logic; -- clk
memory_mem_a ... |
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions ... |
-- Btrace 448
-- Sphere Generator - Test Bench
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.btrace_pack.all;
entity spheregen_TB is
end spheregen_TB;
architecture arch of spheregen_TB is
... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
-- Ejercicio 3, contador Asíncrono
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.txt_util.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_Cont32bAsync IS
END tb_Cont32bAsync;
ARCHITECTURE behavi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY amplifier_tb IS
END amplifier_tb;
ARCHITECTURE behavior OF amplifier_tb IS
-- Component Declaration for the Unit Under Test (UUT)... |
library verilog;
use verilog.vl_types.all;
entity IDctr is
port(
Op : in vl_logic_vector(5 downto 0);
Func : in vl_logic_vector(5 downto 0);
Condition : out vl_logic_vector(2 downto 0);
Branch : out vl_logic;
MemWrite ... |
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digi... |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
--
-- Automatically generated
-- with the command 'bin/ipxact2vhdl --srcFile example/input/test.xml --destDir example/output'
--
-- Do not manually edit!
--
-- VHDL 93
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package example_vhd_pkg is
constant addr_width : natural := 3;
constant d... |
--
-- Automatically generated
-- with the command 'bin/ipxact2vhdl --srcFile example/input/test.xml --destDir example/output'
--
-- Do not manually edit!
--
-- VHDL 93
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package example_vhd_pkg is
constant addr_width : natural := 3;
constant d... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is dis... |
-- Company: Fachhochschule Dortmund
-- Engineer: Mysara Ibrahim
--
-- Create Date: 27/06/2017 10:20:32 AM
-- Design Name: Comparator Unit for Convolutional Codes example project
-- Module Name: MyComparator - Behavioral
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_6_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: in... |
entity guard is
end entity;
architecture test of guard is
signal value : natural := 0;
signal output : natural;
begin
b1: block (value < 10) is
begin
p1: output <= guarded value * 2;
p2: with output select value <= guarded output + 1 when others;
end block;
end architecture;
|
-- *** a.a-CU-HW.vhd *** --
-- this block is describes the control unit.
-- This is a Hardwired control unit
-- Microcode LUT is declared directly here
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.myTypes.all;
entity dlx_cu is
generic (
MICROC... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myMux2 is
port(a: in std_logic; b: in std_logic; sel: in std_logic; s: out std_logic);
end myMux2;
architecture behavioral of myMux2 is
component myAnd2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myOr2
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity DS1722 is
Port( CLK_I: in std_logic;
T2: in std_logic;
RESET: in std_logic;
DATA_IN: in std_logic_vector(7 downto 0);
DATA_OUT: out std_logic_vector(7 downto 0);
ADDRESS: in std_... |
architecture RTL of ENT is begin end architecture RTL;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
-- Some domment
begin
end;
architecture RTL of ENT is--some comment
begin
end;
|
-------------------------------------------------------------------------------
--! @file sbox.vhd
--! @brief AES S-box
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber (mbgh@iis.ee.ethz.ch)
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyright Copyright ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package common is
-- definition for a machine word
subtype word is std_logic_vector(31 downto 0);
subtype reg_addr_t is std_logic_vector(4 downto 0);
subtype alu_func_t is std_logic_vector(3 downto 0);
constan... |
library ieee;
use ieee.numeric_bit.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for A_CLK_struct
--
-- Generated by wig
-- on Wed Jan 29 16:39:40 2003
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Arch... |
-- Bibliotecas Utilizadas
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
--Declaracao da Entidade
ENTITY MaquinaDeEstadosPrincipal IS
--Generic();
PORT --Entradas e Saidas da entidade
(
CLK_50M : IN std_logic; --Clock dado pela Spartan3 em Hz
PS2_CLK1 : IN std_logic; --Sinal de clock inter... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity binary_to_bcd is
port(
binary: in std_logic_vector(7 downto 0);
bcd: out std_logic_vector(7 downto 0)
);
end entity;
architecture struct of binary_to_bcd is
component n_bit_adder
generic(N: integer);
port(
a: in ... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PACKAGE RS232_test IS
-------------------------------------------------------------------------------
-- Procedure for sending one byte over the RS232 serial input
-------------------------------------------------------------------------------
procedure Transmit (
... |
--Helpful resource:
--ftp://www.cs.uregina.ca/pub/class/301/multiplexer/lecture.html
library IEEE;
use IEEE.std_logic_1164.all;
entity mux8_bit is
port(
bit0 : in std_logic := '-';
bit1 : in std_logic := '-';
bit2 : in std_logic := '-';
bit3 : in std_logic := '-';
bit4 : in std_logic := '-';
... |
-- niosii_system_usb_0_avalon_usb_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_usb_0_avalon_usb_slave_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DAT... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_972 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_972;
architecture augh of cmp_972 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_972 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_972;
architecture augh of cmp_972 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity VOICE is
port
(
start:in std_logic;
clk:in std_logic;
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_lo... |
-- top.vhd
-- this VHDL design instatiates a Qsys system with a Nios II processor that has access to the many diffent peripherals
-- on the BeMicro Max 10 board.
--
-- There are many different software examples included in the software folder.
library ieee;
use ieee.std_logic_1164.all;
-- The following is the ent... |
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_prescaler is
end tb_prescaler;
-- Beim Testen den Prescaler anpassen
architecture sim of tb_prescaler is
component prescaler
port (
clk50 : in std_logic;
reset_n : in std_logic;
clk1 : out std_logic);
end component... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Components declaration of the types_pll package.
-----------------------------------------------... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Components declaration of the types_pll package.
-----------------------------------------------... |
-- Test extended identifiers
entity bar is
end entity;
architecture foo of bar is
signal \foo bar\ : integer;
signal \a\\b\ : integer;
signal \Thing!!! \ : integer;
signal \name\ : integer;
signal name : integer;
signal \foo.bar.baz\ : integer;
signal \hello\ : integer;
begin
\foo.bar.... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:49:02 09/11/2011
-- Design Name:
-- Module Name: picas - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 13:56:52
-- Design Name:
-- Module Name: aeg_design_0_switch_port
-- Description: This module describes one port for the Ethernet switch
-- ... |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 13:56:52
-- Design Name:
-- Module Name: aeg_design_0_switch_port
-- Description: This module describes one port for the Ethernet switch
-- ... |
-------------------------------------------------------------------------------
-- Title : Configurable Cordic core
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_core.vhd
-- Author : Aylons <aylons@aylons-yoga2>
-- Company :
-- Create... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
entity test is
type t is range 0 to 2#1#;
end;
|
package pkg is
type prot_t is protected
procedure proc(x : out integer);
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc(x : out integer) is
function nested_fun return integer is
begin
return 5;
end function;
procedure nested_... |
package pkg is
type prot_t is protected
procedure proc(x : out integer);
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc(x : out integer) is
function nested_fun return integer is
begin
return 5;
end function;
procedure nested_... |
package pkg is
type prot_t is protected
procedure proc(x : out integer);
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc(x : out integer) is
function nested_fun return integer is
begin
return 5;
end function;
procedure nested_... |
package pkg is
type prot_t is protected
procedure proc(x : out integer);
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc(x : out integer) is
function nested_fun return integer is
begin
return 5;
end function;
procedure nested_... |
package pkg is
type prot_t is protected
procedure proc(x : out integer);
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc(x : out integer) is
function nested_fun return integer is
begin
return 5;
end function;
procedure nested_... |
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 11:37:33 11/10/2015
-- Design Name:
-- Module Name: FSM_motor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Descripti... |
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 11:37:33 11/10/2015
-- Design Name:
-- Module Name: FSM_motor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Descripti... |
architecture RTL of FIFO is
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer:= 1024;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_3_block.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ---------------------... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_4_block6.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------... |
-------------------------------------------------------------------------------
--
-- File: PkgZmodDAC.vhd
-- Author: Tudor Gherman
-- Original Project: Zmod DAC 1411 Low Level Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digil... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- $Id: xbic_addr_be_support.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_addr_be_support.vhd
---------------------------------------------------------... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.