content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------------------------
-- Sparse FIR Tap
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
-------------------------------------------------------... |
-- $Id: cmoda7_sram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: cmoda7_sram_dummy - syn
-- Description: ... |
------------------------------------------------------------------------------
-- Entity: esa_pciarb
-- File: esa_pciarb.vhd
-- Author: Marko Isomaki
-- Description: GRLIB wrapper for the ESA PCI arbiter
------------------------------------------------------------------------------
library ieee;
library grlib;
... |
------------------------------------------------------------------------------
-- Entity: esa_pciarb
-- File: esa_pciarb.vhd
-- Author: Marko Isomaki
-- Description: GRLIB wrapper for the ESA PCI arbiter
------------------------------------------------------------------------------
library ieee;
library grlib;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_4.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ====================... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
library verilog;
use verilog.vl_types.all;
entity MUX4_1_5bit is
port(
Sel : in vl_logic_vector(1 downto 0);
S0 : in vl_logic_vector(4 downto 0);
S1 : in vl_logic_vector(4 downto 0);
S2 : in vl_logic_vector(4 downto 0... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_ok_3_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id:... |
--
-- File Name: TbUtilPkg.vhd
-- Design Unit Name: TbUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@SynthWorks.com
-- Contributor(s):
-- Jim Lewis email: jim@SynthWorks.com
--
-- Package Defines
--
-- Developed for:
-- SynthWorks Desi... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Thu May 1 14:04:03 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Thu May 1 14:04:03 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
-- CTRL_BIT_REGISTER
-- Einlesen der einzelnen Werte für bestimmte Bits, Berechung der Parität und Ausgabe als Byte
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 08.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 25.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http:/... |
-- CTRL_BIT_REGISTER
-- Einlesen der einzelnen Werte für bestimmte Bits, Berechung der Parität und Ausgabe als Byte
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 08.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 25.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http:/... |
-- CTRL_BIT_REGISTER
-- Einlesen der einzelnen Werte für bestimmte Bits, Berechung der Parität und Ausgabe als Byte
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 08.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 25.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http:/... |
-- CTRL_BIT_REGISTER
-- Einlesen der einzelnen Werte für bestimmte Bits, Berechung der Parität und Ausgabe als Byte
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 08.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 25.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http:/... |
-- light8080_ucode_pkg.vhdl -- Microcode table for light8080 CPU core.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package light8080_ucode_pkg is
type t_rom is array (0 to 511) of std_logic_vector(31 downto 0);
constant microcode : t_rom := (
"00000000000000000000000000000000", -- 000
... |
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:04:20 07/16/2014
-- Design Name:
-- Module Name: encryption_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : E X T R A C T O B S E R V A T I O N
--
--
-- The user function... |
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
... |
----------------------------------------------------------------------------------
-- pulse32.vhd: 32-bit pulser
-- output is high as long as (count < threshold)
-- note: output is clocked
----------------------------------------------------------------------------------
library ieee;
us... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Lice... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Lice... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Lice... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Lice... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package driveseg_pkg is
component driveseg
Port(
data : in STD_LOGIC_VECTOR (15 downto 0);
seg_c : out STD_LOGIC_VECTOR (7 downto 0);
seg_a : out std_logic_vector (3 downto 0);
en : in std_logic_vector(3 downto 0);
clk : in std_logic;
rst : in std_logic);
end c... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:04:29 12/04/2012
-- Design Name:
-- Module Name: ControlBranch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenci... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:04:29 12/04/2012
-- Design Name:
-- Module Name: ControlBranch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenci... |
package pack is
type sl2d_t is array(natural range <>, natural range <>) of bit;
type slv_7_0_t is array(natural range <>) of bit_vector(7 downto 0);
constant size_log2 : integer := 15;
subtype ram_bank_t is slv_7_0_t(0 to (2**size_log2) - 1);
type ram_t is array(0 to 0) of ram_bank_t;
constant r... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_32bit is
port (
SEL: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (31 downto 0);
B: in STD_LOGIC_VECTOR (31 downto 0);
OUTPUT: out STD_LOGIC_VECTOR (31 downto 0)
);
end mux_32bit;
architecture Behavioral of mux_32bit is
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:56:35 04/22/2016
-- Design Name:
-- Module Name: PC_INC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:56:35 04/22/2016
-- Design Name:
-- Module Name: PC_INC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:56:35 04/22/2016
-- Design Name:
-- Module Name: PC_INC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_jtag_debug_module_sysclk is
port(
clk : in vl_logic;
ir_in : in vl_logic_vector(1 downto 0);
sr : in vl_logic_vector(37 downto 0);
vs_udr : in vl_logic;
... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 11:48:22 2017
-- Host : vldmr-PC running 64-bit Service Pack... |
-- functions for resizing vectors with the comma located at the MSB
-- resize_to_msb_trunc realizes a truncation to the new wordsize, if new_size is lower than old size
-- resize_to_msb_trunc realizes a rounding to the new wordsize, if new_size is lower than old size with the use of one additional adder
-- This pr... |
-- functions for resizing vectors with the comma located at the MSB
-- resize_to_msb_trunc realizes a truncation to the new wordsize, if new_size is lower than old size
-- resize_to_msb_trunc realizes a rounding to the new wordsize, if new_size is lower than old size with the use of one additional adder
-- This pr... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the ... |
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
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`protect begin_protected
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`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect begin_protected
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`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
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`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/15/2015 02:54:47 PM
-- Design Name:
-- Module Name: invSubByte - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/15/2015 02:54:47 PM
-- Design Name:
-- Module Name: invSubByte - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
library ieee;
use ieee.std_logic_1164.ALL;
entity child is
port (
O1: out std_logic;
O2: out std_logic
);
end entity child;
architecture rtl of child is
begin
O1 <= '0';
O2 <= '1';
end architecture rtl;
library ieee;
use ieee.std_logic_1164.ALL;
entity top is
port (
O: out std_logic
);
end ... |
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behaviora... |
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behaviora... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
-- Spacewire interface
constant CFG_SPWRTR_ENABLE : integer := CONFIG_SPWRTR_ENABLE;
constant CFG_SPWRTR_INPUT : integer := CONFIG_SPWRTR_INPUT;
constant CFG_SPWRTR_OUTPUT : integer := CONFIG_SPWRTR_OUTPUT;
constant CFG_SPWRTR_RTSAME : integer := CONFIG_SPWRTR_RTSAME;
constant CFG_SPWRTR_FIFO ... |
-- Spacewire interface
constant CFG_SPWRTR_ENABLE : integer := CONFIG_SPWRTR_ENABLE;
constant CFG_SPWRTR_INPUT : integer := CONFIG_SPWRTR_INPUT;
constant CFG_SPWRTR_OUTPUT : integer := CONFIG_SPWRTR_OUTPUT;
constant CFG_SPWRTR_RTSAME : integer := CONFIG_SPWRTR_RTSAME;
constant CFG_SPWRTR_FIFO ... |
-- Spacewire interface
constant CFG_SPWRTR_ENABLE : integer := CONFIG_SPWRTR_ENABLE;
constant CFG_SPWRTR_INPUT : integer := CONFIG_SPWRTR_INPUT;
constant CFG_SPWRTR_OUTPUT : integer := CONFIG_SPWRTR_OUTPUT;
constant CFG_SPWRTR_RTSAME : integer := CONFIG_SPWRTR_RTSAME;
constant CFG_SPWRTR_FIFO ... |
-- Spacewire interface
constant CFG_SPWRTR_ENABLE : integer := CONFIG_SPWRTR_ENABLE;
constant CFG_SPWRTR_INPUT : integer := CONFIG_SPWRTR_INPUT;
constant CFG_SPWRTR_OUTPUT : integer := CONFIG_SPWRTR_OUTPUT;
constant CFG_SPWRTR_RTSAME : integer := CONFIG_SPWRTR_RTSAME;
constant CFG_SPWRTR_FIFO ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- File name: fifo.vhd
-- Created: 2009-04-20 (^-^)y-~~'`
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: FIFO
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
size : positi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity InternalROM is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(16 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;... |
architecture RTL of FIFO is
begin
process is
begin
end process;
-- Comments are allowed
PROC_LABEL : process
begin
end process;
-- Violations below
a <= b;
process is begin
end process;
b <= z;
PROC_LABEL : process begin
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity i2s_rx_tx is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-... |
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity i2s_rx_tx is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-... |
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