content stringlengths 1 1.04M ⌀ |
|---|
-- File: elevator.vhd
-- Generated by MyHDL 0.8.1
-- Date: Sun Jun 14 22:11:56 2015
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_081.all;
entity elevator is
port (
clk: in std_logic;
reset: in std_logic;
en: in std_logic;
... |
----------------------------------------------
-- Design Name : Test bench utils for apf27
-- File Name : apf27_test_pkg.vhd
-- Function : Defines communication functions between imx and fpga
-- Author : Fabien Marteau <fabien.marteau@armadeus.com>
-- Version : 1.00
---------------------------------------------
----... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 15:28:57 11/14/2015
-- Design Name:
-- Module Name: Register_Files - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dep... |
-- Create Date: 16:41:40 09/28/2017
-- Design Name:
-- Module Name: Mod5Seu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Mod5Seu is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
... |
-- Create Date: 16:41:40 09/28/2017
-- Design Name:
-- Module Name: Mod5Seu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Mod5Seu is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity test is
end test;
architecture only of test is
begin -- only
p: process
type color is ( red, blue, green );
variable x : color;
begin -- process p
for i in red to green loop
x := i;
end loop; -- i
assert x = green report "TEST FAILED x was " & color'image(x) severity ERROR;
report "TEST PASSE... |
entity test is
end test;
architecture only of test is
begin -- only
p: process
type color is ( red, blue, green );
variable x : color;
begin -- process p
for i in red to green loop
x := i;
end loop; -- i
assert x = green report "TEST FAILED x was " & color'image(x) severity ERROR;
report "TEST PASSE... |
entity test is
end test;
architecture only of test is
begin -- only
p: process
type color is ( red, blue, green );
variable x : color;
begin -- process p
for i in red to green loop
x := i;
end loop; -- i
assert x = green report "TEST FAILED x was " & color'image(x) severity ERROR;
report "TEST PASSE... |
-- $Id: tst_snhumanio.vhd 416 2011-10-15 13:32:57Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
-- $Id: tst_snhumanio.vhd 416 2011-10-15 13:32:57Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
-- SIMON 64/128
-- key scheduling function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- r: round index
-- k_0..k_3: key
-- subkey_out: round subkey
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity key_schedule is
port (
r : i... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- A very basic sanity test of wait statements
entity wait1 is
end entity;
architecture test of wait1 is
begin
process is
begin
assert now = 0 ns;
wait_1: wait for 1 ns;
assert now = 1 ns;
wait for 1 fs;
assert now = 1000001 fs;
end_wait: wait;
end process;
... |
-- A very basic sanity test of wait statements
entity wait1 is
end entity;
architecture test of wait1 is
begin
process is
begin
assert now = 0 ns;
wait_1: wait for 1 ns;
assert now = 1 ns;
wait for 1 fs;
assert now = 1000001 fs;
end_wait: wait;
end process;
... |
-- A very basic sanity test of wait statements
entity wait1 is
end entity;
architecture test of wait1 is
begin
process is
begin
assert now = 0 ns;
wait_1: wait for 1 ns;
assert now = 1 ns;
wait for 1 fs;
assert now = 1000001 fs;
end_wait: wait;
end process;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- --------------------------------------------------------------------
-- Title : Standard VHDL Synthesis Packages (1076.3, NUMERIC_STD_UNSIGNED)
--
-- This package overloaded the arithmetic operaters for
-- "STD_ULOGIC_VECTOR", and treats this vector like an
-- "UNSIGNED"... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------
-- uut:
-- recode.vhd
-- circbuf_fast.vhd
-- description:
-- simple test_bench to verify recode behavior in normal conditions
-- with a fifo just before
-- and a fifo just after
-- expected result:
-- recode should be configured in weight configuration mo... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_aa
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-... |
-------------------------------------------------------------------------------
-- Title : CLock
-- Project :
-------------------------------------------------------------------------------
-- File : regs.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-03-13
-- ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
architecture rtl of fifo is
constant cons1 : t_type :=
(
1 => func1(std_logic_vector(G_GEN), G_GEN2),
2 => func1(std_logic_vector(G_GEN3), G_GEN4)
);
constant cons1 : t_type :=
(
1 => func1(std_logic_vector(G_GEN), G_GEN2),
2 => func1( std_logic_vector(G_GEN3), G_GEN4)
);
constant cons1 : t_... |
--------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author ... |
--------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author ... |
--------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author ... |
--------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author ... |
--------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author ... |
-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_bidir
-- ============================================================
-- File Name: bidir_dq_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_bidir
--
-- Simulation Library Files(s):
-- stratixiii
-- ============... |
-- Author: Varun Nagpal
-- Net Id: vxn180010
-- Microprocessor Systems Project
-- December, 6th 2018
--
-- Package: Modifiable Paramaters, non-modifiable constants and types (ports)
-- for the Generic Nth order (L = N+1 taps) Transposed Direct-form FIR-filter
--
-- Modifiable variables for Design of ... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- Title : Transmitter FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_t... |
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
--************************************************************************************************
-- Address decoder
-- Version 0.11A
-- Designed by Ruslan Lepetenok
-- Modified 31.07.2005
--************************************************************************************************
library IEEE;
us... |
--************************************************************************************************
-- Address decoder
-- Version 0.11A
-- Designed by Ruslan Lepetenok
-- Modified 31.07.2005
--************************************************************************************************
library IEEE;
us... |
--************************************************************************************************
-- Address decoder
-- Version 0.11A
-- Designed by Ruslan Lepetenok
-- Modified 31.07.2005
--************************************************************************************************
library IEEE;
us... |
--************************************************************************************************
-- Address decoder
-- Version 0.11A
-- Designed by Ruslan Lepetenok
-- Modified 31.07.2005
--************************************************************************************************
library IEEE;
us... |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity top is
port(
SYSCLK_P : in std_logic;
SYSCLK_N : in std_logic;
GPIO_LED : out std_logic_vector (6 downto 0));
end top;
architecture Behavioral of top is
signal clk_200Mhz : std_logi... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:58:50 07/05/05
-- Design Name:
-- Module Name: combination - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
entity issue is
end issue;
architecture sim of issue is
signal clk : std_logic := '1';
signal a, b : std_logic := '0';
begin
clk <= not clk after 5 ns;
a <= '1' after 20 ns,
'0' after 30 ns,
'1' after 40 ns,
'0' after 50 ns;
b <= '1' af... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
-------------------------------------------------------------------------------
--! @file statusControlReg.vhd
--
--! @brief Host interface Status-/Control Registers
--
--! @details The host interface status/control registers provide memory mapped
--! control of the interrupt generator (irqGen) and bridge (magicBridge)... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity crc8_blkrom is
port(
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(31 downto 0)
);
end entity;
architecture behavior of crc8_blkrom is
... |
-- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
------------------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comp200 is
port(
clkcmp2: in std_logic ;
codopcmp2: in std_logic_vector ( 3 downto 0 );
portAcmp2: in std_logic_vector ( 7 downto 0 );
inFlagcmp2: in std_logic;
outcmp2: out std_logic_vec... |
-------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY keyboard IS
PORT( keyboard_clk, keyboard_data, clock_48Mhz ,
reset, read : IN STD_LOGIC;
scan_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : OUT STD_LOGIC);
END keyboard;
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port(
clk : in std_logic;
cs : in std_logic;
read : in std_logic;
address : in std_logic_vector(9 downto 0);
rddata : out std_logic_vector(31 downto 0));
end ROM;
arch... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 10:15:34 2017
-- Host : PC4719 running 64-bit Service Pa... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY memory IS
GENERIC(N : POSITIVE := 8);
PORT(
clk, rst, R0s, R1s, R2s, R3s, R4s, R5s, R6s, R7s : STD_LOGIC;
din : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
R0out, R1out, R2out, R3out, R4out, R5out, R6out, R7out : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END ... |
architecture rtl of fifo is
begin
connect_ports(port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow);
connect_ports(
port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow);
connect_ports(port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow);
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------
entity reg_mux_tb is
generic (tp: time := 10 ns);
end entity reg_mux_tb;
--------------------------------------
architecture circuit of reg_mux_tb is
-- DUT declaration
component reg_mux is
... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.16:15:41)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesafp_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
entity proc_core is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF";
support_bcd : boolean := true );
port(
clock : in ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
entity proc_core is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF";
support_bcd : boolean := true );
port(
clock : in ... |
-- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Description: Hardware Testbench for remote_terminal_control.
-- See DUT descri... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.usb_pkg.all;
entity nano_minimal_io is
generic (
g_support_suspend : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 29 22:11:05 2017
-- Host : GILAMONSTER running 64-bit major rel... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/Complex3Multiply_block3.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "... |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_types.all;
use work.pp_utilitie... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:37:54 04/11/2017
-- Design Name:
-- Module Name: debounce - logic
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.