content stringlengths 1 1.04M ⌀ |
|---|
package pack is
function func(x : integer) return integer;
procedure proc(x : integer);
end package;
-------------------------------------------------------------------------------
entity duplicate is
end entity;
use work.pack.all;
architecture test of duplicate is
function func(x : integer) return inte... |
package pack is
function func(x : integer) return integer;
procedure proc(x : integer);
end package;
-------------------------------------------------------------------------------
entity duplicate is
end entity;
use work.pack.all;
architecture test of duplicate is
function func(x : integer) return inte... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
... |
-------------------------------------------------------------------------------
-- Model: SOLID CYLINDER for TIME-DOMAIN ANALYSIS
--
-- Author: Vladimir Kolchuzhin, MMT, TU Chemnitz
-- <vladimir.kolchuzhin@etit.tu-chemnitz.de>
-- Date: 01.12.2014
-- Library:
-- kvl in hAMSter
-----------------------------------------... |
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Jakub Cabal
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, cop... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--High-Speed D-PHY lane RX PHY for MIPI CSI-2 Rx core
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This entity handles input skew compensation and deserialisation for the
--CSI data ... |
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end record;
type t_record is record
a : std_logic;
b : std_logic;
end record;
type t_record is record a : std_logic; b : std_logic;
end record;
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_978 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_978;
architecture augh of cmp_978 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_978 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_978;
architecture augh of cmp_978 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
--
-- VHDL Architecture lab12_Memory_lib.SRAM.behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 20:20:22 04/22/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
LIBRARY std;
USE std.textio.all;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 15;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
archit... |
-- VHDL do Fluxo de Dados interface recepcao
library ieee;
use ieee.std_logic_1164.all;
entity fluxo_dados_interface_recepcao is
port(
clock: in std_logic;
enable: in std_logic;
entrada: in std_logic_vector(11 downto 0);
saida: out std_logic_vector(11 downto 0)
);
end fluxo_dados_interface_rece... |
--!
--! @file: full_adder.vhd
--! @brief: full adder
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity full_adder is
port (
a, b: std_logic;
... |
-- $Id: tb_pdp11core.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_pdp11core - sim
-- Description: Test b... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity io_bus_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity io_bus_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity io_bus_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity io_bus_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity io_bus_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code mus... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.rtl_pack.all;
use work.tb_pack.all;
entity gearbox_tb is
end;
architecture tb of gearbox_tb is
constant a_width_g : positive := 4;
constant b_width_g : positive := 3;
constant fifo_depth_order_g : positive := 4;
signal ... |
entity test_output is
port (
output : inout integer := 10
);
end test_output;
architecture only of test_output is
begin -- test_output
test: process
begin -- process test
assert output = 10 report "test failed" severity error;
assert output /= 10 report "test passed" severity note;
wait;
... |
entity test_output is
port (
output : inout integer := 10
);
end test_output;
architecture only of test_output is
begin -- test_output
test: process
begin -- process test
assert output = 10 report "test failed" severity error;
assert output /= 10 report "test passed" severity note;
wait;
... |
entity test_output is
port (
output : inout integer := 10
);
end test_output;
architecture only of test_output is
begin -- test_output
test: process
begin -- process test
assert output = 10 report "test failed" severity error;
assert output /= 10 report "test passed" severity note;
wait;
... |
library verilog;
use verilog.vl_types.all;
entity dcfifo_low_latency is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_width_r : vl_notype;
lpm_widthu_r : vl_notype;
lpm_numwords : integer := 2;
delay_rdusedw : integer := 2;
... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture ARCH of ENTITY is
signal sig1, sig2, sig3,
sig4, sig5, sig6 : std_logic;
signal siga, sigb,
sigc,
sigd,
sige,
sigf
: std_logic; -- This is a comment
-- Test variations of a single signal declaration
signal sig1 : std_logic;
signal sig1 : std_logic
;
si... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- NEED RESULT: ARCH00558: Variable declarations - composite static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
------------------------------------------------------... |
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.mac_types.all;
entity mac_expectedoutput is
port(arg : in signed(8 downto 0);
-- clock
system1000 : in std_logic;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Generated Configuration for vgca_tb
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
-- test_ng.vhd
entity TEST_NG is
generic (
INFO_BITS : integer := 1;
INFO_1_VAL : integer := 0
);
port (
I_INFO_0 : in bit_vector(INFO_BITS-1 downto 0);
I_INFO_1 : in bit_vector(INFO_BITS-1 downto 0);
O_INFO_0 : out bit_vector(INFO_BITS-1 downto 0);
... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
--input 48.828125 kHz 8 bit audio
--interpolated to 2048 * 8 * 48.828125 = 800 MHz sampling rate 19-bits
--upconverted to lo
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto... |
--input 48.828125 kHz 8 bit audio
--interpolated to 2048 * 8 * 48.828125 = 800 MHz sampling rate 19-bits
--upconverted to lo
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto... |
--input 48.828125 kHz 8 bit audio
--interpolated to 2048 * 8 * 48.828125 = 800 MHz sampling rate 19-bits
--upconverted to lo
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto... |
library ieee;
use ieee.std_logic_1164.all;
entity var05 is
port (sel : std_logic;
a, b : std_logic_vector (1 downto 0);
res : out std_logic_vector (1 downto 0));
end var05;
architecture behav of var05 is
begin
process (all)
variable idx : integer;
begin
res <= a;
if sel = '1' then
... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
library verilog;
use verilog.vl_types.all;
entity CMMaster0Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_TESTREMAPENABLE: in vl_logic;
F2_TESTESRAM1REMAP: in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
... |
library verilog;
use verilog.vl_types.all;
entity CMMaster0Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_TESTREMAPENABLE: in vl_logic;
F2_TESTESRAM1REMAP: in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
... |
library verilog;
use verilog.vl_types.all;
entity CMMaster0Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_TESTREMAPENABLE: in vl_logic;
F2_TESTESRAM1REMAP: in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
... |
component ni2 is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_external_connection_export : out std_logic_vector(7 downto 0) -- export
);
end component ni2;
u0 : component ni2
port map (
clk_clk => CONNECTED_TO_clk_clk, ... |
component ni2 is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_external_connection_export : out std_logic_vector(7 downto 0) -- export
);
end component ni2;
u0 : component ni2
port map (
clk_clk => CONNECTED_TO_clk_clk, ... |
component ni2 is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_external_connection_export : out std_logic_vector(7 downto 0) -- export
);
end component ni2;
u0 : component ni2
port map (
clk_clk => CONNECTED_TO_clk_clk, ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY t_display IS
END t_display;
ARCHITECTURE behavior OF t_display IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT display
PORT(
a : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
display1 : OUT st... |
library ieee;
use ieee.std_logic_1164.all;
entity substractor is
port(
X, Y: in std_logic_vector(3 downto 0);
Bin: in std_logic;
D: out std_logic_vector(3 downto 0);
Bout: out std_logic
);
end entity;
architecture substractor of substractor is
component full_sub is
port(
X, Y: in std... |
--
-- ADC interface
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of so... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library ieee ;
context ieee.ieee_std_context;
use work.components.all;
entity top is
port (
pin1: out std_logic
);
attribute LOC: string;
attribute LOC of pin1: signal is "13";
end;
architecture arch of top is
signal clk: std_logic;
signal led_timer: unsigned(23 downto 0) := (others=>'0');
begin
... |
library ieee ;
context ieee.ieee_std_context;
use work.components.all;
entity top is
port (
pin1: out std_logic
);
attribute LOC: string;
attribute LOC of pin1: signal is "13";
end;
architecture arch of top is
signal clk: std_logic;
signal led_timer: unsigned(23 downto 0) := (others=>'0');
begin
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:34:50 02/23/2010
-- Design Name:
-- Module Name: VGA_Display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
entity delay3 is
end entity;
architecture test of delay3 is
signal x : bit;
begin
p1: process is
variable v : time := 5 ns;
begin
x <= reject v inertial '1' after 2 ns;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Data/address/control bus for simple von-Neumann MCU.
-- The bus master (CPU) can read/write in e... |
------------------------------------------------------------------------
-- title : package for the 10 gig ethernet mac fifo reference design
-- project : 10 gig ethernet mac fifo reference design
------------------------------------------------------------------------
-- file : xgmac_fifo_pack.vhd
-- author : xi... |
------------------------------------------------------------------------
-- title : package for the 10 gig ethernet mac fifo reference design
-- project : 10 gig ethernet mac fifo reference design
------------------------------------------------------------------------
-- file : xgmac_fifo_pack.vhd
-- author : xi... |
------------------------------------------------------------------------
-- title : package for the 10 gig ethernet mac fifo reference design
-- project : 10 gig ethernet mac fifo reference design
------------------------------------------------------------------------
-- file : xgmac_fifo_pack.vhd
-- author : xi... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity vga_demo is
port(
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);
VGA_HS : o... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
entity rotate_mix_nibbles is
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end entity;
architecture structual of rotate_mix_nibbles is
signal rotated: std_logic_vector(63 downto 0);
signal mix_mul_in,... |
--------------------------------------------------------------------------------
--
-- FileName: pwm.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF A... |
------------------------------------------------------------------------------
-- Title : BPM RF channels swapping and de-swapping mode selector
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-... |
-------------------------------------------------------------------------------
-- File Name : BUF_FIFO.vhd
--
-- Project : JPEG_ENC
--
-- Module : BUF_FIFO
--
-- Content : Input FIFO Buffer
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY demux IS
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY demux IS
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:32:19 01/31/2015
-- Design Name:
-- Module Name: /home/james/devroot/learnfpga/midi/tb/shift_out_tb.vhdl
-- Project Name: midi
-- Target Device:
-- Tool versions:
-- Description: ... |
-- NEED RESULT: ARCH00018: Wait in P1_1 did resume passed
-- NEED RESULT: ARCH00018: Wait in P1_2 did resume passed
-- NEED RESULT: ARCH00018: Wait in P2_1 did resume passed
-- NEED RESULT: ARCH00018: Wait in P2_2 did resume passed
-- NEED RESULT: ARCH00018: Wait in P3_1 did resume passed
-- NEED RESULT: ARCH00018... |
-- NEED RESULT: ARCH00289: Logical operators are correctly predefined for boolean array types passed
-- NEED RESULT: ARCH00289: Logical operators are correctly predefined for bit array types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Inter... |
-- **************************************************
-- * Circuito de pruebas para la sincronización VGA *
-- **************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_top is
port(
clk , rst : in std_logic;
sw : in std... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity flashyLights is
Port ( CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end flashyLights;
architecture Behavioral of flashyLights is
COMPONENT counter30 PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(29 DOWNTO 0));
END COMPON... |
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/27/2017 08:36:56 AM
-- Module Name: regfile - Behavioral
-- Description:
-- Additional Comments:
----------------------------------------------------------------------------------
librar... |
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