content stringlengths 1 1.04M ⌀ |
|---|
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2)... |
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2)... |
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2)... |
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Mar 8 21:33:13 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_testbench is
port(done : out boolean);
end;
architecture structural of packetprocessordf_te... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:35:20 11/27/2016
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
entity ram1 is
end entity;
architecture test of ram1 is
type byte_array_t is array (natural range <>) of bit_vector(7 downto 0);
signal ram : byte_array_t(15 downto 0);
signal addr : integer;
signal dout : bit_vector(7 downto 0);
signal din : bit_vector(7 downto 0);
signal we : bit;
begin
... |
process(CLK)
begin
if(CLK = '1' and CLK'event) then
Q <= D;
end if;
end process;
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
-- Testbench for FIR Moving Average filter which averages L points
entity Testbench is
end Testbench;
architecture test of Testbench is
-- Constants to initialize generics of ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in s... |
-- Baudrate Generator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity baudrategenerator is
generic
(
NUM_BAUD_CLOCK_TICKS : unsigned := to_unsigned(417-1,9); -- 8.000.000 / 19200 = 417
TX_TRIGGER_VALUE : unsigned := to_unsigned(1-1,9) -- ???
);
port
(
clk : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
-- framebuffer access
data_i : in std_logic_vector(7 downto 0);
write_row_i : in std_logic;
write_column_i : in std_logic;
write_color_i : in st... |
-- synthesis library lib
--------------------------------------------------------------------
-- Project : SPI receivers master
-- Author : AlexRayne
-- Date : 2009.03.16.03
-- File :
-- Design :
--------------------------------------------------------------------
-- Description : (win1251) SPI мастер-при... |
library ieee;
use ieee.std_logic_1164.all;
library work;
entity testbench_passage_a_niveau is
end entity;
architecture behaviorial of testbench_passage_a_niveau is
component passage_a_niveau is
port(
clock: in std_logic;
reset: in std_logic;
capteur_droite: in std_logi... |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:25:10 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Desktop/Frecuencimetroo 6.0/Frecuencimentro/PreEscala_TB.vhd
-- Project Name: Frecuencimentro
-- Target Devi... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:25:10 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Desktop/Frecuencimetroo 6.0/Frecuencimentro/PreEscala_TB.vhd
-- Project Name: Frecuencimentro
-- Target Devi... |
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
-- Violations below
type state_machine is (idle, write, read, done);
type state_machine is (idle, write, read, done);
begin
end architecture RTL;
|
-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.10.0.111.2
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
use IEEE.numeric_std.all;
entity tb is
end entity tb;
architecture test of tb is
component fmexg_fifo_w_flags
port (Data : in... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dff04 is
port (r : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic);
end dff04;
architecture behav of dff04 is
signal q : std_logic_vector(7 downto 0);
begin
process (clk, q) is
begi... |
--------------------------------------------------------------------------------
--! @file pulse2pulse_tb.vhd
--! @brief Testbench for pulse clock-domain crossing module pulse2pulse
--! @author Yuan Mei
--!
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logi... |
--------------------------------------------------------------------------------
--! @file pulse2pulse_tb.vhd
--! @brief Testbench for pulse clock-domain crossing module pulse2pulse
--! @author Yuan Mei
--!
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DataMemoryMulticycle is
port(
WriteData: in std_logic_vector(31 downto 0);
Address: in std_logic_vector(31 downto 0);
MemRead, MemWrite: in std_logic;
ReadData: out std_logic_vector(31 downto 0)
);
end DataMemory... |
library verilog;
use verilog.vl_types.all;
entity memory is
port(
addr_a : in vl_logic_vector(10 downto 0);
addr_b : in vl_logic_vector(10 downto 0);
clk : in vl_logic;
q_a : out vl_logic_vector(7 downto 0);
q_b ... |
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eXnor is
port(
entrada1_xnor: in std_logic;
entrada2_xnor: in std_logic;
salida_xnor: out std_logic);
end;
-- Arquitectura
architecture aXnor of eXnor is... |
------------------------------------------------------------------------------
-- This file is part of a signal tracing utility for the LEON3 processor
-- Copyright (C) 2017, ARCADE Lab @ Columbia University
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
entity imp_{{ current_var.name }} is
port (
clk: in std_logic;
reset: in std_logic;
clear: in std_logic;
change: out std_logic;
contra: out std_logic;
{% for var in variables %}
{{ var.name }}: inout std_logic_vector... |
-- revision history:
-- 06.07.2015 Alex Schoenberger created
-- 04.08.2015 Patrick Appenheimer added entity and architecture behave
-- 05.08.2015 Patrick Appenheimer bugfixes
-- 05.08.2015 Patrick Appenheimer subu, and, or added
-- 10.08.2015 Patrick Appenheimer shift, slt added
librar... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memif is
Port (
CLK : in STD_LOGIC;
-- Interface
RAM_CS : in STD_LOGIC; -- RAM chip enable
ROM_CS : in STD_LOGIC; -- ROM chip enable
RW : ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM_TB is
end entity;
architecture RTL of PWM_TB is
component PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0... |
-- PS/2 interface
constant CFG_PS2_ENABLE : integer := CONFIG_PS2_ENABLE;
|
-- PS/2 interface
constant CFG_PS2_ENABLE : integer := CONFIG_PS2_ENABLE;
|
-- PS/2 interface
constant CFG_PS2_ENABLE : integer := CONFIG_PS2_ENABLE;
|
-- PS/2 interface
constant CFG_PS2_ENABLE : integer := CONFIG_PS2_ENABLE;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 02.01.2014 13:22:29
-- Design Name:
-- Module Name: input_queue_overflow - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Vers... |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 02.01.2014 13:22:29
-- Design Name:
-- Module Name: input_queue_overflow - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Vers... |
-------------------------------------------------------------------------------
-- cpu_xadc_wiz_0_0_family.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-- USB Host Controller
constant CFG_USBHC : integer := CONFIG_GRUSBHC_ENABLE;
constant CFG_USBHC_NPORTS : integer := CONFIG_GRUSBHC_NPORTS;
constant CFG_USBHC_EHC : integer := CONFIG_GRUSBHC_EHC;
constant CFG_USBHC_UHC : integer := CONFIG_GRUSBHC_UHC;
constant CFG_USBHC_NCC : integer... |
-- USB Host Controller
constant CFG_USBHC : integer := CONFIG_GRUSBHC_ENABLE;
constant CFG_USBHC_NPORTS : integer := CONFIG_GRUSBHC_NPORTS;
constant CFG_USBHC_EHC : integer := CONFIG_GRUSBHC_EHC;
constant CFG_USBHC_UHC : integer := CONFIG_GRUSBHC_UHC;
constant CFG_USBHC_NCC : integer... |
-------------------------------------------------------------------------------
-- Title : VIA 6522
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
--------------------------------------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:07:01 11/16/2013
-- Design Name:
-- Module Name: myMux2X1_948282 - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--... |
--!-----------------------------------------------------------------------------
--! --
--! Weizmann Institute of Science --
--! Electronics & Data Acquisition Group ... |
--!-----------------------------------------------------------------------------
--! --
--! Weizmann Institute of Science --
--! Electronics & Data Acquisition Group ... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
pio_0_external_connection_export : out std_logic_vector... |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 24 22:16:07 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Copyright 2011-2013(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-... |
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_address_swap.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file c... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library verilog;
use verilog.vl_types.all;
entity ID_EX_Seg is
port(
Clk : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
PC_Add : in vl_logic_vector(31 downto 0);
OverflowEn : in vl_logic;
cond... |
package A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean);
procedure PROC_B(I:in integer; O:out integer; Z:out boolean);
procedure PROC_C(I:in integer; O:out integer; Z:out boolean);
end package;
package body A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean) is
begin
... |
package A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean);
procedure PROC_B(I:in integer; O:out integer; Z:out boolean);
procedure PROC_C(I:in integer; O:out integer; Z:out boolean);
end package;
package body A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean) is
begin
... |
package A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean);
procedure PROC_B(I:in integer; O:out integer; Z:out boolean);
procedure PROC_C(I:in integer; O:out integer; Z:out boolean);
end package;
package body A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean) is
begin
... |
package A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean);
procedure PROC_B(I:in integer; O:out integer; Z:out boolean);
procedure PROC_C(I:in integer; O:out integer; Z:out boolean);
end package;
package body A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean) is
begin
... |
package A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean);
procedure PROC_B(I:in integer; O:out integer; Z:out boolean);
procedure PROC_C(I:in integer; O:out integer; Z:out boolean);
end package;
package body A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean) is
begin
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains con... |
-------------------------------------------------------------------------------
--
-- Title : half_adder_gates
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\M... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: soamem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ===================... |
constant I2CFSMLength : integer := 1295;
constant I2CFSMCfg : std_logic_vector(I2CFSMLength-1 downto 0) := "0001100000001000000001000001000101001100000000001000110011000110000000000000011100100011000000000100010000010100100000110000000000000010000100000001000010000000000000000100010001110110000100000000000100000... |
constant I2CFSMLength : integer := 1295;
constant I2CFSMCfg : std_logic_vector(I2CFSMLength-1 downto 0) := "0001100000001000000001000001000101001100000000001000110011000110000000000000011100100011000000000100010000010100100000110000000000000010000100000001000010000000000000000100010001110110000100000000000100000... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity roi_process is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY cpu_core_portb_int IS
END cpu_core_portb_int;
ARCHITECTURE behavior OF cpu_core_portb_int IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cpu_core
GENERIC( instruction_file : string);
PORT(
... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
entity rc5_key is
port( clr : in std_logic;
clk : in std_logic;
key : in std_logic_vector(127 downto 0);
key_vld : in std_logic;
skey : out rc5_rom_26;
key_rdy :... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
entity FSM is
port (
Clk, Rst, Enter : in std_logic;
Operacao: in std_logic_vector(1 downto 0);
Sel: out std_logic_vector(1 downto 0);
Enable_1, Enable_2: out std_logic
);
end FSM;
architecture FSM_beh of FSM is
type states is (S0, S1, S2, S3, S4, ... |
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <ludovic.noury@esiee.fr>
--
-- This program is free software: you can redistribute it and/or
-- modify it under th... |
-- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Soft... |
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Soft... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:06:19 11/21/2013
-- Design Name:
-- Module Name: Mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' withou... |
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