content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/27/2017 08:36:56 AM
-- Module Name: regfile - Behavioral
-- Description:
-- Additional Comments:
----------------------------------------------------------------------------------
librar... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity test2 is
port (
tx : out std_logic);
end entity;
architecture tb of test2 is
begin
process
-- variable boolobj: boolean; -- ADDED
procedure transmit(data: std_logic_vector; signal tx: out std_logic) is
variable norm: std_logic_vec... |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' T... |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.PhoenixPackage.all;
package TablePackage is
constant NREG : integer := 6;
constant MEMORY_SIZE : integer := NREG;
constant NBITS : integer := 4;
constant CELL_SIZE : integer := 2*NPORT+4*NBITS;
subtype cell is std_logic_vector(CELL_SIZE-1 ... |
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 11:09:53 05/16/2016
-----------... |
library verilog;
use verilog.vl_types.all;
entity MEM_stage is
port(
rst : in vl_logic;
DataMemoryAddress: in vl_logic_vector(15 downto 0);
DataMemoryWriteData: in vl_logic_vector(15 downto 0);
DataMemoryWriteEnable: in vl_logic;
DataMemoryOut : ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity stub_ram_int is
Port ( memAddress : in STD_LOGIC_VECTOR (26 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0);
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
------- binary to bcd converter
------- Uses the ADD-3 (or Double-Dabble) algorithm
------- 12 bit std_logic_vector in, 16 bit std_logic_vector out (4 BCD digits)
------- USAGE: BCD <= to_bcd(BIN);
-------
------- include this text at the beginning of the architecture body, after the signal declarations
-------
-----... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:01 01/15/2015
-- Design Name:
-- Module Name: componant_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:01 01/15/2015
-- Design Name:
-- Module Name: componant_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies... |
-- NEED RESULT: ARCH00117.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00117: One transport transaction occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00117: Old transacti... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-----------H----H--X----X-----CCCCC----22222----0000-----0000------11----------
----------H----H----X-X-----C--------------2---0----0---0----0--1--1---------... |
architecture RTL of FIFO is
begin
process
begin
a <= b; -- level 2
ab <= xy; -- level 2
-- level 2
if (a = b) then -- level 2
z <= y; -- level 3
-- level 2
elsif (a + b -c = z) then -- level 2
z <= ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_24 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_24;
architecture BEHAVIO... |
entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is... |
entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is... |
entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is... |
entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is... |
entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:34:27 2007
-- cmd: /home/wig/work/MIX/mix_0.pl ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-conf-c... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
--------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------... |
--Copyright 2017 Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2.... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.myDeclare.all;
ENTITY TB_com_scheduler IS
END TB_com_scheduler;
ARCH... |
-- $Id: rlinktblib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: rlinktblib
-- Description: rlink test envir... |
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity alu is
port(
a, b: in std_logic_vector(31 downto 0);
alucontrol: in std_logic_vector(2 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic
);
end entity;
architecture behavi... |
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 02/04/2018 01:13:09 PM
-- Module Name: control - Behavioral
-- Description: Control unit for RISCV core
--
-- Additional Comments:
--
----------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SeqDetFSM_Tb is
end SeqDetFSM_Tb;
architecture Stimulus of SeqDetFSM_Tb is
signal s_clk : std_logic;
signal s_xin, s_yout : std_logic;
begin
uut: entity work.SeqDetFSM(MealyArch)
port map(clk => s_clk,
xin => s_xin,
yout=> s_yout);
clk_proc: pr... |
entity attr14 is
end entity;
architecture test of attr14 is
type rec is record
x : bit_vector(7 downto 0);
end record;
signal s : rec;
signal t : bit_vector(3 downto 0);
begin
p1: process is
begin
wait for 1 ns;
s.x(4) <= '1';
wait for 1 ns;
s.x(4) <= '... |
--
-- Inferrable Synchronous SRAM for XST synthesis
--
-- Version : 0220
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--... |
--
-- Inferrable Synchronous SRAM for XST synthesis
--
-- Version : 0220
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00444
--
-- AUTHOR:
--
-- A. Wilm... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library hdl_library_CommonFunctions;
--use hdl_library_CommonFunctions.CommonFunctions.all;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.MathHelpers.all;
entity ClockGenerator is
generi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity somadorSubtrator is
Port ( a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
b0 : in STD_LOGIC;
b1 : in STD_LOGIC;
b2 : in STD_LOGIC;
sel : in STD_LOGIC;
s0 : out STD_LOGIC;
... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
entity repro is
end;
architecture behav of repro
is
procedure test (l : natural) is
variable v : bit_vector (l - 1 downto 0);
begin
assert v (l / 2) = '0';
assert v (0) = '0';
assert v (l - 1) = '0';
end test;
begin
process
begin
test (128 * 1024);
wait;
end process;
end... |
-- $Id: serport_xontx.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Contains a testbench for the generic UART entity.
--
-- To Do:
-- -
--
-- ... |
---------------------------------------------------------------------
-- TITLE: Memory Controller
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 1/31/01
-- FILENAME: mem_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hardware_tester_fsm is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.7
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : gtpa1_dual_wrapper.vhd
-- /___/ /\ ... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Pipeline_Polynomial_Calc_v3
-- Module Name: Pipeline_Polynomial_Calc_v3
-- Proj... |
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Containing a bridge between a RapidIO network and a Wishbone bus. Packets
-- NWR... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
... |
-------------------------------------------------------------------------------
-- Title : AHB2HPI bus bridge
-- Project : LEON3MINI
-------------------------------------------------------------------------------
-- $Id: ahb2hpi.vhd,v 1.23 2005/09/28 14:50:25 tame Mod $
------------------------------------... |
-------------------------------------------------------------------------------
-- Title : AHB2HPI bus bridge
-- Project : LEON3MINI
-------------------------------------------------------------------------------
-- $Id: ahb2hpi.vhd,v 1.23 2005/09/28 14:50:25 tame Mod $
------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_splitter is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS:natural := 6
);
port (
number_in: in std_logic_vector(TOTAL_BITS-1 downto 0);
sign_out: out std_logic;
exp_out: out std_logic_vector(EXP_BITS-1 downto 0);
mant_out:... |
-------------------------------------------------------------------------------
-- Title : BPM Mixer
-- Project :
-------------------------------------------------------------------------------
-- File : mixer.vhd
-- Author : Gustavo BM Bruno
-- Company : LNLS - CNPEM
-- Created : 2014-01-21
-- ... |
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineer... |
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineer... |
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineer... |
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineer... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
-- Failures bel... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:12 09/26/2017
-- Design Name:
-- Module Name: firstrpart - arqfirstrpart
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_na.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =======================... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_na.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =======================... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
library ieee;
use ieee.std_logic_1164.all;
entity zeroReg is
port(
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0)
);
end zeroReg;
architecture bhv of zeroR... |
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2)... |
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