content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ASCII_LUT is
port( ASCIIin : in std_logic_vector(7 downto 0);
SEL_out : out std_logic_vector(6 downto 0));
end ASCII_LUT;
architecture Behavioral of ASCII_LUT is
begin
COLORTEMP : process (ASCIIin)
begin
end process COLORTEMP;
with ASCIIin select
SEL_out... |
----------------------------------------------------------------------------------------------
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS... |
----------------------------------------------------------------------------------------------
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS... |
----------------------------------------------------------------------------------------------
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : Syst... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
entity sub_nat is
port (
clk : in std_logic;
a : in natural;
b : out natural
);
end sub_nat;
architecture rtl of sub_nat is
begin
process(clk)
begin
if rising_edge(clk) then
b <= a;
end if;
end process;
end rtl;
library ieee;
use ieee.st... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This fi... |
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal i : std_logic_vector (7 downto 0);
signal o : std_logic_vector (3 downto 0);
begin
dut: entity work.ent
port map (i, o);
process
begin
i <= x"b6";
wait for 1 ns;
assert o = x"b" se... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
entity noise_generator is
generic (
g_type : string := "Fibonacci"; -- can also be "Galois"
g_polynom : std_logic_vector := X"E10000";
g_fixed_polynom : boolean := true;
g_seed : std_logic_vector := X"000001" );
port (
clo... |
library ieee;
use ieee.std_logic_1164.all;
entity noise_generator is
generic (
g_type : string := "Fibonacci"; -- can also be "Galois"
g_polynom : std_logic_vector := X"E10000";
g_fixed_polynom : boolean := true;
g_seed : std_logic_vector := X"000001" );
port (
clo... |
library ieee;
use ieee.std_logic_1164.all;
entity noise_generator is
generic (
g_type : string := "Fibonacci"; -- can also be "Galois"
g_polynom : std_logic_vector := X"E10000";
g_fixed_polynom : boolean := true;
g_seed : std_logic_vector := X"000001" );
port (
clo... |
library ieee;
use ieee.std_logic_1164.all;
entity noise_generator is
generic (
g_type : string := "Fibonacci"; -- can also be "Galois"
g_polynom : std_logic_vector := X"E10000";
g_fixed_polynom : boolean := true;
g_seed : std_logic_vector := X"000001" );
port (
clo... |
library ieee;
use ieee.std_logic_1164.all;
entity noise_generator is
generic (
g_type : string := "Fibonacci"; -- can also be "Galois"
g_polynom : std_logic_vector := X"E10000";
g_fixed_polynom : boolean := true;
g_seed : std_logic_vector := X"000001" );
port (
clo... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity test is
constant a : b :=
<<constant @foo.bar.baz : t>>;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity e is
end entity e;
architecture a of e is
signal operator_for_cmp : std_logic_vector(7 downto 0) := (others => 'X');
begin
process (operator_for_cmp) is
begin
case operator_for_cmp is
when "00000000" =>
null;
when "00000001" =>
null;
when "00000002" => --... |
library ieee;
use ieee.std_logic_1164.all;
entity e is
end entity e;
architecture a of e is
signal operator_for_cmp : std_logic_vector(7 downto 0) := (others => 'X');
begin
process (operator_for_cmp) is
begin
case operator_for_cmp is
when "00000000" =>
null;
when "00000001" =>
null;
when "00000002" => --... |
library ieee;
use ieee.std_logic_1164.all;
entity e is
end entity e;
architecture a of e is
signal operator_for_cmp : std_logic_vector(7 downto 0) := (others => 'X');
begin
process (operator_for_cmp) is
begin
case operator_for_cmp is
when "00000000" =>
null;
when "00000001" =>
null;
when "00000002" => --... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
--! @file frame_tx_tb.vhd
--! @brief Frame Transmit Handler testbench
--! @author Scott Teal (Scott@Teals.org)
--! @date 2013-11-06
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with th... |
-- title: Testbench for VCORDIC
-- author: Sebastian Weiss
-- last change: 03.12.14
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity euler_tb is
end entity;
architecture behavioral of euler_tb is
constant A : natural := 16;
constan... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_generator_avalon is
generic(
datawidth : natural := 32;
freq_core : natural := 100_000_000;
freq_pwm : natural := 10_000
);
port(
-- avalon clk interface, there is no need for a reset
clk : in std_logic;
... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D8_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D8_C1;
architecture D8_C1 of D8_C1 is
begin
process(rst,clk)
variable dem:integer range 0 to 9;
begin
if (rst='1') then dem:=0;
elsif (rising_edg... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:23 10/06/2010
-- Design Name:
-- Module Name: Cont0a9 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:23 10/06/2010
-- Design Name:
-- Module Name: Cont0a9 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:23 10/06/2010
-- Design Name:
-- Module Name: Cont0a9 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 20... |
library std;
use std.textio.all;
entity test is end entity;
architecture a of test is
component wrapper is end component;
begin
inst :if false generate inst :wrapper; end generate;
process
variable l :line;
begin
write(l, string'("OK")); writeline(output, l); wait;
end process;
end architecture;
package some_... |
library std;
use std.textio.all;
entity test is end entity;
architecture a of test is
component wrapper is end component;
begin
inst :if false generate inst :wrapper; end generate;
process
variable l :line;
begin
write(l, string'("OK")); writeline(output, l); wait;
end process;
end architecture;
package some_... |
library std;
use std.textio.all;
entity test is end entity;
architecture a of test is
component wrapper is end component;
begin
inst :if false generate inst :wrapper; end generate;
process
variable l :line;
begin
write(l, string'("OK")); writeline(output, l); wait;
end process;
end architecture;
package some_... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:35 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- $Id: sys_tst_rlink_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_s3 - syn
-- Description: ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_ok_8_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id:... |
-------------------------------------------------------------------------------
--
-- Title : local_link_sink.vhd - part of the Groucher simulation environment
--
-- Description : This code models the behavior of a local link sink device
--
-- Files: writes the received data and control into a ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ArithmeticalRightShifter_x16 is
Port (
input : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end ArithmeticalRightShifter_x16;
architecture skeleton of ArithmeticalRightShifter_x16 is
begin
process(input) is
begin
fo... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
---------------------------------------------------------------------------------------------------
--
-- Title : Bus End Point
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
-------------------------------------------------------------------------------------------------... |
---------------------------------------------------------------------------------------------------
--
-- Title : Bus End Point
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
-------------------------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/18/2016 01:10:56 PM
-- Design Name:
-- Module Name: app - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- R... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------------------------
entity lut_3inadd is
generic(
NUM_BITS: positive := 113
);
port (
I: in STD_LOGIC_VECTOR(... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:01:45 03/21/2016
-- Design Name:
-- Module Name: TOP_LEVEL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
library ieee;
use ieee.std_logic_1164.all;
entity foo is
port (
input : in std_logic_vector(7 downto 0);
output_ok : out std_logic_vector(7 downto 0);
output_error : out std_logic_vector(7 downto 0)
);
end foo;
architecture foo of foo is
signal null_vector : std_logic_vector(-1 downto 0) ... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux2x3 is
port(S : in std_logic;
X,Y : in std_logic_vector(2 downto 0);
O : out std_logic_vector(2 downto 0));
end mux2x3;
architecture Logic of mux2x3 is
begin
with S select O <= X when '0',
Y when '1',
... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux2x3 is
port(S : in std_logic;
X,Y : in std_logic_vector(2 downto 0);
O : out std_logic_vector(2 downto 0));
end mux2x3;
architecture Logic of mux2x3 is
begin
with S select O <= X when '0',
Y when '1',
... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux2x3 is
port(S : in std_logic;
X,Y : in std_logic_vector(2 downto 0);
O : out std_logic_vector(2 downto 0));
end mux2x3;
architecture Logic of mux2x3 is
begin
with S select O <= X when '0',
Y when '1',
... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux2x3 is
port(S : in std_logic;
X,Y : in std_logic_vector(2 downto 0);
O : out std_logic_vector(2 downto 0));
end mux2x3;
architecture Logic of mux2x3 is
begin
with S select O <= X when '0',
Y when '1',
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_c1571 is
port (
io_irq : out std_logic );
end entity;
architecture harness o... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief 32-bits RAM implementation based on registers
--------------------------------------------------... |
entity test is
type test is (foo);
type test is (bar);
begin end;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Ha... |
architecture rtl of fifo is
variable sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),
element5(
elementE
(3 downto
... |
-- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <n3vu0r@qu1x.org>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 Novem... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity max is
generic(
A : positive := 5;
B : positive := 7
);
port(
dummy : std_logic
);
end max;
architecture test of max is
constant cst : positive := maximum(A,B);
begin
assert cst = 7 severity error;
end architecture;
|
-- Execute
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity Execute is
port (
pc_plus_4 : in addr_t;
regReadData1, regReadData2 : in word_t;
branch_addr : out addr_t;
branch_in : in ctrl_t;
shift_in, alusrc_in : in ctrl_t;
aluop_in : in alu_... |
------------------------------------------------------------------------------
---- ----
---- Dual Port RAM that maps to a Xilinx BRAM ----
---- ----
----... |
--auto-generated by gen_lmcores.py. Don't hand-edit please
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity xwb_lm32 is
generic(g_profile: string;
g_reset_vector: std_logic_vector(31 downto 0) := x"00000000");
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic... |
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of ... |
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