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-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015 - 2016, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: iopad_ddr, iopad_ddrv, iopad_ddrvv -- File: iopad_ddr.vhd -- Author: Jan Andersson - Aeroflex Gaisler -- Description: Wrapper that instantiates an iopad connected to DDR register. -- Special case for easic90 tech since this tech requires that -- oe is directly connected between DDR register and pad. ------------------------------------------------------------------------------ library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allddr.all; use techmap.allpads.all; entity iopad_ddr is generic ( tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := x33v; strength : integer := 12; oepol : integer := 0); port ( pad : inout std_ulogic; i1, i2 : in std_ulogic; -- Input H and L en : in std_ulogic; -- Output enable o1, o2 : out std_ulogic; -- Output H and L c1, c2 : in std_ulogic; ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic); end; architecture rtl of iopad_ddr is signal oe, oen, d, q : std_ulogic; begin def: if (tech /= easic90) generate p : iopad generic map (tech, level, slew, voltage, strength, oepol) port map (pad, q, en, d); ddrregi : ddr_ireg generic map (tech) port map (o1, o2, c1, c2, ce, d, r, s); ddrrego : ddr_oreg generic map (tech) port map (q, c1, c2, ce, i1, i2, r, s); oe <= '0'; oen <= '0'; -- Not used in this configuration end generate def; nex : if (tech = easic90) generate oen <= not en when oepol /= padoen_polarity(tech) else en; p : nextreme_iopad generic map (level, slew, voltage, strength) port map (pad, q, oe, d); ddrregi : nextreme_iddr_reg port map (ck => c1, d => d, qh => o1, ql => o2, rstb => r); ddrrego : nextreme_oddr_reg port map (ck => c1, dh => i1, dl => i2, doe => oen, q => q, oe => oe, rstb => r); end generate; end; library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; entity iopad_ddrv is generic ( tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := x33v; strength : integer := 12; width : integer := 1; oepol : integer := 0); port ( pad : inout std_logic_vector(width-1 downto 0); i1, i2 : in std_logic_vector(width-1 downto 0); en : in std_ulogic; o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic; ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic); end; architecture rtl of iopad_ddrv is begin v : for j in width-1 downto 0 generate x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol) port map (pad(j), i1(j), i2(j), en, o1(j), o2(j), c1, c2, ce, r, s); end generate; end; library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; entity iopad_ddrvv is generic ( tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := x33v; strength : integer := 12; width : integer := 1; oepol : integer := 0); port ( pad : inout std_logic_vector(width-1 downto 0); i1, i2 : in std_logic_vector(width-1 downto 0); en : in std_logic_vector(width-1 downto 0); o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic; ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic); end; architecture rtl of iopad_ddrvv is begin v : for j in width-1 downto 0 generate x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol) port map (pad(j), i1(j), i2(j), en(j), o1(j), o2(j), c1, c2, ce, r, s); end generate; end;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ -- Entity: memctrl -- File: memctrl.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: Memory controller package ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.memctrl.all; package memoryctrl is component mctrl generic ( hindex : integer := 0; pindex : integer := 0; romaddr : integer := 16#000#; rommask : integer := 16#E00#; ioaddr : integer := 16#200#; iomask : integer := 16#E00#; ramaddr : integer := 16#400#; rammask : integer := 16#C00#; paddr : integer := 0; pmask : integer := 16#fff#; wprot : integer := 0; invclk : integer := 0; fast : integer := 0; romasel : integer := 28; sdrasel : integer := 29; srbanks : integer := 4; ram8 : integer := 0; ram16 : integer := 0; sden : integer := 0; sepbus : integer := 0; sdbits : integer := 32; sdlsb : integer := 2; oepol : integer := 0; syncrst : integer := 0; pageburst : integer := 0; scantest : integer := 0; mobile : integer := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; memi : in memory_in_type; memo : out memory_out_type; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; wpo : in wprot_out_type; sdo : out sdram_out_type ); end component; end;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ha00.all; entity topha00 is port( A0: in std_logic ; B0: in std_logic ; S0: out std_logic ; C0: out std_logic ); end; architecture topha0 of topha00 is begin U0: and00 port map (Aa => A0, Ba => B0, Ya => C0); U1: xor00 port map (Ax => A0, Bx => B0, Yx => S0); end topha0;
-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013 -- Date : Sat Mar 15 17:45:54 2014 -- Host : macbook running 64-bit Arch Linux -- Command : write_vhdl -force -mode funcsim -- /home/keith/Documents/VHDL-lib/top/lab_2/part_1/build/lab2_part1.srcs/sources_1/ip/clk_video/clk_video_funcsim.vhdl -- Design : clk_video -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity clk_videoclk_video_clk_wiz is port ( locked : out STD_LOGIC; clk_193MHz : out STD_LOGIC; clk_100MHz : in STD_LOGIC ); end clk_videoclk_video_clk_wiz; architecture STRUCTURE of clk_videoclk_video_clk_wiz is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal clk_100MHz_clk_video : STD_LOGIC; signal clk_193MHz_clk_video : STD_LOGIC; signal clkfbout_buf_clk_video : STD_LOGIC; signal clkfbout_clk_video : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute box_type : string; attribute box_type of clkf_buf : label is "PRIMITIVE"; attribute box_type of clkin1_bufg : label is "PRIMITIVE"; attribute box_type of clkout1_buf : label is "PRIMITIVE"; attribute box_type of mmcm_adv_inst : label is "PRIMITIVE"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); clkf_buf: unisim.vcomponents.BUFG port map ( I => clkfbout_clk_video, O => clkfbout_buf_clk_video ); clkin1_bufg: unisim.vcomponents.BUFG port map ( I => clk_100MHz, O => clk_100MHz_clk_video ); clkout1_buf: unisim.vcomponents.BUFG port map ( I => clk_193MHz_clk_video, O => clk_193MHz ); mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV generic map( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT_F => 30.875000, CLKFBOUT_PHASE => 0.000000, CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 10.000000, CLKIN2_PERIOD => 0.000000, CLKOUT0_DIVIDE_F => 4.000000, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, CLKOUT1_DIVIDE => 1, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, CLKOUT2_DIVIDE => 1, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, CLKOUT2_USE_FINE_PS => false, CLKOUT3_DIVIDE => 1, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, CLKOUT3_USE_FINE_PS => false, CLKOUT4_CASCADE => false, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, CLKOUT4_USE_FINE_PS => false, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, CLKOUT5_USE_FINE_PS => false, CLKOUT6_DIVIDE => 1, CLKOUT6_DUTY_CYCLE => 0.500000, CLKOUT6_PHASE => 0.000000, CLKOUT6_USE_FINE_PS => false, COMPENSATION => "BUF_IN", DIVCLK_DIVIDE => 4, IS_CLKINSEL_INVERTED => '0', IS_PSEN_INVERTED => '0', IS_PSINCDEC_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.010000, REF_JITTER2 => 0.000000, SS_EN => "FALSE", SS_MODE => "CENTER_HIGH", SS_MOD_PERIOD => 10000, STARTUP_WAIT => false ) port map ( CLKFBIN => clkfbout_buf_clk_video, CLKFBOUT => clkfbout_clk_video, CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, CLKIN1 => clk_100MHz_clk_video, CLKIN2 => \<const0>\, CLKINSEL => \<const1>\, CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => clk_193MHz_clk_video, CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, DADDR(6) => \<const0>\, DADDR(5) => \<const0>\, DADDR(4) => \<const0>\, DADDR(3) => \<const0>\, DADDR(2) => \<const0>\, DADDR(1) => \<const0>\, DADDR(0) => \<const0>\, DCLK => \<const0>\, DEN => \<const0>\, DI(15) => \<const0>\, DI(14) => \<const0>\, DI(13) => \<const0>\, DI(12) => \<const0>\, DI(11) => \<const0>\, DI(10) => \<const0>\, DI(9) => \<const0>\, DI(8) => \<const0>\, DI(7) => \<const0>\, DI(6) => \<const0>\, DI(5) => \<const0>\, DI(4) => \<const0>\, DI(3) => \<const0>\, DI(2) => \<const0>\, DI(1) => \<const0>\, DI(0) => \<const0>\, DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, DWE => \<const0>\, LOCKED => locked, PSCLK => \<const0>\, PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, PSEN => \<const0>\, PSINCDEC => \<const0>\, PWRDWN => \<const0>\, RST => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity clk_video is port ( clk_100MHz : in STD_LOGIC; clk_193MHz : out STD_LOGIC; locked : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of clk_video : entity is true; attribute core_generation_info : string; attribute core_generation_info of clk_video : entity is "clk_video,clk_wiz_v5_1,{component_name=clk_video,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; end clk_video; architecture STRUCTURE of clk_video is begin U0: entity work.clk_videoclk_video_clk_wiz port map ( clk_100MHz => clk_100MHz, clk_193MHz => clk_193MHz, locked => locked ); end STRUCTURE;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity rounder_tb is end entity; architecture rounder_tb_arq of rounder_tb is signal man_in: std_logic_vector(7 downto 0) := (others => '0'); signal exp_in: std_logic_vector(2 downto 0) := (others => '0'); signal man_out: std_logic_vector(5 downto 0) := (others => '0'); signal exp_out: std_logic_vector(2 downto 0) := (others => '0'); signal exponent_addition_cout: std_logic := '0'; component rounder is generic( TOTAL_BITS:natural := 23; EXP_BITS: natural := 6 ); port ( exponent_addition_cout: in std_logic; man_in: in std_logic_vector(TOTAL_BITS - EXP_BITS downto 0); exp_in: in std_logic_vector(EXP_BITS - 1 downto 0); man_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0); exp_out : out std_logic_vector(EXP_BITS - 1 downto 0) ); end component; for rounder_0: rounder use entity work.rounder; begin rounder_0: rounder generic map(TOTAL_BITS => 10, EXP_BITS => 3) port map( exponent_addition_cout => exponent_addition_cout, man_in => man_in, exp_in => exp_in, man_out => man_out, exp_out => exp_out ); process type pattern_type is record mi : std_logic_vector(7 downto 0); ei : std_logic_vector(2 downto 0); mo : std_logic_vector(5 downto 0); ec : std_logic; eo : std_logic_vector(2 downto 0); end record; -- The patterns to apply. type pattern_array is array (natural range<>) of pattern_type; constant patterns : pattern_array := ( ("00000000","000","000000",'0',"000"), ("11111111","000","000000",'0',"000"), ("10000001","110","000000",'0',"100") ); begin for i in patterns'range loop -- Set the inputs. man_in <= patterns(i).mi; exp_in <= patterns(i).ei; exponent_addition_cout <= patterns(i).ec; -- Wait for the results. wait for 1 ns; -- Check the outputs. assert man_out = patterns(i).mo report "BAD MANTISSA: " & integer'image(to_integer(unsigned(man_out))) severity error; assert exp_out = patterns(i).eo report "BAD EXPONENT: " & integer'image(to_integer(unsigned(exp_out))) severity error; end loop; assert false report "end of test" severity note; wait; end process; end;
entity sub is port ( a : in bit_vector(1 downto 0); b, c : out bit_vector(1 downto 0); d : out bit_vector(1 downto 0) := "00" ); end entity; architecture test of sub is begin (b(0), c(0)) <= a; (b(1), c(1)) <= a; d(1) <= '1'; end architecture; ------------------------------------------------------------------------------- entity elab18 is end entity; architecture test of elab18 is signal a1, b1, a2, b2 : bit_vector(1 downto 0); begin sub1_i: entity work.sub port map ( a => a1, b => b1, c => open ); process is begin a1 <= "01"; wait for 1 ns; assert b1 = "00"; wait; end process; sub2_i: entity work.sub port map ( a => a2, b => b2 ); process is begin a2 <= "10"; wait for 1 ns; assert b2 = "11"; wait; end process; end architecture;
entity sub is port ( a : in bit_vector(1 downto 0); b, c : out bit_vector(1 downto 0); d : out bit_vector(1 downto 0) := "00" ); end entity; architecture test of sub is begin (b(0), c(0)) <= a; (b(1), c(1)) <= a; d(1) <= '1'; end architecture; ------------------------------------------------------------------------------- entity elab18 is end entity; architecture test of elab18 is signal a1, b1, a2, b2 : bit_vector(1 downto 0); begin sub1_i: entity work.sub port map ( a => a1, b => b1, c => open ); process is begin a1 <= "01"; wait for 1 ns; assert b1 = "00"; wait; end process; sub2_i: entity work.sub port map ( a => a2, b => b2 ); process is begin a2 <= "10"; wait for 1 ns; assert b2 = "11"; wait; end process; end architecture;
entity sub is port ( a : in bit_vector(1 downto 0); b, c : out bit_vector(1 downto 0); d : out bit_vector(1 downto 0) := "00" ); end entity; architecture test of sub is begin (b(0), c(0)) <= a; (b(1), c(1)) <= a; d(1) <= '1'; end architecture; ------------------------------------------------------------------------------- entity elab18 is end entity; architecture test of elab18 is signal a1, b1, a2, b2 : bit_vector(1 downto 0); begin sub1_i: entity work.sub port map ( a => a1, b => b1, c => open ); process is begin a1 <= "01"; wait for 1 ns; assert b1 = "00"; wait; end process; sub2_i: entity work.sub port map ( a => a2, b => b2 ); process is begin a2 <= "10"; wait for 1 ns; assert b2 = "11"; wait; end process; end architecture;
entity sub is port ( a : in bit_vector(1 downto 0); b, c : out bit_vector(1 downto 0); d : out bit_vector(1 downto 0) := "00" ); end entity; architecture test of sub is begin (b(0), c(0)) <= a; (b(1), c(1)) <= a; d(1) <= '1'; end architecture; ------------------------------------------------------------------------------- entity elab18 is end entity; architecture test of elab18 is signal a1, b1, a2, b2 : bit_vector(1 downto 0); begin sub1_i: entity work.sub port map ( a => a1, b => b1, c => open ); process is begin a1 <= "01"; wait for 1 ns; assert b1 = "00"; wait; end process; sub2_i: entity work.sub port map ( a => a2, b => b2 ); process is begin a2 <= "10"; wait for 1 ns; assert b2 = "11"; wait; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; use work.aua_types.all; entity aua_tb is end aua_tb; architecture aua_test of aua_tb is component aua port ( clk_in : in std_logic; reset_pin : in std_logic; switch_pins : in std_logic_vector(15 downto 0); led_pins : out std_logic_vector(15 downto 0); digit0_pins : out std_logic_vector(6 downto 0); digit1_pins : out std_logic_vector(6 downto 0); digit2_pins : out std_logic_vector(6 downto 0); digit3_pins : out std_logic_vector(6 downto 0); digit4_pins : out std_logic_vector(6 downto 0); digit5_pins : out std_logic_vector(6 downto 0); sram_addr : out std_logic_vector(RAM_ADDR_SIZE-1 downto 0); sram_dq : inout word_t; sram_we : out std_logic; -- sram_oe : out std_logic; sram_ub : out std_logic; sram_lb : out std_logic; -- sram_ce : out std_logic txd : out std_logic; rxd : in std_ulogic --~ ncts : in std_logic; --~ nrts : out std_logic ); end component; signal clk : std_logic; signal reset_pin : std_logic; signal switch_pins : std_logic_vector(15 downto 0); signal led_pins : std_logic_vector(15 downto 0); signal digit0_pins : std_logic_vector(6 downto 0); signal digit1_pins : std_logic_vector(6 downto 0); signal digit2_pins : std_logic_vector(6 downto 0); signal digit3_pins : std_logic_vector(6 downto 0); signal digit4_pins : std_logic_vector(6 downto 0); signal digit5_pins : std_logic_vector(6 downto 0); signal sram_addr : std_logic_vector(RAM_ADDR_SIZE-1 downto 0); signal sram_dq : word_t; signal sram_we : std_logic; signal sram_ub : std_logic; signal sram_lb : std_logic; signal txd : std_logic; signal rxd : std_logic; constant freq: natural := 70000000; constant clk_tick: natural := 1000000000/freq; constant uart_baud: natural := 115200; constant uart_clks: natural := freq/uart_baud; begin uart: process procedure icwait(cycles : natural) is begin for i in 1 to cycles loop wait until clk = '0' and clk'event; end loop; end; begin rxd <= '0'; icwait(uart_clks*2); rxd <= '1'; icwait(uart_clks); rxd <= '0'; icwait(uart_clks*2); rxd <= '1'; icwait(uart_clks*2); rxd <= '0'; icwait(uart_clks*2); rxd <= '1'; icwait(uart_clks*2); end process; --~ aua1: configuration work.aua_cache aua1: aua port map ( clk_in => clk, reset_pin => reset_pin, switch_pins => switch_pins, led_pins => led_pins, digit0_pins => digit0_pins, digit1_pins => digit1_pins, digit2_pins => digit2_pins, digit3_pins => digit3_pins, digit4_pins => digit4_pins, digit5_pins => digit5_pins, sram_addr => sram_addr, sram_dq => sram_dq, sram_we => sram_we, sram_ub => sram_ub, sram_lb => sram_lb, txd => txd, rxd => rxd ); CLKGEN: process begin clk <= '1'; wait for 10 ns; clk <= '0'; wait for 10 ns; end process CLKGEN; TEST: process procedure icwait(cycles : natural) is begin for i in 1 to cycles loop wait until clk = '0' and clk'event; end loop; end; begin reset_pin <= '0'; switch_pins <= x"ffff"; sram_dq <= (others => '0'); --~ rxd <= '0'; icwait(2); reset_pin <= '1'; icwait(9000); assert false report "sim finish" SEVERITY failure; end process TEST; end aua_test;
--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2015 -- Module Name: ALU_TB -- Project Name: ALU -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: ALU Test Bench --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; ENTITY ALU_tb_vhd IS END ALU_tb_vhd; ARCHITECTURE behavior OF ALU_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ALU PORT( CLK : in STD_LOGIC; RA : in STD_LOGIC_VECTOR(7 downto 0); RB : in STD_LOGIC_VECTOR(7 downto 0); OPCODE : in STD_LOGIC_VECTOR(3 downto 0); CCR : out STD_LOGIC_VECTOR(3 downto 0); ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0); LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; --Inputs SIGNAL CLK : STD_LOGIC := '0'; SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); --Outputs SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0); SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0); -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 --Condition Codes SIGNAL N : STD_LOGIC := '0'; SIGNAL Z : STD_LOGIC := '0'; SIGNAL V : STD_LOGIC := '0'; SIGNAL C : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ALU PORT MAP( CLK => CLK, RA => RA, RB => RB, OPCODE => OPCODE, CCR => CCR, ALU_OUT => ALU_OUT, LDST_OUT => LDST_OUT); -- Assign condition code bits N <= CCR(3); -- N - Negative Z <= CCR(2); -- Z - Zero V <= CCR(1); -- V - Overflow C <= CCR(0); -- C - Carry/Borrow -- Generate clock gen_Clock: process begin CLK <= '0'; wait for period; CLK <= '1'; wait for period; end process gen_Clock; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; report "Start ALU Test Bench" severity NOTE; ----- Register-Register Arithmetic Tests ----- RA <= "00000101"; -- 5 RB <= "00000011"; -- 3 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01100100"; -- 100 RB <= "00110010"; -- 50 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END Arithmetic Tests ----- ----- CCR Tests ----- RA <= "00000000"; RB <= "00000000"; OPCODE <= "0000"; wait for period; assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000001"; RB <= "11111111"; OPCODE <= "0000"; wait for period; assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000000"; RB <= "00000001"; OPCODE <= "0001"; wait for period; assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "11111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END CCR Tests ----- -- Mem Test -- OPCODE <= "1001"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= X"16"; OPCODE <= "1010"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "1001"; wait for period; assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; -- END Mem Test -- report "Finish ALU Test Bench" severity NOTE; wait; -- will wait forever END PROCESS; END;
--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2015 -- Module Name: ALU_TB -- Project Name: ALU -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: ALU Test Bench --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; ENTITY ALU_tb_vhd IS END ALU_tb_vhd; ARCHITECTURE behavior OF ALU_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ALU PORT( CLK : in STD_LOGIC; RA : in STD_LOGIC_VECTOR(7 downto 0); RB : in STD_LOGIC_VECTOR(7 downto 0); OPCODE : in STD_LOGIC_VECTOR(3 downto 0); CCR : out STD_LOGIC_VECTOR(3 downto 0); ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0); LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; --Inputs SIGNAL CLK : STD_LOGIC := '0'; SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); --Outputs SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0); SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0); -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 --Condition Codes SIGNAL N : STD_LOGIC := '0'; SIGNAL Z : STD_LOGIC := '0'; SIGNAL V : STD_LOGIC := '0'; SIGNAL C : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ALU PORT MAP( CLK => CLK, RA => RA, RB => RB, OPCODE => OPCODE, CCR => CCR, ALU_OUT => ALU_OUT, LDST_OUT => LDST_OUT); -- Assign condition code bits N <= CCR(3); -- N - Negative Z <= CCR(2); -- Z - Zero V <= CCR(1); -- V - Overflow C <= CCR(0); -- C - Carry/Borrow -- Generate clock gen_Clock: process begin CLK <= '0'; wait for period; CLK <= '1'; wait for period; end process gen_Clock; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; report "Start ALU Test Bench" severity NOTE; ----- Register-Register Arithmetic Tests ----- RA <= "00000101"; -- 5 RB <= "00000011"; -- 3 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01100100"; -- 100 RB <= "00110010"; -- 50 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END Arithmetic Tests ----- ----- CCR Tests ----- RA <= "00000000"; RB <= "00000000"; OPCODE <= "0000"; wait for period; assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000001"; RB <= "11111111"; OPCODE <= "0000"; wait for period; assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000000"; RB <= "00000001"; OPCODE <= "0001"; wait for period; assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "11111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END CCR Tests ----- -- Mem Test -- OPCODE <= "1001"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= X"16"; OPCODE <= "1010"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "1001"; wait for period; assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; -- END Mem Test -- report "Finish ALU Test Bench" severity NOTE; wait; -- will wait forever END PROCESS; END;
--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2015 -- Module Name: ALU_TB -- Project Name: ALU -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: ALU Test Bench --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; ENTITY ALU_tb_vhd IS END ALU_tb_vhd; ARCHITECTURE behavior OF ALU_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ALU PORT( CLK : in STD_LOGIC; RA : in STD_LOGIC_VECTOR(7 downto 0); RB : in STD_LOGIC_VECTOR(7 downto 0); OPCODE : in STD_LOGIC_VECTOR(3 downto 0); CCR : out STD_LOGIC_VECTOR(3 downto 0); ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0); LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; --Inputs SIGNAL CLK : STD_LOGIC := '0'; SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); --Outputs SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0); SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0); -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 --Condition Codes SIGNAL N : STD_LOGIC := '0'; SIGNAL Z : STD_LOGIC := '0'; SIGNAL V : STD_LOGIC := '0'; SIGNAL C : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ALU PORT MAP( CLK => CLK, RA => RA, RB => RB, OPCODE => OPCODE, CCR => CCR, ALU_OUT => ALU_OUT, LDST_OUT => LDST_OUT); -- Assign condition code bits N <= CCR(3); -- N - Negative Z <= CCR(2); -- Z - Zero V <= CCR(1); -- V - Overflow C <= CCR(0); -- C - Carry/Borrow -- Generate clock gen_Clock: process begin CLK <= '0'; wait for period; CLK <= '1'; wait for period; end process gen_Clock; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; report "Start ALU Test Bench" severity NOTE; ----- Register-Register Arithmetic Tests ----- RA <= "00000101"; -- 5 RB <= "00000011"; -- 3 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01100100"; -- 100 RB <= "00110010"; -- 50 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END Arithmetic Tests ----- ----- CCR Tests ----- RA <= "00000000"; RB <= "00000000"; OPCODE <= "0000"; wait for period; assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000001"; RB <= "11111111"; OPCODE <= "0000"; wait for period; assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000000"; RB <= "00000001"; OPCODE <= "0001"; wait for period; assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "11111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END CCR Tests ----- -- Mem Test -- OPCODE <= "1001"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= X"16"; OPCODE <= "1010"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "1001"; wait for period; assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; -- END Mem Test -- report "Finish ALU Test Bench" severity NOTE; wait; -- will wait forever END PROCESS; END;
--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2015 -- Module Name: ALU_TB -- Project Name: ALU -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: ALU Test Bench --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; ENTITY ALU_tb_vhd IS END ALU_tb_vhd; ARCHITECTURE behavior OF ALU_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ALU PORT( CLK : in STD_LOGIC; RA : in STD_LOGIC_VECTOR(7 downto 0); RB : in STD_LOGIC_VECTOR(7 downto 0); OPCODE : in STD_LOGIC_VECTOR(3 downto 0); CCR : out STD_LOGIC_VECTOR(3 downto 0); ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0); LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; --Inputs SIGNAL CLK : STD_LOGIC := '0'; SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); --Outputs SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0); SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0); -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 --Condition Codes SIGNAL N : STD_LOGIC := '0'; SIGNAL Z : STD_LOGIC := '0'; SIGNAL V : STD_LOGIC := '0'; SIGNAL C : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ALU PORT MAP( CLK => CLK, RA => RA, RB => RB, OPCODE => OPCODE, CCR => CCR, ALU_OUT => ALU_OUT, LDST_OUT => LDST_OUT); -- Assign condition code bits N <= CCR(3); -- N - Negative Z <= CCR(2); -- Z - Zero V <= CCR(1); -- V - Overflow C <= CCR(0); -- C - Carry/Borrow -- Generate clock gen_Clock: process begin CLK <= '0'; wait for period; CLK <= '1'; wait for period; end process gen_Clock; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; report "Start ALU Test Bench" severity NOTE; ----- Register-Register Arithmetic Tests ----- RA <= "00000101"; -- 5 RB <= "00000011"; -- 3 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01100100"; -- 100 RB <= "00110010"; -- 50 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END Arithmetic Tests ----- ----- CCR Tests ----- RA <= "00000000"; RB <= "00000000"; OPCODE <= "0000"; wait for period; assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000001"; RB <= "11111111"; OPCODE <= "0000"; wait for period; assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000000"; RB <= "00000001"; OPCODE <= "0001"; wait for period; assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "11111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END CCR Tests ----- -- Mem Test -- OPCODE <= "1001"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= X"16"; OPCODE <= "1010"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "1001"; wait for period; assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; -- END Mem Test -- report "Finish ALU Test Bench" severity NOTE; wait; -- will wait forever END PROCESS; END;
--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2015 -- Module Name: ALU_TB -- Project Name: ALU -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: ALU Test Bench --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; ENTITY ALU_tb_vhd IS END ALU_tb_vhd; ARCHITECTURE behavior OF ALU_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ALU PORT( CLK : in STD_LOGIC; RA : in STD_LOGIC_VECTOR(7 downto 0); RB : in STD_LOGIC_VECTOR(7 downto 0); OPCODE : in STD_LOGIC_VECTOR(3 downto 0); CCR : out STD_LOGIC_VECTOR(3 downto 0); ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0); LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; --Inputs SIGNAL CLK : STD_LOGIC := '0'; SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); --Outputs SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0); SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0); -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 --Condition Codes SIGNAL N : STD_LOGIC := '0'; SIGNAL Z : STD_LOGIC := '0'; SIGNAL V : STD_LOGIC := '0'; SIGNAL C : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ALU PORT MAP( CLK => CLK, RA => RA, RB => RB, OPCODE => OPCODE, CCR => CCR, ALU_OUT => ALU_OUT, LDST_OUT => LDST_OUT); -- Assign condition code bits N <= CCR(3); -- N - Negative Z <= CCR(2); -- Z - Zero V <= CCR(1); -- V - Overflow C <= CCR(0); -- C - Carry/Borrow -- Generate clock gen_Clock: process begin CLK <= '0'; wait for period; CLK <= '1'; wait for period; end process gen_Clock; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; report "Start ALU Test Bench" severity NOTE; ----- Register-Register Arithmetic Tests ----- RA <= "00000101"; -- 5 RB <= "00000011"; -- 3 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01100100"; -- 100 RB <= "00110010"; -- 50 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END Arithmetic Tests ----- ----- CCR Tests ----- RA <= "00000000"; RB <= "00000000"; OPCODE <= "0000"; wait for period; assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000001"; RB <= "11111111"; OPCODE <= "0000"; wait for period; assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000000"; RB <= "00000001"; OPCODE <= "0001"; wait for period; assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "11111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END CCR Tests ----- -- Mem Test -- OPCODE <= "1001"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= X"16"; OPCODE <= "1010"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "1001"; wait for period; assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; -- END Mem Test -- report "Finish ALU Test Bench" severity NOTE; wait; -- will wait forever END PROCESS; END;
--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2015 -- Module Name: ALU_TB -- Project Name: ALU -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: ALU Test Bench --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; ENTITY ALU_tb_vhd IS END ALU_tb_vhd; ARCHITECTURE behavior OF ALU_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ALU PORT( CLK : in STD_LOGIC; RA : in STD_LOGIC_VECTOR(7 downto 0); RB : in STD_LOGIC_VECTOR(7 downto 0); OPCODE : in STD_LOGIC_VECTOR(3 downto 0); CCR : out STD_LOGIC_VECTOR(3 downto 0); ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0); LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; --Inputs SIGNAL CLK : STD_LOGIC := '0'; SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); --Outputs SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0); SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0); -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 --Condition Codes SIGNAL N : STD_LOGIC := '0'; SIGNAL Z : STD_LOGIC := '0'; SIGNAL V : STD_LOGIC := '0'; SIGNAL C : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ALU PORT MAP( CLK => CLK, RA => RA, RB => RB, OPCODE => OPCODE, CCR => CCR, ALU_OUT => ALU_OUT, LDST_OUT => LDST_OUT); -- Assign condition code bits N <= CCR(3); -- N - Negative Z <= CCR(2); -- Z - Zero V <= CCR(1); -- V - Overflow C <= CCR(0); -- C - Carry/Borrow -- Generate clock gen_Clock: process begin CLK <= '0'; wait for period; CLK <= '1'; wait for period; end process gen_Clock; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; report "Start ALU Test Bench" severity NOTE; ----- Register-Register Arithmetic Tests ----- RA <= "00000101"; -- 5 RB <= "00000011"; -- 3 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01100100"; -- 100 RB <= "00110010"; -- 50 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END Arithmetic Tests ----- ----- CCR Tests ----- RA <= "00000000"; RB <= "00000000"; OPCODE <= "0000"; wait for period; assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000001"; RB <= "11111111"; OPCODE <= "0000"; wait for period; assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000000"; RB <= "00000001"; OPCODE <= "0001"; wait for period; assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "11111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END CCR Tests ----- -- Mem Test -- OPCODE <= "1001"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= X"16"; OPCODE <= "1010"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "1001"; wait for period; assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; -- END Mem Test -- report "Finish ALU Test Bench" severity NOTE; wait; -- will wait forever END PROCESS; END;
--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2015 -- Module Name: ALU_TB -- Project Name: ALU -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: ALU Test Bench --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; ENTITY ALU_tb_vhd IS END ALU_tb_vhd; ARCHITECTURE behavior OF ALU_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ALU PORT( CLK : in STD_LOGIC; RA : in STD_LOGIC_VECTOR(7 downto 0); RB : in STD_LOGIC_VECTOR(7 downto 0); OPCODE : in STD_LOGIC_VECTOR(3 downto 0); CCR : out STD_LOGIC_VECTOR(3 downto 0); ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0); LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; --Inputs SIGNAL CLK : STD_LOGIC := '0'; SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); --Outputs SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0); SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0); -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 --Condition Codes SIGNAL N : STD_LOGIC := '0'; SIGNAL Z : STD_LOGIC := '0'; SIGNAL V : STD_LOGIC := '0'; SIGNAL C : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ALU PORT MAP( CLK => CLK, RA => RA, RB => RB, OPCODE => OPCODE, CCR => CCR, ALU_OUT => ALU_OUT, LDST_OUT => LDST_OUT); -- Assign condition code bits N <= CCR(3); -- N - Negative Z <= CCR(2); -- Z - Zero V <= CCR(1); -- V - Overflow C <= CCR(0); -- C - Carry/Borrow -- Generate clock gen_Clock: process begin CLK <= '0'; wait for period; CLK <= '1'; wait for period; end process gen_Clock; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; report "Start ALU Test Bench" severity NOTE; ----- Register-Register Arithmetic Tests ----- RA <= "00000101"; -- 5 RB <= "00000011"; -- 3 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01100100"; -- 100 RB <= "00110010"; -- 50 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END Arithmetic Tests ----- ----- CCR Tests ----- RA <= "00000000"; RB <= "00000000"; OPCODE <= "0000"; wait for period; assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000001"; RB <= "11111111"; OPCODE <= "0000"; wait for period; assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000000"; RB <= "00000001"; OPCODE <= "0001"; wait for period; assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "11111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END CCR Tests ----- -- Mem Test -- OPCODE <= "1001"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= X"16"; OPCODE <= "1010"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "1001"; wait for period; assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; -- END Mem Test -- report "Finish ALU Test Bench" severity NOTE; wait; -- will wait forever END PROCESS; END;
--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2015 -- Module Name: ALU_TB -- Project Name: ALU -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: ALU Test Bench --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; ENTITY ALU_tb_vhd IS END ALU_tb_vhd; ARCHITECTURE behavior OF ALU_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ALU PORT( CLK : in STD_LOGIC; RA : in STD_LOGIC_VECTOR(7 downto 0); RB : in STD_LOGIC_VECTOR(7 downto 0); OPCODE : in STD_LOGIC_VECTOR(3 downto 0); CCR : out STD_LOGIC_VECTOR(3 downto 0); ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0); LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; --Inputs SIGNAL CLK : STD_LOGIC := '0'; SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); --Outputs SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0); SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0); -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 --Condition Codes SIGNAL N : STD_LOGIC := '0'; SIGNAL Z : STD_LOGIC := '0'; SIGNAL V : STD_LOGIC := '0'; SIGNAL C : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ALU PORT MAP( CLK => CLK, RA => RA, RB => RB, OPCODE => OPCODE, CCR => CCR, ALU_OUT => ALU_OUT, LDST_OUT => LDST_OUT); -- Assign condition code bits N <= CCR(3); -- N - Negative Z <= CCR(2); -- Z - Zero V <= CCR(1); -- V - Overflow C <= CCR(0); -- C - Carry/Borrow -- Generate clock gen_Clock: process begin CLK <= '0'; wait for period; CLK <= '1'; wait for period; end process gen_Clock; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; report "Start ALU Test Bench" severity NOTE; ----- Register-Register Arithmetic Tests ----- RA <= "00000101"; -- 5 RB <= "00000011"; -- 3 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01100100"; -- 100 RB <= "00110010"; -- 50 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END Arithmetic Tests ----- ----- CCR Tests ----- RA <= "00000000"; RB <= "00000000"; OPCODE <= "0000"; wait for period; assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000001"; RB <= "11111111"; OPCODE <= "0000"; wait for period; assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000000"; RB <= "00000001"; OPCODE <= "0001"; wait for period; assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "11111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END CCR Tests ----- -- Mem Test -- OPCODE <= "1001"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= X"16"; OPCODE <= "1010"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "1001"; wait for period; assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; -- END Mem Test -- report "Finish ALU Test Bench" severity NOTE; wait; -- will wait forever END PROCESS; END;
--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2015 -- Module Name: ALU_TB -- Project Name: ALU -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: ALU Test Bench --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; ENTITY ALU_tb_vhd IS END ALU_tb_vhd; ARCHITECTURE behavior OF ALU_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ALU PORT( CLK : in STD_LOGIC; RA : in STD_LOGIC_VECTOR(7 downto 0); RB : in STD_LOGIC_VECTOR(7 downto 0); OPCODE : in STD_LOGIC_VECTOR(3 downto 0); CCR : out STD_LOGIC_VECTOR(3 downto 0); ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0); LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; --Inputs SIGNAL CLK : STD_LOGIC := '0'; SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); --Outputs SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0); SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0); -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 --Condition Codes SIGNAL N : STD_LOGIC := '0'; SIGNAL Z : STD_LOGIC := '0'; SIGNAL V : STD_LOGIC := '0'; SIGNAL C : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ALU PORT MAP( CLK => CLK, RA => RA, RB => RB, OPCODE => OPCODE, CCR => CCR, ALU_OUT => ALU_OUT, LDST_OUT => LDST_OUT); -- Assign condition code bits N <= CCR(3); -- N - Negative Z <= CCR(2); -- Z - Zero V <= CCR(1); -- V - Overflow C <= CCR(0); -- C - Carry/Borrow -- Generate clock gen_Clock: process begin CLK <= '0'; wait for period; CLK <= '1'; wait for period; end process gen_Clock; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; report "Start ALU Test Bench" severity NOTE; ----- Register-Register Arithmetic Tests ----- RA <= "00000101"; -- 5 RB <= "00000011"; -- 3 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01100100"; -- 100 RB <= "00110010"; -- 50 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END Arithmetic Tests ----- ----- CCR Tests ----- RA <= "00000000"; RB <= "00000000"; OPCODE <= "0000"; wait for period; assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000001"; RB <= "11111111"; OPCODE <= "0000"; wait for period; assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000000"; RB <= "00000001"; OPCODE <= "0001"; wait for period; assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "11111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END CCR Tests ----- -- Mem Test -- OPCODE <= "1001"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= X"16"; OPCODE <= "1010"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "1001"; wait for period; assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; -- END Mem Test -- report "Finish ALU Test Bench" severity NOTE; wait; -- will wait forever END PROCESS; END;
--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2015 -- Module Name: ALU_TB -- Project Name: ALU -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: ALU Test Bench --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; ENTITY ALU_tb_vhd IS END ALU_tb_vhd; ARCHITECTURE behavior OF ALU_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ALU PORT( CLK : in STD_LOGIC; RA : in STD_LOGIC_VECTOR(7 downto 0); RB : in STD_LOGIC_VECTOR(7 downto 0); OPCODE : in STD_LOGIC_VECTOR(3 downto 0); CCR : out STD_LOGIC_VECTOR(3 downto 0); ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0); LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; --Inputs SIGNAL CLK : STD_LOGIC := '0'; SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); --Outputs SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0); SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0); -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 --Condition Codes SIGNAL N : STD_LOGIC := '0'; SIGNAL Z : STD_LOGIC := '0'; SIGNAL V : STD_LOGIC := '0'; SIGNAL C : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ALU PORT MAP( CLK => CLK, RA => RA, RB => RB, OPCODE => OPCODE, CCR => CCR, ALU_OUT => ALU_OUT, LDST_OUT => LDST_OUT); -- Assign condition code bits N <= CCR(3); -- N - Negative Z <= CCR(2); -- Z - Zero V <= CCR(1); -- V - Overflow C <= CCR(0); -- C - Carry/Borrow -- Generate clock gen_Clock: process begin CLK <= '0'; wait for period; CLK <= '1'; wait for period; end process gen_Clock; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; report "Start ALU Test Bench" severity NOTE; ----- Register-Register Arithmetic Tests ----- RA <= "00000101"; -- 5 RB <= "00000011"; -- 3 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01100100"; -- 100 RB <= "00110010"; -- 50 OPCODE <= "0000"; wait for period; assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0001"; wait for period; assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0010"; wait for period; assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "0011"; wait for period; assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR; assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END Arithmetic Tests ----- ----- CCR Tests ----- RA <= "00000000"; RB <= "00000000"; OPCODE <= "0000"; wait for period; assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000001"; RB <= "11111111"; OPCODE <= "0000"; wait for period; assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "00000000"; RB <= "00000001"; OPCODE <= "0001"; wait for period; assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "01111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= "11111111"; RB <= "00000001"; OPCODE <= "0000"; wait for period; assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; ----- END CCR Tests ----- -- Mem Test -- OPCODE <= "1001"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; RA <= X"16"; OPCODE <= "1010"; wait for period; assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; OPCODE <= "1001"; wait for period; assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR; -- END Mem Test -- report "Finish ALU Test Bench" severity NOTE; wait; -- will wait forever END PROCESS; END;
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017 -- Date : Fri Sep 22 14:43:38 2017 -- Host : EffulgentTome running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_3_sim_netlist.vhdl -- Design : zqynq_lab_1_design_auto_pc_3 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1; attribute P_AXI4 : integer; attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0; attribute P_AXILITE : integer; attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2; attribute P_DECERR : string; attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11"; attribute P_INCR : string; attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1; attribute P_SLVERR : string; attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is signal \<const0>\ : STD_LOGIC; signal \^m_axi_arready\ : STD_LOGIC; signal \^m_axi_awready\ : STD_LOGIC; signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_buser\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^m_axi_bvalid\ : STD_LOGIC; signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^m_axi_rlast\ : STD_LOGIC; signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^m_axi_rvalid\ : STD_LOGIC; signal \^m_axi_wready\ : STD_LOGIC; signal \^s_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^s_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^s_axi_arlen\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_arlock\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^s_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^s_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^s_axi_aruser\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^s_axi_arvalid\ : STD_LOGIC; signal \^s_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^s_axi_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^s_axi_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^s_axi_awqos\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^s_axi_awuser\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^s_axi_awvalid\ : STD_LOGIC; signal \^s_axi_bready\ : STD_LOGIC; signal \^s_axi_rready\ : STD_LOGIC; signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_wlast\ : STD_LOGIC; signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_wuser\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^s_axi_wvalid\ : STD_LOGIC; begin \^m_axi_arready\ <= m_axi_arready; \^m_axi_awready\ <= m_axi_awready; \^m_axi_bid\(11 downto 0) <= m_axi_bid(11 downto 0); \^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0); \^m_axi_buser\(0) <= m_axi_buser(0); \^m_axi_bvalid\ <= m_axi_bvalid; \^m_axi_rdata\(31 downto 0) <= m_axi_rdata(31 downto 0); \^m_axi_rid\(11 downto 0) <= m_axi_rid(11 downto 0); \^m_axi_rlast\ <= m_axi_rlast; \^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0); \^m_axi_ruser\(0) <= m_axi_ruser(0); \^m_axi_rvalid\ <= m_axi_rvalid; \^m_axi_wready\ <= m_axi_wready; \^s_axi_araddr\(31 downto 0) <= s_axi_araddr(31 downto 0); \^s_axi_arburst\(1 downto 0) <= s_axi_arburst(1 downto 0); \^s_axi_arcache\(3 downto 0) <= s_axi_arcache(3 downto 0); \^s_axi_arid\(11 downto 0) <= s_axi_arid(11 downto 0); \^s_axi_arlen\(3 downto 0) <= s_axi_arlen(3 downto 0); \^s_axi_arlock\(0) <= s_axi_arlock(0); \^s_axi_arprot\(2 downto 0) <= s_axi_arprot(2 downto 0); \^s_axi_arqos\(3 downto 0) <= s_axi_arqos(3 downto 0); \^s_axi_arsize\(2 downto 0) <= s_axi_arsize(2 downto 0); \^s_axi_aruser\(0) <= s_axi_aruser(0); \^s_axi_arvalid\ <= s_axi_arvalid; \^s_axi_awaddr\(31 downto 0) <= s_axi_awaddr(31 downto 0); \^s_axi_awburst\(1 downto 0) <= s_axi_awburst(1 downto 0); \^s_axi_awcache\(3 downto 0) <= s_axi_awcache(3 downto 0); \^s_axi_awid\(11 downto 0) <= s_axi_awid(11 downto 0); \^s_axi_awlen\(3 downto 0) <= s_axi_awlen(3 downto 0); \^s_axi_awlock\(0) <= s_axi_awlock(0); \^s_axi_awprot\(2 downto 0) <= s_axi_awprot(2 downto 0); \^s_axi_awqos\(3 downto 0) <= s_axi_awqos(3 downto 0); \^s_axi_awsize\(2 downto 0) <= s_axi_awsize(2 downto 0); \^s_axi_awuser\(0) <= s_axi_awuser(0); \^s_axi_awvalid\ <= s_axi_awvalid; \^s_axi_bready\ <= s_axi_bready; \^s_axi_rready\ <= s_axi_rready; \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); \^s_axi_wlast\ <= s_axi_wlast; \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); \^s_axi_wuser\(0) <= s_axi_wuser(0); \^s_axi_wvalid\ <= s_axi_wvalid; m_axi_araddr(31 downto 0) <= \^s_axi_araddr\(31 downto 0); m_axi_arburst(1 downto 0) <= \^s_axi_arburst\(1 downto 0); m_axi_arcache(3 downto 0) <= \^s_axi_arcache\(3 downto 0); m_axi_arid(11 downto 0) <= \^s_axi_arid\(11 downto 0); m_axi_arlen(7) <= \<const0>\; m_axi_arlen(6) <= \<const0>\; m_axi_arlen(5) <= \<const0>\; m_axi_arlen(4) <= \<const0>\; m_axi_arlen(3 downto 0) <= \^s_axi_arlen\(3 downto 0); m_axi_arlock(0) <= \^s_axi_arlock\(0); m_axi_arprot(2 downto 0) <= \^s_axi_arprot\(2 downto 0); m_axi_arqos(3 downto 0) <= \^s_axi_arqos\(3 downto 0); m_axi_arregion(3) <= \<const0>\; m_axi_arregion(2) <= \<const0>\; m_axi_arregion(1) <= \<const0>\; m_axi_arregion(0) <= \<const0>\; m_axi_arsize(2 downto 0) <= \^s_axi_arsize\(2 downto 0); m_axi_aruser(0) <= \^s_axi_aruser\(0); m_axi_arvalid <= \^s_axi_arvalid\; m_axi_awaddr(31 downto 0) <= \^s_axi_awaddr\(31 downto 0); m_axi_awburst(1 downto 0) <= \^s_axi_awburst\(1 downto 0); m_axi_awcache(3 downto 0) <= \^s_axi_awcache\(3 downto 0); m_axi_awid(11 downto 0) <= \^s_axi_awid\(11 downto 0); m_axi_awlen(7) <= \<const0>\; m_axi_awlen(6) <= \<const0>\; m_axi_awlen(5) <= \<const0>\; m_axi_awlen(4) <= \<const0>\; m_axi_awlen(3 downto 0) <= \^s_axi_awlen\(3 downto 0); m_axi_awlock(0) <= \^s_axi_awlock\(0); m_axi_awprot(2 downto 0) <= \^s_axi_awprot\(2 downto 0); m_axi_awqos(3 downto 0) <= \^s_axi_awqos\(3 downto 0); m_axi_awregion(3) <= \<const0>\; m_axi_awregion(2) <= \<const0>\; m_axi_awregion(1) <= \<const0>\; m_axi_awregion(0) <= \<const0>\; m_axi_awsize(2 downto 0) <= \^s_axi_awsize\(2 downto 0); m_axi_awuser(0) <= \^s_axi_awuser\(0); m_axi_awvalid <= \^s_axi_awvalid\; m_axi_bready <= \^s_axi_bready\; m_axi_rready <= \^s_axi_rready\; m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); m_axi_wid(11) <= \<const0>\; m_axi_wid(10) <= \<const0>\; m_axi_wid(9) <= \<const0>\; m_axi_wid(8) <= \<const0>\; m_axi_wid(7) <= \<const0>\; m_axi_wid(6) <= \<const0>\; m_axi_wid(5) <= \<const0>\; m_axi_wid(4) <= \<const0>\; m_axi_wid(3) <= \<const0>\; m_axi_wid(2) <= \<const0>\; m_axi_wid(1) <= \<const0>\; m_axi_wid(0) <= \<const0>\; m_axi_wlast <= \^s_axi_wlast\; m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); m_axi_wuser(0) <= \^s_axi_wuser\(0); m_axi_wvalid <= \^s_axi_wvalid\; s_axi_arready <= \^m_axi_arready\; s_axi_awready <= \^m_axi_awready\; s_axi_bid(11 downto 0) <= \^m_axi_bid\(11 downto 0); s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0); s_axi_buser(0) <= \^m_axi_buser\(0); s_axi_bvalid <= \^m_axi_bvalid\; s_axi_rdata(31 downto 0) <= \^m_axi_rdata\(31 downto 0); s_axi_rid(11 downto 0) <= \^m_axi_rid\(11 downto 0); s_axi_rlast <= \^m_axi_rlast\; s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0); s_axi_ruser(0) <= \^m_axi_ruser\(0); s_axi_rvalid <= \^m_axi_rvalid\; s_axi_wready <= \^m_axi_wready\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_auto_pc_3,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2.1"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of inst : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of inst : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of inst : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of inst : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of inst : label is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of inst : label is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of inst : label is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of inst : label is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of inst : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of inst : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of inst : label is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of inst : label is 0; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of inst : label is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of inst : label is 2; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of inst : label is 1; attribute P_AXI4 : integer; attribute P_AXI4 of inst : label is 0; attribute P_AXILITE : integer; attribute P_AXILITE of inst : label is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of inst : label is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of inst : label is 2; attribute P_DECERR : string; attribute P_DECERR of inst : label is "2'b11"; attribute P_INCR : string; attribute P_INCR of inst : label is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of inst : label is 1; attribute P_SLVERR : string; attribute P_SLVERR of inst : label is "2'b10"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter port map ( aclk => aclk, aresetn => aresetn, m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0), m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0), m_axi_arid(11 downto 0) => m_axi_arid(11 downto 0), m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0), m_axi_arlock(0) => m_axi_arlock(0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0), m_axi_arready => m_axi_arready, m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0), m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0), m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0), m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0), m_axi_awid(11 downto 0) => m_axi_awid(11 downto 0), m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0), m_axi_awlock(0) => m_axi_awlock(0), m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0), m_axi_awready => m_axi_awready, m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0), m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0), m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0), m_axi_awvalid => m_axi_awvalid, m_axi_bid(11 downto 0) => m_axi_bid(11 downto 0), m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_buser(0) => '0', m_axi_bvalid => m_axi_bvalid, m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0), m_axi_rlast => m_axi_rlast, m_axi_rready => m_axi_rready, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_ruser(0) => '0', m_axi_rvalid => m_axi_rvalid, m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0), m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0), m_axi_wlast => m_axi_wlast, m_axi_wready => m_axi_wready, m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0), m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0), m_axi_wvalid => m_axi_wvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0), s_axi_arready => s_axi_arready, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => '0', s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), s_axi_awready => s_axi_awready, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awuser(0) => '0', s_axi_awvalid => s_axi_awvalid, s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0), s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wuser(0) => '0', s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 -- Date : Wed Sep 20 15:37:03 2017 -- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.vhdl -- Design : ila_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k325tffg676-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( clk : in STD_LOGIC; probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 ); probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 ); probe2 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe3 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe4 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe5 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe6 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe7 : in STD_LOGIC_VECTOR ( 7 downto 0 ); probe8 : in STD_LOGIC_VECTOR ( 7 downto 0 ); probe9 : in STD_LOGIC_VECTOR ( 1 downto 0 ); probe10 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe11 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[7:0],probe8[7:0],probe9[1:0],probe10[0:0],probe11[0:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3"; begin end;
-- Address decode logic for ipbus fabric -- -- This file has been AUTOGENERATED from the address table - do not hand edit -- -- We assume the synthesis tool is clever enough to recognise exclusive conditions -- in the if statement. -- -- Dave Newbold, February 2011 library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; package ipbus_decode_PACKAGENAME is constant IPBUS_SEL_WIDTH: positive := INSERT_SEL_WIDTH_HERE; subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0); function ipbus_sel_PACKAGENAME(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t; -- INSERT_SYMBOLIC_CONSTANTS_HERE end ipbus_decode_PACKAGENAME; package body ipbus_decode_PACKAGENAME is function ipbus_sel_PACKAGENAME(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is variable sel: ipbus_sel_t; begin -- INSERT_SELECTION_HERE else sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH)); end if; return sel; end function ipbus_sel_PACKAGENAME; end ipbus_decode_PACKAGENAME;
-- -- This file is part of top_test_sharp_screen -- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr ) -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/> -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY driver_testbench IS END driver_testbench; ARCHITECTURE behavior OF driver_testbench IS -- Component Declaration for the Unit Under Test (UUT) --Inputs signal clk : std_logic := '0'; signal rst : std_logic := '0'; --outputs signal clk_out : std_logic; signal hsync : std_logic; signal vsync : std_logic; signal enable : std_logic; signal r : std_logic_vector(5 downto 0); signal g : std_logic_vector(5 downto 0); signal b : std_logic_vector(5 downto 0); -- Clock period definitions constant clk_period : time := 39.71 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity work.mire_screen PORT MAP ( clk => clk, rst => rst, clk_out => clk_out, vsync => vsync, hsync => hsync, enable => enable, r => r, g => g, b => b ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for clk_period; wait for clk_period*10; -- insert stimulus here wait; end process; END;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_12_ch_12_01.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- -- code from book entity and2 is generic ( Tpd : time ); port ( a, b : in bit; y : out bit ); end entity and2; architecture simple of and2 is begin and2_function : y <= a and b after Tpd; end architecture simple; -- end code from book entity ch_12_01 is end entity ch_12_01; library stimulus; use stimulus.stimulus_generators.all; architecture test of ch_12_01 is signal a1, b1, sig1, sig2, sig_out : bit; signal test_vector : bit_vector(1 to 3); begin -- code from book gate1 : entity work.and2(simple) generic map ( Tpd => 2 ns ) port map ( a => sig1, b => sig2, y => sig_out ); gate2 : entity work.and2(simple) generic map ( Tpd => 3 ns ) port map ( a => a1, b => b1, y => sig1 ); -- end code from book stimulus : all_possible_values ( bv => test_vector, delay_between_values => 10 ns ); (sig2, a1, b1) <= test_vector; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_12_ch_12_01.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- -- code from book entity and2 is generic ( Tpd : time ); port ( a, b : in bit; y : out bit ); end entity and2; architecture simple of and2 is begin and2_function : y <= a and b after Tpd; end architecture simple; -- end code from book entity ch_12_01 is end entity ch_12_01; library stimulus; use stimulus.stimulus_generators.all; architecture test of ch_12_01 is signal a1, b1, sig1, sig2, sig_out : bit; signal test_vector : bit_vector(1 to 3); begin -- code from book gate1 : entity work.and2(simple) generic map ( Tpd => 2 ns ) port map ( a => sig1, b => sig2, y => sig_out ); gate2 : entity work.and2(simple) generic map ( Tpd => 3 ns ) port map ( a => a1, b => b1, y => sig1 ); -- end code from book stimulus : all_possible_values ( bv => test_vector, delay_between_values => 10 ns ); (sig2, a1, b1) <= test_vector; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_12_ch_12_01.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- -- code from book entity and2 is generic ( Tpd : time ); port ( a, b : in bit; y : out bit ); end entity and2; architecture simple of and2 is begin and2_function : y <= a and b after Tpd; end architecture simple; -- end code from book entity ch_12_01 is end entity ch_12_01; library stimulus; use stimulus.stimulus_generators.all; architecture test of ch_12_01 is signal a1, b1, sig1, sig2, sig_out : bit; signal test_vector : bit_vector(1 to 3); begin -- code from book gate1 : entity work.and2(simple) generic map ( Tpd => 2 ns ) port map ( a => sig1, b => sig2, y => sig_out ); gate2 : entity work.and2(simple) generic map ( Tpd => 3 ns ) port map ( a => a1, b => b1, y => sig1 ); -- end code from book stimulus : all_possible_values ( bv => test_vector, delay_between_values => 10 ns ); (sig2, a1, b1) <= test_vector; end architecture test;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block iV9RScEojiIYavQLdmhYeWlVCnGFhhcYHmKUz5KTBhhW0LvpekokIlUr7cgvImmWPpJiEPECt2sX qiIhhZUyjg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hAEiizvT6gbTVOuCKPqs8e9iJKr7DE6v1Yswz0NfOd1f78QdTFAquwZhRRVpTKc55oCyF1cmsJgi 484toQVbDo5rsG2FItfuRPaMP5uiWApMZkjGECC93QdNHOiavmGKwehQmIifadpdw8cu8MTU8oVx rvv6XrKpyyHjLnGIh+k= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block iV9RScEojiIYavQLdmhYeWlVCnGFhhcYHmKUz5KTBhhW0LvpekokIlUr7cgvImmWPpJiEPECt2sX qiIhhZUyjg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hAEiizvT6gbTVOuCKPqs8e9iJKr7DE6v1Yswz0NfOd1f78QdTFAquwZhRRVpTKc55oCyF1cmsJgi 484toQVbDo5rsG2FItfuRPaMP5uiWApMZkjGECC93QdNHOiavmGKwehQmIifadpdw8cu8MTU8oVx rvv6XrKpyyHjLnGIh+k= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block iV9RScEojiIYavQLdmhYeWlVCnGFhhcYHmKUz5KTBhhW0LvpekokIlUr7cgvImmWPpJiEPECt2sX qiIhhZUyjg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hAEiizvT6gbTVOuCKPqs8e9iJKr7DE6v1Yswz0NfOd1f78QdTFAquwZhRRVpTKc55oCyF1cmsJgi 484toQVbDo5rsG2FItfuRPaMP5uiWApMZkjGECC93QdNHOiavmGKwehQmIifadpdw8cu8MTU8oVx rvv6XrKpyyHjLnGIh+k= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block iV9RScEojiIYavQLdmhYeWlVCnGFhhcYHmKUz5KTBhhW0LvpekokIlUr7cgvImmWPpJiEPECt2sX qiIhhZUyjg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hAEiizvT6gbTVOuCKPqs8e9iJKr7DE6v1Yswz0NfOd1f78QdTFAquwZhRRVpTKc55oCyF1cmsJgi 484toQVbDo5rsG2FItfuRPaMP5uiWApMZkjGECC93QdNHOiavmGKwehQmIifadpdw8cu8MTU8oVx rvv6XrKpyyHjLnGIh+k= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hEgx8LhPoov+7F2TsULzociaL8fj7xI+oMiG0ZCm5ZmcJYJ4/TNy9JtpgVN2IH9Yl1Q0crglW30w mQjbBqDAbngJqlTDxTiedOofunRFFeyuz3X6QQ+9+wXP8Pb5m9lVWxgA+GUJWcZA2PXqW4IKUh0x DJ46hTmthnM3XfDSrxz6txi0pg8x2Kv30ya9ntDIto6+F9M4T160lpoqdlLfKR5XV3XnjxkFBSA/ t7G/vJGIYmH/woQNzlQ4lAJRL0ElxgbDDloK8iot0fmVC3Wojw3cHgmFeiRKKO2Ozq0qQK9leiIL 1lkJoPRthX9WG48VBedqbZvc/VYtQFsWj2J3Yw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cC1wfYe5/aqnYJTZsrfGoSYlzsRhNYd32nBp7LOqgXSUBSxmLg+VrFQhSHLMLXFYjuHzM7Nrp89o n9HTRIExQuCoxsfblEDOzzeySwZtf/dFHCh17c/0LvZ7GuFRxfpfI2oAF2Dh7h0e9g46egBIabo/ evmlJqQeQ/NWwsqak0Y= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OaPvfBhqSU+PUXK0gGD7gvz4oJN5TvNleV/oyc9QYEuG7LIEC++cRcPnxfQTbiXDXErneTL3Gr27 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------------------------------------------------------------------------------ -- user_logic.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: user_logic.vhd -- Version: 1.00.a -- Description: User logic. -- Date: Mon Apr 13 19:59:47 2015 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_REG : integer := 2; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ clk_48_i : in std_logic; sample_data_L_in : in std_logic_vector(23 downto 0); sample_data_R_in : in std_logic_vector(23 downto 0); sample_data_L_out : out std_logic_vector(23 downto 0); sample_data_R_out : out std_logic_vector(23 downto 0); -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Resetn : in std_logic; Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg_write_sel : std_logic_vector(1 downto 0); signal slv_reg_read_sel : std_logic_vector(1 downto 0); signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; begin --USER logic implementation added here ------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers -- -- Note: -- The example code presented here is to show you one way of reading/writing -- software accessible registers implemented in the user logic slave model. -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond -- to one software accessible register by the top level template. For example, -- if you have four 32 bit software accessible registers in the user logic, -- you are basically operating on the following memory mapped registers: -- -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register -- "1000" C_BASEADDR + 0x0 -- "0100" C_BASEADDR + 0x4 -- "0010" C_BASEADDR + 0x8 -- "0001" C_BASEADDR + 0xC -- ------------------------------------------ slv_reg_write_sel <= Bus2IP_WrCE(1 downto 0); slv_reg_read_sel <= Bus2IP_RdCE(1 downto 0); slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1); slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1); -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Resetn = '0' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); else case slv_reg_write_sel is when "10" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "01" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1 ) is begin case slv_reg_read_sel is when "10" => slv_ip2bus_data <= slv_reg0; when "01" => slv_ip2bus_data <= slv_reg1; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; end IMP;
------------------------------------------------------------------------------ -- user_logic.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: user_logic.vhd -- Version: 1.00.a -- Description: User logic. -- Date: Mon Apr 13 19:59:47 2015 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_REG : integer := 2; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ clk_48_i : in std_logic; sample_data_L_in : in std_logic_vector(23 downto 0); sample_data_R_in : in std_logic_vector(23 downto 0); sample_data_L_out : out std_logic_vector(23 downto 0); sample_data_R_out : out std_logic_vector(23 downto 0); -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Resetn : in std_logic; Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg_write_sel : std_logic_vector(1 downto 0); signal slv_reg_read_sel : std_logic_vector(1 downto 0); signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; begin --USER logic implementation added here ------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers -- -- Note: -- The example code presented here is to show you one way of reading/writing -- software accessible registers implemented in the user logic slave model. -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond -- to one software accessible register by the top level template. For example, -- if you have four 32 bit software accessible registers in the user logic, -- you are basically operating on the following memory mapped registers: -- -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register -- "1000" C_BASEADDR + 0x0 -- "0100" C_BASEADDR + 0x4 -- "0010" C_BASEADDR + 0x8 -- "0001" C_BASEADDR + 0xC -- ------------------------------------------ slv_reg_write_sel <= Bus2IP_WrCE(1 downto 0); slv_reg_read_sel <= Bus2IP_RdCE(1 downto 0); slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1); slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1); -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Resetn = '0' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); else case slv_reg_write_sel is when "10" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "01" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1 ) is begin case slv_reg_read_sel is when "10" => slv_ip2bus_data <= slv_reg0; when "01" => slv_ip2bus_data <= slv_reg1; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; end IMP;
------------------------------------------------------------------------------ -- user_logic.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: user_logic.vhd -- Version: 1.00.a -- Description: User logic. -- Date: Mon Apr 13 19:59:47 2015 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_REG : integer := 2; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ clk_48_i : in std_logic; sample_data_L_in : in std_logic_vector(23 downto 0); sample_data_R_in : in std_logic_vector(23 downto 0); sample_data_L_out : out std_logic_vector(23 downto 0); sample_data_R_out : out std_logic_vector(23 downto 0); -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Resetn : in std_logic; Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg_write_sel : std_logic_vector(1 downto 0); signal slv_reg_read_sel : std_logic_vector(1 downto 0); signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; begin --USER logic implementation added here ------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers -- -- Note: -- The example code presented here is to show you one way of reading/writing -- software accessible registers implemented in the user logic slave model. -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond -- to one software accessible register by the top level template. For example, -- if you have four 32 bit software accessible registers in the user logic, -- you are basically operating on the following memory mapped registers: -- -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register -- "1000" C_BASEADDR + 0x0 -- "0100" C_BASEADDR + 0x4 -- "0010" C_BASEADDR + 0x8 -- "0001" C_BASEADDR + 0xC -- ------------------------------------------ slv_reg_write_sel <= Bus2IP_WrCE(1 downto 0); slv_reg_read_sel <= Bus2IP_RdCE(1 downto 0); slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1); slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1); -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Resetn = '0' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); else case slv_reg_write_sel is when "10" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "01" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1 ) is begin case slv_reg_read_sel is when "10" => slv_ip2bus_data <= slv_reg0; when "01" => slv_ip2bus_data <= slv_reg1; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; end IMP;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: odpad -- File: odpad.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: tri-state output pad with technology wrapper ------------------------------------------------------------------------------ library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allpads.all; entity odpad is generic (tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := x33v; strength : integer := 12; oepol : integer := 0); port (pad : out std_ulogic; i : in std_ulogic); end; architecture rtl of odpad is signal gnd, oen, padx : std_ulogic; begin oen <= not i when oepol /= padoen_polarity(tech) else i; gnd <= '0'; gen0 : if has_pads(tech) = 0 generate pad <= gnd after 2 ns when oen = '0' -- pragma translate_off else 'X' after 2 ns when is_x(i) -- pragma translate_on else 'Z' after 2 ns; end generate; xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate x0 : virtex_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate x0 : axcel_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; atc : if (tech = atc18s) generate x0 : atc18_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; atcrh : if (tech = atc18rha) generate x0 : atc18rha_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; um : if (tech = umc) generate x0 : umc_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; rhu : if (tech = rhumc) generate x0 : rhumc_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; ihp : if (tech = ihp25) generate x0 : ihp25_toutpad generic map(level, slew, voltage, strength) port map (pad, gnd, oen); end generate; rh18t : if (tech = rhlib18t) generate x0 : rh_lib18t_iopad generic map (strength) port map (padx, gnd, oen, open); pad <= padx; end generate; ut025 : if (tech = ut25) generate x0 : ut025crh_iopad generic map (strength) port map (padx, gnd, oen, open); pad <= padx; end generate; pere : if (tech = peregrine) generate x0 : peregrine_iopad generic map (strength) port map (padx, gnd, oen, open); pad <= padx; end generate; nex : if (tech = easic90) generate x0 : nextreme_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; end; library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; entity odpadv is generic (tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := 0; strength : integer := 0; width : integer := 1; oepol : integer := 0); port ( pad : out std_logic_vector(width-1 downto 0); i : in std_logic_vector(width-1 downto 0)); end; architecture rtl of odpadv is begin v : for j in width-1 downto 0 generate x0 : odpad generic map (tech, level, slew, voltage, strength, oepol) port map (pad(j), i(j)); end generate; end;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: odpad -- File: odpad.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: tri-state output pad with technology wrapper ------------------------------------------------------------------------------ library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allpads.all; entity odpad is generic (tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := x33v; strength : integer := 12; oepol : integer := 0); port (pad : out std_ulogic; i : in std_ulogic); end; architecture rtl of odpad is signal gnd, oen, padx : std_ulogic; begin oen <= not i when oepol /= padoen_polarity(tech) else i; gnd <= '0'; gen0 : if has_pads(tech) = 0 generate pad <= gnd after 2 ns when oen = '0' -- pragma translate_off else 'X' after 2 ns when is_x(i) -- pragma translate_on else 'Z' after 2 ns; end generate; xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate x0 : virtex_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate x0 : axcel_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; atc : if (tech = atc18s) generate x0 : atc18_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; atcrh : if (tech = atc18rha) generate x0 : atc18rha_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; um : if (tech = umc) generate x0 : umc_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; rhu : if (tech = rhumc) generate x0 : rhumc_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; ihp : if (tech = ihp25) generate x0 : ihp25_toutpad generic map(level, slew, voltage, strength) port map (pad, gnd, oen); end generate; rh18t : if (tech = rhlib18t) generate x0 : rh_lib18t_iopad generic map (strength) port map (padx, gnd, oen, open); pad <= padx; end generate; ut025 : if (tech = ut25) generate x0 : ut025crh_iopad generic map (strength) port map (padx, gnd, oen, open); pad <= padx; end generate; pere : if (tech = peregrine) generate x0 : peregrine_iopad generic map (strength) port map (padx, gnd, oen, open); pad <= padx; end generate; nex : if (tech = easic90) generate x0 : nextreme_toutpad generic map (level, slew, voltage, strength) port map (pad, gnd, oen); end generate; end; library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; entity odpadv is generic (tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := 0; strength : integer := 0; width : integer := 1; oepol : integer := 0); port ( pad : out std_logic_vector(width-1 downto 0); i : in std_logic_vector(width-1 downto 0)); end; architecture rtl of odpadv is begin v : for j in width-1 downto 0 generate x0 : odpad generic map (tech, level, slew, voltage, strength, oepol) port map (pad(j), i(j)); end generate; end;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: sram -- File: sram.vhd -- Author: Jiri Gaisler Gaisler Research -- Description: Simulation model of generic async SRAM ------------------------------------------------------------------------------ -- pragma translate_off library ieee; use ieee.std_logic_1164.all; use std.textio.all; library gaisler; use gaisler.sim.all; library grlib; use grlib.stdlib.all; entity sram is generic ( index : integer := 0; -- Byte lane (0 - 3) abits: Positive := 10; -- Default 10 address bits (1 Kbyte) tacc : integer := 10; -- access time (ns) fname : string := "ram.dat"; -- File to read from clear : integer := 0); -- Clear memory port ( a : in std_logic_vector(abits-1 downto 0); d : inout std_logic_vector(7 downto 0); ce1 : in std_logic; we : in std_ulogic; oe : in std_ulogic); end; architecture sim of sram is subtype BYTE is std_logic_vector(7 downto 0); type MEM is array(0 to ((2**Abits)-1)) of BYTE; signal DINT,DI,DO : BYTE; constant ahigh : integer := abits - 1; signal wrpre : std_ulogic; function Vpar(vec : std_logic_vector) return std_ulogic is variable par : std_ulogic := '1'; begin for i in vec'range loop --' par := par xor vec(i); end loop; return par; end; begin RAM : process(CE1,WE,DI,A,OE,D) variable MEMA : MEM; variable L1 : line; variable FIRST : boolean := true; variable ADR : std_logic_vector(19 downto 0); variable BUF : std_logic_vector(31 downto 0); variable CH : character; variable ai : integer := 0; file TCF : text open read_mode is fname; variable rectype : std_logic_vector(3 downto 0); variable recaddr : std_logic_vector(31 downto 0); variable reclen : std_logic_vector(7 downto 0); variable recdata : std_logic_vector(0 to 16*8-1); begin if FIRST then if clear = 1 then MEMA := (others => X"00"); end if; L1:= new string'(""); --' while not endfile(TCF) loop readline(TCF,L1); if (L1'length /= 0) then --' while (not (L1'length=0)) and (L1(L1'left) = ' ') loop std.textio.read(L1,CH); end loop; if L1'length > 0 then --' read(L1, ch); if (ch = 'S') or (ch = 's') then hexread(L1, rectype); hexread(L1, reclen); recaddr := (others => '0'); case rectype is when "0001" => hexread(L1, recaddr(15 downto 0)); when "0010" => hexread(L1, recaddr(23 downto 0)); when "0011" => hexread(L1, recaddr); recaddr(31 downto abits) := (others => '0'); when others => next; end case; hexread(L1, recdata); if index = 6 then ai := conv_integer(recaddr); for i in 0 to 15 loop MEMA(ai+i) := recdata((i*8) to (i*8+7)); end loop; elsif (index = 4) or (index = 5) then ai := conv_integer(recaddr)/2; for i in 0 to 7 loop MEMA(ai+i) := recdata((i*16+(index-4)*8) to (i*16+(index-4)*8+7)); end loop; else ai := conv_integer(recaddr)/4; for i in 0 to 3 loop MEMA(ai+i) := recdata((i*32+index*8) to (i*32+index*8+7)); end loop; end if; end if; end if; end if; end loop; FIRST := false; else if (TO_X01(not CE1) = '1') then if not is_x(a) then ai := conv_integer(A(abits-1 downto 0)); else ai := 0; end if; dint <= mema(ai); end if; if (TO_X01(CE1 or WE) = '1') then if wrpre = '1' then mema(ai) := to_x01(std_logic_vector(DI)); end if; end if; end if; wrpre <= TO_X01((not CE1) and (not WE)); DI <= D; end process; BUFS : process(CE1,WE,DINT,OE) variable DRIVEB : std_logic; begin DRIVEB := TO_X01((not CE1) and (not OE) and WE); case DRIVEB is when '1' => D <= DINT after tacc * 1 ns; when '0' => D <= "ZZZZZZZZ" after 8 ns; when others => D <= "XXXXXXXX"; end case; end process; end sim; -- pragma translate_on
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: sram -- File: sram.vhd -- Author: Jiri Gaisler Gaisler Research -- Description: Simulation model of generic async SRAM ------------------------------------------------------------------------------ -- pragma translate_off library ieee; use ieee.std_logic_1164.all; use std.textio.all; library gaisler; use gaisler.sim.all; library grlib; use grlib.stdlib.all; entity sram is generic ( index : integer := 0; -- Byte lane (0 - 3) abits: Positive := 10; -- Default 10 address bits (1 Kbyte) tacc : integer := 10; -- access time (ns) fname : string := "ram.dat"; -- File to read from clear : integer := 0); -- Clear memory port ( a : in std_logic_vector(abits-1 downto 0); d : inout std_logic_vector(7 downto 0); ce1 : in std_logic; we : in std_ulogic; oe : in std_ulogic); end; architecture sim of sram is subtype BYTE is std_logic_vector(7 downto 0); type MEM is array(0 to ((2**Abits)-1)) of BYTE; signal DINT,DI,DO : BYTE; constant ahigh : integer := abits - 1; signal wrpre : std_ulogic; function Vpar(vec : std_logic_vector) return std_ulogic is variable par : std_ulogic := '1'; begin for i in vec'range loop --' par := par xor vec(i); end loop; return par; end; begin RAM : process(CE1,WE,DI,A,OE,D) variable MEMA : MEM; variable L1 : line; variable FIRST : boolean := true; variable ADR : std_logic_vector(19 downto 0); variable BUF : std_logic_vector(31 downto 0); variable CH : character; variable ai : integer := 0; file TCF : text open read_mode is fname; variable rectype : std_logic_vector(3 downto 0); variable recaddr : std_logic_vector(31 downto 0); variable reclen : std_logic_vector(7 downto 0); variable recdata : std_logic_vector(0 to 16*8-1); begin if FIRST then if clear = 1 then MEMA := (others => X"00"); end if; L1:= new string'(""); --' while not endfile(TCF) loop readline(TCF,L1); if (L1'length /= 0) then --' while (not (L1'length=0)) and (L1(L1'left) = ' ') loop std.textio.read(L1,CH); end loop; if L1'length > 0 then --' read(L1, ch); if (ch = 'S') or (ch = 's') then hexread(L1, rectype); hexread(L1, reclen); recaddr := (others => '0'); case rectype is when "0001" => hexread(L1, recaddr(15 downto 0)); when "0010" => hexread(L1, recaddr(23 downto 0)); when "0011" => hexread(L1, recaddr); recaddr(31 downto abits) := (others => '0'); when others => next; end case; hexread(L1, recdata); if index = 6 then ai := conv_integer(recaddr); for i in 0 to 15 loop MEMA(ai+i) := recdata((i*8) to (i*8+7)); end loop; elsif (index = 4) or (index = 5) then ai := conv_integer(recaddr)/2; for i in 0 to 7 loop MEMA(ai+i) := recdata((i*16+(index-4)*8) to (i*16+(index-4)*8+7)); end loop; else ai := conv_integer(recaddr)/4; for i in 0 to 3 loop MEMA(ai+i) := recdata((i*32+index*8) to (i*32+index*8+7)); end loop; end if; end if; end if; end if; end loop; FIRST := false; else if (TO_X01(not CE1) = '1') then if not is_x(a) then ai := conv_integer(A(abits-1 downto 0)); else ai := 0; end if; dint <= mema(ai); end if; if (TO_X01(CE1 or WE) = '1') then if wrpre = '1' then mema(ai) := to_x01(std_logic_vector(DI)); end if; end if; end if; wrpre <= TO_X01((not CE1) and (not WE)); DI <= D; end process; BUFS : process(CE1,WE,DINT,OE) variable DRIVEB : std_logic; begin DRIVEB := TO_X01((not CE1) and (not OE) and WE); case DRIVEB is when '1' => D <= DINT after tacc * 1 ns; when '0' => D <= "ZZZZZZZZ" after 8 ns; when others => D <= "XXXXXXXX"; end case; end process; end sim; -- pragma translate_on
------------------------------------------------------------------------------- -- $Id: onehot2encoded.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $ ------------------------------------------------------------------------------- -- onehot2encoded.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the user’s sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: onehot2encoded.vhd -- Version: v1.02e -- Description: This file converts a one-hot bus to an encoded bus. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: General use module ------------------------------------------------------------------------------- -- Author: ALS -- History: -- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a -- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a -- ALS 11/27/01 -- ^^^^^^ -- Version 1.02b created to fix registered grant problem. -- ~~~~~~ -- ALS 01/26/02 -- ^^^^^^ -- Created version 1.02c to fix problem with registered grants, and buslock when -- the buslock master is holding request high and performing conversion cycles. -- ~~~~~~ -- ALS 01/09/03 -- ^^^^^^ -- Created version 1.02d to register OPB_timeout to improve timing -- ~~~~~~ -- bsbrao 09/27/04 -- ^^^^^^ -- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to -- opb_ipif_v3_01_a -- ~~~~~~ -- LCW 02/04/05 - update library statements -- GAB 10/05/09 -- ^^^^^^ -- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and -- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d -- -- Updated legal header -- ~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- -- OPB_ARB_PKG includes necessary constants and functions ------------------------------------------------------------------------------- library unisim; use unisim.vcomponents.all; library opb_v20_v1_10_d; use opb_v20_v1_10_d.opb_arb_pkg.all; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics: -- C_1HOT_BUS_SIZE -- number of bits in the 1-hot bus -- -- Definition of Ports: -- Bus_1hot -- input 1-hot bus -- Bus_enc -- output encoded bus -- ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- entity onehot2encoded is generic ( C_1HOT_BUS_SIZE : integer := 8 ); port ( Bus_1hot : in std_logic_vector(0 to C_1HOT_BUS_SIZE-1); Bus_enc : out std_logic_vector(0 to log2(C_1HOT_BUS_SIZE)-1) ); end onehot2encoded; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture implementation of onehot2encoded is ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- encoder logic requires that the 1hot bus be padded to next power of 2 constant PAD_1HOT_BUS_SIZE : integer := pad_power2(C_1HOT_BUS_SIZE); ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- signal pad_1hot_bus : std_logic_vector(0 to PAD_1HOT_BUS_SIZE-1) := (others => '0'); ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- -- OR_BITS is used to determine if segments of the 1-hot bus are '1' ----------------------------------------------------------------------------- -- Begin architecture ----------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Padded bus generation ------------------------------------------------------------------------------- pad_1hot_bus(0 to C_1HOT_BUS_SIZE-1) <= Bus_1hot; ------------------------------------------------------------------------------- -- Encoded Bus generation ------------------------------------------------------------------------------- -- Note this logic uses the padded version of the 1hot bus to insure that -- the calculations are on a constant which is a power of 2 ENC_BUS_GEN: for i in 0 to log2(PAD_1HOT_BUS_SIZE)-1 generate signal temp_or : std_logic_vector(0 to 2**i) := (others => '0'); begin OR_GENERATE: for j in 1 to 2**i generate BUS_OR: entity opb_v20_v1_10_d.or_bits generic map ( C_NUM_BITS => PAD_1HOT_BUS_SIZE/2**(i+1), C_START_BIT => PAD_1HOT_BUS_SIZE/2**(i+1) + (j-1)*PAD_1HOT_BUS_SIZE/2**i, C_BUS_SIZE => PAD_1HOT_BUS_SIZE ) port map ( In_Bus => pad_1hot_bus, Sig => temp_or(j-1), Or_out => temp_or(j) ); end generate OR_GENERATE; Bus_enc(i) <= temp_or(2**i); end generate ENC_BUS_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: onehot2encoded.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $ ------------------------------------------------------------------------------- -- onehot2encoded.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the user’s sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: onehot2encoded.vhd -- Version: v1.02e -- Description: This file converts a one-hot bus to an encoded bus. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: General use module ------------------------------------------------------------------------------- -- Author: ALS -- History: -- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a -- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a -- ALS 11/27/01 -- ^^^^^^ -- Version 1.02b created to fix registered grant problem. -- ~~~~~~ -- ALS 01/26/02 -- ^^^^^^ -- Created version 1.02c to fix problem with registered grants, and buslock when -- the buslock master is holding request high and performing conversion cycles. -- ~~~~~~ -- ALS 01/09/03 -- ^^^^^^ -- Created version 1.02d to register OPB_timeout to improve timing -- ~~~~~~ -- bsbrao 09/27/04 -- ^^^^^^ -- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to -- opb_ipif_v3_01_a -- ~~~~~~ -- LCW 02/04/05 - update library statements -- GAB 10/05/09 -- ^^^^^^ -- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and -- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d -- -- Updated legal header -- ~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- -- OPB_ARB_PKG includes necessary constants and functions ------------------------------------------------------------------------------- library unisim; use unisim.vcomponents.all; library opb_v20_v1_10_d; use opb_v20_v1_10_d.opb_arb_pkg.all; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics: -- C_1HOT_BUS_SIZE -- number of bits in the 1-hot bus -- -- Definition of Ports: -- Bus_1hot -- input 1-hot bus -- Bus_enc -- output encoded bus -- ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- entity onehot2encoded is generic ( C_1HOT_BUS_SIZE : integer := 8 ); port ( Bus_1hot : in std_logic_vector(0 to C_1HOT_BUS_SIZE-1); Bus_enc : out std_logic_vector(0 to log2(C_1HOT_BUS_SIZE)-1) ); end onehot2encoded; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture implementation of onehot2encoded is ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- encoder logic requires that the 1hot bus be padded to next power of 2 constant PAD_1HOT_BUS_SIZE : integer := pad_power2(C_1HOT_BUS_SIZE); ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- signal pad_1hot_bus : std_logic_vector(0 to PAD_1HOT_BUS_SIZE-1) := (others => '0'); ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- -- OR_BITS is used to determine if segments of the 1-hot bus are '1' ----------------------------------------------------------------------------- -- Begin architecture ----------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Padded bus generation ------------------------------------------------------------------------------- pad_1hot_bus(0 to C_1HOT_BUS_SIZE-1) <= Bus_1hot; ------------------------------------------------------------------------------- -- Encoded Bus generation ------------------------------------------------------------------------------- -- Note this logic uses the padded version of the 1hot bus to insure that -- the calculations are on a constant which is a power of 2 ENC_BUS_GEN: for i in 0 to log2(PAD_1HOT_BUS_SIZE)-1 generate signal temp_or : std_logic_vector(0 to 2**i) := (others => '0'); begin OR_GENERATE: for j in 1 to 2**i generate BUS_OR: entity opb_v20_v1_10_d.or_bits generic map ( C_NUM_BITS => PAD_1HOT_BUS_SIZE/2**(i+1), C_START_BIT => PAD_1HOT_BUS_SIZE/2**(i+1) + (j-1)*PAD_1HOT_BUS_SIZE/2**i, C_BUS_SIZE => PAD_1HOT_BUS_SIZE ) port map ( In_Bus => pad_1hot_bus, Sig => temp_or(j-1), Or_out => temp_or(j) ); end generate OR_GENERATE; Bus_enc(i) <= temp_or(2**i); end generate ENC_BUS_GEN; end implementation;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015 - 2016, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: greth_mb -- File: greth_mb.vhd -- Author: Marko Isomaki -- Description: Ethernet Media Access Controller with Ethernet Debug -- Communication Link and dual AHB master interfaces ------------------------------------------------------------------------------ library ieee; library grlib; library gaisler; use ieee.std_logic_1164.all; use grlib.stdlib.all; use grlib.amba.all; use grlib.devices.all; library techmap; use techmap.gencomp.all; use gaisler.net.all; use gaisler.ethernet_mac.all; library eth; use eth.ethcomp.all; entity greth_mb is generic( hindex : integer := 0; ehindex : integer := 0; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#FFF#; pirq : integer := 0; memtech : integer := 0; ifg_gap : integer := 24; attempt_limit : integer := 16; backoff_limit : integer := 10; slot_time : integer := 128; mdcscaler : integer range 0 to 255 := 25; enable_mdio : integer range 0 to 1 := 0; fifosize : integer range 4 to 512 := 8; nsync : integer range 1 to 2 := 2; edcl : integer range 0 to 3 := 0; edclbufsz : integer range 1 to 64 := 1; macaddrh : integer := 16#00005E#; macaddrl : integer := 16#000000#; ipaddrh : integer := 16#c0a8#; ipaddrl : integer := 16#0035#; phyrstadr : integer range 0 to 32 := 0; rmii : integer range 0 to 1 := 0; oepol : integer range 0 to 1 := 0; scanen : integer range 0 to 1 := 0; ft : integer range 0 to 2 := 0; edclft : integer range 0 to 2 := 0; mdint_pol : integer range 0 to 1 := 0; enable_mdint : integer range 0 to 1 := 0; multicast : integer range 0 to 1 := 0; edclsepahb : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; mdiohold : integer := 1; maxsize : integer; gmiimode : integer range 0 to 1 := 0 ); port( rst : in std_ulogic; clk : in std_ulogic; ahbmi : in ahb_mst_in_type; ahbmo : out ahb_mst_out_type; ahbmi2 : in ahb_mst_in_type; ahbmo2 : out ahb_mst_out_type; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; ethi : in eth_in_type; etho : out eth_out_type ); end entity; architecture rtl of greth_mb is function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is begin if (edcl /= 0) and (ebufsize > fifosize) then return ebufsize; else return fifosize; end if; end function; constant fabits : integer := log2(fifosize); type szvct is array (0 to 6) of integer; constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256); constant eabits : integer := log2(edclbufsz) + 8; constant bufsize : std_logic_vector(2 downto 0) := conv_std_logic_vector(log2(edclbufsz), 3); constant ebufsize : integer := ebuf(log2(edclbufsz)); constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize); constant txfabits : integer := log2(txfifosize); constant REVISION : amba_version_type := 0; constant pconfig : apb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq), 1 => apb_iobar(paddr, pmask)); constant hconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, revision, 0), others => zero32); constant ehconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0), others => zero32); signal irq : std_ulogic; --rx ahb fifo signal rxrenable : std_ulogic; signal rxraddress : std_logic_vector(10 downto 0); signal rxwrite : std_ulogic; signal rxwdata : std_logic_vector(31 downto 0); signal rxwaddress : std_logic_vector(10 downto 0); signal rxrdata : std_logic_vector(31 downto 0); --tx ahb fifo signal txrenable : std_ulogic; signal txraddress : std_logic_vector(10 downto 0); signal txwrite : std_ulogic; signal txwdata : std_logic_vector(31 downto 0); signal txwaddress : std_logic_vector(10 downto 0); signal txrdata : std_logic_vector(31 downto 0); --edcl buf signal erenable : std_ulogic; signal eraddress : std_logic_vector(15 downto 0); signal ewritem : std_ulogic; signal ewritel : std_ulogic; signal ewaddressm : std_logic_vector(15 downto 0); signal ewaddressl : std_logic_vector(15 downto 0); signal ewdata : std_logic_vector(31 downto 0); signal erdata : std_logic_vector(31 downto 0); signal lmdio_oe : std_ulogic; -- Fix for wider bus signal hwdata : std_logic_vector(31 downto 0); signal hrdata : std_logic_vector(31 downto 0); signal ehwdata : std_logic_vector(31 downto 0); signal ehrdata : std_logic_vector(31 downto 0); begin ethc0: grethc generic map( ifg_gap => ifg_gap, attempt_limit => attempt_limit, backoff_limit => backoff_limit, mdcscaler => mdcscaler, enable_mdio => enable_mdio, fifosize => fifosize, nsync => nsync, edcl => edcl, edclbufsz => edclbufsz, macaddrh => macaddrh, macaddrl => macaddrl, ipaddrh => ipaddrh, ipaddrl => ipaddrl, phyrstadr => phyrstadr, rmii => rmii, oepol => oepol, scanen => scanen, mdint_pol => mdint_pol, enable_mdint => enable_mdint, multicast => multicast, edclsepahbg => edclsepahb, ramdebug => ramdebug, mdiohold => mdiohold, maxsize => maxsize, gmiimode => gmiimode ) port map( rst => rst, clk => clk, --ahb mst in hgrant => ahbmi.hgrant(hindex), hready => ahbmi.hready, hresp => ahbmi.hresp, hrdata => hrdata, --ahb mst out hbusreq => ahbmo.hbusreq, hlock => ahbmo.hlock, htrans => ahbmo.htrans, haddr => ahbmo.haddr, hwrite => ahbmo.hwrite, hsize => ahbmo.hsize, hburst => ahbmo.hburst, hprot => ahbmo.hprot, hwdata => hwdata, --edcl ahb mst in ehgrant => ahbmi2.hgrant(ehindex), ehready => ahbmi2.hready, ehresp => ahbmi2.hresp, ehrdata => ehrdata, --edcl ahb mst out ehbusreq => ahbmo2.hbusreq, ehlock => ahbmo2.hlock, ehtrans => ahbmo2.htrans, ehaddr => ahbmo2.haddr, ehwrite => ahbmo2.hwrite, ehsize => ahbmo2.hsize, ehburst => ahbmo2.hburst, ehprot => ahbmo2.hprot, ehwdata => ehwdata, --apb slv in psel => apbi.psel(pindex), penable => apbi.penable, paddr => apbi.paddr, pwrite => apbi.pwrite, pwdata => apbi.pwdata, --apb slv out prdata => apbo.prdata, --irq irq => irq, --rx ahb fifo rxrenable => rxrenable, rxraddress => rxraddress, rxwrite => rxwrite, rxwdata => rxwdata, rxwaddress => rxwaddress, rxrdata => rxrdata, --tx ahb fifo txrenable => txrenable, txraddress => txraddress, txwrite => txwrite, txwdata => txwdata, txwaddress => txwaddress, txrdata => txrdata, --edcl buf erenable => erenable, eraddress => eraddress, ewritem => ewritem, ewritel => ewritel, ewaddressm => ewaddressm, ewaddressl => ewaddressl, ewdata => ewdata, erdata => erdata, --ethernet input signals rmii_clk => ethi.rmii_clk, tx_clk => ethi.tx_clk, tx_dv => ethi.tx_dv, rx_clk => ethi.rx_clk, rxd => ethi.rxd(3 downto 0), rx_dv => ethi.rx_dv, rx_er => ethi.rx_er, rx_col => ethi.rx_col, rx_crs => ethi.rx_crs, rx_en => ethi.rx_en, mdio_i => ethi.mdio_i, phyrstaddr => ethi.phyrstaddr, mdint => ethi.mdint, --ethernet output signals reset => etho.reset, txd => etho.txd(3 downto 0), tx_en => etho.tx_en, tx_er => etho.tx_er, mdc => etho.mdc, mdio_o => etho.mdio_o, mdio_oe => lmdio_oe, --scantest testrst => ahbmi.testrst, testen => ahbmi.testen, testoen => ahbmi.testoen, edcladdr => ethi.edcladdr, edclsepahb => ethi.edclsepahb, edcldisable => ethi.edcldisable, speed => etho.speed); etho.txd(7 downto 4) <= "0000"; etho.mdio_oe <= ahbmi.testoen when (scanen = 1) and (ahbmi.testen = '1') else lmdio_oe; etho.gbit <= '0'; etho.tx_clk <= '0'; -- driven in rgmii component irqdrv : process(irq) begin apbo.pirq <= (others => '0'); apbo.pirq(pirq) <= irq; end process; hrdata <= ahbreadword(ahbmi.hrdata); ahbmo.hwdata <= ahbdrivedata(hwdata); ahbmo.hconfig <= hconfig; ahbmo.hindex <= hindex; ahbmo.hirq <= (others => '0'); ehrdata <= ahbreadword(ahbmi2.hrdata); ahbmo2.hwdata <= ahbdrivedata(ehwdata); ahbmo2.hconfig <= ehconfig; ahbmo2.hindex <= ehindex; ahbmo2.hirq <= (others => '0'); apbo.pconfig <= pconfig; apbo.pindex <= pindex; ------------------------------------------------------------------------------- -- FIFOS ---------------------------------------------------------------------- ------------------------------------------------------------------------------- nft : if ft = 0 generate tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits, dbits => 32, sepclk => 0) port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk, txwrite, txwaddress(txfabits-1 downto 0), txwdata); rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits, dbits => 32, sepclk => 0) port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk, rxwrite, rxwaddress(fabits-1 downto 0), rxwdata); end generate; ft1 : if ft /= 0 generate tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => txfabits, dbits => 32, sepclk => 0, ft => ft) port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk, txwrite, txwaddress(txfabits-1 downto 0), txwdata); rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits, dbits => 32, sepclk => 0, ft => ft) port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk, rxwrite, rxwaddress(fabits-1 downto 0), rxwdata); end generate; ------------------------------------------------------------------------------- -- EDCL buffer ram ------------------------------------------------------------ ------------------------------------------------------------------------------- edclramnft : if (edcl /= 0) and (edclft = 0) generate r0 : syncram_2p generic map (memtech, eabits, 16) port map( clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk, ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16)); r1 : syncram_2p generic map (memtech, eabits, 16) port map( clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk, ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0)); end generate; edclramft1 : if (edcl /= 0) and (edclft /= 0) generate r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map( clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk, ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16)); r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map( clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk, ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0)); end generate; -- pragma translate_off bootmsg : report_version generic map ( "greth" & tost(hindex) & ": 10/100 Mbit Ethernet MAC rev " & tost(REVISION) & tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " & tost(edclbufsz) & " kbyte " & tost(txfifosize) & " txfifo," & " irq " & tost(pirq) ); -- pragma translate_on end architecture;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity k_ukf_Vsigactofkofzero is port ( clock : in std_logic; I : in std_logic_vector(31 downto 0); Isc : in std_logic_vector(31 downto 0); Vactcapofk : in std_logic_vector(31 downto 0); M : in std_logic_vector(31 downto 0); D : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); Vsigactofkofzero : out std_logic_vector(31 downto 0) ); end k_ukf_Vsigactofkofzero; architecture struct of k_ukf_Vsigactofkofzero is component k_ukf_Uofk is port ( I : in std_logic_vector(31 downto 0); Isc : in std_logic_vector(31 downto 0); Vactofk : in std_logic_vector(31 downto 0); D : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); clock : in std_logic; Uofk : out std_logic_vector(31 downto 0) ); end component; component k_ukf_Vactcapofk is port ( clock : in std_logic; Vactofk : in std_logic_vector(31 downto 0); M : in std_logic_vector(31 downto 0); Uofk : in std_logic_vector(31 downto 0); Vactcapofk : out std_logic_vector(31 downto 0) ); end component; signal Z : std_logic_vector(31 downto 0); begin M1 : k_ukf_Uofk port map ( clock => clock, I => I, Isc => Isc, Vactofk => Vactcapofk, D => D, B => B, Uofk => Z); M2 : k_ukf_Vactcapofk port map ( clock => clock, Vactofk => Vactcapofk, M => M, Uofk => Z, Vactcapofk => Vsigactofkofzero); end struct;
entity test is end test; library ieee; use ieee.std_logic_1164.all; package foo is TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; -- truth table for "xor" function CONSTANT xor_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | ); end foo; use work.foo.all; library ieee; use ieee.std_logic_1164.all; architecture only of test is begin -- only process begin -- process assert xor_table( 'U', 'U' ) = 'U' report "TEST FAILED-UxU"; assert xor_table( 'U', 'X' ) = 'U' report "TEST FAILED-UxX"; assert xor_table( 'X', '-' ) = 'X' report "TEST FAILED-Xx-"; assert xor_table( '0', '1' ) = '1' report "TEST FAILED-0x1"; assert xor_table( 'H', 'Z' ) = 'X' report "TEST FAILED-HxZ"; assert xor_table( 'Z', 'W' ) = 'X' report "TEST FAILED-ZxW"; assert xor_table( 'L', '1' ) = '1' report "TEST FAILED-Lx1"; assert xor_table( 'H', '1' ) = '0' report "TEST FAILED-Hx1"; assert xor_table( '0', 'L' ) = '0' report "TEST FAILED-0xL"; assert xor_table( 'Z', 'L' ) = 'X' report "TEST FAILED-ZxL"; assert xor_table( 'Z', 'H' ) = 'X' report "TEST FAILED-ZxH"; wait; end process; end only;
entity test is end test; library ieee; use ieee.std_logic_1164.all; package foo is TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; -- truth table for "xor" function CONSTANT xor_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | ); end foo; use work.foo.all; library ieee; use ieee.std_logic_1164.all; architecture only of test is begin -- only process begin -- process assert xor_table( 'U', 'U' ) = 'U' report "TEST FAILED-UxU"; assert xor_table( 'U', 'X' ) = 'U' report "TEST FAILED-UxX"; assert xor_table( 'X', '-' ) = 'X' report "TEST FAILED-Xx-"; assert xor_table( '0', '1' ) = '1' report "TEST FAILED-0x1"; assert xor_table( 'H', 'Z' ) = 'X' report "TEST FAILED-HxZ"; assert xor_table( 'Z', 'W' ) = 'X' report "TEST FAILED-ZxW"; assert xor_table( 'L', '1' ) = '1' report "TEST FAILED-Lx1"; assert xor_table( 'H', '1' ) = '0' report "TEST FAILED-Hx1"; assert xor_table( '0', 'L' ) = '0' report "TEST FAILED-0xL"; assert xor_table( 'Z', 'L' ) = 'X' report "TEST FAILED-ZxL"; assert xor_table( 'Z', 'H' ) = 'X' report "TEST FAILED-ZxH"; wait; end process; end only;
entity test is end test; library ieee; use ieee.std_logic_1164.all; package foo is TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; -- truth table for "xor" function CONSTANT xor_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | ); end foo; use work.foo.all; library ieee; use ieee.std_logic_1164.all; architecture only of test is begin -- only process begin -- process assert xor_table( 'U', 'U' ) = 'U' report "TEST FAILED-UxU"; assert xor_table( 'U', 'X' ) = 'U' report "TEST FAILED-UxX"; assert xor_table( 'X', '-' ) = 'X' report "TEST FAILED-Xx-"; assert xor_table( '0', '1' ) = '1' report "TEST FAILED-0x1"; assert xor_table( 'H', 'Z' ) = 'X' report "TEST FAILED-HxZ"; assert xor_table( 'Z', 'W' ) = 'X' report "TEST FAILED-ZxW"; assert xor_table( 'L', '1' ) = '1' report "TEST FAILED-Lx1"; assert xor_table( 'H', '1' ) = '0' report "TEST FAILED-Hx1"; assert xor_table( '0', 'L' ) = '0' report "TEST FAILED-0xL"; assert xor_table( 'Z', 'L' ) = 'X' report "TEST FAILED-ZxL"; assert xor_table( 'Z', 'H' ) = 'X' report "TEST FAILED-ZxH"; wait; end process; end only;
-- ------------------------------------------------------------- -- -- Entity Declaration for ioblock3_e -- -- Generated -- by: wig -- on: Wed Dec 14 12:20:57 2005 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: ioblock3_e-e.vhd,v 1.4 2005/12/14 12:38:05 wig Exp $ -- $Date: 2005/12/14 12:38:05 $ -- $Log: ioblock3_e-e.vhd,v $ -- Revision 1.4 2005/12/14 12:38:05 wig -- Updated some testcases (verilog, padio) -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.43 , wilfried.gaensheimer@micronas.com -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity ioblock3_e -- entity ioblock3_e is -- Generics: -- No Generated Generics for Entity ioblock3_e -- Generated Port Declaration: port( -- Generated Port for Entity ioblock3_e p_mix_d9_di_go : out std_ulogic_vector(1 downto 0); p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0); p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0); p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0); p_mix_data_i33_go : out std_ulogic_vector(7 downto 0); p_mix_data_i34_go : out std_ulogic_vector(7 downto 0); p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0); p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0); p_mix_display_ls_en_gi : in std_ulogic; p_mix_display_ms_en_gi : in std_ulogic; p_mix_iosel_0_gi : in std_ulogic; p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0); p_mix_nand_dir_gi : in std_ulogic; p_mix_pad_di_31_gi : in std_ulogic; p_mix_pad_di_32_gi : in std_ulogic; p_mix_pad_di_33_gi : in std_ulogic; p_mix_pad_di_34_gi : in std_ulogic; p_mix_pad_di_39_gi : in std_ulogic; p_mix_pad_di_40_gi : in std_ulogic; p_mix_pad_do_31_go : out std_ulogic; p_mix_pad_do_32_go : out std_ulogic; p_mix_pad_do_35_go : out std_ulogic; p_mix_pad_do_36_go : out std_ulogic; p_mix_pad_do_39_go : out std_ulogic; p_mix_pad_do_40_go : out std_ulogic; p_mix_pad_en_31_go : out std_ulogic; p_mix_pad_en_32_go : out std_ulogic; p_mix_pad_en_35_go : out std_ulogic; p_mix_pad_en_36_go : out std_ulogic; p_mix_pad_en_39_go : out std_ulogic; p_mix_pad_en_40_go : out std_ulogic; p_mix_pad_pu_31_go : out std_ulogic; p_mix_pad_pu_32_go : out std_ulogic -- End of Generated Port for Entity ioblock3_e ); end ioblock3_e; -- -- End of Generated Entity ioblock3_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
---------------------------------------------------------------------------------------------------- -- ENTITY - Elliptic Curve Point Doubling -- -- Ports: -- clk_i - Clock -- rst_i - Reset flag -- enable_i - Enable computation -- x1_i - X part of input point -- y1_i - Y part of input point -- x2_io - X part of output point -- y2_o - Y part of putput point -- ready_o - Ready flag -- -- Math: -- s = x1 + y1/x1 -- x2 = s^2 + s + a -- y2 = x1^2 + s*x2 + x2 -- -- Autor: Lennart Bublies (inf100434) -- Date: 27.06.2017 ---------------------------------------------------------------------------------------------------- ------------------------------------------------------------ -- K163 elliptic curve point doubling ------------------------------------------------------------ LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; USE work.tld_ecdsa_package.all; ENTITY e_gf2m_point_doubling IS GENERIC ( MODULO : std_logic_vector(M DOWNTO 0) := ONE ); PORT( -- Clock, reset, enable clk_i: IN std_logic; rst_i: IN std_logic; enable_i: IN std_logic; -- Input signals x1_i: IN std_logic_vector(M-1 DOWNTO 0); y1_i: IN std_logic_vector(M-1 DOWNTO 0); -- Output signals x2_io: INOUT std_logic_vector(M-1 DOWNTO 0); y2_o: OUT std_logic_vector(M-1 DOWNTO 0); ready_o: OUT std_logic ); END e_gf2m_point_doubling; ARCHITECTURE rtl of e_gf2m_point_doubling IS -- Import entity e_gf2m_divider COMPONENT e_gf2m_divider IS GENERIC ( MODULO : std_logic_vector(M DOWNTO 0) ); PORT( clk_i: IN std_logic; rst_i: IN std_logic; enable_i: IN std_logic; g_i: IN std_logic_vector(M-1 DOWNTO 0); h_i: IN std_logic_vector(M-1 DOWNTO 0); z_o: OUT std_logic_vector(M-1 DOWNTO 0); ready_o: OUT std_logic ); end COMPONENT; -- Import entity e_gf2m_classic_squarer COMPONENT e_gf2m_classic_squarer IS GENERIC ( MODULO : std_logic_vector(M-1 DOWNTO 0) ); PORT( a_i: IN std_logic_vector(M-1 DOWNTO 0); c_o: OUT std_logic_vector(M-1 DOWNTO 0) ); end COMPONENT; -- Import entity e_gf2m_interleaved_multiplier COMPONENT e_gf2m_interleaved_multiplier IS GENERIC ( MODULO : std_logic_vector(M-1 DOWNTO 0) ); PORT( clk_i: IN std_logic; rst_i: IN std_logic; enable_i: IN std_logic; a_i: IN std_logic_vector (M-1 DOWNTO 0); b_i: IN std_logic_vector (M-1 DOWNTO 0); z_o: OUT std_logic_vector (M-1 DOWNTO 0); ready_o: OUT std_logic ); end COMPONENT; -- Temporary signals for divider and multiplier SIGNAL div_xy, mult_lx2, lambda, lambda_square, x1_square: std_logic_vector(M-1 DOWNTO 0); SIGNAL x2_tmp, y2_tmp, next_xq, next_yq: std_logic_vector(M-1 DOWNTO 0); -- Signals to switch between multiplier and divider SIGNAL start_div, div_done, start_mult, mult_done, sel, load, ch_q: std_logic; -- Define all available states subtype states IS natural RANGE 0 TO 9; SIGNAL current_state: states; BEGIN -- Output register register_q: PROCESS(clk_i) BEGIN IF clk_i' event and clk_i = '1' THEN IF load = '1' THEN x2_io <= (OTHERS=>'1'); y2_o <= (OTHERS=>'1'); ELSIF ch_q = '1' THEN x2_io <= next_xq; y2_o <= next_yq; END IF; END IF; END PROCESS; -- Instantiate divider entity -- Calculate div_xy = y1 / x1 divider: e_gf2m_divider GENERIC MAP ( MODULO => MODULO ) PORT MAP( clk_i => clk_i, rst_i => rst_i, enable_i => start_div, g_i => y1_i, h_i => x1_i, z_o => div_xy, ready_o => div_done ); -- Compute lambda -- Calculate lambda = x1 + y1/x1 multiplier_inputs: FOR i IN 0 TO M-1 GENERATE lambda(i) <= x1_i(i) xor div_xy(i); END GENERATE; -- Instantiate squarer -- Calculate lambda^2 and x1^2 lambda_square_computation: e_gf2m_classic_squarer GENERIC MAP ( MODULO => MODULO(M-1 DOWNTO 0) ) PORT MAP( a_i => lambda, c_o => lambda_square ); x1_square_computation: e_gf2m_classic_squarer GENERIC MAP ( MODULO => MODULO(M-1 DOWNTO 0) ) PORT MAP( a_i => x1_i, c_o => x1_square ); -- Compute x2_tmp -- Calculate x2 = lambda^2 + lambda + a x2_output: FOR i IN 0 TO M-1 GENERATE x2_tmp(i) <= lambda_square(i) xor lambda(i) xor A(i); END GENERATE; -- Instantiate multiplier entity -- Calculate mult_lx2 = lambda * x2_tmp multiplier: e_gf2m_interleaved_multiplier GENERIC MAP ( MODULO => MODULO(M-1 DOWNTO 0) ) PORT MAP( clk_i => clk_i, rst_i => rst_i, enable_i => start_mult, a_i => lambda, b_i => x2_tmp, z_o => mult_lx2, ready_o => mult_done ); -- Compute y2_tmp -- Calculate y2 = x1^2 + lambda*x2 + x2 y2_output: FOR i IN 0 TO M-1 GENERATE y2_tmp(i) <= x1_square(i) xor mult_lx2(i) xor x2_tmp(i); END GENERATE; WITH sel SELECT next_yq <= y2_tmp WHEN '0', ONES WHEN OTHERS; WITH sel SELECT next_xq <= x2_tmp WHEN '0', ONES WHEN OTHERS; -- State machine control_unit: PROCESS(clk_i, rst_i, current_state) BEGIN -- Handle current state -- 0,1 : Default state -- 2,3 : Calculate s = (py-qy)/(px-qx), s^2 -- 4,5,6 : Calculate rx/ry CASE current_state IS WHEN 0 TO 1 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '1'; WHEN 2 => load <= '1'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0'; WHEN 3 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0'; WHEN 4 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '1'; start_mult <= '0'; ready_o <= '0'; WHEN 5 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0'; WHEN 6 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '1'; ready_o <= '0'; WHEN 7 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0'; WHEN 8 => load <= '0'; sel <= '0'; ch_q <= '1'; start_div <= '0'; start_mult <= '0'; ready_o <= '0'; WHEN 9 => load <= '0'; sel <= '1'; ch_q <= '1'; start_div <= '0'; start_mult <= '0'; ready_o <= '0'; END CASE; IF rst_i = '1' THEN -- Reset state if reset is high current_state <= 0; ELSIF clk_i'event and clk_i = '1' THEN -- Set next state CASE current_state IS WHEN 0 => IF enable_i = '0' THEN current_state <= 1; END IF; WHEN 1 => IF enable_i = '1' THEN current_state <= 2; END IF; WHEN 2 => current_state <= 3; WHEN 3 => IF (x1_i = ONES) OR (y1_i = ONES) THEN current_state <= 9; ELSE current_state <= 4; END IF; WHEN 4 => current_state <= 5; WHEN 5 => IF div_done = '1' THEN current_state <= 6; END IF; WHEN 6 => current_state <= 7; WHEN 7 => IF mult_done = '1' THEN current_state <= 8; END IF; WHEN 8 => current_state <= 0; WHEN 9 => current_state <= 0; END CASE; END IF; END PROCESS; END rtl;
entity add is generic ( -- A comment on its own line without colons WIDTH : integer := 3; -- A comment at the end of a line with no colons -- A comment on its own line with : a colon HEIGHT : integer := 2 -- A comment at the end of a line with : a colon ); port ( -- A comment on its own line without colons clk : in std_logic; -- A comment on its own line with : a colon in : in std_logic_vector(WIDTH-1 downto 0); -- A comment at the end of a line with no colons output : out std_logic_vector(WIDTH-1 downto 0) -- A comment at the end of a line with : a colon ); end add;
---------------------------------------------------------------------------------- -- Engineer: Mike Field <hamster@snap.net.nz< -- -- Module Name: adau1761_configuraiton_data - Behavioral -- Description: A script for the I3C2, which sends out I2c transactions to configure -- the ADAU1761 codec. -- -- See i3c2program for original source for script ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity adau1761_configuraiton_data is Port ( clk : in STD_LOGIC; address : in STD_LOGIC_VECTOR (9 downto 0); data : out STD_LOGIC_VECTOR (8 downto 0)); end adau1761_configuraiton_data; architecture Behavioral of adau1761_configuraiton_data is begin process(clk) begin if rising_edge(clk) then case address is when "0000000000" => data <= "011101111"; when "0000000001" => data <= "101110110"; when "0000000010" => data <= "101000000"; when "0000000011" => data <= "100000000"; when "0000000100" => data <= "100001110"; when "0000000101" => data <= "011111111"; when "0000000110" => data <= "101110110"; when "0000000111" => data <= "101000000"; when "0000001000" => data <= "100000010"; when "0000001001" => data <= "100000000"; when "0000001010" => data <= "101111101"; when "0000001011" => data <= "100000000"; when "0000001100" => data <= "100001100"; when "0000001101" => data <= "100100011"; when "0000001110" => data <= "100000001"; when "0000001111" => data <= "011111111"; when "0000010000" => data <= "011101111"; when "0000010001" => data <= "101110110"; when "0000010010" => data <= "101000000"; when "0000010011" => data <= "100000000"; when "0000010100" => data <= "100001111"; when "0000010101" => data <= "011111111"; when "0000010110" => data <= "011101111"; when "0000010111" => data <= "101110110"; when "0000011000" => data <= "101000000"; when "0000011001" => data <= "100010101"; when "0000011010" => data <= "100000001"; when "0000011011" => data <= "011111111"; when "0000011100" => data <= "101110110"; when "0000011101" => data <= "101000000"; when "0000011110" => data <= "100001010"; when "0000011111" => data <= "100000001"; when "0000100000" => data <= "011111111"; when "0000100001" => data <= "101110110"; when "0000100010" => data <= "101000000"; when "0000100011" => data <= "100001011"; when "0000100100" => data <= "100000101"; when "0000100101" => data <= "011111111"; when "0000100110" => data <= "101110110"; when "0000100111" => data <= "101000000"; when "0000101000" => data <= "100001100"; when "0000101001" => data <= "100000001"; when "0000101010" => data <= "011111111"; when "0000101011" => data <= "101110110"; when "0000101100" => data <= "101000000"; when "0000101101" => data <= "100001101"; when "0000101110" => data <= "100000101"; when "0000101111" => data <= "011111111"; when "0000110000" => data <= "101110110"; when "0000110001" => data <= "101000000"; when "0000110010" => data <= "100011100"; when "0000110011" => data <= "100100001"; when "0000110100" => data <= "011111111"; when "0000110101" => data <= "101110110"; when "0000110110" => data <= "101000000"; when "0000110111" => data <= "100011110"; when "0000111000" => data <= "101000001"; when "0000111001" => data <= "011111111"; when "0000111010" => data <= "101110110"; when "0000111011" => data <= "101000000"; when "0000111100" => data <= "100100011"; when "0000111101" => data <= "111100111"; when "0000111110" => data <= "011111111"; when "0000111111" => data <= "101110110"; when "0001000000" => data <= "101000000"; when "0001000001" => data <= "100100100"; when "0001000010" => data <= "111100111"; when "0001000011" => data <= "011111111"; when "0001000100" => data <= "101110110"; when "0001000101" => data <= "101000000"; when "0001000110" => data <= "100100101"; when "0001000111" => data <= "111100111"; when "0001001000" => data <= "011111111"; when "0001001001" => data <= "101110110"; when "0001001010" => data <= "101000000"; when "0001001011" => data <= "100100110"; when "0001001100" => data <= "111100111"; when "0001001101" => data <= "011111111"; when "0001001110" => data <= "101110110"; when "0001001111" => data <= "101000000"; when "0001010000" => data <= "100011001"; when "0001010001" => data <= "100000011"; when "0001010010" => data <= "011111111"; when "0001010011" => data <= "101110110"; when "0001010100" => data <= "101000000"; when "0001010101" => data <= "100101001"; when "0001010110" => data <= "100000011"; when "0001010111" => data <= "011111111"; when "0001011000" => data <= "101110110"; when "0001011001" => data <= "101000000"; when "0001011010" => data <= "100101010"; when "0001011011" => data <= "100000011"; when "0001011100" => data <= "011111111"; when "0001011101" => data <= "101110110"; when "0001011110" => data <= "101000000"; when "0001011111" => data <= "111110010"; when "0001100000" => data <= "100000001"; when "0001100001" => data <= "011111111"; when "0001100010" => data <= "101110110"; when "0001100011" => data <= "101000000"; when "0001100100" => data <= "111110011"; when "0001100101" => data <= "100000001"; when "0001100110" => data <= "011111111"; when "0001100111" => data <= "101110110"; when "0001101000" => data <= "101000000"; when "0001101001" => data <= "111111001"; when "0001101010" => data <= "101111111"; when "0001101011" => data <= "011111111"; when "0001101100" => data <= "101110110"; when "0001101101" => data <= "101000000"; when "0001101110" => data <= "111111010"; when "0001101111" => data <= "100000011"; when "0001110000" => data <= "011111111"; when "0001110001" => data <= "000010011"; when "0001110010" => data <= "011111110"; when "0001110011" => data <= "011111110"; when "0001110100" => data <= "011111110"; when "0001110101" => data <= "011111110"; when "0001110110" => data <= "011111110"; when "0001110111" => data <= "011111110"; when "0001111000" => data <= "101110110"; when "0001111001" => data <= "101000000"; when "0001111010" => data <= "100011100"; when "0001111011" => data <= "100100000"; when "0001111100" => data <= "011111111"; when "0001111101" => data <= "101110110"; when "0001111110" => data <= "101000000"; when "0001111111" => data <= "100011110"; when "0010000000" => data <= "101000000"; when "0010000001" => data <= "011111111"; when "0010000010" => data <= "011101111"; when "0010000011" => data <= "011101111"; when "0010000100" => data <= "011101111"; when "0010000101" => data <= "011101111"; when "0010000110" => data <= "010100000"; when "0010000111" => data <= "010100001"; when "0010001000" => data <= "011101111"; when "0010001001" => data <= "011101111"; when "0010001010" => data <= "101110110"; when "0010001011" => data <= "101000000"; when "0010001100" => data <= "100011100"; when "0010001101" => data <= "100100001"; when "0010001110" => data <= "011111111"; when "0010001111" => data <= "101110110"; when "0010010000" => data <= "101000000"; when "0010010001" => data <= "100011110"; when "0010010010" => data <= "101000001"; when "0010010011" => data <= "011111111"; when "0010010100" => data <= "011111110"; when "0010010101" => data <= "011111110"; when "0010010110" => data <= "011111110"; when "0010010111" => data <= "011111110"; when "0010011000" => data <= "010000000"; when "0010011001" => data <= "000010100"; when "0010011010" => data <= "010000001"; when "0010011011" => data <= "000011001"; when "0010011100" => data <= "000010011"; when "0010011101" => data <= "011111110"; when "0010011110" => data <= "011111110"; when "0010011111" => data <= "011111110"; when "0010100000" => data <= "101110110"; when "0010100001" => data <= "101000000"; when "0010100010" => data <= "100011100"; when "0010100011" => data <= "100100000"; when "0010100100" => data <= "011111111"; when "0010100101" => data <= "101110110"; when "0010100110" => data <= "101000000"; when "0010100111" => data <= "100011110"; when "0010101000" => data <= "101000000"; when "0010101001" => data <= "011111111"; when "0010101010" => data <= "011101111"; when "0010101011" => data <= "011101111"; when "0010101100" => data <= "011101111"; when "0010101101" => data <= "011101111"; when "0010101110" => data <= "010110000"; when "0010101111" => data <= "010100001"; when "0010110000" => data <= "011101111"; when "0010110001" => data <= "011101111"; when "0010110010" => data <= "101110110"; when "0010110011" => data <= "101000000"; when "0010110100" => data <= "100011100"; when "0010110101" => data <= "100100001"; when "0010110110" => data <= "011111111"; when "0010110111" => data <= "101110110"; when "0010111000" => data <= "101000000"; when "0010111001" => data <= "100011110"; when "0010111010" => data <= "101000001"; when "0010111011" => data <= "011111111"; when "0010111100" => data <= "011111110"; when "0010111101" => data <= "011111110"; when "0010111110" => data <= "011111110"; when "0010111111" => data <= "011111110"; when "0011000000" => data <= "010010000"; when "0011000001" => data <= "000001111"; when "0011000010" => data <= "010000001"; when "0011000011" => data <= "000011110"; when "0011000100" => data <= "000011000"; when "0011000101" => data <= "011111110"; when "0011000110" => data <= "011111110"; when "0011000111" => data <= "011111110"; when "0011001000" => data <= "101110110"; when "0011001001" => data <= "101000000"; when "0011001010" => data <= "100011100"; when "0011001011" => data <= "100100000"; when "0011001100" => data <= "011111111"; when "0011001101" => data <= "101110110"; when "0011001110" => data <= "101000000"; when "0011001111" => data <= "100011110"; when "0011010000" => data <= "101000000"; when "0011010001" => data <= "011111111"; when "0011010010" => data <= "011101111"; when "0011010011" => data <= "011101111"; when "0011010100" => data <= "011101111"; when "0011010101" => data <= "011101111"; when "0011010110" => data <= "010100000"; when "0011010111" => data <= "010110001"; when "0011011000" => data <= "011101111"; when "0011011001" => data <= "011101111"; when "0011011010" => data <= "101110110"; when "0011011011" => data <= "101000000"; when "0011011100" => data <= "100011100"; when "0011011101" => data <= "100100001"; when "0011011110" => data <= "011111111"; when "0011011111" => data <= "101110110"; when "0011100000" => data <= "101000000"; when "0011100001" => data <= "100011110"; when "0011100010" => data <= "101000001"; when "0011100011" => data <= "011111111"; when "0011100100" => data <= "011111110"; when "0011100101" => data <= "011111110"; when "0011100110" => data <= "011111110"; when "0011100111" => data <= "011111110"; when "0011101000" => data <= "010000000"; when "0011101001" => data <= "000000000"; when "0011101010" => data <= "010010001"; when "0011101011" => data <= "000001111"; when "0011101100" => data <= "000011101"; when "0011101101" => data <= "011111110"; when "0011101110" => data <= "011111110"; when "0011101111" => data <= "011111110"; when "0011110000" => data <= "101110110"; when "0011110001" => data <= "101000000"; when "0011110010" => data <= "100011100"; when "0011110011" => data <= "100100000"; when "0011110100" => data <= "011111111"; when "0011110101" => data <= "101110110"; when "0011110110" => data <= "101000000"; when "0011110111" => data <= "100011110"; when "0011111000" => data <= "101000000"; when "0011111001" => data <= "011111111"; when "0011111010" => data <= "011101111"; when "0011111011" => data <= "011101111"; when "0011111100" => data <= "011101111"; when "0011111101" => data <= "011101111"; when "0011111110" => data <= "010110000"; when "0011111111" => data <= "010110001"; when "0100000000" => data <= "011101111"; when "0100000001" => data <= "011101111"; when "0100000010" => data <= "101110110"; when "0100000011" => data <= "101000000"; when "0100000100" => data <= "100011100"; when "0100000101" => data <= "100100001"; when "0100000110" => data <= "011111111"; when "0100000111" => data <= "101110110"; when "0100001000" => data <= "101000000"; when "0100001001" => data <= "100011110"; when "0100001010" => data <= "101000001"; when "0100001011" => data <= "011111111"; when "0100001100" => data <= "011111110"; when "0100001101" => data <= "011111110"; when "0100001110" => data <= "011111110"; when "0100001111" => data <= "011111110"; when "0100010000" => data <= "010010000"; when "0100010001" => data <= "000011001"; when "0100010010" => data <= "010010001"; when "0100010011" => data <= "000010100"; when "0100010100" => data <= "000100010"; when others => data <= (others =>'0'); end case; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Engineer: Mike Field <hamster@snap.net.nz< -- -- Module Name: adau1761_configuraiton_data - Behavioral -- Description: A script for the I3C2, which sends out I2c transactions to configure -- the ADAU1761 codec. -- -- See i3c2program for original source for script ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity adau1761_configuraiton_data is Port ( clk : in STD_LOGIC; address : in STD_LOGIC_VECTOR (9 downto 0); data : out STD_LOGIC_VECTOR (8 downto 0)); end adau1761_configuraiton_data; architecture Behavioral of adau1761_configuraiton_data is begin process(clk) begin if rising_edge(clk) then case address is when "0000000000" => data <= "011101111"; when "0000000001" => data <= "101110110"; when "0000000010" => data <= "101000000"; when "0000000011" => data <= "100000000"; when "0000000100" => data <= "100001110"; when "0000000101" => data <= "011111111"; when "0000000110" => data <= "101110110"; when "0000000111" => data <= "101000000"; when "0000001000" => data <= "100000010"; when "0000001001" => data <= "100000000"; when "0000001010" => data <= "101111101"; when "0000001011" => data <= "100000000"; when "0000001100" => data <= "100001100"; when "0000001101" => data <= "100100011"; when "0000001110" => data <= "100000001"; when "0000001111" => data <= "011111111"; when "0000010000" => data <= "011101111"; when "0000010001" => data <= "101110110"; when "0000010010" => data <= "101000000"; when "0000010011" => data <= "100000000"; when "0000010100" => data <= "100001111"; when "0000010101" => data <= "011111111"; when "0000010110" => data <= "011101111"; when "0000010111" => data <= "101110110"; when "0000011000" => data <= "101000000"; when "0000011001" => data <= "100010101"; when "0000011010" => data <= "100000001"; when "0000011011" => data <= "011111111"; when "0000011100" => data <= "101110110"; when "0000011101" => data <= "101000000"; when "0000011110" => data <= "100001010"; when "0000011111" => data <= "100000001"; when "0000100000" => data <= "011111111"; when "0000100001" => data <= "101110110"; when "0000100010" => data <= "101000000"; when "0000100011" => data <= "100001011"; when "0000100100" => data <= "100000101"; when "0000100101" => data <= "011111111"; when "0000100110" => data <= "101110110"; when "0000100111" => data <= "101000000"; when "0000101000" => data <= "100001100"; when "0000101001" => data <= "100000001"; when "0000101010" => data <= "011111111"; when "0000101011" => data <= "101110110"; when "0000101100" => data <= "101000000"; when "0000101101" => data <= "100001101"; when "0000101110" => data <= "100000101"; when "0000101111" => data <= "011111111"; when "0000110000" => data <= "101110110"; when "0000110001" => data <= "101000000"; when "0000110010" => data <= "100011100"; when "0000110011" => data <= "100100001"; when "0000110100" => data <= "011111111"; when "0000110101" => data <= "101110110"; when "0000110110" => data <= "101000000"; when "0000110111" => data <= "100011110"; when "0000111000" => data <= "101000001"; when "0000111001" => data <= "011111111"; when "0000111010" => data <= "101110110"; when "0000111011" => data <= "101000000"; when "0000111100" => data <= "100100011"; when "0000111101" => data <= "111100111"; when "0000111110" => data <= "011111111"; when "0000111111" => data <= "101110110"; when "0001000000" => data <= "101000000"; when "0001000001" => data <= "100100100"; when "0001000010" => data <= "111100111"; when "0001000011" => data <= "011111111"; when "0001000100" => data <= "101110110"; when "0001000101" => data <= "101000000"; when "0001000110" => data <= "100100101"; when "0001000111" => data <= "111100111"; when "0001001000" => data <= "011111111"; when "0001001001" => data <= "101110110"; when "0001001010" => data <= "101000000"; when "0001001011" => data <= "100100110"; when "0001001100" => data <= "111100111"; when "0001001101" => data <= "011111111"; when "0001001110" => data <= "101110110"; when "0001001111" => data <= "101000000"; when "0001010000" => data <= "100011001"; when "0001010001" => data <= "100000011"; when "0001010010" => data <= "011111111"; when "0001010011" => data <= "101110110"; when "0001010100" => data <= "101000000"; when "0001010101" => data <= "100101001"; when "0001010110" => data <= "100000011"; when "0001010111" => data <= "011111111"; when "0001011000" => data <= "101110110"; when "0001011001" => data <= "101000000"; when "0001011010" => data <= "100101010"; when "0001011011" => data <= "100000011"; when "0001011100" => data <= "011111111"; when "0001011101" => data <= "101110110"; when "0001011110" => data <= "101000000"; when "0001011111" => data <= "111110010"; when "0001100000" => data <= "100000001"; when "0001100001" => data <= "011111111"; when "0001100010" => data <= "101110110"; when "0001100011" => data <= "101000000"; when "0001100100" => data <= "111110011"; when "0001100101" => data <= "100000001"; when "0001100110" => data <= "011111111"; when "0001100111" => data <= "101110110"; when "0001101000" => data <= "101000000"; when "0001101001" => data <= "111111001"; when "0001101010" => data <= "101111111"; when "0001101011" => data <= "011111111"; when "0001101100" => data <= "101110110"; when "0001101101" => data <= "101000000"; when "0001101110" => data <= "111111010"; when "0001101111" => data <= "100000011"; when "0001110000" => data <= "011111111"; when "0001110001" => data <= "000010011"; when "0001110010" => data <= "011111110"; when "0001110011" => data <= "011111110"; when "0001110100" => data <= "011111110"; when "0001110101" => data <= "011111110"; when "0001110110" => data <= "011111110"; when "0001110111" => data <= "011111110"; when "0001111000" => data <= "101110110"; when "0001111001" => data <= "101000000"; when "0001111010" => data <= "100011100"; when "0001111011" => data <= "100100000"; when "0001111100" => data <= "011111111"; when "0001111101" => data <= "101110110"; when "0001111110" => data <= "101000000"; when "0001111111" => data <= "100011110"; when "0010000000" => data <= "101000000"; when "0010000001" => data <= "011111111"; when "0010000010" => data <= "011101111"; when "0010000011" => data <= "011101111"; when "0010000100" => data <= "011101111"; when "0010000101" => data <= "011101111"; when "0010000110" => data <= "010100000"; when "0010000111" => data <= "010100001"; when "0010001000" => data <= "011101111"; when "0010001001" => data <= "011101111"; when "0010001010" => data <= "101110110"; when "0010001011" => data <= "101000000"; when "0010001100" => data <= "100011100"; when "0010001101" => data <= "100100001"; when "0010001110" => data <= "011111111"; when "0010001111" => data <= "101110110"; when "0010010000" => data <= "101000000"; when "0010010001" => data <= "100011110"; when "0010010010" => data <= "101000001"; when "0010010011" => data <= "011111111"; when "0010010100" => data <= "011111110"; when "0010010101" => data <= "011111110"; when "0010010110" => data <= "011111110"; when "0010010111" => data <= "011111110"; when "0010011000" => data <= "010000000"; when "0010011001" => data <= "000010100"; when "0010011010" => data <= "010000001"; when "0010011011" => data <= "000011001"; when "0010011100" => data <= "000010011"; when "0010011101" => data <= "011111110"; when "0010011110" => data <= "011111110"; when "0010011111" => data <= "011111110"; when "0010100000" => data <= "101110110"; when "0010100001" => data <= "101000000"; when "0010100010" => data <= "100011100"; when "0010100011" => data <= "100100000"; when "0010100100" => data <= "011111111"; when "0010100101" => data <= "101110110"; when "0010100110" => data <= "101000000"; when "0010100111" => data <= "100011110"; when "0010101000" => data <= "101000000"; when "0010101001" => data <= "011111111"; when "0010101010" => data <= "011101111"; when "0010101011" => data <= "011101111"; when "0010101100" => data <= "011101111"; when "0010101101" => data <= "011101111"; when "0010101110" => data <= "010110000"; when "0010101111" => data <= "010100001"; when "0010110000" => data <= "011101111"; when "0010110001" => data <= "011101111"; when "0010110010" => data <= "101110110"; when "0010110011" => data <= "101000000"; when "0010110100" => data <= "100011100"; when "0010110101" => data <= "100100001"; when "0010110110" => data <= "011111111"; when "0010110111" => data <= "101110110"; when "0010111000" => data <= "101000000"; when "0010111001" => data <= "100011110"; when "0010111010" => data <= "101000001"; when "0010111011" => data <= "011111111"; when "0010111100" => data <= "011111110"; when "0010111101" => data <= "011111110"; when "0010111110" => data <= "011111110"; when "0010111111" => data <= "011111110"; when "0011000000" => data <= "010010000"; when "0011000001" => data <= "000001111"; when "0011000010" => data <= "010000001"; when "0011000011" => data <= "000011110"; when "0011000100" => data <= "000011000"; when "0011000101" => data <= "011111110"; when "0011000110" => data <= "011111110"; when "0011000111" => data <= "011111110"; when "0011001000" => data <= "101110110"; when "0011001001" => data <= "101000000"; when "0011001010" => data <= "100011100"; when "0011001011" => data <= "100100000"; when "0011001100" => data <= "011111111"; when "0011001101" => data <= "101110110"; when "0011001110" => data <= "101000000"; when "0011001111" => data <= "100011110"; when "0011010000" => data <= "101000000"; when "0011010001" => data <= "011111111"; when "0011010010" => data <= "011101111"; when "0011010011" => data <= "011101111"; when "0011010100" => data <= "011101111"; when "0011010101" => data <= "011101111"; when "0011010110" => data <= "010100000"; when "0011010111" => data <= "010110001"; when "0011011000" => data <= "011101111"; when "0011011001" => data <= "011101111"; when "0011011010" => data <= "101110110"; when "0011011011" => data <= "101000000"; when "0011011100" => data <= "100011100"; when "0011011101" => data <= "100100001"; when "0011011110" => data <= "011111111"; when "0011011111" => data <= "101110110"; when "0011100000" => data <= "101000000"; when "0011100001" => data <= "100011110"; when "0011100010" => data <= "101000001"; when "0011100011" => data <= "011111111"; when "0011100100" => data <= "011111110"; when "0011100101" => data <= "011111110"; when "0011100110" => data <= "011111110"; when "0011100111" => data <= "011111110"; when "0011101000" => data <= "010000000"; when "0011101001" => data <= "000000000"; when "0011101010" => data <= "010010001"; when "0011101011" => data <= "000001111"; when "0011101100" => data <= "000011101"; when "0011101101" => data <= "011111110"; when "0011101110" => data <= "011111110"; when "0011101111" => data <= "011111110"; when "0011110000" => data <= "101110110"; when "0011110001" => data <= "101000000"; when "0011110010" => data <= "100011100"; when "0011110011" => data <= "100100000"; when "0011110100" => data <= "011111111"; when "0011110101" => data <= "101110110"; when "0011110110" => data <= "101000000"; when "0011110111" => data <= "100011110"; when "0011111000" => data <= "101000000"; when "0011111001" => data <= "011111111"; when "0011111010" => data <= "011101111"; when "0011111011" => data <= "011101111"; when "0011111100" => data <= "011101111"; when "0011111101" => data <= "011101111"; when "0011111110" => data <= "010110000"; when "0011111111" => data <= "010110001"; when "0100000000" => data <= "011101111"; when "0100000001" => data <= "011101111"; when "0100000010" => data <= "101110110"; when "0100000011" => data <= "101000000"; when "0100000100" => data <= "100011100"; when "0100000101" => data <= "100100001"; when "0100000110" => data <= "011111111"; when "0100000111" => data <= "101110110"; when "0100001000" => data <= "101000000"; when "0100001001" => data <= "100011110"; when "0100001010" => data <= "101000001"; when "0100001011" => data <= "011111111"; when "0100001100" => data <= "011111110"; when "0100001101" => data <= "011111110"; when "0100001110" => data <= "011111110"; when "0100001111" => data <= "011111110"; when "0100010000" => data <= "010010000"; when "0100010001" => data <= "000011001"; when "0100010010" => data <= "010010001"; when "0100010011" => data <= "000010100"; when "0100010100" => data <= "000100010"; when others => data <= (others =>'0'); end case; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Engineer: Mike Field <hamster@snap.net.nz< -- -- Module Name: adau1761_configuraiton_data - Behavioral -- Description: A script for the I3C2, which sends out I2c transactions to configure -- the ADAU1761 codec. -- -- See i3c2program for original source for script ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity adau1761_configuraiton_data is Port ( clk : in STD_LOGIC; address : in STD_LOGIC_VECTOR (9 downto 0); data : out STD_LOGIC_VECTOR (8 downto 0)); end adau1761_configuraiton_data; architecture Behavioral of adau1761_configuraiton_data is begin process(clk) begin if rising_edge(clk) then case address is when "0000000000" => data <= "011101111"; when "0000000001" => data <= "101110110"; when "0000000010" => data <= "101000000"; when "0000000011" => data <= "100000000"; when "0000000100" => data <= "100001110"; when "0000000101" => data <= "011111111"; when "0000000110" => data <= "101110110"; when "0000000111" => data <= "101000000"; when "0000001000" => data <= "100000010"; when "0000001001" => data <= "100000000"; when "0000001010" => data <= "101111101"; when "0000001011" => data <= "100000000"; when "0000001100" => data <= "100001100"; when "0000001101" => data <= "100100011"; when "0000001110" => data <= "100000001"; when "0000001111" => data <= "011111111"; when "0000010000" => data <= "011101111"; when "0000010001" => data <= "101110110"; when "0000010010" => data <= "101000000"; when "0000010011" => data <= "100000000"; when "0000010100" => data <= "100001111"; when "0000010101" => data <= "011111111"; when "0000010110" => data <= "011101111"; when "0000010111" => data <= "101110110"; when "0000011000" => data <= "101000000"; when "0000011001" => data <= "100010101"; when "0000011010" => data <= "100000001"; when "0000011011" => data <= "011111111"; when "0000011100" => data <= "101110110"; when "0000011101" => data <= "101000000"; when "0000011110" => data <= "100001010"; when "0000011111" => data <= "100000001"; when "0000100000" => data <= "011111111"; when "0000100001" => data <= "101110110"; when "0000100010" => data <= "101000000"; when "0000100011" => data <= "100001011"; when "0000100100" => data <= "100000101"; when "0000100101" => data <= "011111111"; when "0000100110" => data <= "101110110"; when "0000100111" => data <= "101000000"; when "0000101000" => data <= "100001100"; when "0000101001" => data <= "100000001"; when "0000101010" => data <= "011111111"; when "0000101011" => data <= "101110110"; when "0000101100" => data <= "101000000"; when "0000101101" => data <= "100001101"; when "0000101110" => data <= "100000101"; when "0000101111" => data <= "011111111"; when "0000110000" => data <= "101110110"; when "0000110001" => data <= "101000000"; when "0000110010" => data <= "100011100"; when "0000110011" => data <= "100100001"; when "0000110100" => data <= "011111111"; when "0000110101" => data <= "101110110"; when "0000110110" => data <= "101000000"; when "0000110111" => data <= "100011110"; when "0000111000" => data <= "101000001"; when "0000111001" => data <= "011111111"; when "0000111010" => data <= "101110110"; when "0000111011" => data <= "101000000"; when "0000111100" => data <= "100100011"; when "0000111101" => data <= "111100111"; when "0000111110" => data <= "011111111"; when "0000111111" => data <= "101110110"; when "0001000000" => data <= "101000000"; when "0001000001" => data <= "100100100"; when "0001000010" => data <= "111100111"; when "0001000011" => data <= "011111111"; when "0001000100" => data <= "101110110"; when "0001000101" => data <= "101000000"; when "0001000110" => data <= "100100101"; when "0001000111" => data <= "111100111"; when "0001001000" => data <= "011111111"; when "0001001001" => data <= "101110110"; when "0001001010" => data <= "101000000"; when "0001001011" => data <= "100100110"; when "0001001100" => data <= "111100111"; when "0001001101" => data <= "011111111"; when "0001001110" => data <= "101110110"; when "0001001111" => data <= "101000000"; when "0001010000" => data <= "100011001"; when "0001010001" => data <= "100000011"; when "0001010010" => data <= "011111111"; when "0001010011" => data <= "101110110"; when "0001010100" => data <= "101000000"; when "0001010101" => data <= "100101001"; when "0001010110" => data <= "100000011"; when "0001010111" => data <= "011111111"; when "0001011000" => data <= "101110110"; when "0001011001" => data <= "101000000"; when "0001011010" => data <= "100101010"; when "0001011011" => data <= "100000011"; when "0001011100" => data <= "011111111"; when "0001011101" => data <= "101110110"; when "0001011110" => data <= "101000000"; when "0001011111" => data <= "111110010"; when "0001100000" => data <= "100000001"; when "0001100001" => data <= "011111111"; when "0001100010" => data <= "101110110"; when "0001100011" => data <= "101000000"; when "0001100100" => data <= "111110011"; when "0001100101" => data <= "100000001"; when "0001100110" => data <= "011111111"; when "0001100111" => data <= "101110110"; when "0001101000" => data <= "101000000"; when "0001101001" => data <= "111111001"; when "0001101010" => data <= "101111111"; when "0001101011" => data <= "011111111"; when "0001101100" => data <= "101110110"; when "0001101101" => data <= "101000000"; when "0001101110" => data <= "111111010"; when "0001101111" => data <= "100000011"; when "0001110000" => data <= "011111111"; when "0001110001" => data <= "000010011"; when "0001110010" => data <= "011111110"; when "0001110011" => data <= "011111110"; when "0001110100" => data <= "011111110"; when "0001110101" => data <= "011111110"; when "0001110110" => data <= "011111110"; when "0001110111" => data <= "011111110"; when "0001111000" => data <= "101110110"; when "0001111001" => data <= "101000000"; when "0001111010" => data <= "100011100"; when "0001111011" => data <= "100100000"; when "0001111100" => data <= "011111111"; when "0001111101" => data <= "101110110"; when "0001111110" => data <= "101000000"; when "0001111111" => data <= "100011110"; when "0010000000" => data <= "101000000"; when "0010000001" => data <= "011111111"; when "0010000010" => data <= "011101111"; when "0010000011" => data <= "011101111"; when "0010000100" => data <= "011101111"; when "0010000101" => data <= "011101111"; when "0010000110" => data <= "010100000"; when "0010000111" => data <= "010100001"; when "0010001000" => data <= "011101111"; when "0010001001" => data <= "011101111"; when "0010001010" => data <= "101110110"; when "0010001011" => data <= "101000000"; when "0010001100" => data <= "100011100"; when "0010001101" => data <= "100100001"; when "0010001110" => data <= "011111111"; when "0010001111" => data <= "101110110"; when "0010010000" => data <= "101000000"; when "0010010001" => data <= "100011110"; when "0010010010" => data <= "101000001"; when "0010010011" => data <= "011111111"; when "0010010100" => data <= "011111110"; when "0010010101" => data <= "011111110"; when "0010010110" => data <= "011111110"; when "0010010111" => data <= "011111110"; when "0010011000" => data <= "010000000"; when "0010011001" => data <= "000010100"; when "0010011010" => data <= "010000001"; when "0010011011" => data <= "000011001"; when "0010011100" => data <= "000010011"; when "0010011101" => data <= "011111110"; when "0010011110" => data <= "011111110"; when "0010011111" => data <= "011111110"; when "0010100000" => data <= "101110110"; when "0010100001" => data <= "101000000"; when "0010100010" => data <= "100011100"; when "0010100011" => data <= "100100000"; when "0010100100" => data <= "011111111"; when "0010100101" => data <= "101110110"; when "0010100110" => data <= "101000000"; when "0010100111" => data <= "100011110"; when "0010101000" => data <= "101000000"; when "0010101001" => data <= "011111111"; when "0010101010" => data <= "011101111"; when "0010101011" => data <= "011101111"; when "0010101100" => data <= "011101111"; when "0010101101" => data <= "011101111"; when "0010101110" => data <= "010110000"; when "0010101111" => data <= "010100001"; when "0010110000" => data <= "011101111"; when "0010110001" => data <= "011101111"; when "0010110010" => data <= "101110110"; when "0010110011" => data <= "101000000"; when "0010110100" => data <= "100011100"; when "0010110101" => data <= "100100001"; when "0010110110" => data <= "011111111"; when "0010110111" => data <= "101110110"; when "0010111000" => data <= "101000000"; when "0010111001" => data <= "100011110"; when "0010111010" => data <= "101000001"; when "0010111011" => data <= "011111111"; when "0010111100" => data <= "011111110"; when "0010111101" => data <= "011111110"; when "0010111110" => data <= "011111110"; when "0010111111" => data <= "011111110"; when "0011000000" => data <= "010010000"; when "0011000001" => data <= "000001111"; when "0011000010" => data <= "010000001"; when "0011000011" => data <= "000011110"; when "0011000100" => data <= "000011000"; when "0011000101" => data <= "011111110"; when "0011000110" => data <= "011111110"; when "0011000111" => data <= "011111110"; when "0011001000" => data <= "101110110"; when "0011001001" => data <= "101000000"; when "0011001010" => data <= "100011100"; when "0011001011" => data <= "100100000"; when "0011001100" => data <= "011111111"; when "0011001101" => data <= "101110110"; when "0011001110" => data <= "101000000"; when "0011001111" => data <= "100011110"; when "0011010000" => data <= "101000000"; when "0011010001" => data <= "011111111"; when "0011010010" => data <= "011101111"; when "0011010011" => data <= "011101111"; when "0011010100" => data <= "011101111"; when "0011010101" => data <= "011101111"; when "0011010110" => data <= "010100000"; when "0011010111" => data <= "010110001"; when "0011011000" => data <= "011101111"; when "0011011001" => data <= "011101111"; when "0011011010" => data <= "101110110"; when "0011011011" => data <= "101000000"; when "0011011100" => data <= "100011100"; when "0011011101" => data <= "100100001"; when "0011011110" => data <= "011111111"; when "0011011111" => data <= "101110110"; when "0011100000" => data <= "101000000"; when "0011100001" => data <= "100011110"; when "0011100010" => data <= "101000001"; when "0011100011" => data <= "011111111"; when "0011100100" => data <= "011111110"; when "0011100101" => data <= "011111110"; when "0011100110" => data <= "011111110"; when "0011100111" => data <= "011111110"; when "0011101000" => data <= "010000000"; when "0011101001" => data <= "000000000"; when "0011101010" => data <= "010010001"; when "0011101011" => data <= "000001111"; when "0011101100" => data <= "000011101"; when "0011101101" => data <= "011111110"; when "0011101110" => data <= "011111110"; when "0011101111" => data <= "011111110"; when "0011110000" => data <= "101110110"; when "0011110001" => data <= "101000000"; when "0011110010" => data <= "100011100"; when "0011110011" => data <= "100100000"; when "0011110100" => data <= "011111111"; when "0011110101" => data <= "101110110"; when "0011110110" => data <= "101000000"; when "0011110111" => data <= "100011110"; when "0011111000" => data <= "101000000"; when "0011111001" => data <= "011111111"; when "0011111010" => data <= "011101111"; when "0011111011" => data <= "011101111"; when "0011111100" => data <= "011101111"; when "0011111101" => data <= "011101111"; when "0011111110" => data <= "010110000"; when "0011111111" => data <= "010110001"; when "0100000000" => data <= "011101111"; when "0100000001" => data <= "011101111"; when "0100000010" => data <= "101110110"; when "0100000011" => data <= "101000000"; when "0100000100" => data <= "100011100"; when "0100000101" => data <= "100100001"; when "0100000110" => data <= "011111111"; when "0100000111" => data <= "101110110"; when "0100001000" => data <= "101000000"; when "0100001001" => data <= "100011110"; when "0100001010" => data <= "101000001"; when "0100001011" => data <= "011111111"; when "0100001100" => data <= "011111110"; when "0100001101" => data <= "011111110"; when "0100001110" => data <= "011111110"; when "0100001111" => data <= "011111110"; when "0100010000" => data <= "010010000"; when "0100010001" => data <= "000011001"; when "0100010010" => data <= "010010001"; when "0100010011" => data <= "000010100"; when "0100010100" => data <= "000100010"; when others => data <= (others =>'0'); end case; end if; end process; end Behavioral;
entity tb_conv01 is end tb_conv01; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_conv01 is signal i : std_logic_vector(19 downto 0); signal o : std_logic_vector(31 downto 0); begin dut: entity work.conv01 port map (i => i, o => o); process begin i <= x"abcde"; wait for 1 ns; assert o = x"000_abcde" severity failure; wait; end process; end behav;
------------------------------------------------------------------------------- -- -- The Timer/Counter unit. -- -- $Id: timer-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $ -- -- All rights reserved -- ------------------------------------------------------------------------------- configuration t48_timer_rtl_c0 of t48_timer is for rtl end for; end t48_timer_rtl_c0;
library verilog; use verilog.vl_types.all; entity altera_merlin_slave_translator is generic( AV_ADDRESS_W : integer := 32; AV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W: integer := 4; AV_READLATENCY : integer := 1; AV_READ_WAIT_CYCLES: integer := 0; AV_WRITE_WAIT_CYCLES: integer := 0; AV_SETUP_WAIT_CYCLES: integer := 0; AV_DATA_HOLD_CYCLES: integer := 0; USE_READDATAVALID: integer := 1; USE_WAITREQUEST : integer := 1; USE_READRESPONSE: integer := 0; USE_WRITERESPONSE: integer := 0; AV_SYMBOLS_PER_WORD: integer := 4; AV_ADDRESS_SYMBOLS: integer := 0; AV_BURSTCOUNT_SYMBOLS: integer := 0; BITS_PER_WORD : vl_notype; UAV_ADDRESS_W : integer := 38; UAV_BURSTCOUNT_W: integer := 10; UAV_DATA_W : integer := 32; AV_CONSTANT_BURST_BEHAVIOR: integer := 0; UAV_CONSTANT_BURST_BEHAVIOR: integer := 0; CHIPSELECT_THROUGH_READLATENCY: integer := 0; USE_UAV_CLKEN : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES: integer := 0 ); port( clk : in vl_logic; reset : in vl_logic; uav_address : in vl_logic_vector; uav_writedata : in vl_logic_vector; uav_write : in vl_logic; uav_read : in vl_logic; uav_burstcount : in vl_logic_vector; uav_byteenable : in vl_logic_vector; uav_lock : in vl_logic; uav_debugaccess : in vl_logic; uav_clken : in vl_logic; uav_readdatavalid: out vl_logic; uav_waitrequest : out vl_logic; uav_readdata : out vl_logic_vector; uav_response : out vl_logic_vector(1 downto 0); uav_writeresponserequest: in vl_logic; uav_writeresponsevalid: out vl_logic; av_address : out vl_logic_vector; av_writedata : out vl_logic_vector; av_write : out vl_logic; av_read : out vl_logic; av_burstcount : out vl_logic_vector; av_byteenable : out vl_logic_vector; av_writebyteenable: out vl_logic_vector; av_begintransfer: out vl_logic; av_chipselect : out vl_logic; av_beginbursttransfer: out vl_logic; av_lock : out vl_logic; av_clken : out vl_logic; av_debugaccess : out vl_logic; av_outputenable : out vl_logic; av_readdata : in vl_logic_vector; av_readdatavalid: in vl_logic; av_waitrequest : in vl_logic; av_response : in vl_logic_vector(1 downto 0); av_writeresponserequest: out vl_logic; av_writeresponsevalid: in vl_logic ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of AV_ADDRESS_W : constant is 1; attribute mti_svvh_generic_type of AV_DATA_W : constant is 1; attribute mti_svvh_generic_type of AV_BURSTCOUNT_W : constant is 1; attribute mti_svvh_generic_type of AV_BYTEENABLE_W : constant is 1; attribute mti_svvh_generic_type of UAV_BYTEENABLE_W : constant is 1; attribute mti_svvh_generic_type of AV_READLATENCY : constant is 1; attribute mti_svvh_generic_type of AV_READ_WAIT_CYCLES : constant is 1; attribute mti_svvh_generic_type of AV_WRITE_WAIT_CYCLES : constant is 1; attribute mti_svvh_generic_type of AV_SETUP_WAIT_CYCLES : constant is 1; attribute mti_svvh_generic_type of AV_DATA_HOLD_CYCLES : constant is 1; attribute mti_svvh_generic_type of USE_READDATAVALID : constant is 1; attribute mti_svvh_generic_type of USE_WAITREQUEST : constant is 1; attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1; attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1; attribute mti_svvh_generic_type of AV_SYMBOLS_PER_WORD : constant is 1; attribute mti_svvh_generic_type of AV_ADDRESS_SYMBOLS : constant is 1; attribute mti_svvh_generic_type of AV_BURSTCOUNT_SYMBOLS : constant is 1; attribute mti_svvh_generic_type of BITS_PER_WORD : constant is 3; attribute mti_svvh_generic_type of UAV_ADDRESS_W : constant is 1; attribute mti_svvh_generic_type of UAV_BURSTCOUNT_W : constant is 1; attribute mti_svvh_generic_type of UAV_DATA_W : constant is 1; attribute mti_svvh_generic_type of AV_CONSTANT_BURST_BEHAVIOR : constant is 1; attribute mti_svvh_generic_type of UAV_CONSTANT_BURST_BEHAVIOR : constant is 1; attribute mti_svvh_generic_type of CHIPSELECT_THROUGH_READLATENCY : constant is 1; attribute mti_svvh_generic_type of USE_UAV_CLKEN : constant is 1; attribute mti_svvh_generic_type of AV_REQUIRE_UNALIGNED_ADDRESSES : constant is 1; end altera_merlin_slave_translator;
-- -*- vhdl -*- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- -- Cache Replacement Algorithm library ieee; use ieee.std_logic_1164.all; use work.cpu_l1mem_inst_cache_pkg.all; use work.cpu_l1mem_inst_cache_replace_pkg.all; entity cpu_l1mem_inst_cache_replace is port ( clk : in std_ulogic; rstn : in std_ulogic; cpu_l1mem_inst_cache_replace_ctrl_in : in cpu_l1mem_inst_cache_replace_ctrl_in_type; cpu_l1mem_inst_cache_replace_ctrl_out : out cpu_l1mem_inst_cache_replace_ctrl_out_type; cpu_l1mem_inst_cache_replace_dp_in : in cpu_l1mem_inst_cache_replace_dp_in_type; cpu_l1mem_inst_cache_replace_dp_out : out cpu_l1mem_inst_cache_replace_dp_out_type ); end;
library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity s1488_rnd is port( clock: in std_logic; input: in std_logic_vector(7 downto 0); output: out std_logic_vector(18 downto 0) ); end s1488_rnd; architecture behaviour of s1488_rnd is constant s000000: std_logic_vector(5 downto 0) := "111101"; constant s001110: std_logic_vector(5 downto 0) := "000010"; constant s011000: std_logic_vector(5 downto 0) := "011011"; constant s010000: std_logic_vector(5 downto 0) := "111110"; constant s010100: std_logic_vector(5 downto 0) := "111111"; constant s110011: std_logic_vector(5 downto 0) := "010001"; constant s010011: std_logic_vector(5 downto 0) := "010110"; constant s000100: std_logic_vector(5 downto 0) := "001011"; constant s100011: std_logic_vector(5 downto 0) := "001111"; constant s010110: std_logic_vector(5 downto 0) := "011110"; constant s010111: std_logic_vector(5 downto 0) := "101011"; constant s000111: std_logic_vector(5 downto 0) := "100001"; constant s101011: std_logic_vector(5 downto 0) := "110000"; constant s001111: std_logic_vector(5 downto 0) := "101111"; constant s111100: std_logic_vector(5 downto 0) := "011010"; constant s101100: std_logic_vector(5 downto 0) := "111000"; constant s001100: std_logic_vector(5 downto 0) := "110110"; constant s010001: std_logic_vector(5 downto 0) := "001000"; constant s011011: std_logic_vector(5 downto 0) := "000001"; constant s110110: std_logic_vector(5 downto 0) := "100100"; constant s011111: std_logic_vector(5 downto 0) := "001001"; constant s101110: std_logic_vector(5 downto 0) := "101001"; constant s010101: std_logic_vector(5 downto 0) := "100110"; constant s111110: std_logic_vector(5 downto 0) := "111011"; constant s000011: std_logic_vector(5 downto 0) := "011100"; constant s111010: std_logic_vector(5 downto 0) := "100011"; constant s011010: std_logic_vector(5 downto 0) := "100010"; constant s111011: std_logic_vector(5 downto 0) := "011000"; constant s100000: std_logic_vector(5 downto 0) := "000011"; constant s101000: std_logic_vector(5 downto 0) := "110111"; constant s110000: std_logic_vector(5 downto 0) := "010011"; constant s011110: std_logic_vector(5 downto 0) := "110010"; constant s010010: std_logic_vector(5 downto 0) := "000111"; constant s001010: std_logic_vector(5 downto 0) := "001100"; constant s000010: std_logic_vector(5 downto 0) := "110101"; constant s111000: std_logic_vector(5 downto 0) := "010100"; constant s100100: std_logic_vector(5 downto 0) := "000000"; constant s001000: std_logic_vector(5 downto 0) := "100111"; constant s001011: std_logic_vector(5 downto 0) := "011101"; constant s110100: std_logic_vector(5 downto 0) := "101101"; constant s100110: std_logic_vector(5 downto 0) := "100101"; constant s011101: std_logic_vector(5 downto 0) := "100000"; constant s000110: std_logic_vector(5 downto 0) := "111100"; constant s110010: std_logic_vector(5 downto 0) := "000100"; constant s011100: std_logic_vector(5 downto 0) := "110011"; constant s101010: std_logic_vector(5 downto 0) := "010111"; constant s100010: std_logic_vector(5 downto 0) := "111010"; constant s100111: std_logic_vector(5 downto 0) := "111001"; signal current_state, next_state: std_logic_vector(5 downto 0); begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= "------"; output <= "-------------------"; case current_state is when s000000 => if std_match(input, "0-11----") then next_state <= s000000; output <= "0100011010010010111"; elsif std_match(input, "0-01----") then next_state <= s000000; output <= "0000000011000100000"; elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0100011010010010111"; elsif std_match(input, "1-01----") then next_state <= s000000; output <= "0000000011000100000"; elsif std_match(input, "--00----") then next_state <= s000000; output <= "0000000010000110000"; elsif std_match(input, "--10----") then next_state <= s000000; output <= "0000000000000000000"; end if; when s001110 => if std_match(input, "00------") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0010100010001110000"; elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "1---0---") then next_state <= s011000; output <= "0000001010001010000"; elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000001010001010000"; elsif std_match(input, "11--1---") then next_state <= s010000; output <= "0010100010001110000"; end if; when s011000 => if std_match(input, "0-10-010") then next_state <= s000000; output <= "0000010000000000000"; elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000010000000000001"; elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000010000000000101"; elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000010000000000100"; elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000011000011011101"; elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000011000011011001"; elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "0000000000001111101"; elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "0000000000001111100"; elsif std_match(input, "0-00-000") then next_state <= s000000; output <= "0000000000001111001"; elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "0000000000001111000"; elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "0000010001001101101"; elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "0000010001001101100"; elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "0000010001001101000"; elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "0000010001001101001"; elsif std_match(input, "0-----01") then next_state <= s000000; output <= "0000001100111010011"; elsif std_match(input, "0-----11") then next_state <= s000000; output <= "0000001100111010010"; elsif std_match(input, "1-----11") then next_state <= s010100; output <= "0000001100111010010"; elsif std_match(input, "1-----01") then next_state <= s010100; output <= "0000001100111010011"; elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "0000010001001101101"; elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "0000010001001101100"; elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "0000010001001101001"; elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "0000010001001101000"; elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000011000011011101"; elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000011000011011001"; elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "0000000000001111101"; elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "0000000000001111100"; elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "0000000000001111001"; elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "0000000000001111000"; elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000010000000000001"; elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000010000000000000"; elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000010000000000100"; elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000010000000000101"; end if; when s010100 => if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000001010001010000"; end if; when s010011 => if std_match(input, "1----0--") then next_state <= s000100; output <= "0000001010000110011"; elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0000001010000110111"; elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010000110011"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010000110111"; end if; when s000100 => if std_match(input, "11---01-") then next_state <= s100011; output <= "0000001010001010000"; elsif std_match(input, "01---01-") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000001010001010000"; elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000001010001010000"; elsif std_match(input, "01---11-") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "10----1-") then next_state <= s010111; output <= "0000001010001010000"; elsif std_match(input, "00----1-") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "0-----0-") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000001010001010000"; end if; when s100011 => if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000011011001"; elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000001000011011001"; end if; when s110011 => if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "1-------") then next_state <= s000111; output <= "0000001010001010000"; end if; when s000111 => if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110"; elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000001000011011110"; elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000001000011011010"; end if; when s101011 => if std_match(input, "1-------") then next_state <= s001111; output <= "0000001010001010000"; elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; end if; when s001111 => if std_match(input, "1----0--") then next_state <= s000100; output <= "0001000000101011011"; elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0001000000101011111"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000101011111"; elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001000000101011011"; end if; when s010110 => if std_match(input, "1----1--") then next_state <= s111100; output <= "0100001010010010111"; elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001"; elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "0000010001001101000"; elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "0000000000001111000"; elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000010000000000000"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010010010111"; elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000010000000000000"; elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001"; elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "0000000000001111000"; elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "0000010001001101000"; end if; when s111100 => if std_match(input, "0-------") then next_state <= s000000; output <= "0000001110001010000"; elsif std_match(input, "1-------") then next_state <= s100011; output <= "0000001110001010000"; end if; when s101100 => if std_match(input, "1-------") then next_state <= s010110; output <= "0000001010001010000"; elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; end if; when s010111 => if std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000110010010"; elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000000110010110"; elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110010010"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000110010110"; end if; when s001100 => if std_match(input, "1----0--") then next_state <= s010001; output <= "0000001010001010000"; elsif std_match(input, "1----1--") then next_state <= s011011; output <= "0000001010001010000"; elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; end if; when s010001 => if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011110011"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011110111"; elsif std_match(input, "1----1--") then next_state <= s110110; output <= "0000001000011110111"; elsif std_match(input, "1----0--") then next_state <= s110110; output <= "0000001000011110011"; end if; when s110110 => if std_match(input, "1-------") then next_state <= s011111; output <= "0000001010001010000"; elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; end if; when s011111 => if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110111111"; elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110111110"; elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110111010"; elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110111011"; elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110111010"; elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110111011"; elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110111110"; elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110111111"; end if; when s101110 => if std_match(input, "1-------") then next_state <= s010101; output <= "0000001010001010000"; elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; end if; when s010101 => if std_match(input, "1----1--") then next_state <= s111110; output <= "0000001000001111101"; elsif std_match(input, "1----0--") then next_state <= s111110; output <= "0000001000001111001"; elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000001111001"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000001111101"; end if; when s111110 => if std_match(input, "00--1-0-") then next_state <= s000000; output <= "1000001010001010000"; elsif std_match(input, "01--1-0-") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "0---0-0-") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "1000001010001010000"; elsif std_match(input, "10--0---") then next_state <= s000011; output <= "0000001010001010000"; elsif std_match(input, "10--1--1") then next_state <= s111010; output <= "1000001010001010000"; elsif std_match(input, "10--1--0") then next_state <= s011010; output <= "1000001010001010000"; elsif std_match(input, "11--1-11") then next_state <= s111010; output <= "1000001010001010000"; elsif std_match(input, "11--0-11") then next_state <= s000011; output <= "0000001010001010000"; elsif std_match(input, "11--1-10") then next_state <= s011010; output <= "1000001010001010000"; elsif std_match(input, "11--0-10") then next_state <= s000011; output <= "0000001010001010000"; elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000001010001010000"; elsif std_match(input, "11--1-01") then next_state <= s000011; output <= "0000001010001010000"; elsif std_match(input, "11--0-0-") then next_state <= s000011; output <= "0000001010001010000"; end if; when s000011 => if std_match(input, "1----0-1") then next_state <= s001110; output <= "0000001010010010011"; elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "0000001010010110011"; elsif std_match(input, "1----1--") then next_state <= s001110; output <= "0000001010010010111"; elsif std_match(input, "0----0-1") then next_state <= s000000; output <= "0000001010010010011"; elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000001010010010111"; elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "0000001010010110011"; elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000001010010010111"; end if; when s111010 => if std_match(input, "1-------") then next_state <= s100000; output <= "0000001010010010011"; elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010010010011"; end if; when s100000 => if std_match(input, "00--1---") then next_state <= s000000; output <= "0000101010001010000"; elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0000001110001010000"; elsif std_match(input, "11--1---") then next_state <= s101000; output <= "0000001110001010000"; elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000101010001010000"; elsif std_match(input, "11--0---") then next_state <= s101000; output <= "0000001110001010000"; elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001110001010000"; elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000001010001010000"; end if; when s101000 => if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010000110011"; elsif std_match(input, "1-------") then next_state <= s010010; output <= "0000001010000110011"; end if; when s010010 => if std_match(input, "1---0---") then next_state <= s011110; output <= "0000001010001010000"; elsif std_match(input, "0---0---") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "0---1---") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000001010001010000"; end if; when s011110 => if std_match(input, "0-00-00-") then next_state <= s000000; output <= "0000000000001111000"; elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "0000000000001111001"; elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000010000000000001"; elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000010000000000000"; elsif std_match(input, "0--0-1--") then next_state <= s000000; output <= "0000001010010010111"; elsif std_match(input, "0--1-1--") then next_state <= s000000; output <= "0000001010010010111"; elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001"; elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "0000010001001101000"; elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "0000010001001101001"; elsif std_match(input, "1-0--1--") then next_state <= s100000; output <= "0000001010010010111"; elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "0000000000001111000"; elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "0000000000001111001"; elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "0000010001001101001"; elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "0000010001001101000"; elsif std_match(input, "1-10-1--") then next_state <= s100000; output <= "0000001010010010111"; elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000010000000000001"; elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000010000000000000"; elsif std_match(input, "1-11-1--") then next_state <= s100000; output <= "0000001010010010111"; elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001"; end if; when s000010 => if std_match(input, "1----0--") then next_state <= s011110; output <= "0001001010001010000"; elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000001010001010000"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000"; end if; when s001010 => if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010100010001"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101"; elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000001010100010001"; elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101"; end if; when s111000 => if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000001010001010000"; elsif std_match(input, "1---00--") then next_state <= s001000; output <= "0000001010001010000"; elsif std_match(input, "1---1---") then next_state <= s001000; output <= "0000001010001010000"; end if; when s001000 => if std_match(input, "1----0--") then next_state <= s100100; output <= "0000001000011011001"; elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101"; elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011001"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101"; end if; when s100100 => if std_match(input, "1-------") then next_state <= s001011; output <= "0001001010001010000"; elsif std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000"; end if; when s001011 => if std_match(input, "1----0--") then next_state <= s110100; output <= "0000001000011011010"; elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000001000011011110"; elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110"; end if; when s110100 => if std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000"; elsif std_match(input, "1-------") then next_state <= s011011; output <= "0001001010001010000"; end if; when s011011 => if std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000011010111"; elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000011010110"; elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000011010010"; elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000011010011"; elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000001000011010010"; elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000001000011010011"; elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000001000011010110"; elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000001000011010111"; end if; when s100110 => if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "1-------") then next_state <= s011101; output <= "0000001010001010000"; end if; when s011101 => if std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110011000"; elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011001"; elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110011101"; elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110011100"; elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110011101"; elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110011100"; elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110011000"; elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011001"; end if; when s110000 => if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000001111001"; elsif std_match(input, "1-------") then next_state <= s000110; output <= "0000001000001111001"; end if; when s000110 => if std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010001010000"; elsif std_match(input, "1---01--") then next_state <= s011000; output <= "0100001010001010000"; elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0001001010001010000"; elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0100001010001010000"; elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0001001010001010000"; end if; when s011010 => if std_match(input, "1----1--") then next_state <= s100000; output <= "0000001010010010111"; elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000001010100010001"; elsif std_match(input, "1----01-") then next_state <= s110010; output <= "0000001010100010000"; elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001010100010001"; elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001010100010000"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010010010111"; end if; when s110010 => if std_match(input, "1----00-") then next_state <= s011100; output <= "0000001010001010000"; elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000001010001010000"; elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000001010001010000"; elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000001010001010000"; elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; end if; when s011100 => if std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000111010111"; elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000111010110"; elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000111010011"; elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000111010010"; elsif std_match(input, "1----10-") then next_state <= s101010; output <= "0000001000111010110"; elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000001000111010111"; elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000001000111010011"; elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000001000111010010"; end if; when s101010 => if std_match(input, "1-------") then next_state <= s111010; output <= "0000001010001010000"; elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; end if; when s100010 => if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; elsif std_match(input, "1-------") then next_state <= s011010; output <= "0000001010001010000"; end if; when s111011 => if std_match(input, "1----0--") then next_state <= s100111; output <= "0000001010010110011"; elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010010110011"; elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010101010010010111"; elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0010101010010010111"; end if; when s100111 => if std_match(input, "1-------") then next_state <= s111011; output <= "0000001010001010000"; elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000"; end if; when s010000 => if std_match(input, "--------") then next_state <= s000000; output <= "0000001000011010010"; end if; when others => next_state <= "------"; output <= "-------------------"; end case; end process; end behaviour;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gI0Gib0Xo40tvaTEMw79aiJH1u4YEk6HVdqkbeCop9/2waoagY20R0hBuYHx56Xi3cH8QWvex6XO QV3vawSgqw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KoS1rv1CFUKYNXTl71AfETT1Kc5fYzKPPR0kXLN6Rix83Z8+HkHQ7xAG+RQ1+wYFYntMPFYXg+xl jYaYcsZdTVoy/pFQfFzFzIHMvEDyhGlxcCwJE1Sl1y2uiMCYwOlqGqbs4oqeC3o5WmQMaISJXEot laofg7eBOKIh5zVQBfA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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gCcy/fPwodNZ5ehA `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gI0Gib0Xo40tvaTEMw79aiJH1u4YEk6HVdqkbeCop9/2waoagY20R0hBuYHx56Xi3cH8QWvex6XO QV3vawSgqw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KoS1rv1CFUKYNXTl71AfETT1Kc5fYzKPPR0kXLN6Rix83Z8+HkHQ7xAG+RQ1+wYFYntMPFYXg+xl jYaYcsZdTVoy/pFQfFzFzIHMvEDyhGlxcCwJE1Sl1y2uiMCYwOlqGqbs4oqeC3o5WmQMaISJXEot laofg7eBOKIh5zVQBfA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nvHBfVLXEIDiVREK1ZtlLrZ7D2o8+j0PfBQlUywpqi0LlzVpakFF1+4oQpQsRCjkU6FiWgvIYEIQ xF3opsh3cA0gI37cHXNoyxKcLQxiBb2Dt5ILBIpVL/2lp5QxYdpueQnedGu56neNU/SdUK/337V9 TOPZhdfOWs0n9NO+6sHptKi0VUrQEbTdLyOPdpIvhpsiYtlGNt4H6j4UrXNCHEXrsRFrNNaL63L6 8A9bRCIq+R/MVFKYc7XGOwzyv2NvWJLzj8pWBtUQtsewQGRMkz+zKhrZYx9Pi6JkM3pg7prL1N2K nVfeZOjki/Toly6hp2nAp6bI1GZLcIhnkXFrqw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block vERJPdx2yaiBZPvdkozSOrF5HOgqt7Ky7CQ6WmgQMDyJGvZ/HgSlR6X4yONOLwnio7VEgT81lblo CsCnrdCzOuuwCgG2laf1xjkkb3zU4ZQnsAe32Rt5/hL2J5hXn3Xe1UN0lqFw7JHTWR84WXQLd5x3 SJohMIaugOcLRm0nptQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OLi0CblrDwZ0QzOLfc6fg5Rfw9iQF5lR1whM955YYKGPYYzsS7ozaU9fzcer/htJu88wCSAm9nY8 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gCcy/fPwodNZ5ehA `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gI0Gib0Xo40tvaTEMw79aiJH1u4YEk6HVdqkbeCop9/2waoagY20R0hBuYHx56Xi3cH8QWvex6XO QV3vawSgqw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KoS1rv1CFUKYNXTl71AfETT1Kc5fYzKPPR0kXLN6Rix83Z8+HkHQ7xAG+RQ1+wYFYntMPFYXg+xl jYaYcsZdTVoy/pFQfFzFzIHMvEDyhGlxcCwJE1Sl1y2uiMCYwOlqGqbs4oqeC3o5WmQMaISJXEot laofg7eBOKIh5zVQBfA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nvHBfVLXEIDiVREK1ZtlLrZ7D2o8+j0PfBQlUywpqi0LlzVpakFF1+4oQpQsRCjkU6FiWgvIYEIQ xF3opsh3cA0gI37cHXNoyxKcLQxiBb2Dt5ILBIpVL/2lp5QxYdpueQnedGu56neNU/SdUK/337V9 TOPZhdfOWs0n9NO+6sHptKi0VUrQEbTdLyOPdpIvhpsiYtlGNt4H6j4UrXNCHEXrsRFrNNaL63L6 8A9bRCIq+R/MVFKYc7XGOwzyv2NvWJLzj8pWBtUQtsewQGRMkz+zKhrZYx9Pi6JkM3pg7prL1N2K nVfeZOjki/Toly6hp2nAp6bI1GZLcIhnkXFrqw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block vERJPdx2yaiBZPvdkozSOrF5HOgqt7Ky7CQ6WmgQMDyJGvZ/HgSlR6X4yONOLwnio7VEgT81lblo CsCnrdCzOuuwCgG2laf1xjkkb3zU4ZQnsAe32Rt5/hL2J5hXn3Xe1UN0lqFw7JHTWR84WXQLd5x3 SJohMIaugOcLRm0nptQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OLi0CblrDwZ0QzOLfc6fg5Rfw9iQF5lR1whM955YYKGPYYzsS7ozaU9fzcer/htJu88wCSAm9nY8 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gCcy/fPwodNZ5ehA `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gI0Gib0Xo40tvaTEMw79aiJH1u4YEk6HVdqkbeCop9/2waoagY20R0hBuYHx56Xi3cH8QWvex6XO QV3vawSgqw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KoS1rv1CFUKYNXTl71AfETT1Kc5fYzKPPR0kXLN6Rix83Z8+HkHQ7xAG+RQ1+wYFYntMPFYXg+xl jYaYcsZdTVoy/pFQfFzFzIHMvEDyhGlxcCwJE1Sl1y2uiMCYwOlqGqbs4oqeC3o5WmQMaISJXEot laofg7eBOKIh5zVQBfA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nvHBfVLXEIDiVREK1ZtlLrZ7D2o8+j0PfBQlUywpqi0LlzVpakFF1+4oQpQsRCjkU6FiWgvIYEIQ xF3opsh3cA0gI37cHXNoyxKcLQxiBb2Dt5ILBIpVL/2lp5QxYdpueQnedGu56neNU/SdUK/337V9 TOPZhdfOWs0n9NO+6sHptKi0VUrQEbTdLyOPdpIvhpsiYtlGNt4H6j4UrXNCHEXrsRFrNNaL63L6 8A9bRCIq+R/MVFKYc7XGOwzyv2NvWJLzj8pWBtUQtsewQGRMkz+zKhrZYx9Pi6JkM3pg7prL1N2K nVfeZOjki/Toly6hp2nAp6bI1GZLcIhnkXFrqw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block vERJPdx2yaiBZPvdkozSOrF5HOgqt7Ky7CQ6WmgQMDyJGvZ/HgSlR6X4yONOLwnio7VEgT81lblo CsCnrdCzOuuwCgG2laf1xjkkb3zU4ZQnsAe32Rt5/hL2J5hXn3Xe1UN0lqFw7JHTWR84WXQLd5x3 SJohMIaugOcLRm0nptQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OLi0CblrDwZ0QzOLfc6fg5Rfw9iQF5lR1whM955YYKGPYYzsS7ozaU9fzcer/htJu88wCSAm9nY8 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gCcy/fPwodNZ5ehA `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gI0Gib0Xo40tvaTEMw79aiJH1u4YEk6HVdqkbeCop9/2waoagY20R0hBuYHx56Xi3cH8QWvex6XO QV3vawSgqw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KoS1rv1CFUKYNXTl71AfETT1Kc5fYzKPPR0kXLN6Rix83Z8+HkHQ7xAG+RQ1+wYFYntMPFYXg+xl jYaYcsZdTVoy/pFQfFzFzIHMvEDyhGlxcCwJE1Sl1y2uiMCYwOlqGqbs4oqeC3o5WmQMaISJXEot laofg7eBOKIh5zVQBfA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nvHBfVLXEIDiVREK1ZtlLrZ7D2o8+j0PfBQlUywpqi0LlzVpakFF1+4oQpQsRCjkU6FiWgvIYEIQ xF3opsh3cA0gI37cHXNoyxKcLQxiBb2Dt5ILBIpVL/2lp5QxYdpueQnedGu56neNU/SdUK/337V9 TOPZhdfOWs0n9NO+6sHptKi0VUrQEbTdLyOPdpIvhpsiYtlGNt4H6j4UrXNCHEXrsRFrNNaL63L6 8A9bRCIq+R/MVFKYc7XGOwzyv2NvWJLzj8pWBtUQtsewQGRMkz+zKhrZYx9Pi6JkM3pg7prL1N2K nVfeZOjki/Toly6hp2nAp6bI1GZLcIhnkXFrqw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block vERJPdx2yaiBZPvdkozSOrF5HOgqt7Ky7CQ6WmgQMDyJGvZ/HgSlR6X4yONOLwnio7VEgT81lblo CsCnrdCzOuuwCgG2laf1xjkkb3zU4ZQnsAe32Rt5/hL2J5hXn3Xe1UN0lqFw7JHTWR84WXQLd5x3 SJohMIaugOcLRm0nptQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OLi0CblrDwZ0QzOLfc6fg5Rfw9iQF5lR1whM955YYKGPYYzsS7ozaU9fzcer/htJu88wCSAm9nY8 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gCcy/fPwodNZ5ehA `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gI0Gib0Xo40tvaTEMw79aiJH1u4YEk6HVdqkbeCop9/2waoagY20R0hBuYHx56Xi3cH8QWvex6XO QV3vawSgqw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KoS1rv1CFUKYNXTl71AfETT1Kc5fYzKPPR0kXLN6Rix83Z8+HkHQ7xAG+RQ1+wYFYntMPFYXg+xl jYaYcsZdTVoy/pFQfFzFzIHMvEDyhGlxcCwJE1Sl1y2uiMCYwOlqGqbs4oqeC3o5WmQMaISJXEot laofg7eBOKIh5zVQBfA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nvHBfVLXEIDiVREK1ZtlLrZ7D2o8+j0PfBQlUywpqi0LlzVpakFF1+4oQpQsRCjkU6FiWgvIYEIQ xF3opsh3cA0gI37cHXNoyxKcLQxiBb2Dt5ILBIpVL/2lp5QxYdpueQnedGu56neNU/SdUK/337V9 TOPZhdfOWs0n9NO+6sHptKi0VUrQEbTdLyOPdpIvhpsiYtlGNt4H6j4UrXNCHEXrsRFrNNaL63L6 8A9bRCIq+R/MVFKYc7XGOwzyv2NvWJLzj8pWBtUQtsewQGRMkz+zKhrZYx9Pi6JkM3pg7prL1N2K nVfeZOjki/Toly6hp2nAp6bI1GZLcIhnkXFrqw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block vERJPdx2yaiBZPvdkozSOrF5HOgqt7Ky7CQ6WmgQMDyJGvZ/HgSlR6X4yONOLwnio7VEgT81lblo CsCnrdCzOuuwCgG2laf1xjkkb3zU4ZQnsAe32Rt5/hL2J5hXn3Xe1UN0lqFw7JHTWR84WXQLd5x3 SJohMIaugOcLRm0nptQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OLi0CblrDwZ0QzOLfc6fg5Rfw9iQF5lR1whM955YYKGPYYzsS7ozaU9fzcer/htJu88wCSAm9nY8 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gCcy/fPwodNZ5ehA `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gI0Gib0Xo40tvaTEMw79aiJH1u4YEk6HVdqkbeCop9/2waoagY20R0hBuYHx56Xi3cH8QWvex6XO QV3vawSgqw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KoS1rv1CFUKYNXTl71AfETT1Kc5fYzKPPR0kXLN6Rix83Z8+HkHQ7xAG+RQ1+wYFYntMPFYXg+xl jYaYcsZdTVoy/pFQfFzFzIHMvEDyhGlxcCwJE1Sl1y2uiMCYwOlqGqbs4oqeC3o5WmQMaISJXEot laofg7eBOKIh5zVQBfA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nvHBfVLXEIDiVREK1ZtlLrZ7D2o8+j0PfBQlUywpqi0LlzVpakFF1+4oQpQsRCjkU6FiWgvIYEIQ xF3opsh3cA0gI37cHXNoyxKcLQxiBb2Dt5ILBIpVL/2lp5QxYdpueQnedGu56neNU/SdUK/337V9 TOPZhdfOWs0n9NO+6sHptKi0VUrQEbTdLyOPdpIvhpsiYtlGNt4H6j4UrXNCHEXrsRFrNNaL63L6 8A9bRCIq+R/MVFKYc7XGOwzyv2NvWJLzj8pWBtUQtsewQGRMkz+zKhrZYx9Pi6JkM3pg7prL1N2K nVfeZOjki/Toly6hp2nAp6bI1GZLcIhnkXFrqw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block vERJPdx2yaiBZPvdkozSOrF5HOgqt7Ky7CQ6WmgQMDyJGvZ/HgSlR6X4yONOLwnio7VEgT81lblo CsCnrdCzOuuwCgG2laf1xjkkb3zU4ZQnsAe32Rt5/hL2J5hXn3Xe1UN0lqFw7JHTWR84WXQLd5x3 SJohMIaugOcLRm0nptQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OLi0CblrDwZ0QzOLfc6fg5Rfw9iQF5lR1whM955YYKGPYYzsS7ozaU9fzcer/htJu88wCSAm9nY8 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gCcy/fPwodNZ5ehA `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gI0Gib0Xo40tvaTEMw79aiJH1u4YEk6HVdqkbeCop9/2waoagY20R0hBuYHx56Xi3cH8QWvex6XO QV3vawSgqw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KoS1rv1CFUKYNXTl71AfETT1Kc5fYzKPPR0kXLN6Rix83Z8+HkHQ7xAG+RQ1+wYFYntMPFYXg+xl jYaYcsZdTVoy/pFQfFzFzIHMvEDyhGlxcCwJE1Sl1y2uiMCYwOlqGqbs4oqeC3o5WmQMaISJXEot laofg7eBOKIh5zVQBfA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nvHBfVLXEIDiVREK1ZtlLrZ7D2o8+j0PfBQlUywpqi0LlzVpakFF1+4oQpQsRCjkU6FiWgvIYEIQ xF3opsh3cA0gI37cHXNoyxKcLQxiBb2Dt5ILBIpVL/2lp5QxYdpueQnedGu56neNU/SdUK/337V9 TOPZhdfOWs0n9NO+6sHptKi0VUrQEbTdLyOPdpIvhpsiYtlGNt4H6j4UrXNCHEXrsRFrNNaL63L6 8A9bRCIq+R/MVFKYc7XGOwzyv2NvWJLzj8pWBtUQtsewQGRMkz+zKhrZYx9Pi6JkM3pg7prL1N2K nVfeZOjki/Toly6hp2nAp6bI1GZLcIhnkXFrqw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block vERJPdx2yaiBZPvdkozSOrF5HOgqt7Ky7CQ6WmgQMDyJGvZ/HgSlR6X4yONOLwnio7VEgT81lblo CsCnrdCzOuuwCgG2laf1xjkkb3zU4ZQnsAe32Rt5/hL2J5hXn3Xe1UN0lqFw7JHTWR84WXQLd5x3 SJohMIaugOcLRm0nptQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OLi0CblrDwZ0QzOLfc6fg5Rfw9iQF5lR1whM955YYKGPYYzsS7ozaU9fzcer/htJu88wCSAm9nY8 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gCcy/fPwodNZ5ehA `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gI0Gib0Xo40tvaTEMw79aiJH1u4YEk6HVdqkbeCop9/2waoagY20R0hBuYHx56Xi3cH8QWvex6XO QV3vawSgqw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KoS1rv1CFUKYNXTl71AfETT1Kc5fYzKPPR0kXLN6Rix83Z8+HkHQ7xAG+RQ1+wYFYntMPFYXg+xl jYaYcsZdTVoy/pFQfFzFzIHMvEDyhGlxcCwJE1Sl1y2uiMCYwOlqGqbs4oqeC3o5WmQMaISJXEot laofg7eBOKIh5zVQBfA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nvHBfVLXEIDiVREK1ZtlLrZ7D2o8+j0PfBQlUywpqi0LlzVpakFF1+4oQpQsRCjkU6FiWgvIYEIQ xF3opsh3cA0gI37cHXNoyxKcLQxiBb2Dt5ILBIpVL/2lp5QxYdpueQnedGu56neNU/SdUK/337V9 TOPZhdfOWs0n9NO+6sHptKi0VUrQEbTdLyOPdpIvhpsiYtlGNt4H6j4UrXNCHEXrsRFrNNaL63L6 8A9bRCIq+R/MVFKYc7XGOwzyv2NvWJLzj8pWBtUQtsewQGRMkz+zKhrZYx9Pi6JkM3pg7prL1N2K nVfeZOjki/Toly6hp2nAp6bI1GZLcIhnkXFrqw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block vERJPdx2yaiBZPvdkozSOrF5HOgqt7Ky7CQ6WmgQMDyJGvZ/HgSlR6X4yONOLwnio7VEgT81lblo CsCnrdCzOuuwCgG2laf1xjkkb3zU4ZQnsAe32Rt5/hL2J5hXn3Xe1UN0lqFw7JHTWR84WXQLd5x3 SJohMIaugOcLRm0nptQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OLi0CblrDwZ0QzOLfc6fg5Rfw9iQF5lR1whM955YYKGPYYzsS7ozaU9fzcer/htJu88wCSAm9nY8 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gCcy/fPwodNZ5ehA `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gI0Gib0Xo40tvaTEMw79aiJH1u4YEk6HVdqkbeCop9/2waoagY20R0hBuYHx56Xi3cH8QWvex6XO QV3vawSgqw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KoS1rv1CFUKYNXTl71AfETT1Kc5fYzKPPR0kXLN6Rix83Z8+HkHQ7xAG+RQ1+wYFYntMPFYXg+xl jYaYcsZdTVoy/pFQfFzFzIHMvEDyhGlxcCwJE1Sl1y2uiMCYwOlqGqbs4oqeC3o5WmQMaISJXEot laofg7eBOKIh5zVQBfA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nvHBfVLXEIDiVREK1ZtlLrZ7D2o8+j0PfBQlUywpqi0LlzVpakFF1+4oQpQsRCjkU6FiWgvIYEIQ xF3opsh3cA0gI37cHXNoyxKcLQxiBb2Dt5ILBIpVL/2lp5QxYdpueQnedGu56neNU/SdUK/337V9 TOPZhdfOWs0n9NO+6sHptKi0VUrQEbTdLyOPdpIvhpsiYtlGNt4H6j4UrXNCHEXrsRFrNNaL63L6 8A9bRCIq+R/MVFKYc7XGOwzyv2NvWJLzj8pWBtUQtsewQGRMkz+zKhrZYx9Pi6JkM3pg7prL1N2K nVfeZOjki/Toly6hp2nAp6bI1GZLcIhnkXFrqw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block vERJPdx2yaiBZPvdkozSOrF5HOgqt7Ky7CQ6WmgQMDyJGvZ/HgSlR6X4yONOLwnio7VEgT81lblo CsCnrdCzOuuwCgG2laf1xjkkb3zU4ZQnsAe32Rt5/hL2J5hXn3Xe1UN0lqFw7JHTWR84WXQLd5x3 SJohMIaugOcLRm0nptQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OLi0CblrDwZ0QzOLfc6fg5Rfw9iQF5lR1whM955YYKGPYYzsS7ozaU9fzcer/htJu88wCSAm9nY8 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------------------------------------------------------------------------------------------------------------------------ -- Simple Port I/O valid pulse counter -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2011-09-14 V0.01 zelenkaj Extract from portio.vhd ------------------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity portio_cnt is generic ( maxVal : integer := 50 --clock ticks of pcp_clk ); port ( clk : in std_logic; rst : in std_logic; pulse : in std_logic; valid : out std_logic ); end entity portio_cnt; architecture rtl of portio_cnt is signal cnt : integer range 0 to maxVal-2; signal tc, en : std_logic; begin genCnter : if maxVal > 1 generate tc <= '1' when cnt = maxVal-2 else '0'; valid <= en or pulse; counter : process(clk, rst) begin if rst = '1' then cnt <= 0; elsif clk = '1' and clk'event then if tc = '1' then cnt <= 0; elsif en = '1' then cnt <= cnt + 1; else cnt <= 0; end if; end if; end process; enGen : process(clk, rst) begin if rst = '1' then en <= '0'; elsif clk = '1' and clk'event then if pulse = '1' then en <= '1'; elsif tc = '1' then en <= '0'; end if; end if; end process; end generate; genSimple : if maxVal = 1 generate valid <= pulse; end generate; end architecture rtl;
------------------------------------------------------------------------------------------------------------------------ -- Simple Port I/O valid pulse counter -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2011-09-14 V0.01 zelenkaj Extract from portio.vhd ------------------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity portio_cnt is generic ( maxVal : integer := 50 --clock ticks of pcp_clk ); port ( clk : in std_logic; rst : in std_logic; pulse : in std_logic; valid : out std_logic ); end entity portio_cnt; architecture rtl of portio_cnt is signal cnt : integer range 0 to maxVal-2; signal tc, en : std_logic; begin genCnter : if maxVal > 1 generate tc <= '1' when cnt = maxVal-2 else '0'; valid <= en or pulse; counter : process(clk, rst) begin if rst = '1' then cnt <= 0; elsif clk = '1' and clk'event then if tc = '1' then cnt <= 0; elsif en = '1' then cnt <= cnt + 1; else cnt <= 0; end if; end if; end process; enGen : process(clk, rst) begin if rst = '1' then en <= '0'; elsif clk = '1' and clk'event then if pulse = '1' then en <= '1'; elsif tc = '1' then en <= '0'; end if; end if; end process; end generate; genSimple : if maxVal = 1 generate valid <= pulse; end generate; end architecture rtl;
------------------------------------------------------------------------------------------------------------------------ -- Simple Port I/O valid pulse counter -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2011-09-14 V0.01 zelenkaj Extract from portio.vhd ------------------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity portio_cnt is generic ( maxVal : integer := 50 --clock ticks of pcp_clk ); port ( clk : in std_logic; rst : in std_logic; pulse : in std_logic; valid : out std_logic ); end entity portio_cnt; architecture rtl of portio_cnt is signal cnt : integer range 0 to maxVal-2; signal tc, en : std_logic; begin genCnter : if maxVal > 1 generate tc <= '1' when cnt = maxVal-2 else '0'; valid <= en or pulse; counter : process(clk, rst) begin if rst = '1' then cnt <= 0; elsif clk = '1' and clk'event then if tc = '1' then cnt <= 0; elsif en = '1' then cnt <= cnt + 1; else cnt <= 0; end if; end if; end process; enGen : process(clk, rst) begin if rst = '1' then en <= '0'; elsif clk = '1' and clk'event then if pulse = '1' then en <= '1'; elsif tc = '1' then en <= '0'; end if; end if; end process; end generate; genSimple : if maxVal = 1 generate valid <= pulse; end generate; end architecture rtl;
--============================================================================= -- This file is part of FPGA_NEURAL-Network. -- -- FPGA_NEURAL-Network is free software: you can redistribute it and/or -- modify it under the terms of the GNU General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- FPGA_NEURAL-Network is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with FPGA_NEURAL-Network. -- if not, see <http://www.gnu.org/licenses/>. --============================================================================= -- FILE NAME : INPUT_ROM.vhd -- PROJECT : FPGA_NEURAL-Network -- ENTITY : INPUT_ROM -- ARCHITECTURE : rtl --============================================================================= -- AUTORS(s) : Agostini, N; -- DEPARTMENT : Electrical Engineering (UFRGS) -- DATE : Dec 14, 2014 --============================================================================= -- Description: -- --============================================================================= library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- is the to unsigned really required???? use work.fixed_pkg.all; -- ieee_proposed for compatibility version use work.NN_TYPES_pkg.all; use work.INPUT_ROM_pkg.all; --============================================================================= -- Entity declaration for INPUT_ROM --============================================================================= entity INPUT_ROM is port ( clk : in std_logic; SAMPLE_NUMBER : in std_logic_vector (7 downto 0); SELECTED_INPUT : out ARRAY_OF_SFIXED ); end INPUT_ROM; --============================================================================= -- architecture declaration --============================================================================= architecture RTL of INPUT_ROM is -- Constants constant INPUTS_TABLE : INPUT_TABLE(0 to SAMPLE_SIZE-1) := ( (to_sfixed(0.9595,1,L_SIZE), to_sfixed(0.2948,1,L_SIZE), to_sfixed(0.7523,1,L_SIZE), to_sfixed(0.5200,1,L_SIZE), to_sfixed(0.7840,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.6024,1,L_SIZE), to_sfixed(0.4242,1,L_SIZE), to_sfixed(0.6397,1,L_SIZE), to_sfixed(0.4338,1,L_SIZE), to_sfixed(0.6082,1,L_SIZE), to_sfixed(0.9800,1,L_SIZE), to_sfixed(0.6339,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.8901,1,L_SIZE), to_sfixed(0.3069,1,L_SIZE), to_sfixed(0.6625,1,L_SIZE), to_sfixed(0.3733,1,L_SIZE), to_sfixed(0.6173,1,L_SIZE), to_sfixed(0.6830,1,L_SIZE), to_sfixed(0.5433,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.3575,1,L_SIZE), to_sfixed(0.3369,1,L_SIZE), to_sfixed(0.6140,1,L_SIZE), to_sfixed(0.8500,1,L_SIZE), to_sfixed(0.6250,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.8874,1,L_SIZE), to_sfixed(0.4069,1,L_SIZE), to_sfixed(0.8266,1,L_SIZE), to_sfixed(0.6200,1,L_SIZE), to_sfixed(0.6235,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.6378,1,L_SIZE), to_sfixed(0.4545,1,L_SIZE), to_sfixed(0.7849,1,L_SIZE), to_sfixed(0.4369,1,L_SIZE), to_sfixed(0.6023,1,L_SIZE), to_sfixed(0.7925,1,L_SIZE), to_sfixed(0.7054,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9690,1,L_SIZE), to_sfixed(0.3362,1,L_SIZE), to_sfixed(0.7740,1,L_SIZE), to_sfixed(0.5600,1,L_SIZE), to_sfixed(0.6975,1,L_SIZE), to_sfixed(0.9923,1,L_SIZE), to_sfixed(0.6870,1,L_SIZE), to_sfixed(0.3636,1,L_SIZE), to_sfixed(0.6089,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.5029,1,L_SIZE), to_sfixed(0.8625,1,L_SIZE), to_sfixed(0.8810,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.8928,1,L_SIZE), to_sfixed(0.4466,1,L_SIZE), to_sfixed(0.8885,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.7284,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.5295,1,L_SIZE), to_sfixed(0.5909,1,L_SIZE), to_sfixed(0.5084,1,L_SIZE), to_sfixed(0.3323,1,L_SIZE), to_sfixed(0.6082,1,L_SIZE), to_sfixed(0.7325,1,L_SIZE), to_sfixed(0.4375,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9575,1,L_SIZE), to_sfixed(0.3034,1,L_SIZE), to_sfixed(0.7585,1,L_SIZE), to_sfixed(0.5067,1,L_SIZE), to_sfixed(0.6914,1,L_SIZE), to_sfixed(0.8428,1,L_SIZE), to_sfixed(0.6673,1,L_SIZE), to_sfixed(0.5152,1,L_SIZE), to_sfixed(0.5503,1,L_SIZE), to_sfixed(0.5192,1,L_SIZE), to_sfixed(0.6140,1,L_SIZE), to_sfixed(0.7125,1,L_SIZE), to_sfixed(0.8631,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9703,1,L_SIZE), to_sfixed(0.3224,1,L_SIZE), to_sfixed(0.7585,1,L_SIZE), to_sfixed(0.4867,1,L_SIZE), to_sfixed(0.5926,1,L_SIZE), to_sfixed(0.6443,1,L_SIZE), to_sfixed(0.4961,1,L_SIZE), to_sfixed(0.4545,1,L_SIZE), to_sfixed(0.5531,1,L_SIZE), to_sfixed(0.4038,1,L_SIZE), to_sfixed(0.5965,1,L_SIZE), to_sfixed(0.8950,1,L_SIZE), to_sfixed(0.7679,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9481,1,L_SIZE), to_sfixed(0.3707,1,L_SIZE), to_sfixed(0.8080,1,L_SIZE), to_sfixed(0.5867,1,L_SIZE), to_sfixed(0.7469,1,L_SIZE), to_sfixed(0.6701,1,L_SIZE), to_sfixed(0.4941,1,L_SIZE), to_sfixed(0.4697,1,L_SIZE), to_sfixed(0.3492,1,L_SIZE), to_sfixed(0.3885,1,L_SIZE), to_sfixed(0.6199,1,L_SIZE), to_sfixed(0.8950,1,L_SIZE), to_sfixed(0.7708,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.2828,1,L_SIZE), to_sfixed(0.6718,1,L_SIZE), to_sfixed(0.4667,1,L_SIZE), to_sfixed(0.5988,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.5866,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.5531,1,L_SIZE), to_sfixed(0.4000,1,L_SIZE), to_sfixed(0.6316,1,L_SIZE), to_sfixed(0.7125,1,L_SIZE), to_sfixed(0.6220,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9346,1,L_SIZE), to_sfixed(0.2328,1,L_SIZE), to_sfixed(0.7028,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.7680,1,L_SIZE), to_sfixed(0.6201,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.5168,1,L_SIZE), to_sfixed(0.5554,1,L_SIZE), to_sfixed(0.5906,1,L_SIZE), to_sfixed(0.8875,1,L_SIZE), to_sfixed(0.6220,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9508,1,L_SIZE), to_sfixed(0.3724,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.6481,1,L_SIZE), to_sfixed(0.7603,1,L_SIZE), to_sfixed(0.6535,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.6648,1,L_SIZE), to_sfixed(0.4423,1,L_SIZE), to_sfixed(0.7310,1,L_SIZE), to_sfixed(0.7925,1,L_SIZE), to_sfixed(0.8988,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9521,1,L_SIZE), to_sfixed(0.2552,1,L_SIZE), to_sfixed(0.7183,1,L_SIZE), to_sfixed(0.5600,1,L_SIZE), to_sfixed(0.5864,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.4783,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.4385,1,L_SIZE), to_sfixed(0.3846,1,L_SIZE), to_sfixed(0.6842,1,L_SIZE), to_sfixed(0.7050,1,L_SIZE), to_sfixed(0.7619,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9272,1,L_SIZE), to_sfixed(0.2983,1,L_SIZE), to_sfixed(0.7461,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.5494,1,L_SIZE), to_sfixed(0.6701,1,L_SIZE), to_sfixed(0.5433,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.5056,1,L_SIZE), to_sfixed(0.4308,1,L_SIZE), to_sfixed(0.6725,1,L_SIZE), to_sfixed(0.7250,1,L_SIZE), to_sfixed(0.7857,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9946,1,L_SIZE), to_sfixed(0.2983,1,L_SIZE), to_sfixed(0.7399,1,L_SIZE), to_sfixed(0.3800,1,L_SIZE), to_sfixed(0.5617,1,L_SIZE), to_sfixed(0.7990,1,L_SIZE), to_sfixed(0.7264,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.7849,1,L_SIZE), to_sfixed(0.4154,1,L_SIZE), to_sfixed(0.7310,1,L_SIZE), to_sfixed(0.6825,1,L_SIZE), to_sfixed(0.6845,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9697,1,L_SIZE), to_sfixed(0.3224,1,L_SIZE), to_sfixed(0.7368,1,L_SIZE), to_sfixed(0.4000,1,L_SIZE), to_sfixed(0.6296,1,L_SIZE), to_sfixed(0.8505,1,L_SIZE), to_sfixed(0.7165,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.8268,1,L_SIZE), to_sfixed(0.5769,1,L_SIZE), to_sfixed(0.7018,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.9208,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9191,1,L_SIZE), to_sfixed(0.3121,1,L_SIZE), to_sfixed(0.8359,1,L_SIZE), to_sfixed(0.5733,1,L_SIZE), to_sfixed(0.6914,1,L_SIZE), to_sfixed(0.7345,1,L_SIZE), to_sfixed(0.5728,1,L_SIZE), to_sfixed(0.4545,1,L_SIZE), to_sfixed(0.4078,1,L_SIZE), to_sfixed(0.5615,1,L_SIZE), to_sfixed(0.7485,1,L_SIZE), to_sfixed(0.7200,1,L_SIZE), to_sfixed(0.7798,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9643,1,L_SIZE), to_sfixed(0.3310,1,L_SIZE), to_sfixed(0.8421,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.7407,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.6181,1,L_SIZE), to_sfixed(0.5000,1,L_SIZE), to_sfixed(0.5503,1,L_SIZE), to_sfixed(0.4769,1,L_SIZE), to_sfixed(0.6257,1,L_SIZE), to_sfixed(0.6625,1,L_SIZE), to_sfixed(0.7619,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9326,1,L_SIZE), to_sfixed(0.2707,1,L_SIZE), to_sfixed(0.8111,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.7099,1,L_SIZE), to_sfixed(0.7603,1,L_SIZE), to_sfixed(0.6693,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.4804,1,L_SIZE), to_sfixed(0.5077,1,L_SIZE), to_sfixed(0.6608,1,L_SIZE), to_sfixed(0.6425,1,L_SIZE), to_sfixed(0.6726,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9568,1,L_SIZE), to_sfixed(0.2741,1,L_SIZE), to_sfixed(0.7678,1,L_SIZE), to_sfixed(0.5500,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.8505,1,L_SIZE), to_sfixed(0.7736,1,L_SIZE), to_sfixed(0.4848,1,L_SIZE), to_sfixed(0.5196,1,L_SIZE), to_sfixed(0.6692,1,L_SIZE), to_sfixed(0.7193,1,L_SIZE), to_sfixed(0.7050,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9198,1,L_SIZE), to_sfixed(0.5345,1,L_SIZE), to_sfixed(0.7926,1,L_SIZE), to_sfixed(0.5067,1,L_SIZE), to_sfixed(0.7160,1,L_SIZE), to_sfixed(0.6959,1,L_SIZE), to_sfixed(0.5965,1,L_SIZE), to_sfixed(0.2576,1,L_SIZE), to_sfixed(0.4637,1,L_SIZE), to_sfixed(0.3923,1,L_SIZE), to_sfixed(0.5614,1,L_SIZE), to_sfixed(0.8400,1,L_SIZE), to_sfixed(0.5030,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)), (to_sfixed(0.9481,1,L_SIZE), to_sfixed(0.2810,1,L_SIZE), to_sfixed(0.7059,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.7778,1,L_SIZE), to_sfixed(0.7732,1,L_SIZE), to_sfixed(0.6240,1,L_SIZE), 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to_sfixed(0.4381,1,L_SIZE), to_sfixed(0.1280,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.2402,1,L_SIZE), to_sfixed(0.5885,1,L_SIZE), to_sfixed(0.3158,1,L_SIZE), to_sfixed(0.4650,1,L_SIZE), to_sfixed(0.3720,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8982,1,L_SIZE), to_sfixed(0.5586,1,L_SIZE), to_sfixed(0.7368,1,L_SIZE), to_sfixed(0.7167,1,L_SIZE), to_sfixed(0.5679,1,L_SIZE), to_sfixed(0.4974,1,L_SIZE), to_sfixed(0.1496,1,L_SIZE), to_sfixed(0.6818,1,L_SIZE), to_sfixed(0.3492,1,L_SIZE), to_sfixed(0.6477,1,L_SIZE), to_sfixed(0.3216,1,L_SIZE), to_sfixed(0.4050,1,L_SIZE), to_sfixed(0.3869,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8820,1,L_SIZE), to_sfixed(0.6724,1,L_SIZE), to_sfixed(0.7307,1,L_SIZE), to_sfixed(0.7167,1,L_SIZE), to_sfixed(0.6975,1,L_SIZE), to_sfixed(0.3634,1,L_SIZE), to_sfixed(0.2736,1,L_SIZE), to_sfixed(0.5152,1,L_SIZE), to_sfixed(0.3184,1,L_SIZE), to_sfixed(0.7231,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.3325,1,L_SIZE), to_sfixed(0.3274,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9103,1,L_SIZE), to_sfixed(0.5379,1,L_SIZE), to_sfixed(0.8111,1,L_SIZE), to_sfixed(0.8000,1,L_SIZE), to_sfixed(0.7593,1,L_SIZE), to_sfixed(0.3608,1,L_SIZE), to_sfixed(0.3091,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.3492,1,L_SIZE), to_sfixed(0.6615,1,L_SIZE), to_sfixed(0.3450,1,L_SIZE), to_sfixed(0.3250,1,L_SIZE), to_sfixed(0.2976,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8624,1,L_SIZE), to_sfixed(0.4603,1,L_SIZE), to_sfixed(0.7678,1,L_SIZE), to_sfixed(0.7333,1,L_SIZE), to_sfixed(0.6914,1,L_SIZE), to_sfixed(0.3814,1,L_SIZE), to_sfixed(0.2677,1,L_SIZE), to_sfixed(0.3636,1,L_SIZE), to_sfixed(0.3520,1,L_SIZE), to_sfixed(0.8308,1,L_SIZE), to_sfixed(0.2807,1,L_SIZE), to_sfixed(0.3675,1,L_SIZE), to_sfixed(0.2857,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8840,1,L_SIZE), to_sfixed(0.3276,1,L_SIZE), to_sfixed(0.8514,1,L_SIZE), to_sfixed(0.8500,1,L_SIZE), to_sfixed(0.7160,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.2520,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.4358,1,L_SIZE), to_sfixed(0.5462,1,L_SIZE), to_sfixed(0.3567,1,L_SIZE), to_sfixed(0.3325,1,L_SIZE), to_sfixed(0.2530,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8921,1,L_SIZE), to_sfixed(0.5690,1,L_SIZE), to_sfixed(0.7059,1,L_SIZE), to_sfixed(0.6167,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.4639,1,L_SIZE), to_sfixed(0.1634,1,L_SIZE), to_sfixed(0.9242,1,L_SIZE), to_sfixed(0.5223,1,L_SIZE), to_sfixed(0.8092,1,L_SIZE), to_sfixed(0.3275,1,L_SIZE), to_sfixed(0.3775,1,L_SIZE), to_sfixed(0.4018,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8483,1,L_SIZE), to_sfixed(0.2224,1,L_SIZE), to_sfixed(0.6502,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.6358,1,L_SIZE), to_sfixed(0.3814,1,L_SIZE), to_sfixed(0.1142,1,L_SIZE), to_sfixed(0.8030,1,L_SIZE), to_sfixed(0.3911,1,L_SIZE), to_sfixed(0.5846,1,L_SIZE), to_sfixed(0.3392,1,L_SIZE), to_sfixed(0.3875,1,L_SIZE), to_sfixed(0.3810,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8881,1,L_SIZE), to_sfixed(0.8948,1,L_SIZE), to_sfixed(0.7183,1,L_SIZE), to_sfixed(0.7333,1,L_SIZE), to_sfixed(0.5741,1,L_SIZE), to_sfixed(0.4485,1,L_SIZE), to_sfixed(0.1240,1,L_SIZE), to_sfixed(0.9242,1,L_SIZE), to_sfixed(0.4330,1,L_SIZE), to_sfixed(0.6077,1,L_SIZE), to_sfixed(0.3509,1,L_SIZE), to_sfixed(0.3700,1,L_SIZE), to_sfixed(0.4315,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9332,1,L_SIZE), to_sfixed(0.7103,1,L_SIZE), to_sfixed(0.7368,1,L_SIZE), to_sfixed(0.6500,1,L_SIZE), to_sfixed(0.5494,1,L_SIZE), to_sfixed(0.4639,1,L_SIZE), to_sfixed(0.1634,1,L_SIZE), to_sfixed(0.7273,1,L_SIZE), to_sfixed(0.4358,1,L_SIZE), to_sfixed(0.6931,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.4100,1,L_SIZE), to_sfixed(0.2857,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8395,1,L_SIZE), to_sfixed(0.5224,1,L_SIZE), to_sfixed(0.8173,1,L_SIZE), to_sfixed(0.9000,1,L_SIZE), to_sfixed(0.5988,1,L_SIZE), to_sfixed(0.4897,1,L_SIZE), to_sfixed(0.1142,1,L_SIZE), to_sfixed(0.9545,1,L_SIZE), to_sfixed(0.3184,1,L_SIZE), to_sfixed(0.5769,1,L_SIZE), to_sfixed(0.3918,1,L_SIZE), to_sfixed(0.4325,1,L_SIZE), to_sfixed(0.5238,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9670,1,L_SIZE), to_sfixed(0.2897,1,L_SIZE), to_sfixed(0.8359,1,L_SIZE), to_sfixed(0.8333,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.2579,1,L_SIZE), to_sfixed(0.8030,1,L_SIZE), to_sfixed(0.7542,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.4900,1,L_SIZE), to_sfixed(0.3929,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9090,1,L_SIZE), to_sfixed(0.2879,1,L_SIZE), to_sfixed(0.8173,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.5494,1,L_SIZE), to_sfixed(0.6701,1,L_SIZE), to_sfixed(0.2165,1,L_SIZE), to_sfixed(0.7879,1,L_SIZE), to_sfixed(0.6397,1,L_SIZE), to_sfixed(0.9038,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.4450,1,L_SIZE), to_sfixed(0.3690,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8334,1,L_SIZE), to_sfixed(0.6603,1,L_SIZE), to_sfixed(0.7368,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.5928,1,L_SIZE), to_sfixed(0.1811,1,L_SIZE), to_sfixed(0.7576,1,L_SIZE), to_sfixed(0.2905,1,L_SIZE), to_sfixed(0.5885,1,L_SIZE), to_sfixed(0.3275,1,L_SIZE), to_sfixed(0.3950,1,L_SIZE), to_sfixed(0.3095,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9231,1,L_SIZE), to_sfixed(0.5621,1,L_SIZE), to_sfixed(0.7864,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.6605,1,L_SIZE), to_sfixed(0.4716,1,L_SIZE), to_sfixed(0.1102,1,L_SIZE), to_sfixed(0.7576,1,L_SIZE), to_sfixed(0.2235,1,L_SIZE), to_sfixed(0.4523,1,L_SIZE), to_sfixed(0.5614,1,L_SIZE), to_sfixed(0.4550,1,L_SIZE), to_sfixed(0.4048,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8665,1,L_SIZE), to_sfixed(0.5638,1,L_SIZE), to_sfixed(0.7988,1,L_SIZE), to_sfixed(0.7333,1,L_SIZE), to_sfixed(0.6543,1,L_SIZE), to_sfixed(0.4253,1,L_SIZE), to_sfixed(0.1181,1,L_SIZE), to_sfixed(0.9091,1,L_SIZE), to_sfixed(0.2682,1,L_SIZE), to_sfixed(0.4292,1,L_SIZE), to_sfixed(0.5088,1,L_SIZE), to_sfixed(0.5275,1,L_SIZE), to_sfixed(0.3393,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8739,1,L_SIZE), to_sfixed(0.5948,1,L_SIZE), to_sfixed(0.7276,1,L_SIZE), to_sfixed(0.6167,1,L_SIZE), to_sfixed(0.6543,1,L_SIZE), to_sfixed(0.3582,1,L_SIZE), to_sfixed(0.1378,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.2626,1,L_SIZE), to_sfixed(0.4062,1,L_SIZE), to_sfixed(0.3977,1,L_SIZE), to_sfixed(0.4375,1,L_SIZE), to_sfixed(0.4018,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9292,1,L_SIZE), to_sfixed(0.4759,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.7333,1,L_SIZE), to_sfixed(0.5556,1,L_SIZE), to_sfixed(0.3479,1,L_SIZE), to_sfixed(0.1339,1,L_SIZE), to_sfixed(0.6212,1,L_SIZE), to_sfixed(0.2877,1,L_SIZE), to_sfixed(0.7369,1,L_SIZE), to_sfixed(0.4094,1,L_SIZE), to_sfixed(0.4200,1,L_SIZE), to_sfixed(0.3661,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9258,1,L_SIZE), to_sfixed(0.7517,1,L_SIZE), to_sfixed(0.6997,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.3299,1,L_SIZE), to_sfixed(0.0925,1,L_SIZE), to_sfixed(0.7879,1,L_SIZE), to_sfixed(0.3212,1,L_SIZE), to_sfixed(0.5092,1,L_SIZE), to_sfixed(0.4561,1,L_SIZE), to_sfixed(0.4375,1,L_SIZE), to_sfixed(0.3095,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9069,1,L_SIZE), to_sfixed(0.6379,1,L_SIZE), to_sfixed(0.8050,1,L_SIZE), to_sfixed(0.7667,1,L_SIZE), to_sfixed(0.6852,1,L_SIZE), to_sfixed(0.4381,1,L_SIZE), to_sfixed(0.1811,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.4078,1,L_SIZE), to_sfixed(0.8215,1,L_SIZE), to_sfixed(0.4971,1,L_SIZE), to_sfixed(0.3900,1,L_SIZE), to_sfixed(0.4137,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8645,1,L_SIZE), to_sfixed(0.5810,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.6500,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.3814,1,L_SIZE), to_sfixed(0.1299,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.2709,1,L_SIZE), to_sfixed(0.7892,1,L_SIZE), to_sfixed(0.4211,1,L_SIZE), to_sfixed(0.4375,1,L_SIZE), to_sfixed(0.4077,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9157,1,L_SIZE), to_sfixed(0.4448,1,L_SIZE), to_sfixed(0.8328,1,L_SIZE), to_sfixed(0.8167,1,L_SIZE), to_sfixed(0.6481,1,L_SIZE), to_sfixed(0.3995,1,L_SIZE), to_sfixed(0.1654,1,L_SIZE), to_sfixed(0.5909,1,L_SIZE), to_sfixed(0.4302,1,L_SIZE), to_sfixed(0.6662,1,L_SIZE), to_sfixed(0.4327,1,L_SIZE), to_sfixed(0.4500,1,L_SIZE), to_sfixed(0.4464,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9036,1,L_SIZE), to_sfixed(0.7931,1,L_SIZE), to_sfixed(0.8854,1,L_SIZE), to_sfixed(0.8333,1,L_SIZE), to_sfixed(0.6914,1,L_SIZE), to_sfixed(0.5103,1,L_SIZE), to_sfixed(0.1890,1,L_SIZE), to_sfixed(0.4091,1,L_SIZE), to_sfixed(0.3101,1,L_SIZE), to_sfixed(0.6538,1,L_SIZE), to_sfixed(0.3918,1,L_SIZE), to_sfixed(0.4800,1,L_SIZE), to_sfixed(0.3750,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8227,1,L_SIZE), to_sfixed(0.5224,1,L_SIZE), to_sfixed(0.7183,1,L_SIZE), to_sfixed(0.6333,1,L_SIZE), to_sfixed(0.5926,1,L_SIZE), to_sfixed(0.3222,1,L_SIZE), to_sfixed(0.0965,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.2039,1,L_SIZE), to_sfixed(0.4231,1,L_SIZE), to_sfixed(0.3860,1,L_SIZE), to_sfixed(0.4575,1,L_SIZE), to_sfixed(0.3036,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8611,1,L_SIZE), to_sfixed(0.4121,1,L_SIZE), to_sfixed(0.7059,1,L_SIZE), to_sfixed(0.6500,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.3582,1,L_SIZE), to_sfixed(0.1004,1,L_SIZE), to_sfixed(0.7273,1,L_SIZE), to_sfixed(0.1788,1,L_SIZE), to_sfixed(0.7615,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.4075,1,L_SIZE), to_sfixed(0.2798,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9548,1,L_SIZE), to_sfixed(0.4328,1,L_SIZE), to_sfixed(0.7678,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.5617,1,L_SIZE), to_sfixed(0.4330,1,L_SIZE), to_sfixed(0.1378,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.3464,1,L_SIZE), to_sfixed(0.7462,1,L_SIZE), to_sfixed(0.3626,1,L_SIZE), to_sfixed(0.4275,1,L_SIZE), to_sfixed(0.3929,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9245,1,L_SIZE), to_sfixed(0.9741,1,L_SIZE), to_sfixed(0.7585,1,L_SIZE), to_sfixed(0.6833,1,L_SIZE), to_sfixed(0.5864,1,L_SIZE), to_sfixed(0.4330,1,L_SIZE), to_sfixed(0.1201,1,L_SIZE), to_sfixed(0.7879,1,L_SIZE), to_sfixed(0.2961,1,L_SIZE), to_sfixed(0.5923,1,L_SIZE), to_sfixed(0.3743,1,L_SIZE), to_sfixed(0.4350,1,L_SIZE), to_sfixed(0.4405,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9036,1,L_SIZE), to_sfixed(0.6741,1,L_SIZE), to_sfixed(0.7678,1,L_SIZE), to_sfixed(0.7667,1,L_SIZE), to_sfixed(0.6296,1,L_SIZE), to_sfixed(0.4639,1,L_SIZE), to_sfixed(0.1476,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.5615,1,L_SIZE), to_sfixed(0.4094,1,L_SIZE), to_sfixed(0.3900,1,L_SIZE), to_sfixed(0.4464,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8948,1,L_SIZE), to_sfixed(0.7379,1,L_SIZE), to_sfixed(0.6997,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.7407,1,L_SIZE), to_sfixed(0.4098,1,L_SIZE), to_sfixed(0.1358,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.3771,1,L_SIZE), to_sfixed(0.7846,1,L_SIZE), to_sfixed(0.3450,1,L_SIZE), to_sfixed(0.3900,1,L_SIZE), to_sfixed(0.4970,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.8881,1,L_SIZE), to_sfixed(0.4466,1,L_SIZE), to_sfixed(0.7337,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.7407,1,L_SIZE), to_sfixed(0.4253,1,L_SIZE), to_sfixed(0.1339,1,L_SIZE), to_sfixed(0.8030,1,L_SIZE), to_sfixed(0.4078,1,L_SIZE), to_sfixed(0.7154,1,L_SIZE), to_sfixed(0.3509,1,L_SIZE), to_sfixed(0.4050,1,L_SIZE), to_sfixed(0.5000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)), (to_sfixed(0.9528,1,L_SIZE), to_sfixed(0.7069,1,L_SIZE), to_sfixed(0.8483,1,L_SIZE), to_sfixed(0.8167,1,L_SIZE), to_sfixed(0.5926,1,L_SIZE), to_sfixed(0.5284,1,L_SIZE), to_sfixed(0.1496,1,L_SIZE), to_sfixed(0.8485,1,L_SIZE), to_sfixed(0.3771,1,L_SIZE), to_sfixed(0.7077,1,L_SIZE), to_sfixed(0.3567,1,L_SIZE), to_sfixed(0.4000,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)) ); -- Signals signal INPUT : ARRAY_OF_SFIXED (0 to (PERCEPTRONS_INPUT-1)); signal FROM_LOOKUP : ARRAY_OF_SFIXED (0 to (PERCEPTRONS_HIDDEN-1)); signal OUTPUT : ARRAY_OF_SFIXED (0 to (PERCEPTRONS_HIDDEN-1)); -- Signals signal IN_UNSIGNED : unsigned(7 downto 0); signal LOOKUP_TABLE_K : unsigned(7 downto 0); signal LOOKUP_TABLE_OUT : INPUT_LOOKUP_ARRAY; signal LOOKUP_TABLE_OUT_CONSTRAINED : INPUT_CONSTRAINED_SFIXED_ARRAY; signal UNIT_DELAY_OUT : INPUT_CONSTRAINED_SFIXED_ARRAY; --============================================================================= -- architecture begin --============================================================================= begin IN_UNSIGNED <= unsigned(SAMPLE_NUMBER); LOOKUP_TABLE_K <= -- Make sure no index will fall out of boundary to_unsigned(0, 8) when IN_UNSIGNED <= 0 else to_unsigned(SAMPLE_SIZE, 8) when IN_UNSIGNED >= SAMPLE_SIZE else IN_UNSIGNED; LOOKUP_TABLE_OUT <= INPUTS_TABLE(to_integer(LOOKUP_TABLE_K)); GEN_PROPER_OUTPUT: for I in 0 to (PERCEPTRONS_INPUT-1+PERCEPTRONS_OUTPUT) generate LOOKUP_TABLE_OUT_CONSTRAINED(I)<= resize(LOOKUP_TABLE_OUT(I),U_SIZE,L_SIZE); end generate GEN_PROPER_OUTPUT; UNIT_DELAY_PROCESS : process (clk) begin if CLK'event and CLK = '1' then UNIT_DELAY_OUT <= LOOKUP_TABLE_OUT_CONSTRAINED; end if; end process UNIT_DELAY_PROCESS; SELECTED_INPUT <= UNIT_DELAY_OUT; end RTL; --============================================================================= -- architecture end --=============================================================================
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity class_adder is generic(N: integer:= 4); port( number1_in: in std_logic_vector(N-1 downto 0); number2_in: in std_logic_vector(N-1 downto 0); cin: in std_logic; result: out std_logic_vector(N-1 downto 0); cout: out std_logic ); end; architecture class_adder_arq of class_adder is signal aux: signed (N+1 downto 0) := to_signed(0, N+2); begin aux <= ('0' & signed(number1_in) & cin) + ('0' & signed(number2_in) & '1'); result <= std_logic_vector( aux (N downto 1) ); cout <= aux (N+1); end;
library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use ieee.math_real.all ; use ieee.math_complex.all ; entity bladerf is port ( -- Main 38.4MHz system clock c4_clock : in std_logic ; -- VCTCXO DAC dac_sclk : out std_logic ; dac_sdi : out std_logic ; dac_sdo : in std_logic ; dac_csx : out std_logic ; -- LEDs led : buffer std_logic_vector(3 downto 1) := (others =>'0') ; -- LMS RX Interface lms_rx_clock_out : in std_logic ; lms_rx_data : in signed(11 downto 0) ; lms_rx_enable : out std_logic ; lms_rx_iq_select : in std_logic := '0' ; lms_rx_v : out std_logic_vector(2 downto 1) ; -- LMS TX Interface c4_tx_clock : in std_logic ; lms_tx_data : out signed(11 downto 0) ; lms_tx_enable : out std_logic ; lms_tx_iq_select : buffer std_logic := '0' ; lms_tx_v : out std_logic_vector(2 downto 1) ; -- LMS SPI Interface lms_sclk : buffer std_logic ; lms_sen : out std_logic ; lms_sdio : out std_logic ; lms_sdo : in std_logic ; -- LMS Control Interface lms_pll_out : in std_logic ; lms_reset : buffer std_logic ; -- Si5338 I2C Interface si_scl : inout std_logic ; si_sda : inout std_logic ; -- FX3 Interface fx3_pclk : in std_logic ; fx3_gpif : inout std_logic_vector(31 downto 0) ; fx3_ctl : inout std_logic_vector(12 downto 0) ; fx3_uart_rxd : out std_logic ; fx3_uart_txd : in std_logic ; fx3_uart_csx : in std_logic ; -- Reference signals ref_1pps : in std_logic ; ref_sma_clock : in std_logic ; -- Mini expansion mini_exp1 : inout std_logic ; mini_exp2 : inout std_logic ; -- Expansion Interface exp_present : in std_logic ; exp_spi_clock : out std_logic ; exp_spi_miso : in std_logic ; exp_spi_mosi : out std_logic ; exp_clock_in : in std_logic ; exp_gpio : inout std_logic_vector(32 downto 2) ) ; end entity ; -- bladerf --TODO: explain revisions
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:52:25 03/11/2014 -- Design Name: -- Module Name: BaudRateGenerator - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity BaudRateGenerator is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; tick : out STD_LOGIC); end BaudRateGenerator; architecture Behavioral of BaudRateGenerator is signal brojac, brojacNext : unsigned (9 downto 0); begin process (clk, rst) begin if(rst = '0') then brojac <= "0000000000"; else if (clk'event and clk = '1') then brojac <= brojacNext; end if; end if; end process; brojacNext <= "0000000000" when brojac = 651 else brojac + 1; tick <= '1' when brojac = 651 else '0'; end Behavioral;
package COMPONENTS is component DUMMY_MODULE port (I : in bit; O : out bit); end component; end package; entity DUMMY_MODULE is port (I: in bit; O: out bit); end entity; architecture RTL of DUMMY_MODULE is begin O <= I; end architecture; use WORK.COMPONENTS.DUMMY_MODULE; entity DUMMY_TOP is port (I : in bit; O : out bit); end entity; architecture RTL of DUMMY_TOP is begin U: DUMMY_MODULE port map(I=>I, O=>O); end architecture;
package COMPONENTS is component DUMMY_MODULE port (I : in bit; O : out bit); end component; end package; entity DUMMY_MODULE is port (I: in bit; O: out bit); end entity; architecture RTL of DUMMY_MODULE is begin O <= I; end architecture; use WORK.COMPONENTS.DUMMY_MODULE; entity DUMMY_TOP is port (I : in bit; O : out bit); end entity; architecture RTL of DUMMY_TOP is begin U: DUMMY_MODULE port map(I=>I, O=>O); end architecture;
package COMPONENTS is component DUMMY_MODULE port (I : in bit; O : out bit); end component; end package; entity DUMMY_MODULE is port (I: in bit; O: out bit); end entity; architecture RTL of DUMMY_MODULE is begin O <= I; end architecture; use WORK.COMPONENTS.DUMMY_MODULE; entity DUMMY_TOP is port (I : in bit; O : out bit); end entity; architecture RTL of DUMMY_TOP is begin U: DUMMY_MODULE port map(I=>I, O=>O); end architecture;
package COMPONENTS is component DUMMY_MODULE port (I : in bit; O : out bit); end component; end package; entity DUMMY_MODULE is port (I: in bit; O: out bit); end entity; architecture RTL of DUMMY_MODULE is begin O <= I; end architecture; use WORK.COMPONENTS.DUMMY_MODULE; entity DUMMY_TOP is port (I : in bit; O : out bit); end entity; architecture RTL of DUMMY_TOP is begin U: DUMMY_MODULE port map(I=>I, O=>O); end architecture;
package COMPONENTS is component DUMMY_MODULE port (I : in bit; O : out bit); end component; end package; entity DUMMY_MODULE is port (I: in bit; O: out bit); end entity; architecture RTL of DUMMY_MODULE is begin O <= I; end architecture; use WORK.COMPONENTS.DUMMY_MODULE; entity DUMMY_TOP is port (I : in bit; O : out bit); end entity; architecture RTL of DUMMY_TOP is begin U: DUMMY_MODULE port map(I=>I, O=>O); end architecture;