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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1780.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s06b00x00p04n01i01780ent IS
END c09s06b00x00p04n01i01780ent;
ARCHITECTURE c09s06b00x00p04n01i01780arch OF c09s06b00x00p04n01i01780ent IS
signal a, b, p, q: bit;
component comp1
port (p1, p2:bit);
end component;
for L1 : comp1 use entity work.ch0906_p00401_01_ent;
BEGIN
L1:comp2 -- Failure_here: comp2 not declared
port map (q, p);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s06b00x00p04n01i01780 - The component name in the component instantiation statement must be the name of a component declared in a component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s06b00x00p04n01i01780arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1780.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s06b00x00p04n01i01780ent IS
END c09s06b00x00p04n01i01780ent;
ARCHITECTURE c09s06b00x00p04n01i01780arch OF c09s06b00x00p04n01i01780ent IS
signal a, b, p, q: bit;
component comp1
port (p1, p2:bit);
end component;
for L1 : comp1 use entity work.ch0906_p00401_01_ent;
BEGIN
L1:comp2 -- Failure_here: comp2 not declared
port map (q, p);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s06b00x00p04n01i01780 - The component name in the component instantiation statement must be the name of a component declared in a component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s06b00x00p04n01i01780arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1780.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s06b00x00p04n01i01780ent IS
END c09s06b00x00p04n01i01780ent;
ARCHITECTURE c09s06b00x00p04n01i01780arch OF c09s06b00x00p04n01i01780ent IS
signal a, b, p, q: bit;
component comp1
port (p1, p2:bit);
end component;
for L1 : comp1 use entity work.ch0906_p00401_01_ent;
BEGIN
L1:comp2 -- Failure_here: comp2 not declared
port map (q, p);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s06b00x00p04n01i01780 - The component name in the component instantiation statement must be the name of a component declared in a component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s06b00x00p04n01i01780arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_1400a is
generic (
g_version : unsigned(7 downto 0) := X"AB" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate_1541_1400a;
architecture structural of ultimate_1541_1400a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true,
g_vic_copper => true,
g_video_overlay => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_1400a is
generic (
g_version : unsigned(7 downto 0) := X"AB" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate_1541_1400a;
architecture structural of ultimate_1541_1400a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true,
g_vic_copper => true,
g_video_overlay => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_1400a is
generic (
g_version : unsigned(7 downto 0) := X"AB" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate_1541_1400a;
architecture structural of ultimate_1541_1400a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true,
g_vic_copper => true,
g_video_overlay => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_1400a is
generic (
g_version : unsigned(7 downto 0) := X"AB" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate_1541_1400a;
architecture structural of ultimate_1541_1400a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true,
g_vic_copper => true,
g_video_overlay => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PC_register is
port (
clk_in : in std_logic;
rst_in : in std_logic;
cargaPC_i : in std_logic;
incPC_i : in std_logic;
pc_data_i : in std_logic_vector(7 downto 0);
pc_data_o : out std_logic_vector(7 downto 0)
);
end PC_register;
architecture Behavioral of PC_register is
begin
process(clk_in, rst_in)
variable pc_data_o_w : std_logic_vector(7 downto 0); -- variavel auxiliar
variable incPC_cont : integer;
begin
if (rst_in = '1') then
pc_data_o_w := "00000001";
incPC_cont := 0;
elsif (clk_in = '1' and clk_in'event) then
if (cargaPC_i = '1') then
pc_data_o_w := pc_data_i;
elsif (incPC_i = '1') then
incPC_cont := incPC_cont + 1;
if incPC_cont = 2 then
pc_data_o_w := std_logic_vector(unsigned(pc_data_o_w) + 1);
incPC_cont := 0;
end if;
end if;
end if;
pc_data_o <= pc_data_o_w;
end process;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY OMUXT_tb IS
END OMUXT_tb;
ARCHITECTURE behavior OF OMUXT_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OMUXT
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm : IN std_logic_vector(31 downto 0);
i : IN std_logic;
oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Crs2 : std_logic_vector(31 downto 0) := (others => '0');
signal SEUimm : std_logic_vector(31 downto 0) := (others => '0');
signal i : std_logic := '0';
--Outputs
signal oper2 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: OMUXT PORT MAP (
Crs2 => Crs2,
SEUimm => SEUimm,
i => i,
oper2 => oper2
);
-- Stimulus process
stim_proc: process
begin
i<='0';
Crs2<="01000010111001000110011101010111";
SEUimm<="00000000000000000000000100110101";
wait for 20 ns;
Crs2<="00000000000010000000001000000000";
SEUimm<="11111111111111111111001000000000";
wait for 20 ns;
i<='1';
Crs2<="00001111111000000011111111100000";
SEUimm<="00000000000000000000001111111111";
wait for 20 ns;
Crs2<="00000000000000000011101001010100";
SEUimm<="00000000000000000000001111000011";
wait;
end process;
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY OMUXT_tb IS
END OMUXT_tb;
ARCHITECTURE behavior OF OMUXT_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OMUXT
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm : IN std_logic_vector(31 downto 0);
i : IN std_logic;
oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Crs2 : std_logic_vector(31 downto 0) := (others => '0');
signal SEUimm : std_logic_vector(31 downto 0) := (others => '0');
signal i : std_logic := '0';
--Outputs
signal oper2 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: OMUXT PORT MAP (
Crs2 => Crs2,
SEUimm => SEUimm,
i => i,
oper2 => oper2
);
-- Stimulus process
stim_proc: process
begin
i<='0';
Crs2<="01000010111001000110011101010111";
SEUimm<="00000000000000000000000100110101";
wait for 20 ns;
Crs2<="00000000000010000000001000000000";
SEUimm<="11111111111111111111001000000000";
wait for 20 ns;
i<='1';
Crs2<="00001111111000000011111111100000";
SEUimm<="00000000000000000000001111111111";
wait for 20 ns;
Crs2<="00000000000000000011101001010100";
SEUimm<="00000000000000000000001111000011";
wait;
end process;
END;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_BarrelShiftAltr is
generic (
widthin : natural :=32;
widthd : natural :=5;
pipeline : natural :=1;
ndirection : natural :=0;
use_dedicated_circuitry : natural :=0
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end alt_dspbuilder_BarrelShiftAltr;
architecture SYNTH of alt_dspbuilder_BarrelShiftAltr is
signal resdec : std_logic_vector(widthin-1 downto 0);
signal dxin : std_logic_vector(widthin-1 downto 0);
signal resmult : std_logic_vector(2*widthin downto 0);
signal sdirection : std_logic;
signal direction_dff : std_logic_vector(2 downto 0);
signal resdec_ext : std_logic_vector(widthin downto 0);
signal distance_out : std_logic_vector(widthd-1 downto 0);
signal dist_out_reg : std_logic_vector(widthd-1 downto 0);
signal max_distance : std_logic_vector(widthd-1 downto 0);
signal distance_sum : std_logic_vector(widthd-1 downto 0);
signal no_shift : std_logic;
constant distance_zero : std_logic_vector(widthd-1 downto 0):=(others=>'0');
begin
gsdir1:if ndirection=0 generate
sdirection <='0';
end generate gsdir1;
gsdir2:if ndirection=1 generate
sdirection <= '0' when distance=distance_zero else '1';
end generate gsdir2;
gsdir3:if ndirection=2 generate
sdirection <= '0' when distance=distance_zero else direction;
end generate gsdir3;
gnopipeline:if pipeline=0 generate
gc:if use_dedicated_circuitry>0 generate
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE")
PORT MAP (data => distance_out,
eq => resdec);
U1 : lpm_mult GENERIC MAP (lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP (dataa => resdec_ext,
datab => xin,
result => resmult);
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (
lpm_width => widthd,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0)
port map (
dataa => max_distance,
datab => distance,
result => distance_sum,
cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (sdirection='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gc;
gndc:if use_dedicated_circuitry=0 generate
U0 : lpm_clshift GENERIC MAP (lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ARITHMETIC",
lpm_width => widthin,
lpm_widthdist => widthd)
PORT MAP ( distance => distance,
direction => sdirection,
data => xin,
result => yout);
end generate gndc;
end generate gnopipeline;
gpipeline:if pipeline>0 generate
p:process(clock,aclr)
begin
if aclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif clock'event and clock='1' then
if sclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif ena='1' then
dxin <= xin ;
direction_dff(2)<= direction_dff(1);
direction_dff(1)<= direction_dff(0);
direction_dff(0)<= sdirection;
dist_out_reg <= distance_out;
end if;
end if;
end process p;
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE",
lpm_pipeline => 0)
PORT MAP ( data => dist_out_reg,
eq => resdec);
gndc:if use_dedicated_circuitry=0 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gndc;
gdc:if use_dedicated_circuitry=1 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gdc;
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (lpm_width => widthd, lpm_direction => "SUB", lpm_type => "LPM_ADD_SUB", lpm_representation => "UNSIGNED", lpm_pipeline => 0)
port map ( dataa => max_distance, datab => distance, result => distance_sum, cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (direction_dff(2)='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gpipeline;
end SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_BarrelShiftAltr is
generic (
widthin : natural :=32;
widthd : natural :=5;
pipeline : natural :=1;
ndirection : natural :=0;
use_dedicated_circuitry : natural :=0
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end alt_dspbuilder_BarrelShiftAltr;
architecture SYNTH of alt_dspbuilder_BarrelShiftAltr is
signal resdec : std_logic_vector(widthin-1 downto 0);
signal dxin : std_logic_vector(widthin-1 downto 0);
signal resmult : std_logic_vector(2*widthin downto 0);
signal sdirection : std_logic;
signal direction_dff : std_logic_vector(2 downto 0);
signal resdec_ext : std_logic_vector(widthin downto 0);
signal distance_out : std_logic_vector(widthd-1 downto 0);
signal dist_out_reg : std_logic_vector(widthd-1 downto 0);
signal max_distance : std_logic_vector(widthd-1 downto 0);
signal distance_sum : std_logic_vector(widthd-1 downto 0);
signal no_shift : std_logic;
constant distance_zero : std_logic_vector(widthd-1 downto 0):=(others=>'0');
begin
gsdir1:if ndirection=0 generate
sdirection <='0';
end generate gsdir1;
gsdir2:if ndirection=1 generate
sdirection <= '0' when distance=distance_zero else '1';
end generate gsdir2;
gsdir3:if ndirection=2 generate
sdirection <= '0' when distance=distance_zero else direction;
end generate gsdir3;
gnopipeline:if pipeline=0 generate
gc:if use_dedicated_circuitry>0 generate
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE")
PORT MAP (data => distance_out,
eq => resdec);
U1 : lpm_mult GENERIC MAP (lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP (dataa => resdec_ext,
datab => xin,
result => resmult);
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (
lpm_width => widthd,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0)
port map (
dataa => max_distance,
datab => distance,
result => distance_sum,
cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (sdirection='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gc;
gndc:if use_dedicated_circuitry=0 generate
U0 : lpm_clshift GENERIC MAP (lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ARITHMETIC",
lpm_width => widthin,
lpm_widthdist => widthd)
PORT MAP ( distance => distance,
direction => sdirection,
data => xin,
result => yout);
end generate gndc;
end generate gnopipeline;
gpipeline:if pipeline>0 generate
p:process(clock,aclr)
begin
if aclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif clock'event and clock='1' then
if sclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif ena='1' then
dxin <= xin ;
direction_dff(2)<= direction_dff(1);
direction_dff(1)<= direction_dff(0);
direction_dff(0)<= sdirection;
dist_out_reg <= distance_out;
end if;
end if;
end process p;
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE",
lpm_pipeline => 0)
PORT MAP ( data => dist_out_reg,
eq => resdec);
gndc:if use_dedicated_circuitry=0 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gndc;
gdc:if use_dedicated_circuitry=1 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gdc;
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (lpm_width => widthd, lpm_direction => "SUB", lpm_type => "LPM_ADD_SUB", lpm_representation => "UNSIGNED", lpm_pipeline => 0)
port map ( dataa => max_distance, datab => distance, result => distance_sum, cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (direction_dff(2)='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gpipeline;
end SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_BarrelShiftAltr is
generic (
widthin : natural :=32;
widthd : natural :=5;
pipeline : natural :=1;
ndirection : natural :=0;
use_dedicated_circuitry : natural :=0
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end alt_dspbuilder_BarrelShiftAltr;
architecture SYNTH of alt_dspbuilder_BarrelShiftAltr is
signal resdec : std_logic_vector(widthin-1 downto 0);
signal dxin : std_logic_vector(widthin-1 downto 0);
signal resmult : std_logic_vector(2*widthin downto 0);
signal sdirection : std_logic;
signal direction_dff : std_logic_vector(2 downto 0);
signal resdec_ext : std_logic_vector(widthin downto 0);
signal distance_out : std_logic_vector(widthd-1 downto 0);
signal dist_out_reg : std_logic_vector(widthd-1 downto 0);
signal max_distance : std_logic_vector(widthd-1 downto 0);
signal distance_sum : std_logic_vector(widthd-1 downto 0);
signal no_shift : std_logic;
constant distance_zero : std_logic_vector(widthd-1 downto 0):=(others=>'0');
begin
gsdir1:if ndirection=0 generate
sdirection <='0';
end generate gsdir1;
gsdir2:if ndirection=1 generate
sdirection <= '0' when distance=distance_zero else '1';
end generate gsdir2;
gsdir3:if ndirection=2 generate
sdirection <= '0' when distance=distance_zero else direction;
end generate gsdir3;
gnopipeline:if pipeline=0 generate
gc:if use_dedicated_circuitry>0 generate
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE")
PORT MAP (data => distance_out,
eq => resdec);
U1 : lpm_mult GENERIC MAP (lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP (dataa => resdec_ext,
datab => xin,
result => resmult);
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (
lpm_width => widthd,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0)
port map (
dataa => max_distance,
datab => distance,
result => distance_sum,
cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (sdirection='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gc;
gndc:if use_dedicated_circuitry=0 generate
U0 : lpm_clshift GENERIC MAP (lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ARITHMETIC",
lpm_width => widthin,
lpm_widthdist => widthd)
PORT MAP ( distance => distance,
direction => sdirection,
data => xin,
result => yout);
end generate gndc;
end generate gnopipeline;
gpipeline:if pipeline>0 generate
p:process(clock,aclr)
begin
if aclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif clock'event and clock='1' then
if sclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif ena='1' then
dxin <= xin ;
direction_dff(2)<= direction_dff(1);
direction_dff(1)<= direction_dff(0);
direction_dff(0)<= sdirection;
dist_out_reg <= distance_out;
end if;
end if;
end process p;
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE",
lpm_pipeline => 0)
PORT MAP ( data => dist_out_reg,
eq => resdec);
gndc:if use_dedicated_circuitry=0 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gndc;
gdc:if use_dedicated_circuitry=1 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gdc;
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (lpm_width => widthd, lpm_direction => "SUB", lpm_type => "LPM_ADD_SUB", lpm_representation => "UNSIGNED", lpm_pipeline => 0)
port map ( dataa => max_distance, datab => distance, result => distance_sum, cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (direction_dff(2)='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gpipeline;
end SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_BarrelShiftAltr is
generic (
widthin : natural :=32;
widthd : natural :=5;
pipeline : natural :=1;
ndirection : natural :=0;
use_dedicated_circuitry : natural :=0
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end alt_dspbuilder_BarrelShiftAltr;
architecture SYNTH of alt_dspbuilder_BarrelShiftAltr is
signal resdec : std_logic_vector(widthin-1 downto 0);
signal dxin : std_logic_vector(widthin-1 downto 0);
signal resmult : std_logic_vector(2*widthin downto 0);
signal sdirection : std_logic;
signal direction_dff : std_logic_vector(2 downto 0);
signal resdec_ext : std_logic_vector(widthin downto 0);
signal distance_out : std_logic_vector(widthd-1 downto 0);
signal dist_out_reg : std_logic_vector(widthd-1 downto 0);
signal max_distance : std_logic_vector(widthd-1 downto 0);
signal distance_sum : std_logic_vector(widthd-1 downto 0);
signal no_shift : std_logic;
constant distance_zero : std_logic_vector(widthd-1 downto 0):=(others=>'0');
begin
gsdir1:if ndirection=0 generate
sdirection <='0';
end generate gsdir1;
gsdir2:if ndirection=1 generate
sdirection <= '0' when distance=distance_zero else '1';
end generate gsdir2;
gsdir3:if ndirection=2 generate
sdirection <= '0' when distance=distance_zero else direction;
end generate gsdir3;
gnopipeline:if pipeline=0 generate
gc:if use_dedicated_circuitry>0 generate
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE")
PORT MAP (data => distance_out,
eq => resdec);
U1 : lpm_mult GENERIC MAP (lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP (dataa => resdec_ext,
datab => xin,
result => resmult);
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (
lpm_width => widthd,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0)
port map (
dataa => max_distance,
datab => distance,
result => distance_sum,
cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (sdirection='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gc;
gndc:if use_dedicated_circuitry=0 generate
U0 : lpm_clshift GENERIC MAP (lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ARITHMETIC",
lpm_width => widthin,
lpm_widthdist => widthd)
PORT MAP ( distance => distance,
direction => sdirection,
data => xin,
result => yout);
end generate gndc;
end generate gnopipeline;
gpipeline:if pipeline>0 generate
p:process(clock,aclr)
begin
if aclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif clock'event and clock='1' then
if sclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif ena='1' then
dxin <= xin ;
direction_dff(2)<= direction_dff(1);
direction_dff(1)<= direction_dff(0);
direction_dff(0)<= sdirection;
dist_out_reg <= distance_out;
end if;
end if;
end process p;
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE",
lpm_pipeline => 0)
PORT MAP ( data => dist_out_reg,
eq => resdec);
gndc:if use_dedicated_circuitry=0 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gndc;
gdc:if use_dedicated_circuitry=1 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gdc;
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (lpm_width => widthd, lpm_direction => "SUB", lpm_type => "LPM_ADD_SUB", lpm_representation => "UNSIGNED", lpm_pipeline => 0)
port map ( dataa => max_distance, datab => distance, result => distance_sum, cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (direction_dff(2)='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gpipeline;
end SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_BarrelShiftAltr is
generic (
widthin : natural :=32;
widthd : natural :=5;
pipeline : natural :=1;
ndirection : natural :=0;
use_dedicated_circuitry : natural :=0
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end alt_dspbuilder_BarrelShiftAltr;
architecture SYNTH of alt_dspbuilder_BarrelShiftAltr is
signal resdec : std_logic_vector(widthin-1 downto 0);
signal dxin : std_logic_vector(widthin-1 downto 0);
signal resmult : std_logic_vector(2*widthin downto 0);
signal sdirection : std_logic;
signal direction_dff : std_logic_vector(2 downto 0);
signal resdec_ext : std_logic_vector(widthin downto 0);
signal distance_out : std_logic_vector(widthd-1 downto 0);
signal dist_out_reg : std_logic_vector(widthd-1 downto 0);
signal max_distance : std_logic_vector(widthd-1 downto 0);
signal distance_sum : std_logic_vector(widthd-1 downto 0);
signal no_shift : std_logic;
constant distance_zero : std_logic_vector(widthd-1 downto 0):=(others=>'0');
begin
gsdir1:if ndirection=0 generate
sdirection <='0';
end generate gsdir1;
gsdir2:if ndirection=1 generate
sdirection <= '0' when distance=distance_zero else '1';
end generate gsdir2;
gsdir3:if ndirection=2 generate
sdirection <= '0' when distance=distance_zero else direction;
end generate gsdir3;
gnopipeline:if pipeline=0 generate
gc:if use_dedicated_circuitry>0 generate
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE")
PORT MAP (data => distance_out,
eq => resdec);
U1 : lpm_mult GENERIC MAP (lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP (dataa => resdec_ext,
datab => xin,
result => resmult);
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (
lpm_width => widthd,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0)
port map (
dataa => max_distance,
datab => distance,
result => distance_sum,
cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (sdirection='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gc;
gndc:if use_dedicated_circuitry=0 generate
U0 : lpm_clshift GENERIC MAP (lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ARITHMETIC",
lpm_width => widthin,
lpm_widthdist => widthd)
PORT MAP ( distance => distance,
direction => sdirection,
data => xin,
result => yout);
end generate gndc;
end generate gnopipeline;
gpipeline:if pipeline>0 generate
p:process(clock,aclr)
begin
if aclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif clock'event and clock='1' then
if sclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif ena='1' then
dxin <= xin ;
direction_dff(2)<= direction_dff(1);
direction_dff(1)<= direction_dff(0);
direction_dff(0)<= sdirection;
dist_out_reg <= distance_out;
end if;
end if;
end process p;
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE",
lpm_pipeline => 0)
PORT MAP ( data => dist_out_reg,
eq => resdec);
gndc:if use_dedicated_circuitry=0 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gndc;
gdc:if use_dedicated_circuitry=1 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gdc;
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (lpm_width => widthd, lpm_direction => "SUB", lpm_type => "LPM_ADD_SUB", lpm_representation => "UNSIGNED", lpm_pipeline => 0)
port map ( dataa => max_distance, datab => distance, result => distance_sum, cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (direction_dff(2)='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gpipeline;
end SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_BarrelShiftAltr is
generic (
widthin : natural :=32;
widthd : natural :=5;
pipeline : natural :=1;
ndirection : natural :=0;
use_dedicated_circuitry : natural :=0
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end alt_dspbuilder_BarrelShiftAltr;
architecture SYNTH of alt_dspbuilder_BarrelShiftAltr is
signal resdec : std_logic_vector(widthin-1 downto 0);
signal dxin : std_logic_vector(widthin-1 downto 0);
signal resmult : std_logic_vector(2*widthin downto 0);
signal sdirection : std_logic;
signal direction_dff : std_logic_vector(2 downto 0);
signal resdec_ext : std_logic_vector(widthin downto 0);
signal distance_out : std_logic_vector(widthd-1 downto 0);
signal dist_out_reg : std_logic_vector(widthd-1 downto 0);
signal max_distance : std_logic_vector(widthd-1 downto 0);
signal distance_sum : std_logic_vector(widthd-1 downto 0);
signal no_shift : std_logic;
constant distance_zero : std_logic_vector(widthd-1 downto 0):=(others=>'0');
begin
gsdir1:if ndirection=0 generate
sdirection <='0';
end generate gsdir1;
gsdir2:if ndirection=1 generate
sdirection <= '0' when distance=distance_zero else '1';
end generate gsdir2;
gsdir3:if ndirection=2 generate
sdirection <= '0' when distance=distance_zero else direction;
end generate gsdir3;
gnopipeline:if pipeline=0 generate
gc:if use_dedicated_circuitry>0 generate
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE")
PORT MAP (data => distance_out,
eq => resdec);
U1 : lpm_mult GENERIC MAP (lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP (dataa => resdec_ext,
datab => xin,
result => resmult);
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (
lpm_width => widthd,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0)
port map (
dataa => max_distance,
datab => distance,
result => distance_sum,
cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (sdirection='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gc;
gndc:if use_dedicated_circuitry=0 generate
U0 : lpm_clshift GENERIC MAP (lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ARITHMETIC",
lpm_width => widthin,
lpm_widthdist => widthd)
PORT MAP ( distance => distance,
direction => sdirection,
data => xin,
result => yout);
end generate gndc;
end generate gnopipeline;
gpipeline:if pipeline>0 generate
p:process(clock,aclr)
begin
if aclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif clock'event and clock='1' then
if sclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif ena='1' then
dxin <= xin ;
direction_dff(2)<= direction_dff(1);
direction_dff(1)<= direction_dff(0);
direction_dff(0)<= sdirection;
dist_out_reg <= distance_out;
end if;
end if;
end process p;
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE",
lpm_pipeline => 0)
PORT MAP ( data => dist_out_reg,
eq => resdec);
gndc:if use_dedicated_circuitry=0 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gndc;
gdc:if use_dedicated_circuitry=1 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gdc;
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (lpm_width => widthd, lpm_direction => "SUB", lpm_type => "LPM_ADD_SUB", lpm_representation => "UNSIGNED", lpm_pipeline => 0)
port map ( dataa => max_distance, datab => distance, result => distance_sum, cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (direction_dff(2)='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gpipeline;
end SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_BarrelShiftAltr is
generic (
widthin : natural :=32;
widthd : natural :=5;
pipeline : natural :=1;
ndirection : natural :=0;
use_dedicated_circuitry : natural :=0
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end alt_dspbuilder_BarrelShiftAltr;
architecture SYNTH of alt_dspbuilder_BarrelShiftAltr is
signal resdec : std_logic_vector(widthin-1 downto 0);
signal dxin : std_logic_vector(widthin-1 downto 0);
signal resmult : std_logic_vector(2*widthin downto 0);
signal sdirection : std_logic;
signal direction_dff : std_logic_vector(2 downto 0);
signal resdec_ext : std_logic_vector(widthin downto 0);
signal distance_out : std_logic_vector(widthd-1 downto 0);
signal dist_out_reg : std_logic_vector(widthd-1 downto 0);
signal max_distance : std_logic_vector(widthd-1 downto 0);
signal distance_sum : std_logic_vector(widthd-1 downto 0);
signal no_shift : std_logic;
constant distance_zero : std_logic_vector(widthd-1 downto 0):=(others=>'0');
begin
gsdir1:if ndirection=0 generate
sdirection <='0';
end generate gsdir1;
gsdir2:if ndirection=1 generate
sdirection <= '0' when distance=distance_zero else '1';
end generate gsdir2;
gsdir3:if ndirection=2 generate
sdirection <= '0' when distance=distance_zero else direction;
end generate gsdir3;
gnopipeline:if pipeline=0 generate
gc:if use_dedicated_circuitry>0 generate
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE")
PORT MAP (data => distance_out,
eq => resdec);
U1 : lpm_mult GENERIC MAP (lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP (dataa => resdec_ext,
datab => xin,
result => resmult);
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (
lpm_width => widthd,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0)
port map (
dataa => max_distance,
datab => distance,
result => distance_sum,
cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (sdirection='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gc;
gndc:if use_dedicated_circuitry=0 generate
U0 : lpm_clshift GENERIC MAP (lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ARITHMETIC",
lpm_width => widthin,
lpm_widthdist => widthd)
PORT MAP ( distance => distance,
direction => sdirection,
data => xin,
result => yout);
end generate gndc;
end generate gnopipeline;
gpipeline:if pipeline>0 generate
p:process(clock,aclr)
begin
if aclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif clock'event and clock='1' then
if sclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif ena='1' then
dxin <= xin ;
direction_dff(2)<= direction_dff(1);
direction_dff(1)<= direction_dff(0);
direction_dff(0)<= sdirection;
dist_out_reg <= distance_out;
end if;
end if;
end process p;
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE",
lpm_pipeline => 0)
PORT MAP ( data => dist_out_reg,
eq => resdec);
gndc:if use_dedicated_circuitry=0 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gndc;
gdc:if use_dedicated_circuitry=1 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gdc;
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (lpm_width => widthd, lpm_direction => "SUB", lpm_type => "LPM_ADD_SUB", lpm_representation => "UNSIGNED", lpm_pipeline => 0)
port map ( dataa => max_distance, datab => distance, result => distance_sum, cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (direction_dff(2)='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gpipeline;
end SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_BarrelShiftAltr is
generic (
widthin : natural :=32;
widthd : natural :=5;
pipeline : natural :=1;
ndirection : natural :=0;
use_dedicated_circuitry : natural :=0
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end alt_dspbuilder_BarrelShiftAltr;
architecture SYNTH of alt_dspbuilder_BarrelShiftAltr is
signal resdec : std_logic_vector(widthin-1 downto 0);
signal dxin : std_logic_vector(widthin-1 downto 0);
signal resmult : std_logic_vector(2*widthin downto 0);
signal sdirection : std_logic;
signal direction_dff : std_logic_vector(2 downto 0);
signal resdec_ext : std_logic_vector(widthin downto 0);
signal distance_out : std_logic_vector(widthd-1 downto 0);
signal dist_out_reg : std_logic_vector(widthd-1 downto 0);
signal max_distance : std_logic_vector(widthd-1 downto 0);
signal distance_sum : std_logic_vector(widthd-1 downto 0);
signal no_shift : std_logic;
constant distance_zero : std_logic_vector(widthd-1 downto 0):=(others=>'0');
begin
gsdir1:if ndirection=0 generate
sdirection <='0';
end generate gsdir1;
gsdir2:if ndirection=1 generate
sdirection <= '0' when distance=distance_zero else '1';
end generate gsdir2;
gsdir3:if ndirection=2 generate
sdirection <= '0' when distance=distance_zero else direction;
end generate gsdir3;
gnopipeline:if pipeline=0 generate
gc:if use_dedicated_circuitry>0 generate
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE")
PORT MAP (data => distance_out,
eq => resdec);
U1 : lpm_mult GENERIC MAP (lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP (dataa => resdec_ext,
datab => xin,
result => resmult);
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (
lpm_width => widthd,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0)
port map (
dataa => max_distance,
datab => distance,
result => distance_sum,
cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (sdirection='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gc;
gndc:if use_dedicated_circuitry=0 generate
U0 : lpm_clshift GENERIC MAP (lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ARITHMETIC",
lpm_width => widthin,
lpm_widthdist => widthd)
PORT MAP ( distance => distance,
direction => sdirection,
data => xin,
result => yout);
end generate gndc;
end generate gnopipeline;
gpipeline:if pipeline>0 generate
p:process(clock,aclr)
begin
if aclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif clock'event and clock='1' then
if sclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif ena='1' then
dxin <= xin ;
direction_dff(2)<= direction_dff(1);
direction_dff(1)<= direction_dff(0);
direction_dff(0)<= sdirection;
dist_out_reg <= distance_out;
end if;
end if;
end process p;
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE",
lpm_pipeline => 0)
PORT MAP ( data => dist_out_reg,
eq => resdec);
gndc:if use_dedicated_circuitry=0 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gndc;
gdc:if use_dedicated_circuitry=1 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gdc;
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (lpm_width => widthd, lpm_direction => "SUB", lpm_type => "LPM_ADD_SUB", lpm_representation => "UNSIGNED", lpm_pipeline => 0)
port map ( dataa => max_distance, datab => distance, result => distance_sum, cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (direction_dff(2)='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gpipeline;
end SYNTH;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/18/2015 03:48:13 PM
-- Design Name:
-- Module Name: Register8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Register8Bit is
Port
(
Load : in BIT; -- Load Line
Sel : in BIT; -- Select Line
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
State : out BIT_VECTOR(7 downto 0) -- Current state of the Flip Flop
);
end Register8Bit;
architecture Behavioral of Register8Bit is
component FlipFlop1Bit is
Port
(
Load : in BIT; -- Load Line
Sel : in BIT; -- Select Line
Input : in BIT; -- Input Data
Output : out BIT; -- Output Data
State : out BIT -- Current state of the Flip Flop
);
end component FlipFlop1Bit;
begin
b0: FlipFlop1Bit port map (Load, Sel, Input(0), Output(0), State(0));
b1: FlipFlop1Bit port map (Load, Sel, Input(1), Output(1), State(1));
b2: FlipFlop1Bit port map (Load, Sel, Input(2), Output(2), State(2));
b3: FlipFlop1Bit port map (Load, Sel, Input(3), Output(3), State(3));
b4: FlipFlop1Bit port map (Load, Sel, Input(4), Output(4), State(4));
b5: FlipFlop1Bit port map (Load, Sel, Input(5), Output(5), State(5));
b6: FlipFlop1Bit port map (Load, Sel, Input(6), Output(6), State(6));
b7: FlipFlop1Bit port map (Load, Sel, Input(7), Output(7), State(7));
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:12:12 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ab_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-e.vhd,v 1.4 2005/10/06 11:16:07 wig Exp $
-- $Date: 2005/10/06 11:16:07 $
-- $Log: inst_ab_e-e.vhd,v $
-- Revision 1.4 2005/10/06 11:16:07 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ab_e
--
entity inst_ab_e is
-- Generics:
-- No Generated Generics for Entity inst_ab_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ab_e
bus20040728_altop_o1 : out std_ulogic_vector(3 downto 0);
bus20040728_o1 : out std_ulogic_vector(1 downto 0);
bus20040728_o2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
bus20040728_top_o1 : out std_ulogic_vector(3 downto 0);
bus20050930 : out std_ulogic_vector(4 downto 0);
bus20050930_2 : out std_ulogic_vector(5 downto 0);
bus20050930_3 : out std_ulogic_vector(4 downto 0);
bus20050930_p7 : out std_ulogic;
const_04 : in std_ulogic_vector(3 downto 0);
const_08_p : in std_ulogic_vector(4 downto 0);
const_09_p : in std_ulogic_vector(2 downto 0);
const_10_2 : in std_ulogic_vector(3 downto 0);
inst_duo_2 : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_ab_e
);
end inst_ab_e;
--
-- End of Generated Entity inst_ab_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2241.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02241ent IS
END c07s02b06x00p01n01i02241ent;
ARCHITECTURE c07s02b06x00p01n01i02241arch OF c07s02b06x00p01n01i02241ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
k := "goodbye, world" mod "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02241 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02241arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2241.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02241ent IS
END c07s02b06x00p01n01i02241ent;
ARCHITECTURE c07s02b06x00p01n01i02241arch OF c07s02b06x00p01n01i02241ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
k := "goodbye, world" mod "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02241 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02241arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2241.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02241ent IS
END c07s02b06x00p01n01i02241ent;
ARCHITECTURE c07s02b06x00p01n01i02241arch OF c07s02b06x00p01n01i02241ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
k := "goodbye, world" mod "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02241 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02241arch;
|
--Practica1 de Diseño Automatico de Sistemas
--Manejo barra de leds con switches.
--Desarrollada por Héctor Gutiérrez Palancarejo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch is
port(
a : in std_logic_vector(9 downto 0);
b : out std_logic_vector(9 downto 0)
);
end switch;
architecture rtl of switch is
begin
b <= not(a);
end rtl;
|
--
-- File Name: RandomBasePkg.vhd
-- Design Unit Name: RandomBasePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Defines Base randomization, seed definition, seed generation,
-- and seed IO functionality for RandomPkg.vhd
-- Defines:
-- Procedure Uniform - baseline randomization
-- Type RandomSeedType - the seed as a single object
-- function GenRandSeed from integer_vector, integer, or string
-- IO function to_string, & procedures write, read
--
-- In revision 2.0 these types and functions are included by package reference.
-- Long term these will be passed as generics to RandomGenericPkg
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2021 2021.06 Updated GenRandSeed hash to DJBX33A
-- 01/2020 2020.01 Updated Licenses to Apache
-- 6/2015 2015.06 Changed GenRandSeed to impure
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 5/2013 2013.05 No Changes
-- 4/2013 2013.04 No Changes
-- 03/01/2011 2.0 STANDARD VERSION
-- Fixed abstraction by moving RandomParmType to RandomPkg.vhd
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference
-- to ieee_proposed.standard_additions.all ;
-- 02/2009: 1.0 First Public Released Version
-- 01/2008: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2008 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.math_real.all ;
use std.textio.all ;
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use work.SortListPkg_int.all ;
-- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
package RandomBasePkg is
constant OSVVM_RANDOM_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
-----------------------------------------------------------------
-- note NULL_RANGE_TYPE should probably be in std.standard
subtype NULL_RANGE_TYPE is integer range 0 downto 1 ;
constant NULL_INTV : integer_vector (NULL_RANGE_TYPE) := (others => 0) ;
-----------------------------------------------------------------
-- RandomSeedType - Abstract the type for randomization
type RandomSeedType is array (1 to 2) of integer ;
-----------------------------------------------------------------
-- Uniform
-- Generate a random number with a Uniform distribution
-- Required by RandomPkg. All randomization is derived from here.
-- Value produced must be either:
-- 0 <= Value < 1 or 0 < Value < 1
--
-- Current version uses ieee.math_real.Uniform
-- This abstraction allows higher precision version
-- of a uniform distribution to be used provided
--
procedure Uniform (Result : out real ; Seed : inout RandomSeedType) ;
-----------------------------------------------------------------
-- GenRandSeed
-- Generate / hash a seed from a value that is integer_vector, String, Time, or Integer to RandomSeedType
-- Used by RandomPkg.InitSeed
-- GenRandSeed makes sure all values are in a valid range
impure function GenRandSeed (IV : integer_vector) return RandomSeedType ;
impure function OldGenRandSeed(IV : integer_vector) return RandomSeedType ;
impure function GenRandSeed (I : integer) return RandomSeedType ;
impure function OldGenRandSeed(I : integer) return RandomSeedType ;
impure function GenRandSeed (S : string) return RandomSeedType ;
impure function OldGenRandSeed(S : string) return RandomSeedType ;
-----------------------------------------------------------------
--- RandomSeedType IO
function to_string(A : RandomSeedType; Separator : string := " ") return string ;
procedure write(variable L: inout line ; A : RandomSeedType ) ;
procedure read (variable L: inout line ; A : out RandomSeedType ; good : out boolean ) ;
procedure read (variable L: inout line ; A : out RandomSeedType ) ;
-----------------------------------------------------------------
--- Distribution Types and read/write procedures
type RandomDistType is (NONE, UNIFORM, FAVOR_SMALL, FAVOR_BIG, NORMAL, POISSON) ;
type RandomParmType is record
Distribution : RandomDistType ;
Mean : Real ; -- also used as probability of success
StdDeviation : Real ; -- also used as number of trials for binomial
end record ;
-----------------------------------------------------------------
-- RandomParm IO
function to_string(A : RandomDistType) return string ;
procedure write(variable L : inout line ; A : RandomDistType ) ;
procedure read (variable L : inout line ; A : out RandomDistType ; good : out boolean ) ;
procedure read (variable L : inout line ; A : out RandomDistType ) ;
function to_string(A : RandomParmType) return string ;
procedure write(variable L : inout line ; A : RandomParmType ) ;
procedure read (variable L : inout line ; A : out RandomParmType ; good : out boolean ) ;
procedure read (variable L : inout line ; A : out RandomParmType ) ;
-----------------------------------------------------------------
--- Randomization Support
--- Scale - Scale a value to be within a given range
--- FavorSmall, FavorBig - Distribution Support
--- RemoveExclude
function Scale (A, Min, Max : real) return real ;
function Scale (A : real ; Min, Max : integer) return integer ;
function FavorSmall (A : real) return real ;
function FavorBig (A : real) return real ;
function to_time_vector (A : integer_vector ; Unit : time) return time_vector ;
function to_integer_vector (A : time_vector ; Unit : time) return integer_vector ;
procedure RemoveExclude (A, Exclude : integer_vector ; variable NewA : out integer_vector ; variable NewALength : inout natural ) ;
function inside (A : real ; Exclude : real_vector) return boolean ;
procedure RemoveExclude (A, Exclude : real_vector ; variable NewA : out real_vector ; variable NewALength : inout natural ) ;
function inside (A : time ; Exclude : time_vector) return boolean ;
procedure RemoveExclude (A, Exclude : time_vector ; variable NewA : out time_vector ; variable NewALength : inout natural ) ;
end RandomBasePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body RandomBasePkg is
-----------------------------------------------------------------
-- Uniform
-- Generate a random number with a Uniform distribution
-- Required by RandomPkg. All randomization is derived from here.
-- Value produced must be either:
-- 0 <= Value < 1 or 0 < Value < 1
--
-- Current version uses ieee.math_real.Uniform
-- This abstraction allows higher precision version
-- of a uniform distribution to be used provided
--
-----------------------------------------------------------------
procedure Uniform (
-----------------------------------------------------------------
Result : out real ;
Seed : inout RandomSeedType
) is
begin
ieee.math_real.Uniform (Seed(Seed'left), Seed(Seed'right), Result) ;
end procedure Uniform ;
-----------------------------------------------------------------
-- GenRandSeed
-- Convert integer_vector to RandomSeedType
-- Uniform requires two seed values of the form:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
--
-- if 2 seed values are passed to GenRandSeed and they are
-- in the above range, then they must remain unmodified.
------------------------------------------------------------
impure function GenRandSeed(IV : integer_vector) return RandomSeedType is
------------------------------------------------------------
alias iIV : integer_vector(1 to IV'length) is IV ;
variable Seed1 : integer ;
variable Seed2 : integer ;
constant SEED1_MAX : integer := 2147483562 ;
constant SEED2_MAX : integer := 2147483398 ;
begin
if iIV'Length <= 0 then -- no seed
Alert(OSVVM_ALERTLOG_ID, "RandomBasePkg.GenRandSeed received NULL integer_vector", FAILURE) ;
return (3, 17) ; -- if continue seed = (3, 17)
elsif iIV'Length = 1 then -- one seed value
-- inefficient handling, but condition is unlikely
return GenRandSeed(iIV(1)) ; -- generate a seed
else -- only use the left two values
-- mod returns 0 to MAX-1, the -1 adjusts legal values, +1 adjusts them back
-- 1 <= SEED1 <= 2147483562
Seed1 := ((iIV(1)-1) mod SEED1_MAX) + 1 ;
-- 1 <= SEED2 <= 2147483398
Seed2 := ((iIV(2)-1) mod SEED2_MAX) + 1 ;
return (Seed1, Seed2) ;
end if ;
end function GenRandSeed ;
------------------------------------------------------------
impure function OldGenRandSeed(IV : integer_vector) return RandomSeedType is
------------------------------------------------------------
alias iIV : integer_vector(1 to IV'length) is IV ;
variable Seed1 : integer ;
variable Seed2 : integer ;
constant SEED1_MAX : integer := 2147483562 ;
constant SEED2_MAX : integer := 2147483398 ;
begin
if iIV'Length <= 0 then -- no seed
Alert(OSVVM_ALERTLOG_ID, "RandomBasePkg.GenRandSeed received NULL integer_vector", FAILURE) ;
return (3, 17) ; -- if continue seed = (3, 17)
elsif iIV'Length = 1 then -- one seed value
-- inefficient handling, but condition is unlikely
return OldGenRandSeed(iIV(1)) ; -- generate a seed
else -- only use the left two values
-- mod returns 0 to MAX-1, the -1 adjusts legal values, +1 adjusts them back
-- 1 <= SEED1 <= 2147483562
Seed1 := ((iIV(1)-1) mod SEED1_MAX) + 1 ;
-- 1 <= SEED2 <= 2147483398
Seed2 := ((iIV(2)-1) mod SEED2_MAX) + 1 ;
return (Seed1, Seed2) ;
end if ;
end function OldGenRandSeed ;
-----------------------------------------------------------------
-- GenRandSeed - Integer
impure function GenRandSeed(I : integer) return RandomSeedType is
-----------------------------------------------------------------
variable result : RandomSeedType ;
begin
result(1) := integer((real(I) * 5381.0 + 313.0) mod 2.0 ** 30) ;
result(2) := integer((real(I) * 313.0 + 5381.0) mod 2.0 ** 30) ;
return result ; -- make value ranges legal
end function GenRandSeed ;
-----------------------------------------------------------------
impure function OldGenRandSeed(I : integer) return RandomSeedType is
-----------------------------------------------------------------
variable result : integer_vector(1 to 2) ;
begin
result(1) := I ;
result(2) := I/3 + 1 ;
return OldGenRandSeed(result) ; -- make value ranges legal
end function OldGenRandSeed ;
-----------------------------------------------------------------
-- GenRandSeed - String
-- usage: RV.GenRandSeed(RV'instance_path));
-- hash based on DJBX33A
impure function GenRandSeed(S : string) return RandomSeedType is
-----------------------------------------------------------------
constant LEN : integer := S'length ;
constant HALF_LEN : integer := LEN/2 ;
alias revS : string(LEN downto 1) is S ;
variable result : RandomSeedType ;
variable temp : real := 5381.0 ;
begin
for i in 1 to HALF_LEN loop
temp := (temp*33.0 + real(character'pos(revS(i)))) mod (2.0**30) ;
end loop ;
result(1) := integer(temp) ;
for i in HALF_LEN + 1 to LEN loop
temp := (temp*33.0 + real(character'pos(revS(i)))) mod (2.0**30) ;
end loop ;
result(2) := integer(temp) ;
return result ;
end function GenRandSeed ;
-----------------------------------------------------------------
impure function OldGenRandSeed(S : string) return RandomSeedType is
-----------------------------------------------------------------
constant LEN : integer := S'length ;
constant HALF_LEN : integer := LEN/2 ;
alias revS : string(LEN downto 1) is S ;
variable result : integer_vector(1 to 2) ;
variable temp : integer := 0 ;
begin
for i in 1 to HALF_LEN loop
temp := (temp + character'pos(revS(i))) mod (integer'right - 2**8) ;
end loop ;
result(1) := temp ;
for i in HALF_LEN + 1 to LEN loop
temp := (temp + character'pos(revS(i))) mod (integer'right - 2**8) ;
end loop ;
result(2) := temp ;
return OldGenRandSeed(result) ; -- make value ranges legal
end function OldGenRandSeed ;
-----------------------------------------------------------------
-- RandomSeedType IO
--
-----------------------------------------------------------------
function to_string(A : RandomSeedType; Separator : string := " ") return string is
-----------------------------------------------------------------
begin
return to_string(A(A'left)) & Separator & to_string(A(A'right)) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L: inout line ; A : RandomSeedType ) is
-----------------------------------------------------------------
begin
write(L, to_string(A)) ;
end procedure ;
-----------------------------------------------------------------
procedure read(variable L: inout line ; A : out RandomSeedType ; good : out boolean ) is
-----------------------------------------------------------------
variable iReadValid : boolean ;
begin
for i in A'range loop
read(L, A(i), iReadValid) ;
exit when not iReadValid ;
end loop ;
good := iReadValid ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L: inout line ; A : out RandomSeedType ) is
-----------------------------------------------------------------
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot(ReadValid, OSVVM_ALERTLOG_ID, "RandomBasePkg.read[line, RandomSeedType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
-- RandomParmType IO
--
-----------------------------------------------------------------
function to_string(A : RandomDistType) return string is
-----------------------------------------------------------------
begin
return RandomDistType'image(A) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomDistType ) is
-----------------------------------------------------------------
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) is
-----------------------------------------------------------------
variable strval : string(1 to 40) ;
variable len : natural ;
begin
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A := RandomDistType'value(strval(1 to len)) ;
good := len > 0 ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ) is
-----------------------------------------------------------------
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomDistType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
function to_string(A : RandomParmType) return string is
-----------------------------------------------------------------
begin
return RandomDistType'image(A.Distribution) & " " &
to_string(A.Mean, 2) & " " & to_string(A.StdDeviation, 2) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomParmType ) is
-----------------------------------------------------------------
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) is
-----------------------------------------------------------------
variable strval : string(1 to 40) ;
variable len : natural ;
variable igood : boolean ;
begin
loop
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A.Distribution := RandomDistType'value(strval(1 to len)) ;
igood := len > 0 ;
exit when not igood ;
read(L, A.Mean, igood) ;
exit when not igood ;
read(L, A.StdDeviation, igood) ;
exit ;
end loop ;
good := igood ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ) is
-----------------------------------------------------------------
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomParmType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
-- Randomization Support
-- Scale - Scale a value to be within a given range
-- FavorSmall, FavorBig - Distribution Support
-- RemoveExclude
--
-----------------------------------------------------------------
-- Scale - Scale a value to be within a given range
function Scale (A, Min, Max : real) return real is
-----------------------------------------------------------------
variable ValRange : Real ;
begin
ValRange := Max - Min ;
return A * ValRange + Min ;
--!! -- Already done checked and failed if error.
--!! -- If continuing this calculation is no worse than returning real'left
--!! if Max >= Min then
--!! ValRange := Max - Min ;
--!! return A * ValRange + Min ;
--!! else
--!! return real'left ;
--!! end if ;
end function Scale ;
-----------------------------------------------------------------
function Scale (A : real ; Min, Max : integer) return integer is
-----------------------------------------------------------------
variable ValRange : real ;
variable rMin, rMax : real ;
begin
rMin := real(Min) - 0.5 ;
rMax := real(Max) + 0.5 ;
ValRange := rMax - rMin ;
return integer(round(A * ValRange + rMin)) ;
--!! -- Already done checked and failed if error.
--!! -- If continuing this calculation is no worse than returning real'left
--!! if Max >= Min then
--!! rMin := real(Min) - 0.5 ;
--!! rMax := real(Max) + 0.5 ;
--!! ValRange := rMax - rMin ;
--!! return integer(round(A * ValRange + rMin)) ;
--!! else
--!! return integer'left ;
--!! end if ;
end function Scale ;
-----------------------------------------------------------------
-- FavorSmall - create more smaller values
function FavorSmall (A : real) return real is
-----------------------------------------------------------------
begin
return 1.0 - sqrt(A) ;
end FavorSmall ;
-----------------------------------------------------------------
-- FavorBig - create more larger values
-- alias FavorBig is sqrt[real return real] ;
function FavorBig (A : real) return real is
-----------------------------------------------------------------
begin
return sqrt(A) ;
end FavorBig ;
-----------------------------------------------------------------
-- local.
function to_time_vector (A : integer_vector ; Unit : time) return time_vector is
-----------------------------------------------------------------
variable result : time_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) * Unit ;
end loop ;
return result ;
end function to_time_vector ;
-----------------------------------------------------------------
-- local
function to_integer_vector (A : time_vector ; Unit : time) return integer_vector is
-----------------------------------------------------------------
variable result : integer_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) / Unit ;
end loop ;
return result ;
end function to_integer_vector ;
-----------------------------------------------------------------
-- Remove the exclude list from the list - integer_vector
procedure RemoveExclude(A, Exclude : integer_vector ; variable NewA : out integer_vector ; variable NewALength : inout natural ) is
-----------------------------------------------------------------
alias norm_NewA : integer_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-----------------------------------------------------------------
-- Inside - real_vector
function inside(A : real ; Exclude : real_vector) return boolean is
-----------------------------------------------------------------
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-----------------------------------------------------------------
-- Remove the exclude list from the list - real_vector
procedure RemoveExclude(A, Exclude : real_vector ; variable NewA : out real_vector ; variable NewALength : inout natural ) is
-----------------------------------------------------------------
alias norm_NewA : real_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-----------------------------------------------------------------
-- Inside - time_vector
function inside(A : time ; Exclude : time_vector) return boolean is
-----------------------------------------------------------------
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-----------------------------------------------------------------
-- Remove the exclude list from the list - time_vector
procedure RemoveExclude(A, Exclude : time_vector ; variable NewA : out time_vector ; variable NewALength : inout natural ) is
-----------------------------------------------------------------
alias norm_NewA : time_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
end RandomBasePkg ; |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: dltj007@gmail.com
-- Date : 29/06/2015 - 20:31
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ID_EX IS
PORT (clk : IN STD_LOGIC;
RegDst : IN STD_LOGIC;
Jump : IN STD_LOGIC;
Branch : IN STD_LOGIC;
MemRead : IN STD_LOGIC;
MemtoReg : IN STD_LOGIC;
ALUOp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
MemWrite : IN STD_LOGIC;
ALUSrc : IN STD_LOGIC;
RegWrite : IN STD_LOGIC;
JumpAddr : in std_logic_vector(31 downto 0);
RD1 : in std_logic_vector(31 downto 0);
RD2 : in std_logic_vector(31 downto 0);
RtE : in std_logic_vector(4 downto 0);
RdE : in std_logic_vector(4 downto 0);
SignExt : in std_logic_vector(31 downto 0);
PCPlus4 : in std_logic_vector(31 downto 0);
outRegDst : out std_logic;
outJump : out std_logic;
outBranch : out std_logic;
outMemRead : out std_logic;
outMemtoReg : out std_logic;
outALUOp : out STD_LOGIC_VECTOR(1 DOWNTO 0);
outMemWrite : out std_logic;
outALUSrc : out std_logic;
outRegWrite : out std_logic;
outRD1 : out std_logic_vector(31 downto 0);
outRD2 : out std_logic_vector(31 downto 0);
outRtE : out std_logic_vector(4 downto 0);
outRdE : out std_logic_vector(4 downto 0);
outSignExt : out std_logic_vector(31 downto 0);
outPCPlus4 : out std_logic_vector(31 downto 0);
JumpAddrOut : out std_logic_vector(31 downto 0));
END;
Architecture ARC_ID_EX of ID_EX is
BEGIN
PROCESS(clk)
BEGIN
IF( clk'event and clk = '1') THEN
outRegWrite <= RegWrite;
outMemtoReg <= MemtoReg;
outMemWrite <= MemWrite;
outBranch <= Branch;
outALUOp <= ALUOp;
outALUSrc <= ALUSrc;
outRegDst <= RegDst;
JumpAddrOut <= JumpAddr;
outRD1 <= RD1;
outRD2 <= RD2;
outRtE <= RtE;
outRdE <= RdE;
outSignExt <= SignExt;
outPCPlus4 <= PCPlus4;
END IF;
END PROCESS;
END;
|
package gen is
generic (type t);
end gen;
entity e is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture a of e is
subtype T_DATA is std_logic_vector(31 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
package pkg is new work.gen (t => t_data_vector);
begin
end architecture;
|
package gen is
generic (type t);
end gen;
entity e is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture a of e is
subtype T_DATA is std_logic_vector(31 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
package pkg is new work.gen (t => t_data_vector);
begin
end architecture;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY reg IS
GENERIC
(
width : integer
);
PORT
(
clock : IN std_logic;
change : IN std_logic_vector(width-1 downto 0);
state : OUT std_logic_vector(width-1 downto 0)
);
END reg;
ARCHITECTURE behaviour OF reg IS
COMPONENT dFlipFlop IS
PORT
(
c : IN std_logic;
i : IN std_logic;
q : OUT std_logic
);
END COMPONENT;
BEGIN
gen: FOR X IN 0 TO width-1 GENERATE
flipflopx : dFlipFlop PORT MAP (clock, change(X), state(X));
END GENERATE gen;
END behaviour;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
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