content stringlengths 1 1.04M ⌀ |
|---|
--============================================================================
--!
--! \file <FILE_NAME>
--!
--! \project <PROJECT_NAME>
--!
--! \langv VHDL-2008
--!
--! \brief <BRIEF_DESCRIPTION>.
--!
--! \details <DETAILED_DESCRIPTION>.
--!
--! \bug <BUGS_OR_KNOWN_ISSUES>.
--!
--! \see <R... |
library ieee;
use ieee.std_logic_1164.all;
package CU_TOP_FPGA_UART_components is
component CU_TOP_FPGA_UART_CoreUARTapb
GENERIC (
RX_LEGACY_MODE : integer := 0;
-- DEVICE FAMILY
FAMILY : integer := 15;
-- UART configuration parameters
T... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_544 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_544;
architecture augh of sub_544 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_544 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_544;
architecture augh of sub_544 is
signal carry_inA : std_l... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- File Name : DoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : DoubleFifo
--
-- Content : DoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
--------------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : DoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : DoubleFifo
--
-- Content : DoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
--------------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : DoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : DoubleFifo
--
-- Content : DoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
--------------------------------------------------... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
-- A single-port 2KiB RAM with synch read as recommended by Xilinx
-- (C) Copyright 2011 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the ... |
-------------------------------------------------------------------------------
--
-- Title : InstructionBuffer
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\... |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- dvb_dma_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use ... |
-- cb20_width_adapter.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 34;
IN_PKT_ADDR_L : integer := 18;
IN_PKT_DATA_H ... |
--**********************************************************************************************
-- Transparent latch(used in the synchronizer instead of the first DFF)
-- Version 0.2
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************... |
--**********************************************************************************************
-- Transparent latch(used in the synchronizer instead of the first DFF)
-- Version 0.2
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************... |
--**********************************************************************************************
-- Transparent latch(used in the synchronizer instead of the first DFF)
-- Version 0.2
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************... |
--**********************************************************************************************
-- Transparent latch(used in the synchronizer instead of the first DFF)
-- Version 0.2
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity spaceinvaders is port (
clk : in std_logic;
-- video pins
red : out STD_LOGIC_VECTOR (3 downto 0);
green : out STD_LOGIC_VECTOR (3 downto 0);
blue : out STD_LOGIC_VECTOR (3 downto ... |
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
port (
eop : out std_logic; ... |
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
port (
eop : out std_logic; ... |
--------------------------------------------------------------------------------
-- Title : Tx Module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_module.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@m... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:52:32 11/22/2015
-- Design Name:
-- Module Name: U4_1-Freq_Div - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo3.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo3 - entity / architecture pair
-----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo3.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo3 - entity / architecture pair
-----------------------------------------------------... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Automatically generated: write_netlist -wrapapp -vhdl -architecture reconflogic-wrapmax6682mean-a.vhd
architecture WrapMAX6682Mean of MyReconfigLogic is
component CfgIntf
generic (
-- Number of configuration chains
NumCfgs : integer := 3;
BaseAddr : integer := 16#0180#
);
port (
... |
library verilog;
use verilog.vl_types.all;
entity execute_port3 is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iRESET_SYNC : in vl_logic;
iFREE_EX : in vl_logic;
iFREE_SYSREG_NEW_SPR_VALID: in vl_logic;
iFREE_SYSR... |
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_example_design.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:27:52 10/09/2011
-- Design Name:
-- Module Name: C:/Users/BOB/Calculadora/Source/InputModuleTest.vhd
-- Project Name: Calculadora
-- Target Device:
-- Tool versions:
-- Descriptio... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:43:54 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Button Press Synchronizer para keys que são ativas baixas (ou seja, quando pressionadas vao para nivel baixo)
library ieee;
use ieee.std_logic_1164.all;
entity ButtonSync is
port
(
-- Input ports
key0 : in std_logic;
key1 : in std_logic;
key2 : in std_logic;
key3 : in std_logic;
clk : in std_lo... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -a --ieee=synopsis -fexplicit -Wc,-m32 -Wa,--32
-- -e -Wa,--32 -Wl,-m32
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dmem is
port (a: in std_logic_vector(31 downto 0);
wd: in std_logic_vector(31 downto 0);
clk, we: in std_logic;
rd: out std_logic_... |
-- **********************************************
-- * Banco de pruebas para SRAM de doble puerto *
-- **********************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_dp_tb is
generic(
DIR_ANCHO : integer:=2;
DATOS_ANCHO: integer:=8
);
end ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
-- File : bmp_sink.vhd
-- Author : mr-kenhoff
-------------------------------------------------------------------------------
-- Description:
-- Takes a data stream and saves it to a bitmap image
-- Target: Simulator
-- Depe... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 01-03-2017
-- Module Name: dff.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
entity cronometro is
port (
-- Entradas
startStop: in std_logic;
puestaCero: in std_logic;
clk: in std_logic;
rst: in std_logic;
-- Salidas
rightSegs: out std_logic_vector(7 d... |
--------------------------------------------------------------------------------
-- MIPS I CPU - Instruction Set --
--------------------------------------------------------------------------------
-- Type definitions of the MIPS I instruction (sub-)set and some convenie... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.std_logic_1164.all;
-- Flipflop-based N-bit register
entity REGISTER_FDE is
generic (
N: integer := 1
);
port (
DIN: in std_logic_vector(N-1 downto 0); -- Data in
ENABLE: in std_logic; -- Enable
CLK: in std_logic; -- Clock
RESET: in std_logic; -- Reset
DOUT: ou... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.math_real.all;
PACKAGE snake_pack IS
--TYPE int_s IS INTEGER RANGE -20 TO 255;
TYPE int_array IS array (0 to 127) OF INTEGER RANGE -20 TO 255;
COMPONENT conv_7seg IS
PORT (digit : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
seg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ... |
entity agg2 is
end entity;
architecture test of agg2 is
type int_array is array (integer range <>) of integer;
function all_ones(x : int_array) return int_array is
variable y : int_array(1 to x'length) := (others => 0);
begin
y := (others => 1);
return y;
end function;
... |
entity agg2 is
end entity;
architecture test of agg2 is
type int_array is array (integer range <>) of integer;
function all_ones(x : int_array) return int_array is
variable y : int_array(1 to x'length) := (others => 0);
begin
y := (others => 1);
return y;
end function;
... |
entity agg2 is
end entity;
architecture test of agg2 is
type int_array is array (integer range <>) of integer;
function all_ones(x : int_array) return int_array is
variable y : int_array(1 to x'length) := (others => 0);
begin
y := (others => 1);
return y;
end function;
... |
entity agg2 is
end entity;
architecture test of agg2 is
type int_array is array (integer range <>) of integer;
function all_ones(x : int_array) return int_array is
variable y : int_array(1 to x'length) := (others => 0);
begin
y := (others => 1);
return y;
end function;
... |
entity agg2 is
end entity;
architecture test of agg2 is
type int_array is array (integer range <>) of integer;
function all_ones(x : int_array) return int_array is
variable y : int_array(1 to x'length) := (others => 0);
begin
y := (others => 1);
return y;
end function;
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-... |
-------------------------------------------------------------------------------------
-- FILE NAME : amc7823_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - amc7823_ctrl
-- architecture - amc7823_ctrl_syn
--
-- LANGUAGE : VH... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity erode is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
----------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:21:13 05/22/2013
-- Design Name:
-- Module Name: Encoder4x2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity clock_div is
Port ( reset, clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC);
end clock_div;
architecture Behavioral of clock_div is
signal count : std_logic_vector( 3 downto 0 );
begin
clk_out <= count(3);
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:09:43 03/27/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet4/MII_test3.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Descri... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _ ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider_Demo is
port( LEDR : out std_logic_vector(0 downto 0);
CLOCK_50 : in std_logic;
SW : in std_logic_vector(1 downto 0);
HEX7 : out std_logic_vector(6 downto 0));
end FreqDivider_Demo;
architecture Structural of Freq... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: BuzzerDo.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- =================================... |
entity repro1 is
generic (WIDTH : natural := 4);
end;
architecture behav of repro1 is
type myarr is array(natural range <>) of bit_vector(WIDTH-1 downto 0);
type myrec is record
a: bit_vector(WIDTH-1 downto 0);
end record;
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture rtl of fifo is
begin
process begin
while condition loop end loop;
WHILE condition loop end loop;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_221 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_221;
architecture... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_221 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_221;
architecture... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Every HW component class has to be derived from :class:`hwt.synthesizer.unit.Unit` class
--
-- .. hwt-autodoc::
--
ENTITY Showcase0 IS
PORT(
a : IN UNSIGNED(31 DOWNTO 0);
b : IN SIGNED(31 DOWNTO 0);
c : OUT ... |
library verilog;
use verilog.vl_types.all;
entity SlaveArbiter is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
mAddrSel : in vl_logic_vector(4 downto 0);
addrPhEnd : in vl_logic;
m1GatedHMASTLOCK: in vl_logic;
m2... |
library verilog;
use verilog.vl_types.all;
entity SlaveArbiter is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
mAddrSel : in vl_logic_vector(4 downto 0);
addrPhEnd : in vl_logic;
m1GatedHMASTLOCK: in vl_logic;
m2... |
library verilog;
use verilog.vl_types.all;
entity SlaveArbiter is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
mAddrSel : in vl_logic_vector(4 downto 0);
addrPhEnd : in vl_logic;
m1GatedHMASTLOCK: in vl_logic;
m2... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00190
--
-- AUTHOR:
--
-- G. Tomi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Devel... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.