content stringlengths 1 1.04M ⌀ |
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--============================================================================
--!
--! \file <FILE_NAME>
--!
--! \project <PROJECT_NAME>
--!
--! \langv VHDL-2008
--!
--! \brief <BRIEF_DESCRIPTION>.
--!
--! \details <DETAILED_DESCRIPTION>.
--!
--! \bug <BUGS_OR_KNOWN_ISSUES>.
--!
--! \see <REFERENCES>
--!
--! \copyright <COPYRIGHT_OR_LICENSE>
--!
--! Revision history:
--!
--! \version <VERSION>
--! \date <YYYY-MM-DD>
--! \author <AUTHOR_NAME>
--! \brief Create file.
--!
--============================================================================
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity template_testbench is
end entity template_testbench;
architecture tb of template_testbench is
begin
end architecture tb;
|
library ieee;
use ieee.std_logic_1164.all;
package CU_TOP_FPGA_UART_components is
component CU_TOP_FPGA_UART_CoreUARTapb
GENERIC (
RX_LEGACY_MODE : integer := 0;
-- DEVICE FAMILY
FAMILY : integer := 15;
-- UART configuration parameters
TX_FIFO : integer := 0; -- 1 = with tx fifo, 0 = without tx fifo
RX_FIFO : integer := 0; -- 1 = with rx fifo, 0 = without rx fifo
BAUD_VALUE : integer := 0; -- Baud value is set only when fixed buad rate is selected
FIXEDMODE : integer := 0; -- fixed or programmable mode, 0: programmable; 1:fixed
PRG_BIT8 : integer := 0; -- This bit value is selected only when FIXEDMODE is set to 1
PRG_PARITY : integer := 0; -- This bit value is selected only when FIXEDMODE is set to 1
BAUD_VAL_FRCTN : integer := 0; -- 0 = +0.0, 1 = +0.125, 2 = +0.25, 3 = +0.375, 4 = +0.5, 5 = +0.625, 6 = +0.75, 7 = +0.875,
BAUD_VAL_FRCTN_EN : integer := 0 -- 1 = enable baud fraction, 0 = disable baud fraction
);
PORT (
-- Inputs and Outputs
-- APB signals
PCLK : IN std_logic; -- APB system clock
PRESETN : IN std_logic; -- APB system reset
PADDR : IN std_logic_vector(4 DOWNTO 0); -- Address
PSEL : IN std_logic; -- Peripheral select signal
PENABLE : IN std_logic; -- Enable (data valid strobe)
PWRITE : IN std_logic; -- Write/nRead signal
PWDATA : IN std_logic_vector(7 DOWNTO 0); -- 8 bit write data
PRDATA : OUT std_logic_vector(7 DOWNTO 0); -- 8 bit read data
-- AS: Added PREADY and PSLVERR
PREADY : OUT std_logic; -- APB READY signal (tied to 1)
PSLVERR : OUT std_logic; -- APB slave error signal (tied to 0)
-- transmit ready and receive full indicators
TXRDY : OUT std_logic;
RXRDY : OUT std_logic;
-- FLAGS
FRAMING_ERR : OUT std_logic;
PARITY_ERR : OUT std_logic;
OVERFLOW : OUT std_logic;
-- Serial receive and transmit data
RX : IN std_logic;
TX : OUT std_logic
);
end component;
end CU_TOP_FPGA_UART_components; |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_544 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_544;
architecture augh of sub_544 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_544 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_544;
architecture augh of sub_544 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: game_over_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY game_over_tb IS
END ENTITY;
ARCHITECTURE game_over_tb_ARCH OF game_over_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
game_over_synth_inst:ENTITY work.game_over_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc159.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p19n05i00159pkg is
type t is array (1 to 4) of integer;
procedure p (a: in t);
end c04s03b02x02p19n05i00159pkg;
package body c04s03b02x02p19n05i00159pkg is
procedure p (a: in t) is
begin
end p;
end c04s03b02x02p19n05i00159pkg;
use work.c04s03b02x02p19n05i00159pkg.all;
ENTITY c04s03b02x02p19n05i00159ent IS
END c04s03b02x02p19n05i00159ent;
ARCHITECTURE c04s03b02x02p19n05i00159arch OF c04s03b02x02p19n05i00159ent IS
BEGIN
TESTING: PROCESS
variable i : integer := 2;
BEGIN
p (t'(i => 12, others => 0)); -- Failure_here
assert FALSE
report "***FAILED TEST: c04s03b02x02p19n05i00159 - Subelements of an association list may only be locally static names."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p19n05i00159arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc159.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p19n05i00159pkg is
type t is array (1 to 4) of integer;
procedure p (a: in t);
end c04s03b02x02p19n05i00159pkg;
package body c04s03b02x02p19n05i00159pkg is
procedure p (a: in t) is
begin
end p;
end c04s03b02x02p19n05i00159pkg;
use work.c04s03b02x02p19n05i00159pkg.all;
ENTITY c04s03b02x02p19n05i00159ent IS
END c04s03b02x02p19n05i00159ent;
ARCHITECTURE c04s03b02x02p19n05i00159arch OF c04s03b02x02p19n05i00159ent IS
BEGIN
TESTING: PROCESS
variable i : integer := 2;
BEGIN
p (t'(i => 12, others => 0)); -- Failure_here
assert FALSE
report "***FAILED TEST: c04s03b02x02p19n05i00159 - Subelements of an association list may only be locally static names."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p19n05i00159arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc159.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p19n05i00159pkg is
type t is array (1 to 4) of integer;
procedure p (a: in t);
end c04s03b02x02p19n05i00159pkg;
package body c04s03b02x02p19n05i00159pkg is
procedure p (a: in t) is
begin
end p;
end c04s03b02x02p19n05i00159pkg;
use work.c04s03b02x02p19n05i00159pkg.all;
ENTITY c04s03b02x02p19n05i00159ent IS
END c04s03b02x02p19n05i00159ent;
ARCHITECTURE c04s03b02x02p19n05i00159arch OF c04s03b02x02p19n05i00159ent IS
BEGIN
TESTING: PROCESS
variable i : integer := 2;
BEGIN
p (t'(i => 12, others => 0)); -- Failure_here
assert FALSE
report "***FAILED TEST: c04s03b02x02p19n05i00159 - Subelements of an association list may only be locally static names."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p19n05i00159arch;
|
-------------------------------------------------------------------------------
-- File Name : DoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : DoubleFifo
--
-- Content : DoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(7 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end entity DoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(7 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(7 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(7 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(7 downto 0);
signal fifo_data_in : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
data_out <= (others => '0');
fifo1_rd <= '0';
fifo2_rd <= '0';
fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
data_out <= fifo1_q;
fifo1_rd <= rd_req;
fifo_empty <= fifo1_empty;
else
data_out <= fifo2_q;
fifo2_rd <= rd_req;
fifo_empty <= fifo2_empty;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : DoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : DoubleFifo
--
-- Content : DoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(7 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end entity DoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(7 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(7 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(7 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(7 downto 0);
signal fifo_data_in : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
data_out <= (others => '0');
fifo1_rd <= '0';
fifo2_rd <= '0';
fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
data_out <= fifo1_q;
fifo1_rd <= rd_req;
fifo_empty <= fifo1_empty;
else
data_out <= fifo2_q;
fifo2_rd <= rd_req;
fifo_empty <= fifo2_empty;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : DoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : DoubleFifo
--
-- Content : DoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(7 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end entity DoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(7 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(7 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(7 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(7 downto 0);
signal fifo_data_in : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
data_out <= (others => '0');
fifo1_rd <= '0';
fifo2_rd <= '0';
fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
data_out <= fifo1_q;
fifo1_rd <= rd_req;
fifo_empty <= fifo1_empty;
else
data_out <= fifo2_q;
fifo2_rd <= rd_req;
fifo_empty <= fifo2_empty;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity DoubleDiv is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_divbyzero : out std_logic;
o_overflow : out std_logic;
o_underflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end;
architecture arch_DoubleDiv of DoubleDiv is
component idiv53 is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_divident : in std_logic_vector(52 downto 0);
i_divisor : in std_logic_vector(52 downto 0);
o_result : out std_logic_vector(104 downto 0);
o_lshift : out std_logic_vector(6 downto 0);
o_rdy : out std_logic;
o_overflow : out std_logic;
o_zero_resid : out std_logic
);
end component;
type RegistersType is record
busy : std_logic;
ena : std_logic_vector(4 downto 0);
a : std_logic_vector(63 downto 0);
b : std_logic_vector(63 downto 0);
result : std_logic_vector(63 downto 0);
zeroA : std_logic;
zeroB : std_logic;
divisor : std_logic_vector(52 downto 0);
preShift : std_logic_vector(5 downto 0);
expAB : std_logic_vector(12 downto 0);
expAlign : std_logic_vector(11 downto 0);
mantAlign : std_logic_vector(104 downto 0);
postShift : std_logic_vector(11 downto 0);
mantPostScale : std_logic_vector(104 downto 0);
nanRes : std_logic;
overflow : std_logic;
underflow : std_logic;
illegal_op : std_logic;
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), -- busy, ena
(others => '0'), (others => '0'), (others => '0'), -- a, b, result
'0', '0', (others => '0'), (others => '0'), -- zeroA, zeroB, divisor, preShift
(others => '0'), (others => '0'), (others => '0'), -- expAB, expAlign, mantAlign
(others => '0'), (others => '0'), -- postShift, mantPostScale
'0', '0', '0', '0' -- nanRes, overflow, underflow, illegal_op
);
constant zero105 : std_logic_vector(104 downto 0) := (others => '0');
signal r, rin : RegistersType;
signal w_idiv_ena : std_logic;
signal wb_divident : std_logic_vector(52 downto 0);
signal wb_divisor : std_logic_vector(52 downto 0);
signal wb_idiv_result : std_logic_vector(104 downto 0);
signal wb_idiv_lshift : std_logic_vector(6 downto 0);
signal w_idiv_rdy : std_logic;
signal w_idiv_overflow : std_logic;
signal w_idiv_zeroresid : std_logic;
begin
u_idiv53 : idiv53 generic map (
async_reset => async_reset
) port map (
i_nrst => i_nrst,
i_clk => i_clk,
i_ena => w_idiv_ena,
i_divident => wb_divident,
i_divisor => wb_divisor,
o_result => wb_idiv_result,
o_lshift => wb_idiv_lshift,
o_rdy => w_idiv_rdy,
o_overflow => w_idiv_overflow,
o_zero_resid => w_idiv_zeroresid
);
-- registers:
comb : process(i_nrst, i_ena, i_a, i_b, r,
wb_idiv_result, wb_idiv_lshift, w_idiv_rdy, w_idiv_overflow,
w_idiv_zeroresid)
variable v : RegistersType;
variable signA : std_logic;
variable signB : std_logic;
variable mantA : std_logic_vector(52 downto 0);
variable mantB : std_logic_vector(52 downto 0);
variable zeroA : std_logic;
variable zeroB : std_logic;
variable divisor : std_logic_vector(52 downto 0);
variable preShift : integer range 0 to 52;
variable expAB_t : std_logic_vector(11 downto 0);
variable expAB : std_logic_vector(12 downto 0);
variable mantAlign : std_logic_vector(104 downto 0);
variable expShift : std_logic_vector(11 downto 0);
variable expAlign : std_logic_vector(12 downto 0);
variable postShift : std_logic_vector(11 downto 0);
variable mantPostScale : std_logic_vector(104 downto 0);
variable mantShort : std_logic_vector(52 downto 0);
variable tmpMant05 : std_logic_vector(51 downto 0);
variable mantOnes : std_logic;
variable mantEven : std_logic;
variable mant05 : std_logic;
variable rndBit : std_logic;
variable nanA : std_logic;
variable nanB : std_logic;
variable mantZeroA : std_logic;
variable mantZeroB : std_logic;
variable res : std_logic_vector(63 downto 0);
begin
v := r;
v.ena(0) := i_ena and not r.busy;
v.ena(1) := r.ena(0);
v.ena(4 downto 2) := r.ena(3 downto 2) & w_idiv_rdy;
if i_ena = '1' then
v.busy := '1';
v.overflow := '0';
v.underflow := '0';
v.illegal_op := '0';
v.a := i_a;
v.b := i_b;
end if;
signA := r.a(63);
signB := r.b(63);
zeroA := '0';
if r.a(62 downto 0) = zero105(62 downto 0) then
zeroA := '1';
end if;
zeroB := '0';
if r.b(62 downto 0) = zero105(62 downto 0) then
zeroB := '1';
end if;
mantA(51 downto 0) := r.a(51 downto 0);
mantA(52) := '0';
if r.a(62 downto 52) /= zero105(10 downto 0) then
mantA(52) := '1';
end if;
mantB(51 downto 0) := r.b(51 downto 0);
mantB(52) := '0';
if r.b(62 downto 52) /= zero105(10 downto 0) then
mantB(52) := '1';
divisor := mantB;
preShift := 0;
else
divisor := mantB;
preShift := 0;
for i in 1 to 52 loop
if preShift = 0 and mantB(52 - i) = '1' then
divisor := mantB(52-i downto 0) & zero105(i-1 downto 0);
preShift := i;
end if;
end loop;
end if;
-- expA - expB + 1023
expAB_t := ('0' & r.a(62 downto 52)) + 1023;
expAB := ('0' & expAB_t) - ("00" & r.b(62 downto 52));
if r.ena(0) = '1' then
v.divisor := divisor;
v.preShift := conv_std_logic_vector(preShift, 6);
v.expAB := expAB;
v.zeroA := zeroA;
v.zeroB := zeroB;
end if;
w_idiv_ena <= r.ena(1);
wb_divident <= mantA;
wb_divisor <= r.divisor;
-- idiv53 module:
mantAlign := (others => '0');
if wb_idiv_lshift = zero105(6 downto 0) then
mantAlign := wb_idiv_result;
else
for i in 1 to 104 loop
if i = conv_integer(wb_idiv_lshift) then
mantAlign := wb_idiv_result(104-i downto 0) & zero105(i-1 downto 0);
end if;
end loop;
end if;
expShift := ("000000" & r.preShift) - ("00000" & wb_idiv_lshift);
if r.b(62 downto 52) = "00000000000" and r.a(62 downto 52) /= "00000000000" then
expShift := expShift - 1;
elsif r.b(62 downto 52) /= "00000000000" and r.a(62 downto 52) = "00000000000" then
expShift := expShift + 1;
end if;
expAlign := r.expAB + (expShift(11) & expShift);
if expAlign(12) = '1' then
postShift := not expAlign(11 downto 0) + 2;
else
postShift := (others => '0');
end if;
if w_idiv_rdy = '1' then
v.expAlign := expAlign(11 downto 0);
v.mantAlign := mantAlign;
v.postShift := postShift;
-- Exceptions:
v.nanRes := '0';
if expAlign = "0011111111111" then
v.nanRes := '1';
end if;
v.overflow := not expAlign(12) and expAlign(11);
v.underflow := expAlign(12) and expAlign(11);
end if;
-- Prepare to mantissa post-scale
mantPostScale := (others => '0');
if r.postShift = X"000" then
mantPostScale := r.mantAlign;
elsif r.postShift < conv_std_logic_vector(105, 12) then
for i in 1 to 104 loop
if conv_std_logic_vector(i, 7) = r.postShift(6 downto 0) then
mantPostScale := zero105(i-1 downto 0) & r.mantAlign(104 downto i);
end if;
end loop;
end if;
if r.ena(2) = '1' then
v.mantPostScale := mantPostScale;
end if;
-- Rounding bit
mantShort := r.mantPostScale(104 downto 52);
tmpMant05 := r.mantPostScale(51 downto 0);
mantOnes := '0';
if mantShort(52) = '1' and mantShort(51 downto 0) = X"fffffffffffff" then
mantOnes := '1';
end if;
mantEven := r.mantPostScale(52);
mant05 := '0';
if tmpMant05 = X"8000000000000" then
mant05 := '1';
end if;
rndBit := r.mantPostScale(51) and not(mant05 and not mantEven);
-- Check Borders
nanA := '0';
if r.a(62 downto 52) = "11111111111" then
nanA := '1';
end if;
nanB := '0';
if r.b(62 downto 52) = "11111111111" then
nanB := '1';
end if;
mantZeroA := '0';
if r.a(51 downto 0) = zero105(51 downto 0) then
mantZeroA := '1';
end if;
mantZeroB := '0';
if r.b(51 downto 0) = zero105(51 downto 0) then
mantZeroB := '1';
end if;
-- Result multiplexers:
if (nanA and mantZeroA and nanB and mantZeroB) = '1' then
res(63) := '1';
elsif (nanA and not mantZeroA) = '1' then
res(63) := signA;
elsif (nanB and not mantZeroB) = '1' then
res(63) := signB;
elsif (r.zeroA and r.zeroB) = '1' then
res(63) := '1';
else
res(63) := r.a(63) xor r.b(63);
end if;
if nanB = '1' and mantZeroB = '0' then
res(62 downto 52) := r.b(62 downto 52);
elsif (r.underflow or r.zeroA) = '1' and r.zeroB = '0' then
res(62 downto 52) := (others => '0');
elsif (r.overflow or r.zeroB) = '1' then
res(62 downto 52) := (others => '1');
elsif nanA = '1' then
res(62 downto 52) := r.a(62 downto 52);
elsif ((nanB and mantZeroB) or r.expAlign(11)) = '1' then
res(62 downto 52) := (others => '0');
else
res(62 downto 52) := r.expAlign(10 downto 0)
+ (mantOnes and rndBit and not r.overflow);
end if;
if (r.zeroA and r.zeroB) = '1'
or (nanA and mantZeroA and nanB and mantZeroB) = '1' then
res(51) := '1';
res(50 downto 0) := (others => '0');
elsif nanA = '1' and mantZeroA = '0' then
res(51) := '1';
res(50 downto 0) := r.a(50 downto 0);
elsif nanB = '1' and mantZeroB = '0'then
res(51) := '1';
res(50 downto 0) := r.b(50 downto 0);
elsif r.overflow = '1' or r.nanRes = '1' or (nanA and mantZeroA) = '1'
or (nanB and mantZeroB) = '1' then
res(51 downto 0) := (others => '0');
else
res(51 downto 0) := mantShort(51 downto 0) + rndBit;
end if;
if r.ena(3) = '1' then
v.result := res;
v.illegal_op := nanA or nanB;
v.busy := '0';
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_res <= r.result;
o_illegal_op <= r.illegal_op;
o_divbyzero <= r.zeroB;
o_overflow <= r.overflow;
o_underflow <= r.underflow;
o_valid <= r.ena(4);
o_busy <= r.busy;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
|
-- A single-port 2KiB RAM with synch read as recommended by Xilinx
-- (C) Copyright 2011 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram2k is
port (clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(10 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0));
end ram2k;
architecture syn of ram2k is
type ram_type is array (0 to 2047) of std_logic_vector (7 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(a)) <= di;
end if;
do <= RAM(conv_integer(a));
end if;
end process;
end syn;
|
-------------------------------------------------------------------------------
--
-- Title : InstructionBuffer
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\InstructionBuffer.vhd
-- Generated : Wed Dec 7 14:16:19 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {InstructionBuffer} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity InstructionBuffer is
port (
instruction_din: in std_logic_vector(255 downto 0);
instruction_load_enable : in std_logic;
clk : in std_logic;
instruction_dout : out std_logic_vector(15 downto 0)
);
end InstructionBuffer;
--}} End of automatically maintained section
architecture behavioral of InstructionBuffer is
type instruction_buffer is array (0 to 15) of std_logic_vector(15 downto 0); --16 ,16 bit instructions
begin
instructions: process(clk)
variable instruction_buffer_v : instruction_buffer;
variable program_counter : integer range 0 to 15 := 0;
begin
if instruction_load_enable = '1' then
program_counter := 0;
instruction_buffer_v(0) := instruction_din(255 downto 240);
instruction_buffer_v(1) := instruction_din(239 downto 224);
instruction_buffer_v(2) := instruction_din(223 downto 208);
instruction_buffer_v(3) := instruction_din(207 downto 192);
instruction_buffer_v(4) := instruction_din(191 downto 176);
instruction_buffer_v(5) := instruction_din(175 downto 160);
instruction_buffer_v(6) := instruction_din(159 downto 144);
instruction_buffer_v(7) := instruction_din(143 downto 128);
instruction_buffer_v(8) := instruction_din(127 downto 112);
instruction_buffer_v(9) := instruction_din(111 downto 96);
instruction_buffer_v(10) := instruction_din(95 downto 80);
instruction_buffer_v(11) := instruction_din(79 downto 64);
instruction_buffer_v(12) := instruction_din(63 downto 48);
instruction_buffer_v(13) := instruction_din(47 downto 32);
instruction_buffer_v(14) := instruction_din(31 downto 16);
instruction_buffer_v(15) := instruction_din(15 downto 0);
else
if rising_edge(clk) then
instruction_dout <= instruction_buffer_v(program_counter);
if program_counter /= 15 then
program_counter := program_counter + 1;
end if;
end if;
end if;
end process;
end behavioral;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- dvb_dma_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dvb_dma_0 is
port (
address : in std_logic_vector(3 downto 0) := (others => '0'); -- avalon_slave_0.address
byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(31 downto 0); -- .readdata
clk : in std_logic := '0'; -- clock.clk
dvb_sop : in std_logic := '0'; -- conduit_end.export
dvb_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_dval : in std_logic := '0'; -- .export
mem_size : out std_logic_vector(6 downto 0); -- .export
mem_addr : out std_logic_vector(60 downto 0); -- .export
mem_byteen : out std_logic_vector(7 downto 0); -- .export
mem_wrdata : out std_logic_vector(63 downto 0); -- .export
mem_write : out std_logic; -- .export
mem_waitreq : in std_logic := '0'; -- .export
interrupt : out std_logic; -- .export
rst : in std_logic := '0' -- reset_sink.reset
);
end entity dvb_dma_0;
architecture rtl of dvb_dma_0 is
component dvb_dma is
port (
address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
clk : in std_logic := 'X'; -- clk
dvb_sop : in std_logic := 'X'; -- export
dvb_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_dval : in std_logic := 'X'; -- export
mem_size : out std_logic_vector(6 downto 0); -- export
mem_addr : out std_logic_vector(60 downto 0); -- export
mem_byteen : out std_logic_vector(7 downto 0); -- export
mem_wrdata : out std_logic_vector(63 downto 0); -- export
mem_write : out std_logic; -- export
mem_waitreq : in std_logic := 'X'; -- export
interrupt : out std_logic; -- export
rst : in std_logic := 'X' -- reset
);
end component dvb_dma;
begin
dvb_dma_0 : component dvb_dma
port map (
address => address, -- avalon_slave_0.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
clk => clk, -- clock.clk
dvb_sop => dvb_sop, -- conduit_end.export
dvb_data => dvb_data, -- .export
dvb_dval => dvb_dval, -- .export
mem_size => mem_size, -- .export
mem_addr => mem_addr, -- .export
mem_byteen => mem_byteen, -- .export
mem_wrdata => mem_wrdata, -- .export
mem_write => mem_write, -- .export
mem_waitreq => mem_waitreq, -- .export
interrupt => interrupt, -- .export
rst => rst -- reset_sink.reset
);
end architecture rtl; -- of dvb_dma_0
|
-- cb20_width_adapter.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 34;
IN_PKT_ADDR_L : integer := 18;
IN_PKT_DATA_H : integer := 15;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 17;
IN_PKT_BYTEEN_L : integer := 16;
IN_PKT_BYTE_CNT_H : integer := 43;
IN_PKT_BYTE_CNT_L : integer := 41;
IN_PKT_TRANS_COMPRESSED_READ : integer := 35;
IN_PKT_BURSTWRAP_H : integer := 44;
IN_PKT_BURSTWRAP_L : integer := 44;
IN_PKT_BURST_SIZE_H : integer := 47;
IN_PKT_BURST_SIZE_L : integer := 45;
IN_PKT_RESPONSE_STATUS_H : integer := 69;
IN_PKT_RESPONSE_STATUS_L : integer := 68;
IN_PKT_TRANS_EXCLUSIVE : integer := 40;
IN_PKT_BURST_TYPE_H : integer := 49;
IN_PKT_BURST_TYPE_L : integer := 48;
IN_ST_DATA_W : integer := 70;
OUT_PKT_ADDR_H : integer := 52;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 61;
OUT_PKT_BYTE_CNT_L : integer := 59;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 53;
OUT_PKT_BURST_SIZE_H : integer := 65;
OUT_PKT_BURST_SIZE_L : integer := 63;
OUT_PKT_RESPONSE_STATUS_H : integer := 87;
OUT_PKT_RESPONSE_STATUS_L : integer := 86;
OUT_PKT_TRANS_EXCLUSIVE : integer := 58;
OUT_PKT_BURST_TYPE_H : integer := 67;
OUT_PKT_BURST_TYPE_L : integer := 66;
OUT_ST_DATA_W : integer := 88;
ST_CHANNEL_W : integer := 6;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(5 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(69 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(87 downto 0); -- .data
out_channel : out std_logic_vector(5 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity cb20_width_adapter;
architecture rtl of cb20_width_adapter is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(87 downto 0); -- data
out_channel : out std_logic_vector(5 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of cb20_width_adapter
|
--**********************************************************************************************
-- Transparent latch(used in the synchronizer instead of the first DFF)
-- Version 0.2
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity SynchronizerLatch is port(
D : in std_logic;
G : in std_logic;
Q : out std_logic;
QN : out std_logic);
end SynchronizerLatch;
architecture RTL of SynchronizerLatch is
signal Q_Tmp : std_logic;
begin
TransparentLatch:process(G,D)
begin
if G='1' then -- Latch is transparent
Q_Tmp <= D;
end if;
end process;
Q <= Q_Tmp;
QN <= not Q_Tmp;
end RTL;
|
--**********************************************************************************************
-- Transparent latch(used in the synchronizer instead of the first DFF)
-- Version 0.2
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity SynchronizerLatch is port(
D : in std_logic;
G : in std_logic;
Q : out std_logic;
QN : out std_logic);
end SynchronizerLatch;
architecture RTL of SynchronizerLatch is
signal Q_Tmp : std_logic;
begin
TransparentLatch:process(G,D)
begin
if G='1' then -- Latch is transparent
Q_Tmp <= D;
end if;
end process;
Q <= Q_Tmp;
QN <= not Q_Tmp;
end RTL;
|
--**********************************************************************************************
-- Transparent latch(used in the synchronizer instead of the first DFF)
-- Version 0.2
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity SynchronizerLatch is port(
D : in std_logic;
G : in std_logic;
Q : out std_logic;
QN : out std_logic);
end SynchronizerLatch;
architecture RTL of SynchronizerLatch is
signal Q_Tmp : std_logic;
begin
TransparentLatch:process(G,D)
begin
if G='1' then -- Latch is transparent
Q_Tmp <= D;
end if;
end process;
Q <= Q_Tmp;
QN <= not Q_Tmp;
end RTL;
|
--**********************************************************************************************
-- Transparent latch(used in the synchronizer instead of the first DFF)
-- Version 0.2
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity SynchronizerLatch is port(
D : in std_logic;
G : in std_logic;
Q : out std_logic;
QN : out std_logic);
end SynchronizerLatch;
architecture RTL of SynchronizerLatch is
signal Q_Tmp : std_logic;
begin
TransparentLatch:process(G,D)
begin
if G='1' then -- Latch is transparent
Q_Tmp <= D;
end if;
end process;
Q <= Q_Tmp;
QN <= not Q_Tmp;
end RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity spaceinvaders is port (
clk : in std_logic;
-- video pins
red : out STD_LOGIC_VECTOR (3 downto 0);
green : out STD_LOGIC_VECTOR (3 downto 0);
blue : out STD_LOGIC_VECTOR (3 downto 0);
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
-- reset pin
reset : in std_logic;
leds : out STD_LOGIC_VECTOR(3 downto 0));
end spaceinvaders;
architecture Behavioral of spaceinvaders is
signal clk10mhz : STD_LOGIC;
signal clk133mhz : STD_LOGIC;
signal clk133mhzinv : STD_LOGIC;
signal clk25mhz : STD_LOGIC;
signal addressBus : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal dataBusReady : STD_LOGIC := '0';
signal cpuInt : STD_LOGIC := '0';
signal cpuHold : STD_LOGIC := '0';
signal cpuDataIn : STD_LOGIC_VECTOR(7 downto 0);
signal cpuDataOut : STD_LOGIC_VECTOR(7 downto 0);
signal cpuDataBusInputMode : STD_LOGIC;
signal cpuStatus : std_logic_vector(3 downto 0);
signal cpuSync : std_logic;
signal cpuWaitAck : std_logic;
signal cpuWr : std_logic;
signal cpuHlda : std_logic;
signal cpuInte : std_logic;
signal romDataOut : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal romAddr : STD_LOGIC_VECTOR(12 DOWNTO 0) := (others => '0');
signal ramAddr : STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
signal ramDataOut : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal ramDataIn : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
signal ramWea : STD_LOGIC_VECTOR(0 DOWNTO 0) := "0";
signal vramAddrA : STD_LOGIC_VECTOR(12 DOWNTO 0) := (others => '0');
signal vramDataOutA: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal vramDataInA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
signal vramAddrB : STD_LOGIC_VECTOR(12 DOWNTO 0) := (others => '0');
signal vramDataOutB : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal vramWea : STD_LOGIC_VECTOR(0 DOWNTO 0) := "0";
COMPONENT clocks PORT (
clkin : in STD_LOGIC;
clk10mhz : out STD_LOGIC;
clk133mhz : out STD_LOGIC;
clk133mhzinv : out STD_LOGIC;
clk25mhz : out STD_LOGIC);
END COMPONENT;
COMPONENT video PORT (
clkin25mhz : in STD_LOGIC;
red : out STD_LOGIC_VECTOR (3 downto 0);
green : out STD_LOGIC_VECTOR (3 downto 0);
blue : out STD_LOGIC_VECTOR (3 downto 0);
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
vramAddr : out STD_LOGIC_VECTOR (12 downto 0);
vramData : in STD_LOGIC_VECTOR (7 downto 0);
colourOutput : in STD_LOGIC);
END COMPONENT;
COMPONENT vram PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT ram PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT rom PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT i8080 PORT (
clk : IN std_logic;
dataIn : IN std_logic_vector(7 downto 0);
ready : IN std_logic;
hold : IN std_logic;
int : IN std_logic;
reset : IN std_logic;
addressBus : OUT std_logic_vector(15 downto 0);
dataOut : OUT std_logic_vector(7 downto 0);
sync : OUT std_logic;
dataBusIn : OUT std_logic;
waitAck : OUT std_logic;
wr : OUT std_logic;
hlda : OUT std_logic;
inte : OUT std_logic;
status : OUT std_logic_vector(3 downto 0));
END COMPONENT;
type memControllerState is (idle, read0, read1, write0);
signal memState : memControllerState := idle;
signal vgaVsync : std_logic;
BEGIN
process (vgaVsync)
begin
if (rising_edge(vgaVsync)) then
-- interrupt at end of scan (RST 10)
cpuInt <= '1';
else
if (cpuInte = '0') then
cpuInt <= '0';
end if;
end if;
end process;
process (clk10mhz)
variable writing : std_logic := '0';
variable vramAddrAWide : STD_LOGIC_VECTOR(15 DOWNTO 0);
variable ramAddrWide : STD_LOGIC_VECTOR(15 DOWNTO 0);
begin
if (falling_edge(clk10mhz)) then
case (memState) is
when idle =>
vramWea <= "0";
ramWea <= "0";
if (addressBus >= X"2400") then
vramAddrAWide := (addressBus - X"2400");
vramAddrA <= vramAddrAWide(12 downto 0);
elsif (addressBus >= X"2000") then
ramAddrWide := (addressBus - X"2000");
ramAddr <= ramAddrWide(9 downto 0);
else
romAddr <= addressBus(12 downto 0);
end if;
if (cpuDataBusInputMode = '1') then
memState <= read0;
elsif (cpuWr = '1') then
memState <= write0;
end if;
when read0 =>
dataBusReady <= '0';
memState <= read1;
when read1 =>
if (addressBus < X"2000") then
cpuDataIn <= romDataOut;
elsif (addressBus < X"2400") then
cpuDataIn <= ramDataOut;
else
cpuDataIn <= vramDataOutB;
end if;
dataBusReady <= '1';
memState <= idle;
when write0 =>
if (addressBus >= X"2400") then
vramDataInA <= cpuDataOut;
vramWea <= "1";
elsif (addressBus >= X"2000") then
ramDataIn <= cpuDataOut;
ramWea <= "1";
else
report "Attempt to write to ROM address!";
end if;
memState <= idle;
end case;
end if;
end process;
leds <= cpuStatus;
vsync <= vgaVsync;
videoController : video PORT MAP (
clkin25mhz => clk25mhz,
red => red,
green => green,
blue => blue,
hsync => hsync,
vsync => vgaVsync,
vramAddr => vramAddrB,
vramData => vramDataOutB,
colourOutput => '1');
allClocks : clocks PORT MAP (
clkin => clk,
clk10mhz => clk10mhz,
clk133mhz => clk133mhz,
clk133mhzinv => clk133mhzinv,
clk25mhz => clk25mhz);
videoRam : vram PORT MAP (
clka => clk10mhz,
wea => vramWea,
addra => vramAddrA,
dina => vramDataInA,
douta => vramDataOutA,
clkb => clk25mhz,
web => "0",
addrb => vramAddrB,
dinb => "00000000",
doutb => vramDataOutB);
readWriteMemory : ram PORT MAP (
clka => clk10mhz,
wea => ramWea,
addra => ramAddr,
dina => ramDataIn,
douta => ramDataOut);
invadersRom : rom PORT MAP (
clka => clk10mhz,
addra => romAddr,
douta => romDataOut);
cpu: i8080 PORT MAP(
clk => clk10mhz,
dataIn => cpuDataIn,
ready => dataBusReady,
hold => cpuHold,
int => cpuInt,
reset => reset,
addressBus => addressBus,
dataOut => cpuDataOut,
sync => cpuSync,
dataBusIn => cpuDataBusInputMode,
waitAck => cpuWaitAck,
wr => cpuWr,
hlda => cpuHlda,
inte => cpuInte,
status => cpuStatus);
END Behavioral;
|
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
port (
eop : out std_logic; -- eop.wire
counter_1 : out std_logic_vector(23 downto 0); -- counter_1.wire
colorbar : in std_logic_vector(23 downto 0) := (others => '0'); -- colorbar.wire
data : out std_logic_vector(24 downto 0); -- data.wire
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak3.wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak2.wire
data_en : out std_logic; -- data_en.wire
ctrl_en : out std_logic; -- ctrl_en.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
row : in std_logic_vector(31 downto 0) := (others => '0'); -- row.wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak1.wire
check_en : out std_logic; -- check_en.wire
sop : out std_logic; -- sop.wire
ready : in std_logic := '0' -- ready.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNEHYJMBQS is
port (
input : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEHYJMBQS;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_counter_GNKAA2ZBZG is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNKAA2ZBZG;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
check_en : out std_logic; -- wire
pixel_num : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
ready : in std_logic := 'X'; -- wire
data_en : out std_logic; -- wire
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
ctrl_en : out std_logic -- wire
);
end component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP;
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
Signed : natural := 0;
OutputMsb : integer := 8;
aWidth : natural := 8;
bWidth : natural := 8;
OutputLsb : integer := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
dataa : in std_logic_vector(aWidth-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(bWidth-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
port (
sop : out std_logic; -- wire
pixel_num : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
ctrl_en : in std_logic := 'X'; -- wire
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
colorbar : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
data : out std_logic_vector(24 downto 0); -- wire
data_en : in std_logic := 'X'; -- wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
eop : out std_logic; -- wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X' -- reset
);
end component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_cast_GN7PRGDOVA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7PRGDOVA;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
signal pipelined_adder5user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder5user_aclrGND:output -> Pipelined_Adder5:user_aclr
signal pipelined_adder5enavcc_output_wire : std_logic; -- Pipelined_Adder5enaVCC:output -> Pipelined_Adder5:ena
signal multiplier1user_aclrgnd_output_wire : std_logic; -- Multiplier1user_aclrGND:output -> Multiplier1:user_aclr
signal multiplier1enavcc_output_wire : std_logic; -- Multiplier1enaVCC:output -> Multiplier1:ena
signal ready_0_output_wire : std_logic; -- ready_0:output -> Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:ready
signal counter_q_wire : std_logic_vector(23 downto 0); -- Counter:q -> [If_Statement4:a, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:counter, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:counter, counter_1_0:input]
signal test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:ctrl_en -> [Logical_Bit_Operator1:data0, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_en, ctrl_en_0:input]
signal test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:data_en -> [Logical_Bit_Operator11:data0, Logical_Bit_Operator1:data1, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:data_en, data_en_0:input]
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Counter:cnt_ena
signal if_statement4_true_wire : std_logic; -- If_Statement4:true -> Logical_Bit_Operator11:data1
signal logical_bit_operator11_result_wire : std_logic; -- Logical_Bit_Operator11:result -> Counter:sclr
signal multiplier1_result_wire : std_logic_vector(47 downto 0); -- Multiplier1:result -> [Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:pixel_num, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:pixel_num, cast43:input]
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> Pipelined_Adder5:datab
signal pipelined_adder5_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder5:result -> If_Statement4:b
signal ctrl_pak1_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak1_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak1
signal ctrl_pak2_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak2_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak2
signal ctrl_pak3_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak3_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak3
signal colorbar_0_output_wire : std_logic_vector(23 downto 0); -- colorbar_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:colorbar
signal test_pattern_generator_main_ctrl_signal_out_0_data_wire : std_logic_vector(24 downto 0); -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:data -> data_0:input
signal test_pattern_generator_main_ctrl_signal_out_0_sop_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:sop -> sop_0:input
signal test_pattern_generator_main_ctrl_signal_out_0_eop_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:eop -> eop_0:input
signal test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:check_en -> check_en_0:input
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> cast41:input
signal cast41_output_wire : std_logic_vector(23 downto 0); -- cast41:output -> Multiplier1:dataa
signal row_0_output_wire : std_logic_vector(31 downto 0); -- row_0:output -> cast42:input
signal cast42_output_wire : std_logic_vector(23 downto 0); -- cast42:output -> Multiplier1:datab
signal cast43_output_wire : std_logic_vector(23 downto 0); -- cast43:output -> Pipelined_Adder5:dataa
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Counter:aclr, Multiplier1:aclr, Pipelined_Adder5:aclr, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:aclr, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Counter:clock, Multiplier1:clock, Pipelined_Adder5:clock, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:Clock, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:Clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
counter_1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter_q_wire, -- input.wire
output => counter_1 -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => colorbar, -- input.wire
output => colorbar_0_output_wire -- output.wire
);
pipelined_adder5 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast43_output_wire, -- dataa.wire
datab => constant4_output_wire, -- datab.wire
result => pipelined_adder5_result_wire, -- result.wire
user_aclr => pipelined_adder5user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder5enavcc_output_wire -- ena.wire
);
pipelined_adder5user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder5user_aclrgnd_output_wire -- output.wire
);
pipelined_adder5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder5enavcc_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNEHYJMBQS
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_data_wire, -- input.wire
output => data -- output.wire
);
if_statement4 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement4_true_wire, -- true.wire
a => counter_q_wire, -- a.wire
b => pipelined_adder5_result_wire -- b.wire
);
counter : component alt_dspbuilder_counter_GNKAA2ZBZG
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "false",
use_sclr => "true",
use_cout => "false",
modulus => 8388608,
use_cnt_ena => "true",
width => 24,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
cnt_ena => logical_bit_operator1_result_wire, -- cnt_ena.wire
sclr => logical_bit_operator11_result_wire, -- sclr.wire
q => counter_q_wire, -- q.wire
cout => open -- cout.wire
);
constant4 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
logical_bit_operator11 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator11_result_wire, -- result.wire
data0 => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data0.wire
data1 => if_statement4_true_wire -- data1.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_sop_wire, -- input.wire
output => sop -- output.wire
);
ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ready, -- input.wire
output => ready_0_output_wire -- output.wire
);
row_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => row, -- input.wire
output => row_0_output_wire -- output.wire
);
test_pattern_generator_main_ctrl_ctrl_top_0 : component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP
port map (
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
check_en => test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire, -- check_en.wire
pixel_num => multiplier1_result_wire, -- pixel_num.wire
ready => ready_0_output_wire, -- ready.wire
data_en => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data_en.wire
counter => counter_q_wire, -- counter.wire
ctrl_en => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire -- ctrl_en.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- input.wire
output => ctrl_en -- output.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak2, -- input.wire
output => ctrl_pak2_0_output_wire -- output.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak3, -- input.wire
output => ctrl_pak3_0_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak1, -- input.wire
output => ctrl_pak1_0_output_wire -- output.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- input.wire
output => data_en -- output.wire
);
multiplier1 : component alt_dspbuilder_multiplier_GNEIWYOKUR
generic map (
DEDICATED_MULTIPLIER_CIRCUITRY => "YES",
Signed => 0,
OutputMsb => 47,
aWidth => 24,
bWidth => 24,
OutputLsb => 0,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast41_output_wire, -- dataa.wire
datab => cast42_output_wire, -- datab.wire
result => multiplier1_result_wire, -- result.wire
user_aclr => multiplier1user_aclrgnd_output_wire, -- user_aclr.wire
ena => multiplier1enavcc_output_wire -- ena.wire
);
multiplier1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplier1user_aclrgnd_output_wire -- output.wire
);
multiplier1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplier1enavcc_output_wire -- output.wire
);
test_pattern_generator_main_ctrl_signal_out_0 : component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT
port map (
sop => test_pattern_generator_main_ctrl_signal_out_0_sop_wire, -- sop.wire
pixel_num => multiplier1_result_wire, -- pixel_num.wire
ctrl_en => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- ctrl_en.wire
counter => counter_q_wire, -- counter.wire
ctrl_pak1 => ctrl_pak1_0_output_wire, -- ctrl_pak1.wire
colorbar => colorbar_0_output_wire, -- colorbar.wire
data => test_pattern_generator_main_ctrl_signal_out_0_data_wire, -- data.wire
data_en => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data_en.wire
ctrl_pak2 => ctrl_pak2_0_output_wire, -- ctrl_pak2.wire
eop => test_pattern_generator_main_ctrl_signal_out_0_eop_wire, -- eop.wire
ctrl_pak3 => ctrl_pak3_0_output_wire, -- ctrl_pak3.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset -- .reset
);
check_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire, -- input.wire
output => check_en -- output.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_eop_wire, -- input.wire
output => eop -- output.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- data0.wire
data1 => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire -- data1.wire
);
cast41 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast41_output_wire -- output.wire
);
cast42 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast42_output_wire -- output.wire
);
cast43 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier1_result_wire, -- input.wire
output => cast43_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL
|
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
port (
eop : out std_logic; -- eop.wire
counter_1 : out std_logic_vector(23 downto 0); -- counter_1.wire
colorbar : in std_logic_vector(23 downto 0) := (others => '0'); -- colorbar.wire
data : out std_logic_vector(24 downto 0); -- data.wire
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak3.wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak2.wire
data_en : out std_logic; -- data_en.wire
ctrl_en : out std_logic; -- ctrl_en.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
row : in std_logic_vector(31 downto 0) := (others => '0'); -- row.wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak1.wire
check_en : out std_logic; -- check_en.wire
sop : out std_logic; -- sop.wire
ready : in std_logic := '0' -- ready.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNEHYJMBQS is
port (
input : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEHYJMBQS;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_counter_GNKAA2ZBZG is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNKAA2ZBZG;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
check_en : out std_logic; -- wire
pixel_num : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
ready : in std_logic := 'X'; -- wire
data_en : out std_logic; -- wire
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
ctrl_en : out std_logic -- wire
);
end component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP;
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
Signed : natural := 0;
OutputMsb : integer := 8;
aWidth : natural := 8;
bWidth : natural := 8;
OutputLsb : integer := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
dataa : in std_logic_vector(aWidth-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(bWidth-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
port (
sop : out std_logic; -- wire
pixel_num : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
ctrl_en : in std_logic := 'X'; -- wire
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
colorbar : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
data : out std_logic_vector(24 downto 0); -- wire
data_en : in std_logic := 'X'; -- wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
eop : out std_logic; -- wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X' -- reset
);
end component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_cast_GN7PRGDOVA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7PRGDOVA;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
signal pipelined_adder5user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder5user_aclrGND:output -> Pipelined_Adder5:user_aclr
signal pipelined_adder5enavcc_output_wire : std_logic; -- Pipelined_Adder5enaVCC:output -> Pipelined_Adder5:ena
signal multiplier1user_aclrgnd_output_wire : std_logic; -- Multiplier1user_aclrGND:output -> Multiplier1:user_aclr
signal multiplier1enavcc_output_wire : std_logic; -- Multiplier1enaVCC:output -> Multiplier1:ena
signal ready_0_output_wire : std_logic; -- ready_0:output -> Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:ready
signal counter_q_wire : std_logic_vector(23 downto 0); -- Counter:q -> [If_Statement4:a, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:counter, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:counter, counter_1_0:input]
signal test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:ctrl_en -> [Logical_Bit_Operator1:data0, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_en, ctrl_en_0:input]
signal test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:data_en -> [Logical_Bit_Operator11:data0, Logical_Bit_Operator1:data1, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:data_en, data_en_0:input]
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Counter:cnt_ena
signal if_statement4_true_wire : std_logic; -- If_Statement4:true -> Logical_Bit_Operator11:data1
signal logical_bit_operator11_result_wire : std_logic; -- Logical_Bit_Operator11:result -> Counter:sclr
signal multiplier1_result_wire : std_logic_vector(47 downto 0); -- Multiplier1:result -> [Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:pixel_num, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:pixel_num, cast43:input]
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> Pipelined_Adder5:datab
signal pipelined_adder5_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder5:result -> If_Statement4:b
signal ctrl_pak1_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak1_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak1
signal ctrl_pak2_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak2_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak2
signal ctrl_pak3_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak3_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak3
signal colorbar_0_output_wire : std_logic_vector(23 downto 0); -- colorbar_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:colorbar
signal test_pattern_generator_main_ctrl_signal_out_0_data_wire : std_logic_vector(24 downto 0); -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:data -> data_0:input
signal test_pattern_generator_main_ctrl_signal_out_0_sop_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:sop -> sop_0:input
signal test_pattern_generator_main_ctrl_signal_out_0_eop_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:eop -> eop_0:input
signal test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:check_en -> check_en_0:input
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> cast41:input
signal cast41_output_wire : std_logic_vector(23 downto 0); -- cast41:output -> Multiplier1:dataa
signal row_0_output_wire : std_logic_vector(31 downto 0); -- row_0:output -> cast42:input
signal cast42_output_wire : std_logic_vector(23 downto 0); -- cast42:output -> Multiplier1:datab
signal cast43_output_wire : std_logic_vector(23 downto 0); -- cast43:output -> Pipelined_Adder5:dataa
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Counter:aclr, Multiplier1:aclr, Pipelined_Adder5:aclr, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:aclr, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Counter:clock, Multiplier1:clock, Pipelined_Adder5:clock, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:Clock, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:Clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
counter_1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter_q_wire, -- input.wire
output => counter_1 -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => colorbar, -- input.wire
output => colorbar_0_output_wire -- output.wire
);
pipelined_adder5 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast43_output_wire, -- dataa.wire
datab => constant4_output_wire, -- datab.wire
result => pipelined_adder5_result_wire, -- result.wire
user_aclr => pipelined_adder5user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder5enavcc_output_wire -- ena.wire
);
pipelined_adder5user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder5user_aclrgnd_output_wire -- output.wire
);
pipelined_adder5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder5enavcc_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNEHYJMBQS
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_data_wire, -- input.wire
output => data -- output.wire
);
if_statement4 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement4_true_wire, -- true.wire
a => counter_q_wire, -- a.wire
b => pipelined_adder5_result_wire -- b.wire
);
counter : component alt_dspbuilder_counter_GNKAA2ZBZG
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "false",
use_sclr => "true",
use_cout => "false",
modulus => 8388608,
use_cnt_ena => "true",
width => 24,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
cnt_ena => logical_bit_operator1_result_wire, -- cnt_ena.wire
sclr => logical_bit_operator11_result_wire, -- sclr.wire
q => counter_q_wire, -- q.wire
cout => open -- cout.wire
);
constant4 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
logical_bit_operator11 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator11_result_wire, -- result.wire
data0 => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data0.wire
data1 => if_statement4_true_wire -- data1.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_sop_wire, -- input.wire
output => sop -- output.wire
);
ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ready, -- input.wire
output => ready_0_output_wire -- output.wire
);
row_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => row, -- input.wire
output => row_0_output_wire -- output.wire
);
test_pattern_generator_main_ctrl_ctrl_top_0 : component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP
port map (
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
check_en => test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire, -- check_en.wire
pixel_num => multiplier1_result_wire, -- pixel_num.wire
ready => ready_0_output_wire, -- ready.wire
data_en => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data_en.wire
counter => counter_q_wire, -- counter.wire
ctrl_en => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire -- ctrl_en.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- input.wire
output => ctrl_en -- output.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak2, -- input.wire
output => ctrl_pak2_0_output_wire -- output.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak3, -- input.wire
output => ctrl_pak3_0_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak1, -- input.wire
output => ctrl_pak1_0_output_wire -- output.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- input.wire
output => data_en -- output.wire
);
multiplier1 : component alt_dspbuilder_multiplier_GNEIWYOKUR
generic map (
DEDICATED_MULTIPLIER_CIRCUITRY => "YES",
Signed => 0,
OutputMsb => 47,
aWidth => 24,
bWidth => 24,
OutputLsb => 0,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast41_output_wire, -- dataa.wire
datab => cast42_output_wire, -- datab.wire
result => multiplier1_result_wire, -- result.wire
user_aclr => multiplier1user_aclrgnd_output_wire, -- user_aclr.wire
ena => multiplier1enavcc_output_wire -- ena.wire
);
multiplier1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplier1user_aclrgnd_output_wire -- output.wire
);
multiplier1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplier1enavcc_output_wire -- output.wire
);
test_pattern_generator_main_ctrl_signal_out_0 : component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT
port map (
sop => test_pattern_generator_main_ctrl_signal_out_0_sop_wire, -- sop.wire
pixel_num => multiplier1_result_wire, -- pixel_num.wire
ctrl_en => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- ctrl_en.wire
counter => counter_q_wire, -- counter.wire
ctrl_pak1 => ctrl_pak1_0_output_wire, -- ctrl_pak1.wire
colorbar => colorbar_0_output_wire, -- colorbar.wire
data => test_pattern_generator_main_ctrl_signal_out_0_data_wire, -- data.wire
data_en => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data_en.wire
ctrl_pak2 => ctrl_pak2_0_output_wire, -- ctrl_pak2.wire
eop => test_pattern_generator_main_ctrl_signal_out_0_eop_wire, -- eop.wire
ctrl_pak3 => ctrl_pak3_0_output_wire, -- ctrl_pak3.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset -- .reset
);
check_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire, -- input.wire
output => check_en -- output.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_eop_wire, -- input.wire
output => eop -- output.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- data0.wire
data1 => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire -- data1.wire
);
cast41 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast41_output_wire -- output.wire
);
cast42 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast42_output_wire -- output.wire
);
cast43 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier1_result_wire, -- input.wire
output => cast43_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL
|
--------------------------------------------------------------------------------
-- Title : Tx Module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_module.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 13.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- combines the modules tx_put_data, tx_compl_timeout and tx_ctrl
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- * tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tx_module is
generic(
DEVICE_FAMILY : string := "unused";
TX_HEADER_FIFO_DEPTH : natural := 32; -- valid values are: 2^(TX_HEADER_LPM_WIDTHU-1) < TX_HEADER_FIFO_DEPTH <= 2^(TX_HEADER_LPM_WIDTHU)
TX_HEADER_LPM_WIDTHU : natural := 5;
TX_DATA_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(TX_DATA_LPM_WIDTHU-1) < TX_DATA_FIFO_DEPTH <= 2^(TX_DATA_LPM_WIDTHU)
TX_DATA_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
rst : in std_logic;
wb_clk : in std_logic;
wb_rst : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
-- IP Core
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
tx_st_data0 : out std_logic_vector(63 downto 0);
pme_to_cr : out std_logic;
-- Rx Module
rx_tag_nbr : in std_logic_vector(7 downto 0);
rx_tag_rcvd : in std_logic;
-- Wishbone Master
tx_fifo_c_data_clr : in std_logic;
tx_fifo_c_head_clr : in std_logic;
tx_fifo_c_head_enable : in std_logic;
tx_fifo_c_data_enable : in std_logic;
tx_fifo_c_head_in : in std_logic_vector(31 downto 0);
tx_fifo_c_data_in : in std_logic_vector(31 downto 0);
tx_fifo_c_head_full : out std_logic;
tx_fifo_c_data_full : out std_logic;
tx_fifo_c_data_usedw : out std_logic_vector(9 downto 0);
-- Wishbone Slave
tx_fifo_wr_head_clr : in std_logic;
tx_fifo_wr_head_enable : in std_logic;
tx_fifo_wr_head_in : in std_logic_vector(31 downto 0);
tx_fifo_w_data_clr : in std_logic;
tx_fifo_w_data_enable : in std_logic;
tx_fifo_w_data_in : in std_logic_vector(31 downto 0);
tx_fifo_wr_head_full : out std_logic;
tx_fifo_w_data_full : out std_logic;
tx_fifo_w_data_usedw : out std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : out std_logic_vector(4 downto 0);
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
max_payload : in std_logic_vector(2 downto 0);
-- error
tx_compl_abort : out std_logic;
tx_timeout : out std_logic
);
end entity tx_module;
-- ****************************************************************************
architecture tx_module_arch of tx_module is
-- internal signals -----------------------------------------------------------
signal aligned_int : std_logic;
signal data_len_int : std_logic_vector(9 downto 0);
signal wr_rd_int : std_logic; -- 0: write, 1: read
signal posted_int : std_logic; -- 0: non-posted, 1: posted
signal byte_count_int : std_logic_vector(11 downto 0);
signal orig_addr_int : std_logic_vector(31 downto 0);
signal tx_tag_nbr_int : std_logic_vector(7 downto 0);
signal get_header_int : std_logic;
signal make_header_int : std_logic;
signal data_enable_int : std_logic;
signal start_int : std_logic;
signal start_tag_nbr_int : std_logic_vector(4 downto 0);
signal c_wrrd_int : std_logic;
signal completer_id_int : std_logic_vector(15 downto 0);
signal own_id_int : std_logic_vector(15 downto 0);
signal get_next_header_int : std_logic;
signal abort_compl_int : std_logic;
signal send_len_int : std_logic_vector(9 downto 0);
signal send_addr_int : std_logic_vector(31 downto 0);
signal payload_loop_int : std_logic;
signal first_last_full_int : std_logic_vector(1 downto 0);
signal io_write_int : std_logic;
-- FIFO:
signal tx_fifo_c_head_empty_int : std_logic;
signal tx_fifo_c_head_enable_int : std_logic;
signal tx_fifo_c_head_out_int : std_logic_vector(63 downto 0);
signal tx_fifo_c_data_empty_int : std_logic;
signal tx_fifo_c_data_enable_int : std_logic;
signal tx_fifo_c_data_out_int : std_logic_vector(63 downto 0);
signal tx_fifo_wr_head_empty_int : std_logic;
signal tx_fifo_wr_head_enable_int : std_logic;
signal tx_fifo_wr_head_out_int : std_logic_vector(63 downto 0);
signal tx_fifo_w_data_enable_int : std_logic;
signal tx_fifo_w_data_empty_int : std_logic;
signal tx_fifo_w_data_out_int : std_logic_vector(63 downto 0);
signal tx_wrusedw_c : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_w : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_c_out : std_logic_vector (9 downto 0);
signal tx_wrusedw_w_out : std_logic_vector (9 downto 0);
-------------------------------------------------------------------------------
-- components -----------------------------------------------------------------
component tx_ctrl
port(
clk : in std_logic;
rst : in std_logic;
-- IP core
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
pme_to_cr : out std_logic;
-- FIFO
tx_c_head_empty : in std_logic;
tx_wr_head_empty : in std_logic;
tx_c_data_empty : in std_logic;
tx_wr_data_empty : in std_logic;
tx_c_head_enable : out std_logic;
tx_wr_head_enable : out std_logic;
tx_c_data_enable : out std_logic;
tx_wr_data_enable : out std_logic;
-- tx_put_data
aligned : in std_logic;
data_len : in std_logic_vector(9 downto 0);
wr_rd : in std_logic; -- 0: write, 1: read
posted : in std_logic; -- 0: non-posted, 1: posted
byte_count : in std_logic_vector(11 downto 0);
io_write : in std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : in std_logic_vector(31 downto 0);
tx_tag_nbr : out std_logic_vector(7 downto 0);
get_header : out std_logic;
get_next_header : out std_logic;
make_header : out std_logic;
data_enable : out std_logic;
c_wrrd : out std_logic;
completer_id : out std_logic_vector(15 downto 0);
own_id : out std_logic_vector(15 downto 0);
abort_compl : out std_logic;
send_len : out std_logic_vector(9 downto 0);
send_addr : out std_logic_vector(31 downto 0);
payload_loop : out std_logic;
first_last_full : out std_logic_vector(1 downto 0);
-- tx_compl_timeout
start : out std_logic;
start_tag_nbr : out std_logic_vector(4 downto 0);
-- error
compl_abort : out std_logic;
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
max_payload : in std_logic_vector(2 downto 0)
);
end component;
component tx_put_data
port(
clk : in std_logic;
rst : in std_logic;
-- IP Core
tx_st_data0 : out std_logic_vector(63 downto 0);
-- FIFO
tx_c_head_out : in std_logic_vector(63 downto 0);
tx_c_data_out : in std_logic_vector(63 downto 0);
tx_wr_head_out : in std_logic_vector(63 downto 0);
tx_wr_data_out : in std_logic_vector(63 downto 0);
-- tx_ctrl
data_enable : in std_logic;
tag_nbr : in std_logic_vector(7 downto 0);
req_id : in std_logic_vector(15 downto 0);
completer_id : in std_logic_vector(15 downto 0);
c_wrrd : in std_logic; -- 0: completion, 1: write/read
get_header : in std_logic;
get_next_header : in std_logic;
make_header : in std_logic;
abort_compl : in std_logic;
send_len : in std_logic_vector(9 downto 0); -- length of actual packet, stored to header
send_addr : in std_logic_vector(31 downto 0); -- address of actual packet, stored to header
payload_loop : in std_logic; -- =0: no loop, =1: loop -> keep most header info
first_last_full : in std_logic_vector(1 downto 0);
data_length : out std_logic_vector(9 downto 0);
aligned : out std_logic;
wr_rd : out std_logic; -- 0: write, 1: read
posted : out std_logic; -- 0: non-posted, 1: posted
byte_count : out std_logic_vector(11 downto 0);
io_write : out std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : out std_logic_vector(31 downto 0)
);
end component;
component tx_compl_timeout
generic(
CLOCK_TIME : time := 8 ns; -- clock cycle time
TIMEOUT_TIME : integer := 25
);
port(
clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
-- tx_ctrl
tag_nbr_in : in std_logic_vector(4 downto 0);
start : in std_logic;
-- RxModule
rx_tag_nbr : in std_logic_vector(7 downto 0);
rx_tag_rcvd : in std_logic;
-- error
timeout : out std_logic
);
end component;
component generic_dcfifo_mixedw
generic (
g_device_family : string := "Cyclone IV GX";
g_fifo_depth : natural := 32;
g_data_width : natural := 32;
g_data_widthu : natural := 5;
g_q_width : natural := 64;
g_q_widthu : natural := 4;
g_showahead : string := "OFF");
port (
aclr : in std_logic := '0';
data : in std_logic_vector (g_data_width-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (g_q_width-1 downto 0);
rdempty : out std_logic ;
wrfull : out std_logic ;
wrusedw : out std_logic_vector (g_data_widthu-1 downto 0));
end component;
-------------------------------------------------------------------------------
begin
-- instanciate components -----------------------------------------------------
tx_ctrl_comp : tx_ctrl
port map(
clk => clk,
rst => rst,
-- IP core
tx_st_ready0 => tx_st_ready0,
tx_fifo_full0 => tx_fifo_full0,
tx_fifo_empty0 => tx_fifo_empty0,
tx_fifo_rdptr0 => tx_fifo_rdptr0,
tx_fifo_wrptr0 => tx_fifo_wrptr0,
pme_to_sr => pme_to_sr,
tx_st_err0 => tx_st_err0,
tx_st_valid0 => tx_st_valid0,
tx_st_sop0 => tx_st_sop0,
tx_st_eop0 => tx_st_eop0,
pme_to_cr => pme_to_cr,
-- FIFO
tx_c_head_empty => tx_fifo_c_head_empty_int,
tx_wr_head_empty => tx_fifo_wr_head_empty_int,
tx_c_data_empty => tx_fifo_c_data_empty_int,
tx_wr_data_empty => tx_fifo_w_data_empty_int,
tx_c_head_enable => tx_fifo_c_head_enable_int,
tx_wr_head_enable => tx_fifo_wr_head_enable_int,
tx_c_data_enable => tx_fifo_c_data_enable_int,
tx_wr_data_enable => tx_fifo_w_data_enable_int,
-- tx_put_data
aligned => aligned_int,
data_len => data_len_int,
wr_rd => wr_rd_int, -- 0: write, 1: read
posted => posted_int, -- 0: non-posted, 1: posted
byte_count => byte_count_int,
io_write => io_write_int,
orig_addr => orig_addr_int,
tx_tag_nbr => tx_tag_nbr_int,
get_header => get_header_int,
get_next_header => get_next_header_int,
make_header => make_header_int,
data_enable => data_enable_int,
c_wrrd => c_wrrd_int,
completer_id => completer_id_int,
own_id => own_id_int,
abort_compl => abort_compl_int,
send_len => send_len_int,
send_addr => send_addr_int,
payload_loop => payload_loop_int,
first_last_full => first_last_full_int,
-- tx_compl_timeout
start => start_int,
start_tag_nbr => start_tag_nbr_int,
-- error
compl_abort => tx_compl_abort,
-- init
bus_dev_func => bus_dev_func,
max_payload => max_payload
);
tx_put_data_comp : tx_put_data
port map(
clk => clk,
rst => rst,
-- IP Core
tx_st_data0 => tx_st_data0,
-- FIFO
tx_c_head_out => tx_fifo_c_head_out_int,
tx_c_data_out => tx_fifo_c_data_out_int,
tx_wr_head_out => tx_fifo_wr_head_out_int,
tx_wr_data_out => tx_fifo_w_data_out_int,
-- tx_ctrl
data_enable => data_enable_int,
tag_nbr => tx_tag_nbr_int,
req_id => own_id_int,
completer_id => completer_id_int,
c_wrrd => c_wrrd_int,
get_header => get_header_int,
get_next_header => get_next_header_int,
make_header => make_header_int,
abort_compl => abort_compl_int,
send_len => send_len_int,
send_addr => send_addr_int,
payload_loop => payload_loop_int,
first_last_full => first_last_full_int,
data_length => data_len_int,
aligned => aligned_int,
wr_rd => wr_rd_int,
posted => posted_int,
byte_count => byte_count_int,
io_write => io_write_int,
orig_addr => orig_addr_int
);
tx_compl_timeout_comp : tx_compl_timeout
generic map(
CLOCK_TIME => 8 ns, -- clock cycle time
TIMEOUT_TIME => 25
)
port map(
clk => clk,
clk_500 => clk_500,
rst => rst,
-- tx_ctrl
tag_nbr_in => start_tag_nbr_int,
start => start_int,
-- RxModule
rx_tag_nbr => rx_tag_nbr,
rx_tag_rcvd => rx_tag_rcvd,
-- error
timeout => tx_timeout
);
------------------------------------------------
tx_c_header_fifo : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_HEADER_LPM_WIDTHU,
g_q_width => 64,
g_q_widthu => TX_HEADER_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_c_head_clr,
data => tx_fifo_c_head_in,
rdclk => clk,
rdreq => tx_fifo_c_head_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_c_head_enable,
q => tx_fifo_c_head_out_int,
rdempty => tx_fifo_c_head_empty_int,
wrfull => tx_fifo_c_head_full,
wrusedw => open);
tx_wr_header_fifo : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_HEADER_LPM_WIDTHU,
g_q_width => 64,
g_q_widthu => TX_HEADER_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_wr_head_clr,
data => tx_fifo_wr_head_in,
rdclk => clk,
rdreq => tx_fifo_wr_head_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_wr_head_enable,
q => tx_fifo_wr_head_out_int,
rdempty => tx_fifo_wr_head_empty_int,
wrfull => tx_fifo_wr_head_full,
wrusedw => tx_fifo_wr_head_usedw);
------------------------------------------------
tx_c_data_fifo : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_DATA_LPM_WIDTHU,
g_q_width => 64,
g_q_widthu => TX_DATA_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_c_data_clr,
data => tx_fifo_c_data_in,
rdclk => clk,
rdreq => tx_fifo_c_data_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_c_data_enable,
q => tx_fifo_c_data_out_int,
rdempty => tx_fifo_c_data_empty_int,
wrfull => tx_fifo_c_data_full,
wrusedw => tx_wrusedw_c);
tx_w_data_fifo : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_DATA_LPM_WIDTHU,
g_q_width => 64,
g_q_widthu => TX_DATA_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_w_data_clr,
data => tx_fifo_w_data_in,
rdclk => clk,
rdreq => tx_fifo_w_data_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_w_data_enable,
q => tx_fifo_w_data_out_int,
rdempty => tx_fifo_w_data_empty_int,
wrfull => tx_fifo_w_data_full,
wrusedw => tx_wrusedw_w);
-------------------------------------------------------------------------------
tx_wrusedw_c_out <= conv_std_logic_vector(conv_integer(tx_wrusedw_c),10);
tx_wrusedw_w_out <= conv_std_logic_vector(conv_integer(tx_wrusedw_w),10);
tx_fifo_c_data_usedw <= tx_wrusedw_c_out;
tx_fifo_w_data_usedw <= tx_wrusedw_w_out;
-------------------------------------------------------------------------------
end architecture tx_module_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:52:32 11/22/2015
-- Design Name:
-- Module Name: U4_1-Freq_Div - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity U4_1-Freq_Div is
end U4_1-Freq_Div;
architecture Behavioral of U4_1-Freq_Div is
begin
end Behavioral;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo3.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo3 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo3.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo3.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
-- als 01/19/04 added FIFO_AlmostEmpty output from the not of next_data_exists
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.vcomponents.all;
entity srl_fifo3 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
FIFO_AlmostEmpty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo3;
architecture imp of srl_fifo3 is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
FIFO_AlmostEmpty <= not(next_Data_Exists);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo3.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo3 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo3.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo3.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
-- als 01/19/04 added FIFO_AlmostEmpty output from the not of next_data_exists
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.vcomponents.all;
entity srl_fifo3 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
FIFO_AlmostEmpty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo3;
architecture imp of srl_fifo3 is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
FIFO_AlmostEmpty <= not(next_Data_Exists);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test while loops in VHDL.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity vhdl_while is
port(
start: in std_logic;
output: out integer
);
end vhdl_while;
architecture test of vhdl_while is
begin
process(start)
variable a : integer := 0;
begin
if(rising_edge(start)) then
while (a < 10) loop
a := a + 1;
end loop;
output <= a;
end if;
end process;
end test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test while loops in VHDL.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity vhdl_while is
port(
start: in std_logic;
output: out integer
);
end vhdl_while;
architecture test of vhdl_while is
begin
process(start)
variable a : integer := 0;
begin
if(rising_edge(start)) then
while (a < 10) loop
a := a + 1;
end loop;
output <= a;
end if;
end process;
end test;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc722.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p03n01i00722ent IS
generic (( constant i : integer ); -- extra parenthesis
END c01s01b01x00p03n01i00722ent;
ARCHITECTURE c01s01b01x00p03n01i00722arch OF c01s01b01x00p03n01i00722ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p03n01i00722 - Unbalanced parenthesis in generic clause."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p03n01i00722arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc722.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p03n01i00722ent IS
generic (( constant i : integer ); -- extra parenthesis
END c01s01b01x00p03n01i00722ent;
ARCHITECTURE c01s01b01x00p03n01i00722arch OF c01s01b01x00p03n01i00722ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p03n01i00722 - Unbalanced parenthesis in generic clause."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p03n01i00722arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc722.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p03n01i00722ent IS
generic (( constant i : integer ); -- extra parenthesis
END c01s01b01x00p03n01i00722ent;
ARCHITECTURE c01s01b01x00p03n01i00722arch OF c01s01b01x00p03n01i00722ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p03n01i00722 - Unbalanced parenthesis in generic clause."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p03n01i00722arch;
|
-- Automatically generated: write_netlist -wrapapp -vhdl -architecture reconflogic-wrapmax6682mean-a.vhd
architecture WrapMAX6682Mean of MyReconfigLogic is
component CfgIntf
generic (
-- Number of configuration chains
NumCfgs : integer := 3;
BaseAddr : integer := 16#0180#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgClk_o : out std_logic_vector(NumCfgs-1 downto 0);
CfgMode_o : out std_logic;
CfgShift_o : out std_logic_vector(NumCfgs-1 downto 0);
CfgDataOut_o : out std_logic;
CfgDataIn_i : in std_logic_vector(NumCfgs-1 downto 0)
);
end component;
component MAX6682Mean
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
MAX6682CS_n_o : out std_logic;
SPI_Data_i : in std_logic_vector(7 downto 0);
SPI_Write_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_Data_o : out std_logic_vector(7 downto 0);
SPI_FIFOFull_i : in std_logic;
SPI_FIFOEmpty_i : in std_logic;
SPI_Transmission_i : in std_logic;
PauseCounterPreset_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
SPI_CPOL_o : out std_logic;
SPI_CPHA_o : out std_logic;
SPI_LSBFE_o : out std_logic
);
end component;
component ParamIntf
generic (
WrAddrWidth : integer range 1 to 15 := 4;
RdAddrWidth : integer range 1 to 15 := 4;
BaseAddr : integer := 16#0180#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
-- Param Out
ParamWrAddr_o : out std_logic_vector(WrAddrWidth-1 downto 0);
ParamWrData_o : out std_logic_vector(15 downto 0);
ParamWr_o : out std_logic;
-- Param In
ParamRdAddr_o : out std_logic_vector(RdAddrWidth-1 downto 0);
ParamRdData_i : in std_logic_vector(15 downto 0)
);
end component;
component ParamOutReg
generic (
Width : integer := 16
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
ParamWrData_i : in std_logic_vector(Width-1 downto 0);
Param_o : out std_logic_vector(Width-1 downto 0)
);
end component;
signal PauseCounterPreset_s : std_logic_vector(15 downto 0);
signal PeriodCounterPresetH_s : std_logic_vector(15 downto 0);
signal PeriodCounterPresetL_s : std_logic_vector(15 downto 0);
signal SensorValue_s : std_logic_vector(15 downto 0);
signal Threshold_s : std_logic_vector(15 downto 0);
signal CfgClk_s : std_logic_vector(0 downto 0);
signal CfgMode_s : std_logic;
signal CfgShift_s : std_logic_vector(0 downto 0);
signal CfgDataOut_s : std_logic;
signal CfgDataIn_s : std_logic_vector(0 downto 0);
signal ParamWrAddr_s : std_logic_vector(2 downto 0);
signal ParamWrData_s : std_logic_vector(15 downto 0);
signal ParamWr_s : std_logic;
signal ParamRdAddr_s : std_logic_vector(0 downto 0);
signal ParamRdData_s : std_logic_vector(15 downto 0);
type Params_t is array(0 to 1) of std_logic_vector(15 downto 0);
signal Params_s : Params_t;
signal I2C_ErrAckParam_s : std_logic_vector(0 downto 0);
signal ParamI2C_Divider800Enable_s : std_logic;
signal ParamI2C_ErrAckParamEnable_s : std_logic;
signal ParamPauseCounterPresetEnable_s : std_logic;
signal ParamPeriodCounterPresetHEnable_s : std_logic;
signal ParamPeriodCounterPresetLEnable_s : std_logic;
signal ParamThresholdEnable_s : std_logic;
begin
-- Configuration Interface
CfgIntf_0: CfgIntf
generic map (
BaseAddr => 16#0180#,
NumCfgs => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
PerAddr_i => PerAddr_i,
PerDIn_i => PerDIn_i,
PerDOut_o => CfgIntfDOut_o,
PerWr_i => PerWr_i,
PerEn_i => PerEn_i,
CfgClk_o => CfgClk_s,
CfgMode_o => CfgMode_s,
CfgShift_o => CfgShift_s,
CfgDataOut_o => CfgDataOut_s,
CfgDataIn_i => CfgDataIn_s
);
-- Parameterization Interface: 6 write addresses, 2 read addresses
ParamIntf_0: ParamIntf
generic map (
BaseAddr => 16#0188#,
WrAddrWidth => 3,
RdAddrWidth => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
PerAddr_i => PerAddr_i,
PerDIn_i => PerDIn_i,
PerDOut_o => ParamIntfDOut_o,
PerWr_i => PerWr_i,
PerEn_i => PerEn_i,
ParamWrAddr_o => ParamWrAddr_s,
ParamWrData_o => ParamWrData_s,
ParamWr_o => ParamWr_s,
ParamRdAddr_o => ParamRdAddr_s,
ParamRdData_i => ParamRdData_s
);
MAX6682Mean_0: MAX6682Mean
port map (
MAX6682CS_n_o => Outputs_o(0),
CpuIntr_o => ReconfModuleIRQs_o(0),
SPI_Data_o => SPI_DataIn_o,
SPI_Data_i => SPI_DataOut_i,
SPI_FIFOEmpty_i => SPI_FIFOEmpty_i,
SPI_FIFOFull_i => SPI_FIFOFull_i,
SPI_ReadNext_o => SPI_ReadNext_o,
SPI_Transmission_i => SPI_Transmission_i,
SPI_Write_o => SPI_Write_o,
Enable_i => ReconfModuleIn_i(0),
Clk_i => Clk_i,
Reset_n_i => Reset_n_i,
PauseCounterPreset_i => PauseCounterPreset_s,
PeriodCounterPresetH_i => PeriodCounterPresetH_s,
PeriodCounterPresetL_i => PeriodCounterPresetL_s,
SensorValue_o => SensorValue_s,
Threshold_i => Threshold_s
);
AdcDoConvert_o <= '0';
I2C_DataIn_o <= "00000000";
I2C_F100_400_n_o <= '0';
I2C_FIFOReadNext_o <= '0';
I2C_FIFOWrite_o <= '0';
I2C_ReadCount_o <= "0000";
I2C_ReceiveSend_n_o <= '0';
I2C_StartProcess_o <= '0';
Outputs_o(1) <= '0';
Outputs_o(2) <= '0';
Outputs_o(3) <= '0';
Outputs_o(4) <= '0';
Outputs_o(5) <= '0';
Outputs_o(6) <= '0';
Outputs_o(7) <= '0';
ReconfModuleIRQs_o(1) <= '0';
ReconfModuleIRQs_o(2) <= '0';
ReconfModuleIRQs_o(3) <= '0';
ReconfModuleIRQs_o(4) <= '0';
SPI_CPHA_o <= '0';
SPI_CPOL_o <= '0';
SPI_LSBFE_o <= '0';
SPI_SPPR_SPR_o <= "00000000";
ReconfModuleOut_o(0) <= '0';
ReconfModuleOut_o(1) <= '0';
ReconfModuleOut_o(2) <= '0';
ReconfModuleOut_o(3) <= '0';
ReconfModuleOut_o(4) <= '0';
ReconfModuleOut_o(5) <= '0';
ReconfModuleOut_o(6) <= '0';
ReconfModuleOut_o(7) <= '0';
-- just a fixed value for the config interface
CfgDataIn_s <= "0";
-- Param read address decoder
-- Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
-- hope that the synthesis optimizes the MUX
-- Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
-- 0 to n.", even during param write cycles, because ParamRdAddr has the
-- source as ParamWrAddr. Use the parameter "-noindexcheck" during
-- compilation ("vcom"). Simulation works fine then, but ModelSim generates
-- numerous "INTERNAL ERROR"s to stdout, which seem harmless.
ParamRdData_s <= Params_s(to_integer(unsigned(ParamRdAddr_s)));
ParamOutReg_I2C_Divider800: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => I2C_Divider800_o,
Enable_i => ParamI2C_Divider800Enable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_I2C_ErrAckParam: ParamOutReg
generic map (
Width => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => I2C_ErrAckParam_s,
Enable_i => ParamI2C_ErrAckParamEnable_s,
ParamWrData_i => ParamWrData_s(0 downto 0)
);
ParamOutReg_PauseCounterPreset: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PauseCounterPreset_s,
Enable_i => ParamPauseCounterPresetEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_PeriodCounterPresetH: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PeriodCounterPresetH_s,
Enable_i => ParamPeriodCounterPresetHEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_PeriodCounterPresetL: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PeriodCounterPresetL_s,
Enable_i => ParamPeriodCounterPresetLEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_Threshold: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => Threshold_s,
Enable_i => ParamThresholdEnable_s,
ParamWrData_i => ParamWrData_s
);
I2C_ErrAckParam_o <= I2C_ErrAckParam_s(0);
-- Address $00
Params_s(0) <= "00000000" & I2C_Errors_i;
-- Address $01
Params_s(1) <= SensorValue_s;
-- Address $00
ParamI2C_Divider800Enable_s <= ParamWr_s when ParamWrAddr_s = "000" else
'0';
-- Address $01
ParamI2C_ErrAckParamEnable_s <= ParamWr_s when ParamWrAddr_s = "001" else
'0';
-- Address $02
ParamPauseCounterPresetEnable_s <= ParamWr_s when ParamWrAddr_s = "010" else
'0';
-- Address $03
ParamPeriodCounterPresetHEnable_s <= ParamWr_s when ParamWrAddr_s = "011" else
'0';
-- Address $04
ParamPeriodCounterPresetLEnable_s <= ParamWr_s when ParamWrAddr_s = "100" else
'0';
-- Address $05
ParamThresholdEnable_s <= ParamWr_s when ParamWrAddr_s = "101" else
'0';
end WrapMAX6682Mean;
|
library verilog;
use verilog.vl_types.all;
entity execute_port3 is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iRESET_SYNC : in vl_logic;
iFREE_EX : in vl_logic;
iFREE_SYSREG_NEW_SPR_VALID: in vl_logic;
iFREE_SYSREG_NEW_SPR: in vl_logic_vector(31 downto 0);
iSYSREG_TIDR : in vl_logic_vector(31 downto 0);
iSYSREG_PSR : in vl_logic_vector(31 downto 0);
iSYSREG_PDTR : in vl_logic_vector(31 downto 0);
oSYSREG_SPR : out vl_logic_vector(31 downto 0);
oDATAIO_REQ : out vl_logic;
iDATAIO_BUSY : in vl_logic;
oDATAIO_ORDER : out vl_logic_vector(1 downto 0);
oDATAIO_MASK : out vl_logic_vector(3 downto 0);
oDATAIO_RW : out vl_logic;
oDATAIO_TID : out vl_logic_vector(13 downto 0);
oDATAIO_MMUMOD : out vl_logic_vector(1 downto 0);
oDATAIO_PDT : out vl_logic_vector(31 downto 0);
oDATAIO_ADDR : out vl_logic_vector(31 downto 0);
oDATAIO_DATA : out vl_logic_vector(31 downto 0);
iDATAIO_REQ : in vl_logic;
iDATAIO_DATA : in vl_logic_vector(31 downto 0);
iPREVIOUS_EX_ALU3_VALID: in vl_logic;
iPREVIOUS_EX_ALU3_DESTINATION_SYSREG: in vl_logic;
iPREVIOUS_EX_ALU3_COMMIT_TAG: in vl_logic_vector(5 downto 0);
iPREVIOUS_EX_ALU3_CMD: in vl_logic_vector(4 downto 0);
iPREVIOUS_EX_ALU3_SOURCE0: in vl_logic_vector(31 downto 0);
iPREVIOUS_EX_ALU3_SOURCE1: in vl_logic_vector(31 downto 0);
iPREVIOUS_EX_ALU3_ADV_ACTIVE: in vl_logic;
iPREVIOUS_EX_ALU3_ADV_DATA: in vl_logic_vector(5 downto 0);
iPREVIOUS_EX_ALU3_LOGIC_DEST: in vl_logic_vector(4 downto 0);
iPREVIOUS_EX_ALU3_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iPREVIOUS_EX_ALU3_PC: in vl_logic_vector(31 downto 0);
iPREVIOUS_EX_ALU3_SYS_LDST: in vl_logic;
iPREVIOUS_EX_ALU3_LDST: in vl_logic;
oPREVIOUS_EX_ALU3_LOCK: out vl_logic;
oSCHE1_ALU3_VALID: out vl_logic;
oSCHE1_ALU3_COMMIT_TAG: out vl_logic_vector(5 downto 0);
oSCHE2_ALU3_VALID: out vl_logic;
oSCHE2_ALU3_COMMIT_TAG: out vl_logic_vector(5 downto 0);
oSCHE2_ALU3_LOGIC_DEST: out vl_logic_vector(4 downto 0);
oSCHE2_ALU3_DESTINATION_REGNAME: out vl_logic_vector(5 downto 0);
oSCHE2_ALU3_DESTINATION_SYSREG: out vl_logic;
oSCHE2_ALU3_WRITEBACK: out vl_logic;
oSCHE2_ALU3_DATA: out vl_logic_vector(31 downto 0)
);
end execute_port3;
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_example_design.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the VHDL example design for the Tri-Mode
-- Ethernet MAC core. It is intended that this example design
-- can be quickly adapted and downloaded onto an FPGA to provide
-- a real hardware test environment.
--
-- This level:
--
-- * Instantiates the FIFO Block wrapper, containing the
-- block level wrapper and an RX and TX FIFO with an
-- AXI-S interface;
--
-- * Instantiates a simple AXI-S example design,
-- providing an address swap and a simple
-- loopback function;
--
-- * Instantiates transmitter clocking circuitry
-- -the User side of the FIFOs are clocked at gtx_clk
-- at all times
--
-- * Instantiates a state machine which drives the AXI Lite
-- interface to bring the TEMAC up in the correct state
--
-- * Serializes the Statistics vectors to prevent logic being
-- optimized out
--
-- * Ties unused inputs off to reduce the number of IO
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Tri-Mode Ethernet MAC User Gude for further information.
--
--
-- --------------------------------------------------
-- | EXAMPLE DESIGN WRAPPER |
-- | |
-- | |
-- | ------------------- ------------------- |
-- | | | | | |
-- | | Clocking | | Resets | |
-- | | | | | |
-- | ------------------- ------------------- |
-- | -------------------------------------|
-- | |FIFO BLOCK WRAPPER |
-- | | |
-- | | |
-- | | ----------------------|
-- | | | SUPPORT LEVEL |
-- | -------- | | |
-- | | | | | |
-- | | AXI |->|------------->| |
-- | | LITE | | | |
-- | | SM | | | |
-- | | |<-|<-------------| |
-- | | | | | |
-- | -------- | | |
-- | | | |
-- | -------- | ---------- | |
-- | | | | | | | |
-- | | |->|->| |->| |
-- | | PAT | | | | | |
-- | | GEN | | | | | |
-- | |(ADDR | | | AXI-S | | |
-- | | SWAP)| | | FIFO | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | |<-|<-| |<-| |
-- | | | | | | | |
-- | -------- | ---------- | |
-- | | | |
-- | | ----------------------|
-- | -------------------------------------|
-- --------------------------------------------------
--------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.com5402pkg.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example_design level wrapper.
--------------------------------------------------------------------------------
entity gig_eth is
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- clocks
gtx_clk : in std_logic; -- 125MHz
ref_clk : in std_logic; -- 200MHz
-- PHY interface
phy_resetn : out std_logic;
-- RGMII Interface
------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- TCP
MAC_ADDR : IN std_logic_vector(47 DOWNTO 0);
IPv4_ADDR : IN std_logic_vector(31 DOWNTO 0);
IPv6_ADDR : IN std_logic_vector(127 DOWNTO 0);
SUBNET_MASK : IN std_logic_vector(31 DOWNTO 0);
GATEWAY_IP_ADDR : IN std_logic_vector(31 DOWNTO 0);
TCP_CONNECTION_RESET : IN std_logic;
TX_TDATA : IN std_logic_vector(7 downto 0);
TX_TVALID : IN std_logic;
TX_TREADY : OUT std_logic;
RX_TDATA : OUT std_logic_vector(7 downto 0);
RX_TVALID : OUT std_logic;
RX_TREADY : IN std_logic;
-- FIFO
TCP_USE_FIFO : IN std_logic;
TX_FIFO_WRCLK : IN std_logic;
TX_FIFO_Q : IN std_logic_vector(31 downto 0);
TX_FIFO_WREN : IN std_logic;
TX_FIFO_FULL : OUT std_logic;
RX_FIFO_RDCLK : IN std_logic;
RX_FIFO_Q : OUT std_logic_vector(31 downto 0);
RX_FIFO_RDEN : IN std_logic;
RX_FIFO_EMPTY : OUT std_logic;
--
TX_FIFO1_WRCLK : IN std_logic;
TX_FIFO1_Q : IN std_logic_vector(31 downto 0);
TX_FIFO1_WREN : IN std_logic;
TX_FIFO1_FULL : OUT std_logic;
RX_FIFO1_RDCLK : IN std_logic;
RX_FIFO1_Q : OUT std_logic_vector(31 downto 0);
RX_FIFO1_RDEN : IN std_logic;
RX_FIFO1_EMPTY : OUT std_logic
);
end gig_eth;
architecture wrapper of gig_eth is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
COMPONENT COM5402 IS
GENERIC (
CLK_FREQUENCY : integer := 125;
-- CLK frequency in MHz. Needed to compute actual delays.
TX_IDLE_TIMEOUT : integer RANGE 0 TO 50 := 50;
-- inactive input timeout, expressed in 4us units. -- 50*4us = 200us
-- Controls the transmit stream segmentation: data in the elastic buffer will be transmitted if
-- no input is received within TX_IDLE_TIMEOUT, without waiting for the transmit frame to be filled with MSS data bytes.
SIMULATION : std_logic := '0'
-- 1 during simulation with Wireshark .cap file, '0' otherwise
-- Wireshark many not be able to collect offloaded checksum computations.
-- when SIMULATION = '1': (a) IP header checksum is valid if 0000,
-- (b) TCP checksum computation is forced to a valid 00001 irrespective of the 16-bit checksum
-- captured by Wireshark.
);
PORT (
--//-- CLK, RESET
CLK : IN std_logic;
-- All signals are synchronous with CLK
-- CLK must be a global clock 125 MHz or faster to match the Gbps MAC speed.
ASYNC_RESET : IN std_logic; -- to be phased out. replace with SYNC_RESET
SYNC_RESET : IN std_logic;
--//-- CONFIGURATION
-- configuration signals are synchonous with CLK
-- Synchronous with CLK clock.
MAC_ADDR : IN std_logic_vector(47 DOWNTO 0);
IPv4_ADDR : IN std_logic_vector(31 DOWNTO 0);
IPv6_ADDR : IN std_logic_vector(127 DOWNTO 0);
SUBNET_MASK : IN std_logic_vector(31 DOWNTO 0);
GATEWAY_IP_ADDR : IN std_logic_vector(31 DOWNTO 0);
-- local IP address. 4 bytes for IPv4, 16 bytes for IPv6
-- Natural order (MSB) 172.16.1.128 (LSB) as transmitted in the IP frame.
--// User-initiated connection reset for stream I
CONNECTION_RESET : IN std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
--//-- Protocol -> Transmit MAC Interface
-- 32-bit CRC is automatically appended by the MAC layer. User should not supply it.
-- Synchonous with the user-side CLK
MAC_TX_DATA : OUT std_logic_vector(7 DOWNTO 0);
-- MAC reads the data at the rising edge of CLK when MAC_TX_DATA_VALID = '1'
MAC_TX_DATA_VALID : OUT std_logic;
-- data valid
MAC_TX_SOF : out std_logic;
-- start of frame: '1' when sending the first byte.
MAC_TX_EOF : OUT std_logic;
-- '1' when sending the last byte in a packet to be transmitted.
-- Aligned with MAC_TX_DATA_VALID
MAC_TX_CTS : IN std_logic;
-- MAC-generated Clear To Send flow control signal, indicating room in the
-- MAC tx elastic buffer for a complete maximum size frame 1518B.
-- The user should check that this signal is high before deciding to send
-- sending the next frame.
-- Note: MAC_TX_CTS may go low while the frame is transfered in. Ignore it as space is guaranteed
-- at the start of frame.
--//-- Receive MAC -> Protocol
-- Valid rx packets only: packets with bad CRC or invalid address are discarded.
-- The 32-bit CRC is always removed by the MAC layer.
-- Synchonous with the user-side CLK
MAC_RX_DATA : IN std_logic_vector(7 DOWNTO 0);
-- USER reads the data at the rising edge of CLK when MAC_RX_DATA_VALID = '1'
MAC_RX_DATA_VALID : IN std_logic;
-- data valid
MAC_RX_SOF : IN std_logic;
-- '1' when sending the first byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
MAC_RX_EOF : IN std_logic;
-- '1' when sending the last byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
--//-- Application <- UDP rx
UDP_RX_DATA : OUT std_logic_vector(7 DOWNTO 0);
UDP_RX_DATA_VALID : OUT std_logic;
UDP_RX_SOF : OUT std_logic;
UDP_RX_EOF : OUT std_logic;
-- 1 CLK pulse indicating that UDP_RX_DATA is the last byte in the UDP data field.
-- ALWAYS CHECK UDP_RX_DATA_VALID at the end of packet (UDP_RX_EOF = '1') to confirm
-- that the UDP packet is valid. External buffer may have to backtrack to the the last
-- valid pointer to discard an invalid UDP packet.
-- Reason: we only knows about bad UDP packets at the end.
UDP_RX_DEST_PORT_NO : IN std_logic_vector(15 DOWNTO 0);
--//-- Application -> UDP tx
UDP_TX_DATA : IN std_logic_vector(7 DOWNTO 0);
UDP_TX_DATA_VALID : IN std_logic;
UDP_TX_SOF : IN std_logic; -- 1 CLK-wide pulse to mark the first byte in the tx UDP frame
UDP_TX_EOF : IN std_logic; -- 1 CLK-wide pulse to mark the last byte in the tx UDP frame
UDP_TX_CTS : OUT std_logic;
UDP_TX_ACK : OUT std_logic; -- 1 CLK-wide pulse indicating that the previous UDP frame is being sent
UDP_TX_NAK : OUT std_logic; -- 1 CLK-wide pulse indicating that the previous UDP frame could not be sent
UDP_TX_DEST_IP_ADDR : IN std_logic_vector(127 DOWNTO 0);
UDP_TX_DEST_PORT_NO : IN std_logic_vector(15 DOWNTO 0);
UDP_TX_SOURCE_PORT_NO : IN std_logic_vector(15 DOWNTO 0);
--//-- Application <- TCP rx
-- NTCPSTREAMS can operate independently. Only one stream active at any given time.
-- Data is pushed out. Limited flow-control here. Receipient must be able to accept data
-- at any time (in other words, it is the receipient's responsibility to have elastic
-- buffer if needed).
TCP_RX_DATA : OUT SLV8xNTCPSTREAMStype;
TCP_RX_DATA_VALID : OUT std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
TCP_RX_RTS : OUT std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
TCP_RX_CTS : IN std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
-- Optional Clear-To-Send. pull to '1' when output flow control is unused.
-- WARNING: pulling CTS down will stop the flow for ALL streams.
--//-- Application -> TCP tx
-- NTCPSTREAMS can operate independently and concurrently. No scheduling arbitration needed here.
TCP_TX_DATA : IN SLV8xNTCPSTREAMStype;
TCP_TX_DATA_VALID : IN std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
TCP_TX_CTS : OUT std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
-- Clear To Send = transmit flow control.
-- App is responsible for checking the CTS signal before sending APP_DATA
--//-- TEST POINTS, COMSCOPE TRACES
CS1 : OUT std_logic_vector(7 DOWNTO 0);
CS1_CLK : OUT std_logic;
CS2 : OUT std_logic_vector(7 DOWNTO 0);
CS2_CLK : OUT std_logic;
TP : OUT std_logic_vector(10 DOWNTO 1)
);
END COMPONENT;
-- Must have programmable full with single-threshold of 61
-- out of total write-depth 64
COMPONENT fifo8to32
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(7 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(31 DOWNTO 0);
full : OUT std_logic;
prog_full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
COMPONENT fifo32to8
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(31 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(7 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for the Tri-Mode EMAC core FIFO Block wrapper
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_fifo_block
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- RGMII Interface
--------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
-- RGMII Inband Status Registers
----------------------------------
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for the AXI-Lite State machine
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_axi_lite_sm
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
phy_loopback : in std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0);
s_axi_awvalid : out std_logic;
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0);
s_axi_wvalid : out std_logic;
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0);
s_axi_arvalid : out std_logic;
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset logic
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_example_design_resets is
port (
-- clocks
s_axi_aclk : in std_logic;
gtx_clk : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
reset_error : in std_logic;
rx_reset : in std_logic;
tx_reset : in std_logic;
dcm_locked : in std_logic;
-- synchronous reset outputs
glbl_rst_intn : out std_logic;
gtx_resetn : out std_logic := '0';
s_axi_resetn : out std_logic := '0';
phy_resetn : out std_logic;
chk_resetn : out std_logic := '0'
);
end component;
------------------------------------------------------------------------------
-- internal signals used in this top level wrapper.
------------------------------------------------------------------------------
-- example design clocks
signal gtx_clk_bufg : std_logic;
signal refclk_bufg : std_logic;
signal s_axi_aclk : std_logic;
signal rx_mac_aclk : std_logic;
signal tx_mac_aclk : std_logic;
signal phy_resetn_int : std_logic;
-- resets (and reset generation)
signal reset_error : std_logic;
signal s_axi_resetn : std_logic;
signal chk_resetn : std_logic;
signal gtx_resetn : std_logic;
signal rx_reset : std_logic;
signal tx_reset : std_logic;
signal dcm_locked : std_logic;
signal glbl_rst_int : std_logic;
signal phy_reset_count : unsigned(5 downto 0) := (others => '0');
signal glbl_rst_intn : std_logic;
signal mac_speed : std_logic_vector(1 downto 0);
signal serial_response : std_logic;
signal frame_error : std_logic;
signal frame_errorn : std_logic;
signal activity_flash : std_logic;
signal activity_flashn : std_logic;
signal update_speed : std_logic := '0';
signal config_board : std_logic := '0';
-- USER side RX AXI-S interface
signal rx_fifo_clock : std_logic;
signal rx_fifo_resetn : std_logic;
signal rx_axis_fifo_tdata : std_logic_vector(7 downto 0);
signal rx_axis_fifo_tvalid : std_logic;
signal rx_axis_fifo_tlast : std_logic;
signal rx_axis_fifo_tready : std_logic;
-- USER side TX AXI-S interface
signal tx_fifo_clock : std_logic;
signal tx_fifo_resetn : std_logic;
signal tx_axis_fifo_tdata : std_logic_vector(7 downto 0);
signal tx_axis_fifo_tvalid : std_logic;
signal tx_axis_fifo_tlast : std_logic;
signal tx_axis_fifo_tready : std_logic;
-- RX Statistics serialisation signals
signal rx_statistics_s : std_logic := '0';
signal rx_statistics_valid : std_logic;
signal rx_statistics_valid_reg : std_logic;
signal rx_statistics_vector : std_logic_vector(27 downto 0);
signal rx_stats : std_logic_vector(27 downto 0);
signal rx_stats_shift : std_logic_vector(29 downto 0);
signal rx_stats_toggle : std_logic := '0';
signal rx_stats_toggle_sync : std_logic;
signal rx_stats_toggle_sync_reg : std_logic := '0';
-- TX Statistics serialisation signals
signal tx_statistics_s : std_logic := '0';
signal tx_statistics_valid : std_logic;
signal tx_statistics_valid_reg : std_logic;
signal tx_statistics_vector : std_logic_vector(31 downto 0);
signal tx_stats : std_logic_vector(31 downto 0);
signal tx_stats_shift : std_logic_vector(33 downto 0);
signal tx_stats_toggle : std_logic := '0';
signal tx_stats_toggle_sync : std_logic;
signal tx_stats_toggle_sync_reg : std_logic := '0';
-- Pause interface DESerialisation
signal pause_req_s : std_logic := '0';
signal pause_shift : std_logic_vector(18 downto 0);
signal pause_req : std_logic;
signal pause_val : std_logic_vector(15 downto 0);
-- AXI-Lite interface
signal s_axi_awaddr : std_logic_vector(11 downto 0);
signal s_axi_awvalid : std_logic;
signal s_axi_awready : std_logic;
signal s_axi_wdata : std_logic_vector(31 downto 0);
signal s_axi_wvalid : std_logic;
signal s_axi_wready : std_logic;
signal s_axi_bresp : std_logic_vector(1 downto 0);
signal s_axi_bvalid : std_logic;
signal s_axi_bready : std_logic;
signal s_axi_araddr : std_logic_vector(11 downto 0);
signal s_axi_arvalid : std_logic;
signal s_axi_arready : std_logic;
signal s_axi_rdata : std_logic_vector(31 downto 0);
signal s_axi_rresp : std_logic_vector(1 downto 0);
signal s_axi_rvalid : std_logic;
signal s_axi_rready : std_logic;
-- signal tie offs
signal tx_ifg_delay : std_logic_vector(7 downto 0) := (others => '0'); -- not used in this example
signal inband_link_status : std_logic;
signal inband_clock_speed : std_logic_vector(1 downto 0);
signal inband_duplex_status : std_logic;
signal int_frame_error : std_logic;
signal int_activity_flash : std_logic;
-- set board defaults - only updated when reprogrammed
signal enable_phy_loopback : std_logic := '0';
-- tcp
SIGNAL tcp_mac_addr : std_logic_vector(47 DOWNTO 0);
SIGNAL tcp_ipv4_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL tcp_ipv6_addr : std_logic_vector(127 DOWNTO 0);
SIGNAL tcp_subnet_mask : std_logic_vector(31 DOWNTO 0);
SIGNAL tcp_gateway_ip_addr : std_logic_vector(31 DOWNTO 0);
--
SIGNAL mac_rx_sof : std_logic;
--
SIGNAL tcp_rx_data_slv8x : SLV8xNTCPSTREAMStype;
SIGNAL tcp_tx_data_slv8x : SLV8xNTCPSTREAMStype;
SIGNAL tcp_rx_data_valid_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL tcp_tx_data_valid_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL tcp_rx_cts_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL tcp_tx_cts_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL tcp_rx_rts_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL connection_reset_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
--
SIGNAL rx_fifo_full : std_logic;
SIGNAL rx_fifo_fullm3 : std_logic;
SIGNAL tx_fifo_dout : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_fifo_rden : std_logic;
SIGNAL tx_fifo_empty : std_logic;
SIGNAL rx_fifo1_full : std_logic;
SIGNAL rx_fifo1_fullm3 : std_logic;
SIGNAL tx_fifo1_dout : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_fifo1_rden : std_logic;
SIGNAL tx_fifo1_empty : std_logic;
------------------------------------------------------------------------------
-- Begin architecture
------------------------------------------------------------------------------
begin
frame_error <= int_frame_error;
frame_errorn <= not int_frame_error;
activity_flash <= int_activity_flash;
activity_flashn <= not int_activity_flash;
mac_speed <= "11";
----------------------------------------------------------------------------
-- Clock logic to generate required clocks from the 200MHz on board
-- if 125MHz is available directly this can be removed
----------------------------------------------------------------------------
gtx_clk_bufg <= gtx_clk;
refclk_bufg <= ref_clk;
s_axi_aclk <= gtx_clk;
-- generate the user side clocks for the axi fifos
tx_fifo_clock <= gtx_clk_bufg;
rx_fifo_clock <= gtx_clk_bufg;
------------------------------------------------------------------------------
-- Generate resets required for the fifo side signals etc
------------------------------------------------------------------------------
example_resets : tri_mode_ethernet_mac_0_example_design_resets
port map (
-- clocks
s_axi_aclk => s_axi_aclk,
gtx_clk => gtx_clk_bufg,
-- asynchronous resets
glbl_rst => glbl_rst,
reset_error => reset_error,
rx_reset => rx_reset,
tx_reset => tx_reset,
dcm_locked => dcm_locked,
-- synchronous reset outputs
glbl_rst_intn => glbl_rst_intn,
gtx_resetn => gtx_resetn,
s_axi_resetn => s_axi_resetn,
phy_resetn => phy_resetn,
chk_resetn => chk_resetn
);
glbl_rst_int <= NOT glbl_rst_intn;
dcm_locked <= '1';
reset_error <= '0';
-- generate the user side resets for the axi fifos
tx_fifo_resetn <= gtx_resetn;
rx_fifo_resetn <= gtx_resetn;
----------------------------------------------------------------------------
-- Instantiate the AXI-LITE Controller
----------------------------------------------------------------------------
axi_lite_controller : tri_mode_ethernet_mac_0_axi_lite_sm
port map (
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
mac_speed => mac_speed,
update_speed => update_speed,
serial_command => pause_req_s,
serial_response => serial_response,
phy_loopback => enable_phy_loopback,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
------------------------------------------------------------------------------
-- Instantiate the TRIMAC core FIFO Block wrapper
------------------------------------------------------------------------------
trimac_fifo_block : tri_mode_ethernet_mac_0_fifo_block
port map (
gtx_clk => gtx_clk_bufg,
-- asynchronous reset
glbl_rstn => glbl_rst_intn,
rx_axi_rstn => '1',
tx_axi_rstn => '1',
-- Reference clock for IDELAYCTRL's
refclk => refclk_bufg,
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
-- Receiver => AXI-S Interface
------------------------------------------
rx_fifo_clock => rx_fifo_clock,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
-- Transmitter => AXI-S Interface
---------------------------------------------
tx_fifo_clock => tx_fifo_clock,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
-- MAC Control Interface
--------------------------
pause_req => pause_req,
pause_val => pause_val,
-- RGMII Interface
--------------------
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
-- RGMII Inband Status Registers
----------------------------------
inband_link_status => inband_link_status,
inband_clock_speed => inband_clock_speed,
inband_duplex_status => inband_duplex_status,
-- MDIO Interface
-------------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
---------------------------------------------< tcp_server
PROCESS (gtx_clk_bufg) IS
BEGIN -- Make configurations synchronous to CLK125 of the TCP module
IF rising_edge(gtx_clk_bufg) THEN
tcp_mac_addr <= MAC_ADDR;
tcp_ipv4_addr <= IPv4_ADDR;
tcp_ipv6_addr <= IPv6_ADDR;
tcp_subnet_mask <= SUBNET_MASK;
tcp_gateway_ip_addr <= GATEWAY_IP_ADDR;
END IF;
END PROCESS;
-- generate a 1-clk wide pulse SOF (start of frame)
mac_rx_sof_gen : PROCESS (gtx_clk_bufg, glbl_rst_int) IS
VARIABLE state : std_logic;
VARIABLE tvalid_prev : std_logic;
BEGIN
IF glbl_rst_int = '1' THEN
state := '0';
tvalid_prev := '0';
mac_rx_sof <= '0';
ELSIF falling_edge(gtx_clk_bufg) THEN
mac_rx_sof <= '0';
IF state = '0' THEN
IF tvalid_prev = '0' AND rx_axis_fifo_tvalid = '1' THEN
mac_rx_sof <= '1';
state := '1';
END IF;
ELSE -- state = '1'
IF rx_axis_fifo_tlast = '1' THEN
state := '0';
END IF;
END IF;
tvalid_prev := rx_axis_fifo_tvalid;
END IF;
END PROCESS;
rx_axis_fifo_tready <= '1';
connection_reset_v <= (OTHERS => TCP_CONNECTION_RESET);
tcp_server_inst : COM5402
GENERIC MAP (
CLK_FREQUENCY => 125,
-- CLK frequency in MHz. Needed to compute actual delays.
TX_IDLE_TIMEOUT => 50,
-- inactive input timeout, expressed in 4us units. -- 50*4us = 200us
-- Controls the transmit stream segmentation: data in the elastic buffer will be transmitted if
-- no input is received within TX_IDLE_TIMEOUT, without waiting for the transmit frame to be filled with MSS data bytes.
SIMULATION => '0'
-- 1 during simulation with Wireshark .cap file, '0' otherwise
-- Wireshark many not be able to collect offloaded checksum computations.
-- when SIMULATION = '1': (a) IP header checksum is valid if 0000,
-- (b) TCP checksum computation is forced to a valid 00001 irrespective of the 16-bit checksum
-- captured by Wireshark.
)
PORT MAP (
--//-- CLK, RESET
CLK => gtx_clk_bufg,
-- All signals are synchronous with CLK
-- CLK must be a global clock 125 MHz or faster to match the Gbps MAC speed.
ASYNC_RESET => glbl_rst_int, -- to be phased out. replace with SYNC_RESET
SYNC_RESET => glbl_rst_int,
--//-- CONFIGURATION
-- configuration signals are synchonous with CLK
-- Synchronous with CLK clock.
MAC_ADDR => tcp_mac_addr,
IPv4_ADDR => tcp_ipv4_addr,
IPv6_ADDR => tcp_ipv6_addr,
SUBNET_MASK => tcp_subnet_mask,
GATEWAY_IP_ADDR => tcp_gateway_ip_addr,
-- local IP address. 4 bytes for IPv4, 16 bytes for IPv6
-- Natural order (MSB) 172.16.1.128 (LSB) as transmitted in the IP frame.
--// User-initiated connection reset for stream I
CONNECTION_RESET => connection_reset_v,
--//-- Protocol -> Transmit MAC Interface
-- 32-bit CRC is automatically appended by the MAC layer. User should not supply it.
-- Synchonous with the user-side CLK
MAC_TX_DATA => tx_axis_fifo_tdata,
-- MAC reads the data at the rising edge of CLK when MAC_TX_DATA_VALID = '1'
MAC_TX_DATA_VALID => tx_axis_fifo_tvalid,
-- data valid
MAC_TX_SOF => OPEN,
-- start of frame: '1' when sending the first byte.
MAC_TX_EOF => tx_axis_fifo_tlast,
-- '1' when sending the last byte in a packet to be transmitted.
-- Aligned with MAC_TX_DATA_VALID
MAC_TX_CTS => tx_axis_fifo_tready,
-- MAC-generated Clear To Send flow control signal, indicating room in the
-- MAC tx elastic buffer for a complete maximum size frame 1518B.
-- The user should check that this signal is high before deciding to send
-- sending the next frame.
-- Note: MAC_TX_CTS may go low while the frame is transfered in. Ignore it as space is guaranteed
-- at the start of frame.
--//-- Receive MAC -> Protocol
-- Valid rx packets only: packets with bad CRC or invalid address are discarded.
-- The 32-bit CRC is always removed by the MAC layer.
-- Synchonous with the user-side CLK
MAC_RX_DATA => rx_axis_fifo_tdata,
-- USER reads the data at the rising edge of CLK when MAC_RX_DATA_VALID = '1'
MAC_RX_DATA_VALID => rx_axis_fifo_tvalid,
-- data valid
MAC_RX_SOF => mac_rx_sof,
-- '1' when sending the first byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
MAC_RX_EOF => rx_axis_fifo_tlast,
-- '1' when sending the last byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
--//-- Application <- UDP rx
UDP_RX_DATA => OPEN,
UDP_RX_DATA_VALID => OPEN,
UDP_RX_SOF => OPEN,
UDP_RX_EOF => OPEN,
-- 1 CLK pulse indicating that UDP_RX_DATA is the last byte in the UDP data field.
-- ALWAYS CHECK UDP_RX_DATA_VALID at the end of packet (UDP_RX_EOF = '1') to confirm
-- that the UDP packet is valid. External buffer may have to backtrack to the the last
-- valid pointer to discard an invalid UDP packet.
-- Reason: we only knows about bad UDP packets at the end.
UDP_RX_DEST_PORT_NO => (OTHERS => '0'),
--//-- Application -> UDP tx
UDP_TX_DATA => (OTHERS => '0'),
UDP_TX_DATA_VALID => '0',
UDP_TX_SOF => '0', -- 1 CLK-wide pulse to mark the first byte in the tx UDP frame
UDP_TX_EOF => '0', -- 1 CLK-wide pulse to mark the last byte in the tx UDP frame
UDP_TX_CTS => OPEN,
UDP_TX_ACK => OPEN, -- 1 CLK-wide pulse indicating that the previous UDP frame is being sent
UDP_TX_NAK => OPEN, -- 1 CLK-wide pulse indicating that the previous UDP frame could not be sent
UDP_TX_DEST_IP_ADDR => (OTHERS => '0'),
UDP_TX_DEST_PORT_NO => (OTHERS => '0'),
UDP_TX_SOURCE_PORT_NO => (OTHERS => '0'),
--//-- Application <- TCP rx
-- NTCPSTREAMS can operate independently. Only one stream active at any given time.
-- Data is pushed out. Limited flow-control here. Receipient must be able to accept data
-- at any time (in other words, it is the receipient's responsibility to have elastic
-- buffer if needed).
TCP_RX_DATA => tcp_rx_data_slv8x,
TCP_RX_DATA_VALID => tcp_rx_data_valid_v,
TCP_RX_RTS => tcp_rx_rts_v,
TCP_RX_CTS => tcp_rx_cts_v,
-- Optional Clear-To-Send. pull to '1' when output flow control is unused.
-- WARNING: pulling CTS down will stop the flow for ALL streams.
--//-- Application -> TCP tx
-- NTCPSTREAMS can operate independently and concurrently. No scheduling arbitration needed here.
TCP_TX_DATA => tcp_tx_data_slv8x,
TCP_TX_DATA_VALID => tcp_tx_data_valid_v,
TCP_TX_CTS => tcp_tx_cts_v,
-- Clear To Send = transmit flow control.
-- App is responsible for checking the CTS signal before sending APP_DATA
--//-- TEST POINTS, COMSCOPE TRACES
CS1 => OPEN,
CS1_CLK => OPEN,
CS2 => OPEN,
CS2_CLK => OPEN,
TP => OPEN
);
-- Must have programmable full with single-threshold of 61
-- out of total write-depth 64.
-- When RX_CTS is low, the Server continues to drive out 3 more bytes of data
-- (observed with ILA). The fifo must be able to accept them, hence the use
-- of prog_full.
rx_fifo_inst : fifo8to32
PORT MAP (
rst => glbl_rst_int,
wr_clk => gtx_clk_bufg,
rd_clk => RX_FIFO_RDCLK,
din => tcp_rx_data_slv8x(0),
wr_en => tcp_rx_data_valid_v(0),
rd_en => RX_FIFO_RDEN,
dout => RX_FIFO_Q,
full => rx_fifo_full,
prog_full => rx_fifo_fullm3, -- asserted at (full-3) writes
empty => RX_FIFO_EMPTY
);
tcp_rx_cts_v(0) <= (NOT rx_fifo_fullm3) WHEN TCP_USE_FIFO = '1' ELSE
RX_TREADY;
RX_TDATA <= tcp_rx_data_slv8x(0);
RX_TVALID <= tcp_rx_data_valid_v(0);
tx_fifo_inst : fifo32to8
PORT MAP (
rst => glbl_rst_int,
wr_clk => TX_FIFO_WRCLK,
rd_clk => gtx_clk_bufg,
din => TX_FIFO_Q,
wr_en => TX_FIFO_WREN,
rd_en => tx_fifo_rden,
dout => tx_fifo_dout,
full => TX_FIFO_FULL,
empty => tx_fifo_empty
);
tcp_tx_data_valid_v(0) <= ((NOT tx_fifo_empty) AND tcp_tx_cts_v(0)) WHEN TCP_USE_FIFO = '1' ELSE
TX_TVALID;
tx_fifo_rden <= tcp_tx_data_valid_v(0);
tcp_tx_data_slv8x(0) <= tx_fifo_dout WHEN TCP_USE_FIFO = '1' ELSE
TX_TDATA;
TX_TREADY <= tcp_tx_cts_v(0);
-- Stream 1
rx_fifo1_inst : fifo8to32
PORT MAP (
rst => glbl_rst_int,
wr_clk => gtx_clk_bufg,
rd_clk => RX_FIFO1_RDCLK,
din => tcp_rx_data_slv8x(1),
wr_en => tcp_rx_data_valid_v(1),
rd_en => RX_FIFO1_RDEN,
dout => RX_FIFO1_Q,
full => rx_fifo1_full,
prog_full => rx_fifo1_fullm3, -- asserted at (full-3) writes
empty => RX_FIFO1_EMPTY
);
tcp_rx_cts_v(1) <= NOT rx_fifo1_fullm3;
tx_fifo1_inst : fifo32to8
PORT MAP (
rst => glbl_rst_int,
wr_clk => TX_FIFO1_WRCLK,
rd_clk => gtx_clk_bufg,
din => TX_FIFO1_Q,
wr_en => TX_FIFO1_WREN,
rd_en => tx_fifo1_rden,
dout => tx_fifo1_dout,
full => TX_FIFO1_FULL,
empty => tx_fifo1_empty
);
tcp_tx_data_valid_v(1) <= ((NOT tx_fifo1_empty) AND tcp_tx_cts_v(1));
tx_fifo1_rden <= tcp_tx_data_valid_v(1);
tcp_tx_data_slv8x(1) <= tx_fifo1_dout;
end wrapper;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:27:52 10/09/2011
-- Design Name:
-- Module Name: C:/Users/BOB/Calculadora/Source/InputModuleTest.vhd
-- Project Name: Calculadora
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: InputFSM
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CalculadoraTest IS
END CalculadoraTest;
ARCHITECTURE behavior OF CalculadoraTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CalculadoraFSM
PORT(
input : IN std_logic;
clock : IN std_logic;
reset : IN std_logic;
output : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal input : std_logic := '0';
signal clock : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal output : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CalculadoraFSM PORT MAP (
input => input,
clock => clock,
reset => reset,
output => output
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
--wait for 100 ns;
-- Prueba de Multiplicacion: Resultado esperado 100100 -> Osea 36
-- bcd 1001 -> Osea 9
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='1';
wait for 10 ns;
-- operacion Multiplicacion 10
input <='0';
wait for 10 ns;
input <='1';
wait for 10 ns;
-- bcd 0100 -> Osea 4
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
wait for 180 ns;-- Necesitamos un ciclo para realizar los calculos
-- y dejar 10 ns para mostrar los resultados
reset <= '1';--Reseteamos
wait for 10 ns;
reset <= '0';
-- Prueba de Suma: Resultado esperado 0011 -> Osea 3
-- bcd 0001 -> Osea 1
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
-- operacion Suma 00
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
-- bcd 0010 -> Osea 2
input <='0';
wait for 10 ns;
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
wait for 180 ns;-- Necesitamos un ciclo para realizar los calculos
-- y dejar 10 ns para mostrar los resultados
reset <= '1';--Reseteamos
wait for 10 ns;
reset <= '0';
-- Prueba de Resta: Resultado esperado 0010 -> Osea 2
-- bcd 0101 -> Osea 5
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
-- operacion Resta 01
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
-- bcd 0011 -> Osea 3
input <='1';
wait for 10 ns;
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
wait for clock_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:43:54 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_ov7670_controller_0_0 -prefix
-- system_ov7670_controller_0_0_ system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal taken : STD_LOGIC;
begin
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
xclk <= 'Z';
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
-- Button Press Synchronizer para keys que são ativas baixas (ou seja, quando pressionadas vao para nivel baixo)
library ieee;
use ieee.std_logic_1164.all;
entity ButtonSync is
port
(
-- Input ports
key0 : in std_logic;
key1 : in std_logic;
key2 : in std_logic;
key3 : in std_logic;
clk : in std_logic;
-- Output ports
btn0 : out std_logic;
btn1 : out std_logic;
btn2 : out std_logic;
btn3 : out std_logic
);
end ButtonSync;
architecture ButtonSyncImpl of ButtonSync is
type STATES is (EsperaApertar, SaidaAtiva, EsperaSoltar);
signal btn0state, btn1state, btn2state, btn3state : STATES := EsperaApertar;
signal btn0next, btn1next, btn2next, btn3next : STATES := EsperaApertar;
begin
process (clk)
begin
if clk'event and clk = '1' then -- Resposta na transicao positiva do clock
btn0state <= btn0next;
btn1state <= btn1next;
btn2state <= btn2next;
btn3state <= btn3next;
end if;
end process;
process (key0,btn0state)
begin
case btn0state is
when EsperaApertar =>
if key0 = '0' then btn0next <= SaidaAtiva; else btn0next <= EsperaApertar; end if;
btn0 <= '1';
when SaidaAtiva =>
if key0 = '0' then btn0next <= EsperaSoltar; else btn0next <= EsperaApertar; end if;
btn0 <= '0';
when EsperaSoltar =>
if key0 = '0' then btn0next <= EsperaSoltar; else btn0next <= EsperaApertar; end if;
btn0 <= '1';
end case;
end process;
process (key1,btn1state)
begin
case btn1state is
when EsperaApertar =>
if key1 = '0' then btn1next <= SaidaAtiva; else btn1next <= EsperaApertar; end if;
btn1 <= '1';
when SaidaAtiva =>
if key1 = '0' then btn1next <= EsperaSoltar; else btn1next <= EsperaApertar; end if;
btn1 <= '0';
when EsperaSoltar =>
if key1 = '0' then btn1next <= EsperaSoltar; else btn1next <= EsperaApertar; end if;
btn1 <= '1';
end case;
end process;
process (key2,btn2state)
begin
case btn2state is
when EsperaApertar =>
if key2 = '0' then btn2next <= SaidaAtiva; else btn2next <= EsperaApertar; end if;
btn2 <= '1';
when SaidaAtiva =>
if key2 = '0' then btn2next <= EsperaSoltar; else btn2next <= EsperaApertar; end if;
btn2 <= '0';
when EsperaSoltar =>
if key2 = '0' then btn2next <= EsperaSoltar; else btn2next <= EsperaApertar; end if;
btn2 <= '1';
end case;
end process;
process (key3,btn3state)
begin
case btn3state is
when EsperaApertar =>
if key3 = '0' then btn3next <= SaidaAtiva; else btn3next <= EsperaApertar; end if;
btn3 <= '1';
when SaidaAtiva =>
if key3 = '0' then btn3next <= EsperaSoltar; else btn3next <= EsperaApertar; end if;
btn3 <= '0';
when EsperaSoltar =>
if key3 = '0' then btn3next <= EsperaSoltar; else btn3next <= EsperaApertar; end if;
btn3 <= '1';
end case;
end process;
end ButtonSyncImpl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: l2cache
-- File: libcache.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: L2-Cache component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package l2cache is
component l2c is
generic (
hslvidx : integer := 0;
hmstidx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
cached : integer := 16#0000#;
hirq : integer := 0;
cen : integer range 0 to 1 := 0;
hproten : integer range 0 to 1 := 0;
wp : integer range 0 to 1 := 0;
repl : integer range 0 to 1 := 0;
ways : integer range 1 to 4 := 1;
linesize : integer range 16 to 64 := 32;
waysize : integer range 1 to 512 := 1;
memtech : integer range 0 to NTECH := 0;
bbuswidth : integer := 128;
bioaddr : integer := 16#000#;
biomask : integer := 16#000#;
sbus : integer := 0;
mbus : integer := 1;
stat : integer range 0 to 2 := 0;
scantest : integer := 0;
arch : integer := 0;
mtrr : integer := 0;
edacen : integer range 0 to 1 := 0;
rmw : integer range 0 to 1 := 0;
ft : integer range 0 to 1 := 0;
fttiming : integer range 0 to 1 := 0;
wbmask : integer range 0 to 16#FFFF# := 16#FFFF#;
debug : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsov: in ahb_slv_out_vector;
sto : out std_logic_vector(2 downto 0);
debugo: out std_logic_vector(255*debug downto 0)
);
end component;
end;
package body l2cache is
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ijGsPeN2IsIR73K/pq7pNvIVfL+yGCBU9d2PYspGWocl4eglQ+ci1s2LKHxiK/khQcbf4FiA5kqc
aVvQMBHzVQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j9jOQkhjSueqJxMr/PEFIfJ1lwfF7Y9tUSDeDkMS2PlN7uPiwmHvvTHM+GEqMzMdya7VIaAiCUq7
+t0EMUGllv682Ktjd6PjQVAnv9sX3WTHOL2DT6AMXFg0bNpQYhAkpk810eqyBTClrLcKov59URn7
EYWwi+9Rc6mFyHMHL+4=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
kPoG92c/oBOxgV/zdve01Jx7h5Eg7Iziljiy+f2Mr775K3XJFSArYaLzaIpJgnKSMHLAtIRqkD6N
69NYCR1DusSPZwdBjv9BpXBLkUCl3tnm/Lfsq8pkTsbqFb0oLr+4AfyGdFdPl7LzcAEAFSoFGiGz
7gaTG/dlkxVmmxllJEvUbjUS/EBdDLouJYG1TGYHBGcahRwC0gCz8TMnpSIIPcE/mbkEhWiYWh4o
aLtBKvg2c9+0XP/dHM4fzowL43OFN4gCLocFOV5aekhCY1LH4aDQF9tp8AE1ES8s+k+O8mDNRPW/
TxHBm31nat1dOhBGN9Chh5HOmcReW8Q3eYENpg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4Qy/RPGogfA2cO5eoM91ob4uay7VAZnCvwQYb3elAmUZoEP/a+KmpmspGgrShCSQOFSAamIqYsJa
GnmN3+toeenoDuNUzt39ZLrXu4sMEmS/5nemZGGeXzFFbiZS1wh+BdHTAFnFhoCVVkP4TEQ5b6Hf
w4WlXdspCjjsS/lMcg8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
iThWEfjJcy2bl/WuwSnVnc13v6cua1tEs2BKKswvXSpocjn87BRf3HC4eJ9Qt16FX6RB0O8vjZnl
Q5eGo/YWfFj2nQILQPV7VDTZ+EwsHO4HNh9nmR5N5ibOIaiPCm0HxkAPkWcqg2Rbv/VsHcRNGaED
jbQ1dnBpg+R7NupqlgHDXZt5LLJ/RwftT8qZxUr6DW/Gk5bgg5cmI2Qg8BqVqssqykMgwZMQ0PsZ
HL1cVK12176nJxoZ3zACXuBfi6U2va9MyC71n6q/WDcHRSyEPzgU3QZsYUWhjGjY95B65ficQ94I
AmYkV6pMSJxClstFCHTtrwxoUro25R5VdQjbEA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7120)
`protect data_block
LLs8LriFBcBbqTuEBcCZ6+9ZawU41NQ4QLHKJUJC8b51j5g3/gzhJuwf8vwiqJ7hazjZe1h/Liqz
CC6U7C1EeQOxm9udNTPyRmeIpBeuYfgsuQEIoC6VieinzjZcfITk+rTnQh71OtY1XKPC7jEMnWpr
0NGIzxeaBNek5J5ozB0+QctTKkvvX5xZEainn7e0jQyd97yxv+UtF1GNQAobuMlyq8KGxhvYJ6Z/
uKE/CQbuf2rBnds/hbU5Xr31Momm8IXvYV267yPYr0wHkw2LKJuwzBkNmhquJrm7u5IPg7tqyj1c
sex7HVJfCEhpLmh53zXpP1HtfSYfIH4Wco1MAXggQgoA22FP3VUKNmL5lly3eVvObAAmCV8YUCiY
TfvEaC1ky0q1Z8n6YUneyLidPNFI00EAGOhVQWAklUx822Xl8isHGcYYwyKHWQwEzPLw5j3Oi/Lj
pi0MPfnDN5P4RtIFXVAu5y2LE/bZiYGMTLIqnp25nQvVsysE9o1mmkfgaujIB8FPpF72SaiQWdn7
o7+eDSXWYovG8G3aIXmNzwjYss54ayVfIDZaR4QSoUXKzpKS9CIAldJrVyucp95iOH2vxg+EfkuO
2Sai7KV+fdZshp7YN2kFSRUuyMllmE6eaVO7LzbPTU3px/gLENoDqDNK/rzKWWNJv3CskgXPqsrR
cRCyNbtpd+m5dhhDX7MpMWzEzk+TkLi4Vrps9684AOu4nfPr8yNdijuZaSuknagJX2BMsY+m6zd2
igwsKtrkmQUAQj19rAXMa+ATFfV8D9EoL4mCc2kz2OJvipK22wvIDGTCxvPHVHPWDVi22XImkuxk
Mn7C3cDlzQsTHyoS7JI2ci2GRX+pp8EGKazxbUo2ltd5y6WUQZOGvW+I8BLFMbICJBtVFDMS9Cw1
Bquy6mQ5L+MwVZupzyLEESYlJauFHXmjw4pcy5wALGpxECwI8ov3twCiBy9Jt/MPv1kliKvHdd6c
Ad3hkAoBURP7xtvdrTfAfJwd25sFbuow2/Sf2E3CPZhNoQ0Oe659/CEwd4HXBxXpub9t1yScZjJt
BwTz16rHhvQ9p6zHfGQAvwSW8/+9kk10WsNBDLV+g4HFBsTd0IesWuDzjieM54p6clHF009B9jBe
o07QTSiFekqcGTBIGkBWv2vywfkEWNpiGpOtdsDYGLdlQ63DEKi/GFzrVZD0vx8hjv6Y4lGwjMFm
5Kx4PyTODBfyZbjGEn6Sw3Uggvup5kta8ufACGbWVwFSxACencFwAMw2NB7Abmexh7tomSKqmFzY
12/kHM3pLTBwv221IKpMmhDJgVEnwMw5sQAbA2+RY68res9qCdhdC66PDN7IjfL3lG7zvgNt9xnV
/4Tj7GvVXsgqJdqlascVFRY00/o2T0NlxlcsoZVlXwkEFZKMCM6UknH0G/idjkCukP35CWTaJqOQ
MY02NsLQwL8kLgvPPVhoKVuhY74Fom4mFwMdx2sARooaQ5Z25l3jnLdwhSMOi+YHUJbPRWxDk784
+z6CQ0TE6+SPSJeAi1tOTVy1t44itoimMlu42BQ3QkyV3X06kd+G0sFZQiPp50P0U9egBx7MdOPv
qDF8B7ILeoCDGhfLW1qkKTMPs0icd0soBa5Ehr6vDEKtCJklV5j4VPTS7y9Mzp+T5bM50sAA+69t
FpdjBYfvH2zDzjQRvIChzyD8ceuE5uuQqqQTXgZOIOCbsBgWljxH/brSy/tbEW2K2+9n4ZmctE31
Q+LeKlBDOLVk5XnkBXiG6R67DmFAp9f2/0eRRLDGNZ8dCGxtU6vP5wvQmC3PxptjrWJbzWO2UJ5l
dcvLtmWXA4KtDdNHDzLH4C6F5ugdsltExuRUJ0docb55wumtEIaSPeC0Hch9K1N0wq7xqifNpM18
l+660B+pAitePsyZkLPhalTb6mFt9Glzvz69nnJbabdaUKG4LKhK3f/D0aKMEJxzKcL3arfBhDEf
flEXjU4wB/0bRWrAdlLAFPPnA+I7+/FUq2Yax/Y6dXSJumL90jnGSomAs1IlX5vDJp6GahEweV0j
D7/aWoOrnjmzv8YUnlDWL6PwccsPpXl4I6kIeU+SjD7kqBdaDHZMmKh//l6eemcteitTAh+VDmXX
GZCp3vHRBfVn1E6KVaL1mnpVehDLFQfeVkaiah4OiZfrckHv67BkbwErCL9Ciq/XmT0Hi3u88V9Z
kFagjL+LqNPm+xArKa8tmLgmUjrDVhavWEkfyoysAIg61oE1s4WGnTLWlc5mPTa4WfKQzPxc+sRd
fI333YBE59A9kGMa69QWaiM4hlXbEj9CMXcO74m83vFYtWyNwUbH7EEX+0SOMrbIS8fVbND2Vzvp
eKCSWND/on3HxpSWV9h77jSpNWS622GtzJTFWTECSicEogZ6ex4BsH7p+FXsdkPHORah+IeHewx7
13iPbbNxaJBLP1QplOBCXTCGL4MZ+ej30PuIosvsb7199tBLzrfMuFC2hYV4Ta5ln2twBwujedej
g8jFZZkpstrd4P4JNP2qDYmdu40ukiiZIuESEX3ezJ8KZ7g7sehqAi+nM9+bzpQob4VOwTM9Fc4h
G75ccIW9qO94HH8bSE5sDWvYRxiqAf+a0GIyPKLvQm6rR/CSMhP0ppeBc6Ii896fj4ouK8Ij+5I1
jl2E/O+SNgjbjSNcS0esrwJoLBl6E5X+Gjg8Pb0h7pQRb660Q0LgYJ9lDzN9TKkajrNh5fWFAUyz
WMUGF7WrW1O/fjGEhSTE03qMO+ioTCNsz0ySrGGtVPMCTetHrZ8Wv7QIQApssjoC2Jnr6u/9NRQG
PEM1qJCwkaXvLGvdbHPKpWVtjkJf+dhKpQZ0UEKKBcC/+oRFW83G8tJ0UXXwAbQMqdYVOCF/SQKb
KYUV+p6ixNPCeEYlVOeqZ1FJUaO9QjcBIYAcBcquTlS6/oa4eMj/n/+3CSt7WWRhU041tNX6YM8V
hRUOAbcVASCSF00thoceti2w2ymJl3ZGIgN0ppMP5/QQscLhI73u87G9Efi40puQueHKUr21OpDz
tMNfeYdrPktkQ7/UAcdDFF0jl6I4LWuyl7M1myVRalhOWO2Zqd//MyQ8/eVMdU+liokZ/WWj7V9M
izp3CwQdjaXuTWw0pUSoaFGBO7e1CJWGNjaGv3On9O1kchz1MaOVzrQci5JSCTpGoLTCLDqZj4B9
6rjBBfA8ad8nccpIURo0Xk7kwmwi68zhy9AUmFb7SGt5HLGPIeYkRNwGu1VmgGHSE1HpDSkVwyyf
juyX0lmcI/ftNh/nT+Fu5SJDT6M39DLhd8/pQfCfCuuvU7ZVAMazjKkLdG1cZEc+W4zD3gkQGyCn
y5iLfMro4f1fHbgPglNkRnYaf+FICZ4slVNJSt0zRlfq2qALzkPMZqxlEJnP2IUISVXtzEVQlXXy
viwh+NcxOyFLZuDs9BJQFhdcLLjWAyTaMngeN3Y/EFmt8ysh8t+r4plWnUglLwhhjYT2QXMq+wXn
oV7vSxPOc6jC5/yxkRSDAqJQOo+Vqum9mCccBslOJhV9aarnRBQ8wwllJduqDM7HX6iSyQv4VeR6
VpoPNkh5vv2ZWs5KUvpaZbeANyMRi1eVGeKEzaLyQIr5fcaxfROSGqTp/4JMSoNgMZUZo5lKf4RR
m63d9RYPq6kxeS/WqXaSmV40xSbfi3K5++MU7o4eAg3UmkRGLRoo2ysg/+NSVmZFEPc2RGJTUNKT
EE9ONiRxi7ZRg+OxWiWQ8HmsDQgCc52v+C6t2Qwl0E1zJj3/IHsWcltb42WwU84jLMPyAQwiIsg1
O7gWqs571he8TIW+4hbwD8CF4zbT5833qDDHAOBpGLh8RZD248J2BLn+AdXwQHBWClRr9t0GAPlb
wUONaLhFhIR9W3ryW6ZNG7SWVk7Yw/etjJDMvuC+XYtOXr6DqdJMYDiDYAkoQcLWqcra4G24GdzB
Q1dzxkykxtCb3vHNAoWLQJtza9t81wrB4ILM0lXlI4un1CH+UEZzxyGbOZph+VjmfLaZzuFh44VC
0O58iyq4p6wCpQ8gnjBB3bSvR2HlIZ5ODvNKcVffyWSe+bz/hViUPH48ZqLUR94THsJHT30ng593
KyUET9IlBJDHSwbhPp9RdVqhsS7EJUHmXAF7E5Q5W4z0TyBu27hPwUolBbScqq1PlrCM3yQoOyrq
jBO/xWQK4RgGcSFy0qbuKZc6LnElw2CyMx+VMJUOvJ64JFkqIRWHooapfVAVY+7H09I9IECbecND
NxJLXdw31T2yy7gU69tBisYVdcj/WG3t7VEsSPij8js/ptVzbi4FGl2k6vHUPTf25Kw3fx3XH9vi
k9yFM3ATdYUHqtge+gna5i/kFmM8KXqhtzThHe04ISAbgmfpZY/Qm00f+q+4N0ppTqguFwFIdp4d
SpRSRWdMQFYOTLd3tazbKoMuK987f1m3sFvD0G9JmjsL/t5lddwNMQ7oJT/42bB8B9eoMJAtOXfL
eTeImV7tD6NpkiDkOAHPqGdbjhGQ8sV1y36F6R+rwtf0Xbh3BBqHv+Y5rarucgMF1fR44YxtkcOn
EBNP5EMXXkGKUgI4t9qQ89Vfmrhe2kJDLsoQ350m19KNeCuInpVTIDQbO0BuH5K7mhz9ibE5cbP9
vnCUiJegA2DieKS5AiUtqfoWShxglDgeM04+KKpBELKwfqTb5uv5eaBh028yeIpm2KYqhBVOL9Oz
kt3uZsP1e9JzlJJ0cOFqfslf5/TlAOombhhX0edntBE4sXyLDlXy9xkFh/wZdSMuqwfOuUdH5cju
DSQ4BbxeQSdHSNOM04EKVSv31WpEuimRxmnvf1KXqVVhi68lavCzXdEQ2XIzRQ8tb91ErWgMVWoK
B5+fL3VjynEsjrkKKLADgbt3t+f9UBqER5lv9S2h8353X2N5NtYI6HKq6ZOyvugQ2MeiBASLLEAE
c+rsYlRygs4RwZBe3P0RRO87laQcCr5LFpvV8/xSgfTzOdhjZrorpIBk5V+R+i7gs3wxPETy61be
XhrJAL1oU8eB92of5JO/to+Z6h28NR+m+QVYZNwfnvwcL3moemYWSoQfVbht65rFswGxbv4t9VSF
ZWV1TeciTKWko4Pnho7q60gtNybibG/pzIEG/YlS1qm2kL9ed1WzndsaZICpTtMP4qHn18wBm8DT
NlJ1mz8IbEXBAbss5X0CHPL86ejlWRFmk0bIQ3CElVlG9Rc8SzdNvkYxkC1IBPZ6+Li44nI3HMFL
l0U66Bgw2RvQpfLKV6ehrygM4XGAfu5BgBhrIK7HTIJxzHAz40nO4J+bNYYashktx+o9GzMgPJh7
mA2dI1I0jVW1cwi41GNKIo0R688jzdikJ4RDNIzZLK/PLGVU3wJ/T/UoqfJjgDxUpVn28uljgu0p
J1UImOXVsFdn2a+vlRw/u195+ud4GnVDEZbuuik0Q5LmlMSku8zDLu8zV03xerqmt7DSlNRhUNoY
1ucGZfJIkaGdyCxVpPOpnnDA1frkjv/CsKvfUCvGYX2yzfpL0fzyjzHLEhkuMUAnS8RLuTuLi4ur
lj4HkYKYi+o0wwUqaQBudov1GABysKaDn5a7pxaqDys8fCwBLmI2+oY/Iu+pSkJEpMyc9ukvMZwF
79V1hJxkGm/fZHt42NJflm7XLdGKkiZ4mU2kNkFHzqH6aNIk1We/CYlTRafK5s/gij86mZjwXxOR
LtglWRN+LwUzkzAbJ1pAJLRSyYPH+/uZsTVfS2Q+37JPClKdnun4xaapIuDO+VqeZAR1KVvOecXI
1SDbQwSaLRU3JkZzgWuQ/xPLq0rck9JXX37sXMR3J14mGrQe1TbUGBUORHdIDwI1t3HPE+beTsaF
Cr0EjOqayTt5R+XDDUOXXIyTUJkFaIjnDK1yWhtRuPdo64fRfbFyvjTh7PTuA0vpsQ2AGxYigUR7
g6UhQ0XlxukCkuBYvx+KO84FODRWqH6K19y636BRv9OYX4Obv9XWqrtIVexo+7y+KCpKuQhgQwie
eJRbwwtPMTln1XL1xAIOLyYMcmzcvX/BawHMJMhaug1PVl+mg2s8KobDDDMpRBtJQgg17kn9NzYw
tvWJFESmCyPL+Np912fzCVa087i0hYT5aBt3jnk4ji0ZvARhMXldaaiy6w6/21ycM/QIBY7U4bZ9
E9MMblyd6+J9XB2io8+uI3PS5IHEr4Au5ZTunPvaFiRbNaXkAN0oq5VTW3oFEOWZzhY/syVI0H8q
d60xJ6YwXigiiWlk6kMsAolGS5zMoRTQ2W9MQz7jSSqys8jH/11ixDI9gDqnpZnla4prcd/H22YK
/SeddLLiq8BrbChV2X81RXR/lfXB4Ozb/63gjZzaduVHv0hZqyNy7r2FTJxCueS7K2vg+IBVr2/F
+bJdBnZVSCDA6Xdpgrek7CrC/F4t6wr3i2M2rmzv1RaC/qY9pWUUbjtGzk0ttccuCz8cP6GNJilo
Sg5NP8kGnJYR2/gPzqJcHnb9IwK4zf4Q9mvYRIu1LTgbx1/zeClT6dTMA4lbjp0NHEQW9TwVrRAh
by4vS0RZ3cidC39yVyg69vxAVXc1iexlPMsX90iCN8zzFBi/lphatdc2uZpW9ov5UqFaa6qKAU/N
lJj0x+AhLN8Z7HTI4K6Kva9+ksIkamXEhRVmkMV7KwCNyFFpnRodiGN6cRWT1P91c+tLK+ifIZLb
IXnD9FOT7vCb3ubnfMesXVBT8xkbzXDGxuVs6D6pXhnaITnRkyU2nZxDwBYuuyKNtBbuDM3CW9Vp
dfbChmTmuj4puiMuscwgCOMkWx74h3+mN+ajAGCFT1cJtvOqUTvBSCOELdIlpHjY8bodYDGgoxpU
YGBZXZNYwA2FBanaaRf9ptO/WLOYQiY9/uxB37AhCZf3kxE35dEeYQlDJweT2Kj95NBpWxpIngs7
Qo5nVWyLjyS2+4Kal4oiVa+19qdMFbaKjQsvU58BnS2kIHhPTEKdcjiyQWr7Bx1zuZD3uO14/J0z
vpumFUhaHxhZdCqlb802z0C35anBvBO/Qo2UA2DM4a7x7T683I7I+xxCBOLj/qHZ0drY4sSQRdNS
2L3QGAsFtUAfsqjTSJ0/ob1YarhMXf6B7WSKDS1WRBK2WMyWxJomGkrEoWLZ4rcICFGnXMYY4H/H
Azfekm2ykWbb/iQLl/CQe1A02SpfvcGBVH5Bt1ahMPLOSSLzrTsOBBB8Ka6T8BF5IPXmHnsvlyuV
UM1GFSf/VgjiABWSY8xP3/3B0QkrESo/KaAuHFKIXqCuk42dFCgC9q0aEIY+tax92twRQL4TXV0e
0sJ57/LnEqXUKD9DiXpfoDet0cqjRtm3ci0ZOTzboRTDdzBQFsZw0tbtBsg2uoj8vV95FnFq9K/4
LWQSO0XJ6Yq1Oe/F1piz0Otpqi+P3qcrHJlNugTj85CJzsvG+MApBpYTIHQPIqlr8wR+lUaqyLHH
lPvLVqkPmwEGEK0oqnbWmXtNMFeaiyTfMQpohmxjiq5Hlhaa5VbmYl9vG9nYZu+4fKCJtvw008wc
TbKkY0ZCei/jz64pRXWFNIn78rP4d2SNA0XMZ6MoV7DbXBWqtz52qArwU/LXzT5nat0/KNH+rgWj
fGgbd8fIN8Ha97NSduPx8vAPgaIdLmsqlT1DxuyGKAbGg+u+M2QuZc4evHOKcVi1fOLq3nQI6evy
7TxMlLXtHdAdyd54pI3gv9jmLc06NmUo2u39u/sGJxXv7PCv8molcZbAF+1AbLHucXPnJWxWf3KD
YW/zRIu9iA62jl5zN23K7NeRnN31p9KTSSFO13KHXoUtN0GwaR4kkTcmaDEQbeETAHMwuq2i7yTY
rxNG88hAvrZhgJoF0UnICT8GJU5xxckAiIWfJtsg+kbLfEnNTiVwgHPI2oqSLi8ofvWmh4UuV28J
Abjb7TJ2uqvpowe7oRIRsyjl1Da0Z+lvz88vOxiRw+/ZcOzNlHsuDZuLWRHIyn8HLiAnZTwUT03g
V++5wVRpQVrLLFeI6Eld/NOVXQ8a84HXAjAV5olFV2eS2bBGwj7dS6rmiVyjsi+qmdbM0hqe9R8O
p88/3DZpCn30FFvf3QV+a91F2QtrQoQxe6JAqZ2qIKqX1XtbTRqs0WqfpQmvHmct07uZA+iQpbq+
K/sldQRqunqXhXnVCe2ObMYVscCQyIiQBiiRXa0L54sJYjDDj6IY6JUoZKu3I7aIuOyG66tSHgLQ
S/n/X9LaagzkOCGowzc01vm9hNFvTKsHHaUYJ6r6+/KXYRct27uL26ZYXmbiK4ExIVAmGyuEDV1o
KVlt5ey1CVBdcvI6VrWwJtiRPKJSsj25fmWVZgFWNF9LoSMeFIiDHti93/eokw9OKnFPiNA/yvwi
t/5u7LwlHQTQ5HmwOu1Vow0Y7SVzyaWsijv5xGzN3uIs52VccdRbmVYlunSONQAE85EmB40pM9n4
P1iA1QknvqNmIE11NGD+R+IgYpd+PA1pzjLtizEFteEsehsdj2d1AQxt2IJf3k8XKpR9ue1Yas1g
GHREH4szpRpjsg9STvPPzuhRnbJ0t8vvfQYupa6sUsNcYGtMp6daR6EpN4Q0+v2jmMvK9iOtWeXS
y5qleujb3JQybH2GFiiK1icEqTQUG7JGxMA/u767tZB+SSEgzLXf+kPhIvEuMBOUEcxNLMMII3Tz
ED1XlOXB+7dUGGxhUvZp0OZNHyRN8qJZ3SyXnIZu06V8aeKGXxgGJ+fyFP0Ar0fqbYzusHYpaEvB
8QW2Tm+W1uxU5woUQR93a2WfDXGOps7bfQCMR7oXSRY1+t1Tkj5vA7NOfnlvKrDt0b+0lFK+JyMQ
qEizG13BTSUYxTYCbrro/oHdIu38jSqhDeLx3RunRnbNuj8uEQWaV39AiyICSgvi/5Srjr92mXMK
yyyKM3MLR5NIGZBbOJ7UOCX0fcelZHsBwMn8oFUQrJVPplxknK4koanL169WG/X5Ggm00cjaT4w5
9tT6xFl6ZhMFH2sajD7FhSangvlLAkHBz9MDUy4CpVEG7Ku6hiCouj1o831yt8QBKOcjPZliMOEw
PiH3prtGiyTcfu080OFdX6wsGkZ2MJJ+dV5wXuohg5JKwhyMuGOUx3KT3gaM4v3LJMrPQLEygFBP
FEesBkZWUqopqt5NS8Q1mex7GRCsqRIcoS6M9SQm5T2nxcINtxVr/XcxZ2IZArqjkTlD2YRtdX/s
NRCB5hubt0x4JGQg7aWcmgThfmzJeh7HY7kfm6NgeK8NRnPKgcyPtO71txytcC465XzS0Kc9LOOQ
YnRjhqnZiV3r/zQ9tC6NPo0Qaj+LUR/7aOSHvDIgffJ97l65ANTR8c7Rpl44hiDYdMO6gZ0cJklq
VxxpvM07qvYiwFPKvgZsqBSuROiSHGwIfEInlX1i2ajDS6pzvYIRNE2XfX6Ap9UjUDLS99T33i7A
eGZlgVPyEDgMKk7/40qDOU4esTKHdtX/ul7y4BTbNaNnxGANbplYveQodgf/K+78nHt/Gw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ijGsPeN2IsIR73K/pq7pNvIVfL+yGCBU9d2PYspGWocl4eglQ+ci1s2LKHxiK/khQcbf4FiA5kqc
aVvQMBHzVQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j9jOQkhjSueqJxMr/PEFIfJ1lwfF7Y9tUSDeDkMS2PlN7uPiwmHvvTHM+GEqMzMdya7VIaAiCUq7
+t0EMUGllv682Ktjd6PjQVAnv9sX3WTHOL2DT6AMXFg0bNpQYhAkpk810eqyBTClrLcKov59URn7
EYWwi+9Rc6mFyHMHL+4=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
kPoG92c/oBOxgV/zdve01Jx7h5Eg7Iziljiy+f2Mr775K3XJFSArYaLzaIpJgnKSMHLAtIRqkD6N
69NYCR1DusSPZwdBjv9BpXBLkUCl3tnm/Lfsq8pkTsbqFb0oLr+4AfyGdFdPl7LzcAEAFSoFGiGz
7gaTG/dlkxVmmxllJEvUbjUS/EBdDLouJYG1TGYHBGcahRwC0gCz8TMnpSIIPcE/mbkEhWiYWh4o
aLtBKvg2c9+0XP/dHM4fzowL43OFN4gCLocFOV5aekhCY1LH4aDQF9tp8AE1ES8s+k+O8mDNRPW/
TxHBm31nat1dOhBGN9Chh5HOmcReW8Q3eYENpg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4Qy/RPGogfA2cO5eoM91ob4uay7VAZnCvwQYb3elAmUZoEP/a+KmpmspGgrShCSQOFSAamIqYsJa
GnmN3+toeenoDuNUzt39ZLrXu4sMEmS/5nemZGGeXzFFbiZS1wh+BdHTAFnFhoCVVkP4TEQ5b6Hf
w4WlXdspCjjsS/lMcg8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
iThWEfjJcy2bl/WuwSnVnc13v6cua1tEs2BKKswvXSpocjn87BRf3HC4eJ9Qt16FX6RB0O8vjZnl
Q5eGo/YWfFj2nQILQPV7VDTZ+EwsHO4HNh9nmR5N5ibOIaiPCm0HxkAPkWcqg2Rbv/VsHcRNGaED
jbQ1dnBpg+R7NupqlgHDXZt5LLJ/RwftT8qZxUr6DW/Gk5bgg5cmI2Qg8BqVqssqykMgwZMQ0PsZ
HL1cVK12176nJxoZ3zACXuBfi6U2va9MyC71n6q/WDcHRSyEPzgU3QZsYUWhjGjY95B65ficQ94I
AmYkV6pMSJxClstFCHTtrwxoUro25R5VdQjbEA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7120)
`protect data_block
LLs8LriFBcBbqTuEBcCZ6+9ZawU41NQ4QLHKJUJC8b51j5g3/gzhJuwf8vwiqJ7hazjZe1h/Liqz
CC6U7C1EeQOxm9udNTPyRmeIpBeuYfgsuQEIoC6VieinzjZcfITk+rTnQh71OtY1XKPC7jEMnWpr
0NGIzxeaBNek5J5ozB0+QctTKkvvX5xZEainn7e0jQyd97yxv+UtF1GNQAobuMlyq8KGxhvYJ6Z/
uKE/CQbuf2rBnds/hbU5Xr31Momm8IXvYV267yPYr0wHkw2LKJuwzBkNmhquJrm7u5IPg7tqyj1c
sex7HVJfCEhpLmh53zXpP1HtfSYfIH4Wco1MAXggQgoA22FP3VUKNmL5lly3eVvObAAmCV8YUCiY
TfvEaC1ky0q1Z8n6YUneyLidPNFI00EAGOhVQWAklUx822Xl8isHGcYYwyKHWQwEzPLw5j3Oi/Lj
pi0MPfnDN5P4RtIFXVAu5y2LE/bZiYGMTLIqnp25nQvVsysE9o1mmkfgaujIB8FPpF72SaiQWdn7
o7+eDSXWYovG8G3aIXmNzwjYss54ayVfIDZaR4QSoUXKzpKS9CIAldJrVyucp95iOH2vxg+EfkuO
2Sai7KV+fdZshp7YN2kFSRUuyMllmE6eaVO7LzbPTU3px/gLENoDqDNK/rzKWWNJv3CskgXPqsrR
cRCyNbtpd+m5dhhDX7MpMWzEzk+TkLi4Vrps9684AOu4nfPr8yNdijuZaSuknagJX2BMsY+m6zd2
igwsKtrkmQUAQj19rAXMa+ATFfV8D9EoL4mCc2kz2OJvipK22wvIDGTCxvPHVHPWDVi22XImkuxk
Mn7C3cDlzQsTHyoS7JI2ci2GRX+pp8EGKazxbUo2ltd5y6WUQZOGvW+I8BLFMbICJBtVFDMS9Cw1
Bquy6mQ5L+MwVZupzyLEESYlJauFHXmjw4pcy5wALGpxECwI8ov3twCiBy9Jt/MPv1kliKvHdd6c
Ad3hkAoBURP7xtvdrTfAfJwd25sFbuow2/Sf2E3CPZhNoQ0Oe659/CEwd4HXBxXpub9t1yScZjJt
BwTz16rHhvQ9p6zHfGQAvwSW8/+9kk10WsNBDLV+g4HFBsTd0IesWuDzjieM54p6clHF009B9jBe
o07QTSiFekqcGTBIGkBWv2vywfkEWNpiGpOtdsDYGLdlQ63DEKi/GFzrVZD0vx8hjv6Y4lGwjMFm
5Kx4PyTODBfyZbjGEn6Sw3Uggvup5kta8ufACGbWVwFSxACencFwAMw2NB7Abmexh7tomSKqmFzY
12/kHM3pLTBwv221IKpMmhDJgVEnwMw5sQAbA2+RY68res9qCdhdC66PDN7IjfL3lG7zvgNt9xnV
/4Tj7GvVXsgqJdqlascVFRY00/o2T0NlxlcsoZVlXwkEFZKMCM6UknH0G/idjkCukP35CWTaJqOQ
MY02NsLQwL8kLgvPPVhoKVuhY74Fom4mFwMdx2sARooaQ5Z25l3jnLdwhSMOi+YHUJbPRWxDk784
+z6CQ0TE6+SPSJeAi1tOTVy1t44itoimMlu42BQ3QkyV3X06kd+G0sFZQiPp50P0U9egBx7MdOPv
qDF8B7ILeoCDGhfLW1qkKTMPs0icd0soBa5Ehr6vDEKtCJklV5j4VPTS7y9Mzp+T5bM50sAA+69t
FpdjBYfvH2zDzjQRvIChzyD8ceuE5uuQqqQTXgZOIOCbsBgWljxH/brSy/tbEW2K2+9n4ZmctE31
Q+LeKlBDOLVk5XnkBXiG6R67DmFAp9f2/0eRRLDGNZ8dCGxtU6vP5wvQmC3PxptjrWJbzWO2UJ5l
dcvLtmWXA4KtDdNHDzLH4C6F5ugdsltExuRUJ0docb55wumtEIaSPeC0Hch9K1N0wq7xqifNpM18
l+660B+pAitePsyZkLPhalTb6mFt9Glzvz69nnJbabdaUKG4LKhK3f/D0aKMEJxzKcL3arfBhDEf
flEXjU4wB/0bRWrAdlLAFPPnA+I7+/FUq2Yax/Y6dXSJumL90jnGSomAs1IlX5vDJp6GahEweV0j
D7/aWoOrnjmzv8YUnlDWL6PwccsPpXl4I6kIeU+SjD7kqBdaDHZMmKh//l6eemcteitTAh+VDmXX
GZCp3vHRBfVn1E6KVaL1mnpVehDLFQfeVkaiah4OiZfrckHv67BkbwErCL9Ciq/XmT0Hi3u88V9Z
kFagjL+LqNPm+xArKa8tmLgmUjrDVhavWEkfyoysAIg61oE1s4WGnTLWlc5mPTa4WfKQzPxc+sRd
fI333YBE59A9kGMa69QWaiM4hlXbEj9CMXcO74m83vFYtWyNwUbH7EEX+0SOMrbIS8fVbND2Vzvp
eKCSWND/on3HxpSWV9h77jSpNWS622GtzJTFWTECSicEogZ6ex4BsH7p+FXsdkPHORah+IeHewx7
13iPbbNxaJBLP1QplOBCXTCGL4MZ+ej30PuIosvsb7199tBLzrfMuFC2hYV4Ta5ln2twBwujedej
g8jFZZkpstrd4P4JNP2qDYmdu40ukiiZIuESEX3ezJ8KZ7g7sehqAi+nM9+bzpQob4VOwTM9Fc4h
G75ccIW9qO94HH8bSE5sDWvYRxiqAf+a0GIyPKLvQm6rR/CSMhP0ppeBc6Ii896fj4ouK8Ij+5I1
jl2E/O+SNgjbjSNcS0esrwJoLBl6E5X+Gjg8Pb0h7pQRb660Q0LgYJ9lDzN9TKkajrNh5fWFAUyz
WMUGF7WrW1O/fjGEhSTE03qMO+ioTCNsz0ySrGGtVPMCTetHrZ8Wv7QIQApssjoC2Jnr6u/9NRQG
PEM1qJCwkaXvLGvdbHPKpWVtjkJf+dhKpQZ0UEKKBcC/+oRFW83G8tJ0UXXwAbQMqdYVOCF/SQKb
KYUV+p6ixNPCeEYlVOeqZ1FJUaO9QjcBIYAcBcquTlS6/oa4eMj/n/+3CSt7WWRhU041tNX6YM8V
hRUOAbcVASCSF00thoceti2w2ymJl3ZGIgN0ppMP5/QQscLhI73u87G9Efi40puQueHKUr21OpDz
tMNfeYdrPktkQ7/UAcdDFF0jl6I4LWuyl7M1myVRalhOWO2Zqd//MyQ8/eVMdU+liokZ/WWj7V9M
izp3CwQdjaXuTWw0pUSoaFGBO7e1CJWGNjaGv3On9O1kchz1MaOVzrQci5JSCTpGoLTCLDqZj4B9
6rjBBfA8ad8nccpIURo0Xk7kwmwi68zhy9AUmFb7SGt5HLGPIeYkRNwGu1VmgGHSE1HpDSkVwyyf
juyX0lmcI/ftNh/nT+Fu5SJDT6M39DLhd8/pQfCfCuuvU7ZVAMazjKkLdG1cZEc+W4zD3gkQGyCn
y5iLfMro4f1fHbgPglNkRnYaf+FICZ4slVNJSt0zRlfq2qALzkPMZqxlEJnP2IUISVXtzEVQlXXy
viwh+NcxOyFLZuDs9BJQFhdcLLjWAyTaMngeN3Y/EFmt8ysh8t+r4plWnUglLwhhjYT2QXMq+wXn
oV7vSxPOc6jC5/yxkRSDAqJQOo+Vqum9mCccBslOJhV9aarnRBQ8wwllJduqDM7HX6iSyQv4VeR6
VpoPNkh5vv2ZWs5KUvpaZbeANyMRi1eVGeKEzaLyQIr5fcaxfROSGqTp/4JMSoNgMZUZo5lKf4RR
m63d9RYPq6kxeS/WqXaSmV40xSbfi3K5++MU7o4eAg3UmkRGLRoo2ysg/+NSVmZFEPc2RGJTUNKT
EE9ONiRxi7ZRg+OxWiWQ8HmsDQgCc52v+C6t2Qwl0E1zJj3/IHsWcltb42WwU84jLMPyAQwiIsg1
O7gWqs571he8TIW+4hbwD8CF4zbT5833qDDHAOBpGLh8RZD248J2BLn+AdXwQHBWClRr9t0GAPlb
wUONaLhFhIR9W3ryW6ZNG7SWVk7Yw/etjJDMvuC+XYtOXr6DqdJMYDiDYAkoQcLWqcra4G24GdzB
Q1dzxkykxtCb3vHNAoWLQJtza9t81wrB4ILM0lXlI4un1CH+UEZzxyGbOZph+VjmfLaZzuFh44VC
0O58iyq4p6wCpQ8gnjBB3bSvR2HlIZ5ODvNKcVffyWSe+bz/hViUPH48ZqLUR94THsJHT30ng593
KyUET9IlBJDHSwbhPp9RdVqhsS7EJUHmXAF7E5Q5W4z0TyBu27hPwUolBbScqq1PlrCM3yQoOyrq
jBO/xWQK4RgGcSFy0qbuKZc6LnElw2CyMx+VMJUOvJ64JFkqIRWHooapfVAVY+7H09I9IECbecND
NxJLXdw31T2yy7gU69tBisYVdcj/WG3t7VEsSPij8js/ptVzbi4FGl2k6vHUPTf25Kw3fx3XH9vi
k9yFM3ATdYUHqtge+gna5i/kFmM8KXqhtzThHe04ISAbgmfpZY/Qm00f+q+4N0ppTqguFwFIdp4d
SpRSRWdMQFYOTLd3tazbKoMuK987f1m3sFvD0G9JmjsL/t5lddwNMQ7oJT/42bB8B9eoMJAtOXfL
eTeImV7tD6NpkiDkOAHPqGdbjhGQ8sV1y36F6R+rwtf0Xbh3BBqHv+Y5rarucgMF1fR44YxtkcOn
EBNP5EMXXkGKUgI4t9qQ89Vfmrhe2kJDLsoQ350m19KNeCuInpVTIDQbO0BuH5K7mhz9ibE5cbP9
vnCUiJegA2DieKS5AiUtqfoWShxglDgeM04+KKpBELKwfqTb5uv5eaBh028yeIpm2KYqhBVOL9Oz
kt3uZsP1e9JzlJJ0cOFqfslf5/TlAOombhhX0edntBE4sXyLDlXy9xkFh/wZdSMuqwfOuUdH5cju
DSQ4BbxeQSdHSNOM04EKVSv31WpEuimRxmnvf1KXqVVhi68lavCzXdEQ2XIzRQ8tb91ErWgMVWoK
B5+fL3VjynEsjrkKKLADgbt3t+f9UBqER5lv9S2h8353X2N5NtYI6HKq6ZOyvugQ2MeiBASLLEAE
c+rsYlRygs4RwZBe3P0RRO87laQcCr5LFpvV8/xSgfTzOdhjZrorpIBk5V+R+i7gs3wxPETy61be
XhrJAL1oU8eB92of5JO/to+Z6h28NR+m+QVYZNwfnvwcL3moemYWSoQfVbht65rFswGxbv4t9VSF
ZWV1TeciTKWko4Pnho7q60gtNybibG/pzIEG/YlS1qm2kL9ed1WzndsaZICpTtMP4qHn18wBm8DT
NlJ1mz8IbEXBAbss5X0CHPL86ejlWRFmk0bIQ3CElVlG9Rc8SzdNvkYxkC1IBPZ6+Li44nI3HMFL
l0U66Bgw2RvQpfLKV6ehrygM4XGAfu5BgBhrIK7HTIJxzHAz40nO4J+bNYYashktx+o9GzMgPJh7
mA2dI1I0jVW1cwi41GNKIo0R688jzdikJ4RDNIzZLK/PLGVU3wJ/T/UoqfJjgDxUpVn28uljgu0p
J1UImOXVsFdn2a+vlRw/u195+ud4GnVDEZbuuik0Q5LmlMSku8zDLu8zV03xerqmt7DSlNRhUNoY
1ucGZfJIkaGdyCxVpPOpnnDA1frkjv/CsKvfUCvGYX2yzfpL0fzyjzHLEhkuMUAnS8RLuTuLi4ur
lj4HkYKYi+o0wwUqaQBudov1GABysKaDn5a7pxaqDys8fCwBLmI2+oY/Iu+pSkJEpMyc9ukvMZwF
79V1hJxkGm/fZHt42NJflm7XLdGKkiZ4mU2kNkFHzqH6aNIk1We/CYlTRafK5s/gij86mZjwXxOR
LtglWRN+LwUzkzAbJ1pAJLRSyYPH+/uZsTVfS2Q+37JPClKdnun4xaapIuDO+VqeZAR1KVvOecXI
1SDbQwSaLRU3JkZzgWuQ/xPLq0rck9JXX37sXMR3J14mGrQe1TbUGBUORHdIDwI1t3HPE+beTsaF
Cr0EjOqayTt5R+XDDUOXXIyTUJkFaIjnDK1yWhtRuPdo64fRfbFyvjTh7PTuA0vpsQ2AGxYigUR7
g6UhQ0XlxukCkuBYvx+KO84FODRWqH6K19y636BRv9OYX4Obv9XWqrtIVexo+7y+KCpKuQhgQwie
eJRbwwtPMTln1XL1xAIOLyYMcmzcvX/BawHMJMhaug1PVl+mg2s8KobDDDMpRBtJQgg17kn9NzYw
tvWJFESmCyPL+Np912fzCVa087i0hYT5aBt3jnk4ji0ZvARhMXldaaiy6w6/21ycM/QIBY7U4bZ9
E9MMblyd6+J9XB2io8+uI3PS5IHEr4Au5ZTunPvaFiRbNaXkAN0oq5VTW3oFEOWZzhY/syVI0H8q
d60xJ6YwXigiiWlk6kMsAolGS5zMoRTQ2W9MQz7jSSqys8jH/11ixDI9gDqnpZnla4prcd/H22YK
/SeddLLiq8BrbChV2X81RXR/lfXB4Ozb/63gjZzaduVHv0hZqyNy7r2FTJxCueS7K2vg+IBVr2/F
+bJdBnZVSCDA6Xdpgrek7CrC/F4t6wr3i2M2rmzv1RaC/qY9pWUUbjtGzk0ttccuCz8cP6GNJilo
Sg5NP8kGnJYR2/gPzqJcHnb9IwK4zf4Q9mvYRIu1LTgbx1/zeClT6dTMA4lbjp0NHEQW9TwVrRAh
by4vS0RZ3cidC39yVyg69vxAVXc1iexlPMsX90iCN8zzFBi/lphatdc2uZpW9ov5UqFaa6qKAU/N
lJj0x+AhLN8Z7HTI4K6Kva9+ksIkamXEhRVmkMV7KwCNyFFpnRodiGN6cRWT1P91c+tLK+ifIZLb
IXnD9FOT7vCb3ubnfMesXVBT8xkbzXDGxuVs6D6pXhnaITnRkyU2nZxDwBYuuyKNtBbuDM3CW9Vp
dfbChmTmuj4puiMuscwgCOMkWx74h3+mN+ajAGCFT1cJtvOqUTvBSCOELdIlpHjY8bodYDGgoxpU
YGBZXZNYwA2FBanaaRf9ptO/WLOYQiY9/uxB37AhCZf3kxE35dEeYQlDJweT2Kj95NBpWxpIngs7
Qo5nVWyLjyS2+4Kal4oiVa+19qdMFbaKjQsvU58BnS2kIHhPTEKdcjiyQWr7Bx1zuZD3uO14/J0z
vpumFUhaHxhZdCqlb802z0C35anBvBO/Qo2UA2DM4a7x7T683I7I+xxCBOLj/qHZ0drY4sSQRdNS
2L3QGAsFtUAfsqjTSJ0/ob1YarhMXf6B7WSKDS1WRBK2WMyWxJomGkrEoWLZ4rcICFGnXMYY4H/H
Azfekm2ykWbb/iQLl/CQe1A02SpfvcGBVH5Bt1ahMPLOSSLzrTsOBBB8Ka6T8BF5IPXmHnsvlyuV
UM1GFSf/VgjiABWSY8xP3/3B0QkrESo/KaAuHFKIXqCuk42dFCgC9q0aEIY+tax92twRQL4TXV0e
0sJ57/LnEqXUKD9DiXpfoDet0cqjRtm3ci0ZOTzboRTDdzBQFsZw0tbtBsg2uoj8vV95FnFq9K/4
LWQSO0XJ6Yq1Oe/F1piz0Otpqi+P3qcrHJlNugTj85CJzsvG+MApBpYTIHQPIqlr8wR+lUaqyLHH
lPvLVqkPmwEGEK0oqnbWmXtNMFeaiyTfMQpohmxjiq5Hlhaa5VbmYl9vG9nYZu+4fKCJtvw008wc
TbKkY0ZCei/jz64pRXWFNIn78rP4d2SNA0XMZ6MoV7DbXBWqtz52qArwU/LXzT5nat0/KNH+rgWj
fGgbd8fIN8Ha97NSduPx8vAPgaIdLmsqlT1DxuyGKAbGg+u+M2QuZc4evHOKcVi1fOLq3nQI6evy
7TxMlLXtHdAdyd54pI3gv9jmLc06NmUo2u39u/sGJxXv7PCv8molcZbAF+1AbLHucXPnJWxWf3KD
YW/zRIu9iA62jl5zN23K7NeRnN31p9KTSSFO13KHXoUtN0GwaR4kkTcmaDEQbeETAHMwuq2i7yTY
rxNG88hAvrZhgJoF0UnICT8GJU5xxckAiIWfJtsg+kbLfEnNTiVwgHPI2oqSLi8ofvWmh4UuV28J
Abjb7TJ2uqvpowe7oRIRsyjl1Da0Z+lvz88vOxiRw+/ZcOzNlHsuDZuLWRHIyn8HLiAnZTwUT03g
V++5wVRpQVrLLFeI6Eld/NOVXQ8a84HXAjAV5olFV2eS2bBGwj7dS6rmiVyjsi+qmdbM0hqe9R8O
p88/3DZpCn30FFvf3QV+a91F2QtrQoQxe6JAqZ2qIKqX1XtbTRqs0WqfpQmvHmct07uZA+iQpbq+
K/sldQRqunqXhXnVCe2ObMYVscCQyIiQBiiRXa0L54sJYjDDj6IY6JUoZKu3I7aIuOyG66tSHgLQ
S/n/X9LaagzkOCGowzc01vm9hNFvTKsHHaUYJ6r6+/KXYRct27uL26ZYXmbiK4ExIVAmGyuEDV1o
KVlt5ey1CVBdcvI6VrWwJtiRPKJSsj25fmWVZgFWNF9LoSMeFIiDHti93/eokw9OKnFPiNA/yvwi
t/5u7LwlHQTQ5HmwOu1Vow0Y7SVzyaWsijv5xGzN3uIs52VccdRbmVYlunSONQAE85EmB40pM9n4
P1iA1QknvqNmIE11NGD+R+IgYpd+PA1pzjLtizEFteEsehsdj2d1AQxt2IJf3k8XKpR9ue1Yas1g
GHREH4szpRpjsg9STvPPzuhRnbJ0t8vvfQYupa6sUsNcYGtMp6daR6EpN4Q0+v2jmMvK9iOtWeXS
y5qleujb3JQybH2GFiiK1icEqTQUG7JGxMA/u767tZB+SSEgzLXf+kPhIvEuMBOUEcxNLMMII3Tz
ED1XlOXB+7dUGGxhUvZp0OZNHyRN8qJZ3SyXnIZu06V8aeKGXxgGJ+fyFP0Ar0fqbYzusHYpaEvB
8QW2Tm+W1uxU5woUQR93a2WfDXGOps7bfQCMR7oXSRY1+t1Tkj5vA7NOfnlvKrDt0b+0lFK+JyMQ
qEizG13BTSUYxTYCbrro/oHdIu38jSqhDeLx3RunRnbNuj8uEQWaV39AiyICSgvi/5Srjr92mXMK
yyyKM3MLR5NIGZBbOJ7UOCX0fcelZHsBwMn8oFUQrJVPplxknK4koanL169WG/X5Ggm00cjaT4w5
9tT6xFl6ZhMFH2sajD7FhSangvlLAkHBz9MDUy4CpVEG7Ku6hiCouj1o831yt8QBKOcjPZliMOEw
PiH3prtGiyTcfu080OFdX6wsGkZ2MJJ+dV5wXuohg5JKwhyMuGOUx3KT3gaM4v3LJMrPQLEygFBP
FEesBkZWUqopqt5NS8Q1mex7GRCsqRIcoS6M9SQm5T2nxcINtxVr/XcxZ2IZArqjkTlD2YRtdX/s
NRCB5hubt0x4JGQg7aWcmgThfmzJeh7HY7kfm6NgeK8NRnPKgcyPtO71txytcC465XzS0Kc9LOOQ
YnRjhqnZiV3r/zQ9tC6NPo0Qaj+LUR/7aOSHvDIgffJ97l65ANTR8c7Rpl44hiDYdMO6gZ0cJklq
VxxpvM07qvYiwFPKvgZsqBSuROiSHGwIfEInlX1i2ajDS6pzvYIRNE2XfX6Ap9UjUDLS99T33i7A
eGZlgVPyEDgMKk7/40qDOU4esTKHdtX/ul7y4BTbNaNnxGANbplYveQodgf/K+78nHt/Gw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ijGsPeN2IsIR73K/pq7pNvIVfL+yGCBU9d2PYspGWocl4eglQ+ci1s2LKHxiK/khQcbf4FiA5kqc
aVvQMBHzVQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j9jOQkhjSueqJxMr/PEFIfJ1lwfF7Y9tUSDeDkMS2PlN7uPiwmHvvTHM+GEqMzMdya7VIaAiCUq7
+t0EMUGllv682Ktjd6PjQVAnv9sX3WTHOL2DT6AMXFg0bNpQYhAkpk810eqyBTClrLcKov59URn7
EYWwi+9Rc6mFyHMHL+4=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
kPoG92c/oBOxgV/zdve01Jx7h5Eg7Iziljiy+f2Mr775K3XJFSArYaLzaIpJgnKSMHLAtIRqkD6N
69NYCR1DusSPZwdBjv9BpXBLkUCl3tnm/Lfsq8pkTsbqFb0oLr+4AfyGdFdPl7LzcAEAFSoFGiGz
7gaTG/dlkxVmmxllJEvUbjUS/EBdDLouJYG1TGYHBGcahRwC0gCz8TMnpSIIPcE/mbkEhWiYWh4o
aLtBKvg2c9+0XP/dHM4fzowL43OFN4gCLocFOV5aekhCY1LH4aDQF9tp8AE1ES8s+k+O8mDNRPW/
TxHBm31nat1dOhBGN9Chh5HOmcReW8Q3eYENpg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4Qy/RPGogfA2cO5eoM91ob4uay7VAZnCvwQYb3elAmUZoEP/a+KmpmspGgrShCSQOFSAamIqYsJa
GnmN3+toeenoDuNUzt39ZLrXu4sMEmS/5nemZGGeXzFFbiZS1wh+BdHTAFnFhoCVVkP4TEQ5b6Hf
w4WlXdspCjjsS/lMcg8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
iThWEfjJcy2bl/WuwSnVnc13v6cua1tEs2BKKswvXSpocjn87BRf3HC4eJ9Qt16FX6RB0O8vjZnl
Q5eGo/YWfFj2nQILQPV7VDTZ+EwsHO4HNh9nmR5N5ibOIaiPCm0HxkAPkWcqg2Rbv/VsHcRNGaED
jbQ1dnBpg+R7NupqlgHDXZt5LLJ/RwftT8qZxUr6DW/Gk5bgg5cmI2Qg8BqVqssqykMgwZMQ0PsZ
HL1cVK12176nJxoZ3zACXuBfi6U2va9MyC71n6q/WDcHRSyEPzgU3QZsYUWhjGjY95B65ficQ94I
AmYkV6pMSJxClstFCHTtrwxoUro25R5VdQjbEA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7120)
`protect data_block
LLs8LriFBcBbqTuEBcCZ6+9ZawU41NQ4QLHKJUJC8b51j5g3/gzhJuwf8vwiqJ7hazjZe1h/Liqz
CC6U7C1EeQOxm9udNTPyRmeIpBeuYfgsuQEIoC6VieinzjZcfITk+rTnQh71OtY1XKPC7jEMnWpr
0NGIzxeaBNek5J5ozB0+QctTKkvvX5xZEainn7e0jQyd97yxv+UtF1GNQAobuMlyq8KGxhvYJ6Z/
uKE/CQbuf2rBnds/hbU5Xr31Momm8IXvYV267yPYr0wHkw2LKJuwzBkNmhquJrm7u5IPg7tqyj1c
sex7HVJfCEhpLmh53zXpP1HtfSYfIH4Wco1MAXggQgoA22FP3VUKNmL5lly3eVvObAAmCV8YUCiY
TfvEaC1ky0q1Z8n6YUneyLidPNFI00EAGOhVQWAklUx822Xl8isHGcYYwyKHWQwEzPLw5j3Oi/Lj
pi0MPfnDN5P4RtIFXVAu5y2LE/bZiYGMTLIqnp25nQvVsysE9o1mmkfgaujIB8FPpF72SaiQWdn7
o7+eDSXWYovG8G3aIXmNzwjYss54ayVfIDZaR4QSoUXKzpKS9CIAldJrVyucp95iOH2vxg+EfkuO
2Sai7KV+fdZshp7YN2kFSRUuyMllmE6eaVO7LzbPTU3px/gLENoDqDNK/rzKWWNJv3CskgXPqsrR
cRCyNbtpd+m5dhhDX7MpMWzEzk+TkLi4Vrps9684AOu4nfPr8yNdijuZaSuknagJX2BMsY+m6zd2
igwsKtrkmQUAQj19rAXMa+ATFfV8D9EoL4mCc2kz2OJvipK22wvIDGTCxvPHVHPWDVi22XImkuxk
Mn7C3cDlzQsTHyoS7JI2ci2GRX+pp8EGKazxbUo2ltd5y6WUQZOGvW+I8BLFMbICJBtVFDMS9Cw1
Bquy6mQ5L+MwVZupzyLEESYlJauFHXmjw4pcy5wALGpxECwI8ov3twCiBy9Jt/MPv1kliKvHdd6c
Ad3hkAoBURP7xtvdrTfAfJwd25sFbuow2/Sf2E3CPZhNoQ0Oe659/CEwd4HXBxXpub9t1yScZjJt
BwTz16rHhvQ9p6zHfGQAvwSW8/+9kk10WsNBDLV+g4HFBsTd0IesWuDzjieM54p6clHF009B9jBe
o07QTSiFekqcGTBIGkBWv2vywfkEWNpiGpOtdsDYGLdlQ63DEKi/GFzrVZD0vx8hjv6Y4lGwjMFm
5Kx4PyTODBfyZbjGEn6Sw3Uggvup5kta8ufACGbWVwFSxACencFwAMw2NB7Abmexh7tomSKqmFzY
12/kHM3pLTBwv221IKpMmhDJgVEnwMw5sQAbA2+RY68res9qCdhdC66PDN7IjfL3lG7zvgNt9xnV
/4Tj7GvVXsgqJdqlascVFRY00/o2T0NlxlcsoZVlXwkEFZKMCM6UknH0G/idjkCukP35CWTaJqOQ
MY02NsLQwL8kLgvPPVhoKVuhY74Fom4mFwMdx2sARooaQ5Z25l3jnLdwhSMOi+YHUJbPRWxDk784
+z6CQ0TE6+SPSJeAi1tOTVy1t44itoimMlu42BQ3QkyV3X06kd+G0sFZQiPp50P0U9egBx7MdOPv
qDF8B7ILeoCDGhfLW1qkKTMPs0icd0soBa5Ehr6vDEKtCJklV5j4VPTS7y9Mzp+T5bM50sAA+69t
FpdjBYfvH2zDzjQRvIChzyD8ceuE5uuQqqQTXgZOIOCbsBgWljxH/brSy/tbEW2K2+9n4ZmctE31
Q+LeKlBDOLVk5XnkBXiG6R67DmFAp9f2/0eRRLDGNZ8dCGxtU6vP5wvQmC3PxptjrWJbzWO2UJ5l
dcvLtmWXA4KtDdNHDzLH4C6F5ugdsltExuRUJ0docb55wumtEIaSPeC0Hch9K1N0wq7xqifNpM18
l+660B+pAitePsyZkLPhalTb6mFt9Glzvz69nnJbabdaUKG4LKhK3f/D0aKMEJxzKcL3arfBhDEf
flEXjU4wB/0bRWrAdlLAFPPnA+I7+/FUq2Yax/Y6dXSJumL90jnGSomAs1IlX5vDJp6GahEweV0j
D7/aWoOrnjmzv8YUnlDWL6PwccsPpXl4I6kIeU+SjD7kqBdaDHZMmKh//l6eemcteitTAh+VDmXX
GZCp3vHRBfVn1E6KVaL1mnpVehDLFQfeVkaiah4OiZfrckHv67BkbwErCL9Ciq/XmT0Hi3u88V9Z
kFagjL+LqNPm+xArKa8tmLgmUjrDVhavWEkfyoysAIg61oE1s4WGnTLWlc5mPTa4WfKQzPxc+sRd
fI333YBE59A9kGMa69QWaiM4hlXbEj9CMXcO74m83vFYtWyNwUbH7EEX+0SOMrbIS8fVbND2Vzvp
eKCSWND/on3HxpSWV9h77jSpNWS622GtzJTFWTECSicEogZ6ex4BsH7p+FXsdkPHORah+IeHewx7
13iPbbNxaJBLP1QplOBCXTCGL4MZ+ej30PuIosvsb7199tBLzrfMuFC2hYV4Ta5ln2twBwujedej
g8jFZZkpstrd4P4JNP2qDYmdu40ukiiZIuESEX3ezJ8KZ7g7sehqAi+nM9+bzpQob4VOwTM9Fc4h
G75ccIW9qO94HH8bSE5sDWvYRxiqAf+a0GIyPKLvQm6rR/CSMhP0ppeBc6Ii896fj4ouK8Ij+5I1
jl2E/O+SNgjbjSNcS0esrwJoLBl6E5X+Gjg8Pb0h7pQRb660Q0LgYJ9lDzN9TKkajrNh5fWFAUyz
WMUGF7WrW1O/fjGEhSTE03qMO+ioTCNsz0ySrGGtVPMCTetHrZ8Wv7QIQApssjoC2Jnr6u/9NRQG
PEM1qJCwkaXvLGvdbHPKpWVtjkJf+dhKpQZ0UEKKBcC/+oRFW83G8tJ0UXXwAbQMqdYVOCF/SQKb
KYUV+p6ixNPCeEYlVOeqZ1FJUaO9QjcBIYAcBcquTlS6/oa4eMj/n/+3CSt7WWRhU041tNX6YM8V
hRUOAbcVASCSF00thoceti2w2ymJl3ZGIgN0ppMP5/QQscLhI73u87G9Efi40puQueHKUr21OpDz
tMNfeYdrPktkQ7/UAcdDFF0jl6I4LWuyl7M1myVRalhOWO2Zqd//MyQ8/eVMdU+liokZ/WWj7V9M
izp3CwQdjaXuTWw0pUSoaFGBO7e1CJWGNjaGv3On9O1kchz1MaOVzrQci5JSCTpGoLTCLDqZj4B9
6rjBBfA8ad8nccpIURo0Xk7kwmwi68zhy9AUmFb7SGt5HLGPIeYkRNwGu1VmgGHSE1HpDSkVwyyf
juyX0lmcI/ftNh/nT+Fu5SJDT6M39DLhd8/pQfCfCuuvU7ZVAMazjKkLdG1cZEc+W4zD3gkQGyCn
y5iLfMro4f1fHbgPglNkRnYaf+FICZ4slVNJSt0zRlfq2qALzkPMZqxlEJnP2IUISVXtzEVQlXXy
viwh+NcxOyFLZuDs9BJQFhdcLLjWAyTaMngeN3Y/EFmt8ysh8t+r4plWnUglLwhhjYT2QXMq+wXn
oV7vSxPOc6jC5/yxkRSDAqJQOo+Vqum9mCccBslOJhV9aarnRBQ8wwllJduqDM7HX6iSyQv4VeR6
VpoPNkh5vv2ZWs5KUvpaZbeANyMRi1eVGeKEzaLyQIr5fcaxfROSGqTp/4JMSoNgMZUZo5lKf4RR
m63d9RYPq6kxeS/WqXaSmV40xSbfi3K5++MU7o4eAg3UmkRGLRoo2ysg/+NSVmZFEPc2RGJTUNKT
EE9ONiRxi7ZRg+OxWiWQ8HmsDQgCc52v+C6t2Qwl0E1zJj3/IHsWcltb42WwU84jLMPyAQwiIsg1
O7gWqs571he8TIW+4hbwD8CF4zbT5833qDDHAOBpGLh8RZD248J2BLn+AdXwQHBWClRr9t0GAPlb
wUONaLhFhIR9W3ryW6ZNG7SWVk7Yw/etjJDMvuC+XYtOXr6DqdJMYDiDYAkoQcLWqcra4G24GdzB
Q1dzxkykxtCb3vHNAoWLQJtza9t81wrB4ILM0lXlI4un1CH+UEZzxyGbOZph+VjmfLaZzuFh44VC
0O58iyq4p6wCpQ8gnjBB3bSvR2HlIZ5ODvNKcVffyWSe+bz/hViUPH48ZqLUR94THsJHT30ng593
KyUET9IlBJDHSwbhPp9RdVqhsS7EJUHmXAF7E5Q5W4z0TyBu27hPwUolBbScqq1PlrCM3yQoOyrq
jBO/xWQK4RgGcSFy0qbuKZc6LnElw2CyMx+VMJUOvJ64JFkqIRWHooapfVAVY+7H09I9IECbecND
NxJLXdw31T2yy7gU69tBisYVdcj/WG3t7VEsSPij8js/ptVzbi4FGl2k6vHUPTf25Kw3fx3XH9vi
k9yFM3ATdYUHqtge+gna5i/kFmM8KXqhtzThHe04ISAbgmfpZY/Qm00f+q+4N0ppTqguFwFIdp4d
SpRSRWdMQFYOTLd3tazbKoMuK987f1m3sFvD0G9JmjsL/t5lddwNMQ7oJT/42bB8B9eoMJAtOXfL
eTeImV7tD6NpkiDkOAHPqGdbjhGQ8sV1y36F6R+rwtf0Xbh3BBqHv+Y5rarucgMF1fR44YxtkcOn
EBNP5EMXXkGKUgI4t9qQ89Vfmrhe2kJDLsoQ350m19KNeCuInpVTIDQbO0BuH5K7mhz9ibE5cbP9
vnCUiJegA2DieKS5AiUtqfoWShxglDgeM04+KKpBELKwfqTb5uv5eaBh028yeIpm2KYqhBVOL9Oz
kt3uZsP1e9JzlJJ0cOFqfslf5/TlAOombhhX0edntBE4sXyLDlXy9xkFh/wZdSMuqwfOuUdH5cju
DSQ4BbxeQSdHSNOM04EKVSv31WpEuimRxmnvf1KXqVVhi68lavCzXdEQ2XIzRQ8tb91ErWgMVWoK
B5+fL3VjynEsjrkKKLADgbt3t+f9UBqER5lv9S2h8353X2N5NtYI6HKq6ZOyvugQ2MeiBASLLEAE
c+rsYlRygs4RwZBe3P0RRO87laQcCr5LFpvV8/xSgfTzOdhjZrorpIBk5V+R+i7gs3wxPETy61be
XhrJAL1oU8eB92of5JO/to+Z6h28NR+m+QVYZNwfnvwcL3moemYWSoQfVbht65rFswGxbv4t9VSF
ZWV1TeciTKWko4Pnho7q60gtNybibG/pzIEG/YlS1qm2kL9ed1WzndsaZICpTtMP4qHn18wBm8DT
NlJ1mz8IbEXBAbss5X0CHPL86ejlWRFmk0bIQ3CElVlG9Rc8SzdNvkYxkC1IBPZ6+Li44nI3HMFL
l0U66Bgw2RvQpfLKV6ehrygM4XGAfu5BgBhrIK7HTIJxzHAz40nO4J+bNYYashktx+o9GzMgPJh7
mA2dI1I0jVW1cwi41GNKIo0R688jzdikJ4RDNIzZLK/PLGVU3wJ/T/UoqfJjgDxUpVn28uljgu0p
J1UImOXVsFdn2a+vlRw/u195+ud4GnVDEZbuuik0Q5LmlMSku8zDLu8zV03xerqmt7DSlNRhUNoY
1ucGZfJIkaGdyCxVpPOpnnDA1frkjv/CsKvfUCvGYX2yzfpL0fzyjzHLEhkuMUAnS8RLuTuLi4ur
lj4HkYKYi+o0wwUqaQBudov1GABysKaDn5a7pxaqDys8fCwBLmI2+oY/Iu+pSkJEpMyc9ukvMZwF
79V1hJxkGm/fZHt42NJflm7XLdGKkiZ4mU2kNkFHzqH6aNIk1We/CYlTRafK5s/gij86mZjwXxOR
LtglWRN+LwUzkzAbJ1pAJLRSyYPH+/uZsTVfS2Q+37JPClKdnun4xaapIuDO+VqeZAR1KVvOecXI
1SDbQwSaLRU3JkZzgWuQ/xPLq0rck9JXX37sXMR3J14mGrQe1TbUGBUORHdIDwI1t3HPE+beTsaF
Cr0EjOqayTt5R+XDDUOXXIyTUJkFaIjnDK1yWhtRuPdo64fRfbFyvjTh7PTuA0vpsQ2AGxYigUR7
g6UhQ0XlxukCkuBYvx+KO84FODRWqH6K19y636BRv9OYX4Obv9XWqrtIVexo+7y+KCpKuQhgQwie
eJRbwwtPMTln1XL1xAIOLyYMcmzcvX/BawHMJMhaug1PVl+mg2s8KobDDDMpRBtJQgg17kn9NzYw
tvWJFESmCyPL+Np912fzCVa087i0hYT5aBt3jnk4ji0ZvARhMXldaaiy6w6/21ycM/QIBY7U4bZ9
E9MMblyd6+J9XB2io8+uI3PS5IHEr4Au5ZTunPvaFiRbNaXkAN0oq5VTW3oFEOWZzhY/syVI0H8q
d60xJ6YwXigiiWlk6kMsAolGS5zMoRTQ2W9MQz7jSSqys8jH/11ixDI9gDqnpZnla4prcd/H22YK
/SeddLLiq8BrbChV2X81RXR/lfXB4Ozb/63gjZzaduVHv0hZqyNy7r2FTJxCueS7K2vg+IBVr2/F
+bJdBnZVSCDA6Xdpgrek7CrC/F4t6wr3i2M2rmzv1RaC/qY9pWUUbjtGzk0ttccuCz8cP6GNJilo
Sg5NP8kGnJYR2/gPzqJcHnb9IwK4zf4Q9mvYRIu1LTgbx1/zeClT6dTMA4lbjp0NHEQW9TwVrRAh
by4vS0RZ3cidC39yVyg69vxAVXc1iexlPMsX90iCN8zzFBi/lphatdc2uZpW9ov5UqFaa6qKAU/N
lJj0x+AhLN8Z7HTI4K6Kva9+ksIkamXEhRVmkMV7KwCNyFFpnRodiGN6cRWT1P91c+tLK+ifIZLb
IXnD9FOT7vCb3ubnfMesXVBT8xkbzXDGxuVs6D6pXhnaITnRkyU2nZxDwBYuuyKNtBbuDM3CW9Vp
dfbChmTmuj4puiMuscwgCOMkWx74h3+mN+ajAGCFT1cJtvOqUTvBSCOELdIlpHjY8bodYDGgoxpU
YGBZXZNYwA2FBanaaRf9ptO/WLOYQiY9/uxB37AhCZf3kxE35dEeYQlDJweT2Kj95NBpWxpIngs7
Qo5nVWyLjyS2+4Kal4oiVa+19qdMFbaKjQsvU58BnS2kIHhPTEKdcjiyQWr7Bx1zuZD3uO14/J0z
vpumFUhaHxhZdCqlb802z0C35anBvBO/Qo2UA2DM4a7x7T683I7I+xxCBOLj/qHZ0drY4sSQRdNS
2L3QGAsFtUAfsqjTSJ0/ob1YarhMXf6B7WSKDS1WRBK2WMyWxJomGkrEoWLZ4rcICFGnXMYY4H/H
Azfekm2ykWbb/iQLl/CQe1A02SpfvcGBVH5Bt1ahMPLOSSLzrTsOBBB8Ka6T8BF5IPXmHnsvlyuV
UM1GFSf/VgjiABWSY8xP3/3B0QkrESo/KaAuHFKIXqCuk42dFCgC9q0aEIY+tax92twRQL4TXV0e
0sJ57/LnEqXUKD9DiXpfoDet0cqjRtm3ci0ZOTzboRTDdzBQFsZw0tbtBsg2uoj8vV95FnFq9K/4
LWQSO0XJ6Yq1Oe/F1piz0Otpqi+P3qcrHJlNugTj85CJzsvG+MApBpYTIHQPIqlr8wR+lUaqyLHH
lPvLVqkPmwEGEK0oqnbWmXtNMFeaiyTfMQpohmxjiq5Hlhaa5VbmYl9vG9nYZu+4fKCJtvw008wc
TbKkY0ZCei/jz64pRXWFNIn78rP4d2SNA0XMZ6MoV7DbXBWqtz52qArwU/LXzT5nat0/KNH+rgWj
fGgbd8fIN8Ha97NSduPx8vAPgaIdLmsqlT1DxuyGKAbGg+u+M2QuZc4evHOKcVi1fOLq3nQI6evy
7TxMlLXtHdAdyd54pI3gv9jmLc06NmUo2u39u/sGJxXv7PCv8molcZbAF+1AbLHucXPnJWxWf3KD
YW/zRIu9iA62jl5zN23K7NeRnN31p9KTSSFO13KHXoUtN0GwaR4kkTcmaDEQbeETAHMwuq2i7yTY
rxNG88hAvrZhgJoF0UnICT8GJU5xxckAiIWfJtsg+kbLfEnNTiVwgHPI2oqSLi8ofvWmh4UuV28J
Abjb7TJ2uqvpowe7oRIRsyjl1Da0Z+lvz88vOxiRw+/ZcOzNlHsuDZuLWRHIyn8HLiAnZTwUT03g
V++5wVRpQVrLLFeI6Eld/NOVXQ8a84HXAjAV5olFV2eS2bBGwj7dS6rmiVyjsi+qmdbM0hqe9R8O
p88/3DZpCn30FFvf3QV+a91F2QtrQoQxe6JAqZ2qIKqX1XtbTRqs0WqfpQmvHmct07uZA+iQpbq+
K/sldQRqunqXhXnVCe2ObMYVscCQyIiQBiiRXa0L54sJYjDDj6IY6JUoZKu3I7aIuOyG66tSHgLQ
S/n/X9LaagzkOCGowzc01vm9hNFvTKsHHaUYJ6r6+/KXYRct27uL26ZYXmbiK4ExIVAmGyuEDV1o
KVlt5ey1CVBdcvI6VrWwJtiRPKJSsj25fmWVZgFWNF9LoSMeFIiDHti93/eokw9OKnFPiNA/yvwi
t/5u7LwlHQTQ5HmwOu1Vow0Y7SVzyaWsijv5xGzN3uIs52VccdRbmVYlunSONQAE85EmB40pM9n4
P1iA1QknvqNmIE11NGD+R+IgYpd+PA1pzjLtizEFteEsehsdj2d1AQxt2IJf3k8XKpR9ue1Yas1g
GHREH4szpRpjsg9STvPPzuhRnbJ0t8vvfQYupa6sUsNcYGtMp6daR6EpN4Q0+v2jmMvK9iOtWeXS
y5qleujb3JQybH2GFiiK1icEqTQUG7JGxMA/u767tZB+SSEgzLXf+kPhIvEuMBOUEcxNLMMII3Tz
ED1XlOXB+7dUGGxhUvZp0OZNHyRN8qJZ3SyXnIZu06V8aeKGXxgGJ+fyFP0Ar0fqbYzusHYpaEvB
8QW2Tm+W1uxU5woUQR93a2WfDXGOps7bfQCMR7oXSRY1+t1Tkj5vA7NOfnlvKrDt0b+0lFK+JyMQ
qEizG13BTSUYxTYCbrro/oHdIu38jSqhDeLx3RunRnbNuj8uEQWaV39AiyICSgvi/5Srjr92mXMK
yyyKM3MLR5NIGZBbOJ7UOCX0fcelZHsBwMn8oFUQrJVPplxknK4koanL169WG/X5Ggm00cjaT4w5
9tT6xFl6ZhMFH2sajD7FhSangvlLAkHBz9MDUy4CpVEG7Ku6hiCouj1o831yt8QBKOcjPZliMOEw
PiH3prtGiyTcfu080OFdX6wsGkZ2MJJ+dV5wXuohg5JKwhyMuGOUx3KT3gaM4v3LJMrPQLEygFBP
FEesBkZWUqopqt5NS8Q1mex7GRCsqRIcoS6M9SQm5T2nxcINtxVr/XcxZ2IZArqjkTlD2YRtdX/s
NRCB5hubt0x4JGQg7aWcmgThfmzJeh7HY7kfm6NgeK8NRnPKgcyPtO71txytcC465XzS0Kc9LOOQ
YnRjhqnZiV3r/zQ9tC6NPo0Qaj+LUR/7aOSHvDIgffJ97l65ANTR8c7Rpl44hiDYdMO6gZ0cJklq
VxxpvM07qvYiwFPKvgZsqBSuROiSHGwIfEInlX1i2ajDS6pzvYIRNE2XfX6Ap9UjUDLS99T33i7A
eGZlgVPyEDgMKk7/40qDOU4esTKHdtX/ul7y4BTbNaNnxGANbplYveQodgf/K+78nHt/Gw==
`protect end_protected
|
-- -a --ieee=synopsis -fexplicit -Wc,-m32 -Wa,--32
-- -e -Wa,--32 -Wl,-m32
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dmem is
port (a: in std_logic_vector(31 downto 0);
wd: in std_logic_vector(31 downto 0);
clk, we: in std_logic;
rd: out std_logic_vector(31 downto 0));
end entity;
architecture arq_dmem of dmem is
type mem is array (0 to 63) of std_logic_vector(31 downto 0);
begin
process(clk)
variable my_mem: mem;
variable address: std_logic_vector(5 downto 0);
variable pos_a: integer;
begin
for pos in 0 to 63 loop --Inicializo mi memoria
my_mem(pos) := std_logic_vector(to_unsigned(pos, 32));
end loop;
if clk'EVENT and clk='1' then
address := a(7 downto 2);
pos_a := to_integer(unsigned(address));
if we='1' then
my_mem(pos_a) := wd;
rd <= wd;
else
rd <= my_mem(pos_a);
end if;
end if;
end process;
end architecture;
|
-- **********************************************
-- * Banco de pruebas para SRAM de doble puerto *
-- **********************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_dp_tb is
generic(
DIR_ANCHO : integer:=2;
DATOS_ANCHO: integer:=8
);
end sram_dp_tb;
architecture arq_bp of sram_dp_tb is
constant T: time := 20 ns; -- Período del Reloj
signal clk, we: std_logic;
signal w_dir, r_dir: std_logic_vector(DIR_ANCHO-1 downto 0);
signal d, q: std_logic_vector(DATOS_ANCHO-1 downto 0);
begin
-- =============
-- Instanciación
-- =============
unidad_sram_dp: entity work.sram_dp(arq_dir_reg)
generic map(DIR_ANCHO => DIR_ANCHO,
DATOS_ANCHO => DATOS_ANCHO)
port map(
clk => clk,
we => we,
w_dir => w_dir,
r_dir => r_dir,
d => d,
q => q
);
-- =====
-- Reloj
-- =====
process begin
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
end process;
-- ===============
-- Otros estímulos
-- ===============
process begin
-- Inicialización de la primera dirección en 0
we <= '1'; -- Activar escritura
w_dir <= (others => '0');
r_dir <= (others => '0');
d <= (others => '0');
wait until falling_edge(clk);
-- Escribir en la última dirección (la escritura áun está activada)
w_dir <= (others => '1');
d <= (others => '1'); -- Escribir el valor máximo
wait until falling_edge(clk);
-- Escribir en la tercera dirección (la escritura áun está activada)
w_dir <= "10";
d <= (others => '0');
wait until falling_edge(clk);
-- Leer la última dirección
we <= '0'; -- Desactivar escritura
r_dir <= (others => '1');
d <= "00001111"; -- no debería almacenarse en la dirección w_dir anterior
wait until falling_edge(clk);
-- Leer la tercera dirección
-- (la escritura no está activada)
r_dir <= "10";
wait until falling_edge(clk);
-- Sobrescribir y leer la memoria completa
for i in 0 to 2**DIR_ANCHO-1 loop
we <= '1'; -- Escritura activada
w_dir <= std_logic_vector(to_unsigned(i, DIR_ANCHO));
d <= std_logic_vector(to_unsigned(i+8, DATOS_ANCHO));
r_dir <= std_logic_vector(to_unsigned(i, DIR_ANCHO));
wait until falling_edge(clk);
end loop;
-- Leer toda la memoria
for i in 0 to 2**DIR_ANCHO-1 loop
we <= '0'; -- Escritura desactivada
r_dir <= std_logic_vector(to_unsigned(i, DIR_ANCHO));
-- En w_dir no debería almacenarse d
w_dir <= std_logic_vector(to_unsigned(i, DIR_ANCHO));
d <= std_logic_vector(to_unsigned(i+4, DATOS_ANCHO));
wait until falling_edge(clk);
end loop;
-- ===================
-- Terminar simulación
-- ===================
assert false
report "Simulación Completada"
severity failure;
end process;
end arq_bp;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity counter is
port ( clk, reset : in bit; count : out natural );
end entity counter;
--------------------------------------------------
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
loop
wait until clk = '1' or reset = '1';
exit when reset = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
-- at this point, reset = '1'
count_value := 0;
count <= count_value;
wait until reset = '0';
end loop;
end process incrementer;
end architecture behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity counter is
port ( clk, reset : in bit; count : out natural );
end entity counter;
--------------------------------------------------
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
loop
wait until clk = '1' or reset = '1';
exit when reset = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
-- at this point, reset = '1'
count_value := 0;
count <= count_value;
wait until reset = '0';
end loop;
end process incrementer;
end architecture behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity counter is
port ( clk, reset : in bit; count : out natural );
end entity counter;
--------------------------------------------------
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
loop
wait until clk = '1' or reset = '1';
exit when reset = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
-- at this point, reset = '1'
count_value := 0;
count <= count_value;
wait until reset = '0';
end loop;
end process incrementer;
end architecture behavior;
|
-------------------------------------------------------------------------------
-- File : bmp_sink.vhd
-- Author : mr-kenhoff
-------------------------------------------------------------------------------
-- Description:
-- Takes a data stream and saves it to a bitmap image
-- Target: Simulator
-- Dependencies: bmp_pkg.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bmp_pkg.all;
entity bmp_sink is
generic (
FILENAME : string;
SEQUENCE : string := "TRUE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
val_i : in std_logic;
dat_i : in std_logic_vector(23 downto 0);
rdy_o : out std_logic := '1';
eol_i : in std_logic;
eof_i : in std_logic;
halt_i : in std_logic
);
end entity;
architecture behavioural of bmp_sink is
signal x : natural := 0;
signal y : natural := 0;
signal iteration : integer := 0;
begin
rdy_o <= not halt_i when rising_edge(clk_i);
sink_process : process( clk_i )
variable sink_bmp : bmp_ptr;
variable sink_pix : bmp_pix;
variable is_bmp_created : boolean := false;
variable is_bmp_saved : boolean := false;
begin
-- Create bitmap on startup
if is_bmp_created = false then
sink_bmp := new bmp;
is_bmp_created := true;
end if;
if rising_edge( clk_i ) then
if rst_i = '1' then
x <= 0;
y <= 0;
else
if val_i = '1' and halt_i = '0' then
sink_pix.r := dat_i(23 downto 16);
sink_pix.g := dat_i(15 downto 8);
sink_pix.b := dat_i(7 downto 0);
bmp_set_pix( sink_bmp, x, y, sink_pix );
if eol_i = '1' then
x <= 0;
if eof_i = '1' then
y <= 0;
-- Frame completed. Save to bitmap..
if SEQUENCE = "FALSE" then
if is_bmp_saved = false then
bmp_save( sink_bmp, FILENAME & ".bmp" );
is_bmp_saved := true;
end if;
elsif SEQUENCE = "TRUE" then
bmp_save( sink_bmp, FILENAME & "_" & INTEGER'IMAGE(iteration) & ".bmp" );
is_bmp_saved := true;
end if;
iteration <= iteration + 1;
else
y <= y + 1;
end if;
else
x <= x + 1;
end if;
end if;
end if;
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 01-03-2017
-- Module Name: dff.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity dff is
port (
d, clk : in std_logic;
q : out std_logic);
end entity;
architecture arch_1_dff of dff is
begin
process
begin
wait until clk = '1';
q <= d;
end process;
end architecture;
architecture arch_2_dff of dff is
begin
process (clk)
begin
if clk'event and clk = '1' then
q <= d;
end if;
end process;
end architecture;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_10_alut.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package alu_types is
subtype alu_func is std_ulogic_vector(3 downto 0);
constant alu_add : alu_func := "0000";
constant alu_addu : alu_func := "0001";
constant alu_sub : alu_func := "0010";
constant alu_subu : alu_func := "0011";
end package alu_types;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_10_alut.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package alu_types is
subtype alu_func is std_ulogic_vector(3 downto 0);
constant alu_add : alu_func := "0000";
constant alu_addu : alu_func := "0001";
constant alu_sub : alu_func := "0010";
constant alu_subu : alu_func := "0011";
end package alu_types;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_10_alut.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package alu_types is
subtype alu_func is std_ulogic_vector(3 downto 0);
constant alu_add : alu_func := "0000";
constant alu_addu : alu_func := "0001";
constant alu_sub : alu_func := "0010";
constant alu_subu : alu_func := "0011";
end package alu_types;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
entity cronometro is
port (
-- Entradas
startStop: in std_logic;
puestaCero: in std_logic;
clk: in std_logic;
rst: in std_logic;
-- Salidas
rightSegs: out std_logic_vector(7 downto 0);
leftSegs: out std_logic_vector(7 downto 0);
decimasSegs: out std_logic_vector(7 downto 0);
puntoDec: out std_logic
);
end cronometro;
architecture Behavioral of cronometro is
signal ssDebounced,ssDebFallEdge,ssDebRiseEdge: std_logic;
signal pODebounced,pODebFallEdge,pODebRiseEdge: std_logic;
signal t: std_logic;
signal salidaCont5kk: std_logic_vector(22 downto 0);
signal salidaContDecimas, salidaContUnidades,salidaContDecenas: std_logic_vector(3 downto 0);
signal cuentaDecimas, cuentaUnidades, cuentaDecenas: std_logic;
signal cs1 : std_logic_vector( 22 downto 0 );
signal cs2,cs3,cs4 : std_logic_vector( 3 downto 0 );
signal lit1,lit2,lit3: std_logic;
component debouncer
port(rst: in std_logic;
clk: in std_logic;
x: in std_logic;
xDeb: out std_logic;
xDebFallingEdge: out std_logic;
xDebRisingEdge: out std_logic);
end component;
component binToSeg is
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end component;
begin
-- ELIMINACION DE REBOTES EN LOS PUSHBUTTONS
debouncerStartStop: debouncer port map (rst,clk,startStop,ssDebounced,ssDebFallEdge,ssDebRiseEdge);
debouncerPuestaCero: debouncer port map (rst,clk,puestaCero,pODebounced,pODebFallEdge,pODebRiseEdge);
-- CONTADORES
contMod5kk:
process( clk, cs1, rst, pODebFallEdge, ssDebFallEdge )
begin
salidaCont5kk <= cs1;
if rst = '0' then
cs1 <= conv_std_logic_vector( 0 , 23 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs1 <= conv_std_logic_vector( 0 , 23 );
elsif t = '1' then
if cs1 = conv_std_logic_vector( 4999999 , 23 ) then
cs1 <= conv_std_logic_vector( 0 , 23 );
else
cs1 <= cs1 + 1;
end if;
end if;
end if;
end process;
-- contDecimas cuenta cuando se tenga 4.999.999 = 10011000100101100111111 en cont5Millones
cuentaDecimas <= salidaCont5kk(22) and salidaCont5kk(19) and salidaCont5kk(18) and salidaCont5kk(14) and salidaCont5kk(11) and
salidaCont5kk(9) and salidaCont5kk(8) and salidaCont5kk(5) and salidaCont5kk(4) and salidaCont5kk(3) and
salidaCont5kk(2) and salidaCont5kk(1) and salidaCont5kk(0);
contDecimas:
process( clk, cs2, rst, pODebFallEdge, cuentaDecimas )
begin
salidaContDecimas <= cs2;
if rst = '0' then
cs2 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs2 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaDecimas = '1' then
if cs2 = conv_std_logic_vector( 9 , 4 ) then
cs2 <= conv_std_logic_vector( 0 , 4 );
else
cs2 <= cs2 + 1;
end if;
end if;
end if;
end process;
-- contUnidades cuenta cuando se tenga 9 = 1001 en contDecimas
cuentaUnidades <= (salidaContDecimas(3) and salidaContDecimas(0)) and cuentaDecimas;
contUnidades:
process( clk, cs3, rst, pODebFallEdge, cuentaUnidades )
begin
salidaContUnidades <= cs3;
if rst = '0' then
cs3 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs3 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaUnidades = '1' then
if cs3 = conv_std_logic_vector( 9 , 4 ) then
cs3 <= conv_std_logic_vector( 0 , 4 );
else
cs3 <= cs3 + 1;
end if;
end if;
end if;
end process;
cuentaDecenas <= (salidaContUnidades(3) and salidaContUnidades(0)) and (cuentaDecimas and cuentaUnidades);
contDecenas:
process( clk, cs4, rst, pODebFallEdge, cuentaDecenas )
begin
salidaContDecenas <= cs4;
if rst = '0' then
cs4 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs4 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaDecenas = '1' then
if cs4 = conv_std_logic_vector( 5 , 4 ) then
cs4 <= conv_std_logic_vector( 0 , 4 );
else
cs4 <= cs4 + 1;
end if;
end if;
end if;
end process;
-- BIESTABLE T
-- Usamos el flanco de bajada (fall) porque la placa tiene logica negativa
biestableT:
process(clk)
begin
if (rst = '0') then
t <= '0';
elsif (clk'event and clk='1') then
if (ssDebFallEdge = '1') then
t <= not (t);
end if;
end if;
end process;
parpadeoPuntoDecimal:
process(salidaContDecimas)
begin
lit1 <= not salidaContDecimas(3) and not salidaContDecimas(2);
lit2 <= not salidaContDecimas(3) and not salidaContDecimas(1) and not salidaContDecimas(0);
lit3 <= lit1 or lit2;
if (lit3 = '1') then
puntoDec <= '1';
else
puntoDec <= '0';
end if;
end process;
-- DISPLAYS 8 SEGMENTOS
decenasSeg: binToSeg port map (salidaContDecenas,leftSegs);
unidadesSeg: binToSeg port map (salidaContUnidades,rightSegs);
deciSeg: binToSeg port map (salidaContDecimas,decimasSegs);
end Behavioral;
-- x3 x2 x1 x0 z
--------------------
--0 0 0 0 0 1
--1 0 0 0 1 1
--2 0 0 1 0 1
--3 0 0 1 1 1
--4 0 1 0 0 1
--5 0 1 0 1 0
--6 0 1 1 0 0
--7 0 1 1 1 0
--8 1 0 0 0 0
--9 1 0 0 1 0
-- Mapa de Karnaugh ==> FLASH = (¬ x3)(¬ x2) + (¬ x3)(¬ x1)(¬ x0)
|
--------------------------------------------------------------------------------
-- MIPS I CPU - Instruction Set --
--------------------------------------------------------------------------------
-- Type definitions of the MIPS I instruction (sub-)set and some convenience --
-- functions to convert binary operation representations to symbolic --
-- equivalents. --
-- --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mips1 is
-----------------------------------------------------------------------------
-- OP Codes --
-----------------------------------------------------------------------------
type op_t is (
AD, -- Operations with AluOp
RI, -- Additional Branches
J, -- Jump
JAL, -- Jump And Link to $ra
BEQ, -- Branch On Equal
BNE, -- Branch On Not Equal
BLEZ, -- Branch Less Equal Zero
BGTZ, -- Branch Greater Than Zero
ADDI, -- Add Immediate
ADDIU, -- Add Immediate Unsigned
SLTI, -- SLT Immediate
SLTIU, -- SLT Immediate Unsigned
ANDI, -- And Immediate
ORI, -- Or Immediate
XORI, -- Xor Immediate
LUI, -- Load Upper Immediate
LB, -- Load Byte
LH, -- Load Half Word
LW, -- Load Word
LBU, -- Load Byte Unsigned
LHU, -- Load Half Word Unsigned
SB, -- Store Byte
SH, -- Store Half Word
SW, -- Store Word
CP0, -- Co-Processor 0 Operations
ERR -- Unknown OP
);
function op(i : std_logic_vector) return op_t;
-----------------------------------------------------------------------------
-- ALU OP Codes --
-----------------------------------------------------------------------------
-- In this implementation of the MIPS I instruction set, ADD, ADDU and --
-- SUB, SUBU cause indentical behaviour. This means that ADDU and SUBU do --
-- NOT trap on overflow. --
-----------------------------------------------------------------------------
type alu_op_t is (
ADD, -- Addition
ADDU, -- Add Unsigned
SUB, -- Subtraction
SUBU, -- Subtract Unsigned
AND0, -- Logic and
OR0, -- Logic or
NOR0, -- Logic nor
XOR0, -- Logic xor
SLT, -- Set On Less Than
SLTU, -- SLT Unsigned
SLL0, -- Shift Left Logical
SLLV, -- SLL Variable
SRA0, -- Shift Right Arith
SRAV, -- SRA Variable
SRL0, -- Shift Right Logical
SRLV, -- SRL Variable
JALR, -- Jump And Link Reg
JR, -- Jump Reg
MFCP0, -- Move From Co-Processor 0
MTCP0, -- Move To Co-Processor 0
RFE, -- Restore From Exception
ERR -- Unknown ALU OP
);
-- Convert ALU Op bit pattern into its symbolic representation.
function aluop(i : std_logic_vector) return alu_op_t;
-----------------------------------------------------------------------------
-- REGIMM Codes --
-----------------------------------------------------------------------------
type rimm_op_t is (
BGEZ, -- Branch Greater Equal 0
BGEZAL, -- BGEZ And Link
BLTZ, -- Branch Less Than 0
BLTZAL, -- BLTZ And Link
ERR -- Unknown RIMM OP
);
-- Convert Reg Immediate Op bit pattern into its symbolic representation.
function rimmop(i : std_logic_vector) return rimm_op_t;
-----------------------------------------------------------------------------
-- CP0 Codes --
-----------------------------------------------------------------------------
type cp0_op_t is (
MFCP0, -- Move From Co-Processor 0
MTCP0, -- Move To Co-Processor 0
RFE, -- Restore From Exception
ERR -- Unknown CP0 OP
);
type cp0_reg_t is (
SR, -- Status Register
CAUSE, -- Cause Register
EPC, -- EPC
ERR -- Unknown CP0 REG
);
-- Convert CP0 Op and Reg Addresses bit patterns into its symbolic
-- representation.
function cp0op(i : std_logic_vector) return cp0_op_t;
function cp0reg(i : std_logic_vector) return cp0_reg_t;
end mips1;
package body mips1 is
function op(i : std_logic_vector) return op_t is
begin
case i(31 downto 26) is
when "000000" => return AD; -- Operations with AluOp
when "000001" => return RI; -- Additional Branches
when "000010" => return J; -- Jump
when "000011" => return JAL; -- Jump And Link to $ra
when "000100" => return BEQ; -- Branch On Equal
when "000101" => return BNE; -- Branch On Not Equal
when "000110" => return BLEZ; -- Branch Less Equal Zero
when "000111" => return BGTZ; -- Branch Greater Than Zero
when "001000" => return ADDI; -- Add Immediate
when "001001" => return ADDIU; -- Add Immediate Unsigned
when "001010" => return SLTI; -- SLT Immediate
when "001011" => return SLTIU; -- SLT Immediate Unsigned
when "001100" => return ANDI; -- And Immediate
when "001101" => return ORI; -- Or Immediate
when "001110" => return XORI; -- Xor Immediate
when "001111" => return LUI; -- Load Upper Immediate
when "100000" => return LB; -- Load Byte
when "100001" => return LH; -- Load Half Word
when "100011" => return LW; -- Load Word
when "100100" => return LBU; -- Load Byte Unsigned
when "100101" => return LHU; -- Load Half Word Unsigned
when "101000" => return SB; -- Store Byte
when "101001" => return SH; -- Store Half Word
when "101011" => return SW; -- Store Word
when "010000" => return CP0; -- Co-Processor 0 Operations
when others => return ERR; -- Unknown OP
end case;
end op;
function aluop(i : std_logic_vector) return alu_op_t is
begin
case i(5 downto 0) is
when "100000" => return ADD; -- Addition
when "100001" => return ADDU; -- Add Unsigned
when "100010" => return SUB; -- Subtract
when "100011" => return SUBU; -- Subtract Unsigned
when "100100" => return AND0; -- Logic and
when "100101" => return OR0; -- Logic or
when "100111" => return NOR0; -- Logic nor
when "100110" => return XOR0; -- Logic xor
when "101010" => return SLT; -- Set On Less Than
when "101011" => return SLTU; -- SLT Unsigned
when "000000" => return SLL0; -- Shift Left Logical
when "000100" => return SLLV; -- SLL Variable
when "000011" => return SRA0; -- Shift Right Arith
when "000111" => return SRAV; -- SRA Variable
when "000010" => return SRL0; -- Shift Right Logical
when "000110" => return SRLV; -- SRL Variable
when "001001" => return JALR; -- Jump And Link Reg
when "001000" => return JR; -- Jump Reg
when others => return ERR; -- Unknown ALU OP
end case;
end aluop;
function rimmop(i : std_logic_vector) return rimm_op_t is
begin
case i(20 downto 16) is
when "00001" => return BGEZ; -- Branch Greater Equal 0
when "10001" => return BGEZAL; -- BGEZ And Link
when "00000" => return BLTZ; -- Branch Less Than 0
when "10000" => return BLTZAL; -- BLTZ And Link
when others => return ERR; -- Unknown RIMM OP
end case;
end rimmop;
function cp0op(i : std_logic_vector) return cp0_op_t is
begin
case i(25 downto 21) is
when "00000" => return MFCP0; -- Move From Co-Processor 0
when "00100" => return MTCP0; -- Move To Co-Processor 0
when "10000" => return RFE; -- Restore From Exception
when others => return ERR; -- Unknown CP0 OP
end case;
end cp0op;
function cp0reg(i : std_logic_vector) return cp0_reg_t is
begin
case i(4 downto 0) is
when "01100" => return SR; -- Status Register
when "01101" => return CAUSE; -- Cause Register
when "01110" => return EPC; -- EPC
when others => return ERR; -- Unknown CP0 REG
end case;
end cp0reg;
end mips1; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_14 is
end entity inline_14;
----------------------------------------------------------------
architecture test of inline_14 is
signal PC, functional_next_PC, equivalent_next_PC : integer := 0;
begin
block_3_p : block is
port ( next_PC : out integer );
port map ( next_PC => functional_next_PC );
begin
-- code from book:
PC_incr : next_PC <= PC + 4 after 5 ns;
-- end of code from book
end block block_3_p;
----------------
block_3_q : block is
port ( next_PC : out integer );
port map ( next_PC => equivalent_next_PC );
begin
-- code from book:
PC_incr : process is
begin
next_PC <= PC + 4 after 5 ns;
wait on PC;
end process PC_incr;
-- end of code from book
end block block_3_q;
----------------
stimulus : process is
begin
for i in 1 to 10 loop
PC <= i after 20 ns;
wait for 20 ns;
end loop;
wait;
end process stimulus;
verifier :
assert functional_next_PC = equivalent_next_PC
report "Functional and equivalent models give different results";
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_14 is
end entity inline_14;
----------------------------------------------------------------
architecture test of inline_14 is
signal PC, functional_next_PC, equivalent_next_PC : integer := 0;
begin
block_3_p : block is
port ( next_PC : out integer );
port map ( next_PC => functional_next_PC );
begin
-- code from book:
PC_incr : next_PC <= PC + 4 after 5 ns;
-- end of code from book
end block block_3_p;
----------------
block_3_q : block is
port ( next_PC : out integer );
port map ( next_PC => equivalent_next_PC );
begin
-- code from book:
PC_incr : process is
begin
next_PC <= PC + 4 after 5 ns;
wait on PC;
end process PC_incr;
-- end of code from book
end block block_3_q;
----------------
stimulus : process is
begin
for i in 1 to 10 loop
PC <= i after 20 ns;
wait for 20 ns;
end loop;
wait;
end process stimulus;
verifier :
assert functional_next_PC = equivalent_next_PC
report "Functional and equivalent models give different results";
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_14 is
end entity inline_14;
----------------------------------------------------------------
architecture test of inline_14 is
signal PC, functional_next_PC, equivalent_next_PC : integer := 0;
begin
block_3_p : block is
port ( next_PC : out integer );
port map ( next_PC => functional_next_PC );
begin
-- code from book:
PC_incr : next_PC <= PC + 4 after 5 ns;
-- end of code from book
end block block_3_p;
----------------
block_3_q : block is
port ( next_PC : out integer );
port map ( next_PC => equivalent_next_PC );
begin
-- code from book:
PC_incr : process is
begin
next_PC <= PC + 4 after 5 ns;
wait on PC;
end process PC_incr;
-- end of code from book
end block block_3_q;
----------------
stimulus : process is
begin
for i in 1 to 10 loop
PC <= i after 20 ns;
wait for 20 ns;
end loop;
wait;
end process stimulus;
verifier :
assert functional_next_PC = equivalent_next_PC
report "Functional and equivalent models give different results";
end architecture test;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_acache
-- File: mmu_acache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Interface module between (MMU,I/D cache controllers) and Amba AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_acache is
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
mcmmi : in memory_mm_in_type;
mcmmo : out memory_mm_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_acache is
type reg_type is record -- cache control register type
bg : std_logic; -- bus grant
bo : std_logic_vector(1 downto 0); -- bus owner
ba : std_logic; -- bus active
lb : std_ulogic; -- last burst cycle
retry : std_logic; -- retry/split pending
retry2 : std_ulogic; -- retry/split pending
werr : std_logic; -- write error
hlocken : std_ulogic; -- ready to perform locked transaction
hcache : std_logic; -- cacheable access
nba : std_ulogic;
nbo : std_logic_vector(1 downto 0); -- bus owner
end record;
type reg2_type is record
reqmsk : std_logic_vector(2 downto 0);
hclken2 : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : reg_type := (
bg => '0',
bo => (others => '0'),
ba => '0',
lb => '0',
retry => '0',
retry2 => '0',
werr => '0',
hlocken => '0',
hcache => '0',
nba => '0',
nbo => (others => '0')
);
constant R2RES : reg2_type := (
reqmsk => (others => '0'), hclken2 => '0'
);
constant L3DI :integer := GAISLER_LEON3
;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, L3DI, 0, LEON3_VERSION, 0),
others => zero32);
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
function dec_fixed(haddr : std_logic_vector(3 downto 0);
cached : integer)
return std_ulogic is
begin
if (cached /= 0) then return ctbl(conv_integer(haddr(3 downto 0)));
else return('1'); end if;
end;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
begin
comb : process(ahbi, r, rst, mcii, mcdi, mcmmi, ahbso, hclken, r2)
variable v : reg_type;
variable v2 : reg2_type;
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_logic; -- read/write
variable hlock : std_logic; -- bus lock
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_logic; -- bus request
variable iready, dready, mmready : std_logic;
variable igrant, dgrant, mmgrant : std_logic;
variable iretry, dretry, mmretry : std_logic;
variable ihcache, dhcache, mmhcache, dec_hcache : std_logic;
variable imexc, dmexc, mmmexc : std_logic;
variable dreq : std_logic;
variable nbo : std_logic_vector(1 downto 0);
variable su, nb, bo_icache : std_ulogic;
variable scanen : std_ulogic;
variable vreqmsk: std_ulogic;
variable burst : std_ulogic;
begin
-- initialisation
htrans := HTRANS_IDLE;
v := r; v.werr := '0'; v2 := r2;
iready := '0'; dready := '0'; mmready := '0';
igrant := '0'; dgrant := '0'; mmgrant := '0';
imexc := '0'; dmexc := '0'; mmmexc := '0'; hlock := '0';
iretry := '0'; dretry := '0'; mmretry := '0';
ihcache := '0'; dhcache := '0'; mmhcache := '0'; su := '0';
if (r.bo = "00") then bo_icache := '1'; else bo_icache := '0'; end if;
haddr := (others => '0');
hwrite := '0';
hsize := (others => '0');
hlock := '0';
hburst := (others => '0');
if ahbi.hready = '1' then v.lb := '0'; end if;
if scantest = 1 then scanen := ahbi.scanen; else scanen := '0'; end if;
v.retry2 := (r.retry or r.retry2) and not (r.ba and not r.retry);
vreqmsk := orv(r2.reqmsk);
-- generate AHB signals
dreq := mcdi.req;
hwdata := mcdi.data;
hbusreq := '0';
if (mcii.req = '1') and ((clk2x = 0) or (r2.reqmsk(2) = '1')) and (r.hlocken = '0') and
not (( ((r.ba and dreq) = '1') and (r.bo = "01")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "00";
hbusreq := '1'; burst := mcii.burst;
htrans := HTRANS_NONSEQ;
elsif (dreq = '1') and ((clk2x = 0) or (r2.reqmsk(1) = '1')) and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "01";
hbusreq := '1'; burst := mcdi.burst;
if (not mcdi.lock or r.hlocken) = '1' then htrans := HTRANS_NONSEQ; end if;
elsif (mcmmi.req = '1') and ((clk2x = 0) or (r2.reqmsk(0) = '1')) and (r.hlocken = '0') and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and dreq) = '1') and (r.bo = "01"))) then
nbo := "10";
hbusreq := '1'; burst := '0';
htrans := HTRANS_NONSEQ;
else
nbo := "11"; burst := '0';
end if;
-- dont change bus master if we have started driving htrans
if r.nba = '1' then
nbo := r.nbo; hbusreq := '1'; htrans := HTRANS_NONSEQ;
end if;
-- dont change bus master on retry
if (r.retry2 and not r.ba) = '1' then
nbo := r.bo; hbusreq := '1'; htrans := HTRANS_NONSEQ;
end if;
dec_hcache := ahb_slv_dec_cache(mcdi.address, ahbso, cached);
if nbo = "10" then
haddr := mcmmi.address; hwrite := not mcmmi.read; hsize := '0' & mcmmi.size;
hlock := mcmmi.lock;
htrans := HTRANS_NONSEQ; hburst := HBURST_SINGLE;
if (mcmmi.req and r.bg and ahbi.hready and not r.retry) = '1'
then mmgrant := '1'; v.hcache := dec_fixed(haddr(31 downto 28), cached); end if;
elsif nbo = "00" then
haddr := mcii.address; hwrite := '0'; hsize := HSIZE_WORD; hlock := '0';
su := mcii.su;
if ((mcii.req and r.ba) = '1') and (r.bo = "00") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
if (((ilinesize = 4) and haddr(3 downto 2) = "10")
or ((ilinesize = 8) and haddr(4 downto 2) = "110")) and (ahbi.hready = '1')
then v.lb := '1'; end if;
end if;
if mcii.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (mcii.req and r.bg and ahbi.hready and not r.retry) = '1'
then igrant := '1'; v.hcache := dec_fixed(haddr(31 downto 28), cached); end if;
elsif nbo = "01" then
haddr := mcdi.address; hwrite := not mcdi.read; hsize := '0' & mcdi.size;
hlock := mcdi.lock;
if mcdi.asi /= "1010" then su := '1'; else su := '0'; end if; --ASI_UDATA
if mcdi.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if ((dreq and r.ba) = '1') and (r.bo = "01") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
hburst := HBURST_INCR;
end if;
if (dreq and r.bg and ahbi.hready and not r.retry) = '1'
then dgrant := (not mcdi.lock or r.hlocken) or r.retry2; v.hcache := dec_hcache; end if;
end if;
if (hclken = '1') or (clk2x = 0) then
if (r.ba = '1') and ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT))
then v.retry := not ahbi.hready; else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if r.bo = "10" then
hwdata := mcmmi.data;
if r.ba = '1' then
mmhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => mmready := '1';
when HRESP_RETRY | HRESP_SPLIT=> mmretry := '1';
when others => mmready := '1'; mmmexc := '1'; v.werr := not mcmmi.read;
end case;
end if;
end if;
elsif r.bo = "00" then
if r.ba = '1' then
ihcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => iready := '1';
when HRESP_RETRY | HRESP_SPLIT=> iretry := '1';
when others => iready := '1'; imexc := '1';
end case;
end if;
end if;
elsif r.bo = "01" then
if r.ba = '1' then
dhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => dready := '1';
when HRESP_RETRY | HRESP_SPLIT=> dretry := '1';
when others => dready := '1'; dmexc := '1'; v.werr := not mcdi.read;
end case;
end if;
end if;
hlock := mcdi.lock or ((r.retry or (r.retry2 and not r.ba)) and r.hlocken);
end if;
if nbo = "01" and ((hsize = "011") or ((mcdi.read and mcdi.cache) = '1')) then
hsize := "010";
end if;
if (r.bo = "01") and (hlock = '1') then nbo := "01"; end if;
if ahbi.hready = '1' then
if r.retry = '0' then v.bo := nbo; end if;
v.bg := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else v.ba := '0'; end if;
v.hlocken := hlock and ahbi.hgrant(hindex);
if (clk2x /= 0) then
igrant := igrant and vreqmsk;
dgrant := dgrant and vreqmsk;
mmgrant := mmgrant and vreqmsk;
if (r.bo = nbo) then v.ba := v.ba and vreqmsk; end if;
end if;
end if;
if hburst = HBURST_SINGLE then nb := '1'; else nb := '0'; end if;
v.nbo := nbo; v.nba := orv(htrans) and not v.ba;
-- parity generation
if (clk2x /= 0) then
v2.hclken2 := hclken;
if hclken = '1' then
v2.reqmsk := mcii.req & mcdi.req & mcmmi.req;
if (clk2x > 8) and (r2.hclken2 = '1') then v2.reqmsk := "111"; end if;
end if;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.bg := '0'; v.bo := "00"; v.ba := '0'; v.retry := '0'; v.werr := '0'; v.lb := '0';
v.hcache := '0'; v.hlocken := '0'; v.nba := '0'; v.nbo := "00";
v.retry2 := '0';
end if;
-- drive ports
ahbo.haddr <= haddr ;
ahbo.htrans <= htrans;
-- ahbo.hbusreq <= hbusreq and not r.lb and not ((((not bo_icache) and r.ba) or nb) and r.bg);
-- ahbo.hbusreq <= hbusreq and not r.lb and not((not burst) and r.bg);
ahbo.hbusreq <= hbusreq and (not r.lb or orv(nbo)) and (burst or not r.bg);
ahbo.hwdata <= ahbdrivedata(hwdata);
ahbo.hlock <= hlock;
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hindex <= hindex;
if nbo = "00" then ahbo.hprot <= "11" & su & '0';
else ahbo.hprot <= "11" & su & '1'; end if;
mcio.grant <= igrant;
mcio.ready <= iready;
mcio.mexc <= imexc;
mcio.retry <= iretry;
mcio.cache <= ihcache;
mcdo.grant <= dgrant;
mcdo.ready <= dready;
mcdo.mexc <= dmexc;
mcdo.retry <= dretry;
mcdo.werr <= r.werr;
mcdo.cache <= dhcache;
mcdo.ba <= r.ba;
mcdo.bg <= r.bg and not v.bo(1);
mcmmo.grant <= mmgrant;
mcmmo.ready <= mmready;
mcmmo.mexc <= mmmexc;
mcmmo.retry <= mmretry;
mcmmo.werr <= r.werr;
mcmmo.cache <= mmhcache;
mcio.scanen <= scanen;
mcdo.scanen <= scanen;
mcdo.testen <= ahbi.testen;
rin <= v; r2in <= v2;
end process;
mcio.data <= ahbreadword(ahbi.hrdata);
mcdo.data <= ahbreadword(ahbi.hrdata);
mcmmo.data <= ahbreadword(ahbi.hrdata);
ahbo.hirq <= (others => '0');
ahbo.hconfig <= hconfig;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
reg2gen : if (clk2x /= 0) generate
reg2 : process(clk)
begin
if rising_edge(clk) then
r2 <= r2in;
if RESET_ALL and (rst = '0') then r2 <= R2RES; end if;
end if;
end process;
end generate;
noreg2gen : if (clk2x = 0) generate
r2.reqmsk <= "000";
end generate;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
-- Flipflop-based N-bit register
entity REGISTER_FDE is
generic (
N: integer := 1
);
port (
DIN: in std_logic_vector(N-1 downto 0); -- Data in
ENABLE: in std_logic; -- Enable
CLK: in std_logic; -- Clock
RESET: in std_logic; -- Reset
DOUT: out std_logic_vector(N-1 downto 0) -- Data out
);
end REGISTER_FDE;
-- Architectures
architecture ASYNCHRONOUS of REGISTER_FDE is
component FLIPFLOP
port (
D: in std_logic;
ENABLE : in std_logic;
CK: in std_logic;
RESET: in std_logic;
Q: out std_logic
);
end component;
signal INT_OUT : std_logic_vector(N-1 downto 0);
begin
REG_GEN_A : for i in 0 to N-1 generate
ASYNC_REG : FLIPFLOP
port map(DIN(i),ENABLE, CLK, RESET, INT_OUT(i));
end generate;
DOUT <= INT_OUT;
end ASYNCHRONOUS;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mul
-- File: mul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets integer multiply and optionally the
-- UMUL/SMUL/UMAC/SMAC instructions.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.target.all;
use work.config.all;
use work.iface.all;
use work.multlib.all;
entity mul is
port (
rst : in std_logic;
clk : in clk_type;
holdn : in std_logic;
muli : in mul_in_type;
mulo : out mul_out_type
);
end;
architecture rtl of mul is
component hw_smult
generic ( abits : integer := 10; bbits : integer := 8 );
port (
a : in std_logic_vector(abits-1 downto 0);
b : in std_logic_vector(bbits-1 downto 0);
c : out std_logic_vector(abits+bbits-1 downto 0)
);
end component;
type mul_regtype is record
acc : std_logic_vector(63 downto 0);
state : std_logic_vector(1 downto 0);
start : std_logic;
end record;
type mac_regtype is record
mac : std_logic;
signed : std_logic;
end record;
signal rm, rmin : mul_regtype;
signal mm, mmin : mac_regtype;
signal ma, mb : std_logic_vector(32 downto 0);
signal prod : std_logic_vector(65 downto 0);
signal mreg : std_logic_vector(49 downto 0);
begin
mulcomb : process(rst, rm, muli, mreg, prod, mm)
variable mop1, mop2 : std_logic_vector(32 downto 0);
variable acc, acc1, acc2 : std_logic_vector(48 downto 0);
variable vready, zero : std_logic;
variable v : mul_regtype;
variable w : mac_regtype;
constant CZero: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
begin
v := rm; w := mm; vready := '0'; v.start := muli.start;
mop1 := muli.op1; mop2 := muli.op2;
acc1 := (others => '0'); acc2 := (others => '0');
w.mac := muli.mac; w.signed := muli.signed; zero := '0';
-- select input 2 to accumulator
case MULTIPLIER is
when m16x16 =>
acc2(32 downto 0) := mreg(32 downto 0);
when m32x8 =>
acc2(40 downto 0) := mreg(40 downto 0);
when m32x16 =>
acc2(48 downto 0) := mreg(48 downto 0);
when others => null;
end case;
-- state machine + inputs to multiplier and accumulator input 1
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(32 downto 0) := '0' & rm.acc(63 downto 32);
when m32x8 =>
mop1 := muli.op1;
mop2(8 downto 0) := '0' & muli.op2(7 downto 0);
acc1(40 downto 0) := '0' & rm.acc(63 downto 24);
when m32x16 =>
mop1 := muli.op1;
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(48 downto 0) := '0' & rm.acc(63 downto 16);
when others => null;
end case;
if (rm.start = '1') then v.state := "01"; end if;
when "01" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
v.state := "10";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(15 downto 8);
v.state := "10";
when m32x16 =>
mop1 := muli.op1; mop2(16 downto 0) := muli.op2(32 downto 16);
v.state := "00";
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := muli.op2(32 downto 16);
acc1(32 downto 0) := rm.acc(48 downto 16);
v.state := "11";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(23 downto 16);
acc1(40 downto 0) := rm.acc(48 downto 8);
v.state := "11";
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := muli.op2(32 downto 16);
acc1(32 downto 0) := rm.acc(48 downto 16);
v.state := "00";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := muli.op2(32 downto 24);
acc1(40 downto 0) := rm.acc(56 downto 16);
v.state := "00";
when others => null;
end case;
end case;
-- optional UMAC/SMAC support
if MACEN then
if ((muli.mac and muli.signed) = '1') then
mop1(16) := muli.op1(15); mop2(16) := muli.op2(15);
end if;
if mm.mac = '1' then
acc1(32 downto 0) := muli.y(0) & muli.asr18;
if mm.signed = '1' then acc2(39 downto 32) := (others => mreg(31));
else acc2(39 downto 32) := (others => '0'); end if;
end if;
acc1(39 downto 33) := muli.y(7 downto 1);
end if;
-- accumulator for iterative multiplication (and MAC)
-- pragma translate_off
if not (is_x(acc1 & acc2)) then
-- pragma translate_on
case MULTIPLIER is
when m16x16 =>
if MACEN then
acc(39 downto 0) := acc1(39 downto 0) + acc2(39 downto 0);
else
acc(32 downto 0) := acc1(32 downto 0) + acc2(32 downto 0);
end if;
when m32x8 =>
acc(40 downto 0) := acc1(40 downto 0) + acc2(40 downto 0);
when m32x16 =>
acc(48 downto 0) := acc1(48 downto 0) + acc2(48 downto 0);
when m32x32 =>
v.acc(31 downto 0) := prod(63 downto 32);
when others => null;
end case;
-- pragma translate_off
end if;
-- pragma translate_on
-- save intermediate result to accumulator
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 => v.acc(63 downto 32) := acc(31 downto 0);
when m32x8 => v.acc(63 downto 24) := acc(39 downto 0);
when m32x16 => v.acc(63 downto 16) := acc(47 downto 0);
when others => null;
end case;
when "01" =>
case MULTIPLIER is
when m16x16 => v.acc := CZero(31 downto 0) & mreg(31 downto 0);
when m32x8 =>
v.acc := CZero(23 downto 0) & mreg(39 downto 0);
if muli.signed = '1' then v.acc(48 downto 40) := (others => acc(40)); end if;
when m32x16 =>
v.acc := CZero(15 downto 0) & mreg(47 downto 0); vready := '1';
if muli.signed = '1' then v.acc(63 downto 48) := (others => acc(48)); end if;
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 => v.acc(48 downto 16) := acc(32 downto 0);
when m32x8 => v.acc(48 downto 8) := acc(40 downto 0);
if muli.signed = '1' then v.acc(56 downto 49) := (others => acc(40)); end if;
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
v.acc(48 downto 16) := acc(32 downto 0);
if muli.signed = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
vready := '1';
when m32x8 => v.acc(56 downto 16) := acc(40 downto 0); vready := '1';
if muli.signed = '1' then v.acc(63 downto 57) := (others => acc(40)); end if;
when others => null;
end case;
end case;
-- drive result and condition codes
if (rst = '0') or (muli.flush = '1') then v.state := "00"; end if;
rmin <= v; ma <= mop1; mb <= mop2; mulo.ready <= vready; mmin <= w;
case MULTIPLIER is
when m16x16 =>
if rm.acc(31 downto 0) = CZero(31 downto 0) then zero := '1'; end if;
if MACEN and (mm.mac = '1') then
mulo.result(39 downto 0) <= acc(39 downto 0);
if mm.signed = '1' then
mulo.result(63 downto 40) <= (others => acc(39));
else
mulo.result(63 downto 40) <= (others => '0');
end if;
else
mulo.result(39 downto 0) <= v.acc(39 downto 32) & rm.acc(31 downto 0);
mulo.result(63 downto 40) <= v.acc(63 downto 40);
end if;
mulo.icc <= rm.acc(31) & zero & "00";
when m32x8 =>
if (rm.acc(23 downto 0) = CZero(23 downto 0)) and
(v.acc(31 downto 24) = CZero(7 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 24) & rm.acc(23 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x16 =>
if (rm.acc(15 downto 0) = CZero(15 downto 0)) and
(v.acc(31 downto 16) = CZero(15 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 16) & rm.acc(15 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x32 =>
mulo.result <= rm.acc(31 downto 0) & prod(31 downto 0);
mulo.icc <= "0000"; -- icc set in iu.vhd
when others => null;
mulo.result <= (others => '-');
mulo.icc <= (others => '-');
end case;
end process;
xm1616 : if MULTIPLIER = m16x16 generate
m0 : hw_smult generic map (17, 17)
port map (ma(16 downto 0), mb(16 downto 0), prod(33 downto 0));
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then
if MACEN then mm <= mmin; end if;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
end if;
end process;
end generate;
xm3208 : if MULTIPLIER = m32x8 generate
m0 : hw_smult generic map (33, 9)
port map (ma(32 downto 0), mb(8 downto 0), prod(41 downto 0));
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then
mreg(41 downto 0) <= prod(41 downto 0);
end if;
end if;
end process;
end generate;
xm3216 : if MULTIPLIER = m32x16 generate
m0 : hw_smult generic map (33, 17)
port map (ma(32 downto 0), mb(16 downto 0), prod(49 downto 0));
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then
mreg(49 downto 0) <= prod(49 downto 0);
end if;
end if;
end process;
end generate;
xm3232 : if MULTIPLIER = m32x32 generate
m0 : hw_smult generic map (33, 33)
port map (ma(32 downto 0), mb(32 downto 0), prod(65 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then rm <= rmin; end if;
end if;
end process;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mul
-- File: mul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets integer multiply and optionally the
-- UMUL/SMUL/UMAC/SMAC instructions.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.target.all;
use work.config.all;
use work.iface.all;
use work.multlib.all;
entity mul is
port (
rst : in std_logic;
clk : in clk_type;
holdn : in std_logic;
muli : in mul_in_type;
mulo : out mul_out_type
);
end;
architecture rtl of mul is
component hw_smult
generic ( abits : integer := 10; bbits : integer := 8 );
port (
a : in std_logic_vector(abits-1 downto 0);
b : in std_logic_vector(bbits-1 downto 0);
c : out std_logic_vector(abits+bbits-1 downto 0)
);
end component;
type mul_regtype is record
acc : std_logic_vector(63 downto 0);
state : std_logic_vector(1 downto 0);
start : std_logic;
end record;
type mac_regtype is record
mac : std_logic;
signed : std_logic;
end record;
signal rm, rmin : mul_regtype;
signal mm, mmin : mac_regtype;
signal ma, mb : std_logic_vector(32 downto 0);
signal prod : std_logic_vector(65 downto 0);
signal mreg : std_logic_vector(49 downto 0);
begin
mulcomb : process(rst, rm, muli, mreg, prod, mm)
variable mop1, mop2 : std_logic_vector(32 downto 0);
variable acc, acc1, acc2 : std_logic_vector(48 downto 0);
variable vready, zero : std_logic;
variable v : mul_regtype;
variable w : mac_regtype;
constant CZero: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
begin
v := rm; w := mm; vready := '0'; v.start := muli.start;
mop1 := muli.op1; mop2 := muli.op2;
acc1 := (others => '0'); acc2 := (others => '0');
w.mac := muli.mac; w.signed := muli.signed; zero := '0';
-- select input 2 to accumulator
case MULTIPLIER is
when m16x16 =>
acc2(32 downto 0) := mreg(32 downto 0);
when m32x8 =>
acc2(40 downto 0) := mreg(40 downto 0);
when m32x16 =>
acc2(48 downto 0) := mreg(48 downto 0);
when others => null;
end case;
-- state machine + inputs to multiplier and accumulator input 1
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(32 downto 0) := '0' & rm.acc(63 downto 32);
when m32x8 =>
mop1 := muli.op1;
mop2(8 downto 0) := '0' & muli.op2(7 downto 0);
acc1(40 downto 0) := '0' & rm.acc(63 downto 24);
when m32x16 =>
mop1 := muli.op1;
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(48 downto 0) := '0' & rm.acc(63 downto 16);
when others => null;
end case;
if (rm.start = '1') then v.state := "01"; end if;
when "01" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
v.state := "10";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(15 downto 8);
v.state := "10";
when m32x16 =>
mop1 := muli.op1; mop2(16 downto 0) := muli.op2(32 downto 16);
v.state := "00";
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := muli.op2(32 downto 16);
acc1(32 downto 0) := rm.acc(48 downto 16);
v.state := "11";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(23 downto 16);
acc1(40 downto 0) := rm.acc(48 downto 8);
v.state := "11";
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := muli.op2(32 downto 16);
acc1(32 downto 0) := rm.acc(48 downto 16);
v.state := "00";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := muli.op2(32 downto 24);
acc1(40 downto 0) := rm.acc(56 downto 16);
v.state := "00";
when others => null;
end case;
end case;
-- optional UMAC/SMAC support
if MACEN then
if ((muli.mac and muli.signed) = '1') then
mop1(16) := muli.op1(15); mop2(16) := muli.op2(15);
end if;
if mm.mac = '1' then
acc1(32 downto 0) := muli.y(0) & muli.asr18;
if mm.signed = '1' then acc2(39 downto 32) := (others => mreg(31));
else acc2(39 downto 32) := (others => '0'); end if;
end if;
acc1(39 downto 33) := muli.y(7 downto 1);
end if;
-- accumulator for iterative multiplication (and MAC)
-- pragma translate_off
if not (is_x(acc1 & acc2)) then
-- pragma translate_on
case MULTIPLIER is
when m16x16 =>
if MACEN then
acc(39 downto 0) := acc1(39 downto 0) + acc2(39 downto 0);
else
acc(32 downto 0) := acc1(32 downto 0) + acc2(32 downto 0);
end if;
when m32x8 =>
acc(40 downto 0) := acc1(40 downto 0) + acc2(40 downto 0);
when m32x16 =>
acc(48 downto 0) := acc1(48 downto 0) + acc2(48 downto 0);
when m32x32 =>
v.acc(31 downto 0) := prod(63 downto 32);
when others => null;
end case;
-- pragma translate_off
end if;
-- pragma translate_on
-- save intermediate result to accumulator
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 => v.acc(63 downto 32) := acc(31 downto 0);
when m32x8 => v.acc(63 downto 24) := acc(39 downto 0);
when m32x16 => v.acc(63 downto 16) := acc(47 downto 0);
when others => null;
end case;
when "01" =>
case MULTIPLIER is
when m16x16 => v.acc := CZero(31 downto 0) & mreg(31 downto 0);
when m32x8 =>
v.acc := CZero(23 downto 0) & mreg(39 downto 0);
if muli.signed = '1' then v.acc(48 downto 40) := (others => acc(40)); end if;
when m32x16 =>
v.acc := CZero(15 downto 0) & mreg(47 downto 0); vready := '1';
if muli.signed = '1' then v.acc(63 downto 48) := (others => acc(48)); end if;
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 => v.acc(48 downto 16) := acc(32 downto 0);
when m32x8 => v.acc(48 downto 8) := acc(40 downto 0);
if muli.signed = '1' then v.acc(56 downto 49) := (others => acc(40)); end if;
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
v.acc(48 downto 16) := acc(32 downto 0);
if muli.signed = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
vready := '1';
when m32x8 => v.acc(56 downto 16) := acc(40 downto 0); vready := '1';
if muli.signed = '1' then v.acc(63 downto 57) := (others => acc(40)); end if;
when others => null;
end case;
end case;
-- drive result and condition codes
if (rst = '0') or (muli.flush = '1') then v.state := "00"; end if;
rmin <= v; ma <= mop1; mb <= mop2; mulo.ready <= vready; mmin <= w;
case MULTIPLIER is
when m16x16 =>
if rm.acc(31 downto 0) = CZero(31 downto 0) then zero := '1'; end if;
if MACEN and (mm.mac = '1') then
mulo.result(39 downto 0) <= acc(39 downto 0);
if mm.signed = '1' then
mulo.result(63 downto 40) <= (others => acc(39));
else
mulo.result(63 downto 40) <= (others => '0');
end if;
else
mulo.result(39 downto 0) <= v.acc(39 downto 32) & rm.acc(31 downto 0);
mulo.result(63 downto 40) <= v.acc(63 downto 40);
end if;
mulo.icc <= rm.acc(31) & zero & "00";
when m32x8 =>
if (rm.acc(23 downto 0) = CZero(23 downto 0)) and
(v.acc(31 downto 24) = CZero(7 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 24) & rm.acc(23 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x16 =>
if (rm.acc(15 downto 0) = CZero(15 downto 0)) and
(v.acc(31 downto 16) = CZero(15 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 16) & rm.acc(15 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x32 =>
mulo.result <= rm.acc(31 downto 0) & prod(31 downto 0);
mulo.icc <= "0000"; -- icc set in iu.vhd
when others => null;
mulo.result <= (others => '-');
mulo.icc <= (others => '-');
end case;
end process;
xm1616 : if MULTIPLIER = m16x16 generate
m0 : hw_smult generic map (17, 17)
port map (ma(16 downto 0), mb(16 downto 0), prod(33 downto 0));
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then
if MACEN then mm <= mmin; end if;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
end if;
end process;
end generate;
xm3208 : if MULTIPLIER = m32x8 generate
m0 : hw_smult generic map (33, 9)
port map (ma(32 downto 0), mb(8 downto 0), prod(41 downto 0));
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then
mreg(41 downto 0) <= prod(41 downto 0);
end if;
end if;
end process;
end generate;
xm3216 : if MULTIPLIER = m32x16 generate
m0 : hw_smult generic map (33, 17)
port map (ma(32 downto 0), mb(16 downto 0), prod(49 downto 0));
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then
mreg(49 downto 0) <= prod(49 downto 0);
end if;
end if;
end process;
end generate;
xm3232 : if MULTIPLIER = m32x32 generate
m0 : hw_smult generic map (33, 33)
port map (ma(32 downto 0), mb(32 downto 0), prod(65 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then rm <= rmin; end if;
end if;
end process;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mul
-- File: mul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets integer multiply and optionally the
-- UMUL/SMUL/UMAC/SMAC instructions.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.target.all;
use work.config.all;
use work.iface.all;
use work.multlib.all;
entity mul is
port (
rst : in std_logic;
clk : in clk_type;
holdn : in std_logic;
muli : in mul_in_type;
mulo : out mul_out_type
);
end;
architecture rtl of mul is
component hw_smult
generic ( abits : integer := 10; bbits : integer := 8 );
port (
a : in std_logic_vector(abits-1 downto 0);
b : in std_logic_vector(bbits-1 downto 0);
c : out std_logic_vector(abits+bbits-1 downto 0)
);
end component;
type mul_regtype is record
acc : std_logic_vector(63 downto 0);
state : std_logic_vector(1 downto 0);
start : std_logic;
end record;
type mac_regtype is record
mac : std_logic;
signed : std_logic;
end record;
signal rm, rmin : mul_regtype;
signal mm, mmin : mac_regtype;
signal ma, mb : std_logic_vector(32 downto 0);
signal prod : std_logic_vector(65 downto 0);
signal mreg : std_logic_vector(49 downto 0);
begin
mulcomb : process(rst, rm, muli, mreg, prod, mm)
variable mop1, mop2 : std_logic_vector(32 downto 0);
variable acc, acc1, acc2 : std_logic_vector(48 downto 0);
variable vready, zero : std_logic;
variable v : mul_regtype;
variable w : mac_regtype;
constant CZero: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
begin
v := rm; w := mm; vready := '0'; v.start := muli.start;
mop1 := muli.op1; mop2 := muli.op2;
acc1 := (others => '0'); acc2 := (others => '0');
w.mac := muli.mac; w.signed := muli.signed; zero := '0';
-- select input 2 to accumulator
case MULTIPLIER is
when m16x16 =>
acc2(32 downto 0) := mreg(32 downto 0);
when m32x8 =>
acc2(40 downto 0) := mreg(40 downto 0);
when m32x16 =>
acc2(48 downto 0) := mreg(48 downto 0);
when others => null;
end case;
-- state machine + inputs to multiplier and accumulator input 1
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(32 downto 0) := '0' & rm.acc(63 downto 32);
when m32x8 =>
mop1 := muli.op1;
mop2(8 downto 0) := '0' & muli.op2(7 downto 0);
acc1(40 downto 0) := '0' & rm.acc(63 downto 24);
when m32x16 =>
mop1 := muli.op1;
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(48 downto 0) := '0' & rm.acc(63 downto 16);
when others => null;
end case;
if (rm.start = '1') then v.state := "01"; end if;
when "01" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
v.state := "10";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(15 downto 8);
v.state := "10";
when m32x16 =>
mop1 := muli.op1; mop2(16 downto 0) := muli.op2(32 downto 16);
v.state := "00";
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := muli.op2(32 downto 16);
acc1(32 downto 0) := rm.acc(48 downto 16);
v.state := "11";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(23 downto 16);
acc1(40 downto 0) := rm.acc(48 downto 8);
v.state := "11";
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := muli.op2(32 downto 16);
acc1(32 downto 0) := rm.acc(48 downto 16);
v.state := "00";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := muli.op2(32 downto 24);
acc1(40 downto 0) := rm.acc(56 downto 16);
v.state := "00";
when others => null;
end case;
end case;
-- optional UMAC/SMAC support
if MACEN then
if ((muli.mac and muli.signed) = '1') then
mop1(16) := muli.op1(15); mop2(16) := muli.op2(15);
end if;
if mm.mac = '1' then
acc1(32 downto 0) := muli.y(0) & muli.asr18;
if mm.signed = '1' then acc2(39 downto 32) := (others => mreg(31));
else acc2(39 downto 32) := (others => '0'); end if;
end if;
acc1(39 downto 33) := muli.y(7 downto 1);
end if;
-- accumulator for iterative multiplication (and MAC)
-- pragma translate_off
if not (is_x(acc1 & acc2)) then
-- pragma translate_on
case MULTIPLIER is
when m16x16 =>
if MACEN then
acc(39 downto 0) := acc1(39 downto 0) + acc2(39 downto 0);
else
acc(32 downto 0) := acc1(32 downto 0) + acc2(32 downto 0);
end if;
when m32x8 =>
acc(40 downto 0) := acc1(40 downto 0) + acc2(40 downto 0);
when m32x16 =>
acc(48 downto 0) := acc1(48 downto 0) + acc2(48 downto 0);
when m32x32 =>
v.acc(31 downto 0) := prod(63 downto 32);
when others => null;
end case;
-- pragma translate_off
end if;
-- pragma translate_on
-- save intermediate result to accumulator
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 => v.acc(63 downto 32) := acc(31 downto 0);
when m32x8 => v.acc(63 downto 24) := acc(39 downto 0);
when m32x16 => v.acc(63 downto 16) := acc(47 downto 0);
when others => null;
end case;
when "01" =>
case MULTIPLIER is
when m16x16 => v.acc := CZero(31 downto 0) & mreg(31 downto 0);
when m32x8 =>
v.acc := CZero(23 downto 0) & mreg(39 downto 0);
if muli.signed = '1' then v.acc(48 downto 40) := (others => acc(40)); end if;
when m32x16 =>
v.acc := CZero(15 downto 0) & mreg(47 downto 0); vready := '1';
if muli.signed = '1' then v.acc(63 downto 48) := (others => acc(48)); end if;
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 => v.acc(48 downto 16) := acc(32 downto 0);
when m32x8 => v.acc(48 downto 8) := acc(40 downto 0);
if muli.signed = '1' then v.acc(56 downto 49) := (others => acc(40)); end if;
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
v.acc(48 downto 16) := acc(32 downto 0);
if muli.signed = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
vready := '1';
when m32x8 => v.acc(56 downto 16) := acc(40 downto 0); vready := '1';
if muli.signed = '1' then v.acc(63 downto 57) := (others => acc(40)); end if;
when others => null;
end case;
end case;
-- drive result and condition codes
if (rst = '0') or (muli.flush = '1') then v.state := "00"; end if;
rmin <= v; ma <= mop1; mb <= mop2; mulo.ready <= vready; mmin <= w;
case MULTIPLIER is
when m16x16 =>
if rm.acc(31 downto 0) = CZero(31 downto 0) then zero := '1'; end if;
if MACEN and (mm.mac = '1') then
mulo.result(39 downto 0) <= acc(39 downto 0);
if mm.signed = '1' then
mulo.result(63 downto 40) <= (others => acc(39));
else
mulo.result(63 downto 40) <= (others => '0');
end if;
else
mulo.result(39 downto 0) <= v.acc(39 downto 32) & rm.acc(31 downto 0);
mulo.result(63 downto 40) <= v.acc(63 downto 40);
end if;
mulo.icc <= rm.acc(31) & zero & "00";
when m32x8 =>
if (rm.acc(23 downto 0) = CZero(23 downto 0)) and
(v.acc(31 downto 24) = CZero(7 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 24) & rm.acc(23 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x16 =>
if (rm.acc(15 downto 0) = CZero(15 downto 0)) and
(v.acc(31 downto 16) = CZero(15 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 16) & rm.acc(15 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x32 =>
mulo.result <= rm.acc(31 downto 0) & prod(31 downto 0);
mulo.icc <= "0000"; -- icc set in iu.vhd
when others => null;
mulo.result <= (others => '-');
mulo.icc <= (others => '-');
end case;
end process;
xm1616 : if MULTIPLIER = m16x16 generate
m0 : hw_smult generic map (17, 17)
port map (ma(16 downto 0), mb(16 downto 0), prod(33 downto 0));
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then
if MACEN then mm <= mmin; end if;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
end if;
end process;
end generate;
xm3208 : if MULTIPLIER = m32x8 generate
m0 : hw_smult generic map (33, 9)
port map (ma(32 downto 0), mb(8 downto 0), prod(41 downto 0));
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then
mreg(41 downto 0) <= prod(41 downto 0);
end if;
end if;
end process;
end generate;
xm3216 : if MULTIPLIER = m32x16 generate
m0 : hw_smult generic map (33, 17)
port map (ma(32 downto 0), mb(16 downto 0), prod(49 downto 0));
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then
mreg(49 downto 0) <= prod(49 downto 0);
end if;
end if;
end process;
end generate;
xm3232 : if MULTIPLIER = m32x32 generate
m0 : hw_smult generic map (33, 33)
port map (ma(32 downto 0), mb(32 downto 0), prod(65 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then rm <= rmin; end if;
end if;
end process;
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.math_real.all;
PACKAGE snake_pack IS
--TYPE int_s IS INTEGER RANGE -20 TO 255;
TYPE int_array IS array (0 to 127) OF INTEGER RANGE -20 TO 255;
COMPONENT conv_7seg IS
PORT (digit : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
seg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ;
END COMPONENT;
COMPONENT create_food IS
-- Altura e comprimento do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
width : INTEGER := 6);
PORT (reset : IN STD_LOGIC;
eaten : IN STD_LOGIC;
gmap : IN STD_LOGIC_VECTOR(0 TO N*M-1);
new_food : OUT INTEGER RANGE 0 TO N*M-1);
END COMPONENT;
COMPONENT gclock IS
-- Frequencia de 1Hz
-- clock do hardware
PORT (CLOCK_27 : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
clock_out : OUT STD_LOGIC) ;
END COMPONENT;
COMPONENT make_map IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
-- clock do jogo
PORT (clock : IN STD_LOGIC;
-- reseta o jogo
reset : IN STD_LOGIC;
-- aumento do tamanho
eaten : IN STD_LOGIC;
snake_size : IN INTEGER RANGE 0 TO N*M;
-- direcao para onde a cobra esta se movendo
-- 11 : cima
-- 00 : baixo
-- 10 : esquerda
-- 01 : direita
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-- posicoes da cobra no mapa
snake_body : OUT int_array);
END COMPONENT;
COMPONENT size_counter IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
PORT (reset : IN STD_LOGIC;
food_pos : IN INTEGER RANGE -20 TO 255;
--food_pos : IN INTEGER RANGE 0 TO N*M-1;
snake_head : IN INTEGER RANGE -20 TO 255;
snake_size : OUT INTEGER RANGE 0 TO N*M;
eaten : OUT STD_LOGIC);
END COMPONENT;
COMPONENT colision IS
-- Dimensoes do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10);
PORT (snake_body : IN int_array;
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
reset : IN STD_LOGIC;
gmap : OUT STD_LOGIC_VECTOR(0 to N*M-1);
lost : OUT STD_LOGIC);
END COMPONENT ;
COMPONENT snake_dir IS
PORT (reset : IN STD_LOGIC;
snake_turn : IN STD_LOGIC_VECTOR(1 downto 0);
dir : BUFFER STD_LOGIC_VECTOR(0 to 1));
END COMPONENT;
END snake_pack;
|
entity agg2 is
end entity;
architecture test of agg2 is
type int_array is array (integer range <>) of integer;
function all_ones(x : int_array) return int_array is
variable y : int_array(1 to x'length) := (others => 0);
begin
y := (others => 1);
return y;
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
begin
assert all_ones(x) = (1, 1, 1);
wait;
end process;
end architecture;
|
entity agg2 is
end entity;
architecture test of agg2 is
type int_array is array (integer range <>) of integer;
function all_ones(x : int_array) return int_array is
variable y : int_array(1 to x'length) := (others => 0);
begin
y := (others => 1);
return y;
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
begin
assert all_ones(x) = (1, 1, 1);
wait;
end process;
end architecture;
|
entity agg2 is
end entity;
architecture test of agg2 is
type int_array is array (integer range <>) of integer;
function all_ones(x : int_array) return int_array is
variable y : int_array(1 to x'length) := (others => 0);
begin
y := (others => 1);
return y;
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
begin
assert all_ones(x) = (1, 1, 1);
wait;
end process;
end architecture;
|
entity agg2 is
end entity;
architecture test of agg2 is
type int_array is array (integer range <>) of integer;
function all_ones(x : int_array) return int_array is
variable y : int_array(1 to x'length) := (others => 0);
begin
y := (others => 1);
return y;
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
begin
assert all_ones(x) = (1, 1, 1);
wait;
end process;
end architecture;
|
entity agg2 is
end entity;
architecture test of agg2 is
type int_array is array (integer range <>) of integer;
function all_ones(x : int_array) return int_array is
variable y : int_array(1 to x'length) := (others => 0);
begin
y := (others => 1);
return y;
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
begin
assert all_ones(x) = (1, 1, 1);
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
-- LED example, by Jerome Cornet
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Aaatop is
Port (
CLK : in STD_LOGIC;
txd : inout std_logic;
rxd : in std_logic;
ARD_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
-- DUO_LED : out std_logic;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end Aaatop;
architecture Behavioral of Aaatop is
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal LED1 : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
component clk32to40
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
-- Architecture declarations
signal csromn : std_logic := '1';
signal csesramn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0) := X"FF";
SIGNAL dbus_esram : std_logic_vector(7 DOWNTO 0) := X"EE";
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(2 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT blk_mem_40K
PORT (
addra : IN std_logic_VECTOR (15 DOWNTO 0);
clka : IN std_logic;
dina : IN std_logic_VECTOR (7 DOWNTO 0);
wea : IN std_logic_VECTOR (0 DOWNTO 0);
douta : OUT std_logic_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
-- COMPONENT bootstrap
-- PORT (
-- abus : IN std_logic_vector (7 DOWNTO 0);
-- dbus : OUT std_logic_vector (7 DOWNTO 0)
-- );
-- END COMPONENT;
-- COMPONENT esram
-- PORT (
-- addra : IN std_logic_VECTOR (7 DOWNTO 0);
-- clka : IN std_logic;
-- dina : IN std_logic_VECTOR (7 DOWNTO 0);
-- wea : IN std_logic_VECTOR (0 DOWNTO 0);
-- douta : OUT std_logic_VECTOR (7 DOWNTO 0)
-- );
-- END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
begin
ARD_RESET <= not(DUO_SW1);
sram_addr <= '0' & abus;
CTS <= '1';
-- w1b(1) <= 'Z';
-- PIN3 <= not w1b(1); -- por
PIN3 <= '1';
dcm0: clk32to40
port map
(-- Clock in ports
CLK_IN1 => clk,
-- Clock out ports
CLK_OUT1 => CLOCK_40MHZ);
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram)
begin
case sel_s is
when "011" => dbus_in_cpu <= dbus_esram; -- esram
when "101" => dbus_in_cpu <= dbus_com1; -- UART
when "110" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when others=> dbus_in_cpu <= dbus_in; -- Embedded SRAM
end case;
end process;
process(csesramn,wrn,rdn,dbus_out,sram_data)
begin
sram_ce <= '1';
sram_we <= '1';
sram_oe <= '1';
sram_data <= (others => 'Z');
if csesramn='0' then
sram_ce <= '0';
if wrn='0' then
sram_data <= dbus_out;
sram_we <= '0';
else
if rdn='0' then
dbus_esram <= sram_data;
sram_oe <= '0';
end if;
end if;
end if;
end process;
-- HDL Embedded Text Block 7 clogic
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= csesramn & cscom1 & csromn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
-- csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- esram 256 bytes
-- 0xEEE00
-- csesramn <= '0' when ((abus(19 downto 8)=X"EEE") AND iom='0') else '1';
csesramn <= '0' when ((abus(19)='0') AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => CLOCK_40MHZ,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
U_3 : blk_mem_40K
PORT MAP (
clka => CLOCK_40MHZ,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
);
-- esram0 : esram
-- PORT map (
-- addra => abus(15 downto 0),
-- clka => CLOCK_40MHZ,
-- dina => dbus_out,
-- wea => wea_esram,
-- douta => dbus_in_esram
-- );
-- U_2 : bootstrap
-- PORT MAP (
-- abus => abus(7 DOWNTO 0),
-- dbus => dbus_rom
-- );
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => CLOCK_40MHZ,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
end Behavioral;
|
-------------------------------------------------------------------------------------
-- FILE NAME : amc7823_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - amc7823_ctrl
-- architecture - amc7823_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file initialises the internal registers in the AMC7823 from FPGA ROM
-- through SPI communication bus.
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
-- Memoryies NGC
library UNISIM;
use UNISIM.vcomponents.all;
entity amc7823_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF";
g_sim : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end amc7823_ctrl;
architecture amc7823_ctrl_syn of amc7823_ctrl is
component fmc150_stellar_cmd is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port
(
reset : in std_logic;
-- Command Interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0); --caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0); --out register address
in_reg : in std_logic_vector(31 downto 0); --requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0); --value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component fmc150_stellar_cmd;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component amc7823_init_mem is
port (
clka : in std_logic;
addra : in std_logic_vector(4 downto 0);
douta : out std_logic_vector(31 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector(27 downto 0) := x"0000320";
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"0000115"; --page 1 (0x40), reg 0x15
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"000011E"; --page 1 (0x40), reg 0x1E
type sh_states is (idle, instruct, data_io, data_valid);
signal sh_state : sh_states;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal mon_reset : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal page_reg : std_logic_vector(1 downto 0);
signal inst_reg : std_logic_vector(4 downto 0);
signal data_reg : std_logic_vector(15 downto 0);
signal sh_counter : integer;
signal sh_counter_gen : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(31 downto 0);
signal init_address : std_logic_vector(4 downto 0);
signal init_data : std_logic_vector(31 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(15 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 20MHz)
----------------------------------------------------------------------------------------------------
gen_serial_clk : if (g_sim = 0) generate
process (clk)
-- Divide by 2^4 = 16, CLKmax = 16 x 20MHz = 320MHz
variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
begin
if (rising_edge(clk)) then
clk_div := clk_div + '1';
-- The slave samples the data on the falling edge of SCLK.
-- therefore we make sure the external clock is slightly
-- before the internal clock.
sclk_ext <= clk_div(clk_div'length-1);
serial_clk <= sclk_ext;
end if;
end process;
end generate;
-- Do not divide clock. Improve simulation speed.
gen_serial_clk_sim : if (g_sim = 1) generate
serial_clk <= clk;
end generate;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc150_stellar_cmd_inst : fmc150_stellar_cmd
generic map
(
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map
(
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => '0',
mbx_in_reg => (others => '0')
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the DAC state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
mon_reset <= '1';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
page_reg <= (others=> '0');
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
--Write
if (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
mon_reset <= out_reg(1);
else
mon_reset <= '0';
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 28) & busy & not mon_n_int & mon_reset & init_done_prev;
-- read from serial if when address is within DAC range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 16) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within DAC range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
page_reg <= out_reg_addr(9 downto 8);
inst_reg <= out_reg_addr(4 downto 0);
data_reg <= out_reg(15 downto 0);
-- Read instruction, only when address is within DAC range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
page_reg <= in_reg_addr(9 downto 8);
inst_reg <= in_reg_addr(4 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- DAC serial interface state-machine
----------------------------------------------------------------------------------------------------
--gen_sh_counter : if (g_sim = 0) generate
sh_counter_gen <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
--end generate;
--gen_sh_counter_sim : if (g_sim = 1) generate
-- sh_counter_gen <= 1;
--end generate;
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= sh_counter_gen;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus one data byte;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
----------------------------------------------------------------------------------------------------
-- DAC instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
--rw + X,PG + X,StartADR + X,EndADR+ data
shift_reg <= '0' & init_data(26 downto 24) & init_data(21 downto 16) & init_data(21 downto 16) & init_data(15 downto 0);
-- Stop when update instruction is reveived (= last instruction)
if (init_data(31 downto 16) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
-- Always access one register per cycle
shift_reg <= inst_rw & '0' & page_reg & '0' & inst_reg & '0' & inst_reg & data_reg;
elsif (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length - 2 downto 0) & sdi;
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from DAC
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(15 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory
----------------------------------------------------------------------------------------------------
amc7823_init_mem_inst : amc7823_init_mem
port map (
clka => serial_clk,
addra => init_address,
douta => init_data
);
----------------------------------------------------------------------------------------------------
-- Capture data in on falling edge SCLK
-- therefore pass the signal to the process that captures on the rising edge of serial clock.
----------------------------------------------------------------------------------------------------
--process (serial_clk)
--begin
-- if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
-- end if;
--end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = data_io and read_n_write = '1') else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= not sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);
mon_n_reset <= not mon_reset;
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end amc7823_ctrl_syn;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity erode is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end erode;
architecture rtl of erode is
component erode_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_value : in std_logic_vector(15 downto 0);
heigtimg_reg_value : in std_logic_vector(15 downto 0);
er00_reg_m00 : in std_logic_vector(7 downto 0);
er01_reg_m01 : in std_logic_vector(7 downto 0);
er02_reg_m02 : in std_logic_vector(7 downto 0);
er10_reg_m10 : in std_logic_vector(7 downto 0);
er11_reg_m11 : in std_logic_vector(7 downto 0);
er12_reg_m12 : in std_logic_vector(7 downto 0);
er20_reg_m20 : in std_logic_vector(7 downto 0);
er21_reg_m21 : in std_logic_vector(7 downto 0);
er22_reg_m22 : in std_logic_vector(7 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component erode_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_value : out std_logic_vector(15 downto 0);
heigtimg_reg_value : out std_logic_vector(15 downto 0);
er00_reg_m00 : out std_logic_vector(7 downto 0);
er01_reg_m01 : out std_logic_vector(7 downto 0);
er02_reg_m02 : out std_logic_vector(7 downto 0);
er10_reg_m10 : out std_logic_vector(7 downto 0);
er11_reg_m11 : out std_logic_vector(7 downto 0);
er12_reg_m12 : out std_logic_vector(7 downto 0);
er20_reg_m20 : out std_logic_vector(7 downto 0);
er21_reg_m21 : out std_logic_vector(7 downto 0);
er22_reg_m22 : out std_logic_vector(7 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_value : std_logic_vector (15 downto 0);
signal heigtimg_reg_value : std_logic_vector (15 downto 0);
signal er00_reg_m00 : std_logic_vector (7 downto 0);
signal er01_reg_m01 : std_logic_vector (7 downto 0);
signal er02_reg_m02 : std_logic_vector (7 downto 0);
signal er10_reg_m10 : std_logic_vector (7 downto 0);
signal er11_reg_m11 : std_logic_vector (7 downto 0);
signal er12_reg_m12 : std_logic_vector (7 downto 0);
signal er20_reg_m20 : std_logic_vector (7 downto 0);
signal er21_reg_m21 : std_logic_vector (7 downto 0);
signal er22_reg_m22 : std_logic_vector (7 downto 0);
begin
erode_process_inst : erode_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_value => widthimg_reg_value,
heigtimg_reg_value => heigtimg_reg_value,
er00_reg_m00 => er00_reg_m00,
er01_reg_m01 => er01_reg_m01,
er02_reg_m02 => er02_reg_m02,
er10_reg_m10 => er10_reg_m10,
er11_reg_m11 => er11_reg_m11,
er12_reg_m12 => er12_reg_m12,
er20_reg_m20 => er20_reg_m20,
er21_reg_m21 => er21_reg_m21,
er22_reg_m22 => er22_reg_m22,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
erode_slave_inst : erode_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_value => widthimg_reg_value,
heigtimg_reg_value => heigtimg_reg_value,
er00_reg_m00 => er00_reg_m00,
er01_reg_m01 => er01_reg_m01,
er02_reg_m02 => er02_reg_m02,
er10_reg_m10 => er10_reg_m10,
er11_reg_m11 => er11_reg_m11,
er12_reg_m12 => er12_reg_m12,
er20_reg_m20 => er20_reg_m20,
er21_reg_m21 => er21_reg_m21,
er22_reg_m22 => er22_reg_m22,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:21:13 05/22/2013
-- Design Name:
-- Module Name: Encoder4x2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Encoder4x2 is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
O : out STD_LOGIC_VECTOR (1 downto 0));
end Encoder4x2;
architecture Behavioral of Encoder4x2 is
begin
process(I)
begin
case i is
when "0001" => O <= "00";
when "0010" => O <= "01";
when "0100" => O <= "10";
when "1000" => O <= "11";
when others => null;
end case;
end process;
end Behavioral;
|
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- This file contains custom math functions.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package math_custom is
-- Function: clog2()
-- Description: Takes the ceil(log2) of a positive integer.
-- Useful for avoiding all the casting that takes place in math_real.
function clog2(input : positive) return natural;
-- Function: clog2_pos()
-- Description: Computes ceil(log2(input)), but with clog2(1)=1 instead of 0
-- Useful for getting minimum bits needed to index "input" number of
-- distinct values, such as for addresses.
function clog2_pos(input : positive) return positive;
-- Function: bitsNeeded
-- Description: returns the number of bits required to store a specified
-- value. Can also be used to determine the bits required for
-- a specific number of unique values by substracting one from
-- the inputs.
-- e.g. 1, when trying to determine how many bits are needed to store a
-- value X, call bitsNeeded(X)
--
-- e.g. 2, when trying to determine how many bits are needed for an address
-- space with X elements, call bitsNeeded(X-1). For example, an address
-- space for 8 elements would require bitsNeeded(7) because 7 would be the
-- highest address.
function bitsNeeded(value : natural) return positive;
-- Function: bitsForValue
-- Description: An alias for bitsNeeded to provide a more consistent naming
-- convention that matches bitsForAmount()
function bitsForValue(value : positive) return positive;
-- Function: bitsForAmount
-- Description: returns the number of bits required to store "amount"
-- distinct values. This is useful when determining the number
-- of bits for an address space. It is also equivalent to
-- bitsNeeded(amount-1).
-- e.g. 1, when trying to determine how many bits are needed for an address
-- space with X elements, call bitsForAmount(X). For example, an address
-- space for 8 elements would require bitsForAmount(8) bits. Alternatively,
-- bitsNeeded(8-1) also works.
function bitsForAmount(amount : positive) return positive;
end package;
package body math_custom is
function clog2(input : positive) return natural is
begin
return natural(ceil(log2(real(input))));
end function;
function clog2_pos(input : positive) return positive is
variable temp : natural;
variable logVal : natural;
begin
if (input = 1) then
return 1;
else
return positive(ceil(log2(real(input))));
end if;
end function;
function bitsNeeded(value : natural) return positive is
begin
return clog2_pos(value+1);
end function;
function bitsForValue(value : positive) return positive is
begin
return bitsNeeded(value);
end function;
function bitsForAmount(amount : positive) return positive is
begin
return clog2_pos(amount);
end function;
end package body;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rst_ps7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_ps7_0_100M_0;
ARCHITECTURE system_rst_ps7_0_100M_0_arch OF system_rst_ps7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rst_ps7_0_100M_0_arch : ARCHITECTURE IS "system_rst_ps7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "system_rst_ps7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_ps7_0_100M_0_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity clock_div is
Port ( reset, clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC);
end clock_div;
architecture Behavioral of clock_div is
signal count : std_logic_vector( 3 downto 0 );
begin
clk_out <= count(3);
process( reset, clk_in )
begin
if( reset = '1' ) then
count <= ( others => '0' );
elsif( rising_edge( clk_in ) ) then
count <= count + "0001";
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:09:43 03/27/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet4/MII_test3.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MII_RX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MII_test3 IS
END MII_test3;
ARCHITECTURE behavior OF MII_test3 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MII_RX
PORT(
recv_data : IN std_logic_vector(4 downto 0);
recv_strobe : IN std_logic;
recv_clock : IN std_logic;
recv_error : IN std_logic;
next_frame : IN std_logic;
data_received : OUT std_logic;
clk : IN std_logic;
reset : IN std_logic;
busy : OUT std_logic;
ram_clk : IN std_logic;
ram_enable : IN std_logic;
ram_output : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal recv_data : std_logic_vector(4 downto 0) := (others => '0');
signal recv_strobe : std_logic := '0';
signal recv_clock : std_logic := '0';
signal recv_error : std_logic := '0';
signal next_frame : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal ram_clk : std_logic := '0';
signal ram_enable : std_logic := '0';
--Outputs
signal data_received : std_logic;
signal busy : std_logic;
signal ram_output : std_logic_vector(7 downto 0);
-- Clock period definitions
constant recv_clock_period : time := 100 ns;
constant clk_period : time := 10 ns;
constant ram_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MII_RX PORT MAP (
recv_data => recv_data,
recv_strobe => recv_strobe,
recv_clock => recv_clock,
recv_error => recv_error,
next_frame => next_frame,
data_received => data_received,
clk => clk,
reset => reset,
busy => busy,
ram_clk => ram_clk,
ram_enable => ram_enable,
ram_output => ram_output
);
-- Clock process definitions
recv_clock_process :process
begin
recv_clock <= '0';
wait for recv_clock_period/2;
recv_clock <= '1';
wait for recv_clock_period/2;
end process;
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
ram_clk_process :process
begin
ram_clk <= '0';
wait for ram_clk_period/2;
ram_clk <= '1';
wait for ram_clk_period/2;
end process;
recv_data <= "00001", "00010" after 200 ns, "00011" after 400 ns, "00100" after 600 ns, "00101" after 800 ns, "00110" after 1000 ns, "00111" after 2000 ns, "01000" after 2200 ns, "01001" after 2400 ns, "01010" after 2600 ns, "01011" after 2800 ns, "01100" after 3000 ns;
recv_strobe <= '1', '0' after 1000 ns, '1' after 2000 ns;
ram_enable <= '1' after 1000 ns, '0' after 2000 ns;
END;
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Floating-point package (Generic package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body float_generic_pkg is
-- Author David Bishop (dbishop@vhdl.org)
-----------------------------------------------------------------------------
-- type declarations
-----------------------------------------------------------------------------
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant
-- types of boundary conditions
type boundary_type is (normal, infinity, zero, denormal);
-- null range array constant
constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- Special version of "minimum" to do some boundary checking
function mine (L, R : INTEGER)
return INTEGER is
begin -- function minimum
if (L = INTEGER'low or R = INTEGER'low) then
report float_generic_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- Generates the base number for the exponent normalization offset.
function gen_expon_base (
constant exponent_width : NATURAL)
return SIGNED
is
variable result : SIGNED (exponent_width-1 downto 0);
begin
result := (others => '1');
result (exponent_width-1) := '0';
return result;
end function gen_expon_base;
-- Integer version of the "log2" command (contributed by Peter Ashenden)
function log2 (A : NATURAL) return NATURAL is
variable quotient : NATURAL;
variable result : NATURAL := 0;
begin
quotient := A / 2;
while quotient > 0 loop
quotient := quotient / 2;
result := result + 1;
end loop;
return result;
end function log2;
-- Function similar to the ILOGB function in MATH_REAL
function log2 (A : REAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if (A = 1.0 or A = 0.0) then
return 0;
end if;
Y := A;
if(A > 1.0) then
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y * 2.0;
N := N - 1;
end loop;
return N;
end function log2;
-- purpose: Test the boundary conditions of a Real number
procedure test_boundary (
arg : in REAL; -- Input, converted to real
constant fraction_width : in NATURAL; -- length of FP output fraction
constant exponent_width : in NATURAL; -- length of FP exponent
constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP
variable btype : out boundary_type;
variable log2i : out INTEGER
) is
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
constant exp_min : SIGNED (12 downto 0) :=
-(resize(expon_base, 13)) + 1; -- Minimum normal exponent
constant exp_ext_min : SIGNED (12 downto 0) :=
exp_min - fraction_width; -- Minimum for denormal exponent
variable log2arg : INTEGER; -- log2 of argument
begin -- function test_boundary
-- Check to see if the exponent is big enough
-- Note that the argument is always an absolute value at this point.
log2arg := log2(arg);
if arg = 0.0 then
btype := zero;
elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)
btype := normal;
else
if log2arg < to_integer(exp_min) then
if denormalize then
if log2arg < to_integer(exp_ext_min) then
btype := zero;
else
btype := denormal;
end if;
else
if log2arg < to_integer(exp_min)-1 then
btype := zero;
else
btype := normal; -- Can still represent this number
end if;
end if;
elsif exponent_width < 11 then
if log2arg > to_integer(expon_base)+1 then
btype := infinity;
else
btype := normal;
end if;
else
btype := normal;
end if;
end if;
log2i := log2arg;
end procedure test_boundary;
-- purpose: Rounds depending on the state of the "round_style"
-- Logic taken from
-- "What Every Computer Scientist Should Know About Floating Point Arithmetic"
-- by David Goldberg (1991)
function check_round (
fract_in : STD_ULOGIC; -- input fraction
sign : STD_ULOGIC; -- sign bit
remainder : UNSIGNED; -- remainder to round from
sticky : STD_ULOGIC := '0'; -- Sticky bit
constant round_style : round_type) -- rounding type
return BOOLEAN
is
variable result : BOOLEAN;
variable or_reduced : STD_ULOGIC;
begin -- function check_round
result := false;
if (remainder'length > 0) then -- if remainder in a null array
or_reduced := or (remainder & sticky);
rounding_case : case round_style is
when round_nearest => -- Round Nearest, default mode
if remainder(remainder'high) = '1' then -- round
if (remainder'length > 1) then
if ((or (remainder(remainder'high-1
downto remainder'low)) = '1'
or sticky = '1')
or fract_in = '1') then
-- Make the bottom bit zero if possible if we are at 1/2
result := true;
end if;
else
result := (fract_in = '1' or sticky = '1');
end if;
end if;
when round_inf => -- round up if positive, else truncate.
if or_reduced = '1' and sign = '0' then
result := true;
end if;
when round_neginf => -- round down if negative, else truncate.
if or_reduced = '1' and sign = '1' then
result := true;
end if;
when round_zero => -- round toward 0 Truncate
null;
end case rounding_case;
end if;
return result;
end function check_round;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
procedure fp_round (
fract_in : in UNSIGNED; -- input fraction
expon_in : in SIGNED; -- input exponent
fract_out : out UNSIGNED; -- output fraction
expon_out : out SIGNED) is -- output exponent
begin -- procedure fp_round
if and (fract_in) = '1' then -- Fraction is all "1"
expon_out := expon_in + 1;
fract_out := to_unsigned(0, fract_out'high+1);
else
expon_out := expon_in;
fract_out := fract_in + 1;
end if;
end procedure fp_round;
-- This version of break_number doesn't call "classfp"
procedure break_number ( -- internal version
arg : in UNRESOLVED_float;
fptyp : in valid_fpstate;
denormalize : in BOOLEAN := true;
fract : out UNSIGNED;
expon : out SIGNED) is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable exp : SIGNED (expon'range);
begin
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (fraction_width) := '1';
exp := SIGNED(arg(exponent_width-1 downto 0));
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert no_warning
report float_generic_pkg'instance_name
& "BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a NAN goes in, a NAN comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- purpose: floating point to UNSIGNED
-- Used by to_integer, to_unsigned, and to_signed functions
procedure float_to_unsigned (
arg : in UNRESOLVED_float; -- floating point input
variable sign : out STD_ULOGIC; -- sign of output
variable frac : out UNSIGNED; -- unsigned biased output
constant denormalize : in BOOLEAN; -- turn on denormalization
constant bias : in NATURAL; -- bias for fixed point
constant round_style : in round_type) is -- rounding method
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable fract : UNSIGNED (frac'range); -- internal version of frac
variable isign : STD_ULOGIC; -- internal version of sign
variable exp : INTEGER; -- Exponent
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
-- Base to divide fraction by
variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable remainder : UNSIGNED (2 downto 0);
variable round : STD_ULOGIC; -- round BIT
begin
isign := to_x01(arg(arg'high));
-- exponent /= '0', normal floating point
expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (expon);
-- Figure out the fraction
fract := (others => '0'); -- fill with zero
fract (fract'high) := '1'; -- Add the "1.0".
shift := (fract'high-1) - exp;
if fraction_width > fract'high then -- Can only use size-2 bits
fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-fract'high)));
else -- can use all bits
fract (fract'high-1 downto fract'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := fract & "000";
if shift < 0 then -- Overflow
fract := (others => '1');
else
frac_shift := shift_right (frac_shift, shift);
fract := frac_shift (frac_shift'high downto 3);
remainder := frac_shift (2 downto 0);
-- round (round_zero will bypass this and truncate)
case round_style is
when round_nearest =>
round := remainder(2) and
(fract (0) or (or (remainder (1 downto 0))));
when round_inf =>
round := remainder(2) and not isign;
when round_neginf =>
round := remainder(2) and isign;
when others =>
round := '0';
end case;
if round = '1' then
fract := fract + 1;
end if;
end if;
frac := fract;
sign := isign;
end procedure float_to_unsigned;
-- purpose: returns a part of a vector, this function is here because
-- or (fractr (to_integer(shiftx) downto 0));
-- can't be synthesized in some synthesis tools.
function smallfract (
arg : UNSIGNED;
shift : NATURAL)
return STD_ULOGIC
is
variable orx : STD_ULOGIC;
begin
orx := arg(shift);
for i in arg'range loop
if i < shift then
orx := arg(i) or orx;
end if;
end loop;
return orx;
end function smallfract;
---------------------------------------------------------------------------
-- Visible functions
---------------------------------------------------------------------------
-- purpose: converts the negative index to a positive one
-- negative indices are illegal in 1164 and 1076.3
function to_sulv (
arg : UNRESOLVED_float) -- fp vector
return STD_ULOGIC_VECTOR
is
variable intermediate_result : UNRESOLVED_float(arg'length-1 downto 0);
begin -- function to_std_ulogic_vector
if arg'length < 1 then
return NSLV;
end if;
intermediate_result := arg;
return STD_ULOGIC_VECTOR (intermediate_result);
end function to_sulv;
-- Converts an fp into an SULV
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_slv;
-- purpose: normalizes a floating point number
-- This version assumes an "unsigned" input with
function normalize (
fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign BIT
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction
variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction
variable exp : SIGNED (exponent_width+1 downto 0); -- exponent
variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent
variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result
variable shiftr : INTEGER; -- shift amount
variable stickyx : STD_ULOGIC; -- version of sticky
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round, zerores, infres : BOOLEAN;
begin -- function normalize
zerores := false;
infres := false;
round := false;
shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1"
- fraction_width - nguard; -- subtract the length we want
exp := resize (expon, exp'length) + shiftr;
if (or (fract) = '0') then -- Zero
zerores := true;
elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)
or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then
if (exp >= -resize(expon_base, exp'length)-fraction_width-1)
and denormalize then
exp := -resize(expon_base, exp'length)-1;
shiftr := -to_integer (expon + expon_base); -- new shift
else -- return zero
zerores := true;
end if;
elsif (exp > expon_base-1) then -- infinity
infres := true;
end if;
if zerores then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif infres then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
sfract := fract srl shiftr; -- shift
if shiftr > 0 then
-- stickyx := sticky or (or (fract (shiftr-1 downto 0)));
stickyx := sticky or smallfract (fract, shiftr-1);
else
stickyx := sticky;
end if;
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
sticky => stickyx,
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp(rexp'range),
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp(rexp'range);
end if;
-- result
rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));
rexpon (exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := UNRESOLVED_float(rexpon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
result (exponent_width) := sign; -- sign BIT
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with a "size_res" input
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -size_res'low;
constant exponent_width : NATURAL := size_res'high;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- Regular "normalize" function with a "size_res" input.
function normalize (
fract : UNRESOLVED_UNSIGNED; -- unsigned
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
begin
return normalize (fract => fract,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
end function normalize;
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate
is
constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : INTEGER := x'high; -- length of FP output exponent
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- classfp
if (arg'length < 1 or fraction_width < 3 or exponent_width < 3
or x'left < x'right) then
report float_generic_pkg'instance_name
& "CLASSFP: " &
"Floating point number detected with a bad range"
severity error;
return isx;
end if;
-- Check for "X".
arg := to_01 (x, 'X');
if (arg(0) = 'X') then
return isx; -- If there is an X in the number
-- Special cases, check for illegal number
elsif check_error and
(and (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '1') then -- Exponent is all "1".
if or (to_slv (arg (-1 downto -fraction_width)))
/= '0' then -- Fraction must be all "0" or this is not a number.
if (arg(-1) = '1') then -- From "W. Khan - IEEE standard
return nan; -- 754 binary FP Signaling nan (Not a number)
else
return quiet_nan;
end if;
-- Check for infinity
elsif arg(exponent_width) = '0' then
return pos_inf; -- Positive infinity
else
return neg_inf; -- Negative infinity
end if;
-- check for "0"
elsif or (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '0' then -- Exponent is all "0"
if or (to_slv (arg (-1 downto -fraction_width)))
= '0' then -- Fraction is all "0"
if arg(exponent_width) = '0' then
return pos_zero; -- Zero
else
return neg_zero;
end if;
else
if arg(exponent_width) = '0' then
return pos_denormal; -- Denormal number (ieee extended fp)
else
return neg_denormal;
end if;
end if;
else
if arg(exponent_width) = '0' then
return pos_normal; -- Normal FP number
else
return neg_normal;
end if;
end if;
end function Classfp;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_UNSIGNED;
expon : out UNRESOLVED_SIGNED;
sign : out STD_ULOGIC) is
variable fptyp : valid_fpstate;
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => fract,
expon => expon);
end procedure break_number;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_ufixed; -- 1 downto -fraction_width
expon : out UNRESOLVED_SIGNED; -- exponent_width-1 downto 0
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => ufract,
expon => expon);
fract (0 downto -fraction_width) := ufixed (ufract);
end procedure break_number;
-- Arithmetic functions
function "abs" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := '0'; -- set the sign bit to positive
return result;
else
return NAFP;
end if;
end function "abs";
-- IEEE 754 "negative" function
function "-" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := not result (arg'high); -- invert sign bit
return result;
else
return NAFP;
end if;
end function "-";
-- Addition, adds two floating point numbers
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant addguard : NATURAL := guard; -- add one guard bit
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions
variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables
variable urfract, ulfract : UNSIGNED (fraction_width downto 0);
variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions
variable sign : STD_ULOGIC; -- sign of the output
variable leftright : BOOLEAN; -- left or right used
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- addition
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf and rfptype = neg_inf)
or (lfptype = neg_inf and rfptype = pos_inf) then
-- Return quiet NAN, IEEE754-1985-7.1,2
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0
fpresult := neg_zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl := (others => '0');
fractl (fraction_width+addguard downto addguard) := ulfract;
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr := (others => '0');
fractr (fraction_width+addguard downto addguard) := urfract;
shiftx := (exponl(exponent_width-1) & exponl) - exponr;
if shiftx < -fractl'high then
rexpon := exponr(exponent_width-1) & exponr;
fractc := fractr;
fracts := (others => '0'); -- add zero
leftright := false;
sticky := or (fractl);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (fractl, to_integer(shiftx));
fractc := fractr;
rexpon := exponr(exponent_width-1) & exponr;
leftright := false;
-- sticky := or (fractl (to_integer(shiftx) downto 0));
sticky := smallfract (fractl, to_integer(shiftx));
elsif shiftx = 0 then
rexpon := exponl(exponent_width-1) & exponl;
sticky := '0';
if fractr > fractl then
fractc := fractr;
fracts := fractl;
leftright := false;
else
fractc := fractl;
fracts := fractr;
leftright := true;
end if;
elsif shiftx > fractr'high then
rexpon := exponl(exponent_width-1) & exponl;
fracts := (others => '0'); -- add zero
fractc := fractl;
leftright := true;
sticky := or (fractr);
elsif shiftx > 0 then
fracts := shift_right (fractr, to_integer(shiftx));
fractc := fractl;
rexpon := exponl(exponent_width-1) & exponl;
leftright := true;
-- sticky := or (fractr (to_integer(shiftx) downto 0));
sticky := smallfract (fractr, to_integer(shiftx));
end if;
-- add
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if l(l'high) = r(r'high) then
ufract := fractc + fracts;
sign := l(l'high);
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
sign := l(l'high);
else
sign := r(r'high);
end if;
end if;
if or (ufract) = '0' then
sign := '0'; -- IEEE 854, 6.3, paragraph 2.
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => addguard);
end if;
return fpresult;
end function add;
-- Subtraction, Calls "add".
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable negr : UNRESOLVED_float (r'range); -- negative version of r
begin
negr := -r; -- r := -r
return add (l => l,
r => negr,
round_style => round_style,
guard => guard,
check_error => check_error,
denormalize => denormalize);
end function subtract;
-- Floating point multiply
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant multguard : NATURAL := guard; -- guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction
variable shifty : INTEGER; -- denormal shift
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif ((lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
fpresult (exponent_width) := fp_sign;
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
rfract := fractl * fractr; -- Multiply the fraction
sfract := rfract (rfract'high downto
rfract'high - (fraction_width+1+multguard));
sticky := or (rfract (rfract'high-(fraction_width+1+multguard)
downto 0));
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => multguard);
end if;
return fpresult;
end function multiply;
function short_divide (
lx, rx : UNSIGNED)
return UNSIGNED
is
-- This is a special divider for the floating point routines.
-- For a true unsigned divider, "stages" needs to = lx'high
constant stages : INTEGER := lx'high - rx'high; -- number of stages
variable partial : UNSIGNED (lx'range);
variable q : UNSIGNED (stages downto 0);
variable partial_argl : SIGNED (rx'high + 2 downto 0);
variable partial_arg : SIGNED (rx'high + 2 downto 0);
begin
partial := lx;
for i in stages downto 0 loop
partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)),
partial_argl'length);
partial_arg := partial_argl - SIGNED ("0" & rx);
if (partial_arg (partial_arg'high) = '1') then -- negative
q(i) := '0';
else
q(i) := '1';
partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=
UNSIGNED (partial_arg(rx'range));
end if;
end loop;
-- to make the output look like that of the unsigned IEEE divide.
return resize (q, lx'length);
end function short_divide;
-- 1/X function. Needed for algorithm development.
function reciprocal (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant divguard : NATURAL := guard; -- guard bits
function onedivy (
arg : UNSIGNED)
return UNSIGNED
is
variable q : UNSIGNED((2*arg'high)+1 downto 0);
variable one : UNSIGNED (q'range);
begin
one := (others => '0');
one(one'high) := '1';
q := short_divide (one, arg); -- Unsigned divide
return resize (q, arg'length+1);
end function onedivy;
variable fptype : valid_fpstate;
variable expon : SIGNED (exponent_width-1 downto 0); -- exponents
variable denorm_offset : NATURAL range 0 to 2;
variable fract : UNSIGNED (fraction_width downto 0);
variable fractg : UNSIGNED (fraction_width+divguard downto 0);
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- reciprocal
fptype := Classfp(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- 1/inf, return 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_zero | pos_zero => -- 1/0
report float_generic_pkg'instance_name
& "RECIPROCAL: Floating Point divide by zero"
severity error;
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
if (fptype = pos_denormal or fptype = neg_denormal)
and ((arg (-1) or arg(-2)) /= '1') then
-- 1/denormal = infinity, with the exception of 2**-expon_base
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult (exponent_width) := to_x01 (arg (exponent_width));
else
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => fract,
expon => expon);
fractg := (others => '0');
if (fptype = pos_denormal or fptype = neg_denormal) then
-- The reciprocal of a denormal number is typically zero,
-- except for two special cases which are trapped here.
if (to_x01(arg (-1)) = '1') then
fractg (fractg'high downto divguard+1) :=
fract (fract'high-1 downto 0); -- Shift to not denormal
denorm_offset := 1; -- add 1 to exponent compensate
else -- arg(-2) = '1'
fractg (fractg'high downto divguard+2) :=
fract (fract'high-2 downto 0); -- Shift to not denormal
denorm_offset := 2; -- add 2 to exponent compensate
end if;
else
fractg (fractg'high downto divguard) := fract;
denorm_offset := 0;
end if;
expon := - expon - 3 + denorm_offset;
sfract := onedivy (fractg);
-- normalize
fpresult := normalize (fract => sfract,
expon => expon,
sign => arg(exponent_width),
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end if;
end case classcase;
return fpresult;
end function reciprocal;
-- floating point division
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left
variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractl'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign, sticky : STD_ULOGIC; -- sign of result
variable shifty, shiftx : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divide
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf -- inf / inf
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_generic_pkg'instance_name
& "DIVIDE: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
-- Compute the exponent
rexpon := resize (exponl, rexpon'length) - exponr - 2;
if (rfptype = pos_denormal or rfptype = neg_denormal) then
-- Do the shifting here not after. That way we have a smaller
-- shifter, and need a smaller divider, because the top
-- bit in the divisor will always be a "1".
shifty := fraction_width - find_leftmost(urfract, '1');
urfract := shift_left (urfract, shifty);
rexpon := rexpon + shifty;
end if;
fractr := (others => '0');
fractr (fraction_width+divguard downto divguard) := urfract;
if (lfptype = pos_denormal or lfptype = neg_denormal) then
shiftx := fraction_width - find_leftmost(ulfract, '1');
ulfract := shift_left (ulfract, shiftx);
rexpon := rexpon - shiftx;
end if;
fractl := (others => '0');
fractl (fractl'high downto fractl'high-fraction_width) := ulfract;
-- divide
rfract := short_divide (fractl, fractr); -- unsigned divide
sfract := rfract (sfract'range); -- lower bits
sticky := '1';
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end case classcase2;
end case classcase;
return fpresult;
end function divide;
-- division by a power of 2
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divisionbyp2
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_generic_pkg'instance_name
& "DIVIDEBYP2: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
assert (or (urfract (fraction_width-1 downto 0)) = '0')
report float_generic_pkg'instance_name
& "DIVIDEBYP2: "
& "Dividebyp2 called with a non power of two divisor"
severity error;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 1;
-- normalize
fpresult := normalize (fract => ulfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase2;
end case classcase;
return fpresult;
end function dividebyp2;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL :=
-mine (mine(l'low, r'low), c'low); -- length of FP output fraction
constant exponent_width : NATURAL :=
maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent
variable lfptype, rfptype, cfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable fractx : UNSIGNED (fraction_width+guard downto 0);
variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction
variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent
variable shifty : INTEGER; -- denormal shift
variable shiftx : SIGNED (rexpon'range); -- shift fractions
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);
variable leftright : BOOLEAN; -- left or right used
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
cfptype := Classfp (c, check_error);
end if;
if (lfptype = isx or rfptype = isx or cfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
cfptype = nan or cfptype = quiet_nan) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf
or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
cresize := resize (arg => to_X01(c),
exponent_width => exponent_width,
fraction_width => -cresize'low,
denormalize_in => denormalize,
denormalize => denormalize);
cfptype := Classfp (cresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
break_number (
arg => cresize,
fptyp => cfptype,
denormalize => denormalize,
fract => fractx,
expon => exponc);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
shiftx := rexpon - exponc;
if shiftx < -fractl'high then
rexpon2 := resize (exponc, rexpon2'length);
fractc := "0" & fractx;
fracts := (others => '0');
sticky := or (rfract);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (rfract (rfract'high downto rfract'high
- fracts'length+1),
to_integer(shiftx));
fractc := "0" & fractx;
rexpon2 := resize (exponc, rexpon2'length);
leftright := false;
sticky := or (rfract (to_integer(shiftx)+rfract'high
- fracts'length downto 0));
elsif shiftx = 0 then
rexpon2 := resize (exponc, rexpon2'length);
sticky := or (rfract (rfract'high - fractc'length downto 0));
if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx
then
fractc := "0" & fractx;
fracts := rfract (rfract'high downto rfract'high
- fracts'length+1);
leftright := false;
else
fractc := rfract (rfract'high downto rfract'high
- fractc'length+1);
fracts := "0" & fractx;
leftright := true;
end if;
elsif shiftx > fractx'high then
rexpon2 := rexpon;
fracts := (others => '0');
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or (fractx & rfract (rfract'high - fractc'length
downto 0));
else -- fractx'high > shiftx > 0
rexpon2 := rexpon;
fracts := "0" & shift_right (fractx, to_integer (shiftx));
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or (fractx (to_integer (shiftx) downto 0)
& rfract (rfract'high - fractc'length downto 0));
end if;
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if fp_sign = to_X01(c(c'high)) then
ufract := fractc + fracts;
fp_sign := fp_sign;
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
fp_sign := fp_sign;
else
fp_sign := c(c'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon2,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end if;
return fpresult;
end function mac;
-- "rem" function
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractr'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (abs(l) < abs(r)) then
fpresult := l;
else
fp_sign := to_X01(l(l'high)); -- sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fraction_width+divguard downto divguard) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponr(exponr'high)&exponr);
shifty := to_integer(exponl - rexpon);
if (shifty > 0) then
fractr := shift_right (fractr, shifty);
rexpon := rexpon + shifty;
end if;
if (fractr /= 0) then
-- rem
rfract := fractl rem fractr; -- unsigned rem
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
else
-- If we shift "fractr" so far that it becomes zero, return zero.
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
end if;
return fpresult;
end function remainder;
-- "mod" function
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
remres := remainder (l => abs(l),
r => abs(r),
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
-- MOD is the same as REM, but you do something different with
-- negative values
if (Is_Negative (l)) then
remres := - remres;
end if;
if (Is_Negative (l) = Is_Negative (r) or remres = 0) then
fpresult := remres;
else
fpresult := add (l => remres,
r => r,
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
end if;
end if;
return fpresult;
end function modulo;
-- Square root of a floating point number. Done using Newton's Iteration.
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable sign : STD_ULOGIC;
variable fpresult : float (arg'range);
variable fptype : valid_fpstate;
variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents
variable expon : SIGNED(exponent_width downto 0); -- exponents
variable ufact : ufixed (0 downto arg'low);
variable fact : ufixed (2 downto -fraction_width); -- fraction
variable resb : ufixed (fact'high+1 downto fact'low);
begin -- square root
fptype := Classfp (arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan |
-- Return quiet NAN, IEEE754-1985-7.1,1
neg_normal | neg_denormal | neg_inf => -- sqrt (neg)
-- Return quiet NAN, IEEE754-1985-7.1.6
fpresult := qnanfp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_inf => -- Sqrt (inf), return infinity
fpresult := pos_inffp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_zero => -- return 0
fpresult := zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when neg_zero => -- IEEE754-1985-6.3 return -0
fpresult := neg_zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when others =>
break_number (arg => arg,
denormalize => denormalize,
check_error => false,
fract => ufact,
expon => iexpon,
sign => sign);
expon := resize (iexpon+1, expon'length); -- get exponent
fact := resize (ufact, fact'high, fact'low);
if (expon(0) = '1') then
fact := fact sla 1; -- * 2.0
end if;
expon := shift_right (expon, 1); -- exponent/2
-- Newton's iteration - root := (1 + arg) / 2
resb := (fact + 1) sra 1;
for j in 0 to fraction_width/4 loop
-- root := (root + (arg/root))/2
resb := resize (arg => (resb + (fact/resb)) sra 1,
left_index => resb'high,
right_index => resb'low,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
end loop;
fpresult := normalize (fract => resb,
expon => expon-1,
sign => '0',
exponent_width => arg'high,
fraction_width => -arg'low,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end case classcase;
return fpresult;
end function sqrt;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is
-- Technically -0 should return "false", but I'm leaving that case out.
begin
return (to_x01(arg(arg'high)) = '1');
end function Is_Negative;
-- compare functions
-- =, /=, >=, <=, <, >
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : BOOLEAN;
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- equal
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return false;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := true;
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
is_equal := (to_slv(lresize) = to_slv(rresize));
end if;
if (check_error) then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_equal and not is_unordered;
end function eq;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_less_than, is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_less_than := false;
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (fractl < fractr);
else
is_less_than := (fractl > fractr); -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (expl < expr);
else
is_less_than := (expl > expr); -- negative
end if;
end if;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
if (lfptype = neg_zero and rfptype = pos_zero) then
is_less_than := false; -- -0 < 0 returns false.
else
is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_less_than and not is_unordered;
end function lt;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_greater_than : BOOLEAN;
variable is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- greater_than
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_greater_than := false;
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := fractl > fractr;
else
is_greater_than := fractl < fractr; -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := expl > expr;
else
is_greater_than := expl < expr; -- negative
end if;
end if;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
if (lfptype = pos_zero and rfptype = neg_zero) then
is_greater_than := false; -- 0 > -0 returns false.
else
is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_greater_than and not is_unordered;
end function gt;
-- purpose: /= function
function ne ( -- not equal /=
l, r : UNRESOLVED_float;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_equal, is_unordered : BOOLEAN;
begin
is_equal := eq (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not (is_equal and not is_unordered);
end function ne;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_greater_than, is_unordered : BOOLEAN;
begin
is_greater_than := gt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_greater_than and not is_unordered;
end function le;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_less_than, is_unordered : BOOLEAN;
begin
is_less_than := lt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_less_than and not is_unordered;
end function ge;
function "?=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?=
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
lfptype := Classfp (L, float_check_error);
rfptype := Classfp (R, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => L,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => R,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := to_sulv(lresize) ?= to_sulv(rresize);
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return is_equal and not is_unordered;
end function "?=";
function "?/=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?/=
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
lfptype := Classfp (L, float_check_error);
rfptype := Classfp (R, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => L,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => R,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := to_sulv(lresize) ?= to_sulv(rresize);
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return not (is_equal and not is_unordered);
end function "?/=";
function "?>" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?>"": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L > R then
return '1';
else
return '0';
end if;
end if;
end function "?>";
function "?>=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?>="": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L >= R then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
function "?<" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?<"": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L < R then
return '1';
else
return '0';
end if;
end if;
end function "?<";
function "?<=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?<="": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L <= R then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
function std_match (L, R : UNRESOLVED_float) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
report float_generic_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
-- These override the defaults for the compare operators.
function "=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return eq(l, r);
end function "=";
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ne(l, r);
end function "/=";
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ge(l, r);
end function ">=";
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return le(l, r);
end function "<=";
function ">" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return gt(l, r);
end function ">";
function "<" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return lt(l, r);
end function "<";
-- purpose: maximum of two numbers (overrides default)
function maximum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (L, exponent_width, fraction_width);
rresize := resize (R, exponent_width, fraction_width);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (L, exponent_width, fraction_width);
rresize := resize (R, exponent_width, fraction_width);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
-----------------------------------------------------------------------------
-- conversion functions
-----------------------------------------------------------------------------
-- Converts a floating point number of one format into another format
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
-- result value
variable fptype : valid_fpstate;
variable expon_in : SIGNED (in_exponent_width-1 downto 0);
variable fract_in : UNSIGNED (in_fraction_width downto 0);
variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract
variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract
begin
fptype := Classfp(arg, check_error);
if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in
and (in_exponent_width < exponent_width
or in_fraction_width < fraction_width))
or in_exponent_width > exponent_width
or in_fraction_width > fraction_width then
-- size reduction
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf =>
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_inf =>
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero =>
result := zerofp (fraction_width => fraction_width, -- hate -0
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize_in,
fract => fract_in,
expon => expon_in);
if fraction_width > in_fraction_width and denormalize_in then
-- You only get here if you have a denormal input
fract_out := (others => '0'); -- pad with zeros
fract_out (fraction_width downto
fraction_width - in_fraction_width) := fract_in;
result := normalize (
fract => fract_out,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
else
result := normalize (
fract => fract_in,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => in_fraction_width - fraction_width);
end if;
end case classcase;
else -- size increase or the same size
if exponent_width > in_exponent_width then
expon_in := SIGNED(arg (in_exponent_width-1 downto 0));
if fptype = pos_zero or fptype = neg_zero then
result (exponent_width-1 downto 0) := (others => '0');
elsif expon_in = -1 then -- inf or nan (shorts out check_error)
result (exponent_width-1 downto 0) := (others => '1');
else
-- invert top BIT
expon_in(expon_in'high) := not expon_in(expon_in'high);
expon_out := resize (expon_in, expon_out'length); -- signed expand
-- Flip it back.
expon_out(expon_out'high) := not expon_out(expon_out'high);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);
end if;
result (exponent_width) := arg (in_exponent_width); -- sign
else -- exponent_width = in_exponent_width
result (exponent_width downto 0) := arg (in_exponent_width downto 0);
end if;
if fraction_width > in_fraction_width then
result (-1 downto -fraction_width) := (others => '0'); -- zeros
result (-1 downto -in_fraction_width) :=
arg (-1 downto -in_fraction_width);
else -- fraction_width = in_fraciton_width
result (-1 downto -fraction_width) :=
arg (-1 downto -in_fraction_width);
end if;
end if;
return result;
end function resize;
function resize (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
return result;
end if;
end function resize;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32 is
begin
return resize (arg => arg,
exponent_width => float32'high,
fraction_width => -float32'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64 is
begin
return resize (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128 is
begin
return resize (arg => arg,
exponent_width => float128'high,
fraction_width => -float128'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float128;
-- to_float (Real)
-- typically not Synthesizable unless the input is a constant.
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_real : REAL; -- Real version of argument
variable validfp : boundary_type; -- Check for valid results
variable exp : INTEGER; -- Integer version of exponent
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable frac : REAL; -- Real version of fraction
constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding
variable round : BOOLEAN; -- to round or not to round
begin
result := (others => '0');
arg_real := arg;
if arg_real < 0.0 then
result (exponent_width) := '1';
arg_real := - arg_real; -- Make it positive.
else
result (exponent_width) := '0';
end if;
test_boundary (arg => arg_real,
fraction_width => fraction_width,
exponent_width => exponent_width,
denormalize => denormalize,
btype => validfp,
log2i => exp);
if validfp = zero then
return result; -- Result initialized to "0".
elsif validfp = infinity then
result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1"
-- return infinity.
return result;
else
if validfp = denormal then -- Exponent will default to "0".
expon := (others => '0');
frac := arg_real * (2.0 ** (to_integer(expon_base)-1));
else -- Number less than 1. "normal" number
expon := UNSIGNED (to_signed (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.
end if;
for i in 0 to fract'high loop
if frac >= 2.0 ** (-1 - i) then
fract (fract'high - i) := '1';
frac := frac - 2.0 ** (-1 - i);
else
fract (fract'high - i) := '0';
end if;
end loop;
round := false;
case round_style is
when round_nearest =>
if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if frac /= 0.0 and result(exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if frac /= 0.0 and result(exponent_width) = '1' then
round := true;
end if;
when others =>
null; -- don't round
end case;
if (round) then
if and(fract) = '1' then -- fraction is all "1"
expon := expon + 1;
fract := (others => '0');
else
fract := fract + 1;
end if;
end if;
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
return result;
end if;
end function to_float;
-- to_float (Integer)
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : NATURAL; -- Natural version of argument
variable expon : SIGNED (exponent_width-1 downto 0);
variable exptmp : SIGNED (exponent_width-1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');
variable fracttmp : UNSIGNED (fraction_width-1 downto 0);
variable round : BOOLEAN;
variable shift : NATURAL;
variable shiftr : NATURAL;
variable roundfrac : NATURAL; -- used in rounding
begin
if arg < 0 then
result (exponent_width) := '1';
arg_int := -arg; -- Make it positive.
else
result (exponent_width) := '0';
arg_int := arg;
end if;
if arg_int = 0 then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- If the number is larger than we can represent in this number system
-- we need to return infinity.
shift := log2(arg_int);
if shift > to_integer(expon_base) then
-- worry about infinity
if result (exponent_width) = '0' then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- return negative infinity.
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
else -- Normal number (can't be denormal)
-- Compute Exponent
expon := to_signed (shift-1, expon'length); -- positive fraction.
-- Compute Fraction
arg_int := arg_int - 2**shift; -- Subtract off the 1.0
shiftr := shift;
for I in fract'high downto maximum (fract'high - shift + 1, 0) loop
shiftr := shiftr - 1;
if (arg_int >= 2**shiftr) then
arg_int := arg_int - 2**shiftr;
fract(I) := '1';
else
fract(I) := '0';
end if;
end loop;
-- Rounding routine
round := false;
if arg_int > 0 then
roundfrac := 2**(shiftr-1);
case round_style is
when round_nearest =>
if arg_int > roundfrac or
((arg_int = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if arg_int /= 0 and result (exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if arg_int /= 0 and result (exponent_width) = '1' then
round := true;
end if;
when others =>
null;
end case;
end if;
if round then
fp_round(fract_in => fract,
expon_in => expon,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
expon := exptmp;
end if;
-- Put the number together and return
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
end if;
return result;
end function to_float;
-- to_float (unsigned)
function to_float (
arg : UNRESOLVED_UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := arg'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is arg;
variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg
begin
if arg'length < 1 then
return NAFP;
end if;
sarg (XARG'range) := SIGNED (XARG);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style);
return result;
end function to_float;
-- to_float (signed)
function to_float (
arg : UNRESOLVED_SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := arg'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is arg;
variable arg_int : UNSIGNED(XARG'range); -- Real version of argument
variable argb2 : UNSIGNED(XARG'high/2 downto 0); -- log2 of input
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable rfract : UNSIGNED (fraction_width-1 downto 0);
variable sign : STD_ULOGIC; -- sign bit
begin
if arg'length < 1 then
return NAFP;
end if;
if Is_X (XARG) then
result := (others => 'X');
elsif (XARG = 0) then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- Normal number (can't be denormal)
sign := to_X01(XARG (XARG'high));
arg_int := UNSIGNED(abs (to_01(XARG)));
-- Compute Exponent
argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2
if argb2 > UNSIGNED(expon_base) then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
result (exponent_width) := sign;
else
exp := SIGNED(resize(argb2, exp'length));
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract (0),
sign => sign,
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := (others => '0');
rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
result (exponent_width) := sign;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
end if;
return result;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float
is
variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if arg'length < 1 then
return NAFP;
end if;
fpvar := UNRESOLVED_float(arg);
return fpvar;
end function to_float;
-- purpose: converts a ufixed to a floating point
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float
is
variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- function to_float
if (arg'length < 1) then
return NAFP;
end if;
sarg (arg'range) := sfixed (arg);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style,
denormalize => denormalize);
return result;
end function to_float;
function to_float (
arg : UNRESOLVED_sfixed; -- signed fixed point
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float
is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : sfixed (integer_width downto in_fraction_width);
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width
downto 0); -- unsigned version of argument
variable argx : SIGNED (integer_width - in_fraction_width downto 0);
variable exp, exptmp : SIGNED (exponent_width + 1 downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin
if (arg'length < 1) then
return NAFP;
end if;
xresult := to_01(arg, 'X');
argx := SIGNED(to_slv(xresult));
if (Is_X (arg)) then
result := (others => 'X');
elsif (argx = 0) then
result := (others => '0');
else
result := (others => '0'); -- zero out the result
if argx(argx'left) = '1' then -- toss the sign bit
result (exponent_width) := '1'; -- Negative number
arg_int := UNSIGNED(to_x01(not STD_LOGIC_VECTOR (argx))) + 1; -- Make it positive with two's complement
else
result (exponent_width) := '0';
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx))); -- new line: direct conversion to unsigned
end if;
-- Compute Exponent
exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result (-1 downto -fraction_width) := (others => '0');
result (exponent_width -1 downto 0) := (others => '1');
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize(exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
return result;
end function to_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- to_integer (float)
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER
is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (-arg'low downto 0); -- Fraction
variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction
variable expon : SIGNED (arg'high-1 downto 0);
variable isign : STD_ULOGIC; -- internal version of sign
variable round : STD_ULOGIC; -- is rounding needed?
variable result : INTEGER;
variable base : INTEGER; -- Integer exponent
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := 0; -- return 0
when pos_inf =>
result := INTEGER'high;
when neg_inf =>
result := INTEGER'low;
when others =>
break_number (
arg => arg,
fptyp => validfp,
denormalize => false,
fract => frac,
expon => expon);
fract (fract'high) := '0'; -- Add extra bit for 0.6 case
fract (fract'high-1 downto 0) := frac;
isign := to_x01 (arg (arg'high));
base := to_integer (expon) + 1;
if base < -1 then
result := 0;
elsif base >= frac'high then
result := to_integer (fract) * 2**(base - frac'high);
else -- We need to round
if base = -1 then -- trap for 0.6 case.
result := 0;
else
result := to_integer (fract (frac'high downto frac'high-base));
end if;
-- rounding routine
case round_style is
when round_nearest =>
if frac'high - base > 1 then
round := fract (frac'high - base - 1) and
(fract (frac'high - base)
or (or (fract (frac'high - base - 2 downto 0))));
else
round := fract (frac'high - base - 1) and
fract (frac'high - base);
end if;
when round_inf =>
round := fract(frac'high - base - 1) and not isign;
when round_neginf =>
round := fract(frac'high - base - 1) and isign;
when others =>
round := '0';
end case;
if round = '1' then
result := result + 1;
end if;
end if;
if isign = '1' then
result := - result;
end if;
end case classcase;
return result;
end function to_integer;
-- to_unsigned (float)
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED
is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction
variable sign : STD_ULOGIC; -- not used
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1');
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
end case classcase;
return (frac);
end function to_unsigned;
-- to_signed (float)
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED
is
variable sign : STD_ULOGIC; -- true if negative
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction
variable result : UNRESOLVED_SIGNED (size-1 downto 0);
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := (others => '0'); -- return 0
when pos_inf =>
result := (others => '1');
result (result'high) := '0';
when neg_inf =>
result := (others => '0');
result (result'high) := '1';
when others =>
float_to_unsigned (
arg => arg,
sign => sign,
frac => frac,
denormalize => false,
bias => 0,
round_style => round_style);
result (size-1) := '0';
result (size-2 downto 0) := UNRESOLVED_SIGNED(frac (size-2 downto 0));
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if frac(frac'high) = '1' then -- return most negative number
result := (others => '0');
result (result'high) := '1';
else
result := -result;
end if;
else
if frac(frac'high) = '1' then -- return most positive number
result := (others => '1');
result (result'high) := '0';
end if;
end if;
end case classcase;
return result;
end function to_signed;
-- purpose: Converts a float to ufixed
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);
variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result
begin -- function to_ufixed
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1'); -- always saturate
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
-- Figure out the fraction
if (validfp = pos_denormal) and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Remove the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
end case classcase;
result_big := to_ufixed (
arg => STD_ULOGIC_VECTOR(frac),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- purpose: Converts a float to sfixed
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable sign : BOOLEAN; -- true if negative
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable rsigned : SIGNED (size-1 downto 0); -- signed version of result
variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);
variable result : UNRESOLVED_sfixed (left_index downto right_index)
:= (others => '0'); -- result
begin -- function to_sfixed
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero =>
result := (others => '0'); -- return 0
when neg_inf =>
result (left_index) := '1'; -- return smallest negative number
when pos_inf =>
result := (others => '1'); -- return largest number
result (left_index) := '0';
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
if arg(exponent_width) = '0' then
sign := false;
else
sign := true;
end if;
-- Figure out the fraction
if (validfp = pos_denormal or validfp = neg_denormal)
and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
if not sign then
rsigned := SIGNED("0" & frac);
else
rsigned := -(SIGNED("0" & frac));
end if;
result_big := to_sfixed (
arg => STD_LOGIC_VECTOR(rsigned),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
end case classcase;
return result;
end function to_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED
is
variable result : UNRESOLVED_UNSIGNED (size_res'range);
begin
if (size_res'length = 0) then
return result;
else
result := to_unsigned (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_unsigned;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED
is
variable result : UNRESOLVED_SIGNED (size_res'range);
begin
if (size_res'length = 0) then
return result;
else
result := to_signed (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_signed;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_sfixed;
-- to_real (float)
-- typically not Synthesizable unless the input is a constant.
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable validfp : valid_fpstate; -- Valid FP state
variable expon : UNSIGNED (exponent_width - 1 downto 0)
:= (others => '1'); -- Vectorized exponent
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | pos_zero | neg_zero | nan | quiet_nan =>
return 0.0;
when neg_inf =>
return REAL'low; -- Negative infinity.
when pos_inf =>
return REAL'high; -- Positive infinity
when others =>
expon_base := 2**(exponent_width-1) -1;
if to_X01(arg(exponent_width)) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
-- Figure out the fraction
for i in 0 to fraction_width-1 loop
if to_X01(arg (-1 - i)) = '1' then
frac := frac + (2.0 **(-1 - i));
end if;
end loop; -- i
if validfp = pos_normal or validfp = neg_normal or not denormalize then
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
sign := sign * (2.0 ** exp) * (1.0 + frac);
else -- exponent = '0', IEEE extended floating point
exp := 1 - expon_base;
sign := sign * (2.0 ** exp) * frac;
end if;
return sign;
end case classcase;
end function to_real;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_sulv (result);
end function realtobits;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
-- purpose: Removes meta-logical values from FP string
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range);
begin -- function to_01
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_01: null detected, returning NULL"
severity warning;
return NAFP;
end if;
result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));
return result;
end function to_01;
function Is_X
(arg : UNRESOLVED_float)
return BOOLEAN is
begin
return Is_X (to_slv(arg));
end function Is_X;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_X01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01(to_slv(arg)));
return result;
end if;
end function to_X01;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_X01Z: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01Z(to_slv(arg)));
return result;
end if;
end function to_X01Z;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_UX01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_UX01(to_slv(arg)));
return result;
end if;
end function to_UX01;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return add (l, r);
end function "+";
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return subtract (l, r);
end function "-";
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return multiply (l, r);
end function "*";
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return divide (l, r);
end function "/";
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return remainder (l, r);
end function "rem";
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return modulo (l, r);
end function "mod";
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
-- ?= overloads
function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?= r_float;
end function "?=";
function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?/= r_float;
end function "?/=";
function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?> r_float;
end function "?>";
function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?>= r_float;
end function "?>=";
function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?< r_float;
end function "?<";
function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?<= r_float;
end function "?<=";
-- real and float
function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?= r;
end function "?=";
function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?/= r;
end function "?/=";
function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?> r;
end function "?>";
function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?>= r;
end function "?>=";
function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?< r;
end function "?<";
function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?<= r;
end function "?<=";
-- ?= overloads
function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?= r_float;
end function "?=";
function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?/= r_float;
end function "?/=";
function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?> r_float;
end function "?>";
function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?>= r_float;
end function "?>=";
function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?< r_float;
end function "?<";
function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?<= r_float;
end function "?<=";
-- integer and float
function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?= r;
end function "?=";
function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?/= r;
end function "?/=";
function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?> r;
end function "?>";
function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?>= r;
end function "?>=";
function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?< r;
end function "?<";
function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?<= r;
end function "?<=";
-- minimum and maximum overloads
function minimum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
function minimum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_float (RESULT, L'high, -L'low);
end function "not";
function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "and";
function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L and to_sulv(R));
return result;
end function "and";
function "and" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) and R);
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L or to_sulv(R));
return result;
end function "or";
function "or" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) or R);
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L nand to_sulv(R));
return result;
end function "nand";
function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) nand R);
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L nor to_sulv(R));
return result;
end function "nor";
function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) nor R);
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L xor to_sulv(R));
return result;
end function "xor";
function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) xor R);
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L xnor to_sulv(R));
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) xnor R);
return result;
end function "xnor";
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return and to_sulv(l);
end function "and";
function "nand" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nand to_sulv(l);
end function "nand";
function "or" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return or to_sulv(l);
end function "or";
function "nor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nor to_sulv(l);
end function "nor";
function "xor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xor to_sulv(l);
end function "xor";
function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xnor to_sulv(l);
end function "xnor";
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (
x, y : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
begin
return y(y'high) & x (x'high-1 downto x'low);
end function Copysign;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction
constant exponent_width : NATURAL := y'high; -- length of FP output exponent
variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
variable exp : SIGNED (exponent_width downto 0);
variable ufract : UNSIGNED (fraction_width downto 0);
variable fptype : valid_fpstate;
begin
-- This can be done by simply adding N to the exponent.
arg := to_01 (y, 'X');
fptype := Classfp(arg, check_error);
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => ufract,
expon => expon);
exp := resize (expon, exp'length) + N;
result := normalize (
fract => ufract,
expon => exp,
sign => to_x01 (arg (arg'high)),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase;
return result;
end function Scalb;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : UNRESOLVED_SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable n_int : INTEGER;
begin
n_int := to_integer(N);
return Scalb (y => y,
N => n_int,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
end function Scalb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return INTEGER
is
constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : INTEGER; -- result
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width - 1 downto 0);
variable fract : UNSIGNED (fraction_width downto 0);
constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent
-- offset +1
variable fptype : valid_fpstate;
begin
-- Just return the exponent.
arg := to_01 (x, 'X');
fptype := Classfp(arg);
classcase : case fptype is
when isx | nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := 0;
when pos_denormal | neg_denormal =>
fract (fraction_width) := '0';
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
result := find_leftmost (fract, '1') -- Find the first "1"
- fraction_width; -- subtract the length we want
result := -expon_base + 1 + result;
when others =>
expon := SIGNED(arg (exponent_width - 1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
expon := expon + 1;
result := to_integer (expon);
end case classcase;
return result;
end function Logb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return UNRESOLVED_SIGNED
is
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : SIGNED (exponent_width - 1 downto 0); -- result
begin
-- Just return the exponent.
result := to_signed (Logb (x), exponent_width);
return result;
end function Logb;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
function "=" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function "="
return eq (l => l,
r => r,
check_error => false);
end function "=";
function ">" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function ">"
return gt (l => l,
r => r,
check_error => false);
end function ">";
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable expon : UNSIGNED (exponent_width-1 downto 0);
variable sign : STD_ULOGIC;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable validfpx, validfpy : valid_fpstate; -- Valid FP state
begin -- fp_Nextafter
-- If Y > X, add one to the fraction, otherwise subtract.
validfpx := Classfp (x, check_error);
validfpy := Classfp (y, check_error);
if validfpx = isx or validfpy = isx then
result := (others => 'X');
return result;
elsif (validfpx = nan or validfpy = nan) then
return nanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (validfpx = quiet_nan or validfpy = quiet_nan) then
return qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif x = y then -- Return X
return x;
else
fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction
expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent
sign := x(exponent_width); -- sign bit
if (y > x) then
-- Increase the number given
if validfpx = neg_inf then
-- return most negative number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero or validfpx = neg_zero then
-- return smallest denormal number
sign := '0';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = pos_normal then
if and (fract) = '1' then -- fraction is all "1".
if and (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert no_warning
report float_generic_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1;
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = pos_denormal then
if and (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = neg_normal then
if or (fract) = '0' then -- fraction is all "0".
if or (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest negative denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = neg_denormal then
if or (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
else
-- Decrease the number
if validfpx = pos_inf then
-- return most positive number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero
or Classfp (x) = neg_zero then
-- return smallest negative denormal number
sign := '1';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = neg_normal then
if and (fract) = '1' then -- fraction is all "1".
if and (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert no_warning
report float_generic_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1; -- Fraction overflow
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = neg_denormal then
if and (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = pos_normal then
if or (fract) = '0' then -- fraction is all "0".
if or (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest positive denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = pos_denormal then
if or (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
end if;
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);
result (exponent_width) := sign;
return result;
end if;
end function Nextafter;
-- Returns True if X is unordered with Y.
function Unordered (
x, y : UNRESOLVED_float) -- floating point input
return BOOLEAN
is
variable lfptype, rfptype : valid_fpstate;
begin
lfptype := Classfp (x);
rfptype := Classfp (y);
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
lfptype = isx or rfptype = isx) then
return true;
else
return false;
end if;
end function Unordered;
function Finite (
x : UNRESOLVED_float)
return BOOLEAN
is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = pos_inf) or (fp_state = neg_inf) then
return true;
else
return false;
end if;
end function Finite;
function Isnan (
x : UNRESOLVED_float)
return BOOLEAN
is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = nan) or (fp_state = quiet_nan) then
return true;
else
return false;
end if;
end function Isnan;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
return result;
end function zerofp;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-1) := '1'; -- MSB of Fraction "1"
-- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point"
-- The difference between a signaling NAN and a quiet NAN is that
-- the MSB of the Fraction is a "1" in a Signaling NAN, and is a
-- "0" in a quiet NAN.
return result;
end function nanfp;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-fraction_width) := '1'; -- LSB of Fraction "1"
-- (Could have been any bit)
return result;
end function qnanfp;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1"
return result;
end function pos_inffp;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width downto 0) := (others => '1'); -- top bits all "1"
return result;
end function neg_inffp;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width) := '1';
return result;
end function neg_zerofp;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function zerofp;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return nanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function nanfp;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return qnanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function qnanfp;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return pos_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function pos_inffp;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_inffp;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_zerofp;
-- Textio functions
-- purpose: writes float into a line (NOTE changed basetype)
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable c : CHARACTER;
variable left : positive;
begin
while L /= null and L.all'length /= 0 loop
left := L.all'left;
c := L.all(left);
if (c = ' ' or c = NBSP or c = HT) then
read (L, c);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- purpose: Checks the punctuation in a line
procedure check_punctuation (
arg : in STRING;
colon : out BOOLEAN; -- There was a colon in the line
dot : out BOOLEAN; -- There was a dot in the line
good : out BOOLEAN; -- True if enough characters found
chars : in INTEGER) is
-- Examples. Legal inputs are "0000000", "0000.000", "0:000:000"
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable icolon, idot : BOOLEAN; -- internal
variable j : INTEGER := 0; -- charters read
begin
good := false;
icolon := false;
idot := false;
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then
exit;
elsif xarg(i) = ':' then
icolon := true;
elsif xarg(i) = '.' then
idot := true;
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
if j = chars then
good := true; -- There are enough charactes to read
end if;
colon := icolon;
if idot and icolon then
dot := false;
else
dot := idot;
end if;
end procedure check_punctuation;
-- purpose: Searches a line for a ":" and replaces it with a ".".
procedure fix_colon (
arg : inout STRING;
chars : in integer) is
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable j : INTEGER := 0; -- charters read
begin
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then
exit;
elsif xarg(i) = ':' then
xarg (i) := '.';
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
end procedure fix_colon;
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_float; -- floating point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'high - VALUE'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
WRITE (L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable readOk : BOOLEAN;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
READ (L, c, readOk);
if VALUE'length > 0 then
i := VALUE'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report float_generic_pkg'instance_name
& "READ(float): "
& "Error end of file encountered."
severity error;
return;
elsif c = ' ' or c = CR or c = HT then -- reading done.
if (i /= VALUE'low) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Warning: Value truncated."
severity warning;
return;
end if;
elsif c = '_' then
if i = VALUE'high then -- Begins with an "_"
report float_generic_pkg'instance_name
& "READ(float): "
& "String begins with an ""_""" severity error;
return;
elsif lastu then -- "__" detected
report float_generic_pkg'instance_name
& "READ(float): "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
if not (i = -1 or i = VALUE'high-1) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Warning: Separator point does not match number format: '"
& c & "' encountered at location " & INTEGER'image(i) & "."
severity warning;
end if;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < VALUE'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (L, c, readOk);
end loop readloop;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
READ (L, c, readOk);
if VALUE'length > 0 then
i := VALUE'high;
GOOD := false;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
return;
elsif c = ' ' or c = CR or c = HT then -- reading done
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
-- good := (i = -1 or i = value'high-1);
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < VALUE'low then
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (L, c, readOk);
end loop readloop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((VALUE'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/3)
& " valid octal characters."
severity error;
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (2 downto 1) /= "00" then
report float_generic_pkg'instance_name & "OREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_generic_pkg'instance_name & "OREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((VALUE'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (2 downto 1) /= "00" then
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure OREAD;
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((VALUE'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/4)
& " valid hex characters."
severity error;
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (3 downto 1) /= "000" then
report float_generic_pkg'instance_name & "HREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_generic_pkg'instance_name & "HREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((VALUE'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (3 downto 1) /= "000" then
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_float) return STRING is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(value(value'high)));
s(2) := ':';
sindx := 3;
for i in value'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto value'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end function to_string;
function to_hstring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_hstring (slv);
end function to_hstring;
function to_ostring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_ostring (slv);
end function to_ostring;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report float_generic_pkg'instance_name
& "from_string: Bad string " & bstring
severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report float_generic_pkg'instance_name
& "from_ostring: Bad string " & ostring
severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report float_generic_pkg'instance_name
& "from_hstring: Bad string " & hstring
severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_string (bstring => bstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_ostring (ostring => ostring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_hstring (hstring => hstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_hstring;
end package body float_generic_pkg;
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Floating-point package (Generic package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body float_generic_pkg is
-- Author David Bishop (dbishop@vhdl.org)
-----------------------------------------------------------------------------
-- type declarations
-----------------------------------------------------------------------------
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant
-- types of boundary conditions
type boundary_type is (normal, infinity, zero, denormal);
-- null range array constant
constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- Special version of "minimum" to do some boundary checking
function mine (L, R : INTEGER)
return INTEGER is
begin -- function minimum
if (L = INTEGER'low or R = INTEGER'low) then
report float_generic_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- Generates the base number for the exponent normalization offset.
function gen_expon_base (
constant exponent_width : NATURAL)
return SIGNED
is
variable result : SIGNED (exponent_width-1 downto 0);
begin
result := (others => '1');
result (exponent_width-1) := '0';
return result;
end function gen_expon_base;
-- Integer version of the "log2" command (contributed by Peter Ashenden)
function log2 (A : NATURAL) return NATURAL is
variable quotient : NATURAL;
variable result : NATURAL := 0;
begin
quotient := A / 2;
while quotient > 0 loop
quotient := quotient / 2;
result := result + 1;
end loop;
return result;
end function log2;
-- Function similar to the ILOGB function in MATH_REAL
function log2 (A : REAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if (A = 1.0 or A = 0.0) then
return 0;
end if;
Y := A;
if(A > 1.0) then
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y * 2.0;
N := N - 1;
end loop;
return N;
end function log2;
-- purpose: Test the boundary conditions of a Real number
procedure test_boundary (
arg : in REAL; -- Input, converted to real
constant fraction_width : in NATURAL; -- length of FP output fraction
constant exponent_width : in NATURAL; -- length of FP exponent
constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP
variable btype : out boundary_type;
variable log2i : out INTEGER
) is
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
constant exp_min : SIGNED (12 downto 0) :=
-(resize(expon_base, 13)) + 1; -- Minimum normal exponent
constant exp_ext_min : SIGNED (12 downto 0) :=
exp_min - fraction_width; -- Minimum for denormal exponent
variable log2arg : INTEGER; -- log2 of argument
begin -- function test_boundary
-- Check to see if the exponent is big enough
-- Note that the argument is always an absolute value at this point.
log2arg := log2(arg);
if arg = 0.0 then
btype := zero;
elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)
btype := normal;
else
if log2arg < to_integer(exp_min) then
if denormalize then
if log2arg < to_integer(exp_ext_min) then
btype := zero;
else
btype := denormal;
end if;
else
if log2arg < to_integer(exp_min)-1 then
btype := zero;
else
btype := normal; -- Can still represent this number
end if;
end if;
elsif exponent_width < 11 then
if log2arg > to_integer(expon_base)+1 then
btype := infinity;
else
btype := normal;
end if;
else
btype := normal;
end if;
end if;
log2i := log2arg;
end procedure test_boundary;
-- purpose: Rounds depending on the state of the "round_style"
-- Logic taken from
-- "What Every Computer Scientist Should Know About Floating Point Arithmetic"
-- by David Goldberg (1991)
function check_round (
fract_in : STD_ULOGIC; -- input fraction
sign : STD_ULOGIC; -- sign bit
remainder : UNSIGNED; -- remainder to round from
sticky : STD_ULOGIC := '0'; -- Sticky bit
constant round_style : round_type) -- rounding type
return BOOLEAN
is
variable result : BOOLEAN;
variable or_reduced : STD_ULOGIC;
begin -- function check_round
result := false;
if (remainder'length > 0) then -- if remainder in a null array
or_reduced := or (remainder & sticky);
rounding_case : case round_style is
when round_nearest => -- Round Nearest, default mode
if remainder(remainder'high) = '1' then -- round
if (remainder'length > 1) then
if ((or (remainder(remainder'high-1
downto remainder'low)) = '1'
or sticky = '1')
or fract_in = '1') then
-- Make the bottom bit zero if possible if we are at 1/2
result := true;
end if;
else
result := (fract_in = '1' or sticky = '1');
end if;
end if;
when round_inf => -- round up if positive, else truncate.
if or_reduced = '1' and sign = '0' then
result := true;
end if;
when round_neginf => -- round down if negative, else truncate.
if or_reduced = '1' and sign = '1' then
result := true;
end if;
when round_zero => -- round toward 0 Truncate
null;
end case rounding_case;
end if;
return result;
end function check_round;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
procedure fp_round (
fract_in : in UNSIGNED; -- input fraction
expon_in : in SIGNED; -- input exponent
fract_out : out UNSIGNED; -- output fraction
expon_out : out SIGNED) is -- output exponent
begin -- procedure fp_round
if and (fract_in) = '1' then -- Fraction is all "1"
expon_out := expon_in + 1;
fract_out := to_unsigned(0, fract_out'high+1);
else
expon_out := expon_in;
fract_out := fract_in + 1;
end if;
end procedure fp_round;
-- This version of break_number doesn't call "classfp"
procedure break_number ( -- internal version
arg : in UNRESOLVED_float;
fptyp : in valid_fpstate;
denormalize : in BOOLEAN := true;
fract : out UNSIGNED;
expon : out SIGNED) is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable exp : SIGNED (expon'range);
begin
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (fraction_width) := '1';
exp := SIGNED(arg(exponent_width-1 downto 0));
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert no_warning
report float_generic_pkg'instance_name
& "BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a NAN goes in, a NAN comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- purpose: floating point to UNSIGNED
-- Used by to_integer, to_unsigned, and to_signed functions
procedure float_to_unsigned (
arg : in UNRESOLVED_float; -- floating point input
variable sign : out STD_ULOGIC; -- sign of output
variable frac : out UNSIGNED; -- unsigned biased output
constant denormalize : in BOOLEAN; -- turn on denormalization
constant bias : in NATURAL; -- bias for fixed point
constant round_style : in round_type) is -- rounding method
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable fract : UNSIGNED (frac'range); -- internal version of frac
variable isign : STD_ULOGIC; -- internal version of sign
variable exp : INTEGER; -- Exponent
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
-- Base to divide fraction by
variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable remainder : UNSIGNED (2 downto 0);
variable round : STD_ULOGIC; -- round BIT
begin
isign := to_x01(arg(arg'high));
-- exponent /= '0', normal floating point
expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (expon);
-- Figure out the fraction
fract := (others => '0'); -- fill with zero
fract (fract'high) := '1'; -- Add the "1.0".
shift := (fract'high-1) - exp;
if fraction_width > fract'high then -- Can only use size-2 bits
fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-fract'high)));
else -- can use all bits
fract (fract'high-1 downto fract'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := fract & "000";
if shift < 0 then -- Overflow
fract := (others => '1');
else
frac_shift := shift_right (frac_shift, shift);
fract := frac_shift (frac_shift'high downto 3);
remainder := frac_shift (2 downto 0);
-- round (round_zero will bypass this and truncate)
case round_style is
when round_nearest =>
round := remainder(2) and
(fract (0) or (or (remainder (1 downto 0))));
when round_inf =>
round := remainder(2) and not isign;
when round_neginf =>
round := remainder(2) and isign;
when others =>
round := '0';
end case;
if round = '1' then
fract := fract + 1;
end if;
end if;
frac := fract;
sign := isign;
end procedure float_to_unsigned;
-- purpose: returns a part of a vector, this function is here because
-- or (fractr (to_integer(shiftx) downto 0));
-- can't be synthesized in some synthesis tools.
function smallfract (
arg : UNSIGNED;
shift : NATURAL)
return STD_ULOGIC
is
variable orx : STD_ULOGIC;
begin
orx := arg(shift);
for i in arg'range loop
if i < shift then
orx := arg(i) or orx;
end if;
end loop;
return orx;
end function smallfract;
---------------------------------------------------------------------------
-- Visible functions
---------------------------------------------------------------------------
-- purpose: converts the negative index to a positive one
-- negative indices are illegal in 1164 and 1076.3
function to_sulv (
arg : UNRESOLVED_float) -- fp vector
return STD_ULOGIC_VECTOR
is
variable intermediate_result : UNRESOLVED_float(arg'length-1 downto 0);
begin -- function to_std_ulogic_vector
if arg'length < 1 then
return NSLV;
end if;
intermediate_result := arg;
return STD_ULOGIC_VECTOR (intermediate_result);
end function to_sulv;
-- Converts an fp into an SULV
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_slv;
-- purpose: normalizes a floating point number
-- This version assumes an "unsigned" input with
function normalize (
fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign BIT
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction
variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction
variable exp : SIGNED (exponent_width+1 downto 0); -- exponent
variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent
variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result
variable shiftr : INTEGER; -- shift amount
variable stickyx : STD_ULOGIC; -- version of sticky
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round, zerores, infres : BOOLEAN;
begin -- function normalize
zerores := false;
infres := false;
round := false;
shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1"
- fraction_width - nguard; -- subtract the length we want
exp := resize (expon, exp'length) + shiftr;
if (or (fract) = '0') then -- Zero
zerores := true;
elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)
or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then
if (exp >= -resize(expon_base, exp'length)-fraction_width-1)
and denormalize then
exp := -resize(expon_base, exp'length)-1;
shiftr := -to_integer (expon + expon_base); -- new shift
else -- return zero
zerores := true;
end if;
elsif (exp > expon_base-1) then -- infinity
infres := true;
end if;
if zerores then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif infres then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
sfract := fract srl shiftr; -- shift
if shiftr > 0 then
-- stickyx := sticky or (or (fract (shiftr-1 downto 0)));
stickyx := sticky or smallfract (fract, shiftr-1);
else
stickyx := sticky;
end if;
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
sticky => stickyx,
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp(rexp'range),
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp(rexp'range);
end if;
-- result
rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));
rexpon (exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := UNRESOLVED_float(rexpon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
result (exponent_width) := sign; -- sign BIT
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with a "size_res" input
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -size_res'low;
constant exponent_width : NATURAL := size_res'high;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- Regular "normalize" function with a "size_res" input.
function normalize (
fract : UNRESOLVED_UNSIGNED; -- unsigned
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
begin
return normalize (fract => fract,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
end function normalize;
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate
is
constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : INTEGER := x'high; -- length of FP output exponent
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- classfp
if (arg'length < 1 or fraction_width < 3 or exponent_width < 3
or x'left < x'right) then
report float_generic_pkg'instance_name
& "CLASSFP: " &
"Floating point number detected with a bad range"
severity error;
return isx;
end if;
-- Check for "X".
arg := to_01 (x, 'X');
if (arg(0) = 'X') then
return isx; -- If there is an X in the number
-- Special cases, check for illegal number
elsif check_error and
(and (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '1') then -- Exponent is all "1".
if or (to_slv (arg (-1 downto -fraction_width)))
/= '0' then -- Fraction must be all "0" or this is not a number.
if (arg(-1) = '1') then -- From "W. Khan - IEEE standard
return nan; -- 754 binary FP Signaling nan (Not a number)
else
return quiet_nan;
end if;
-- Check for infinity
elsif arg(exponent_width) = '0' then
return pos_inf; -- Positive infinity
else
return neg_inf; -- Negative infinity
end if;
-- check for "0"
elsif or (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '0' then -- Exponent is all "0"
if or (to_slv (arg (-1 downto -fraction_width)))
= '0' then -- Fraction is all "0"
if arg(exponent_width) = '0' then
return pos_zero; -- Zero
else
return neg_zero;
end if;
else
if arg(exponent_width) = '0' then
return pos_denormal; -- Denormal number (ieee extended fp)
else
return neg_denormal;
end if;
end if;
else
if arg(exponent_width) = '0' then
return pos_normal; -- Normal FP number
else
return neg_normal;
end if;
end if;
end function Classfp;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_UNSIGNED;
expon : out UNRESOLVED_SIGNED;
sign : out STD_ULOGIC) is
variable fptyp : valid_fpstate;
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => fract,
expon => expon);
end procedure break_number;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_ufixed; -- 1 downto -fraction_width
expon : out UNRESOLVED_SIGNED; -- exponent_width-1 downto 0
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => ufract,
expon => expon);
fract (0 downto -fraction_width) := ufixed (ufract);
end procedure break_number;
-- Arithmetic functions
function "abs" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := '0'; -- set the sign bit to positive
return result;
else
return NAFP;
end if;
end function "abs";
-- IEEE 754 "negative" function
function "-" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := not result (arg'high); -- invert sign bit
return result;
else
return NAFP;
end if;
end function "-";
-- Addition, adds two floating point numbers
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant addguard : NATURAL := guard; -- add one guard bit
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions
variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables
variable urfract, ulfract : UNSIGNED (fraction_width downto 0);
variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions
variable sign : STD_ULOGIC; -- sign of the output
variable leftright : BOOLEAN; -- left or right used
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- addition
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf and rfptype = neg_inf)
or (lfptype = neg_inf and rfptype = pos_inf) then
-- Return quiet NAN, IEEE754-1985-7.1,2
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0
fpresult := neg_zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl := (others => '0');
fractl (fraction_width+addguard downto addguard) := ulfract;
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr := (others => '0');
fractr (fraction_width+addguard downto addguard) := urfract;
shiftx := (exponl(exponent_width-1) & exponl) - exponr;
if shiftx < -fractl'high then
rexpon := exponr(exponent_width-1) & exponr;
fractc := fractr;
fracts := (others => '0'); -- add zero
leftright := false;
sticky := or (fractl);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (fractl, to_integer(shiftx));
fractc := fractr;
rexpon := exponr(exponent_width-1) & exponr;
leftright := false;
-- sticky := or (fractl (to_integer(shiftx) downto 0));
sticky := smallfract (fractl, to_integer(shiftx));
elsif shiftx = 0 then
rexpon := exponl(exponent_width-1) & exponl;
sticky := '0';
if fractr > fractl then
fractc := fractr;
fracts := fractl;
leftright := false;
else
fractc := fractl;
fracts := fractr;
leftright := true;
end if;
elsif shiftx > fractr'high then
rexpon := exponl(exponent_width-1) & exponl;
fracts := (others => '0'); -- add zero
fractc := fractl;
leftright := true;
sticky := or (fractr);
elsif shiftx > 0 then
fracts := shift_right (fractr, to_integer(shiftx));
fractc := fractl;
rexpon := exponl(exponent_width-1) & exponl;
leftright := true;
-- sticky := or (fractr (to_integer(shiftx) downto 0));
sticky := smallfract (fractr, to_integer(shiftx));
end if;
-- add
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if l(l'high) = r(r'high) then
ufract := fractc + fracts;
sign := l(l'high);
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
sign := l(l'high);
else
sign := r(r'high);
end if;
end if;
if or (ufract) = '0' then
sign := '0'; -- IEEE 854, 6.3, paragraph 2.
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => addguard);
end if;
return fpresult;
end function add;
-- Subtraction, Calls "add".
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable negr : UNRESOLVED_float (r'range); -- negative version of r
begin
negr := -r; -- r := -r
return add (l => l,
r => negr,
round_style => round_style,
guard => guard,
check_error => check_error,
denormalize => denormalize);
end function subtract;
-- Floating point multiply
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant multguard : NATURAL := guard; -- guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction
variable shifty : INTEGER; -- denormal shift
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif ((lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
fpresult (exponent_width) := fp_sign;
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
rfract := fractl * fractr; -- Multiply the fraction
sfract := rfract (rfract'high downto
rfract'high - (fraction_width+1+multguard));
sticky := or (rfract (rfract'high-(fraction_width+1+multguard)
downto 0));
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => multguard);
end if;
return fpresult;
end function multiply;
function short_divide (
lx, rx : UNSIGNED)
return UNSIGNED
is
-- This is a special divider for the floating point routines.
-- For a true unsigned divider, "stages" needs to = lx'high
constant stages : INTEGER := lx'high - rx'high; -- number of stages
variable partial : UNSIGNED (lx'range);
variable q : UNSIGNED (stages downto 0);
variable partial_argl : SIGNED (rx'high + 2 downto 0);
variable partial_arg : SIGNED (rx'high + 2 downto 0);
begin
partial := lx;
for i in stages downto 0 loop
partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)),
partial_argl'length);
partial_arg := partial_argl - SIGNED ("0" & rx);
if (partial_arg (partial_arg'high) = '1') then -- negative
q(i) := '0';
else
q(i) := '1';
partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=
UNSIGNED (partial_arg(rx'range));
end if;
end loop;
-- to make the output look like that of the unsigned IEEE divide.
return resize (q, lx'length);
end function short_divide;
-- 1/X function. Needed for algorithm development.
function reciprocal (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant divguard : NATURAL := guard; -- guard bits
function onedivy (
arg : UNSIGNED)
return UNSIGNED
is
variable q : UNSIGNED((2*arg'high)+1 downto 0);
variable one : UNSIGNED (q'range);
begin
one := (others => '0');
one(one'high) := '1';
q := short_divide (one, arg); -- Unsigned divide
return resize (q, arg'length+1);
end function onedivy;
variable fptype : valid_fpstate;
variable expon : SIGNED (exponent_width-1 downto 0); -- exponents
variable denorm_offset : NATURAL range 0 to 2;
variable fract : UNSIGNED (fraction_width downto 0);
variable fractg : UNSIGNED (fraction_width+divguard downto 0);
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- reciprocal
fptype := Classfp(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- 1/inf, return 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_zero | pos_zero => -- 1/0
report float_generic_pkg'instance_name
& "RECIPROCAL: Floating Point divide by zero"
severity error;
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
if (fptype = pos_denormal or fptype = neg_denormal)
and ((arg (-1) or arg(-2)) /= '1') then
-- 1/denormal = infinity, with the exception of 2**-expon_base
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult (exponent_width) := to_x01 (arg (exponent_width));
else
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => fract,
expon => expon);
fractg := (others => '0');
if (fptype = pos_denormal or fptype = neg_denormal) then
-- The reciprocal of a denormal number is typically zero,
-- except for two special cases which are trapped here.
if (to_x01(arg (-1)) = '1') then
fractg (fractg'high downto divguard+1) :=
fract (fract'high-1 downto 0); -- Shift to not denormal
denorm_offset := 1; -- add 1 to exponent compensate
else -- arg(-2) = '1'
fractg (fractg'high downto divguard+2) :=
fract (fract'high-2 downto 0); -- Shift to not denormal
denorm_offset := 2; -- add 2 to exponent compensate
end if;
else
fractg (fractg'high downto divguard) := fract;
denorm_offset := 0;
end if;
expon := - expon - 3 + denorm_offset;
sfract := onedivy (fractg);
-- normalize
fpresult := normalize (fract => sfract,
expon => expon,
sign => arg(exponent_width),
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end if;
end case classcase;
return fpresult;
end function reciprocal;
-- floating point division
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left
variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractl'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign, sticky : STD_ULOGIC; -- sign of result
variable shifty, shiftx : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divide
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf -- inf / inf
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_generic_pkg'instance_name
& "DIVIDE: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
-- Compute the exponent
rexpon := resize (exponl, rexpon'length) - exponr - 2;
if (rfptype = pos_denormal or rfptype = neg_denormal) then
-- Do the shifting here not after. That way we have a smaller
-- shifter, and need a smaller divider, because the top
-- bit in the divisor will always be a "1".
shifty := fraction_width - find_leftmost(urfract, '1');
urfract := shift_left (urfract, shifty);
rexpon := rexpon + shifty;
end if;
fractr := (others => '0');
fractr (fraction_width+divguard downto divguard) := urfract;
if (lfptype = pos_denormal or lfptype = neg_denormal) then
shiftx := fraction_width - find_leftmost(ulfract, '1');
ulfract := shift_left (ulfract, shiftx);
rexpon := rexpon - shiftx;
end if;
fractl := (others => '0');
fractl (fractl'high downto fractl'high-fraction_width) := ulfract;
-- divide
rfract := short_divide (fractl, fractr); -- unsigned divide
sfract := rfract (sfract'range); -- lower bits
sticky := '1';
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end case classcase2;
end case classcase;
return fpresult;
end function divide;
-- division by a power of 2
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divisionbyp2
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_generic_pkg'instance_name
& "DIVIDEBYP2: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
assert (or (urfract (fraction_width-1 downto 0)) = '0')
report float_generic_pkg'instance_name
& "DIVIDEBYP2: "
& "Dividebyp2 called with a non power of two divisor"
severity error;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 1;
-- normalize
fpresult := normalize (fract => ulfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase2;
end case classcase;
return fpresult;
end function dividebyp2;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL :=
-mine (mine(l'low, r'low), c'low); -- length of FP output fraction
constant exponent_width : NATURAL :=
maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent
variable lfptype, rfptype, cfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable fractx : UNSIGNED (fraction_width+guard downto 0);
variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction
variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent
variable shifty : INTEGER; -- denormal shift
variable shiftx : SIGNED (rexpon'range); -- shift fractions
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);
variable leftright : BOOLEAN; -- left or right used
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
cfptype := Classfp (c, check_error);
end if;
if (lfptype = isx or rfptype = isx or cfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
cfptype = nan or cfptype = quiet_nan) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf
or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
cresize := resize (arg => to_X01(c),
exponent_width => exponent_width,
fraction_width => -cresize'low,
denormalize_in => denormalize,
denormalize => denormalize);
cfptype := Classfp (cresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
break_number (
arg => cresize,
fptyp => cfptype,
denormalize => denormalize,
fract => fractx,
expon => exponc);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
shiftx := rexpon - exponc;
if shiftx < -fractl'high then
rexpon2 := resize (exponc, rexpon2'length);
fractc := "0" & fractx;
fracts := (others => '0');
sticky := or (rfract);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (rfract (rfract'high downto rfract'high
- fracts'length+1),
to_integer(shiftx));
fractc := "0" & fractx;
rexpon2 := resize (exponc, rexpon2'length);
leftright := false;
sticky := or (rfract (to_integer(shiftx)+rfract'high
- fracts'length downto 0));
elsif shiftx = 0 then
rexpon2 := resize (exponc, rexpon2'length);
sticky := or (rfract (rfract'high - fractc'length downto 0));
if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx
then
fractc := "0" & fractx;
fracts := rfract (rfract'high downto rfract'high
- fracts'length+1);
leftright := false;
else
fractc := rfract (rfract'high downto rfract'high
- fractc'length+1);
fracts := "0" & fractx;
leftright := true;
end if;
elsif shiftx > fractx'high then
rexpon2 := rexpon;
fracts := (others => '0');
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or (fractx & rfract (rfract'high - fractc'length
downto 0));
else -- fractx'high > shiftx > 0
rexpon2 := rexpon;
fracts := "0" & shift_right (fractx, to_integer (shiftx));
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or (fractx (to_integer (shiftx) downto 0)
& rfract (rfract'high - fractc'length downto 0));
end if;
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if fp_sign = to_X01(c(c'high)) then
ufract := fractc + fracts;
fp_sign := fp_sign;
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
fp_sign := fp_sign;
else
fp_sign := c(c'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon2,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end if;
return fpresult;
end function mac;
-- "rem" function
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractr'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (abs(l) < abs(r)) then
fpresult := l;
else
fp_sign := to_X01(l(l'high)); -- sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fraction_width+divguard downto divguard) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponr(exponr'high)&exponr);
shifty := to_integer(exponl - rexpon);
if (shifty > 0) then
fractr := shift_right (fractr, shifty);
rexpon := rexpon + shifty;
end if;
if (fractr /= 0) then
-- rem
rfract := fractl rem fractr; -- unsigned rem
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
else
-- If we shift "fractr" so far that it becomes zero, return zero.
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
end if;
return fpresult;
end function remainder;
-- "mod" function
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
remres := remainder (l => abs(l),
r => abs(r),
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
-- MOD is the same as REM, but you do something different with
-- negative values
if (Is_Negative (l)) then
remres := - remres;
end if;
if (Is_Negative (l) = Is_Negative (r) or remres = 0) then
fpresult := remres;
else
fpresult := add (l => remres,
r => r,
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
end if;
end if;
return fpresult;
end function modulo;
-- Square root of a floating point number. Done using Newton's Iteration.
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable sign : STD_ULOGIC;
variable fpresult : float (arg'range);
variable fptype : valid_fpstate;
variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents
variable expon : SIGNED(exponent_width downto 0); -- exponents
variable ufact : ufixed (0 downto arg'low);
variable fact : ufixed (2 downto -fraction_width); -- fraction
variable resb : ufixed (fact'high+1 downto fact'low);
begin -- square root
fptype := Classfp (arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan |
-- Return quiet NAN, IEEE754-1985-7.1,1
neg_normal | neg_denormal | neg_inf => -- sqrt (neg)
-- Return quiet NAN, IEEE754-1985-7.1.6
fpresult := qnanfp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_inf => -- Sqrt (inf), return infinity
fpresult := pos_inffp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_zero => -- return 0
fpresult := zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when neg_zero => -- IEEE754-1985-6.3 return -0
fpresult := neg_zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when others =>
break_number (arg => arg,
denormalize => denormalize,
check_error => false,
fract => ufact,
expon => iexpon,
sign => sign);
expon := resize (iexpon+1, expon'length); -- get exponent
fact := resize (ufact, fact'high, fact'low);
if (expon(0) = '1') then
fact := fact sla 1; -- * 2.0
end if;
expon := shift_right (expon, 1); -- exponent/2
-- Newton's iteration - root := (1 + arg) / 2
resb := (fact + 1) sra 1;
for j in 0 to fraction_width/4 loop
-- root := (root + (arg/root))/2
resb := resize (arg => (resb + (fact/resb)) sra 1,
left_index => resb'high,
right_index => resb'low,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
end loop;
fpresult := normalize (fract => resb,
expon => expon-1,
sign => '0',
exponent_width => arg'high,
fraction_width => -arg'low,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end case classcase;
return fpresult;
end function sqrt;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is
-- Technically -0 should return "false", but I'm leaving that case out.
begin
return (to_x01(arg(arg'high)) = '1');
end function Is_Negative;
-- compare functions
-- =, /=, >=, <=, <, >
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : BOOLEAN;
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- equal
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return false;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := true;
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
is_equal := (to_slv(lresize) = to_slv(rresize));
end if;
if (check_error) then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_equal and not is_unordered;
end function eq;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_less_than, is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_less_than := false;
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (fractl < fractr);
else
is_less_than := (fractl > fractr); -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (expl < expr);
else
is_less_than := (expl > expr); -- negative
end if;
end if;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
if (lfptype = neg_zero and rfptype = pos_zero) then
is_less_than := false; -- -0 < 0 returns false.
else
is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_less_than and not is_unordered;
end function lt;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_greater_than : BOOLEAN;
variable is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- greater_than
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_greater_than := false;
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := fractl > fractr;
else
is_greater_than := fractl < fractr; -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := expl > expr;
else
is_greater_than := expl < expr; -- negative
end if;
end if;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
if (lfptype = pos_zero and rfptype = neg_zero) then
is_greater_than := false; -- 0 > -0 returns false.
else
is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_greater_than and not is_unordered;
end function gt;
-- purpose: /= function
function ne ( -- not equal /=
l, r : UNRESOLVED_float;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_equal, is_unordered : BOOLEAN;
begin
is_equal := eq (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not (is_equal and not is_unordered);
end function ne;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_greater_than, is_unordered : BOOLEAN;
begin
is_greater_than := gt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_greater_than and not is_unordered;
end function le;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_less_than, is_unordered : BOOLEAN;
begin
is_less_than := lt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_less_than and not is_unordered;
end function ge;
function "?=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?=
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
lfptype := Classfp (L, float_check_error);
rfptype := Classfp (R, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => L,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => R,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := to_sulv(lresize) ?= to_sulv(rresize);
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return is_equal and not is_unordered;
end function "?=";
function "?/=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?/=
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
lfptype := Classfp (L, float_check_error);
rfptype := Classfp (R, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => L,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => R,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := to_sulv(lresize) ?= to_sulv(rresize);
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return not (is_equal and not is_unordered);
end function "?/=";
function "?>" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?>"": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L > R then
return '1';
else
return '0';
end if;
end if;
end function "?>";
function "?>=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?>="": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L >= R then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
function "?<" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?<"": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L < R then
return '1';
else
return '0';
end if;
end if;
end function "?<";
function "?<=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?<="": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L <= R then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
function std_match (L, R : UNRESOLVED_float) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
report float_generic_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
-- These override the defaults for the compare operators.
function "=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return eq(l, r);
end function "=";
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ne(l, r);
end function "/=";
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ge(l, r);
end function ">=";
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return le(l, r);
end function "<=";
function ">" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return gt(l, r);
end function ">";
function "<" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return lt(l, r);
end function "<";
-- purpose: maximum of two numbers (overrides default)
function maximum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (L, exponent_width, fraction_width);
rresize := resize (R, exponent_width, fraction_width);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (L, exponent_width, fraction_width);
rresize := resize (R, exponent_width, fraction_width);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
-----------------------------------------------------------------------------
-- conversion functions
-----------------------------------------------------------------------------
-- Converts a floating point number of one format into another format
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
-- result value
variable fptype : valid_fpstate;
variable expon_in : SIGNED (in_exponent_width-1 downto 0);
variable fract_in : UNSIGNED (in_fraction_width downto 0);
variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract
variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract
begin
fptype := Classfp(arg, check_error);
if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in
and (in_exponent_width < exponent_width
or in_fraction_width < fraction_width))
or in_exponent_width > exponent_width
or in_fraction_width > fraction_width then
-- size reduction
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf =>
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_inf =>
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero =>
result := zerofp (fraction_width => fraction_width, -- hate -0
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize_in,
fract => fract_in,
expon => expon_in);
if fraction_width > in_fraction_width and denormalize_in then
-- You only get here if you have a denormal input
fract_out := (others => '0'); -- pad with zeros
fract_out (fraction_width downto
fraction_width - in_fraction_width) := fract_in;
result := normalize (
fract => fract_out,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
else
result := normalize (
fract => fract_in,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => in_fraction_width - fraction_width);
end if;
end case classcase;
else -- size increase or the same size
if exponent_width > in_exponent_width then
expon_in := SIGNED(arg (in_exponent_width-1 downto 0));
if fptype = pos_zero or fptype = neg_zero then
result (exponent_width-1 downto 0) := (others => '0');
elsif expon_in = -1 then -- inf or nan (shorts out check_error)
result (exponent_width-1 downto 0) := (others => '1');
else
-- invert top BIT
expon_in(expon_in'high) := not expon_in(expon_in'high);
expon_out := resize (expon_in, expon_out'length); -- signed expand
-- Flip it back.
expon_out(expon_out'high) := not expon_out(expon_out'high);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);
end if;
result (exponent_width) := arg (in_exponent_width); -- sign
else -- exponent_width = in_exponent_width
result (exponent_width downto 0) := arg (in_exponent_width downto 0);
end if;
if fraction_width > in_fraction_width then
result (-1 downto -fraction_width) := (others => '0'); -- zeros
result (-1 downto -in_fraction_width) :=
arg (-1 downto -in_fraction_width);
else -- fraction_width = in_fraciton_width
result (-1 downto -fraction_width) :=
arg (-1 downto -in_fraction_width);
end if;
end if;
return result;
end function resize;
function resize (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
return result;
end if;
end function resize;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32 is
begin
return resize (arg => arg,
exponent_width => float32'high,
fraction_width => -float32'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64 is
begin
return resize (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128 is
begin
return resize (arg => arg,
exponent_width => float128'high,
fraction_width => -float128'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float128;
-- to_float (Real)
-- typically not Synthesizable unless the input is a constant.
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_real : REAL; -- Real version of argument
variable validfp : boundary_type; -- Check for valid results
variable exp : INTEGER; -- Integer version of exponent
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable frac : REAL; -- Real version of fraction
constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding
variable round : BOOLEAN; -- to round or not to round
begin
result := (others => '0');
arg_real := arg;
if arg_real < 0.0 then
result (exponent_width) := '1';
arg_real := - arg_real; -- Make it positive.
else
result (exponent_width) := '0';
end if;
test_boundary (arg => arg_real,
fraction_width => fraction_width,
exponent_width => exponent_width,
denormalize => denormalize,
btype => validfp,
log2i => exp);
if validfp = zero then
return result; -- Result initialized to "0".
elsif validfp = infinity then
result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1"
-- return infinity.
return result;
else
if validfp = denormal then -- Exponent will default to "0".
expon := (others => '0');
frac := arg_real * (2.0 ** (to_integer(expon_base)-1));
else -- Number less than 1. "normal" number
expon := UNSIGNED (to_signed (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.
end if;
for i in 0 to fract'high loop
if frac >= 2.0 ** (-1 - i) then
fract (fract'high - i) := '1';
frac := frac - 2.0 ** (-1 - i);
else
fract (fract'high - i) := '0';
end if;
end loop;
round := false;
case round_style is
when round_nearest =>
if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if frac /= 0.0 and result(exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if frac /= 0.0 and result(exponent_width) = '1' then
round := true;
end if;
when others =>
null; -- don't round
end case;
if (round) then
if and(fract) = '1' then -- fraction is all "1"
expon := expon + 1;
fract := (others => '0');
else
fract := fract + 1;
end if;
end if;
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
return result;
end if;
end function to_float;
-- to_float (Integer)
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : NATURAL; -- Natural version of argument
variable expon : SIGNED (exponent_width-1 downto 0);
variable exptmp : SIGNED (exponent_width-1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');
variable fracttmp : UNSIGNED (fraction_width-1 downto 0);
variable round : BOOLEAN;
variable shift : NATURAL;
variable shiftr : NATURAL;
variable roundfrac : NATURAL; -- used in rounding
begin
if arg < 0 then
result (exponent_width) := '1';
arg_int := -arg; -- Make it positive.
else
result (exponent_width) := '0';
arg_int := arg;
end if;
if arg_int = 0 then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- If the number is larger than we can represent in this number system
-- we need to return infinity.
shift := log2(arg_int);
if shift > to_integer(expon_base) then
-- worry about infinity
if result (exponent_width) = '0' then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- return negative infinity.
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
else -- Normal number (can't be denormal)
-- Compute Exponent
expon := to_signed (shift-1, expon'length); -- positive fraction.
-- Compute Fraction
arg_int := arg_int - 2**shift; -- Subtract off the 1.0
shiftr := shift;
for I in fract'high downto maximum (fract'high - shift + 1, 0) loop
shiftr := shiftr - 1;
if (arg_int >= 2**shiftr) then
arg_int := arg_int - 2**shiftr;
fract(I) := '1';
else
fract(I) := '0';
end if;
end loop;
-- Rounding routine
round := false;
if arg_int > 0 then
roundfrac := 2**(shiftr-1);
case round_style is
when round_nearest =>
if arg_int > roundfrac or
((arg_int = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if arg_int /= 0 and result (exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if arg_int /= 0 and result (exponent_width) = '1' then
round := true;
end if;
when others =>
null;
end case;
end if;
if round then
fp_round(fract_in => fract,
expon_in => expon,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
expon := exptmp;
end if;
-- Put the number together and return
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
end if;
return result;
end function to_float;
-- to_float (unsigned)
function to_float (
arg : UNRESOLVED_UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := arg'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is arg;
variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg
begin
if arg'length < 1 then
return NAFP;
end if;
sarg (XARG'range) := SIGNED (XARG);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style);
return result;
end function to_float;
-- to_float (signed)
function to_float (
arg : UNRESOLVED_SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := arg'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is arg;
variable arg_int : UNSIGNED(XARG'range); -- Real version of argument
variable argb2 : UNSIGNED(XARG'high/2 downto 0); -- log2 of input
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable rfract : UNSIGNED (fraction_width-1 downto 0);
variable sign : STD_ULOGIC; -- sign bit
begin
if arg'length < 1 then
return NAFP;
end if;
if Is_X (XARG) then
result := (others => 'X');
elsif (XARG = 0) then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- Normal number (can't be denormal)
sign := to_X01(XARG (XARG'high));
arg_int := UNSIGNED(abs (to_01(XARG)));
-- Compute Exponent
argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2
if argb2 > UNSIGNED(expon_base) then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
result (exponent_width) := sign;
else
exp := SIGNED(resize(argb2, exp'length));
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract (0),
sign => sign,
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := (others => '0');
rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
result (exponent_width) := sign;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
end if;
return result;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float
is
variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if arg'length < 1 then
return NAFP;
end if;
fpvar := UNRESOLVED_float(arg);
return fpvar;
end function to_float;
-- purpose: converts a ufixed to a floating point
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float
is
variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- function to_float
if (arg'length < 1) then
return NAFP;
end if;
sarg (arg'range) := sfixed (arg);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style,
denormalize => denormalize);
return result;
end function to_float;
function to_float (
arg : UNRESOLVED_sfixed; -- signed fixed point
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float
is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : sfixed (integer_width downto in_fraction_width);
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width
downto 0); -- unsigned version of argument
variable argx : SIGNED (integer_width - in_fraction_width downto 0);
variable exp, exptmp : SIGNED (exponent_width + 1 downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin
if (arg'length < 1) then
return NAFP;
end if;
xresult := to_01(arg, 'X');
argx := SIGNED(to_slv(xresult));
if (Is_X (arg)) then
result := (others => 'X');
elsif (argx = 0) then
result := (others => '0');
else
result := (others => '0'); -- zero out the result
if argx(argx'left) = '1' then -- toss the sign bit
result (exponent_width) := '1'; -- Negative number
arg_int := UNSIGNED(to_x01(not STD_LOGIC_VECTOR (argx))) + 1; -- Make it positive with two's complement
else
result (exponent_width) := '0';
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx))); -- new line: direct conversion to unsigned
end if;
-- Compute Exponent
exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result (-1 downto -fraction_width) := (others => '0');
result (exponent_width -1 downto 0) := (others => '1');
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize(exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
return result;
end function to_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- to_integer (float)
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER
is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (-arg'low downto 0); -- Fraction
variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction
variable expon : SIGNED (arg'high-1 downto 0);
variable isign : STD_ULOGIC; -- internal version of sign
variable round : STD_ULOGIC; -- is rounding needed?
variable result : INTEGER;
variable base : INTEGER; -- Integer exponent
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := 0; -- return 0
when pos_inf =>
result := INTEGER'high;
when neg_inf =>
result := INTEGER'low;
when others =>
break_number (
arg => arg,
fptyp => validfp,
denormalize => false,
fract => frac,
expon => expon);
fract (fract'high) := '0'; -- Add extra bit for 0.6 case
fract (fract'high-1 downto 0) := frac;
isign := to_x01 (arg (arg'high));
base := to_integer (expon) + 1;
if base < -1 then
result := 0;
elsif base >= frac'high then
result := to_integer (fract) * 2**(base - frac'high);
else -- We need to round
if base = -1 then -- trap for 0.6 case.
result := 0;
else
result := to_integer (fract (frac'high downto frac'high-base));
end if;
-- rounding routine
case round_style is
when round_nearest =>
if frac'high - base > 1 then
round := fract (frac'high - base - 1) and
(fract (frac'high - base)
or (or (fract (frac'high - base - 2 downto 0))));
else
round := fract (frac'high - base - 1) and
fract (frac'high - base);
end if;
when round_inf =>
round := fract(frac'high - base - 1) and not isign;
when round_neginf =>
round := fract(frac'high - base - 1) and isign;
when others =>
round := '0';
end case;
if round = '1' then
result := result + 1;
end if;
end if;
if isign = '1' then
result := - result;
end if;
end case classcase;
return result;
end function to_integer;
-- to_unsigned (float)
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED
is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction
variable sign : STD_ULOGIC; -- not used
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1');
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
end case classcase;
return (frac);
end function to_unsigned;
-- to_signed (float)
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED
is
variable sign : STD_ULOGIC; -- true if negative
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction
variable result : UNRESOLVED_SIGNED (size-1 downto 0);
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := (others => '0'); -- return 0
when pos_inf =>
result := (others => '1');
result (result'high) := '0';
when neg_inf =>
result := (others => '0');
result (result'high) := '1';
when others =>
float_to_unsigned (
arg => arg,
sign => sign,
frac => frac,
denormalize => false,
bias => 0,
round_style => round_style);
result (size-1) := '0';
result (size-2 downto 0) := UNRESOLVED_SIGNED(frac (size-2 downto 0));
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if frac(frac'high) = '1' then -- return most negative number
result := (others => '0');
result (result'high) := '1';
else
result := -result;
end if;
else
if frac(frac'high) = '1' then -- return most positive number
result := (others => '1');
result (result'high) := '0';
end if;
end if;
end case classcase;
return result;
end function to_signed;
-- purpose: Converts a float to ufixed
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);
variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result
begin -- function to_ufixed
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1'); -- always saturate
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
-- Figure out the fraction
if (validfp = pos_denormal) and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Remove the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
end case classcase;
result_big := to_ufixed (
arg => STD_ULOGIC_VECTOR(frac),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- purpose: Converts a float to sfixed
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable sign : BOOLEAN; -- true if negative
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable rsigned : SIGNED (size-1 downto 0); -- signed version of result
variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);
variable result : UNRESOLVED_sfixed (left_index downto right_index)
:= (others => '0'); -- result
begin -- function to_sfixed
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero =>
result := (others => '0'); -- return 0
when neg_inf =>
result (left_index) := '1'; -- return smallest negative number
when pos_inf =>
result := (others => '1'); -- return largest number
result (left_index) := '0';
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
if arg(exponent_width) = '0' then
sign := false;
else
sign := true;
end if;
-- Figure out the fraction
if (validfp = pos_denormal or validfp = neg_denormal)
and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
if not sign then
rsigned := SIGNED("0" & frac);
else
rsigned := -(SIGNED("0" & frac));
end if;
result_big := to_sfixed (
arg => STD_LOGIC_VECTOR(rsigned),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
end case classcase;
return result;
end function to_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED
is
variable result : UNRESOLVED_UNSIGNED (size_res'range);
begin
if (size_res'length = 0) then
return result;
else
result := to_unsigned (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_unsigned;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED
is
variable result : UNRESOLVED_SIGNED (size_res'range);
begin
if (size_res'length = 0) then
return result;
else
result := to_signed (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_signed;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_sfixed;
-- to_real (float)
-- typically not Synthesizable unless the input is a constant.
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable validfp : valid_fpstate; -- Valid FP state
variable expon : UNSIGNED (exponent_width - 1 downto 0)
:= (others => '1'); -- Vectorized exponent
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | pos_zero | neg_zero | nan | quiet_nan =>
return 0.0;
when neg_inf =>
return REAL'low; -- Negative infinity.
when pos_inf =>
return REAL'high; -- Positive infinity
when others =>
expon_base := 2**(exponent_width-1) -1;
if to_X01(arg(exponent_width)) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
-- Figure out the fraction
for i in 0 to fraction_width-1 loop
if to_X01(arg (-1 - i)) = '1' then
frac := frac + (2.0 **(-1 - i));
end if;
end loop; -- i
if validfp = pos_normal or validfp = neg_normal or not denormalize then
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
sign := sign * (2.0 ** exp) * (1.0 + frac);
else -- exponent = '0', IEEE extended floating point
exp := 1 - expon_base;
sign := sign * (2.0 ** exp) * frac;
end if;
return sign;
end case classcase;
end function to_real;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_sulv (result);
end function realtobits;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
-- purpose: Removes meta-logical values from FP string
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range);
begin -- function to_01
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_01: null detected, returning NULL"
severity warning;
return NAFP;
end if;
result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));
return result;
end function to_01;
function Is_X
(arg : UNRESOLVED_float)
return BOOLEAN is
begin
return Is_X (to_slv(arg));
end function Is_X;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_X01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01(to_slv(arg)));
return result;
end if;
end function to_X01;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_X01Z: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01Z(to_slv(arg)));
return result;
end if;
end function to_X01Z;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_UX01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_UX01(to_slv(arg)));
return result;
end if;
end function to_UX01;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return add (l, r);
end function "+";
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return subtract (l, r);
end function "-";
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return multiply (l, r);
end function "*";
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return divide (l, r);
end function "/";
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return remainder (l, r);
end function "rem";
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return modulo (l, r);
end function "mod";
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
-- ?= overloads
function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?= r_float;
end function "?=";
function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?/= r_float;
end function "?/=";
function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?> r_float;
end function "?>";
function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?>= r_float;
end function "?>=";
function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?< r_float;
end function "?<";
function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?<= r_float;
end function "?<=";
-- real and float
function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?= r;
end function "?=";
function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?/= r;
end function "?/=";
function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?> r;
end function "?>";
function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?>= r;
end function "?>=";
function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?< r;
end function "?<";
function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?<= r;
end function "?<=";
-- ?= overloads
function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?= r_float;
end function "?=";
function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?/= r_float;
end function "?/=";
function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?> r_float;
end function "?>";
function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?>= r_float;
end function "?>=";
function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?< r_float;
end function "?<";
function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?<= r_float;
end function "?<=";
-- integer and float
function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?= r;
end function "?=";
function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?/= r;
end function "?/=";
function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?> r;
end function "?>";
function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?>= r;
end function "?>=";
function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?< r;
end function "?<";
function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?<= r;
end function "?<=";
-- minimum and maximum overloads
function minimum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
function minimum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_float (RESULT, L'high, -L'low);
end function "not";
function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "and";
function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L and to_sulv(R));
return result;
end function "and";
function "and" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) and R);
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L or to_sulv(R));
return result;
end function "or";
function "or" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) or R);
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L nand to_sulv(R));
return result;
end function "nand";
function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) nand R);
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L nor to_sulv(R));
return result;
end function "nor";
function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) nor R);
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L xor to_sulv(R));
return result;
end function "xor";
function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) xor R);
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L xnor to_sulv(R));
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) xnor R);
return result;
end function "xnor";
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return and to_sulv(l);
end function "and";
function "nand" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nand to_sulv(l);
end function "nand";
function "or" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return or to_sulv(l);
end function "or";
function "nor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nor to_sulv(l);
end function "nor";
function "xor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xor to_sulv(l);
end function "xor";
function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xnor to_sulv(l);
end function "xnor";
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (
x, y : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
begin
return y(y'high) & x (x'high-1 downto x'low);
end function Copysign;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction
constant exponent_width : NATURAL := y'high; -- length of FP output exponent
variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
variable exp : SIGNED (exponent_width downto 0);
variable ufract : UNSIGNED (fraction_width downto 0);
variable fptype : valid_fpstate;
begin
-- This can be done by simply adding N to the exponent.
arg := to_01 (y, 'X');
fptype := Classfp(arg, check_error);
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => ufract,
expon => expon);
exp := resize (expon, exp'length) + N;
result := normalize (
fract => ufract,
expon => exp,
sign => to_x01 (arg (arg'high)),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase;
return result;
end function Scalb;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : UNRESOLVED_SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable n_int : INTEGER;
begin
n_int := to_integer(N);
return Scalb (y => y,
N => n_int,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
end function Scalb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return INTEGER
is
constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : INTEGER; -- result
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width - 1 downto 0);
variable fract : UNSIGNED (fraction_width downto 0);
constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent
-- offset +1
variable fptype : valid_fpstate;
begin
-- Just return the exponent.
arg := to_01 (x, 'X');
fptype := Classfp(arg);
classcase : case fptype is
when isx | nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := 0;
when pos_denormal | neg_denormal =>
fract (fraction_width) := '0';
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
result := find_leftmost (fract, '1') -- Find the first "1"
- fraction_width; -- subtract the length we want
result := -expon_base + 1 + result;
when others =>
expon := SIGNED(arg (exponent_width - 1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
expon := expon + 1;
result := to_integer (expon);
end case classcase;
return result;
end function Logb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return UNRESOLVED_SIGNED
is
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : SIGNED (exponent_width - 1 downto 0); -- result
begin
-- Just return the exponent.
result := to_signed (Logb (x), exponent_width);
return result;
end function Logb;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
function "=" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function "="
return eq (l => l,
r => r,
check_error => false);
end function "=";
function ">" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function ">"
return gt (l => l,
r => r,
check_error => false);
end function ">";
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable expon : UNSIGNED (exponent_width-1 downto 0);
variable sign : STD_ULOGIC;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable validfpx, validfpy : valid_fpstate; -- Valid FP state
begin -- fp_Nextafter
-- If Y > X, add one to the fraction, otherwise subtract.
validfpx := Classfp (x, check_error);
validfpy := Classfp (y, check_error);
if validfpx = isx or validfpy = isx then
result := (others => 'X');
return result;
elsif (validfpx = nan or validfpy = nan) then
return nanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (validfpx = quiet_nan or validfpy = quiet_nan) then
return qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif x = y then -- Return X
return x;
else
fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction
expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent
sign := x(exponent_width); -- sign bit
if (y > x) then
-- Increase the number given
if validfpx = neg_inf then
-- return most negative number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero or validfpx = neg_zero then
-- return smallest denormal number
sign := '0';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = pos_normal then
if and (fract) = '1' then -- fraction is all "1".
if and (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert no_warning
report float_generic_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1;
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = pos_denormal then
if and (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = neg_normal then
if or (fract) = '0' then -- fraction is all "0".
if or (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest negative denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = neg_denormal then
if or (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
else
-- Decrease the number
if validfpx = pos_inf then
-- return most positive number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero
or Classfp (x) = neg_zero then
-- return smallest negative denormal number
sign := '1';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = neg_normal then
if and (fract) = '1' then -- fraction is all "1".
if and (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert no_warning
report float_generic_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1; -- Fraction overflow
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = neg_denormal then
if and (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = pos_normal then
if or (fract) = '0' then -- fraction is all "0".
if or (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest positive denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = pos_denormal then
if or (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
end if;
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);
result (exponent_width) := sign;
return result;
end if;
end function Nextafter;
-- Returns True if X is unordered with Y.
function Unordered (
x, y : UNRESOLVED_float) -- floating point input
return BOOLEAN
is
variable lfptype, rfptype : valid_fpstate;
begin
lfptype := Classfp (x);
rfptype := Classfp (y);
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
lfptype = isx or rfptype = isx) then
return true;
else
return false;
end if;
end function Unordered;
function Finite (
x : UNRESOLVED_float)
return BOOLEAN
is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = pos_inf) or (fp_state = neg_inf) then
return true;
else
return false;
end if;
end function Finite;
function Isnan (
x : UNRESOLVED_float)
return BOOLEAN
is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = nan) or (fp_state = quiet_nan) then
return true;
else
return false;
end if;
end function Isnan;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
return result;
end function zerofp;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-1) := '1'; -- MSB of Fraction "1"
-- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point"
-- The difference between a signaling NAN and a quiet NAN is that
-- the MSB of the Fraction is a "1" in a Signaling NAN, and is a
-- "0" in a quiet NAN.
return result;
end function nanfp;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-fraction_width) := '1'; -- LSB of Fraction "1"
-- (Could have been any bit)
return result;
end function qnanfp;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1"
return result;
end function pos_inffp;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width downto 0) := (others => '1'); -- top bits all "1"
return result;
end function neg_inffp;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width) := '1';
return result;
end function neg_zerofp;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function zerofp;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return nanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function nanfp;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return qnanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function qnanfp;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return pos_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function pos_inffp;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_inffp;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_zerofp;
-- Textio functions
-- purpose: writes float into a line (NOTE changed basetype)
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable c : CHARACTER;
variable left : positive;
begin
while L /= null and L.all'length /= 0 loop
left := L.all'left;
c := L.all(left);
if (c = ' ' or c = NBSP or c = HT) then
read (L, c);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- purpose: Checks the punctuation in a line
procedure check_punctuation (
arg : in STRING;
colon : out BOOLEAN; -- There was a colon in the line
dot : out BOOLEAN; -- There was a dot in the line
good : out BOOLEAN; -- True if enough characters found
chars : in INTEGER) is
-- Examples. Legal inputs are "0000000", "0000.000", "0:000:000"
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable icolon, idot : BOOLEAN; -- internal
variable j : INTEGER := 0; -- charters read
begin
good := false;
icolon := false;
idot := false;
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then
exit;
elsif xarg(i) = ':' then
icolon := true;
elsif xarg(i) = '.' then
idot := true;
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
if j = chars then
good := true; -- There are enough charactes to read
end if;
colon := icolon;
if idot and icolon then
dot := false;
else
dot := idot;
end if;
end procedure check_punctuation;
-- purpose: Searches a line for a ":" and replaces it with a ".".
procedure fix_colon (
arg : inout STRING;
chars : in integer) is
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable j : INTEGER := 0; -- charters read
begin
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then
exit;
elsif xarg(i) = ':' then
xarg (i) := '.';
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
end procedure fix_colon;
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_float; -- floating point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'high - VALUE'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
WRITE (L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable readOk : BOOLEAN;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
READ (L, c, readOk);
if VALUE'length > 0 then
i := VALUE'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report float_generic_pkg'instance_name
& "READ(float): "
& "Error end of file encountered."
severity error;
return;
elsif c = ' ' or c = CR or c = HT then -- reading done.
if (i /= VALUE'low) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Warning: Value truncated."
severity warning;
return;
end if;
elsif c = '_' then
if i = VALUE'high then -- Begins with an "_"
report float_generic_pkg'instance_name
& "READ(float): "
& "String begins with an ""_""" severity error;
return;
elsif lastu then -- "__" detected
report float_generic_pkg'instance_name
& "READ(float): "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
if not (i = -1 or i = VALUE'high-1) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Warning: Separator point does not match number format: '"
& c & "' encountered at location " & INTEGER'image(i) & "."
severity warning;
end if;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < VALUE'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (L, c, readOk);
end loop readloop;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
READ (L, c, readOk);
if VALUE'length > 0 then
i := VALUE'high;
GOOD := false;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
return;
elsif c = ' ' or c = CR or c = HT then -- reading done
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
-- good := (i = -1 or i = value'high-1);
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < VALUE'low then
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (L, c, readOk);
end loop readloop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((VALUE'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/3)
& " valid octal characters."
severity error;
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (2 downto 1) /= "00" then
report float_generic_pkg'instance_name & "OREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_generic_pkg'instance_name & "OREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((VALUE'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (2 downto 1) /= "00" then
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure OREAD;
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((VALUE'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/4)
& " valid hex characters."
severity error;
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (3 downto 1) /= "000" then
report float_generic_pkg'instance_name & "HREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_generic_pkg'instance_name & "HREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((VALUE'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (3 downto 1) /= "000" then
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_float) return STRING is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(value(value'high)));
s(2) := ':';
sindx := 3;
for i in value'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto value'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end function to_string;
function to_hstring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_hstring (slv);
end function to_hstring;
function to_ostring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_ostring (slv);
end function to_ostring;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report float_generic_pkg'instance_name
& "from_string: Bad string " & bstring
severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report float_generic_pkg'instance_name
& "from_ostring: Bad string " & ostring
severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report float_generic_pkg'instance_name
& "from_hstring: Bad string " & hstring
severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_string (bstring => bstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_ostring (ostring => ostring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_hstring (hstring => hstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_hstring;
end package body float_generic_pkg;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze Generic AddressDecoder Unit
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
use PoC.vectors.all;
use PoC.io.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity PicoBlaze_AddressDecoder is
generic (
DEVICE_NAME : STRING;
BUS_NAME : STRING;
READ_MAPPINGS : T_PB_PORTNUMBER_MAPPING_VECTOR;
WRITE_MAPPINGS : T_PB_PORTNUMBER_MAPPING_VECTOR;
WRITEK_MAPPINGS : T_PB_PORTNUMBER_MAPPING_VECTOR
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
In_WriteStrobe : in STD_LOGIC;
In_WriteStrobe_K : in STD_LOGIC;
In_ReadStrobe : in STD_LOGIC;
In_Address : in T_SLV_8;
In_Data : in T_SLV_8;
Out_WriteStrobe : out STD_LOGIC;
Out_ReadStrobe : out STD_LOGIC;
Out_WriteAddress : out T_SLV_8;
Out_ReadAddress : out T_SLV_8;
Out_Data : out T_SLV_8
);
end entity;
architecture rtl of PicoBlaze_AddressDecoder is
attribute KEEP : BOOLEAN;
signal WriteAddress : T_SLV_8;
signal WriteAddress_K : T_SLV_8;
signal ReadAddress : T_SLV_8;
signal WriteHit : STD_LOGIC;
signal WriteHit_K : STD_LOGIC;
signal ReadHit : STD_LOGIC;
signal Out_WriteStrobe_i : STD_LOGIC := '0';
signal Out_ReadStrobe_i : STD_LOGIC;
signal Out_WriteAddress_i : T_SLV_8 := (others => '0');
signal Out_ReadAddress_i : T_SLV_8;
signal Out_Data_i : T_SLV_8 := (others => '0');
begin
process(In_Address, In_WriteStrobe, In_WriteStrobe_K, In_ReadStrobe)
begin
WriteAddress <= (others => '0');
WriteAddress_K <= (others => '0');
ReadAddress <= (others => '0');
WriteHit <= '0';
WriteHit_K <= '0';
ReadHit <= '0';
assert PB_VERBOSE
report "PicoBlaze_AddressDecoder: Report PortNumber mappings for device " & str_trim(DEVICE_NAME) &
" on bus " & str_trim(BUS_NAME)
severity NOTE;
for i in WRITEK_MAPPINGS'range loop
assert PB_VERBOSE
report " Map PortNumber " & INTEGER'image(WRITEK_MAPPINGS(i).PortNumber) &
" to register number " & INTEGER'image(WRITEK_MAPPINGS(i).RegNumber) &
" as K-writeable"
severity NOTE;
if (In_Address(3 downto 0) = to_slv(WRITEK_MAPPINGS(i).PortNumber, 4)) then
WriteAddress_K <= to_slv(WRITEK_MAPPINGS(i).RegNumber, WriteAddress_K'length);
WriteHit_K <= In_WriteStrobe_K;
end if;
end loop;
for i in WRITE_MAPPINGS'range loop
assert PB_VERBOSE
report " Map PortNumber " & INTEGER'image(WRITE_MAPPINGS(i).PortNumber) &
" to register number " & INTEGER'image(WRITE_MAPPINGS(i).RegNumber) &
" as writeable"
severity NOTE;
if (In_Address = to_slv(WRITE_MAPPINGS(i).PortNumber, In_Address'length)) then
WriteAddress <= to_slv(WRITE_MAPPINGS(i).RegNumber, WriteAddress'length);
WriteHit <= In_WriteStrobe;
end if;
end loop;
for i in READ_MAPPINGS'range loop
assert PB_VERBOSE
report " Map PortNumber " & INTEGER'image(READ_MAPPINGS(i).PortNumber) &
" to register number " & INTEGER'image(READ_MAPPINGS(i).RegNumber) &
" as readable"
severity NOTE;
if (In_Address = to_slv(READ_MAPPINGS(i).PortNumber, In_Address'length)) then
ReadAddress <= to_slv(READ_MAPPINGS(i).RegNumber, ReadAddress'length);
ReadHit <= In_ReadStrobe;
end if;
end loop;
end process;
process(Clock, ReadHit, ReadAddress)
begin
if rising_edge(Clock) then
if (WriteHit_K = '1') then
Out_WriteStrobe_i <= WriteHit_K;
Out_WriteAddress_i <= WriteAddress_K;
else
Out_WriteStrobe_i <= WriteHit;
Out_WriteAddress_i <= WriteAddress;
end if;
Out_Data_i <= In_Data;
end if;
Out_ReadStrobe_i <= ReadHit;
Out_ReadAddress_i <= ReadAddress;
end process;
Out_WriteStrobe <= Out_WriteStrobe_i;
Out_ReadStrobe <= Out_ReadStrobe_i;
Out_WriteAddress <= Out_WriteAddress_i;
Out_ReadAddress <= Out_ReadAddress_i;
Out_Data <= Out_Data_i;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Altera Cyclone-III Embedded Evaluation Kit LEON3 Demonstration design test
-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
-- Adapted for EEK by Jan Andersson, Gaisler Research
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal ssram_cen : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adsp_n : std_ulogic;
signal ssram_adv_n : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clkin : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
-- Connections over HSMC connector
-- LCD touch panel display
signal hc_vd : std_logic;
signal hc_hd : std_logic;
signal hc_den : std_logic;
signal hc_nclk : std_logic;
signal hc_lcd_data : std_logic_vector(7 downto 0);
signal hc_grest : std_logic;
signal hc_scen : std_logic;
signal hc_sda : std_logic;
signal hc_adc_penirq_n : std_logic;
signal hc_adc_dout : std_logic;
signal hc_adc_busy : std_logic;
signal hc_adc_din : std_logic;
signal hc_adc_dclk : std_logic;
signal hc_adc_cs_n : std_logic;
-- Shared by video decoder and audio codec
signal hc_i2c_sclk : std_logic;
signal hc_i2c_sdat : std_logic;
-- Video decoder
signal hc_td_d : std_logic_vector(7 downto 0);
signal hc_td_hs : std_logic;
signal hc_td_vs : std_logic;
signal hc_td_27mhz : std_logic;
signal hc_td_reset : std_logic;
-- Audio codec
signal hc_aud_adclrck : std_logic;
signal hc_aud_adcdat : std_logic;
signal hc_aud_daclrck : std_logic;
signal hc_aud_dacdat : std_logic;
signal hc_aud_bclk : std_logic;
signal hc_aud_xck : std_logic;
-- SD card
signal hc_sd_dat : std_logic;
signal hc_sd_dat3 : std_logic;
signal hc_sd_cmd : std_logic;
signal hc_sd_clk : std_logic;
-- Ethernet PHY
signal hc_tx_d : std_logic_vector(3 downto 0);
signal hc_rx_d : std_logic_vector(3 downto 0);
signal hc_tx_clk : std_logic;
signal hc_rx_clk : std_logic;
signal hc_tx_en : std_logic;
signal hc_rx_dv : std_logic;
signal hc_rx_crs : std_logic;
signal hc_rx_err : std_logic;
signal hc_rx_col : std_logic;
signal hc_mdio : std_logic;
signal hc_mdc : std_logic;
signal hc_eth_reset_n : std_logic;
-- RX232 (console/debug UART)
signal hc_uart_rxd : std_logic;
signal hc_uart_txd : std_logic;
-- PS/2
signal hc_ps2_dat : std_logic;
signal hc_ps2_clk : std_logic;
-- VGA/DAC
signal hc_vga_data : std_logic_vector(9 downto 0);
signal hc_vga_clock : std_ulogic;
signal hc_vga_hs : std_ulogic;
signal hc_vga_vs : std_ulogic;
signal hc_vga_blank : std_ulogic;
signal hc_vga_sync : std_ulogic;
-- I2C EEPROM
signal hc_id_i2cscl : std_logic;
signal hc_id_i2cdat : std_logic;
-- Ethernet PHY sim model
signal phy_tx_er : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal hc_tx_dt : std_logic_vector(7 downto 0) := (others => '0');
signal hc_rx_dt : std_logic_vector(7 downto 0) := (others => '0');
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; hc_uart_rxd <= '1';
address(0) <= '0';
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error,
address(25 downto 1), data, romsn, oen, writen, open,
ssram_cen, ssram_wen, ssram_bw, ssram_oen,
ssram_clk, ssram_adscn, iosn,
-- DDR
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
-- DSU
dsubren, dsuact,
-- I/O port
gpio,
-- LCD
hc_vd, hc_hd, hc_den, hc_nclk, hc_lcd_data, hc_grest, hc_scen,
hc_sda, hc_adc_penirq_n, hc_adc_dout, hc_adc_busy, hc_adc_din,
hc_adc_dclk, hc_adc_cs_n,
-- Shared by video decoder and audio codec
hc_i2c_sclk, hc_i2c_sdat,
-- Video decoder
hc_td_d, hc_td_hs, hc_td_vs, hc_td_27mhz, hc_td_reset,
-- Audio codec
hc_aud_adclrck, hc_aud_adcdat, hc_aud_daclrck, hc_aud_dacdat,
hc_aud_bclk, hc_aud_xck,
-- SD card
hc_sd_dat, hc_sd_dat3, hc_sd_cmd, hc_sd_clk,
-- Ethernet PHY
hc_tx_d, hc_rx_d, hc_tx_clk, hc_rx_clk, hc_tx_en, hc_rx_dv, hc_rx_crs,
hc_rx_err, hc_rx_col, hc_mdio, hc_mdc, hc_eth_reset_n,
-- RX232 (console/debug UART)
hc_uart_rxd, hc_uart_txd,
-- PS/2
hc_ps2_dat, hc_ps2_clk,
-- VGA/DAC
hc_vga_data, hc_vga_clock, hc_vga_hs, hc_vga_vs, hc_vga_blank, hc_vga_sync,
-- I2C EEPROM
hc_id_i2cscl, hc_id_i2cdat
);
-- I2C bus pull-ups
hc_i2c_sclk <= 'H'; hc_i2c_sdat <= 'H';
hc_id_i2cscl <= 'H'; hc_id_i2cdat <= 'H';
-- SD card signals
spiflashmod : spi_flash
generic map (ftype => 3, debug => 0, dummybyte => 0)
port map (sck => hc_sd_clk, di => hc_sd_cmd, do => hc_sd_dat, csn => hc_sd_dat3);
hc_sd_dat <= 'Z'; hc_sd_cmd <= 'Z';
-- hc_sd_dat <= hc_sd_cmd; -- Loopback
-- ddr0 : mt46v16m16
-- generic map (index => -1, fname => sdramfile)
-- port map(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 1)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
datazz <= "HHHH";
ssram_adsp_n <= '1'; ssram_adv_n <= '1';
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => data,
iAddr => address(20 downto 2), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
inADSP => ssram_adsp_n, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_cen,
iCE2 => vcc, inCE3 => gnd, iZz => gnd);
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31 downto 16),
gnd, gnd, romsn, writen, oen);
-- Ethernet PHY
hc_mdio <= 'H';
phy_tx_er <= '0';
phy_gtx_clk <= '0';
hc_tx_dt(3 downto 0) <= hc_tx_d;
hc_rx_d <= hc_rx_dt(3 downto 0);
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(hc_eth_reset_n, hc_mdio, hc_tx_clk, hc_rx_clk, hc_rx_dt, hc_rx_dv,
hc_rx_err, hc_rx_col, hc_rx_crs, hc_tx_dt, hc_tx_en, phy_tx_er, hc_mdc, phy_gtx_clk);
-- I2C memory
i0: i2c_slave_model
port map (hc_id_i2cscl, hc_id_i2cdat);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider_Demo is
port( LEDR : out std_logic_vector(0 downto 0);
CLOCK_50 : in std_logic;
SW : in std_logic_vector(1 downto 0);
HEX7 : out std_logic_vector(6 downto 0));
end FreqDivider_Demo;
architecture Structural of FreqDivider_Demo is
signal s_count : std_logic_vector(3 downto 0);
signal s_clk_out:std_logic;
begin
--FreqDivider: entity work.FreqDivider(Behavioral)
-- generic map(K => 25000000)
-- port map(clkIn => CLOCK_50,
-- clkOut=> LEDR(0));
FreqDivider: entity work.FreqDivider(Behavioral)
generic map(K => 50000000)
port map(clkIn => CLOCK_50,
clkOut => s_clk_out);
UpDown4: entity work.CounterUpDown4(Behavioral)
port map(clk => s_clk_out,
updown => SW(0),
reset => SW(1),
count => s_count);
Bin7SegDec: entity work.Bin7SegDecoder(Behavioral)
port map(enable => '1',
decOut_n => HEX7(6 downto 0),
binInput => s_count);
end Structural; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1281.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01281ent IS
END c08s04b00x00p04n01i01281ent;
ARCHITECTURE c08s04b00x00p04n01i01281arch OF c08s04b00x00p04n01i01281ent IS
signal S1 : integer ;
BEGIN
Function FUN_1 return BOOLEAN is
begin
return FALSE;
end FUN_1;
TESTING: PROCESS
BEGIN
FUN_1 <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01281 - Function calls are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01281arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1281.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01281ent IS
END c08s04b00x00p04n01i01281ent;
ARCHITECTURE c08s04b00x00p04n01i01281arch OF c08s04b00x00p04n01i01281ent IS
signal S1 : integer ;
BEGIN
Function FUN_1 return BOOLEAN is
begin
return FALSE;
end FUN_1;
TESTING: PROCESS
BEGIN
FUN_1 <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01281 - Function calls are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01281arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1281.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01281ent IS
END c08s04b00x00p04n01i01281ent;
ARCHITECTURE c08s04b00x00p04n01i01281arch OF c08s04b00x00p04n01i01281ent IS
signal S1 : integer ;
BEGIN
Function FUN_1 return BOOLEAN is
begin
return FALSE;
end FUN_1;
TESTING: PROCESS
BEGIN
FUN_1 <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01281 - Function calls are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01281arch;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: BuzzerDo.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY BuzzerDo IS
PORT
(
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END BuzzerDo;
ARCHITECTURE SYN OF buzzerdo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(29 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 94697,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 30
)
PORT MAP (
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "94697"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "30"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "94697"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
entity repro1 is
generic (WIDTH : natural := 4);
end;
architecture behav of repro1 is
type myarr is array(natural range <>) of bit_vector(WIDTH-1 downto 0);
type myrec is record
a: bit_vector(WIDTH-1 downto 0);
end record;
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc461.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00461ent IS
END c03s02b01x01p19n01i00461ent;
ARCHITECTURE c03s02b01x01p19n01i00461arch OF c03s02b01x01p19n01i00461ent IS
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
constant C66 : current := 1 A;
function complex_scalar(s : current) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return current is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : current;
signal S2 : current;
signal S3 : current:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00461"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00461 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00461arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc461.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00461ent IS
END c03s02b01x01p19n01i00461ent;
ARCHITECTURE c03s02b01x01p19n01i00461arch OF c03s02b01x01p19n01i00461ent IS
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
constant C66 : current := 1 A;
function complex_scalar(s : current) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return current is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : current;
signal S2 : current;
signal S3 : current:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00461"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00461 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00461arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc461.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00461ent IS
END c03s02b01x01p19n01i00461ent;
ARCHITECTURE c03s02b01x01p19n01i00461arch OF c03s02b01x01p19n01i00461ent IS
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
constant C66 : current := 1 A;
function complex_scalar(s : current) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return current is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : current;
signal S2 : current;
signal S3 : current:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00461"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00461 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00461arch;
|
architecture rtl of fifo is
begin
process begin
while condition loop end loop;
WHILE condition loop end loop;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_221 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_221;
architecture augh of sub_221 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
gt <= not(tmp_le);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_221 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_221;
architecture augh of sub_221 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
gt <= not(tmp_le);
end architecture;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Every HW component class has to be derived from :class:`hwt.synthesizer.unit.Unit` class
--
-- .. hwt-autodoc::
--
ENTITY Showcase0 IS
PORT(
a : IN UNSIGNED(31 DOWNTO 0);
b : IN SIGNED(31 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clk : IN STD_LOGIC;
cmp_0 : OUT STD_LOGIC;
cmp_1 : OUT STD_LOGIC;
cmp_2 : OUT STD_LOGIC;
cmp_3 : OUT STD_LOGIC;
cmp_4 : OUT STD_LOGIC;
cmp_5 : OUT STD_LOGIC;
contOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
e : IN STD_LOGIC;
f : OUT STD_LOGIC;
fitted : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
g : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
h : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
j : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
k : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_0 : OUT STD_LOGIC;
output : OUT STD_LOGIC;
rst_n : IN STD_LOGIC;
sc_signal : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF Showcase0 IS
TYPE arr_t_0 IS ARRAY (3 DOWNTO 0) OF SIGNED(7 DOWNTO 0);
TYPE arr_t_1 IS ARRAY (3 DOWNTO 0) OF UNSIGNED(7 DOWNTO 0);
CONSTANT const_private_signal : UNSIGNED(31 DOWNTO 0) := UNSIGNED'(X"0000007B");
SIGNAL fallingEdgeRam : arr_t_0;
SIGNAL r : STD_LOGIC := '0';
SIGNAL r_0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
SIGNAL r_1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
SIGNAL r_next : STD_LOGIC;
SIGNAL r_next_0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL r_next_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
CONSTANT rom : arr_t_1 := (
UNSIGNED'(X"00"),
UNSIGNED'(X"01"),
UNSIGNED'(X"02"),
UNSIGNED'(X"03"));
BEGIN
assig_process_c: PROCESS(a, b)
VARIABLE tmpCastExpr_0 : UNSIGNED(31 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a + UNSIGNED(b);
c <= STD_LOGIC_VECTOR(tmpCastExpr_0);
END PROCESS;
cmp_0 <= '1' WHEN (a < UNSIGNED'(X"00000004")) ELSE '0';
cmp_1 <= '1' WHEN (a > UNSIGNED'(X"00000004")) ELSE '0';
cmp_2 <= '1' WHEN (b <= SIGNED'(X"00000004")) ELSE '0';
cmp_3 <= '1' WHEN (b >= SIGNED'(X"00000004")) ELSE '0';
cmp_4 <= '1' WHEN (b /= SIGNED'(X"00000004")) ELSE '0';
cmp_5 <= '1' WHEN (b = SIGNED'(X"00000004")) ELSE '0';
contOut <= STD_LOGIC_VECTOR(const_private_signal);
f <= r;
assig_process_fallingEdgeRam: PROCESS(clk)
VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
VARIABLE tmpCastExpr_2 : SIGNED(7 DOWNTO 0);
VARIABLE tmpCastExpr_1 : UNSIGNED(7 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a(7 DOWNTO 0);
tmpCastExpr_2 := fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1)));
tmpCastExpr_1 := UNSIGNED(tmpCastExpr_2);
IF FALLING_EDGE(clk) THEN
fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1))) <= SIGNED(tmpCastExpr_0);
k <= X"000000" & STD_LOGIC_VECTOR(tmpCastExpr_1);
END IF;
END PROCESS;
assig_process_fitted: PROCESS(a)
VARIABLE tmpCastExpr_0 : UNSIGNED(15 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a(15 DOWNTO 0);
fitted <= STD_LOGIC_VECTOR(tmpCastExpr_0);
END PROCESS;
assig_process_g: PROCESS(a, b)
VARIABLE tmpCastExpr_0 : UNSIGNED(5 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a(5 DOWNTO 0);
g <= (a(1) AND b(1)) & ((a(0) XOR b(0)) OR a(1)) & STD_LOGIC_VECTOR(tmpCastExpr_0);
END PROCESS;
assig_process_h: PROCESS(a, r)
BEGIN
IF a(2) = '1' THEN
IF r = '1' THEN
h <= X"00";
ELSIF a(1) = '1' THEN
h <= X"01";
ELSE
h <= X"02";
END IF;
END IF;
END PROCESS;
assig_process_j: PROCESS(clk)
VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
BEGIN
tmpCastExpr_0 := rom(TO_INTEGER(UNSIGNED(r_1)));
IF RISING_EDGE(clk) THEN
j <= STD_LOGIC_VECTOR(tmpCastExpr_0);
END IF;
END PROCESS;
out_0 <= '0';
output <= 'X';
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r_1 <= "00";
r_0 <= "00";
r <= '0';
ELSE
r_1 <= r_next_1;
r_0 <= r_next_0;
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next_0 <= i;
r_next_1 <= r_0;
assig_process_r_next_1: PROCESS(e, r)
BEGIN
IF NOT r = '1' THEN
r_next <= e;
ELSE
r_next <= r;
END IF;
END PROCESS;
assig_process_sc_signal: PROCESS(a)
BEGIN
CASE a IS
WHEN UNSIGNED'(X"00000001") =>
sc_signal <= X"00";
WHEN UNSIGNED'(X"00000002") =>
sc_signal <= X"01";
WHEN UNSIGNED'(X"00000003") =>
sc_signal <= X"03";
WHEN OTHERS =>
sc_signal <= X"04";
END CASE;
END PROCESS;
END ARCHITECTURE;
|
library verilog;
use verilog.vl_types.all;
entity SlaveArbiter is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
mAddrSel : in vl_logic_vector(4 downto 0);
addrPhEnd : in vl_logic;
m1GatedHMASTLOCK: in vl_logic;
m2GatedHMASTLOCK: in vl_logic;
COM_WEIGHTEDMODE: in vl_logic;
masterAddrInProg: out vl_logic_vector(4 downto 0)
);
end SlaveArbiter;
|
library verilog;
use verilog.vl_types.all;
entity SlaveArbiter is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
mAddrSel : in vl_logic_vector(4 downto 0);
addrPhEnd : in vl_logic;
m1GatedHMASTLOCK: in vl_logic;
m2GatedHMASTLOCK: in vl_logic;
COM_WEIGHTEDMODE: in vl_logic;
masterAddrInProg: out vl_logic_vector(4 downto 0)
);
end SlaveArbiter;
|
library verilog;
use verilog.vl_types.all;
entity SlaveArbiter is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
mAddrSel : in vl_logic_vector(4 downto 0);
addrPhEnd : in vl_logic;
m1GatedHMASTLOCK: in vl_logic;
m2GatedHMASTLOCK: in vl_logic;
COM_WEIGHTEDMODE: in vl_logic;
masterAddrInProg: out vl_logic_vector(4 downto 0)
);
end SlaveArbiter;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00190
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00190
-- PKG00190/BODY
-- ENT00190(ARCH00190)
-- ENT00190_Test_Bench(ARCH00190_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00190 is
type r_st_rec1 is record
f1 : integer ;
f2 : st_rec1 ;
end record ;
function c_r_st_rec1_1 return r_st_rec1 ;
-- (c_integer_1, c_st_rec1_1) ;
function c_r_st_rec1_2 return r_st_rec1 ;
-- (c_integer_2, c_st_rec1_2) ;
--
type r_st_rec2 is record
f1 : integer ;
f2 : st_rec2 ;
end record ;
function c_r_st_rec2_1 return r_st_rec2 ;
-- (c_integer_1, c_st_rec2_1) ;
function c_r_st_rec2_2 return r_st_rec2 ;
-- (c_integer_2, c_st_rec2_2) ;
--
type r_st_rec3 is record
f1 : integer ;
f2 : st_rec3 ;
end record ;
function c_r_st_rec3_1 return r_st_rec3 ;
-- (c_integer_1, c_st_rec3_1) ;
function c_r_st_rec3_2 return r_st_rec3 ;
-- (c_integer_2, c_st_rec3_2) ;
--
--
end PKG00190 ;
--
package body PKG00190 is
function c_r_st_rec1_1 return r_st_rec1
is begin
return (c_integer_1, c_st_rec1_1) ;
end c_r_st_rec1_1 ;
--
function c_r_st_rec1_2 return r_st_rec1
is begin
return (c_integer_2, c_st_rec1_2) ;
end c_r_st_rec1_2 ;
--
--
function c_r_st_rec2_1 return r_st_rec2
is begin
return (c_integer_1, c_st_rec2_1) ;
end c_r_st_rec2_1 ;
--
function c_r_st_rec2_2 return r_st_rec2
is begin
return (c_integer_2, c_st_rec2_2) ;
end c_r_st_rec2_2 ;
--
--
function c_r_st_rec3_1 return r_st_rec3
is begin
return (c_integer_1, c_st_rec3_1) ;
end c_r_st_rec3_1 ;
--
function c_r_st_rec3_2 return r_st_rec3
is begin
return (c_integer_2, c_st_rec3_2) ;
end c_r_st_rec3_2 ;
--
--
--
end PKG00190 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00190.all ;
entity ENT00190 is
port (
s_r_st_rec1 : inout r_st_rec1
; s_r_st_rec2 : inout r_st_rec2
; s_r_st_rec3 : inout r_st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_rec1 : chk_sig_type := -1 ;
signal chk_r_st_rec2 : chk_sig_type := -1 ;
signal chk_r_st_rec3 : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_r_st_rec1 : inout r_st_rec1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns,
c_r_st_rec1_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00190.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00190" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_r_st_rec2 : inout r_st_rec2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns,
c_r_st_rec2_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00190.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00190" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_r_st_rec3 : inout r_st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns,
c_r_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00190.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00190" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00190" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00190 ;
--
architecture ARCH00190 of ENT00190 is
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_r_st_rec1,
counter,
correct,
savtime,
chk_r_st_rec1
) ;
wait until (not s_r_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_r_st_rec2,
counter,
correct,
savtime,
chk_r_st_rec2
) ;
wait until (not s_r_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_r_st_rec3,
counter,
correct,
savtime,
chk_r_st_rec3
) ;
wait until (not s_r_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00190 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00190.all ;
entity ENT00190_Test_Bench is
signal s_r_st_rec1 : r_st_rec1
:= c_r_st_rec1_1 ;
signal s_r_st_rec2 : r_st_rec2
:= c_r_st_rec2_1 ;
signal s_r_st_rec3 : r_st_rec3
:= c_r_st_rec3_1 ;
--
end ENT00190_Test_Bench ;
--
architecture ARCH00190_Test_Bench of ENT00190_Test_Bench is
begin
L1:
block
component UUT
port (
s_r_st_rec1 : inout r_st_rec1
; s_r_st_rec2 : inout r_st_rec2
; s_r_st_rec3 : inout r_st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00190 ( ARCH00190 ) ;
begin
CIS1 : UUT
port map (
s_r_st_rec1
, s_r_st_rec2
, s_r_st_rec3
) ;
end block L1 ;
end ARCH00190_Test_Bench ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: logan
-- File: logan.vhd
-- Author: Kristoffer Carlsson, Gaisler Research
-- Description: On-chip logic analyzer IP core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0; -- Use qualifer bit
usediv : integer range 0 to 1 := 1; -- Enable/disable div counter
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic; -- Synchronous reset
clk : in std_logic; -- System clock
tclk : in std_logic; -- Trace clock
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end logan;
architecture rtl of logan is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LOGAN, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant abits: integer := 8 + log2x(depth/256 - 1);
constant az : std_logic_vector(abits-1 downto 0) := (others => '0');
constant dz : std_logic_vector(dbits-1 downto 0) := (others => '0');
type trig_cfg_type is record
pattern : std_logic_vector(dbits-1 downto 0); -- Pattern to trig on
mask : std_logic_vector(dbits-1 downto 0); -- trigger mask
count : std_logic_vector(5 downto 0); -- match counter
eq : std_ulogic; -- Trig on match or no match?
end record;
type trig_cfg_arr is array (0 to trigl-1) of trig_cfg_type;
type reg_type is record
armed : std_ulogic;
trig_demet : std_ulogic;
trigged : std_ulogic;
fin_demet : std_ulogic;
finished : std_ulogic;
qualifier : std_logic_vector(7 downto 0);
qual_val : std_ulogic;
divcount : std_logic_vector(15 downto 0);
counter : std_logic_vector(abits-1 downto 0);
page : std_logic_vector(3 downto 0);
trig_conf : trig_cfg_arr;
end record;
type trace_reg_type is record
armed : std_ulogic;
arm_demet : std_ulogic;
trigged : std_ulogic;
finished : std_ulogic;
sample : std_ulogic;
divcounter : std_logic_vector(15 downto 0);
match_count : std_logic_vector(5 downto 0);
counter : std_logic_vector(abits-1 downto 0);
curr_tl : integer range 0 to trigl-1;
w_addr : std_logic_vector(abits-1 downto 0);
end record;
signal r_addr : std_logic_vector(13 downto 0);
signal bufout : std_logic_vector(255 downto 0);
signal r_en : std_ulogic;
signal r, rin : reg_type;
signal tr, trin : trace_reg_type;
signal sigreg : std_logic_vector(dbits-1 downto 0);
signal sigold : std_logic_vector(dbits-1 downto 0);
begin
bufout(255 downto dbits) <= (others => '0');
-- Combinatorial process for AMBA clock domain
comb1: process(rstn, apbi, r, tr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable tl : integer range 0 to trigl-1;
variable pattern, mask : std_logic_vector(255 downto 0);
begin
v := r;
rdata := (others => '0'); tl := 0;
pattern := (others => '0'); mask := (others => '0');
-- Two stage synch
v.trig_demet := tr.trigged;
v.trigged := r.trig_demet;
v.fin_demet := tr.finished;
v.finished := r.fin_demet;
if r.finished = '1' then
v.armed := '0';
end if;
r_en <= '0';
-- Read/Write --
if apbi.psel(pindex) = '1' then
-- Write
if apbi.pwrite = '1' and apbi.penable = '1' then
-- Only conf area writeable
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => pattern(31 downto 0) := apbi.pwdata;
when "0001" => pattern(63 downto 32) := apbi.pwdata;
when "0010" => pattern(95 downto 64) := apbi.pwdata;
when "0011" => pattern(127 downto 96) := apbi.pwdata;
when "0100" => pattern(159 downto 128) := apbi.pwdata;
when "0101" => pattern(191 downto 160) := apbi.pwdata;
when "0110" => pattern(223 downto 192) := apbi.pwdata;
when "0111" => pattern(255 downto 224) := apbi.pwdata;
when "1000" => mask(31 downto 0) := apbi.pwdata;
when "1001" => mask(63 downto 32) := apbi.pwdata;
when "1010" => mask(95 downto 64) := apbi.pwdata;
when "1011" => mask(127 downto 96) := apbi.pwdata;
when "1100" => mask(159 downto 128) := apbi.pwdata;
when "1101" => mask(191 downto 160) := apbi.pwdata;
when "1110" => mask(223 downto 192) := apbi.pwdata;
when "1111" => mask(255 downto 224) := apbi.pwdata;
when others => null;
end case;
-- write back updated pattern/mask
v.trig_conf(tl).pattern := pattern(dbits-1 downto 0);
v.trig_conf(tl).mask := mask(dbits-1 downto 0);
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
v.trig_conf(tl).count := apbi.pwdata(6 downto 1);
v.trig_conf(tl).eq := apbi.pwdata(0);
-- arm/reset
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
v.armed := apbi.pwdata(0);
-- Page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
v.page := apbi.pwdata(3 downto 0);
-- Trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
v.counter := apbi.pwdata(abits-1 downto 0);
-- div count
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
v.divcount := apbi.pwdata(15 downto 0);
-- qualifier bit
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
v.qualifier := apbi.pwdata(7 downto 0);
v.qual_val := apbi.pwdata(8);
end if;
end if;
-- end write
-- Read
else
-- Read config/status area
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => rdata := pattern(31 downto 0);
when "0001" => rdata := pattern(63 downto 32);
when "0010" => rdata := pattern(95 downto 64);
when "0011" => rdata := pattern(127 downto 96);
when "0100" => rdata := pattern(159 downto 128);
when "0101" => rdata := pattern(191 downto 160);
when "0110" => rdata := pattern(223 downto 192);
when "0111" => rdata := pattern(255 downto 224);
when "1000" => rdata := mask(31 downto 0);
when "1001" => rdata := mask(63 downto 32);
when "1010" => rdata := mask(95 downto 64);
when "1011" => rdata := mask(127 downto 96);
when "1100" => rdata := mask(159 downto 128);
when "1101" => rdata := mask(191 downto 160);
when "1110" => rdata := mask(223 downto 192);
when "1111" => rdata := mask(255 downto 224);
when others => rdata := (others => '0');
end case;
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
rdata(6 downto 1) := v.trig_conf(tl).count;
rdata(0) := v.trig_conf(tl).eq;
-- status
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
rdata := conv_std_logic_vector(usereg,1) & conv_std_logic_vector(usequal,1) &
r.armed & r.trigged &
conv_std_logic_vector(dbits,8)&
conv_std_logic_vector(depth-1,14)&
conv_std_logic_vector(trigl,6);
-- trace buffer index
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00001" then
rdata(abits-1 downto 0) := tr.w_addr(abits-1 downto 0);
-- page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
rdata(3 downto 0) := r.page;
-- trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
rdata(abits-1 downto 0) := r.counter;
-- divcount
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
rdata(15 downto 0) := r.divcount;
-- qualifier
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
rdata(7 downto 0) := r.qualifier;
rdata(8) := r.qual_val;
end if;
-- Read from trace buffer
else
-- address always r.page & apbi.paddr(14 downto 5)
r_en <= '1';
-- Select word from pattern
case apbi.paddr(4 downto 2) is
when "000" => rdata := bufout(31 downto 0);
when "001" => rdata := bufout(63 downto 32);
when "010" => rdata := bufout(95 downto 64);
when "011" => rdata := bufout(127 downto 96);
when "100" => rdata := bufout(159 downto 128);
when "101" => rdata := bufout(191 downto 160);
when "110" => rdata := bufout(223 downto 192);
when "111" => rdata := bufout(255 downto 224);
when others => rdata := (others => '0');
end case;
end if;
end if; -- end read
end if;
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.finished := '0'; v.trig_demet := '0'; v.fin_demet := '0';
v.counter := (others => '0');
v.divcount := X"0001";
v.qualifier := (others => '0');
v.qual_val := '0';
v.page := (others => '0');
end if;
apbo.prdata <= rdata;
rin <= v;
end process;
-- Combinatorial process for trace clock domain
comb2 : process (rstn, tr, r, sigreg)
variable v : trace_reg_type;
begin
v := tr;
v.sample := '0';
if tr.armed = '0' then
v.trigged := '0'; v.counter := (others => '0'); v.curr_tl := 0; v.match_count := (others => '0');
end if;
-- Synch arm signal
v.arm_demet := r.armed;
v.armed := tr.arm_demet;
if tr.finished = '1' then
v.finished := tr.armed;
end if;
-- Trigger --
if tr.armed = '1' and tr.finished = '0' then
if usediv = 1 then
if tr.divcounter = X"0000" then
v.divcounter := r.divcount-1;
if usequal = 0 or sigreg(conv_integer(r.qualifier)) = r.qual_val then
v.sample := '1';
end if;
else
v.divcounter := v.divcounter - 1;
end if;
else
v.sample := '1';
end if;
if tr.sample = '1' then v.w_addr := tr.w_addr + 1; end if;
if tr.trigged = '1' and tr.sample = '1' then
if tr.counter = r.counter then
v.trigged := '0';
v.sample := '0';
v.finished := '1';
v.counter := (others => '0');
else v.counter := tr.counter + 1; end if;
else
-- match?
if ((sigreg xor r.trig_conf(tr.curr_tl).pattern) and r.trig_conf(tr.curr_tl).mask) = dz then
-- trig on equal
if r.trig_conf(tr.curr_tl).eq = '1' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
else -- not a match
-- trig on inequal
if r.trig_conf(tr.curr_tl).eq = '0' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
end if;
end if;
end if;
-- end trigger
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.sample := '0'; v.finished := '0'; v.arm_demet := '0';
v.curr_tl := 0;
v.counter := (others => '0');
v.divcounter := (others => '0');
v.match_count := (others => '0');
v.w_addr := (others => '0');
end if;
trin <= v;
end process;
-- clk traced signals through register to minimize fan out
inreg: if usereg = 1 generate
process (tclk)
begin
if rising_edge(tclk) then
sigold <= sigreg;
sigreg <= signals;
end if;
end process;
end generate;
noinreg: if usereg = 0 generate
sigreg <= signals;
sigold <= signals;
end generate;
-- Update registers
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
treg: process(tclk)
begin
if rising_edge(tclk) then tr <= trin; end if;
end process;
r_addr <= r.page & apbi.paddr(14 downto 5);
trace_buf : syncram_2p
generic map (tech => memtech, abits => abits, dbits => dbits)
port map (clk, r_en, r_addr(abits-1 downto 0), bufout(dbits-1 downto 0), -- read
tclk, tr.sample, tr.w_addr, sigold); -- write
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3128.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x02p12n01i03128ent_a IS
generic ( g1 : integer := 3 );
END c05s02b01x02p12n01i03128ent_a;
ARCHITECTURE c05s02b01x02p12n01i03128arch_a OF c05s02b01x02p12n01i03128ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert g1 /= 2 report "g1 = 2" severity FAILURE;
assert g1 /= 3 report "g1 = 3" severity FAILURE;
assert g1 = 4 report "g1 /= 4" severity FAILURE;
assert g1 /= 5 report "g1 = 5" severity FAILURE;
assert g1 /= 6 report "g1 = 6" severity FAILURE;
assert NOT( g1 /= 2 and
g1 /= 3 and
g1 = 4 and
g1 /= 5 and
g1 /= 6 )
report "***PASSED TEST: c05s02b01x02p12n01i03128"
severity NOTE;
assert ( g1 /= 2 and
g1 /= 3 and
g1 = 4 and
g1 /= 5 and
g1 /= 6 )
report "***FAILED TEST: c05s02b01x02p12n01i03128 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x02p12n01i03128arch_a;
ENTITY c05s02b01x02p12n01i03128ent IS
END c05s02b01x02p12n01i03128ent;
ARCHITECTURE c05s02b01x02p12n01i03128arch OF c05s02b01x02p12n01i03128ent IS
BEGIN
labeled : block
component ic_socket
generic ( g1 : integer := 2 );
end component;
for instance : ic_socket use entity work.c05s02b01x02p12n01i03128ent_a (c05s02b01x02p12n01i03128arch_a)
generic map ( g1 => g1 + g1 );
begin
instance : ic_socket ;
end block;
END c05s02b01x02p12n01i03128arch;
configuration vests28 of c05s02b01x02p12n01i03128ent is
for c05s02b01x02p12n01i03128arch
end for;
end vests28;
|
--------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Feb 19, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.types.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity upc is
port (
clk : in clock;
CI : in MVL7;
clear : in MVL7;
Y_temp : in MVL7_VECTOR(11 downto 0);
uPC : inout MVL7_VECTOR(11 downto 0)
);
end upc;
architecture upc of upc is
begin
-------------------------------------------------------------------------------
PC : block ( (clk = '1') and (not clk'stable) )
begin
uPC <= guarded Y_temp + ("00000000000" & CI) WHEN (clear = '0') ELSE
"000000000000" WHEN clear = '1' ELSE
uPC;
end block PC;
------------------------------------------------------------------------------
end upc;
|
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